Semiconductor storage device and data writing method of semiconductor storage device

Abstract

To provide a semiconductor storage device that reduces time required for consecutive data rewrite to a plurality of addresses.SOLUTION: A semiconductor storage device 100 comprises a command register and an address buffer. The command register includes a mode setting part having a first write mode for, when a second address other than a first address of a plurality of consecutive addresses in a memory is designated after data write into the first address, writing data into the second address, and a second write mode for writing data into the first address through the second address consecutively. The address buffer includes a frequency setting part of setting data write frequency since start of data write into a start address till completion of data write into a completion address. When the second write mode is selected, the command register writes data at the frequency set in the frequency setting part into one or more addresses consecutive from the start address.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor memory device and a method for writing data to a semiconductor memory device. [Background technology]

[0002] The controller of the memory device disclosed in Patent Document 1 receives write data to be written to the semiconductor memory, and when it receives a write start command, it transitions to a sequential write mode, i.e., a continuous write mode. In this type of conventional technology, when rewriting data to a rewritable flash memory, data is often rewritten to multiple consecutive addresses. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2011-175615 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the conventional technology, even when rewriting data to multiple consecutive addresses, the time required to complete rewriting data to multiple specified addresses may increase because the addresses must be set each time data writing to each address is completed. Thus, the conventional technology has room for improvement in rewriting data to multiple consecutive addresses.

[0005] In consideration of the above circumstances, an object of the present disclosure is to provide a semiconductor memory device and a data writing method for a semiconductor memory device that can reduce the time required to rewrite data to a plurality of consecutive addresses. [Means for solving the problem]

[0006] In order to solve the above problems, a semiconductor memory device according to the present disclosure includes a command register that holds data input from outside and controls writing of data to a rewritable memory, and an address buffer that holds an address that is specified from outside among addresses of the memory, wherein the command register has a mode setting unit that includes a first write mode in which, when a second address other than the first address is specified after writing of data to a first address among a plurality of consecutive addresses in the memory is completed, data is written to the second address, and a second write mode in which data is written consecutively from the first address to the second address among the plurality of addresses, wherein, when the first address is set as a start address for starting writing of data and the second address is set as a completion address for completing writing of data, the address buffer has a number setting unit that sets the number of data writes from starting writing of data to the start address to completing writing of data to the completion address, and when the command register selects the second write mode, data is written to the start address and one or more addresses consecutive to the start address, corresponding to the number of times set in the number setting unit.

[0007] A data writing method for a semiconductor memory device according to the present disclosure is a data writing method for a semiconductor memory device including a command register that holds data input from outside and controls writing of data to a rewritable memory, and an address buffer that holds an address specified from outside among addresses of the memory, the method including the steps of: selecting, by the command register, either a first write mode in which data is written to a second address when a second address other than the first address is specified after completion of writing data to a first address among a plurality of consecutive addresses in the memory; or a second write mode in which data is written consecutively from the first address to the second address among the plurality of addresses; setting, by the address buffer, when the first address is set as a start address for starting writing of data and the second address is set as a completion address for completing writing of data, a number of data writes from starting writing of data to the start address to completing writing of data to the completion address; and, when the command register selects the second write mode, writing data corresponding to the number of writes to each of the start address and one or more addresses consecutive to the start address. Effect of the Invention

[0008] The present disclosure has an effect of providing a semiconductor memory device and a data writing method for a semiconductor memory device that can reduce the time required to rewrite data to a plurality of consecutive addresses. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram showing a configuration of a semiconductor memory device according to an embodiment of the present disclosure. [Diagram 2] FIG. 2 is a diagram showing functional blocks of the command register. [Diagram 3] FIG. 3 is a diagram showing functional blocks of the address buffer. [Figure 4]FIG. 4 is a timing chart for explaining an example of operation when the normal write mode is set. [Diagram 5] FIG. 5 is a timing chart for explaining an example of operation when the successive write mode is set. [Figure 6] FIG. 6 is a flowchart illustrating the data writing method for the semiconductor memory device of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, an embodiment will be described with reference to the drawings. Note that the same or similar reference numerals are used to designate the same functions or configurations, and the description thereof will be omitted as appropriate.

[0011] (Embodiment) 1 is a diagram showing a configuration of a semiconductor memory device according to an embodiment of the present disclosure. The semiconductor memory device 100 may include a command register 10, an address buffer 20, a data input buffer 30, and a flash memory 40.

[0012] (Command register 10) A write clock signal WEB and a data input signal DIN are input to the command register 10. The write clock signal WEB may be interpreted as a write clock signal. The data input signal DIN may include a command for setting a mode, data to be written to an address, etc. The command for setting a mode may be interpreted as setting an operation mode. The operation mode may include a normal write mode and a continuous write mode. The normal write mode may be interpreted as a first write mode. The continuous write mode may be interpreted as a second write mode. The first write mode or the second write mode may be interpreted as a mode for writing data to the flash memory 40. Details of these modes will be described later.

[0013] The command register 10 may hold data input from the outside and control writing of the data to a rewritable memory. The outside may be interpreted as an external control circuit 200. The memory may be interpreted as a flash memory 40.

[0014] The command register 10 may include a first mode circuit 11 for setting a normal write mode, that is, a first write mode, and a second mode circuit 12 for setting a successive write mode, that is, a second write mode.

[0015] The first mode circuit 11 may set a normal write mode based on the write clock signal WEB and the data input signal DIN. The second mode circuit 12 may set a continuous write mode based on the write clock signal WEB and the data input signal DIN.

[0016] The command register 10 may transmit a write signal BUSY to the external control circuit 200. Specifically, during a write operation to the flash memory 40, the command register 10 may transmit a signal indicating that data is being written as a write signal BUSY to the external control circuit 200.

[0017] (Address Buffer 20) A write clock signal WEB and an address input signal AIN are input to the address buffer 20. The address buffer 20 may hold an address designated from outside among the addresses held by the flash memory 40, using the write clock signal WEB and the address input signal AIN. Specifically, the address buffer 20 may include an address latch that latches an address input from outside, and the address latch may store a write start address input from outside and addresses other than the start address.

[0018] The address buffer 20 may select a WL (word line) and a BL (bit line) according to a write clock signal WEB and an address input signal AIN.

[0019] The address buffer 20 may include a repeat register 21 for setting the number of repetitions of data rewrite in the address buffer 20. The number of repetitions of data rewrite may be interpreted as a repeat number R or a repeat count R (R is a natural number equal to or greater than 1). The repeat register 21 may be interpreted as a count setting unit. The repeat register 21 and the count setting unit will be described in detail later.

[0020] A write clock signal WEB and a data input signal DIN are input to the data input buffer 30. The data input buffer 30 may temporarily store data to be written to the flash memory 40 and set the write data using the write clock signal WEB and the data input signal DIN.

[0021] 2 and 3, the functions of the command register 10 and the address buffer 20 will be described. Fig. 2 is a diagram showing functional blocks of the command register. The command register 10 may include an external input section 10a, a mode setting section 10b, and a data writing section 10c.

[0022] (External input unit 10a) The external input section 10a may input a write clock pulse WEB and a data input signal DIN.

[0023] (Mode setting section 10b) The mode setting section 10b may set a first write mode, which is a normal write mode, or a second write mode, which is a successive write mode, according to the data input signal DIN.

[0024] Specifically, when the level of the write clock pulse WEB falls from H to L, the mode setting unit 10b may set the first write mode or the second write mode as the operation mode of the command register 10 in accordance with the command included in the input data input signal DIN. The mode setting unit 10b may set the first write mode, which is the normal write mode, as the operation mode by controlling the first mode circuit 11 shown in Fig. 1. The mode setting unit 10b may set the second write mode, which is the continuous write mode, as the operation mode by controlling the second mode circuit 12 shown in Fig. 1.

[0025] (First write mode) The first write mode may be interpreted as a mode in which data is intermittently written to a plurality of addresses. Specifically, the first write mode may be interpreted as a mode in which, after data has been written to a first address, which is a specific address among a plurality of consecutive addresses A1 to An (n is a natural number equal to or greater than 1) in the flash memory 40, when a second address other than the first address is designated, data is written to the second address.

[0026] The first address may be interpreted as a specific address among the multiple addresses A1 to An, and the second address may be interpreted as an address subsequent to the first address among the multiple addresses A1 to An.

[0027] For example, if the first address among multiple addresses A1 to An is address A1, the second address may be interpreted as any one of addresses A2 to An. If the first address is address An-2, the second address may be interpreted as any one of addresses An-1 and An.

[0028] (Second write mode) The second write mode may be interpreted as a mode in which data is written continuously from the first address to the second address a number of times corresponding to the repeat count R, using a specific first address as a write start address among a plurality of consecutive addresses A1 to An (n is a natural number equal to or greater than 1) in the flash memory 40. The second write mode may be interpreted as a mode in which data is written continuously to a plurality of addresses.

[0029] For example, among a plurality of addresses A1 to An, if the first address is address A1 and the repeat count R is 4, the second address may be interpreted as address A4. In this case, writing is performed continuously from addresses A1 to A4.

[0030] (Data writing unit 10c) The data writing unit 10c may control writing of data to the flash memory 40. Specifically, when the mode setting unit 10b sets or selects the first write mode, the data writing unit 10c writes data to a first address among the multiple addresses A1 to An when the first address is set. After the data writing is completed, the data writing unit 10c may write data to a second address other than the first address when the second address is set.

[0031] When the mode setting unit 10b sets or selects the second write mode, the data writing unit 10c may continuously write data to the start address and one or more addresses subsequent to the start address, the number of times corresponding to the number of times set in the number setting unit. The details of the number setting unit will be described later.

[0032] When the mode setting section 10b sets or selects the second write mode, the data writing section 10c may transmit to the address buffer 20 address information indicating a start address and one or more addresses subsequent to the start address.

[0033] 3 is a diagram showing functional blocks of the address buffer 20. The address buffer 20 may include a count setting unit 20a, an address selection unit 20b, and a count management unit 20c.

[0034] (Number of times setting unit 20a) The number setting unit 20a may set the number of times data is written from the start of writing data to the start address to the completion address. The start address may be interpreted as a first address at which data writing starts. The completion address may be interpreted as a second address at which data writing is completed. For example, among multiple addresses A1 to An, if the start address (first address) is address A1 and the repeat count R is 4, the completion address (second address) may be interpreted as address A4. In this case, writing is performed continuously from addresses A1 to A4.

[0035] (Address selection unit 20b) The address selection unit 20b may select a bit line and a word line corresponding to the start address, or may select a bit line and a word line corresponding to one or more addresses subsequent to the start address.

[0036] (Number of times management unit 20c) The number management unit 20c may increment the number of writes set in the number setting unit 20a every time data is written to an address corresponding to the bit line and word line selected by the address selection unit 20b. Specifically, the number management unit 20c may increment the number of writes every time data is written to each address from when the command register 10 starts writing data to multiple addresses in the flash memory 40 until the data writing is completed.

[0037] (Operation of Semiconductor Memory Device 100) Next, the operation of the semiconductor memory device 100 will be described with reference to Figures 4 and 5. First, the operation when the normal write mode is set will be described with reference to Figure 4, and then the operation when the continuous write mode is set will be described with reference to Figure 5.

[0038] (Normal write mode) 4 is a timing chart for explaining an example of operation when the normal write mode is set. The internal write signal INTW shown in FIG.

[0039] In FIG. 4, data writing in the first cycle is executed with the first CLK (clock) of the write clock pulse WEB as a trigger, that is, when the first CLK after the write clock pulse WEB falls is detected.

[0040] Specifically, when the first CLK of the write clock pulse WEB is detected, if the command included in the data input signal DIN is a command indicating the setting of the normal write mode, the semiconductor memory device 100 transitions to the normal write mode. The command indicating the setting of the normal write mode may be, for example, "#0000A0".

[0041] After that, when the second CLK of the write clock pulse WEB is detected, the write address A(a) and write data D(a) are set, and the write operation is started while the data is internally held by each latch circuit. Specifically, the semiconductor memory device 100 takes in the data included in the data input signal DIN and the address included in the address input signal AIN, and transitions to a write state in the flash memory 40. At this time, when the second CLK of the write clock pulse WEB is detected, the internal write signal INTW transitions from a non-write state "L" to a write state "H" to become a write enable signal. The write monitor signal BUSY is approximately linked to the internal write signal INTW, and the semiconductor memory device 100 switches the level of the write monitor signal BUSY from L to H.

[0042] This starts writing data to a specific address. After a specific write time (several tens of us) set in the semiconductor memory device 100 has elapsed, the internal write signal INTW transitions from the write state "H" to the non-write state "L," switching the level of the write monitor signal BUSY from H to L. This ends the first cycle of data writing.

[0043] When the external control circuit 200 detects that the level of the write monitor signal BUSY has switched from H to L, it determines that the first cycle of data writing has ended.

[0044] The external control circuit 200 performs mode setting (for example, first mode setting) again when a specific time (monitor processing time) has elapsed since the data write was completed, and sets the address A(b) and data D(b) of the data to be written in the second cycle. In the semiconductor memory device 100, such mode setting, data setting, address setting, and data writing are repeated in each cycle up to N cycles.

[0045] (Continuous write mode) Fig. 5 is a timing chart for explaining an example of operation when the continuous write mode is set. In Fig. 5, the first cycle of data writing is triggered by the first CLK of the write clock pulse WEB, that is, when the first CLK after the write clock pulse WEB falls is detected.

[0046] Specifically, when the first CLK of the write clock pulse WEB is detected, if the command included in the data input signal DIN is a command indicating the setting of the continuous write mode, the semiconductor memory device 100 transitions to the continuous write mode. The command indicating the setting of the continuous write mode may be, for example, "#0003B0" (4 times of continuous data write) or "#00FFB0" (256 times of continuous data write). In other words, the continuous write mode and the number of repetitions R of data rewrite are set.

[0047] After that, when the second CLK of the write clock pulse WEB (the rising edge of CLK) is detected, the write address A(a) and write data D(a) are set, and the write operation is started while being internally held in each latch circuit.

[0048] At this time, the semiconductor memory device 100 receives the data contained in the data input signal DIN and the address contained in the address input signal AIN, and sets the write start address A(s).

[0049] As a result, the write operation is performed from the write start address A(s) a number of times corresponding to the repeat count, while the address is automatically incremented.

[0050] When the second CLK of the write clock pulse WEB is detected, the internal write signal INTW transitions from the non-write state "L" to the write state "H", thereby enabling writing. The write monitor signal BUSY is approximately linked to the internal write signal INTW, and the semiconductor memory device 100 switches the level of the write monitor signal BUSY from L to H. This ends the first cycle of data writing.

[0051] When the external control circuit 200 detects that the level of the write monitor signal BUSY has switched from H to L, it determines that the first cycle of data writing, that is, the writing of the write data D(s+1), has ended.

[0052] The external control circuit 200 monitors the timing at which the level of the BUSY signal rises from L to H, and switches to data for the second cycle and thereafter.

[0053] Specifically, the internal write signal INTW transitions to the write state "H" and then transitions to the non-write state "L" when a specific internally set write time (several tens of us) has elapsed. This causes the level of the write monitor signal BUSY to switch from H to L. At this time, the external control circuit 200 does not perform mode setting, and the semiconductor memory device 100 switches to the data D(s+1) to be written in the second cycle, and further switches to the address A(s+1). By transitioning from the non-write state "L" to the write state "H", the semiconductor memory device 100 becomes in a write-enabled state.

[0054] This operation is repeated up to R cycles according to the number of repeats R.

[0055] 6 is a flowchart for explaining a data writing method of the semiconductor memory device of the present disclosure. The data writing method of the semiconductor memory device may include a process of selecting a write mode (step S1) and a process of setting the number of data writes from the start of writing data to a start address to the completion of writing data to a completion address (step S2).

[0056] In step S1, when a second address other than the first address is specified after data has been written to a first address among multiple consecutive addresses in a memory, the command register selects either a first write mode in which data is written to the second address, or a second write mode in which data is written consecutively from the first address to the second address among the multiple addresses.

[0057] In step S2, when the address buffer sets the first address as a start address for starting data writing and the second address as a completion address for completing data writing, it sets the number of data writes from the start of data writing to the start address to the completion of data writing to the completion address.

[0058] In addition, the data writing method for a semiconductor memory device may include, when the command register selects the second write mode, a process (step S3) of writing data corresponding to a number of times to each of the starting address and one or more addresses subsequent to the starting address.

[0059] (Action and effect) The semiconductor memory device 100 disclosed herein is configured to be capable of setting a second write mode in which data is written continuously from a first address to a second address, and when the second write mode is set, data is automatically written to the starting address and one or more addresses subsequent to the starting address, the number of times corresponding to the number set in the number setting unit 20a.

[0060] Therefore, continuous data rewrite processing can be performed internally. In other words, data rewrite can be performed only by the internal processing of the semiconductor memory device 100 without the need for the external control circuit 200 to set a mode (e.g., set the first mode) or reset the addresses every time data is written to each of a plurality of continuous addresses.

[0061] In this way, since there is no need to set the address each time writing of data to an address is completed, it is possible to reduce the monitoring process time in the external control circuit 200. Since data can be written to consecutive addresses while reducing the monitoring process time, the time required to complete rewriting data to multiple consecutive addresses can be significantly shortened.

[0062] In addition, by monitoring that the level of the write monitor signal BUSY has risen from L to H and switching the data for the next cycle, the write data setting latch time can also be reduced.

[0063] Furthermore, since the control during successive rewriting can be simplified, the circuit scale of the external control circuit 200 can be reduced.

[0064] In addition, the following supplementary notes are provided in relation to the above description.

[0065] (Appendix 1) a command register that holds data input from an external device and controls writing of the data to a rewritable memory; an address buffer for holding an address designated from outside among the addresses of the memory; Equipped with The command register includes: a first write mode in which, after completing writing data to a first address among a plurality of consecutive addresses in the memory, when a second address other than the first address is designated, data is written to the second address; a second write mode in which data is written continuously from the first address to the second address among the plurality of addresses, The address buffer includes: a number setting unit that sets the number of data writes from when the first address is a start address for starting data writing and the second address is a completion address for completing data writing, the number of data writes being set from when data writing is started to the start address to when data writing is completed to the completion address; When the second write mode is selected, the command register writes data to the start address and one or more addresses subsequent to the start address, the number of times corresponding to the number of times set in the number setting unit. Semiconductor memory device. (Appendix 2) 2. The semiconductor memory device of claim 1, wherein the address buffer selects a bit line and a word line corresponding to the start address and one or more addresses subsequent to the start address. (Appendix 3) 3. The semiconductor memory device of claim 2, wherein when the second write mode is selected, the command register transmits address information indicating the start address and one or more addresses consecutive to the start address to the address buffer. (Appendix 4) 2. The semiconductor memory device according to claim 1, wherein the address buffer increments the number of times each time data is written from when the command register starts writing data to the plurality of addresses until the command register completes writing the data. (Appendix 5) A data writing method for a semiconductor memory device including a command register that holds data input from an external source and controls writing of data to a rewritable memory, and an address buffer that holds an address that is externally designated among addresses of the memory, comprising the steps of: a step of selecting, by the command register, either a first write mode in which data is written to a first address among a plurality of consecutive addresses in the memory when a second address other than the first address is designated after completion of writing data to the first address, or a second write mode in which data is written consecutively from the first address to the second address among the plurality of addresses; a step of setting a number of data writes from when the address buffer starts writing data to the start address to when the address buffer sets the first address as a start address for starting writing data and the second address as a completion address for completing writing data to the completion address; when the command register selects the second write mode, writing data to the start address and one or more addresses subsequent to the start address a number of times corresponding to the number of times; A data writing method for a semiconductor memory device comprising: [Explanation of symbols]

[0066] 10 Command Register 10a External input section 10b Mode setting section 10c Data writing section 11 First mode circuit 12 Second mode circuit 20 Address Buffer 20a Number of times setting section 20b Address selection section 20c Number of times management section 21 Repeat Register 30 Data Input Buffer 40 Flash Memory 100 Semiconductor memory device 200 External control circuit

Claims

1. a command register that holds data input from an external device and controls writing of the data to a rewritable memory; an address buffer for holding an externally designated address among the addresses of the memory; Equipped with The command register includes: a first write mode in which, after completing writing data to a first address among a plurality of consecutive addresses in the memory, when a second address other than the first address is designated, data is written to the second address; a second write mode in which data is written continuously from the first address to the second address among the plurality of addresses, The address buffer includes: a number setting unit that sets the number of data writes from when the first address is a start address for starting data writing and the second address is a completion address for completing data writing, the number of data writes being set from when data writing is started to the start address to when data writing is completed to the completion address; When the second write mode is selected, the command register writes data to the start address and one or more addresses subsequent to the start address, the number of times corresponding to the number of times set in the number setting unit. Semiconductor memory device.

2. 2. The semiconductor memory device according to claim 1, wherein said address buffer selects a bit line and a word line corresponding to said starting address and one or more addresses subsequent to said starting address.

3. 3. The semiconductor memory device according to claim 2, wherein said command register, when selecting said second write mode, transmits to said address buffer address information indicating said starting address and one or more addresses subsequent to said starting address.

4. 2. The semiconductor memory device according to claim 1, wherein said address buffer increments said count every time data is written from when said command register starts writing data to said plurality of addresses until the data writing is completed.

5. A data writing method for a semiconductor memory device including a command register that holds data input from an external source and controls writing of data to a rewritable memory, and an address buffer that holds an address that is externally designated among addresses of the memory, comprising the steps of: a step of selecting, by the command register, either a first write mode in which data is written to a first address among a plurality of consecutive addresses in the memory when a second address other than the first address is designated after completion of writing data to the first address, or a second write mode in which data is written consecutively from the first address to the second address among the plurality of addresses; a step of setting a number of data writes from when the address buffer starts writing data to the start address to when the address buffer sets the first address as a start address for starting writing data and the second address as a completion address for completing writing data to the completion address; writing data to the start address and one or more addresses subsequent to the start address a number of times corresponding to the number of times when the command register selects the second write mode; A data writing method for a semiconductor memory device comprising:

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