Regulator circuit and inverter circuit

Abstract

To provide a low-saturation regulator circuit and an inverter circuit that are capable of stable operation and have a simple configuration.SOLUTION: A regulator circuit (1) adjusts an input voltage (Vin) from a power source (10) to a predetermined voltage via a first N-type transistor (20) and outputs the adjusted voltage, and includes a boost section (30) and a first control section (40), the boost section (30) boosts the input voltage (Vin) to generate a first drive voltage (Vg) for the first N-type transistor (20), and the first control section (40) adjusts the first drive voltage (Vg) based on the output voltage of the first N-type transistor (20) and performs control to maintain the drive voltage level of the first N-type transistor (20) at a predetermined value.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a regulator circuit and an inverter circuit. [Background technology]

[0002] P-type transistors are generally used for the output of low-saturation regulator circuits, but it is difficult to ensure a phase margin and severe measures against oscillation are required. On the other hand, if N-type transistors are used, it is easy to ensure a phase margin, but an input / output voltage difference is required, and it does not become a low-saturation regulator circuit. Patent Document 1 discloses a regulator circuit (step-up switching power supply circuit) that uses N-type transistors. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2019-129631 A Summary of the Invention [Problem to be solved by the invention]

[0004] In recent years, regulator circuits are sometimes used in connection with inverter circuits, but there is a problem that connecting a regulator circuit whose operation is unstable or which is not low saturation to an inverter circuit may lead to a decrease in the performance of the inverter circuit. In addition, there is an increasing need for regulator circuits that are not complicated in configuration. Therefore, there is a demand for the development of a low saturation regulator circuit that is capable of stable operation and has a simple configuration.

[0005] The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a regulator circuit and an inverter circuit that can solve the above problems. [Means for solving the problem]

[0006] The regulator circuit (1) according to the present invention includes a first N-type transistor (20), a boost section (30), and a first control section (40), and adjusts an input voltage (Vin) from a power source (10) to a predetermined voltage via the first N-type transistor (20) and outputs the adjusted voltage, wherein the boost section (30) boosts the input voltage (Vin) to generate a first drive voltage (Vg) for the first N-type transistor (20), and the first control section (40) adjusts the first drive voltage (Vg) based on a voltage (Vout) on the output side of the first N-type transistor (20) and performs control to maintain the drive voltage level of the first N-type transistor (20) at a predetermined value.

[0007] According to the present invention, the regulator circuit (1) includes a first N-type transistor (20), a boost section (30), and a first control section (40), and adjusts an input voltage (Vin) from a power source (10) to a predetermined voltage via the first N-type transistor (20) and outputs the adjusted voltage, in which the boost section (30) boosts the input voltage (Vin) to generate a first drive voltage (Vg) for the first N-type transistor (20), and the first control section (40) adjusts the first drive voltage (Vg) based on the output voltage (Vout) of the first N-type transistor (20) to maintain the drive voltage level of the first N-type transistor (20) at a predetermined value. This makes it possible to provide a low-saturation regulator circuit that is capable of stable operation and has a simple configuration.

[0008] The regulator circuit (1) of the present invention is a regulator circuit (1) that adjusts an input voltage (Vin) from a power source (10) to a predetermined voltage via a first N-type transistor (20) and outputs the adjusted voltage, and includes a boost section (30) and a first control section (40). The boost section (30) receives the input voltage (Vin) and boosts the input voltage (Vin) to generate a first drive voltage (Vg) for the first N-type transistor (20). The first control section (40) adjusts the first drive voltage (Vg) based on a voltage (Vout) on the output side of the first N-type transistor (20) and performs control to maintain the High level of the drive voltage of the first N-type transistor (20) at a predetermined value.

[0009] According to the present invention, the regulator circuit (1) adjusts an input voltage (Vin) from a power source (10) to a predetermined voltage via a first N-type transistor (20) and outputs the adjusted voltage, and includes a boost section (30) and a control section (40), in which the input voltage (Vin) is input to the boost section (30) and boosts the input voltage (Vin) to generate a first drive voltage (Vg) for the first N-type transistor (20), and the control section (40) adjusts the first drive voltage (Vg) based on the output voltage (Vout) of the first N-type transistor (20) and performs control to maintain the high level of the first drive voltage (Vg) for the first N-type transistor (20) at a predetermined value. This makes it possible to provide a low-saturation regulator circuit that is capable of stable operation and has a simple configuration.

[0010] The regulator circuit (1) according to the present invention is characterized in including a second control section (50) connected between a boost section (30) and a first N-type transistor (20) and having any one or a combination of a constant current source (52), resistors (54, 56), and a capacitor (58).

[0011] According to the present invention, since the first drive voltage (Vg) is stably adjusted, it is possible to stably control the drive voltage level of the first N-type transistor (20) to be maintained at a predetermined value, thereby making it possible to provide a low saturation regulator circuit with a simple configuration that can operate more reliably and stably.

[0012] The regulator circuit (1) according to the present invention is characterized in that it includes a third control unit (60) connected between a power source (10) and a boost unit (30) and adjusting the supply voltage to the boost unit (30).

[0013] According to the present invention, a stable voltage supply to the boosting unit (30) can be achieved without using a power supply for supplying voltage to the boosting unit (30) separate from the power supply (10). This makes it possible to provide a low-saturation regulator circuit with a simple configuration that can reliably operate stably.

[0014] The inverter circuit (100) of the present invention is an inverter circuit (100) including the above-described regulator circuit (1), and includes a step-down setting unit (110) and an inverter unit (120). The step-down setting unit (110) supplies a voltage obtained by step-down setting of the voltage on the output side of the first N-type transistor (20) to the inverter unit (120). The inverter unit (120) has a Hi-side switching element (120a) and a Low-side switching element (120b), and outputs control signals (VB1, VB2) based on the step-down set voltage (VBD) by turning on and off the Hi-side switching element (120a) and the Low-side switching element (120b) in response to an input voltage (VA) input from a signal source (A).

[0015] According to the present invention, the boost section (30) of the regulator circuit (1) boosts the input voltage (Vin) from the power supply (10) to generate a first drive voltage (Vg) for the first N-type transistor (20), and the first control section (40) adjusts the first drive voltage (Vg) based on the output voltage of the first N-type transistor (20) and performs control to maintain the drive voltage level of the first N-type transistor (20) at a predetermined value. This makes it possible to provide a low-saturation regulator circuit capable of stable operation and having a simple configuration. The step-down setting section (110) of the inverter circuit (100) supplies a voltage (VBD) obtained by stepping down the voltage on the output side of the first N-type transistor (20) to the inverter section (120). The inverter section (120) stably outputs a control signal that turns on and off the Hi-side switching element (120a) and the Low-side switching element (120b) in response to the input voltage (VA) input from the signal source (A) to output control signals (VB1, VB2) based on the step-down set voltage (VBD). This improves the performance of the inverter circuit (100).

[0016] The inverter circuit (200) according to the present invention is an inverter circuit (200) including the regulator circuit (1) described above, and includes an inverter section (210), a first power supply (221), a second power supply (222), a first capacitor (241), a second capacitor (242), a change-over switch (250), and a pulse generator (270). The inverter section (210) has a high-side switching element (211) and a low-side switching element (212). The first power supply (221) supplies a first voltage to the inverter section (210). The second power supply (222) supplies a second voltage to the change-over switch (250). the first capacitor (241) supplies a drive voltage (Vg) that drives the Hi-side switching element (120a); the second capacitor (242) supplies a voltage to the first capacitor (241); the change-over switch (250) switches between charging and discharging the second capacitor (242) by turning on and off; and the pulse generator (270) generates a pulse-shaped control signal for controlling the Hi-side switching element (211), the Low-side switching element (212), and the change-over switch (250) based on the voltage on the output side of the first N-type transistor (20).

[0017] According to the present invention, the boost section (30) of the regulator circuit (1) boosts the input voltage (Vin) to generate a first drive voltage (Vg) for the first N-type transistor (20), and the first control section (40) adjusts the first drive voltage (Vg) based on the output voltage of the first N-type transistor (20) to control the drive voltage level of the first N-type transistor (20) to be maintained at a predetermined value. This makes it possible to provide a low-saturation regulator circuit that can operate stably and has a simple configuration. By supplying power from this low-saturation regulator circuit to the pulse generator (270), the pulse generator (270) can generate a stable pulse voltage and supply it to the high-side switching element (211), the low-side switching element (212), and the change-over switch (250).

[0018] The first power supply (221) supplies a first voltage to the inverter section (210), the second power supply (222) supplies a second voltage to the changeover switch (250), the first capacitor (241) supplies a drive voltage (Vg) for driving the high-side switching element (211), the second capacitor (242) supplies a voltage to the first capacitor (241), the changeover switch (250) switches between charging and discharging the second capacitor (242) by turning on and off, and the pulse generator (270) generates a pulse-shaped control signal for controlling the high-side switching element (120a), the low-side switching element (120b), and the changeover switch (250) based on the voltage on the output side of the first N-type transistor (20). In this manner, the performance of the inverter circuit (1) can be improved. Effect of the Invention

[0019] According to the present invention, it is possible to provide a low-saturation regulator circuit that is capable of stable operation and has a simple configuration. [Brief description of the drawings]

[0020] [Figure 1] 1 is a first circuit diagram showing an overview of an entire configuration of a regulator circuit according to an embodiment of the present invention. [Diagram 2] 2 is a circuit diagram showing a configuration of a first N-type transistor of the regulator circuit. FIG. [Diagram 3] 4 is a circuit diagram showing a configuration of a first control unit of the regulator circuit. FIG. [Figure 4] FIG. 2 is a second circuit diagram showing an outline of the overall configuration of the regulator circuit. [Diagram 5] 4 is a circuit diagram showing a configuration of a second control unit of the regulator circuit. FIG. [Figure 6] FIG. 4 is a third circuit diagram showing an outline of the overall configuration of the regulator circuit. [Figure 7] 4 is a circuit diagram showing a configuration of a third control unit of the regulator circuit. FIG. [Figure 8] 2 is a circuit diagram showing details of the overall configuration of a regulator circuit. FIG. [Figure 9] 1 is a block diagram showing a configuration of a motor control system including an inverter circuit equipped with a regulator circuit according to an embodiment of the present invention. [Figure 10] FIG. 2 is a block diagram showing the configuration of the inverter circuit. [Figure 11] FIG. 2 is a circuit diagram showing a configuration of the inverter circuit. [Figure 12] 4 is a diagram showing the relationship between the input voltage from an external signal source and the through current in a first inverter section in the inverter circuit. FIG. [Figure 13] 4 is a diagram showing the relationship between a voltage corresponding to a first control signal and a through current in a second inverter section in the inverter circuit. FIG. [Figure 14] 1A is a diagram showing the configuration of a P-channel MOSFET transistor in a step-down setting section, and FIG. 1B is a diagram showing the configuration of a P-channel MOSFET transistor in a second inverter circuit. [Figure 15] 4 is a diagram showing the relationship between the input voltage from an external signal source and the through current in a first inverter section in the inverter circuit according to the first embodiment of the present invention. FIG. [Figure 16] 3 is an enlarged circuit diagram showing a configuration of an inverter circuit according to a first comparative example of the present invention. FIG. [Figure 17] 11 is a diagram showing the relationship between the input voltage from an external signal source and the through current in a first inverter section in the inverter circuit according to Comparative Example 1 of the present invention. FIG. [Figure 18] FIG. 11 is a diagram showing the relationship between a voltage signal corresponding to a first control signal and a through current in a second inverter section in the inverter circuit according to Example 2 of the present invention. [Figure 19] 11 is a diagram showing the relationship between a voltage signal corresponding to a first control signal and a through current in a second inverter section in an inverter circuit according to Comparative Example 2 of the present invention. FIG. [Figure 20] FIG. 11 is a circuit diagram showing a configuration of another inverter circuit according to an embodiment of the present invention. [Figure 21]4 is a circuit diagram showing the detailed configuration of a changeover switch in the inverter circuit. FIG. [Figure 22] 13A and 13B are timing charts for explaining the operation of the inverter circuit and diagrams showing capacitor voltages, where (a) is a timing chart for explaining the operation of the Hi side switching element, (b) is a timing chart for explaining the operation of the Low side switching element, (c) is a timing chart for explaining the operation of the change-over switch, (d) is a timing chart for explaining the operation of CLK, (e) is a diagram showing the voltage across the first capacitor, (f) is a diagram showing the voltage across the second capacitor, and (g) is a diagram showing the upper end voltage of the second capacitor. [Figure 23] 1 is a circuit diagram showing a state in which the high-side switching element is on, the low-side switching element is off, and the change-over switch is off in the inverter circuit. [Figure 24] FIG. 24 is a circuit diagram showing details of the state of the changeover switch in FIG. 23. [Diagram 25] 1 is a circuit diagram showing a state in which the high-side switching element is on, the low-side switching element is off, and the change-over switch is on in the inverter circuit. [Figure 26] FIG. 26 is a circuit diagram showing in detail the state of the changeover switch in FIG. 25. [Figure 27] 1 is a circuit diagram showing a state in which the high-side switching element is off, the low-side switching element is on, and the change-over switch is on in the inverter circuit. [Figure 28] FIG. 13 is a diagram showing a modified example of the inverter circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] An embodiment of the present invention will be described with reference to the drawings. Note that the embodiment described below does not limit the present invention, and appropriate modifications or applications are possible without departing from the spirit of the invention. For example, the effects of the present invention can be achieved even with the configuration described below.

[0022] <Configuration corresponding to claims 1 and 2> FIG. 1 is a first circuit diagram showing an overview of the overall configuration of a regulator circuit according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing the configuration of a first N-type transistor of the regulator circuit, FIG. 3 is a circuit diagram showing the configuration of a first control unit of the regulator circuit, FIG. 4 is a second circuit diagram showing an overview of the overall configuration of the regulator circuit, FIG. 5 is a circuit diagram showing the configuration of a second control unit of the regulator circuit, FIG. 6 is a third circuit diagram showing an overview of the overall configuration of the regulator circuit, FIG. 7 is a circuit diagram showing the configuration of a third control unit of the regulator circuit, and FIG. 8 is a circuit diagram showing details of the overall configuration of the regulator circuit.

[0023] A regulator circuit 1 according to an embodiment of the present invention will be described with reference to Fig. 1. The regulator circuit 1, power supply 10, first N-type transistor 20, boost unit 30, and first control unit 40 in this embodiment correspond to the regulator circuit, power supply, first N-type transistor, boost unit, and first control unit according to the present invention, respectively.

[0024] The regulator circuit 1 includes a first N-type transistor 20, a boost section 30, and a first control section 40, and adjusts the input voltage Vin from a power source 10 to a predetermined voltage via the first N-type transistor 20 and outputs the voltage. The boost section 30 boosts the input voltage Vin to generate a first drive voltage Vg for the first N-type transistor 20, and the first control section 40 adjusts the first drive voltage Vg based on the output voltage of the first N-type transistor 20, thereby performing control to maintain the drive voltage level of the first N-type transistor 20 at a predetermined value.

[0025] More specifically, the regulator circuit 1 includes a first N-type transistor 20, a boost section 30, and a first control section 40, and adjusts the input voltage Vin from the power supply 10 to a predetermined voltage via the first N-type transistor 20 and outputs the adjusted voltage. The boost section 30 receives the input voltage Vin and boosts the input voltage Vin to generate a first drive voltage Vg for the first N-type transistor 20. The first control section 40 adjusts the first drive voltage of the first N-type transistor 20 based on the voltage Vout on the output side of the first N-type transistor 20, and performs control to maintain the High level of the first drive voltage Vg of the first N-type transistor 20 at a predetermined value.

[0026] As shown in FIG. 2, the first N-type transistor 20 is configured to adjust the voltage Vin from the power supply 10 and output a predetermined voltage. In the regulator circuit 1 according to the present invention, since an N-type transistor is used, a low-saturation regulator capable of sufficiently reducing the input / output voltage difference while easily securing a phase margin compared to a P-type transistor can be realized. The first N-type transistor 20 has a drain 20d, a gate 20g, and a source 20s. The drain 20d is connected to the power supply 10, one end of a resistor 66 described later, and a drain 62d of the second N-type transistor 62. The gate 20g is connected to a terminal 55B of the second control unit 50 and a terminal 42C of the first control unit 40. The source 20s is connected to the inverter circuits 100 and 200 and one end of a resistor 44.

[0027] As described above, the boost unit 30 receives the input voltage Vin and boosts the input voltage Vin to generate the first drive voltage Vg for the first N-type transistor 20. More specifically, the boost unit 30 boosts the input voltage Vin by ΔVa and generates the first drive voltage Vg for the first N-type transistor 20 based on the boosted voltage Va (Vin+ΔVa).

[0028] The boost unit 30 has terminals 30A and 30B for connection to other components. The terminal 30A of the boost unit 30 is connected to the source 62s of the second N-type transistor 62 and one end of the resistor 64. The terminal 30B of the boost unit 30 is connected to the terminal 55A of the second control unit 50. When the input voltage Vin is 0V, the boost unit 30 does not perform a boost operation and Va is 0V.

[0029] As described above, the first control unit 40 adjusts the first drive voltage Vg based on the output voltage Vout of the first N-type transistor 20, and performs control to maintain the drive voltage level of the first N-type transistor 20 at a predetermined value.

[0030] 3, the first control unit 40 has a comparator 42, a resistor 44, a resistor 46, and a power supply 48. The comparator 42 has a terminal 42A, a terminal 42B, and a terminal 42C. The terminal 42A is connected to the other end of the resistor 44 and one end of the resistor 46. The terminal 42B is connected to the positive electrode of the power supply 48. The terminal 42C is connected to the gate 20g of the first N-type transistor 20 and a terminal 55B of the second control unit 50. One end of the resistor 44 is connected to the source 20s of the first N-type transistor 20 and the inverter circuits 100 and 200. The other end of the resistor 46 and the negative electrode of the power supply 48 are connected to the ground G.

[0031] The control voltage Vb output by the first control unit 40 is determined based on the result of comparing the voltage Vb' of the power supply 48 input to terminal 42B with the voltage Vout' obtained by dividing the output side voltage Vout of the first N-type transistor 20 input to terminal 42A by resistors 44 and 46.

[0032] <Configuration corresponding to claim 3> 4 and 5, the regulator circuit 1 in this embodiment is preferably provided with a second control unit 50 connected between the boost unit 30 and the first N-type transistor 20 and having at least one or a combination of a constant current source 52, a resistor 54, a resistor 56, and a capacitor 58. The second control unit 50 is configured by appropriately combining the constant current source 52, the resistor 54, the resistor 56, and / or the capacitor 58. The constant current source 52, the resistor 54, the resistor 56, the capacitor 58, and the second control unit 50 in this embodiment correspond to the constant current source, the resistor, the capacitor, and the second control unit according to the present invention, respectively.

[0033] The constant current source 52 adjusts the first drive voltage Vg by generating and supplying a predetermined constant current corresponding to the specifications of the first N-type transistor 20, and performs control to maintain the drive voltage level of the first N-type transistor 20 at a predetermined value. Moreover, the resistor 54 adjusts the first drive voltage Vg by supplying a current corresponding to the specifications of the first N-type transistor 20 and the drive capacity of the first control unit 40, and performs control to maintain the drive voltage level of the first N-type transistor 20 at a predetermined value. The resistor 56 and / or the capacitor 58 suppress noise superimposed on the output from the boost unit 30.

[0034] <Configuration of the embodiment corresponding to claim 4> The regulator circuit 1 preferably includes a third control unit 60 as shown in Fig. 6 and Fig. 7. The third control unit 60 preferably includes a second N-type transistor 62 that is connected between the power source 10 and the boost unit 30 and adjusts the supply voltage to the boost unit 30. The third control unit 60 in this embodiment corresponds to the second N-type transistor and the third control unit, respectively, of the present invention.

[0035] The third control section 60 can be configured as a step-down circuit by appropriately combining, for example, a resistor 64, a resistor 66, and a Zener diode 68 in addition to the second N-type transistor 62.

[0036] The second N-type transistor 62 is, for example, an N-channel MOSFET, and is configured to adjust the voltage Vin from the power supply 10 and output a predetermined voltage to the boost unit 30. In this embodiment, since an N-type transistor is used as the second N-type transistor 62, it is possible to sufficiently reduce the input / output voltage difference while making it easier to ensure a phase margin compared to a P-type transistor.

[0037] The second N-type transistor 62 has a drain 62d, a gate 62g, and a source 62s. The drain 62d is connected to the power supply 10, one end of the resistor 66, and the drain 20d of the first N-type transistor 20. The gate 62g is connected to the other end of the resistor 66 and the cathode of the Zener diode 68. The source 62s is connected to one end of the resistor 64 and the booster unit 30. One end of the resistor 66 is connected to the power supply 10 and the drain 62d of the second N-type transistor 62. The other end of the resistor 66 is connected to the gate 62g of the second N-type transistor 62 and the cathode of the Zener diode 68. The anode of the Zener diode 68 and the other end of the resistor 64 are connected to the ground G.

[0038] The third control unit 60 is preferably configured to include, for example, a charge pump connected between the power source 10 and the boost unit 30 to adjust the supply voltage to the boost unit 30. By including a charge pump, when the input voltage Vin from the power source 10 is insufficient, for example, the input voltage Vin, the first drive voltage Vg, and / or Vout can be detected, and the charge pump can be operated to boost the input voltage Vin from the power source 10 and adjust the supply voltage to the boost unit 30. Such adjustment is preferably performed based on a detection signal from the boost unit 30, the first control unit 40, the second control unit 50, or the third control unit 60.

[0039] <Operation of the configuration corresponding to claims 1 to 4> The regulator circuit 1 of this embodiment configured as above can be operated as follows.

[0040] That is, the second N-type transistor 62 of the third control unit 60 is turned on. As a result, the voltage Vin from the power supply 10 is input to the boost unit 30 via the second N-type transistor 62. At the junction α of the output side (terminal 30B) of the boost unit 30 and the output side (terminal 42C) of the first control unit 40, when the voltage Va boosted by the boost unit 30 is greater than the control voltage Vb output by the first control unit 40, the boosted voltage Va becomes the drive voltage (gate voltage) Vg, and when the voltage Va boosted by the boost unit 30 is smaller than the control voltage Vb output by the first control unit 40, the control voltage Vb becomes the drive voltage (gate voltage) Vg.

[0041] In this way, when the drive voltage (gate voltage) Vg is input to the gate electrode 20g of the first N-type transistor 20 by the boost unit 30 or the first control unit 40, the first N-type transistor 20 is turned on and the voltage Vout is output to the inverter circuits 100, 200.

[0042] On the other hand, when the second N-type transistor 62 is turned off and the input voltage Vin is not input to the booster 30, the voltage Va boosted by the booster 30 becomes 0, and at the junction α of the output side (terminal 30B) of the booster 30 and the output side (terminal 42C) of the first control unit 40, the voltage Va boosted by the booster 30 becomes smaller than the control voltage Vb output by the first control unit 40, and the control voltage Vb becomes the drive voltage (gate voltage) Vg. As a result, the drive voltage (gate voltage) Vg is input to the gate electrode 20g of the first N-type transistor 20, so that the first N-type transistor 20 is turned on and the voltage Vout is output to the inverter circuits 100, 200.

[0043] <Effect of the configuration corresponding to claim 1> In the regulator circuit 1 of this embodiment, the regulator circuit 1 adjusts the input voltage Vin from the power supply 10 to a predetermined voltage via the first N-type transistor 20 and outputs the adjusted voltage. In the regulator circuit 1, the boost unit 30 boosts the input voltage Vin to generate a first drive voltage Vg for the first N-type transistor 20. The first control unit 40 adjusts the first drive voltage Vg based on the voltage Vout on the output side of the first N-type transistor 20, and performs control to maintain the drive voltage level of the first N-type transistor 20 at a predetermined value. This makes it possible to provide a low-saturation regulator circuit that is capable of stable operation and has a simple configuration.

[0044] <Effect of the configuration corresponding to claim 2> In the regulator circuit 1 according to this embodiment, the regulator circuit 1 adjusts the input voltage Vin from the power source 10 to a predetermined voltage via the first N-type transistor 20 and outputs the adjusted voltage. The regulator circuit 1 includes a booster 30 and a controller 40. The booster 30 receives the input voltage Vin and boosts the input voltage Vin to generate a first drive voltage Vg for the first N-type transistor 20. The first controller 40 adjusts the first drive voltage Vg based on the output voltage Vout of the first N-type transistor 20, and performs control to maintain the High level of the first drive voltage Vg for the first N-type transistor 20 at a predetermined value. This makes it possible to provide a low-saturation regulator circuit that is capable of stable operation and has a simple configuration.

[0045] <Effect of the configuration corresponding to claim 3> As exemplified in this embodiment, when the regulator circuit 1 is configured to include the second control unit 50, the first drive voltage Vg is stably adjusted, and therefore the drive voltage level of the first N-type transistor 20 can be stably controlled to be maintained at a predetermined value. This makes it possible to provide a low saturation regulator circuit 1 with a simple configuration that can operate more reliably and stably.

[0046] <Effect of the configuration corresponding to claim 4> As exemplified in this embodiment, when the regulator circuit 1 is configured to include the third control unit 60, it is possible to stably supply voltage to the boost unit 30 without using a power supply for supplying voltage to the boost unit 30 separate from the power supply 10. This makes it possible to provide a low saturation regulator circuit with a simple configuration that can reliably operate stably.

[0047] In addition, by inputting the input voltage Vin to the boost unit 30 via the second N-type transistor 62 that is turned on on the high side, when the input voltage Vin is low, the second N-type transistor 62 is turned off and the input voltage Vin is not input to the boost unit 30.

[0048] <Configuration corresponding to claim 5> FIG. 9 is a block diagram showing the configuration of a motor control system including an inverter circuit equipped with a regulator circuit according to an embodiment of the present invention. FIG. 10 is a block diagram showing the configuration of the inverter circuit. FIG. 11 is a circuit diagram showing the configuration of the inverter circuit. FIG. 12 is a diagram showing the relationship between the input voltage from an external signal source and the through current in the first inverter section in the inverter circuit. FIG. 13 is a diagram showing the relationship between the voltage corresponding to the first control signal in the inverter circuit and the through current in the second inverter section. FIG. 14 is a diagram showing the configuration of a P-channel MOSFET transistor in the inverter circuit.

[0049] 9, the configuration of a motor control system 100A including an inverter circuit 100 of the present invention will be explained in brief. The motor control system 100A is configured such that a plurality of inverter circuits 100 supply control signals to a motor drive switching circuit E via a logic circuit C and a driver circuit D based on an input voltage VA from a signal source A, more specifically an external signal source A, and a voltage Vout from the source electrode 20s side which is the output side of the first N-type transistor 20, thereby controlling the motor M. The external signal source A can be, for example, a microcomputer, and the input voltage VA is input from the external signal source A as a square wave pulse signal.

[0050] As shown in Figures 10 to 14, the inverter circuit 100 is an inverter circuit including a regulator circuit 1, and includes a step-down setting unit 110 and an inverter unit 120. The step-down setting unit 110 supplies a voltage VBD, which is a step-down setting of the voltage Vout on the output side of the first N-type transistor 20, to the inverter unit 120. The inverter unit 120 has a Hi-side switching element 120a and a Low-side switching element 120b, and outputs control signals VB1, VB2 based on the step-down set voltage VBD by turning on and off the Hi-side switching element 120a and the Low-side switching element 120b in response to an input voltage VA input from a signal source A.

[0051] In the inverter circuit 100, the regulator circuit 1 adjusts the input voltage from the power source 10 to a predetermined voltage via the first N-type transistor 20 and outputs the adjusted voltage. In the regulator circuit 1, the boost unit 30 boosts the input voltage to generate a first drive voltage Vg1 for the first N-type transistor 20, and the control unit 40 adjusts the first drive voltage Vg1 based on the output voltage of the first N-type transistor 20, and performs control to maintain the drive voltage level of the first N-type transistor 20 at a predetermined value. The step-down setting unit 110 of the inverter circuit 100 supplies a voltage VBD obtained by stepping down the output voltage Vout of the first N-type transistor 20 to the inverter unit 120. The inverter unit 120 has a Hi-side switching element 120a and a Low-side switching element 120b, and outputs control signals VB1 and VB2 based on the step-down set voltage VBD by turning on and off the Hi-side switching element 120a and the Low-side switching element 120b according to the input voltage VA input from the signal source A.

[0052] The inverter section 120 includes a first inverter section 121 and a second inverter section 122. The high-side switching element 120a includes a first high-side switching element 121a and a second high-side switching element 122a, and the low-side switching element 120b includes a first low-side switching element 121b and a second low-side switching element 122b. The inverter circuit 100 includes a first connection line L110 to a fifth connection line L150.

[0053] The first connection line L110 is a connection line connected to the source electrode 20s side, which is the output side of the first N-type transistor 20, and is supplied with a voltage Vout on the source electrode 20s side, which is the output side of the first N-type transistor 20. The voltage Vout on the source electrode 20s side, which is the output side of the first N-type transistor 20, is supplied at a constant voltage via the first connection line L110. The second connection line L120 is a connection line provided in parallel with the first connection line L110.

[0054] The third connection line L130 is a connection line that branches off from the first connection line L110 and connects the first connection line L110 and the second connection line L120. The third connection line L130 has the step-down setting unit 110 and the first inverter unit 121 connected in series to each other. The third connection line L130 includes connection lines L131, L132, L133, and L134 and a branch line L131'.

[0055] The fourth connection line L140 is a connection line that branches off from the first connection line L110 and connects the first connection line L110 and the second connection line L120, and is provided in parallel with the third connection line L130. The fourth connection line L140 includes connection lines L143 and L144. The second inverter section 122 is connected to the fourth connection line L140. The first inverter section 121 and the second inverter section 122 are arranged in parallel via the third connection line L130 and the fourth connection line L140. The fifth connection line L150 is a connection line that connects the midpoint 121A of the first inverter section 121 arranged in parallel with the gate electrodes 131aa and 131ba of the second inverter section 122.

[0056] The step-down setting unit 110 can supply the first inverter unit 121 with a voltage VBD obtained by stepping down the voltage Vout on the source electrode 20s side, which is the output side of the first N-type transistor 20. More specifically, the step-down setting unit 110 can supply the first inverter unit 121 with a voltage VBD obtained by stepping down the voltage Vout from the source electrode 20s side, which is the output side of the first N-type transistor 20. The step-down setting unit 110 has a step-down setting switching element 111, and can supply the inverter unit 120 with a voltage VBD obtained by stepping down the voltage Vout on the source electrode 20s side, which is the output side of the first N-type transistor 20, by a threshold voltage ΔVD of the step-down setting switching element 111, by turning on the step-down setting switching element 111.

[0057] More specifically, the step-down setting unit 110 has a step-down setting switching element 111, and by turning on the step-down setting switching element 111, a voltage VBD can be supplied to the first inverter unit 121, which is obtained by stepping down the voltage Vout on the source electrode 20s side, which is the output side of the first N-type transistor 20, by the threshold voltage ΔVD of the step-down setting switching element 111, more specifically, by the gate threshold voltage ΔVD (hereinafter, the gate threshold voltage is simply referred to as the threshold voltage), as shown in Equation 1 (the threshold voltage ΔVD is, to be precise, the absolute value of the threshold voltage ΔVD). The step-down setting switching element 111 can be a P-channel MOSFET transistor. [Number 1] VBD = Vout - |ΔVD|

[0058] That is, the step-down setting switching element 111 has a gate electrode 111a, a source electrode 111b, and a drain electrode 111c, and the gate electrode 111a and the drain electrode 111b are connected. A predetermined threshold voltage ΔVD is set for the step-down setting switching element 111.

[0059] A gate voltage VGD is input to the gate electrode 111a. That is, when the input gate voltage VGD is equal to or less than the input voltage Vout of the source electrode 111b, that is, the voltage VBD obtained by subtracting the threshold voltage ΔVD from the voltage Vout on the source electrode 20s side, which is the output side of the first N-type transistor 20, the step-down setting switching element 111 is turned on, and a predetermined current flows between the source electrode 111b and the drain electrode 111c. The voltage Vout from the source electrode 20s side, which is the output side of the first N-type transistor 20, is input to the source electrode 111b as a source voltage, and the voltage VBD obtained by stepping down the voltage Vout on the source electrode 20s side, which is the output side of the first N-type transistor 20, is output from the drain electrode 111c as a drain voltage.

[0060] A branch line L131' from the connection line L131 that connects the drain electrode 111c and the second inverter section 122 is connected to the gate electrode 111a.

[0061] That is, the gate electrode 111a and the drain electrode 111b are connected via a branch line L131'. The voltage from the drain electrode 111c is input to the gate electrode 111a via the branch line L131' as the gate voltage VGD, and the voltage output from the drain electrode 111c and supplied to the second inverter unit 122, that is, the stepped-down voltage VBD, is the voltage VBD that is the stepped-down voltage Vout on the source electrode 20s side, which is the output side of the first N-type transistor 20, by the threshold voltage ΔVD of the stepped-down setting switching element 11 as shown in Equation 1. In this embodiment, for example, the voltage Vout on the source electrode 20s side, which is the output side of the first N-type transistor 20, can be set to 5V, the threshold voltage ΔVD can be set to 1.1V, and the stepped-down voltage VBD can be set to 3.9V.

[0062] The first inverter unit 121 has a first Hi-side switching element 121a and a first Low-side switching element 121b, and generates and outputs a first control signal VB1 whose level is shifted to an intermediate voltage value between the input voltage VA input from the signal source A and the voltage Vout on the source electrode 20s side, which is the output side of the first N-type transistor 20, based on a voltage VBD that is set by turning on and off the first Hi-side switching element 121a and the first Low-side switching element 121b in response to an input voltage VA input from a signal source A. The second inverter unit 122 has a second Hi-side switching element 122a and a second Low-side switching element 122b. The first control signal VB1 is input to the first Hi-side switching element 122a and the second Low-side switching element 122b, and the second Hi-side switching element 122a and the second Low-side switching element 122b are turned on and off by input of the first control signal VB1, and a second control signal VB2 is generated and output that is level-shifted to the value of the voltage Vout on the source electrode 20s side, which is the output side of the first N-type transistor 20, with respect to the voltage VBD based on the first control signal VB1 (the intermediate voltage value between the input voltage VA and the voltage Vout on the source electrode 20s side, which is the output side of the first N-type transistor 20, is not limited to the median value between the input voltage VA and the voltage Vout on the source electrode 20s side, which is the output side of the first N-type transistor 20).

[0063] More specifically, the first inverter unit 121 is configured with a half-bridge CMOS and has a first Hi-side switching element 121a and a first Low-side switching element 121b. The first Hi-side switching element 121a and the first Low-side switching element 121b are connected in series. The first inverter unit 121 can generate and output a first control signal VB1 based on a voltage Vout (more specifically, a voltage VBD) on the source electrode 20s side, which is the output side of the first N-type transistor 20, by turning on and off the first Hi-side switching element 121a and the first Low-side switching element 121b according to an input voltage VA input from an external signal source A. The first Hi-side switching element 121a can be a P-channel MOSFET transistor.

[0064] That is, the first Hi side switching element 121a has a gate electrode 121aa, a source electrode 121ab, and a drain electrode 121ac, and is set with a predetermined threshold voltage ΔVP1, more specifically, a gate threshold voltage ΔVP1 (hereinafter, the gate threshold voltage is simply referred to as the threshold voltage) (to be precise, the threshold voltage ΔVP1 is the absolute value of the threshold voltage ΔVP1). An input voltage VA from an external signal source A is input to the gate electrode 121aa as a gate voltage VA.

[0065] In other words, when the input gate voltage VA is smaller than the stepped-down voltage VBD, that is, the voltage VBD' obtained by subtracting the threshold voltage ΔVP1 of the first Hi side switching element 121a from the input voltage VBD (source voltage) of the source electrode 121ab of the first Hi side switching element 121a, the first Hi side switching element 121a is turned on, and a predetermined current flows between the source electrode 121ab and the drain electrode 121ac. The stepped-down voltage VBD (source voltage) is input to the source electrode 121ab via the connection line L131, and the stepped-down voltage VBD (drain voltage) is output from the drain electrode 121ac as a voltage corresponding to the first control signal VB1. [Number 2] VBD´ = VBD - |ΔVP1|

[0066] The first low-side switching element 121b may be an N-channel MOSFET transistor. That is, the first low-side switching element 121b has a gate electrode 121ba, a drain electrode 121bb, and a source electrode 121bc, and is set with a predetermined threshold voltage ΔVN1, more specifically, a gate threshold voltage ΔVN1 (hereinafter, the gate threshold voltage is simply referred to as the threshold voltage) (the threshold voltage ΔVN1 is, to be precise, the absolute value of the threshold voltage ΔVN1).

[0067] An input voltage VA from an external signal source A is input as a gate voltage VA to the gate electrode 121ba via a connection line L132. That is, when the input gate voltage VA is greater than a threshold voltage ΔVN1, the first low-side switching element 121b is turned on, and a predetermined current flows between the drain electrode 121bb and the source electrode 121bc. The drain electrode 121bb of the first low-side switching element 121b is connected to the drain electrode 121ac of the first high-side switching element 121a via a connection line L33, and the source electrode 121bc of the first low-side switching element 121b is connected to the second connection line L120 via a connection line L134.

[0068] Here, in the first inverter section 121, when the first Hi side switching element 121a and the first Low side switching element 121b are both on and the voltage VBD' is greater than the input voltage VA from the external signal source A, i.e., the gate voltage VA, a large through current i1 may flow from the first Hi side switching element 121a to the first Low side switching element 121b.

[0069] On the other hand, when the voltage VBD' is smaller than the input voltage VA from the external signal source A, i.e., the gate voltage VA, the through current i1 is reduced even if both the first Hi side switching element 121a and the first Low side switching element 121b are on.

[0070] As shown in Figure 12, the voltage VBD' is the maximum output VA of the input voltage VA. MAX If the step-down setting unit 110 sets the step-down voltage and the threshold voltage ΔVP1 so that the through current i1 is smaller than the threshold voltage ΔVP1, a region in which the through current i1 is reliably reduced is formed.

[0071] Therefore, in this embodiment, as shown in the formula 3, the voltage VBD' is the maximum output VA of the input voltage VA. MAX The step-down setting by the step-down setting unit 110 and the threshold voltage ΔVP1 are set so that the step-down voltage VBD set by the step-down setting unit 110 is smaller than the maximum output of the input voltage VA. MAX When the threshold voltage of the first Hi-side switching element 121a is ΔVP1, VA MAX >It is preferable that the VBD-ΔVP1 relationship is established. [Number 3] VA MAX >VBD-ΔVP1 VBD-ΔVP1=VBD´

[0072] In this way, the voltage VBD' is the maximum output VA of the input voltage VA. MAX By setting the step-down setting and the threshold voltage ΔVP1 so that the input voltage VA is smaller than the voltage VBD', as shown in FIG. 12, it is possible to reliably form a region F of the input voltage VA where the input voltage VA is greater than the voltage VBD', and the through current i1 generated in the first inverter section 121 can be reduced.

[0073] In FIG. 12, the region F' of the input voltage VA where the through current i1 occurs is the range from the threshold voltage ΔVN1 of the first low-side switching element 121b to the voltage VBD', and the region F of the input voltage VA where the through current i1 is reduced is the range from the voltage VBD' to the maximum output VA of the input voltage VA. MAX The through current i1 is also reduced in a region F'' where the input voltage VA is equal to or lower than the threshold voltage ΔVN1, the first high-side switching element 121a is on, and the first low-side switching element 121b is off. Note that in this embodiment, for example,MAX can be set to 3.3V, the voltage based on the first control signal VB1, i.e., voltage VBD, can be set to 3.9V, the threshold voltage ΔVP1 of the first Hi side switching element 121a can be set to 1.2V, the threshold voltage ΔVN1 of the first Low side switching element 121b can be set to 1.2V, and the voltage VBD' obtained by subtracting the threshold voltage ΔVP1 of the first Hi side switching element 121a from the stepped-down set voltage VBD can be set to 2.7V.

[0074] The second inverter unit 122 is configured with a half-bridge CMOS and has a second Hi-side switching element 122a and a second Low-side switching element 122b. The second Hi-side switching element 122a and the second Low-side switching element 122b are connected in series. The second inverter unit 122 is connected to the midpoint 121A of the first inverter unit 121 via a fifth connection line L150, and can receive a voltage VBD corresponding to the first control signal VB1 output by the first inverter unit 121.

[0075] In other words, the second inverter unit 122 turns on and off the second Hi-side switching element 122a and the second Low-side switching element 122b using the voltage VBD corresponding to the first control signal VB1 output by the first inverter unit 121, i.e., the stepped-down voltage VBD, to generate and output the second control signal VB2 whose level is shifted from the voltage VBD based on the first control signal VB1 to the value of the voltage Vout on the source electrode 20s side, which is the output side of the first N-type transistor 20. The second Hi-side switching element 122a can be a P-channel MOSFET transistor.

[0076] That is, the second Hi side switching element 122a has a gate electrode 122aa, a source electrode 122ab, and a drain electrode 122ac, and is set with a predetermined threshold voltage ΔVP2, more specifically, a gate threshold voltage ΔVP2 (hereinafter, the gate threshold voltage is simply referred to as the threshold voltage) (to be precise, the threshold voltage ΔVP2 is the absolute value of the threshold voltage ΔVP2). A voltage VBD corresponding to the first control signal VB1 from the first inverter unit 121 is input to the gate electrode 122aa as a gate voltage VBD.

[0077] That is, when the input drive voltage (gate voltage) VBD is smaller than the voltage Vout on the source electrode 20s side, which is the output side of the first N-type transistor 20, that is, the voltage VB' obtained by subtracting the threshold voltage ΔVP2 of the second Hi side switching element 122a from the input voltage Vout (source voltage) of the source electrode 122ab of the second Hi side switching element 122a, the second Hi side switching element 122a is turned on, and a predetermined current flows between the source electrode 122ab and the drain electrode 122ac. The voltage Vout (source voltage) on the source electrode 20s side, which is the output side of the first N-type transistor 20, is input to the source electrode 122ab via the connection line L140, and the voltage Vout (drain voltage) on the source electrode 20s side, which is the output side of the first N-type transistor 20, is output from the drain electrode 122ac as a voltage corresponding to the second control signal VB2. [Number 4] VB´=Vout-|ΔVP2|

[0078] The second low-side switching element 122b may be an N-channel MOSFET transistor. That is, the second low-side switching element 122b has a gate electrode 122ba, a drain electrode 122bb, and a source electrode 122bc, and is set with a predetermined threshold voltage ΔVN2, more specifically, a gate threshold voltage ΔVN1 (hereinafter, the gate threshold voltage is simply referred to as the threshold voltage) (the threshold voltage ΔVN2 is, to be precise, the absolute value of the threshold voltage ΔVN2). A voltage VBD corresponding to the first control signal VB1 from the first inverter unit 121 is input to the gate electrode 122ba as a gate voltage VBD.

[0079] That is, when the input gate voltage VBD is greater than the threshold voltage ΔVN2, the second Low side switching element 122b is turned on, and a predetermined current flows between the drain electrode 122bb and the source electrode 122bc. The drain electrode 122bb of the second Low side switching element 122b is connected to the drain electrode 122ac of the second High side switching element 122a via the connection line L143, and the source electrode 122bc of the second Low side switching element 122b is connected to the second connection line L120 via the connection line L144.

[0080] Here, in the second inverter section 122, when the second Hi side switching element 122a and the second Low side switching element 122b are both on and the voltage VB' is greater than the voltage VBD corresponding to the first control signal VB1 from the first inverter section 121, i.e., the gate voltage VBD, a large through current i2 may flow from the second Hi side switching element 122a to the second Low side switching element 122b.

[0081] On the other hand, when the voltage VB' is smaller than the voltage VBD corresponding to the first control signal VB1 from the first inverter section 121, i.e., the gate voltage VBD, the through current i2 is reduced even if the second Hi side switching element 122a and the second Low side switching element 122b are both on.

[0082] As shown in FIG. 13, the voltage VB′ is a maximum output VBD of the voltage VBD corresponding to the first control signal VB1 from the first inverter unit 121. MAX If the step-down setting unit 110 sets the step-down voltage and the threshold voltage ΔVP2 so that the through current i2 is smaller than the threshold voltage ΔVP2, a region in which the through current i2 is reliably reduced is formed.

[0083] For this reason, in this embodiment, as shown in Equation 5, the voltage VB' is a maximum output VBD of the voltage VBD corresponding to the first control signal VB1 from the first inverter unit 121. MAX The step-down setting unit 110 and the threshold voltage ΔVP2 are set so that the step-down setting is smaller than Vout (the voltage on the source electrode 20s side, which is the output side of the first N-type transistor 20, is Vout, and the maximum output of the voltage VBD corresponding to the first control signal VB1 output by the first inverter unit 121 is VBD MAX When the threshold voltage of the second Hi side switching element 121a is ΔVP2, VBD MAX It is preferable that the relationship Vout-ΔVP2 holds. [Number 5] VBD MAX >Vout-ΔVP2 Vout-ΔVP2=VB´

[0084] In this way, the voltage VB' is equal to the maximum output VBD of the voltage VBD corresponding to the first control signal VB1 from the first inverter unit 121. MAX By setting the step-down setting and the threshold voltage ΔVP2 so that the voltage VBD corresponding to the first control signal VB1 from the first inverter unit 121 is smaller than the voltage VB', it is possible to reliably form a region G in which the voltage VBD corresponding to the first control signal VB1 from the first inverter unit 121 is greater than the voltage VB', and the through current i2 generated in the second inverter unit 122 can be reduced.

[0085] In FIG. 13, the region G' of the voltage VBD where the through current i2 occurs is the range from the threshold voltage ΔVN2 of the second low-side switching element 122b to the voltage VB', and the region G of the voltage VBD where the through current i2 is reduced is the range from the voltage VB' to the maximum output VBD of the voltage VBD. MAX The through current i2 is also reduced in a region G'' where the voltage VBD corresponding to the first control signal VB1 from the first inverter unit 121 is equal to or lower than the threshold voltage ΔVN2, the second high-side switching element 122a is on, and the second low-side switching element 122b is off. In this embodiment, for example, the maximum output VBD of the voltage based on the first control signal VB1 MAXcan be set to 3.9V, the voltage based on the second control signal VB2, i.e., the voltage Vout on the source electrode 20s side, which is the output side of the first N-type transistor 20, can be set to 5V, the threshold voltage ΔVP2 of the second Hi side switching element 122a can be set to 1.3V, the threshold voltage ΔVN2 of the second Low side switching element 122b can be set to 1.3V, and the voltage VB' obtained by subtracting the threshold voltage ΔVP2 of the second Hi side switching element 122a from the voltage Vout on the source electrode 20s side, which is the output side of the first N-type transistor 20, can be set to 3.7V.

[0086] Here, it is preferable that the threshold voltage ΔVP2 of the second Hi side switching element 122a is set to be larger than the threshold voltage ΔVD of the step-down setting switching element 111. That is, in this embodiment, by providing the step-down voltage setting unit 110, the maximum output VBD of the voltage VBD corresponding to the first control signal VB1 output by the first inverter unit 121 is increased by 100% compared to the case where the step-down voltage setting unit 110 is not provided. MAX Therefore, a through current i2 is likely to occur in the second inverter unit 122. However, by making the threshold voltage ΔVP2 of the second Hi side switching element 122a larger than the threshold voltage ΔVD of the step-down setting switching element 111 (by making the threshold voltage ΔVD of the step-down setting switching element 111 smaller than the threshold voltage ΔVP2 of the second Hi side switching element 122a), in a case where the threshold voltage ΔVP2 and the threshold voltage ΔVD are made equal to each other, the maximum output VBD MAX This makes it possible to reliably increase the voltage VB' to a maximum output VBD of the voltage VBD corresponding to the first control signal VB1 output by the first inverter unit 121. MAX can be made smaller than

[0087] Furthermore, when the impurity concentrations (N-concentration) injected into the channel portions 111d, 122ad of the step-down setting switching element 111 and the second Hi side switching element 122a are made equal, it is preferable to make the dimensions of the second Hi side switching element 122a smaller than the dimensions of the step-down setting switching element 111, as shown in Fig. 14 (note that the impurity concentration (N-concentration) is the amount of impurity per unit capacity of the channel portions 111d, 122ad of the elements 111, 122a). This dimension can be the dimension of the channel widths W, w.

[0088] In other words, when the dimensions of the step-down setting switching element 111 and the second Hi side switching element 122a are equivalent, it is preferable to make the impurity concentration (N-concentration) of the channel portion 122ad of the second Hi side switching element 122a lower than the impurity concentration (N-concentration) of the channel portion 111d of the step-down setting switching element 111.

[0089] In other words, by making the channel width W of the second Hi side switching element 122 smaller than the channel width w of the step-down setting switching element 111 while making the impurity concentrations (N-concentration) of the step-down setting switching element 111 and the second Hi side switching element 122a equivalent, it is possible to reliably make the threshold voltage ΔVP2 of the second Hi side switching element 122 larger than the threshold voltage ΔVD of the step-down setting switching element 111.

[0090] In other words, by making the dimensions of the step-down setting switching element 111 and the second Hi side switching element 122a equivalent and making the impurity concentration (N-concentration) of the second Hi side switching element 122 lower than the impurity concentration (N-concentration) of the step-down setting switching element 111, it is possible to reliably make the threshold voltage ΔVP2 of the second Hi side switching element 122 higher than the threshold voltage ΔVD of the step-down setting switching element 111.

[0091] From another perspective, it is preferable to make the mutual conductance (gm) of the second Hi side switching element 122a smaller than the mutual conductance (gm) of the step-down setting switching element 111. This ensures that the threshold voltage ΔVP2 of the second Hi side switching element 122a is greater than the threshold voltage ΔVD of the step-down setting switching element 111.

[0092] In other words, as described above, by making the channel width W of the second Hi side switching element 122a smaller than the channel width w of the step-down setting switching element 111, or by making the impurity concentration (N-concentration) of the second Hi side switching element 122a lower than the impurity concentration (N-concentration) of the step-down setting switching element 111, the threshold voltage ΔVD of the step-down setting switching element 111 can be made lower than the threshold voltage ΔVP2 of the second Hi side switching element 122a.

[0093] This is because the mutual conductance (gm) of the step-down setting switching element 111 becomes relatively large and the current driving capability increases relatively, and when the second Hi side switching element 122a and the step-down setting switching element 111 are set to the same gate voltage, a larger current flows through the step-down setting switching element 111 which has a relatively large channel width w and a relatively large mutual conductance (gm). In other words, when the same current flows, the step-down setting switching element 111 which has a relatively large channel width w and a relatively large mutual conductance (gm) can lower the gate voltage.

[0094] [Example 1] Next, a first embodiment of the present invention will be described with reference to Fig. 15. The first embodiment of the present invention is an example of the step-down setting unit 110 and the first inverter unit 121, and assumes that the voltage Vout on the source electrode 20s side, which is the output side of the first N-type transistor 20, is 5V, the threshold voltage ΔVD of the step-down setting switching element 111 is 1.1V which is 0.1V lower than the normal threshold voltage of 1.2V, the step-down set voltage VBD is 3.9V, the threshold voltage ΔVP1 of the first Hi-side switching element 121a and the threshold voltage ΔVN1 of the first Low-side switching element 121b are 1.2V which is the same as the normal threshold voltage, and the maximum output VA of the input voltage VA from the external signal source A is 1.2V. MAX In this example, the voltage Vout on the source electrode 20s side, which is the output side of the first N-type transistor 20, is supplied at a constant voltage of 5 V.

[0095] In this embodiment 1, in the range (region F') from the threshold voltage of 1.2V of the first Low side switching element 121b to a voltage of 2.7V obtained by subtracting the threshold voltage of 1.2V of the first Hi side switching element 121a from the step-down set voltage of 3.9V, the through current i1 is generated. However, in the range (region F) from the voltage 2.7V obtained by subtracting the threshold voltage of 1.2V of the first Hi side switching element 121a from the step-down set voltage of 3.9V to the maximum output of 3.3V of the input voltage VA, the through current i1 is reduced.

[0096] [Comparative Example 1] Next, Comparative Example 1 of the present invention will be described with reference to Figures 16 and 17. Comparative Example 1 of the present invention is an example of the first inverter section 121 of the inverter circuit 100 that does not include the step-down setting section 110, and shows an example in which the voltage Vout (corresponding to the step-down set voltage VBD in Example 1) on the source electrode 20s side, which is the output side of the first N-type transistor 20, is 5V, the threshold voltage ΔVP1 of the first Hi-side switching element 121a and the threshold voltage ΔVN1 of the first Low-side switching element 121b are 1.2V, which is the same as the normal threshold voltage, and the maximum output of the input voltage VA from the external signal source A is 3.3V.

[0097] In this comparative example 1, the voltage of 3.8V obtained by subtracting the threshold voltage of 1.2V of the first Hi side switching element 121a from the voltage of 5V on the source electrode 20s side, which is the output side of the first N-type transistor 20, is greater than the maximum output of 3.3V of the input voltage VA from the external signal source A, and as a result, the region F of the input voltage VA in which the through current i1 is reduced is not formed.

[0098] [Example 2] Next, Example 2 of the present invention is shown in Fig. 15. Example 2 of the present invention is an example of the second inverter unit 122 following Example 1, in which the voltage Vout on the source electrode 20s side, which is the output side of the first N-type transistor 20, is set to 5V, the threshold voltage ΔVP2 of the second Hi-side switching element 122a and the threshold voltage ΔVN2 of the second Low-side switching element 122b are set to 1.3V (0.2V higher than the threshold voltage ΔVD of the step-down setting switching element 11) which is 0.1V higher than the normal threshold voltage, and the maximum output VBD of the voltage VBD corresponding to the first control signal VB1 output by the first inverter unit 121 is set to 0.0V. MAX In this example, the voltage Vout on the source electrode 20s side, which is the output side of the first N-type transistor 20, is 3.9 V.

[0099] In the second embodiment, a through current i2 occurs in a range (region G') from the threshold voltage 1.3V of the second low-side switching element 122b to a voltage 3.7V obtained by subtracting the threshold voltage 1.3 from the voltage 5V on the source electrode 20s side, which is the output side of the first N-type transistor 20. However, in a range from the voltage 3.7V obtained by subtracting the threshold voltage 1.3V of the second high-side switching element 122a from the voltage 5V on the source electrode 20s side, which is the output side of the first N-type transistor 20, MAX In the range up to 3.9 V (region G'), the through current i2 is reduced.

[0100] [Comparative Example 2] Next, Comparative Example 2 of the present invention will be described with reference to Fig. 16. Comparative Example 2 of the present invention illustrates an example in which the threshold voltage ΔVD of the step-down setting switching element 111 and the threshold voltage ΔVP2 of the second Hi side switching element 121a in Example 2 are both set to be equal to 1.2V.

[0101] In this comparative example 2, the voltage obtained by subtracting the threshold voltage of 1.2V of the second Hi side switching element 122a from the voltage 5V on the source electrode 20s side, which is the output side of the first N-type transistor 20, is 3.8V, and the maximum output of the voltage VBD corresponding to the first control signal VB1 output by the first inverter unit 121 is also 3.8V. As a result, the maximum output of the voltage VBD is 3.8V and the voltage obtained by subtracting the threshold voltage of the second Hi side switching element 122a, 1.2V from the voltage 5V on the source electrode 20s side, which is the output side of the first N-type transistor 20, 3.8V are equal, and the region G of the voltage VBD in which the through current i2 is reduced is not formed.

[0102] <Effect of the configuration corresponding to claim 5> As described above, according to the present invention, the boost unit 30 of the regulator circuit 1 boosts the input voltage Vin from the power source 10 to generate the first drive voltage Vg for the first N-type transistor 20, and the first control unit 40 adjusts the first drive voltage Vg based on the output voltage of the first N-type transistor 20, and performs control to maintain the drive voltage level of the first N-type transistor 20 at a predetermined value. This makes it possible to provide a low-saturation regulator circuit that can operate stably and has a simple configuration, and the step-down setting unit 110 of the inverter circuit 100 supplies the inverter unit 120 with the voltage VBD obtained by stepping down the output voltage Vout of the first N-type transistor 20, and the inverter unit 120 stably outputs control signals that turn on and off the Hi-side switching element 120a and the Low-side switching element 120b in response to the input voltage VA input from the signal source A to output the control signals VB1 and VB2 based on the step-down set voltage VBD, thereby improving the performance of the inverter circuit 120.

[0103] Further, the step-down setting unit 110 supplies the inverter unit 120 with a voltage VBD obtained by stepping down the voltage Vout on the source electrode 20s side, which is the output side of the first N-type transistor 20. The inverter unit 120 has a Hi side switching element 120a and a low side switching element 120b, and outputs control signals VB1, VB2 that are level-shifted to an intermediate voltage value VBD between the input voltage VA input from the signal source A and the voltage Vout on the source electrode 20s side, which is the output side of the first N-type transistor 20, based on the step-down set voltage VBD by turning on and off the Hi side switching element 120a and the low side switching element 120b in accordance with the input voltage VA input from the signal source A. In this way, the voltage Vout on the source electrode 20s side, which is the output side of the first N-type transistor 20, is stepped down and supplied to the inverter unit 120, thereby making it possible to reduce the through currents i1, i2 generated in the inverter unit 120.

[0104] Furthermore, the step-down setting unit 110 has a step-down setting switching element 111, and by turning on the step-down setting switching element 111, it can supply to the inverter unit 120 a voltage VBD obtained by stepping down the voltage Vout on the source electrode 20s side, which is the output side of the first N-type transistor 20, by the threshold voltage ΔVD of the step-down setting switching element 111, and can supply to the inverter unit 120 a voltage VBD obtained by stepping down the voltage Vout on the source electrode 20s side, which is the output side of the first N-type transistor 20, by the threshold voltage ΔVD.

[0105] Furthermore, the step-down setting unit 110 supplies a voltage VBD obtained by stepping down the voltage Vout on the source electrode 20s side, which is the output side of the first N-type transistor 20, to the first inverter unit 121. The first inverter unit 121 has a first Hi-side switching element 121a and a first low-side switching element 121b, and outputs a first control signal VB1 that is level-shifted to an intermediate voltage value between the input voltage VA input from the signal source A and the voltage Vout on the source electrode 20s side, which is the output side of the first N-type transistor 20, based on the step-down-set voltage VBD by turning on and off the first Hi-side switching element 121a and the first low-side switching element 121b in accordance with the input voltage VA input from the signal source A. The second inverter unit 122 has a second Hi-side switching element 122a and a second low-side switching element 122b, and By turning on and off the second Hi-side switching element 122a and the second Low-side switching element 122b by inputting the first control signal VB1 and outputting the second control signal VB2 which is level-shifted to the value of the voltage Vout on the source electrode 20s side which is the output side of the first N-type transistor 20 with respect to the voltage VBD based on the first control signal VB1, a control signal VB2 is generated in which the input voltage VA input from the signal source A via the first inverter unit 121 and the second inverter unit 122 is shifted to the value of the voltage Vout on the source electrode 20s side which is the output side of the first N-type transistor 20, and the voltage Vout on the source electrode 20s side which is the output side of the first N-type transistor 20 is stepped down and supplied to the first inverter unit 121 and the second inverter unit 122, thereby reducing the through currents i1, i2 generated in the first inverter unit 121 and the second inverter unit 122.

[0106] Furthermore, the voltage set by the step-down setting unit 110 is set to VBD, and the maximum output of the input voltage VA is set to VA MAX When the threshold voltage of the first Hi-side switching element 121a is ΔVP1, VA MAX>By establishing the relationship of VBD-ΔVP1, the voltage VBD' obtained by subtracting the threshold voltage ΔVP1 of the first Hi-side switching element 121a of the first inverter unit 121 from the voltage VBD set by the step-down setting unit 10 is set to the maximum output VA of the input voltage VA. MAX , and the through current i1 occurring in the first inverter section 121 can be reduced.

[0107] In addition, the voltage on the source electrode 20s side, which is the output side of the first N-type transistor 20, is designated as Vout, and the maximum output of the voltage VBD corresponding to the first control signal VB1 outputted by the first inverter unit 121 is designated as VBD MAX When the threshold voltage of the second Hi-side switching element 122a is ΔVP2, VBD MAX >Vout-ΔVP2 is established, the voltage VB' obtained by subtracting the threshold voltage ΔVP2 of the second Hi-side switching element 122a of the second inverter section 122 from the voltage Vout on the source electrode 20s side, which is the output side of the first N-type transistor 20, is the maximum output VBD of the voltage VBD corresponding to the first control signal VB1. MAX , and the through current i2 occurring in the second inverter section 122 can be reduced.

[0108] Furthermore, by making the threshold voltage ΔVP2 of the second Hi-side switching element 122a larger than the threshold voltage ΔVD of the step-down setting switching element 11, the maximum output VBD of the voltage VBD corresponding to the first control signal VB1 output by the first inverter unit 121 is MAX Therefore, the voltage VB' obtained by subtracting the threshold voltage ΔVP2 of the second Hi-side switching element 122a from the voltage Vout on the source electrode 20s side, which is the output side of the first N-type transistor 20, can be reliably set to the maximum output VBD of the voltage VBD corresponding to the first control signal VB1 output by the first inverter unit 121. MAX can be made smaller than

[0109] Furthermore, by making the mutual conductance of the second Hi side switching element 122a smaller than the mutual conductance of the step-down setting switching element 111, the threshold voltage ΔVP2 of the second Hi side switching element 122a can be reliably made larger than the threshold voltage ΔVD of the step-down setting switching element 111.

[0110] Furthermore, by making the dimensions of the second Hi side switching element 122a smaller than the dimensions of the step-down setting switching element 111, the threshold voltage ΔVP2 of the second Hi side switching element 122a can be reliably made larger than the threshold voltage ΔVD of the step-down setting switching element 111.

[0111] Furthermore, by making the impurity concentration (N-concentration) of the second Hi side switching element 122a lower than the impurity concentration (N-concentration) of the step-down setting switching element 11, the threshold voltage ΔVP2 of the second Hi side switching element 122a can be reliably made higher than the threshold voltage ΔVD of the step-down setting switching element 111.

[0112] <Modification of the configuration corresponding to claim 5> It is needless to say that the inverter circuit 100 of the present invention is not limited to the above-described embodiment, and various modifications and applications are possible within the scope of the invention.

[0113] That is, in the embodiment of the inverter circuit 100 described above, the step-down setting unit 110 turns on the step-down setting switching element 111 to supply to the inverter unit 120 a voltage VBD obtained by stepping down the voltage Vout on the source electrode 20s side, which is the output side of the first N-type transistor 20, by the threshold voltage ΔVD of the step-down setting switching element 111; however, the desired effect can also be achieved by stepping down the voltage Vout on the source electrode 20s side, which is the output side of the first N-type transistor 20, by using various resistors or other means instead of the step-down setting switching element 111.

[0114] In the embodiment of the inverter circuit 100 described above, the voltage VB′ obtained by subtracting the threshold voltage ΔVP1 of the first Hi-side switching element 121a of the first inverter unit 121 from the voltage VBD set by the step-down setting unit 110 is equal to the maximum output VA of the input voltage VA. MAX The step-down setting by the step-down setting unit 110 and the threshold voltage ΔVP1 of the first Hi-side switching element 121a are set so that the maximum output VA of the input voltage VA is smaller than the voltage VBD set only by the step-down setting unit 110. MAX It may be possible to set the value to be smaller than .

[0115] In other words, the voltage VBD' obtained by subtracting the threshold voltage ΔVP1 of the first Hi-side switching element 121a from the stepped-down voltage VBD is equal to the maximum output VA of the input voltage VA. MAX As long as the step-down setting unit 110 at least sets the step-down voltage so that the step-down voltage is smaller than the threshold voltage, a desired effect can be achieved.

[0116] Furthermore, in the embodiment of the inverter circuit 100 described above, the voltage VB′ obtained by subtracting the threshold voltage ΔVP2 of the second Hi-side switching element 122a from the voltage Vout on the source electrode 20s side, which is the output side of the first N-type transistor 20, is equal to the maximum output VBD of the voltage corresponding to the first control signal VB1 output by the first inverter unit 121. MAX However, the voltage VB′ obtained by subtracting the threshold voltage ΔVP2 of the second Hi side switching element 122a from the voltage Vout on the source electrode 20s side, which is the output side of the first N-type transistor 20, due only to the voltage buck setting by the voltage buck setting unit 110 is smaller than the maximum output VBD of the voltage corresponding to the first control signal VB1 output by the first inverter unit 121. MAX It may be possible to set the value to be smaller than .

[0117] That is, the voltage VB′ obtained by subtracting the threshold voltage ΔVP2 of the second Hi-side switching element 122a from the voltage Vout on the source electrode 20s side, which is the output side of the first N-type transistor 20, is equal to the maximum output VBD of the voltage corresponding to the first control signal VB1 output by the first inverter unit 121. MAX As long as the step-down setting unit 110 at least sets the step-down voltage so that the step-down voltage is smaller than the threshold voltage, a desired effect can be achieved.

[0118] Furthermore, in the above-described embodiment, the threshold voltage ΔVP1 of the first Hi side switching element 121a and the threshold voltage ΔVN1 of the first Low side switching element 121b are set to be equivalent, and the threshold voltage ΔPN2 of the second Hi side switching element 122a and the threshold voltage ΔVN2 of the second Low side switching element 122b are set to be equivalent, but they may be set to different threshold voltages.

[0119] Furthermore, in the above-described embodiment, the signal source A is an external signal source A, but the same technical effect can be achieved even if the signal source A is an internal signal source A.

[0120] In the above, the maximum output voltage VA of the input voltage from the external signal source A is MAX The embodiment in which the input voltage is set to 3.3V has been described, but the maximum output VA MAX Of course, it can be used in the same way even when the voltage exceeds 3.3V, such as when the input voltage is 5V. MAX When the voltage exceeds 3.3 V, the shoot-through current can be further suppressed, which is an even more preferable embodiment.

[0121] That is, for example, an external signal source A formed of a microcomputer often has an input voltage VA of 3.3 V or 5 V, but the inverter circuit 100 of the present invention can accommodate any input voltage VA without changing or selecting the circuit, making it a user-friendly inverter circuit 100. Also, the input voltage VA may be accompanied by unintended fluctuations such as noise, but even in such cases, the through currents i1 and i2 can be effectively suppressed.

[0122] <Configuration corresponding to claim 6> 20 is a circuit diagram showing the configuration of another inverter circuit according to an embodiment of the present invention, FIG. 21 is a circuit diagram showing the details of the configuration of the change-over switch in the inverter circuit, FIG. 22 is a timing chart for explaining the operation of the inverter circuit and a diagram showing the capacitor voltage, FIG. 23 is a circuit diagram showing a state in which the Hi side switching element is on, the Low side switching element is off, and the change-over switch is off in the inverter circuit, FIG. 24 is a circuit diagram showing details of the state of the change-over switch in FIG. 23, FIG. 25 is a circuit diagram showing a state in which the Hi side switching element is on, the Low side switching element is off, and the change-over switch is on in the inverter circuit, FIG. 26 is a circuit diagram showing details of the state of the change-over switch in FIG. 25, and FIG. 27 is a circuit diagram showing a state in which the Hi side switching element is off, the Low side switching element is on, and the change-over switch is on in the inverter circuit.

[0123] With reference to FIG. 20, another inverter circuit 200 according to an embodiment of the present invention will be described.

[0124] The inverter circuit 200 is an inverter circuit 200 including a regulator circuit 1, and includes an inverter unit 210, a first power source 221, a second power source 222, a first capacitor 241, a second capacitor 242, a changeover switch 250, and a pulse generator 270. The inverter unit 210 has a Hi-side switching element 211 and a Low-side switching element 212. The first power source 221 supplies a first voltage to the inverter unit 210. The second power source 222 supplies a second voltage to the changeover switch 250. The first capacitor 241 supplies a drive voltage to drive the Hi-side switching element 211, the second capacitor 242 supplies a voltage to the first capacitor 241, the change-over switch 250 switches between charging and discharging the second capacitor 242 by turning it on and off, and the pulse generator 270 generates a pulse-shaped control signal for controlling the Hi-side switching element 211, the Low-side switching element 212, and the change-over switch 250 based on the voltage Vout on the output side of the N-type transistor 20.

[0125] More specifically, the inverter circuit 200 includes the above-mentioned regulator circuit 1. The inverter circuit 200 further includes an inverter unit 210, a first power source 221, a second power source 222, a first capacitor 241, a second capacitor 242, and a changeover switch 250. The first power source 221 supplies a first voltage V1 to the inverter unit 210. The second power source 222 supplies a second voltage V2 to the changeover switch 250 and also supplies the second voltage V2 to the second capacitor 242 via the changeover switch 250 to discharge the second capacitor 242. The first capacitor 241 supplies a first voltage V1 to the inverter unit 210. The inverter unit 210 supplies a voltage (V2-Vf91) due to discharging to the first capacitor 241, the second capacitor 242 supplies a voltage (V1-Vf93+V2) due to discharging of the second capacitor 242 to the first capacitor 241, the first capacitor 241 discharges while charging with the voltage (V1-Vf93+V2) due to discharging of the second capacitor 242, the changeover switch 250 switches between charging and discharging of the second capacitor 242 by turning on and off, and the second voltage V2 from the second power supply 222 is configured to be relatively lower than the first voltage V1 from the first power supply 221. In this embodiment, the inverter unit 210, the second power supply 222, and the first capacitor 241 configure a bootstrap circuit, and the first power supply 221, the second capacitor 242, and the changeover switch 250 configure a charge pump.

[0126] The inverter unit 210 has a high-side switching element 211 and a low-side switching element 212. The inverter unit 210 has a drive circuit 230, and the drive circuit 230 has a high-side drive circuit 231 that drives the high-side switching element 211 and a low-side drive circuit 232 that drives the low-side switching element 212. The high-side drive circuit 231 and the low-side drive circuit 232 can output drive voltages for turning on the high-side switching element 211 and the low-side switching element 212.

[0127] The inverter circuit 200 has a pulse generator 270, which can output pulse-like control signals 270A, 270B, and 270C to the Hi side drive circuit 231, the Low side drive circuit 232, and the change-over switch 250 based on the voltage Vout on the source electrode 20s side, which is the output side of the first N-channel MOSFET transistor 20 (the pulse generator 270 can be configured with a microcomputer, for example, and can output pulse-like control signals 270A, 270B, and 270C of 0V to 5V). The inverter circuit 200 is configured to supply the current output from the inverter unit 210 to the load 260 via an inductance 280.

[0128] The inverter circuit 200 is configured by electrically connecting a high side switching element 211, a low side switching element 212, a first power supply 221, a second power supply 222, a high side driving circuit 231, a low side driving circuit 232, a first capacitor 241, a second capacitor 242, a changeover switch 250, a pulse generator 270, and an inductance 280 by connection lines L201 to L221. The inverter circuit 200 has a control circuit 200A, and the control circuit 200A includes the high side driving circuit 231, the low side driving circuit 232, the changeover switch 250, the pulse generator 270, a level shift circuit 271, a flip-flop 272, and a voltage detector 273.

[0129] That is, the connection line L201 connects the first power supply 221 and the Hi side switching element 211. The Hi side switching element 211 is configured with an N-channel type MOSFET transistor, and the connection line L201 connects the first power supply 221 and the drain electrode 211d of the Hi side switching element 211.

[0130] The connection line L202 connects in series the high-side switching element 211 and the low-side switching element 212. The low-side switching element 212 is configured with an N-channel type MOSFET transistor, and the connection line L202 connects a source electrode 211s of the high-side switching element 211 and a drain electrode 212d of the low-side switching element 212.

[0131] The connection line L203 connects the source electrode 212s of the low-side switching element 212 and the ground G1.

[0132] The connection line L204 connects the midpoint L202A between the source electrode 211s of the high-side switching element 211 and the drain electrode 212d of the low-side switching element 212 in the connection line L202 to the inductance 280.

[0133] The connection line L205 connects a midpoint L204A of the connection line L204 (that is, a midpoint L204A between the midpoint L202A of the connection line L202 and the inductance 280) to one end 241a of the first capacitor 241.

[0134] The connection line L206 connects the other end 241b of the first capacitor 241 and the second power supply 222. A first diode 291 is provided in the connection line L206, and the first diode 291 can prevent a current based on the first voltage V1 of the first power supply 221 from flowing back to the second power supply 222 via the connection lines L201, L202 (the connection line L202 from the Hi side switching element 211 to the midpoint L202A), L204 (the connection line L204 from the midpoint L202A to the midpoint L204A), L205, and the first capacitor 241 (the voltage drop of the first diode 291 is Vf91).

[0135] The connection line L207 connects the midpoint L206A between the other end 241b of the first capacitor 241 and the second power supply 222 in the connection line L206, and the Hi side drive circuit 231.

[0136] The connection line L208 connects the Hi-side driver circuit 231 and the gate electrode 211g of the Hi-side switching element 211.

[0137] The connection line L209 connects the Hi side driving circuit 231 and a midpoint L202A of the connection line L202.

[0138] The connection line L210 connects the second power supply 222 and the low-side driving circuit 232.

[0139] The connection line L211 connects the low-side driver circuit 232 and the gate electrode 212g of the low-side switching element 212.

[0140] The connection line L212 connects the low-side drive circuit 232 to a midpoint L203A between the source electrode 212s of the low-side switching element 212 on the connection line L203 and the ground G1.

[0141] The connection line L13 connects the midpoint L206B between the second power supply 222 and the midpoint L206A in the connection line L206 to the changeover switch 250. As shown in FIG. 21, the changeover switch 250 is configured with a half-bridge inverter circuit (CMOS), in which a P-channel MOSFET transistor 251 as a Hi-side switching element and an N-channel MOSFET transistor 252 as a Low-side switching element are connected in series. That is, when the input side of the changeover switch 250 is Hi, the output side is Low, and when the input side is Low, the output side is Hi. The connection line L213 connects the midpoint L206B to the source electrode 251s of the P-channel MOSFET transistor 251 in the changeover switch 250.

[0142] The connection line L214 connects the drain electrode 251d of the P-channel MOSFET transistor 251 and the drain electrode 252d of the N-channel MOSFET transistor 252 in the changeover switch 250 in series.

[0143] The connection line L215 connects the source electrode 252s of the N-channel MOSFET transistor 252 in the changeover switch 250 to the ground G2.

[0144] The connection line 216 connects a midpoint L214A between the drain electrode 251d of the P-channel MOSFET transistor 251 and the drain electrode 252d of the N-channel MOSFET transistor 252 in the connection line L214 and one end 242a of the second capacitor 242.

[0145] The connection line L217 connects the other end 242b of the second capacitor 242 and a midpoint L206C between the midpoint L206A and the midpoint L206B of the connection line L206. The connection line L217 is provided with a second diode 292 (the voltage drop of the second diode 292 is Vf92), and the second diode 292 has a function of rectifying a current based on the voltage (V1-Vf93+V2) caused by the discharge of the second capacitor 242 so that the current based on the voltage (V1-Vf93+V2) caused by the discharge of the second capacitor 242 flows to the first capacitor 241 (the second diode 292 can also prevent a current based on the voltage (V2-Vf91) caused by the discharge of the first capacitor 241 from flowing back to the second capacitor 242).

[0146] The connection line L218 connects a midpoint L217A between the other end 242b of the second capacitor 242 and the midpoint L206C in the connection line L217, and a midpoint L204B between the midpoint L204A in the connection line L204 and the inductance 280. A third diode 293 (the voltage drop of the third diode 293 is Vf93) is provided in the connection line L218, and the third diode 293 can prevent a current based on the voltage (V1-Vf93+V2) due to the discharge of the second capacitor 242 from flowing back into the connection line L204.

[0147] The connection line L219 connects the pulse generator 270 and the Hi side driver circuit 231 via a level shift circuit 271, a flip-flop 272, and a voltage detector 273.

[0148] The connection line L220 connects the pulse generator 270 and the low-side driver circuit 232.

[0149] The connection line L221 connects the pulse generator 270 and the changeover switch 250. More specifically, the connection line L221 connects the pulse generator 270 and a gate electrode 251g of the P-channel MOSFET transistor 251 and a gate electrode 252g of the N-channel MOSFET transistor 252 in the changeover switch 250.

[0150] The inverter circuit 200 of the present invention thus configured can be operated as shown in Figures 22 to 27. In Figures 22 to 27, the flow of current is indicated by dotted arrows, Figure 23 is a circuit diagram corresponding to time T2 in Figure 22, Figure 25 is a circuit diagram corresponding to time T1 in Figure 22, and Figure 27 is a circuit diagram corresponding to time T3 in Figure 22.

[0151] As shown in Figures 22(a), (b), and (c), first, a pulse generator 270 generates pulse-shaped control signals 270A, 270B, and 270C based on the voltage Vout on the source electrode 20s side, which is the output side of the first N-channel MOSFET transistor 20.

[0152] That is, as shown in FIG. 23, the control signal 270A is output to the Hi side driving circuit 231 via the connection line L219, the control signal 270B is output to the Low side driving circuit 232 via the connection line L220, and the control signal 270C is output to the changeover switch 250 via the connection line L221.

[0153] That is, the Hi side drive circuit 231 inputs the control signal 270A via connection line L219. Furthermore, the Hi side drive circuit 231 inputs the voltage (V2-Vf91) resulting from the discharge of the first capacitor 241 as a drive voltage via connection lines L206 (connection line L206 from the other end 241b of the first capacitor 241 to the midpoint L206A) and L207. As a result, a gate voltage (V1+V2-Vf91) is output from the Hi side drive circuit 231 to the gate electrode 211g of the Hi side switching element 211 via connection line L208.

[0154] Due to the output of this gate voltage (V1+V2-Vf91), the Hi-side switching element 211 turns on, and a current based on the first voltage V1 of the first power supply 221 flows between the source electrode 211s and the drain electrode 211d.

[0155] When the Hi-side drive circuit 231 receives the control signal 270A, the Low-side switching element 232 is turned off. This allows the current flowing between the source electrode 211s and the drain electrode 211d to be supplied to the load 260 via the connection line L202 (the connection line L202 extending from the source electrode 211s of the Hi-side switching element 211 to the midpoint L202A), the connection line L204, and the inductance 280.

[0156] Furthermore, when the Hi side driver circuit 231 receives the control signal 270A, the control signal 270C is output intermittently to the changeover switch 250 via the connection line L221, and the changeover switch 250 repeatedly turns on and off alternately.

[0157] As a result, the second capacitor 242 can alternately discharge and charge while the first capacitor 241 is supplying the discharged voltage (V2-Vf91) to the inverter unit 210 as a driving voltage, and can supply the first capacitor 241 with the voltage (V1-Vf93+V2) generated by the discharge of the second capacitor 242 by discharging.

[0158] More specifically, when the first capacitor 241 supplies a discharged voltage (V2-Vf91) as a drive voltage to the Hi side drive circuit 211 of the inverter section 210 to turn on the Hi side switching element 211, and when the change-over switch 250 is not inputting the control signal 270C (when the input side of the change-over switch is Low), this is the state of t2 in FIG. 22, and as shown in FIG. 24, the P-channel MOSFET transistor 251 of the change-over switch 250 is ON and the N-channel MOSFET transistor 252 is OFF, and the output side of the change-over switch 250 is Hi. As a result, as shown in FIG. 23, an electric path is formed from the second power source 222, the connection line L206 (the connection line L206 from the second power source 222 to the midpoint L206B), the connection line L213, the changeover switch 250, the connection line L216, the second capacitor 242, the connection line L217, and the connection line L206 (the connection line L206 from the midpoint L206C to the other end 241b of the first capacitor 241). As shown in FIGS. 22(d), (e), (f), and (g), The discharge of the capacitor 242 is performed based on the second voltage (V1-Vf93+V2) while the Hi side switching element 211 is on and while the changeover switch 250 is on, and the voltage (V1-Vf93+V2) due to the discharge of the second capacitor 242 is supplied to the first capacitor 241 (in this state, the third diode 293 operates to prevent a current based on the voltage (V1-Vf93+V2) due to the discharge of the second capacitor 242 from flowing back to the connection line L204). This allows the first capacitor 241 to be discharged while being charged (the changeover switch 250 being on means that the input side of the changeover switch 250 is Low and the output side is Hi).

[0159] On the other hand, when the first capacitor 241 supplies the discharged voltage (V2-Vf91) as a drive voltage to the Hi side drive circuit 211 of the inverter section 210 to turn on the Hi side switching element 211, and the change-over switch 250 inputs the control signal 270C (when the input side of the change-over switch is Hi), the state is t1 in Figure 22, and becomes the state shown in Figures 25 and 26.

[0160] That is, as shown in Fig. 26, the P-channel MOSFET transistor 251 of the changeover switch 250 is turned off and the N-channel MOSFET transistor 252 is turned on, and the output side of the changeover switch 250 becomes Low. As a result, as shown in Fig. 25, an electric path is formed from the first power supply 221, the connection line L1, the Hi-side switching element 211, the connection line L202 (the connection line L202 from the Hi-side switching element 211 to the midpoint L202A), the connection line L204, the connection line L218, the connection line L217 (the connection line L217 from the midpoint L217A to the second capacitor 242), the second capacitor 242, the connection line L216, the changeover switch 250, the connection line L215, to the ground G2, and the second capacitor 242 is charged as shown in Figs. 22(d), (e), (f), and (g). That is, the second capacitor 242 is charged based on the first voltage V1 from the first power source 221 while the Hi side switching element 211 is on and while the changeover switch 250 is off (when the changeover switch 250 is off, the input side of the changeover switch 250 is in a Hi state and the output side is in a Low state). The changeover switch 250 is not directly connected to the first power source 221. More specifically, the changeover switch 250 and the first power source 221 are connected to the first power source 221 via the second capacitor 242, and a voltage after charging by the second capacitor 242 based on the first voltage V1 from the first power source 221 is supplied to the changeover switch 250.

[0161] The control signal 270A from the pulse generator 270 is input to the Hi side drive circuit 231 via a level shift circuit 271, a flip-flop 272, and a voltage detector 273. In other words, when the voltage detector 273 detects that the voltage (V2-Vf91) due to the discharge of the first capacitor 241 is equal to or greater than a predetermined value, the voltage of 41V due to the discharge is sufficient to charge the gate electrode 211g of the Hi side switching element 211, and the control signal 270A from the pulse generator 270 is set by the flip-flop 272 and sent to the Hi side drive circuit 231. On the other hand, when the voltage detector 273 detects that the voltage (V2-Vf91) due to the discharge of the first capacitor 241 is below a predetermined value, the voltage (V2-Vf91) due to the discharge is insufficient to charge the gate electrode 211g of the Hi side switching element 211, and the control signal 270A from the pulse generator 270 is reset by the flip-flop 272 and is not sent to the Hi side drive circuit 231.

[0162] The low-side driving circuit 232 also inputs a control signal 270B via the connection line L220. Furthermore, the low-side driving circuit 232 inputs a second voltage V2 of the second power supply 222 via the connection line L210. As a result, a gate voltage (V2) is output from the low-side driving circuit 232 to the gate electrode 212g of the low-side switching element 212 via the connection line L211. The output of this gate voltage (V2) turns on the low-side switching element 212, and the drain electrode 212d and the source electrode 212s become conductive.

[0163] When the Low-side drive circuit 232 receives the control signal 270B, the Hi-side switching element 231 is turned off (state of t3 in FIG. 22). As a result, as shown in FIG. 27, an electric path is formed that extends from the second power supply 222, the connection line L206, the first capacitor 241, the connection line L205, the connection line L204 (the connection line L204 extending from the midpoint L204A to the midpoint L202A), the connection line L202 (the connection line L202 extending from the midpoint L202A to the Low-side switching element 212), the connection line L203, and the ground G1, and the first capacitor 241 is charged as shown in FIG. 22(e).

[0164] When the Low-side drive circuit 232 receives the control signal 270B, the changeover switch 250 continues to receive the control signal 270C, the input side is in a Hi state, and the output side is in a Low state, the P-channel MOSFET transistor 251 is off, and the N-channel MOSFET transistor is on. In this state, the Hi-side switching element 211 is off, and therefore the second capacitor 242 is not charged (the third diode acts to prevent the current based on the voltage (V1-Vf93+V2) due to the discharge of the second capacitor 242 from flowing back to the connection line L204).

[0165] <Effect of the configuration corresponding to claim 6> As described above, according to the present invention, the boost unit 30 of the regulator circuit 1 boosts the input voltage Vin to generate the first drive voltage Vg for the first N-type transistor 20, and the first control unit 40 adjusts the first drive voltage Vg based on the output voltage of the first N-type transistor 20, and performs control to maintain the drive voltage level of the first N-type transistor 20 at a predetermined value. This makes it possible to provide a low-saturation regulator circuit that is capable of stable operation and has a simple configuration. By supplying power from this low-saturation regulator circuit to the pulse generator 270, the pulse generator 270 can generate a stable pulse voltage and supply it to the Hi-side switching element 211, the Low-side switching element 212, and the change-over switch 250.

[0166] The first power supply 221 supplies a first voltage to the inverter unit 210, the second power supply 222 supplies a second voltage to the changeover switch 250, the first capacitor 241 supplies a drive voltage Vg that drives the Hi-side switching element 211, the second capacitor 242 supplies a voltage to the first capacitor 241, the changeover switch 250 switches between charging and discharging the second capacitor 242 by turning on and off, and the pulse generator 270 generates a pulse-shaped control signal for controlling the Hi-side switching element 120a, the Low-side switching element 120b, and the changeover switch 250 based on the voltage Vout on the output side of the first N-type transistor 20. In this way, the performance of the inverter circuit 1 can be improved.

[0167] Moreover, according to the inverter circuit 200 of the present invention, the first power supply 221 supplies the first voltage V1 to the inverter section 210, the second power supply 222 supplies the second voltage V2 to the change-over switch 250, the first capacitor 241 supplies a drive voltage that drives the inverter section 210, and the second capacitor 242 supplies a voltage (V1-Vf93+V2) to the first capacitor 241. By switching the change-over switch 250 on and off to switch between charging and discharging the second capacitor 242, it becomes possible for the second capacitor 242 to charge in a manner that supplements the first capacitor 241, and the operation of turning off the Hi side switching element 211 can be reduced.

[0168] Furthermore, the second capacitor 242 alternately discharges and charges, and supplies a voltage (V1-Vf93+V2) to the first capacitor 241 by discharging. Therefore, while the first capacitor 241 supplies the discharged voltage (V2-Vf91) to the inverter unit 210, the second capacitor 242 can charge in a manner that adds to the first capacitor 241 while maintaining the discharged voltage (V1-Vf93+V2).

[0169] Furthermore, the second capacitor 242 is charged based on the first voltage V1 while the Hi side switching element 211 is on, thereby enabling coordination of charging and discharging with the first capacitor 241, which is charged and discharged based on the first voltage V1.

[0170] Furthermore, since the second capacitor 242 is discharged based on the second voltage V2 while the changeover switch 250 is on, the second capacitor 242 can charge the first capacitor 241 while securing the voltage (V1-Vf93+V2) due to discharge even without the supply of the voltage V1 from the first power supply 221. The capacity of this charge can be adjusted by changing the performance and capacity of the changeover switch 250, such as the switching speed (switching frequency).

[0171] Furthermore, since the second voltage V2 is relatively lower than the first voltage V1, a relatively low voltage is supplied to the changeover switch 250 that switches between charging and discharging the second capacitor 242, thereby preventing the changeover switch 250 from withstanding high voltages and reducing switching noise.

[0172] That is, the changeover switch 250 often operates at high frequencies, which can cause noise. However, in an inverter circuit 200 that requires high voltage, such as for an EV (electric vehicle) motor, as the changeover switch 250 becomes more highly voltage resistant, the frequency of the changeover switch 250 becomes even higher, which can cause a problem of even greater switching noise.

[0173] Furthermore, since the changeover switch 250 is not directly connected to the first power supply 221, a relatively low voltage can be supplied to the changeover switch 250, which prevents the changeover switch 250 from withstanding high voltages and also reduces switching noise.

[0174] That is, by connecting the changeover switch 250 and the first power supply 221 via at least the second capacitor 242, the changeover switch 250 can supply a relatively high first voltage V1 of the first power supply 221 after charging by the second capacitor 242, and so on. This makes it possible to supply a relatively low voltage to the changeover switch 250, thereby preventing the changeover switch 250 from becoming a high voltage withstand switch, reducing switching noise, and enabling the first capacitor 241 and the second capacitor 242 to be linked in charge and discharge (the changeover switch 250 and the first power supply 221 are connected via the second capacitor 242, the third diode 293, and the Hi side switch 211, but the above-mentioned effects can be achieved by connecting the changeover switch 250 and the first power supply 221 via at least the second capacitor 242).

[0175] <Modification of the configuration corresponding to claim 6> It should be noted that the inverter circuit 200 of the present invention is not limited to the above-described embodiment, and various modifications and applications are possible without departing from the spirit and scope of the invention.

[0176] For example, in the embodiment of the inverter circuit 200 described above, the inverter unit 210 includes the Hi-side switching element 211 and the Low-side switching element 212, and supplies the voltage (V2-Vf91) resulting from the discharge of the first capacitor 241 to the Hi-side drive circuit 231 of the Hi-side switching element 211, but for example, the inverter unit 210 may be configured with other switching elements, and the voltage (V2-Vf91) resulting from the discharge of the first capacitor 241 may be supplied to the inverter unit 210. In other words, the first capacitor 241 may include various modified examples and application examples related to the inverter unit 210, so long as it is configured to simply supply the voltage (V2-Vf91) resulting from the discharge to the inverter unit 210 as a drive voltage.

[0177] In addition, the changeover switch 250 is a half-bridge inverter circuit having a P-channel MOSFET transistor 251 and an N-channel MOSFET transistor 252, but is not limited to this configuration and may include various types of switches as long as they switch the charging and discharging of the second capacitor 242 by turning them on and off.

[0178] 28, a resistor 295 may be provided between the midpoint L217A and the second capacitor 242. This makes it possible to adjust the current value of the second capacitor 242.

[0179] Furthermore, in the embodiment of the inverter circuit 200 described above, the control circuit 200A includes the Hi side driving circuit 231, the Low side driving circuit 232, the changeover switch 250, the pulse generator 270, the level shift circuit 271, the flip-flop 272, and the voltage detector 273, but it is also possible to include only the changeover switch 250, and to provide the Hi side driving circuit 231, the Low side driving circuit 232, the pulse generator 270, the level shift circuit 271, the flip-flop 272, and the voltage detector 273 on the main body side of the inverter circuit 200. That is, the control circuit 200A can achieve the required effects by including at least the changeover switch 250.

[0180] In addition, in the embodiment of the inverter circuit 200 described above, the second voltage V2 of the second power source 222 is relatively lower than the first voltage V1 of the first power source 221, but it does not deviate from the spirit of the present invention even if the first voltage V1 of the first power source 221 is relatively lower than the second voltage V2 of the second power source 222.

[0181] Furthermore, in the embodiment of the regulator 1 described above, the N-type transistors 20 and 50 are MOSFET transistors, in the embodiment of the inverter circuit 100, the switching elements 111, 121a, 121b, 122a, and 122b are MOSFET transistors, and in the embodiment of the inverter circuit 200, the Hi-side switching element 211 and the Low-side switching element 212 are MOSFET transistors, but the required effects can be achieved even if they are bipolar transistors. In this case, the above-mentioned gate electrodes 20g, 50g, 211g, 212g, 111a, 121aa, 121ba, 122aa, 122ba, source electrodes 20s, 50s, 211s, 212s, 111b, 121ab, 121bc, 122ab, 122bc, and drain electrodes 20d, 50d, 211d, 212d, 111d, 121ac, 121bb, 122ac, 122bb will be read as base electrodes, emitter electrodes, and collector electrodes, respectively, and the gate voltage, source voltage, and drain voltage will be read as base voltage, emitter voltage, and collector voltage, respectively. [Explanation of symbols]

[0182] G: Grand Va: Voltage after boosting ΔVa: Boosted voltage Vb: Control voltage Vb´: Voltage input to terminal 42B Vg: Gate voltage Vin: Input voltage Vout: Output voltage Vout´: Voltage input to terminal 42A α: Confluence point 1: Regulator circuit 10: Power supply 20: N-type transistor (first N-type transistor 20) 20g: Gate electrode 20s: Source electrode 20d: Drain electrode 30: Booster section 30A: Input side (terminal) 30B: Output side (terminal) 40: First control section 42: Comparator 42A: Terminal (first input terminal) 42B: Terminal (second input terminal) 42C: Terminal (output terminal) 44: Resistance 46: Resistance 48: Power supply 50: Second control section 52: Constant current source 54: Resistance 55A: Input side (terminal) 55B: Output side (terminal) 56: Resistance 58: Capacitor 60: Third control section 62: Second N-type transistor 62g: Gate electrode 62s: source electrode 62d: Drain electrode 64,66:Resistance 68: Zener diode A: External signal source VA: Input voltage VA MAX : Maximum output at input voltage VB': Voltage obtained by subtracting the threshold voltage of the second Hi-side switching element from the reference voltage VBD: Voltage set to step down the reference voltage VBD MAX : Maximum output of voltage corresponding to the first control signal from the first inverter unit VBD': voltage obtained by subtracting the threshold voltage of the first Hi-side switching element from the input voltage of the source electrode 21ab of the first Hi-side switching element VB1: First control signal VB2: Second control signal ΔVD: Threshold voltage of the step-down setting switching element VGD: Gate voltage ΔVP1: Threshold voltage of the first Hi-side switching element ΔVN1: Threshold voltage of the first low-side switching element ΔVP2: Threshold voltage of the second Hi-side switching element ΔVN2: Threshold voltage of the second low-side switching element C: Logic circuit D: Driver circuit E: Motor drive switching circuit F: Region where the input voltage is greater than the voltage VBD' F´: Input voltage range where shoot-through current occurs F´´: Region where the first high side switching element is off and the first low side switching element is on G: Region where the voltage corresponding to the first control signal is greater than the voltage VB' G´: Voltage VBD region where shoot-through current occurs G´´: Region where the second high side switching element is off and the second low side switching element is on i1: through current of the first inverter i2: through current of the second inverter L110: First connection line L120: Second connection line L130: 3rd connection line L131: Connection line L131´: Branch line L132: Connection line L133: Connection line L134: Connection line L140: 4th connection line L143: Connection line L144: Connection line L150: 5th connection line M: Motor W: Channel width of the second Hi-side switching element w: Channel width of step-down setting switching element 100: Inverter circuit 110: Step-down setting section 110: Step-down setting switching element 110a: gate electrode 110b: source electrode 110c: Drain electrode 120: Inverter section 120a: Hi side switching element 120b: Low side switching element 121: First inverter section 121A: Midpoint 121a: First Hi side switching element 121aa: Gate electrode 121ab: source electrode 121ac: Drain electrode 121b: First low-side switching element 121ba: gate electrode 121bb: Drain electrode 121bc: Source electrode 122: Second inverter section 122a: Second Hi side switching element 122aa: Gate electrode 122ab: source electrode 122ac: Drain electrode 122b: second low-side switching element 122ba: gate electrode 122bb: Drain electrode 122bc: source electrode 100A: Motor control system G1, G2: Ground L1 to L21: Connection lines L2A,L3A,L4A,L4B,L6A,L6B,L6C,L14A,L17A: Midpoint T1, T2, T3: Time t1~t19: Time V1: Voltage of the first power supply V2: Voltage of the second power supply Vf91: Voltage drop of the first diode Vf92: Voltage drop of the second diode Vf93: Voltage drop of the third diode 200: Inverter circuit 200A: Control circuit 210: Inverter section 211: Hi side switching element 211g: Gate electrode 211s: source electrode 211d: Drain electrode 212: Low side switching element 212g: Gate electrode 212s: source electrode 212d: Drain electrode 221: 1st power supply 222:Second power supply 230: Drive circuit 231::Hi side driver circuit 232: Low side drive circuit 241: First capacitor 241a: one end 241b: other end 242: Second capacitor 242a: one end 242b: other end 250: Changeover switch 251: P-channel MOSFET transistor 251g: Gate electrode 251s: source electrode 251d: Drain electrode 252: N-channel MOSFET transistor 252g: Gate electrode 252d: Drain electrode 252s: source electrode 260: Load 270: Pulse generator 270A, 270B, 270C: Control signals 271: Level shift circuit 272: Flip-flop 273: Voltage detector 280: Inductance 291: First diode 292: Second diode 293: Third diode 295: Resistance

Claims

1. A regulator circuit (1) that adjusts an input voltage (Vin) from a power supply (10) to a predetermined voltage via a first N-type transistor (20) and outputs the adjusted voltage, The device includes a booster (30) and a first controller (40), The regulator circuit (1) is characterized in that the boost unit (30) boosts the input voltage (Vin) to generate a first drive voltage (Vg) for the first N-type transistor (20), and the first control unit (40) adjusts the first drive voltage (Vg) based on a voltage (Vout) on the output side of the first N-type transistor (20) to perform control to maintain the drive voltage level of the first N-type transistor (20) at a predetermined value.

2. A regulator circuit (1) that adjusts an input voltage (Vin) from a power supply (10) to a predetermined voltage via a first N-type transistor (20) and outputs the adjusted voltage, The device includes a booster (30) and a first controller (40), The boost unit (30) receives the input voltage (Vin) and boosts the input voltage (Vin) to generate a first drive voltage (Vg) for the first N-type transistor (20); The regulator circuit (1) is characterized in that the first control unit (40) adjusts a first drive voltage (Vg) of the first N-type transistor (20) based on a voltage (Vout) on the output side of the first N-type transistor (20) and performs control to maintain a High level of the first drive voltage (Vg) of the first N-type transistor (20) at a predetermined value.

3. 3. The regulator circuit (1) according to claim 1 or 2, further comprising a second control section (50) connected between the boost section (30) and the first N-type transistor (20) and having any one or a combination of a constant current source (52), resistors (54, 56) and a capacitor (58).

4. The regulator circuit (1) according to claim 1 or 2, further comprising a third control unit (60) connected between the power supply (10) and the boost unit (30) and adjusting the supply voltage to the boost unit (30).

5. An inverter circuit (100) comprising the regulator circuit (1) according to any one of claims 1 to 3, The power supply system includes a step-down setting unit (110) and an inverter unit (120), The step-down setting unit (110) supplies a voltage (VBD) obtained by stepping down the output side voltage (Vout) of the first N-type transistor (20) to the inverter unit (120); The inverter circuit (100) is characterized in that the inverter unit (120) has a high-side switching element (120a) and a low-side switching element (120b), and turns on and off the high-side switching element (120a) and the low-side switching element (120b) in response to an input voltage (VA) input from a signal source (A), thereby outputting control signals (VB1, VB2) based on the set stepped-down voltage (VBD).

6. An inverter circuit (200) comprising the regulator circuit (1) according to any one of claims 1 to 3, The power supply device includes an inverter unit (210), a first power supply (221), a second power supply (222), a first capacitor (241), a second capacitor (242), a changeover switch (250), and a pulse generator (270), The inverter unit (210) has a high-side switching element (211) and a low-side switching element (212), The first power source (221) supplies a first voltage to the inverter unit (210); The second power supply (222) supplies a second voltage to the changeover switch (250); The first capacitor (241) supplies a drive voltage for driving the Hi side switching element (211), The second capacitor (242) supplies a voltage to the first capacitor (241); The changeover switch (250) switches between charging and discharging the second capacitor (242) by turning on and off, The inverter circuit (200) is characterized in that the pulse generator (270) generates a pulse-shaped control signal for controlling the high-side switching element (211), the low-side switching element (212), and the change-over switch (250) based on the output voltage (Vout) of the first N-type transistor (20).

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