Array substrate and liquid crystal display device

Abstract

To suppress film thickness unevenness of an orientation film.SOLUTION: An array substrate 21 includes a first electrode 41, a first insulating film 35 disposed on an upper layer side of the first electrode 41 and having an opening part 35A provided at a position overlapping with at least the first electrode 41, a second electrode 42 disposed on an upper layer side of the first insulating film 35, overlapping with the first electrode 41 at least in the opening part 35A, and connected to the first electrode 41, a second insulating film 36 disposed on an upper layer side of the second electrode 42, and an orientation film 38 disposed on an upper layer side of the second insulating film 36. The second insulating film 36 includes an insulating part 44 provided in the opening part 35A. The insulating part 44 includes a high part 44A of the first insulating film 35 that is higher than an opening edge of the opening part 35A.SELECTED DRAWING: Figure 12

Description

[Technical field]

[0001] The technique disclosed in this specification relates to an array substrate and a liquid crystal display device. [Background technology]

[0002] Conventionally, one example of a liquid crystal display device is known, which is described in Patent Document 1 below. The liquid crystal display device described in Patent Document 1 includes switching elements arranged in a display region including pixels, a color filter layer including a first color filter of a first color and a second color filter of a second color different from the first color, and a conductive layer connected to the switching elements through contact holes penetrating the color filter layer. The conductive layer is in contact with the first color filter and the second color filter at the contact holes. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-26039 Summary of the Invention [Problem to be solved by the invention]

[0004] The above-mentioned Patent Document 1 discloses a configuration in which a black layer is disposed inside the contact hole, and the black layer blocks light incident on the area where the color filter layer is removed in the contact hole, thereby suppressing color mixing. However, in Patent Document 1, the black layer is formed flush with the insulating layer around the contact hole. For this reason, when forming an alignment film on the upper layer side of the insulating layer in the manufacturing process, the alignment film material is likely to accumulate on the black layer. If the alignment film material accumulates on the black layer, there is a risk that the alignment film material will be insufficient in positions other than on the black layer, and the alignment film may become locally thin or the alignment film may not be formed locally. If a thin or non-formed portion occurs in the alignment film, the alignment of the liquid crystal may be disturbed near that portion, resulting in a visually noticeable display defect.

[0005] The technology described in this specification was developed based on the above circumstances, and aims to suppress unevenness in the thickness of an alignment film. [Means for solving the problem]

[0006] (1) An array substrate related to the technology described in this specification comprises a first electrode, a first insulating film arranged on an upper layer side of the first electrode and having an opening at a position overlapping at least with the first electrode, a second electrode arranged on an upper layer side of the first insulating film, overlapping with the first electrode at least within the opening and connected to the first electrode, a second insulating film arranged on an upper layer side of the second electrode, and an alignment film arranged on an upper layer side than the second insulating film, wherein the second insulating film has an insulating portion arranged in the opening, and the insulating portion includes a high portion of the first insulating film that is higher than an edge of the opening.

[0007] (2) In addition to the above (1), the array substrate may be configured such that the first electrodes and the second electrodes are arranged in a row at intervals in a first direction, and the opening and the insulating portion both extend along the first direction and cross the first electrodes and the second electrodes in a row.

[0008] (3) In addition to the above (2), the array substrate may further include a first light-shielding portion arranged below the first electrode and made of a light-shielding material, the first light-shielding portion extending along the first direction and overlapping the insulating portion.

[0009] (4) In addition to the above (2), the array substrate may further include a second light-shielding portion arranged below the alignment film and made of a light-shielding material, the second light-shielding portion being arranged in a line spaced apart relationship to sandwich the first electrode and the second electrode in the first direction, and the high-level portion being sandwiched between two of the second light-shielding portions in the first direction.

[0010] (5) In addition to any one of (1) to (4) above, the array substrate may have a height of the high portion from an edge of the opening of the first insulating film that is greater than a thickness of the alignment film.

[0011] (6) In addition to any one of (1) to (4) above, the array substrate may have a height of the high portion from an edge of the opening of the first insulating film that is smaller than a thickness of the alignment film.

[0012] (7) In addition to any one of (1) to (6) above, the array substrate may be configured so that the higher portion becomes gradually higher from the outer circumferential end side toward the center side of the insulating portion.

[0013] (8) In addition to any one of (1) to (6), the array substrate may be configured such that the upper surface of the higher portion is flat.

[0014] (9) In addition to any one of (1) to (6) above, the array substrate may be configured so that the high-level portion becomes gradually lower from the outer circumferential end side toward the center side of the insulating portion.

[0015] (10) A liquid crystal display device related to the technology described in this specification includes an array substrate described in any one of (1) to (9) above, a counter substrate arranged to face the array substrate, and a liquid crystal layer arranged between the array substrate and the counter substrate.

[0016] (11) In addition to the above (10), the liquid crystal display device may further include a spacer on the opposing substrate protruding toward the array substrate, the first electrodes and the second electrodes are arranged in a row at intervals in a first direction, the opening and the insulating portion both extend along the first direction and are arranged across the first electrodes and the second electrodes in a row, and the insulating portion may include a bump in the first insulating film that is higher than an opening edge of the opening and overlaps the spacer.

[0017] (12) In addition to the above-mentioned (11), the liquid crystal display device may be configured such that the high-level portion is lower than the bump. Effect of the Invention

[0018] According to the technique described in this specification, unevenness in the thickness of the alignment film can be suppressed. [Brief description of the drawings]

[0019] [Figure 1] FIG. 1 is a schematic perspective view showing a state in which a user wears a head-mounted display according to a first embodiment on his or her head. [Diagram 2] FIG. 1 is a schematic side view showing an optical relationship between a liquid crystal display device and a lens unit provided in a head-mounted device constituting a head-mounted display according to a first embodiment, and a user's eyeball. [Diagram 3] 1 is a schematic plan view of a liquid crystal panel and a flexible substrate included in a liquid crystal display device according to a first embodiment; [Figure 4] 1 is a schematic cross-sectional view of a liquid crystal panel according to a first embodiment of the present invention; [Diagram 5] FIG. 2 is a plan view showing a pixel arrangement in a display area of ​​an array substrate provided in the liquid crystal panel according to the first embodiment; [Figure 6] 6 is a cross-sectional view of the liquid crystal panel according to the first embodiment taken along line vi-vi in ​​FIG. [Figure 7] 6 is a cross-sectional view of the liquid crystal panel according to the first embodiment taken along line vii-vii of FIG. 5 . [Figure 8] 8 is a cross-sectional view of the liquid crystal panel according to the first embodiment taken along line viii-vii of FIG. 5 . [Figure 9] FIG. 1 is a plan view showing pixels in a display region of a liquid crystal panel according to a first embodiment, in which a first metal film and a fourth metal film are shown in a shaded manner. [Figure 10] FIG. 2 is a plan view showing pixels in a display region of the liquid crystal panel according to the first embodiment, in which the semiconductor film and the second metal film are shown in a shaded manner. [Figure 11] FIG. 2 is a plan view showing pixels in a display region of the liquid crystal panel according to the first embodiment, in which the first transparent electrode film, the second transparent electrode film, and the third transparent electrode film are shaded. [Figure 12] 5A and 5B are cross-sectional views of the liquid crystal panel according to the first embodiment. [Figure 13] 5. A cross-sectional view of the liquid crystal panel according to the first embodiment taken along line xiii-xiii in FIG. [Figure 14] FIG. 13 is a cross-sectional view showing a state in which a second planarization film is formed in a thirteenth step included in the array substrate manufacturing process according to the first embodiment, in which the cross-sectional structure at the same cutting position as in FIG. 7 and the cross-sectional structure at the same cutting position as in FIG. 12 are both shown. [Figure 15] FIG. 13 is a cross-sectional view showing a state in which a second planarization film is exposed through a photomask in a thirteenth step included in the array substrate manufacturing process according to the first embodiment, in which the cross-sectional structure at the same cutting position as in FIG. 7 and the cross-sectional structure at the same cutting position as in FIG. 12 are both shown. [Figure 16] FIG. 13 is a cross-sectional view showing a state in which the second planarization film is developed in a thirteenth step included in the array substrate manufacturing process according to the first embodiment, in which the cross-sectional structure at the same cutting position as in FIG. 7 and the cross-sectional structure at the same cutting position as in FIG. 12 are both shown. [Figure 17] FIG. 13 is a cross-sectional view showing the cross-sectional structure of a liquid crystal panel according to a second embodiment taken along the same line as in FIG. 12 . [Figure 18]FIG. 14 is a cross-sectional view showing the cross-sectional structure of a liquid crystal panel according to a second embodiment taken along the same line as in FIG. 13 . [Figure 19] FIG. 13 is a cross-sectional view showing a state in which the second planarization film is exposed through a photomask in a thirteenth step included in the array substrate manufacturing process according to the second embodiment, and showing a cross-sectional structure at the same cutting position as in FIG. [Figure 20] 13 is a cross-sectional view showing the cross-sectional structure of a liquid crystal panel according to a third embodiment taken along the same line as in FIG. 12 . [Figure 21] FIG. 14 is a cross-sectional view showing the cross-sectional structure of a liquid crystal panel according to a third embodiment taken along the same line as in FIG. 13 . [Figure 22] FIG. 13 is a cross-sectional view showing a state in which the second planarization film is exposed through a photomask in a thirteenth step included in the array substrate manufacturing process according to the third embodiment, and showing a cross-sectional structure at the same cutting position as in FIG. [Diagram 23] FIG. 13 is a cross-sectional view showing the cross-sectional structure of a liquid crystal panel according to a fourth embodiment taken along the same line as in FIG. 12 . [Figure 24] FIG. 14 is a cross-sectional view showing the cross-sectional structure of a liquid crystal panel according to a fourth embodiment taken along the same line as in FIG. 13 . [Diagram 25] FIG. 13 is a cross-sectional view showing a state in which the second planarization film is exposed through a photomask in a thirteenth step included in the array substrate manufacturing process according to the fourth embodiment, and showing a cross-sectional structure at the same cutting position as in FIG. [Figure 26] FIG. 13 is a cross-sectional view showing the cross-sectional structure of a liquid crystal panel according to a fifth embodiment taken along the same line as in FIG. 12 . [Figure 27] FIG. 14 is a cross-sectional view showing the cross-sectional structure of a liquid crystal panel according to a fifth embodiment taken along the same line as in FIG. 13 . [Figure 28] FIG. 13 is a cross-sectional view showing a state in which the second planarization film is exposed through a photomask in a thirteenth step included in the array substrate manufacturing process according to the fifth embodiment, and showing a cross-sectional structure at the same cutting position as in FIG. [Figure 29] FIG. 13 is a cross-sectional view showing the cross-sectional structure of a liquid crystal panel according to a sixth embodiment taken along the same line as in FIG. 12 . [Diagram 30] FIG. 14 is a cross-sectional view showing the cross-sectional structure of a liquid crystal panel according to a sixth embodiment taken along the same line as in FIG. [Diagram 31] FIG. 13 is a cross-sectional view showing a state in which the second planarization film is exposed through a photomask in a thirteenth step included in the array substrate manufacturing process according to the sixth embodiment, and showing a cross-sectional structure at the same cutting position as in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] <Embodiment 1> A first embodiment will be described with reference to Fig. 1 to Fig. 16. In this embodiment, a goggle-type head-mounted display (HMD) 10HMD and a liquid crystal display device 10 used therein are illustrated. Note that an X-axis, a Y-axis, and a Z-axis are shown in a part of each drawing, and each axis direction is drawn to be the direction shown in each drawing.

[0021] The appearance of a goggle-type head mounted display 10HMD will be described with reference to Fig. 1. The head mounted display 10HMD includes a head mounted device 10HMDa that is mounted on a user's head 10HD, as shown in Fig. 1. The head mounted device 10HMDa surrounds both of the user's eyes.

[0022] The configuration of the head-mounted device 10HMDa will be described with reference to FIG. 2. As shown in FIG. 2, the head-mounted device 10HMDa incorporates at least a liquid crystal display device 10 for displaying an image and a lens unit 10RE for focusing the image displayed on the liquid crystal display device 10 on the user's eyeball 10EY. The liquid crystal display device 10 includes at least a liquid crystal panel (display device) 11 and a backlight device (illumination device) 12 for irradiating the liquid crystal panel 11 with light. The main surface of the liquid crystal panel 11 facing the lens unit 10RE is a display surface 11DS for displaying an image. The lens unit 10RE is disposed between the liquid crystal display device 10 and the user's eyeball 10EY. The lens unit 10RE imparts a refracting effect to light. By adjusting the focal length of the lens unit 10RE, the user can recognize that an image focused on the retina 10EYb via the crystalline lens 10EYa of the eyeball 10EY is displayed on a virtual display 10VD that appears to be located at a distance L2 from the eyeball 10EY. This distance L2 is much larger than the actual distance L1 from the eyeball 10EY to the liquid crystal display device 10. This allows the user to view an enlarged image, which is a virtual image, displayed on the virtual display 10VD, which has a screen size (e.g., about several tens of inches to several hundreds of inches) that is much larger than the screen size (e.g., about several tenths of an inch to a few inches) of the liquid crystal display device 10.

[0023] It is possible to mount one liquid crystal display device 10 on the head mounted device 10HMDa and display an image for the right eye and an image for the left eye on the liquid crystal display device 10. Alternatively, it is possible to mount two liquid crystal display devices 10 on the head mounted device 10HMDa and display an image for the right eye on one liquid crystal display device 10 and an image for the left eye on the other liquid crystal display device 10. The head mounted device 10HMDa may also be provided with earphones or the like that are placed against the user's ears to output sound.

[0024] The configuration of the liquid crystal panel 11 provided in the liquid crystal display device 10 will be described with reference to FIG. 3 and the like. The configuration of the backlight device 12 is as known, and includes, for example, a light source such as an LED and an optical member that converts light from the light source into planar light by applying an optical effect. As shown in FIG. 3, the liquid crystal panel 11 has a rectangular shape as a whole in a planar view. The central part of the screen of the liquid crystal panel 11 is a display area AA where an image is displayed. The outer peripheral part of the screen of the liquid crystal panel 11, which is a frame-like part surrounding the display area AA, is a non-display area NAA where no image is displayed. The area surrounded by the dashed line in FIG. 3 is the display area AA. The liquid crystal panel 11 according to this embodiment is used in the head-mounted display 10HMD described above, and therefore has extremely high resolution, with a pixel density of, for example, about 1000 ppi or more.

[0025] As shown in FIG. 3, the liquid crystal panel 11 is formed by bonding a pair of substrates 20 and 21. The substrate 20 and 21 are disposed on the front side as a counter substrate (second substrate, CF substrate) 20, and the substrate 20 and 21 are disposed on the back side as an array substrate (first substrate, active matrix substrate) 21. The counter substrate 20 and the array substrate 21 are formed by laminating various films on the inner side of the substrates 20GS and 21GS, which are both made of glass and have almost transparent and excellent light transmission. The substrates 20GS and 21GS contain, for example, non-alkali glass as a main material. The array substrate 21 is larger than the counter substrate 20, and a part of it protrudes laterally from the counter substrate 20. A driver 13 for performing display drive and a flexible substrate 14 are mounted (connected) on the protruding portion 21A of the array substrate 21 via an ACF (Anisotropic Conductive Film). The flexible substrate 14 is configured by forming a number of wiring patterns on a base material having insulating properties and flexibility. A control circuit board (signal supply source) 15 that supplies various input signals to the driver 13 from the outside is connected to the flexible board .

[0026] Next, the cross-sectional configuration of the liquid crystal panel 11 will be outlined with reference to FIG. 4. As shown in FIG. 4, the pair of substrates 20, 21 are disposed facing each other with a gap in the Z-axis direction, which is the normal direction of the main surfaces of the substrates 20, 21. Between the pair of substrates 20, 21, at least a liquid crystal layer 22 and a seal portion 23 for sealing (sealing) the liquid crystal layer 22 are interposed. The liquid crystal layer 22 contains liquid crystal molecules, which are a substance whose optical properties change with the application of an electric field. The seal portion 23 has a rectangular frame shape (endless ring shape) as a whole in a plan view, and surrounds the liquid crystal layer 22 all around in the non-display area NAA. The seal portion 23 maintains a gap (cell gap) equivalent to the thickness of the liquid crystal layer 22. A polarizing plate 24 is attached to each of the outer surfaces of the pair of substrates 20, 21.

[0027] An outline of the pixel arrangement in the display area AA of the array substrate 21 will be described with reference to FIG. 5. As shown in FIG. 5, a plurality of gate wirings (scanning wirings) 25 and source wirings (image wirings) 26 are arranged in a lattice pattern on the inner surface of the display area AA of the array substrate 21. The gate wirings 25 extend along the X-axis direction so as to cross the display area AA. A plurality of the gate wirings 25 are arranged side by side at intervals in the Y-axis direction. The source wirings 26 extend along the Y-axis direction so as to cross the display area AA vertically, and are substantially perpendicular (intersect) with the gate wirings 25. A plurality of the source wirings 26 are arranged side by side at intervals in the X-axis direction. A TFT (switching element) 27 and a pixel electrode (third electrode) 28 are provided near the intersection of the gate wirings 25 and the source wirings 26. A plurality of the TFTs 27 and the pixel electrodes 28 are arranged side by side regularly along the X-axis direction and the Y-axis direction. The TFTs 27 are connected to the gate wirings 25, the source wirings 26, and the pixel electrodes 28. The TFT 27 has a gate electrode 27A to which the gate line 25 is connected, a source electrode 27B to which the source line 26 is connected, a drain electrode 27C to which the pixel electrode 28 is connected, and a semiconductor portion 27D connected to the source electrode 27B and the drain electrode 27C. The semiconductor portion 27D is made of a semiconductor material and is disposed so as to overlap the gate electrode 27A. When the TFT 27 is driven based on a scanning signal supplied from the gate line 25 to the gate electrode 27A, it charges the pixel electrode 28 to a potential based on an image signal supplied from the source line 26 to the source electrode 27B. The pixel electrode 28 is elongated in the Y-axis direction.

[0028] As shown in FIG. 6, a common electrode 30 is provided on the inner surface of the display area AA of the array substrate 21. The common electrode 30 is located above the pixel electrodes 28 and is arranged over almost the entire display area AA. As a result, the common electrode 30 overlaps all the pixel electrodes 28 arranged in the display area AA. In this manner, in the array substrate 21 according to the present embodiment, the "upper electrode" that is the electrode located on the upper layer side of the pixel electrodes 28 and the common electrode 30 is the common electrode 30, and the "lower electrode" that is the electrode located on the lower layer side is the pixel electrode 28. A plurality of slits 30A are formed in the portions of the common electrode 30 that overlap the plurality of pixel electrodes 28. A common potential signal that is a common potential (reference potential) is supplied to the common electrode 30. When the pixel electrodes 28 are charged to a potential based on an image signal transmitted to the source wiring 26 in response to the driving of the TFT 27, a potential difference occurs between the pixel electrodes 28 and the common electrode 30. Then, a fringe electric field (oblique electric field) including a component in the normal direction to the main surface of the array substrate 21, in addition to a component along the main surface of the array substrate 21, is generated between the opening edge of the slit 30A in the common electrode 30 and the pixel electrode 28. Therefore, by utilizing this fringe electric field, the orientation state of the liquid crystal molecules contained in the liquid crystal layer 22 can be controlled, and a predetermined display is performed based on the orientation state of the liquid crystal molecules. In other words, the liquid crystal panel 11 according to this embodiment operates in FFS (Fringe Field Switching) mode.

[0029] Next, various films laminated on the glass substrate 21GS of the array substrate 21 will be described in detail with reference to Figures 6 to 8. As shown in Figures 6 to 8, on the glass substrate 21GS of the array substrate 21, at least a first metal film, a base coat film 31, a semiconductor film, a gate insulating film 32, a second metal film, a first interlayer insulating film 33, a third metal film, a second interlayer insulating film 34, a first transparent electrode film, a first planarizing film (first insulating film) 35, a second transparent electrode film, a second planarizing film (second insulating film) 36, a third transparent electrode film, a third interlayer insulating film 37, a fourth transparent electrode film, a light-shielding film, and an alignment film 38 are laminated in this order from the lower layer side (glass substrate 21GS side).

[0030] The first metal film, the second metal film, and the third metal film are each a single layer film made of one type of metal material, or a laminated film or an alloy made of different types of metal materials, and thus have electrical conductivity and light shielding properties. Of these, the first metal film constitutes the first light shielding portion 40, as shown in FIG. 7. The first light shielding portion 40 is disposed at a position overlapping the semiconductor portion 27D of the TFT 27, and can block light from the backlight device 12 toward the semiconductor portion 27D. This can suppress fluctuations in the characteristics of the TFT 27 that may occur when the semiconductor portion 27D is irradiated with light. The second metal film constitutes the gate wiring 25 and the gate electrode 27A. The portion of the gate wiring 25 that overlaps the semiconductor portion 27D in a plan view is the gate electrode 27A. The third metal film constitutes the source wiring 26, as shown in FIG. 6.

[0031] The first transparent electrode film, the second transparent electrode film, the third transparent electrode film, and the fourth transparent electrode film are made of a transparent electrode material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide). Of these, the first transparent electrode film constitutes the first electrode 41, as shown in FIG. 7. One end portion of the first electrode 41 is connected to the drain electrode 27C. The second transparent electrode film constitutes the second electrode 42. One end portion of the second electrode 42 is connected to the other end portion of the first electrode 41, and the other end portion is connected to the pixel electrode 28. The drain electrode 27C and the pixel electrode 28 are connected by the first electrode 41 and the second electrode 42. The third transparent electrode film constitutes the pixel electrode 28. The fourth transparent electrode film constitutes the common electrode 30.

[0032] The semiconductor film is made of an oxide semiconductor material. More specifically, the semiconductor film is made of an oxide thin film containing indium (In), gallium (Ga), and zinc (Zn), which are types of oxide semiconductors. The oxide thin film containing indium (In), gallium (Ga), and zinc (Zn) is considered to be amorphous or crystalline. The oxide semiconductor material of the semiconductor film has a characteristic of having a higher resistance value when no voltage is applied (off state) compared to a silicon semiconductor material. In addition, the oxide semiconductor material of the semiconductor film has a higher electron mobility compared to an amorphous silicon semiconductor material.

[0033] The semiconductor film according to this embodiment is partially made to have low resistance by a low resistance treatment in the manufacturing process, and is composed of a low resistance region and a non-resistance region. In FIG. 7 and other figures, the low resistance region in the semiconductor film is illustrated as being shaded. The non-low resistance region in the semiconductor film is made possible to move charges only under a specific condition (when a scanning signal is supplied to the gate electrode 27A). The non-low resistance region in the semiconductor film constitutes the semiconductor section 27D. The semiconductor section 27D is a portion of the semiconductor film that overlaps the gate electrode 27A in a plan view. The low resistance region in the semiconductor film has an extremely low resistivity, for example, about 1 / 10000000000 to 1 / 100, compared to the non-low resistance region, and is always possible to move charges, functioning as a conductor. As shown in FIG. 7 and FIG. 8, the source electrode 27B and the drain electrode 27C are constituted by the low resistance region in the semiconductor film. The resistance reduction process of the semiconductor film is performed during the manufacturing process of the array substrate 21 by using the gate wiring 25 and the gate electrode 27A as a mask after the gate wiring 25 and the gate electrode 27A made of the second metal film are provided. In the resistance reduction process, the resistance reduction process is selectively performed on the portions of the semiconductor film that are not covered by the gate wiring 25 and the gate electrode 27A (non-overlapping portions, exposed portions), and the resistance reduction process is not performed on the portions that are covered by the gate wiring 25 and the gate electrode 27A (overlapping portions, non-exposed portions). The resistance reduction process is performed using, for example, NH 3 , H 2 , N 2 These include plasma treatment and annealing treatment using gases such as He.

[0034] The base coat film 31, the gate insulating film 32, the first interlayer insulating film 33, the second interlayer insulating film 34, and the third interlayer insulating film 37 are all made of SiO 2 , which is a type of inorganic material (inorganic resin material). 2 (silicon oxide, silicon oxide), SiN x(silicon nitride) or the like. Of these, the base coat film 31 is interposed between the first light-shielding portion 40 and the gate wiring 25 and gate electrode 27A to keep them in an insulated state. The gate insulating film 32 is interposed between the gate wiring 25 and gate electrode 27A and the source electrode 27B, drain electrode 27C and semiconductor portion 27D to keep them in an insulated state. The first interlayer insulating film 33 is interposed between the gate wiring 25 and source wiring 26 to keep them in an insulated state. The second interlayer insulating film 34 is interposed between the source wiring 26 and the first electrode 41 to keep them in an insulated state. The third interlayer insulating film 37 is interposed between the pixel electrode 28 and the common electrode 30 to keep them insulated.

[0035] The first planarization film 35 and the second planarization film 36 are both made of PMMA (acrylic resin), which is a kind of organic material (organic resin material). The first planarization film 35 and the second planarization film 36 made of an organic material are usually thicker than the base coat film 31, the gate insulating film 32, the first interlayer insulating film 33, the second interlayer insulating film 34, and the third interlayer insulating film 37 made of an inorganic material. Specifically, the base coat film 31, the gate insulating film 32, the first interlayer insulating film 33, the second interlayer insulating film 34, and the third interlayer insulating film 37 made of an inorganic material have a thickness of, for example, several tens to several hundreds of nm, whereas the first planarization film 35 and the second planarization film 36 made of an organic material have a thickness of, for example, approximately 1 μm to 3 μm. The first planarization film 35 is interposed between the first electrode 41 and the second electrode 42. The second planarization film 36 is interposed between the second electrode 42 and the pixel electrode 28.

[0036] The light-shielding film may have a laminated structure of, for example, a light-shielding layer made of a metal material, a reflection-transmission layer made of a metal material, and a transmission layer made of a light-transmitting resin material. Specifically, the light-shielding film may have a laminated structure of, for example, a light-shielding layer made of Mo (molybdenum) and a transmission layer made of a light-transmitting resin material, in that order from the bottom. x a first transmission layer made of, for example, Mo, having a thickness smaller than that of the light-shielding layer, and a second reflection / transmission layer made of, for example, SiN xand a second transmission layer made of, for example, a thin film. The light-shielding layer among them has a function of blocking light irradiated from the backlight device 12. The thickness of the light-shielding layer is preferably, for example, 30 nm or more in order to achieve the light-shielding function described above. The first transmission layer has a function of reducing reflection of external light by utilizing thin film interference. The thickness of the first transmission layer is preferably, for example, in the range of 20 nm to 100 nm in order to achieve the function of reducing reflection of external light described above. The reflective-transmitting layer has a function of reducing reflection of external light and a function of re-reflecting light reflected by the light-shielding layer. The thickness of the reflective-transmitting layer is preferably, for example, in the range of 3 nm to 20 nm in order to achieve each of the functions described above. The second transmission layer has a function of reducing reflection of external light by utilizing thin film interference. The thickness of the second transmission layer is smaller than the thickness of the first transmission layer. The light-shielding film having such a configuration constitutes the second light-shielding section 43. In addition to the above, the light-shielding film may have a single-layer structure or a multi-layer structure made of a metal material having light-shielding properties, or may have a single-layer structure or a multi-layer structure made of a light-shielding resin material.

[0037] The alignment film 38 is made of an organic material such as polyimide. The alignment film 38 has a function of aligning liquid crystal molecules by being subjected to a photo-alignment treatment on the upper surface facing the liquid crystal layer 22. The thickness of the alignment film 38 is, for example, about several tens to several hundreds of nm.

[0038] On the other hand, as shown in FIG. 6 and FIG. 7, the glass substrate 20GS of the counter substrate 20 is provided with a color filter 29, a counter-side light shielding portion 20BM, an overcoat film 20OC, a spacer 39, and a counter-side alignment film 20PI. The color filter 29 is arranged so as to overlap with the pixel electrode 28 of the array substrate 21, and constitutes a pixel, which is a display unit, together with the overlapping pixel electrode 28. The color filter 29 includes a plurality of types (three types) of different colors. The plurality of types of color filters 29 of different colors are arranged so as to be adjacent to each other in the extending direction (X-axis direction) of the gate wiring 25. That is, the arrangement direction of the plurality of types of color filters 29 of different colors coincides with the X-axis direction. The plurality of types of color filters 29 of different colors extend along the extending direction (Y-axis direction) of the source wiring 26. In this way, the plurality of types of color filters 29 of different colors are arranged in a vertical stripe pattern as a whole. The color filters 29, which are different from one another in color, are arranged such that their boundaries (color boundaries) overlap the source wiring 26. The color filters 29 include three types of filters: a green color filter (first color filter) that exhibits green, a blue color filter (second color filter) that exhibits blue, and a red color filter (third color filter) that exhibits red. The green color filter, together with the overlapping pixel electrode 28, constitutes a green pixel (first pixel) that exhibits green. The blue color filter, together with the overlapping pixel electrode 28, constitutes a blue pixel (second pixel) that exhibits blue. The red color filter, together with the overlapping pixel electrode 28, constitutes a red pixel (third pixel) that exhibits red. In FIG. 6 and other figures, the colors of the color filters 29 are indicated by the letters R (Red), G (Green), and B (Blue).

[0039] The opposing side light shielding portion 20BM is made of a synthetic resin material or the like having excellent light shielding properties, and is provided on the inner surface of the glass substrate 20GS as shown in FIG. 7. The opposing side light shielding portion 20BM extends along the X-axis direction and is arranged so as to overlap the gate wiring 25 provided on the array substrate 21. The opposing side light shielding portion 20BM is arranged in a row at intervals in the Y-axis direction, and is arranged in a horizontal stripe pattern in a plan view. The overcoat film 20OC is provided on the upper layer side of the opposing side light shielding portion 20BM, and is arranged in a solid pattern over almost the entire area of ​​the opposing substrate 20, thereby making it possible to flatten the opposing substrate 20. The opposing side alignment film 20PI is provided on the upper layer side of the overcoat film 20OC, and is arranged facing the liquid crystal layer 22. The opposing side alignment film 20PI is made of an organic material such as polyimide, similar to the alignment film 38 on the array substrate 21 side, and has a function of aligning liquid crystal molecules by performing a photoalignment treatment on the upper surface facing the liquid crystal layer 22.

[0040] As shown in FIG. 7, the spacer 39 protrudes from the counter substrate 20 toward the array substrate 21 along the Z-axis direction (the normal direction of the main surface of the counter substrate 20). In detail, the spacer 39 is made of a resin material, protrudes from the surface of the overcoat film 20OC in the display area AA of the counter substrate 20 toward the array substrate 21 along the Z-axis direction, and the protruding tip surface faces the array substrate 21. The spacer 39 is generally in the shape of a slightly tapered column. The spacer 39 may include two types of spacers having different protruding heights from the overcoat film 20OC. FIG. 7 illustrates a spacer 39 with a large protruding height. The protruding tip surface of the spacer 39 with a large protruding height contacts the inner surface of the array substrate 21 (the alignment film 38). In contrast, the spacer 39 having a small protruding height has a clearance between the protruding tip surface and the inner surface of the array substrate 21, and the protruding tip surface comes into contact with the inner surface of the array substrate 21 only when either of the pair of substrates 20, 21 is bent inward due to the action of an external force. Such a spacer 39 can maintain the gap (thickness of the liquid crystal layer 22, cell gap) between the pair of substrates 20, 21. As shown in Fig. 5, the spacer 39 is arranged to overlap the gate electrode 27A of a specific TFT 27 (for example, the TFT 27 connected to the pixel electrode 28 constituting the blue pixel having the lowest luminosity factor) among the multiple TFTs 27 aligned along the X-axis direction.

[0041] Next, the planar shapes of the first light-shielding portion 40 made of the first metal film and the second light-shielding portion 43 made of the fourth metal film will be described mainly with reference to FIG. 9. In FIG. 9, the configurations made of the first metal film and the fourth metal film (the first light-shielding portion 40 and the second light-shielding portion 43) are illustrated with different hatching patterns. As shown in FIG. 9, the first light-shielding portion 40 has a horizontally elongated strip shape extending along the X-axis direction, and most of it is arranged to overlap the gate wiring 25 in a plan view. The width dimension of the first light-shielding portion 40 is slightly larger than the width dimension of the gate wiring 25, and both ends in the width direction (Y-axis direction) protrude from both side edges of the gate wiring 25. Therefore, it can be said that the first light-shielding portion 40 covers the entire area of ​​the semiconductor portion 27D arranged to overlap the gate electrode 27A made of a part of the gate wiring 25 from the back side. This allows the first light-shielding portion 40 to efficiently block light traveling from the backlight device 12 toward the semiconductor portion 27D.

[0042] As shown in FIG. 9, the second light-shielding portion 43 has a vertically elongated strip shape extending along the Y-axis direction, and most of it is arranged to overlap the source wiring 26 in a plan view. The width dimension of the second light-shielding portion 43 is slightly larger than the width dimension of the source wiring 26, and both ends in the width direction (X-axis direction) protrude from both side edges of the source wiring 26. The length dimension of the second light-shielding portion 43 is larger than the dimension of the pixel electrode 28 in the Y-axis direction, and both ends in the length direction (Y-axis direction) are arranged to overlap the two gate wirings 25 sandwiching the pixel electrode 28 in a plan view. It can be said that the second light-shielding portion 43 configured in this way separates the two pixel electrodes 28 adjacent to each other across the source wiring 26 in the X-axis direction over the entire length in the Y-axis direction. The second light-shielding portions 43 are regularly arranged side by side at intervals in the X-axis direction and the Y-axis direction. The number of second light-shielding portions 43 in the X-axis direction matches the number of source lines 26. The number of second light-shielding portions 43 in the Y-axis direction matches the number of pixel electrodes 28 arranged in the Y-axis direction.

[0043] As shown in FIG. 6, the second light-shielding portion 43 made of the fifth metal film is disposed on the upper layer side of the common electrode 30 made of the fourth transparent electrode film, and is in direct contact with the common electrode 30. Therefore, the second light-shielding portion 43 has the same potential (common potential) as the common electrode 30. The second light-shielding portion 43 can block light irradiated from the backlight device 12 toward the liquid crystal panel 11, for example. The second light-shielding portion 43 separates the pixel electrodes 28 adjacent to each other in the X-axis direction, and is disposed at the boundary between the color filters 29 that are adjacent to each other in the X-axis direction and exhibit different colors. Therefore, even if light that has passed through the pixel electrode 28 constituting a green pixel is heading toward the color filter 29 that exhibits red or blue, the light can be blocked by the second light-shielding portion 43. Similarly, even if light transmitted through the pixel electrode 28 constituting a blue pixel is directed toward the color filter 29 that exhibits red or the color filter 29 that exhibits green, the light can be blocked by the second light-shielding portion 43. Also, even if light transmitted through the pixel electrode 28 constituting a red pixel is directed toward the color filter 29 that exhibits green or the color filter 29 that exhibits blue, the light can be blocked by the second light-shielding portion 43. As a result, the second light-shielding portion 43 makes it difficult for color mixing to occur, so that the display independence of the display of each pixel that exhibits each color is guaranteed. In particular, the second light-shielding portion 43 is made of a fourth metal film and is disposed on the upper layer side of the common electrode 30, that is, next to the alignment film 38 in the array substrate 21, so that more light that may cause color mixing can be blocked. As a result, a higher color mixing prevention function is obtained.

[0044] Next, the planar shapes of the source electrode 27B, the drain electrode 27C, and the semiconductor portion 27D made of a semiconductor film will be described mainly with reference to FIG. 10. In FIG. 10, the configuration (gate wiring 25, gate electrode 27A, source electrode 27B, drain electrode 27C, and semiconductor portion 27D) made of the second metal film and the semiconductor film are illustrated with different hatching patterns. As shown in FIG. 10, the source electrode 27B, the drain electrode 27C, and the semiconductor portion 27D are arranged to extend along a diagonal direction with respect to the Y-axis direction and cross the gate wiring 25. The source electrode 27B is arranged adjacent to the pixel electrode 28 side (lower side of FIG. 10) to be connected in the Y-axis direction with respect to the semiconductor portion 27D overlapping with the gate wiring 25 (gate electrode 27A). One end of the source electrode 27B (upper side of FIG. 10) is connected to the semiconductor portion 27D, while the other end (lower side of FIG. 10) is arranged to overlap with the source wiring 26 in a plan view. The drain electrode 27C is disposed adjacent to the semiconductor portion 27D overlapping the gate wiring 25 on the opposite side (upper side in FIG. 10) to the pixel electrode 28 to be connected in the Y-axis direction. That is, the source electrode 27B and the drain electrode 27C are disposed to sandwich the gate wiring 25 and the semiconductor portion 27D in the Y-axis direction. One end (lower side in FIG. 10) of the drain electrode 27C is connected to the semiconductor portion 27D, while the other end (upper side in FIG. 10) of the drain electrode 27C is disposed to overlap the first electrode 41 in a plan view. The other end of the drain electrode 27C is disposed to overlap a part of the pixel electrode 28 to be not connected, and is disposed approximately in the center of the pixel electrode 28 in the X-axis direction.

[0045] 8, the source electrode 27B is connected to the source wiring 26 through a first contact hole CH1 provided in the gate insulating film 32 and the first interlayer insulating film 33 interposed between the source electrode 27B and the source wiring 26 to be connected. The first contact hole CH1 is disposed at a position overlapping both the other end of the source electrode 27B and the source wiring 26, and is provided in communication with the gate insulating film 32 and the first interlayer insulating film 33.

[0046] Next, the planar shapes of the first electrode 41 made of the first transparent electrode film, the second electrode 42 made of the second transparent electrode film, and the pixel electrode 28 made of the third transparent electrode film will be described mainly with reference to FIG. 11. In FIG. 11, the configuration made of the first transparent electrode film, the second transparent electrode film, and the third transparent electrode film (the first electrode 41, the second electrode 42, and the pixel electrode 28) are illustrated with different hatching patterns. As shown in FIG. 11, the first electrode 41, the second electrode 42, and the pixel electrode 28 all have a vertically elongated rectangular shape extending along the Y-axis direction. The pixel electrode 28 is disposed in a position sandwiching the gate wiring 25 between it and the drain electrode 27C to be connected in the Y-axis direction. The first electrode 41 connected to the drain electrode 27C and the second electrode 42 connected to the pixel electrode 28 are connected to each other at a position overlapping the gate wiring 25. In detail, the first electrode 41 is arranged such that one end (upper side in FIG. 11) overlaps one end of the drain electrode 27C, and the other end (lower side in FIG. 11) overlaps most of the gate electrode 27A and the semiconductor portion 27D. The second electrode 42 is arranged such that one end (upper side in FIG. 11) overlaps the other end of the first electrode 41, and the other end (lower side in FIG. 11) overlaps a part of the pixel electrode 28. The first electrodes 41 and the second electrodes 42 are arranged in a plurality of pairs spaced apart from each other in the X-axis direction, and the arrangement interval is equal to the arrangement interval of the plurality of pixel electrodes 28 in the X-axis direction. The plurality of first electrodes 41 and the second electrodes 42 are arranged alternately and repeatedly with the plurality of second light-shielding portions 43 in the X-axis direction. That is, the second light-shielding portion 43 is interposed between the two pairs of the first electrodes 41 and the two pairs of the second electrodes 42 that are adjacent to each other with an interval in the X-axis direction. A first electrode 41 and a second electrode 42 are interposed between two second light-shielding portions 43 adjacent to each other with a gap therebetween in the X-axis direction.

[0047] 12, the first electrode 41 is connected to the drain electrode 27C through a second contact hole CH2 provided in the gate insulating film 32, the first interlayer insulating film 33, and the second interlayer insulating film 34 that are interposed between the first electrode 41 and the drain electrode 27C to be connected. The second contact hole CH2 is disposed at a position overlapping both one end of the first electrode 41 and the other end of the drain electrode 27C, and is provided in communication with the gate insulating film 32, the first interlayer insulating film 33, and the second interlayer insulating film 34.

[0048] As shown in FIG. 12, the second electrode 42 is connected to the first electrode 41 through an opening 35A provided in the first planarization film 35 interposed between the second electrode 42 and the first electrode 41 to be connected. The opening 35A is arranged at a position overlapping both one end of the second electrode 42 and the other end of the first electrode 41, and is provided penetrating the first planarization film 35 along the Z-axis direction. The opening 35A is also arranged to overlap the gate electrode 27A, the semiconductor portion 27D, and the first light-shielding portion 40 in a plan view. As shown in FIG. 13, the opening 35A is provided in a portion of the first planarization film 35 other than the portion overlapping both the first electrode 41 and the second electrode 42. That is, the opening 35A is provided extending along the X-axis direction so as to cross the first electrodes 41 and the second electrodes 42 arranged at intervals in the X-axis direction. The opening 35A overlaps most of the gate wiring 25 in a plan view, and has a length that covers almost the entire length of the display area AA in the X-axis direction. The width of the opening 35A is slightly smaller than the width of the gate wiring 25, and both side edges of the gate wiring 25 do not overlap the opening 35A. The opening 35A is arranged to overlap all of the gate electrodes 27A, semiconductor parts 27D, source wiring 26, first light-shielding parts 40, and second light-shielding parts 43 that are arranged along the X-axis direction, as well as all of the first electrodes 41 and second electrodes 42 that are arranged along the X-axis direction, in a plan view. In addition, one end of the pixel electrode 28 (the right side in FIG. 12, the upper side in FIG. 11) is connected to the other end of the second electrode 42 in a manner that directly contacts it from the upper layer side.

[0049] In the array substrate 21 according to this embodiment, as shown in FIG. 12, an insulating portion 44 is provided in the opening 35A of the first planarization film 35. The insulating portion 44 is made of the second planarization film 36 located on the upper layer side of the second transparent electrode film forming the second electrode 42, and is provided in a form that fills (fills) the opening 35A. Therefore, the insulating portion 44 covers the first electrode 41 and the second electrode 42 in the opening 35A. The pixel electrode 28, the third interlayer insulating film 37, and the common electrode 30 located on the upper layer side of the second planarization film 36 are planarized by this insulating portion 44. The second planarization film 36 is not formed outside the opening 35A in the display area AA. As a result, the second planarization film 36 does not intervene between the overlapping portion of the second electrode 42 made of the second transparent electrode film and the pixel electrode 28 made of the third transparent electrode film, and therefore the second electrode 42 and the pixel electrode 28 are directly in contact with each other to be connected to each other.

[0050] Specifically, as shown in FIG. 13, the insulating portion 44 is provided so as to fill the entire width and length of the opening 35A extending along the X-axis direction. That is, the insulating portion 44 extends along the X-axis direction, crosses the first electrodes 41 and the second electrodes 42 arranged at intervals in the X-axis direction, and is arranged so as to overlap a part of each of the first electrodes 41 and the second electrodes 42. The insulating portion 44 overlaps most of the gate wiring 25 and the first light-shielding portion 40 in a plan view, and has a length that covers almost the entire length of the display area AA in the X-axis direction. The width and length of the insulating portion 44 are almost the same as those of the opening 35A. The width of the insulating portion 44 is slightly smaller than the width of the gate wiring 25, and both side edges of the gate wiring 25 do not overlap the insulating portion 44. The insulating portion 44 is arranged to overlap all the gate electrodes 27A and semiconductor portions 27D arranged along the X-axis direction in a plan view, in addition to all the first electrodes 41 and second electrodes 42 arranged along the X-axis direction. The insulating portion 44 crosses the source wirings 26 and the second light shielding portions 43 arranged at intervals in the X-axis direction, and is arranged to overlap parts of the source wirings 26 and the second light shielding portions 43. The insulating portion 44 is also arranged to overlap the other end of the pixel electrode 28 (left side in FIG. 12, lower side in FIG. 11) in a plan view. In this way, the insulating portion 44 is provided to extend along the X-axis direction together with the opening 35A and cross the first electrodes 41 and the second electrodes 42, so that the following effects can be obtained compared to the case where a plurality of openings and insulating portions are provided at intervals in the X-axis direction. That is, even if a photomask used to pattern the openings 35A and the insulating portions 44 during manufacturing is misaligned in the X-axis direction, it is possible to prevent the openings 35A and the insulating portions 44 from being provided in a misaligned state in the X-axis direction. This is particularly suitable for the case where the arrangement intervals of the openings 35A and the insulating portions 44 in the X-axis direction become narrower as the definition increases.

[0051] As shown in FIG. 12 and FIG. 13, the insulating portion 44 includes a high-level portion 44A that is higher than the edge of the opening 35A of the first planarization film 35. The high-level portion 44A is arranged at a position overlapping the gate electrode 27A and the semiconductor portion 27D of the TFT 27. The high-level portion 44A is provided in a substantially circular range that is substantially concentric with the center of the overlapping portion of the first electrode 41 and the second electrode 42 in a plan view in the insulating portion 44. The high-level portion 44A has a diameter that is approximately the width dimension of the insulating portion 44. Therefore, in the insulating portion 44 that extends along the X-axis direction and has a band shape, the high-level portion 44A is provided partially and has an island shape (dot shape) in a plan view. The high-level portions 44A are arranged side by side with a plurality of intervals in the X-axis direction, and are arranged sandwiched between two second light-shielding portions 43 in the X-axis direction. Specifically, the high-order portion 44A is disposed so as to overlap the gate electrode 27A of the TFT 27 (e.g., the TFT 27 connected to the pixel electrodes 28 constituting the green and red pixels) among the multiple TFTs 27 aligned along the X-axis direction and not overlapping the spacer 39. In addition, the other end of the pixel electrode 28 is disposed so as to ride on the high-order portion 44A.

[0052] According to the high-level portion 44A having such a configuration, the pixel electrodes 28, the third interlayer insulating film 37, the common electrode 30, and the alignment film 38, which are located above the first planarization film 35, are higher in the portions that overlap the high-level portion 44A in a plan view than the other portions. Therefore, in the process of forming the alignment film 38 in the manufacturing process of the array substrate 21, when the material of the alignment film 38 is applied to the upper side of the common electrode 30 and the second light-shielding portion 43, the material of the alignment film 38 is likely to flow from the position on the high-level portion 44A to the position other than the high-level portion 44A, and the material of the alignment film 38 is unlikely to accumulate on the insulating portion 44. As a result, the material of the alignment film 38 is unlikely to be insufficient at positions other than the insulating portion 44, and therefore the thickness of the alignment film 38 is unlikely to be uneven at positions other than the insulating portion 44. In this embodiment, since the high-level portion 44A is sandwiched between the two second light-shielding portions 43 in the X-axis direction, when forming the alignment film 38, the material of the alignment film 38 can be made to flow from the high-level portion 44A side toward the two second light-shielding portions 43 sandwiching the high-level portion 44A in the X-axis direction. As a result, a large amount of material is supplied to the portions of the alignment film 38 that overlap with the two second light-shielding portions 43 sandwiching the high-level portion 44A, improving the coverage of the alignment film 38 with respect to each second light-shielding portion 43. This makes it possible to prevent the portions of the alignment film 38 located on the second light-shielding portions 43 from being locally thinned. As described above, since the unevenness in the thickness of the alignment film 38 is suppressed in the array substrate 21, alignment defects are less likely to occur in the liquid crystal molecules contained in the liquid crystal layer 22. This improves the display quality.

[0053] As shown in Figs. 12 and 13, the high-level portion 44A is configured to gradually become higher from the outer circumferential end side toward the center side of the insulating portion 44. The high-level portion 44A is configured to be highest at the center position in a plan view and lowest at the outer circumferential end position. In this way, when forming the alignment film 38, the material of the alignment film 38 is more likely to flow radially from the center side toward the outer circumferential end side of the insulating portion 44. This allows the material of the alignment film 38 to be smoothly supplied to positions other than on the insulating portion 44, making it less likely that the alignment film 38 will have uneven thickness at positions other than on the insulating portion 44.

[0054] As shown in FIG. 12 and FIG. 13, the high-level portion 44A has a height H1 from the edge of the opening 35A in the first planarization film 35, which is smaller than the thickness of the alignment film 38. This height H1 is the dimension along the Z-axis direction from the edge of the opening 35A in the first planarization film 35 to the highest position (center position in a plan view) in the high-level portion 44A. Specifically, the height H1 of the high-level portion 44A is set to be in the range of, for example, about 0.1 μm to 0.5 μm. In this way, by making the height of the high-level portion 44A smaller than the thickness of the alignment film 38, the material of the alignment film 38 is more likely to exist on the insulating portion 44 when the alignment film 38 is formed. Specifically, the alignment film 38 is formed continuously on the high-level portion 44A, although its thickness is slightly thinner than that of the other positions than the high-level portion 44A. This makes it difficult for the alignment film 38 to be interrupted on the insulating portion 44.

[0055] 7 and 13, a bump 44B is provided at a position of the insulating section 44 that overlaps with the spacer 39 of the counter substrate 20. The bump 44B is provided so as to be higher than the edge of the opening 35A of the first planarization film 35. The bump 44B is arranged at a position that overlaps with the gate electrode 27A and the semiconductor section 27D of the TFT 27. The bump 44B is provided in a substantially circular range that is substantially concentric with the center of the overlapping portion of the first electrode 41 and the second electrode 42 in a plan view in the insulating section 44. The bump 44B has a diameter approximately equal to the width dimension of the insulating section 44. Therefore, the bump 44B is provided partially in the insulating section 44 that is in a strip shape extending along the X-axis direction, and is island-shaped in a plan view. The bumps 44B are arranged in a line with a gap in the X-axis direction, and are sandwiched between two second light-shielding parts 43 in the X-axis direction. Specifically, the bumps 44B are arranged overlapping the gate electrodes 27A of the TFTs 27 (e.g., the TFTs 27 connected to the pixel electrodes 28 constituting the blue pixels having the lowest visibility) that overlap the spacer 39 among the multiple TFTs 27 arranged along the X-axis direction. With this configuration, the spacer 39 can be brought into contact with the part of the inner surface of the array substrate 21 that overlaps with the bumps 44B included in the insulating part 44. This allows the distance (cell gap) between the array substrate 21 and the counter substrate 20 that face each other to be well maintained. When manufacturing the array substrate 21, the insulating part 44 including the bumps 44B can be provided in addition to the high-level part 44A by patterning the second planarization film 36, so that the number of steps can be reduced compared to the case where the bumps are provided separately from the insulating part 44.

[0056] As shown in FIG. 13, the height H2 of the bump 44B from the edge of the opening 35A in the first planarization film 35 is greater than the height H1 of the high-level portion 44A. That is, the high-level portion 44A is formed to be lower than the bump 44B. Specifically, the height H2 of the bump 44B is set to, for example, about 1 μm. Compared to a case in which the high-level portion is set to a height equal to or greater than that of the bump 44B, the step between the insulating portion 44 and the edge of the opening 35A in the first planarization film 35 is reduced. This makes it difficult for pattern defects to occur in the pixel electrode 28 that is disposed so as to ride on the high-level portion 44A.

[0057] 13, the first light-shielding portion 40 extends along the X-axis direction and overlaps with the insulating portion 44, so that even if poor alignment occurs in the portion of the alignment film 38 that overlaps with the insulating portion 44, the first light-shielding portion 40 can block light. This makes it possible to prevent inadvertent light leakage.

[0058] The liquid crystal display device 10 according to this embodiment has the above-mentioned structure, and its manufacturing method will be described below. The liquid crystal display device 10 is manufactured by assembling the liquid crystal panel 11 and the backlight device 12, which are manufactured separately. The manufacturing method of the liquid crystal panel 11 includes a counter substrate manufacturing process (CF substrate manufacturing process) for manufacturing the counter substrate 20, an array substrate manufacturing process (substrate manufacturing process) for manufacturing the array substrate 21, and a bonding process for bonding the manufactured counter substrate 20 and array substrate 21 together. The array substrate manufacturing process will be described below.

[0059] The array substrate manufacturing process includes a first step of depositing and patterning a first metal film, a second step of depositing a base coat film 31, a third step of depositing and patterning a semiconductor film, a fourth step of depositing a gate insulating film 32, a fifth step of depositing and patterning a second metal film, a sixth step of selectively lowering the resistance of the semiconductor film using the patterned second metal film as a mask, a seventh step of depositing and patterning a first interlayer insulating film 33, an eighth step of depositing and patterning a third metal film, and a eighth step of depositing and patterning a second interlayer insulating film 34. The method includes at least a 9th step, a 10th step of depositing and patterning a first transparent electrode film, an 11th step of depositing and patterning a first planarization film 35, a 12th step of depositing and patterning a second transparent electrode film, a 13th step of depositing and patterning a second planarization film 36, a 14th step of depositing and patterning a third transparent electrode film, a 15th step of depositing a third interlayer insulating film 37, a 16th step of depositing and patterning a fourth transparent electrode film, a 17th step of depositing and patterning a light-shielding film, and an 18th step of depositing an alignment film 38.

[0060] Among the steps, the first light-shielding portion 40 is formed through the first step. The semiconductor portion 27D is formed through the third step. The gate wiring 25 and the gate electrode 27A are formed through the fifth step. The source electrode 27B and the drain electrode 27C are formed through the sixth step. The first contact hole CH1 is formed through the seventh step. The source wiring 26 is formed through the eighth step. The second contact hole CH2 is formed through the ninth step. The first electrode 41 is formed through the tenth step. The opening 35A is formed through the eleventh step. The second electrode 42 is formed through the twelfth step. The insulating portion 44 (including the high-level portion 44A and the bump 44B) is formed through the thirteenth step. The pixel electrode 28 is formed through the fourteenth step. The common electrode 30 is formed through the sixteenth step. The second light-shielding portion 43 is formed through the seventeenth step.

[0061] The term "patterning" refers to the processing of a film based on a general photolithography method. Specifically, a photoresist film is formed on the film to be processed, the photoresist film is exposed to light by an exposure device through a photomask having a predetermined opening pattern, the photoresist film is developed, and etching is performed through the developed photoresist film, thereby processing the film to be processed, i.e., patterning is performed.

[0062] Among the steps, the 13th step will be described in detail. In the 13th step, as shown in FIG. 14, the second planarization film 36 is formed on the second transparent electrode film patterned through the previous 12th step (film formation step). After that, the second planarization film 36 is exposed to light using an exposure device and a photomask 60 (exposure step). The second planarization film 36 is made of an organic material having positive photosensitivity. Here, the photomask 60 will be described. As shown in FIG. 15, the photomask 60 includes a transparent base material 61 having sufficiently high light transmittance and a light shielding film 62 formed on the main surface of the base material 61. The light shielding film 62 shields the exposure light from the light source of the exposure device and has a partial opening 63. In FIG. 15, the exposure light irradiated to the second planarization film 36 is represented by a downward arrow.

[0063] The photomask 60 used in the exposure step included in the 13th step is a so-called gray-tone mask. Specifically, as shown in FIG. 15, a plurality of slits 64 are formed in a part of the light-shielding film 62 constituting the photomask 60, the resolution of which is equal to or less than the resolution of the exposure device. In the portion of the light-shielding film 62 where the slits 64 are formed, the transmittance of the exposure light is higher than the transmittance of the exposure light in the light-shielding film 62 (almost 0%), and is set to, for example, about 10% to 70%. The transmittance of the exposure light in the portion of the light-shielding film 62 where the slits 64 are formed varies depending on the distribution density of the slits 64, and the transmittance of the exposure light tends to increase as the distribution density of the slits 64 increases. The above-mentioned opening 63 is an opening that is equal to or greater than the resolution of the exposure device, and the transmittance of the exposure light in the opening 63 is set to be almost 100%.

[0064] 15, the photomask 60 has a light-shielding region A1 where the light-shielding film 62 is formed, a light-transmitting region A2 where the openings 63 are formed, and a semi-transmitting region A3 where the slits 64 are formed. The transmittance of the exposure light in the semi-transmitting region A3 is higher than the transmittance in the light-shielding region A1 and lower than the transmittance in the transmissive region A2. In this embodiment, the photomask 60 is arranged such that the light-shielding region A1 overlaps with the planned formation positions of the bumps 44B in a plan view, the semi-transmitting region A3 overlaps with the planned formation positions of the parts of the insulating portion 44 excluding the bumps 44B in a plan view, and the transmissive region A2 overlaps with the planned formation positions of the components other than the insulating portion 44 in a plan view. Here, the semi-transmitting region A3 includes a first semi-transmitting region that overlaps in plan view with the planned formation position of the high-level portion 44A of the insulating portion 44, and a second semi-transmitting region that overlaps in plan view with the planned formation position of the portion of the insulating portion 44 excluding the high-level portion 44A and the bump 44B. FIG. 15 illustrates the first semi-transmitting region. In the first semi-transmitting region, the distribution density of the slits 64 is lower than that of the second semi-transmitting region, and the transmittance of the exposure light is lower than that of the second semi-transmitting region. The first semi-transmitting region is configured such that the distribution density of the slits 64 gradually decreases from the center to the outer peripheral edge. In other words, the first semi-transmitting region is configured such that the distribution density of the light-shielding film 62 gradually increases from the center to the outer peripheral edge. As a result, the amount of transmitted light in the first semi-transmitting region gradually increases from the center to the outer peripheral edge. In the second semi-transmitting region, the distribution density of the slits 64 is made substantially constant over the entire region, so that the amount of transmitted light through the second semi-transmitting region is made substantially constant over the entire region.

[0065] In the exposure step included in the 13th step, as shown in FIG. 15, when the exposure light emitted from the light source of the exposure device is irradiated onto the second planarization film 36 through the photomask 60 having the above-mentioned configuration, the second planarization film 36 is selectively exposed. In detail, the exposure amount is the largest in the portion of the second planarization film 36 overlapping with the transparent region A2 of the photomask 60, the exposure amount is the next largest in the portion of the second planarization film 36 overlapping with the semi-transparent region A3 of the photomask 60, and the portion of the second planarization film 36 overlapping with the light-shielding region A1 of the photomask 60 is hardly exposed. In the portion of the second planarization film 36 overlapping with the first semi-transparent region of the semi-transparent region A3, the exposure amount gradually increases from the center to the outer circumferential edge. In the portion of the second planarization film 36 overlapping with the second semi-transparent region of the semi-transparent region A3, the exposure amount is almost constant over the entire region.

[0066] In the 13th step, the second planarization film 36 is developed after the exposure step (development step). Then, as shown in FIG. 16, the exposed portion of the second planarization film 36 is selectively removed according to the amount of exposure. The second planarization film 36 that has been subjected to the development step provides an insulating portion 44 that is disposed so as to fill the opening 35A. The insulating portion 44 provided in the 13th step includes a high-level portion 44A that is gradually higher from the outer circumferential end side toward the center side, and a bump 44B that is higher than the high-level portion 44A.

[0067] As described above, the array substrate 21 of this embodiment comprises a first electrode 41, a first planarization film (first insulating film) 35 arranged on the upper side of the first electrode 41 and having an opening 35A at a position overlapping at least with the first electrode 41, a second electrode 42 arranged on the upper side of the first planarization film 35, overlapping with the first electrode 41 at least within the opening 35A and connected to the first electrode 41, a second planarization film (second insulating film) 36 arranged on the upper side of the second electrode 42, and an alignment film 38 arranged on the upper side of the second planarization film 36, and the second planarization film 36 has an insulating portion 44 arranged in the opening 35A, and the insulating portion 44 includes a higher portion 44A that is higher than the opening edge of the opening 35A in the first planarization film 35.

[0068] The second electrode 42 is connected to the first electrode 41 through the opening 35A of the first planarization film 35. The insulating portion 44 of the second planarization film 36 provided in the opening 35A of the first planarization film 35 includes a high portion 44A that is higher than the opening edge of the opening 35A of the first planarization film 35, so that the material of the alignment film 38 is less likely to accumulate on the insulating portion 44 when the alignment film 38 is formed, compared to the conventional method. As a result, a situation in which the material of the alignment film 38 is insufficient at positions other than on the insulating portion 44 is less likely to occur, so that the alignment film 38 is less likely to have uneven thickness at positions other than on the insulating portion 44.

[0069] Moreover, the first electrodes 41 and the second electrodes 42 are arranged in a line with a gap between them in the first direction, and the openings 35A and the insulating parts 44 are both provided extending along the first direction and crossing the first electrodes 41 and the second electrodes 42. In this way, the openings 35A and the insulating parts 44 are both provided extending along the first direction and crossing the first electrodes 41 and the second electrodes 42, so that the following effect can be obtained compared to the case where the openings and the insulating parts are provided with a gap between them in the first direction. That is, even if the photomask used to pattern the openings 35A and the insulating parts 44 during manufacturing is misaligned in the first direction, the openings 35A and the insulating parts 44 are prevented from being provided in a state of being misaligned in the first direction. This is particularly suitable when the arrangement interval between the openings 35A and the insulating parts 44 in the first direction becomes narrower with the increase in resolution.

[0070] The liquid crystal display further includes a first light-shielding portion 40 made of a light-shielding material and disposed below the first electrode 41, the first light-shielding portion 40 extending along the first direction and disposed overlapping the insulating portion 44. In this manner, the first light-shielding portion 40 extending along the first direction is disposed overlapping the insulating portion 44 extending along the first direction, so that even if poor alignment occurs in the portion of the alignment film 38 that overlaps the insulating portion 44, the first light-shielding portion 40 can block light, thereby preventing inadvertent light leakage.

[0071] Further, the alignment film 38 includes a second light-shielding portion 43 made of a light-shielding material and disposed on the lower layer side of the alignment film 38. A plurality of the second light-shielding portions 43 are arranged at intervals so as to sandwich the first electrode 41 and the second electrode 42 in the first direction, and the high-order portion 44A is disposed sandwiched between the two second light-shielding portions 43 in the first direction. In this manner, it is possible to prevent light transmitted through the first electrode 41 and the second electrode 42 sandwiched between the two second light-shielding portions 43 from leaking to the first electrode 41 and the second electrode 42 adjacent to each other across the second light-shielding portion 43 in the first direction. When forming the alignment film 38, the material of the alignment film 38 can be made to flow in the first direction from the high-order portion 44A side toward the two second light-shielding portions 43 side sandwiching the high-order portion 44A. This makes it possible to prevent the portions of the alignment film 38 that overlap with the two second light-shielding portions 43 that sandwich the high-level portion 44A from becoming locally thin.

[0072] Moreover, the height H1 of the high-level portion 44A from the edge of the opening 35A of the first planarization film 35 is smaller than the film thickness of the alignment film 38. In this manner, by making the height H1 of the high-level portion 44A smaller than the film thickness of the alignment film 38, the material of the alignment film 38 is more likely to be present on the insulating portion 44 when the alignment film 38 is formed. As a result, the alignment film 38 is less likely to be interrupted on the insulating portion 44.

[0073] Moreover, the high portion 44A is configured to gradually become higher from the outer circumferential end side toward the center side of the insulating portion 44. In this way, when forming the alignment film 38, the material of the alignment film 38 can easily flow from the center side toward the outer circumferential end side of the insulating portion 44. This allows the material of the alignment film 38 to be smoothly supplied to positions other than on the insulating portion 44, making it more difficult for thickness unevenness of the alignment film 38 to occur in positions other than on the insulating portion 44.

[0074] Moreover, the liquid crystal display device 10 according to this embodiment includes the above-described array substrate 21, a counter substrate 20 disposed opposite the array substrate 21, and a liquid crystal layer 22 disposed between the array substrate 21 and the counter substrate 20. In such a liquid crystal display device 10, since unevenness in the thickness of the alignment film 38 is suppressed in the array substrate 21, alignment defects are less likely to occur in the liquid crystal molecules contained in the liquid crystal layer 22. This improves the display quality.

[0075] The counter substrate 20 is provided with a spacer 39 protruding toward the array substrate 21, and the first electrodes 41 and the second electrodes 42 are arranged in a line with a gap between them in the first direction, and the opening 35A and the insulating portion 44 extend along the first direction and are provided across the first electrodes 41 and the second electrodes 42, and the insulating portion 44 includes a bump 44B that is higher than the opening edge of the opening 35A in the first planarization film 35 and is arranged to overlap the spacer 39. The spacer 39 provided on the counter substrate 20 and protruding toward the array substrate 21 can be brought into contact with a portion of the inner surface of the array substrate 21 that overlaps with the bump 44B included in the insulating portion 44. This allows the distance (cell gap) between the array substrate 21 and the counter substrate 20, which face each other, to be well maintained. When manufacturing the array substrate 21, the second planarization film 36 can be patterned to provide an insulating portion 44 including a bump 44B in addition to a high-level portion 44A, thereby enabling a reduction in labor hours, etc., compared to the case where the bump is provided separately from the insulating portion 44.

[0076] Moreover, the high-level portion 44A is lower than the bump 44B. Compared to a case in which the high-level portion is equal to or higher in height than the bump 44B, the step between the insulating portion 44 and the edge of the opening 35A in the first planarization film 35 is reduced. As a result, for example, when an electrode or the like is provided on the insulating portion 44, pattern defects are less likely to occur in the electrode or the like.

[0077] <Embodiment 2> A second embodiment will be described with reference to Fig. 17 to Fig. 19. In this second embodiment, the configurations of an alignment film 138 and a high-level portion 144A are changed. Note that a duplicated description of the structure, action, and effect similar to those of the first embodiment will be omitted.

[0078] As shown in FIG. 17 and FIG. 18, the high-level portion 144A according to this embodiment has a height H101 from the opening edge of the opening 135A of the first planarization film 135 that is larger than the height H1 (see FIG. 12) in the first embodiment and is larger than the thickness of the alignment film 138. Specifically, the height H101 of the high-level portion 144A is set to be in the range of about 0.1 μm to 0.5 μm, for example. In this way, by making the height H101 of the high-level portion 144A larger than the thickness of the alignment film 138, the material of the alignment film 138 is less likely to exist on the insulating portion 144 when the alignment film 138 is formed. In this embodiment, the alignment film 138 is almost not formed at a position where it overlaps with the high-level portion 144A in a plan view. As a result, the material of the alignment film 138 can be supplied more to positions other than the insulating portion 144, so that the alignment film 138 is less likely to have uneven thickness at positions other than the insulating portion 144.

[0079] Next, the configuration of the photomask 160 used in the exposure step included in the 13th step of the array substrate manufacturing process will be described. As shown in FIG. 19, the first semi-transmitting region of the semi-transmitting region A103 of the photomask 160 has a lower distribution density of the slits 164 over the entire region than the distribution density of the slits 64 in the first semi-transmitting region described in the above-mentioned embodiment 1 (see FIG. 15). Specifically, the distribution density of the slits 164 at the center of the first semi-transmitting region is lower than the distribution density of the slits 64 at the center of the first semi-transmitting region described in the above-mentioned embodiment 1, and the distribution density of the slits 164 at the outer periphery of the first semi-transmitting region is lower than the distribution density of the slits 64 at the outer periphery of the first semi-transmitting region described in the above-mentioned embodiment 1. When the second planarization film 136 is exposed using such a photomask 160, the exposure amount of the part of the second planarization film 136 overlapping with the first semi-transmitting region is smaller than the exposure amount in the first embodiment. As a result, the high-level portion 144A provided by developing the second planarization film 136 is higher than the high-level portion 44A described in the first embodiment.

[0080] As described above, according to this embodiment, the height H101 of the high-level portion 144A from the edge of the opening 135A of the first planarization film 135 is greater than the film thickness of the alignment film 138. In this way, by making the height H101 of the high-level portion 144A greater than the film thickness of the alignment film 138, the material of the alignment film 138 is less likely to exist on the insulating portion 144 when the alignment film 138 is formed, and more of the material of the alignment film 138 can be supplied to positions other than the insulating portion 144. As a result, unevenness in the film thickness of the alignment film 138 is less likely to occur in positions other than the insulating portion 144.

[0081] <Embodiment 3> A third embodiment will be described with reference to Fig. 20 to Fig. 22. In this third embodiment, a configuration of a higher part 244A is changed from that of the first embodiment. Note that a duplicated description of the structure, action, and effect similar to those of the first embodiment will be omitted.

[0082] As shown in FIG. 20 and FIG. 21, the high-level portion 244A according to this embodiment has a substantially flat upper surface. That is, the high-level portion 244A has a substantially constant height H201 from the edge of the opening 235A of the first planarization film 235. In this way, the alignment film 238 is planarized on the insulating portion 244, and in particular, the portion of the alignment film 238 that overlaps with the high-level portion 244A becomes flat. Also, as in the first embodiment, the high-level portion 244A has a height H201 from the edge of the opening 235A of the first planarization film 235 that is smaller than the film thickness of the alignment film 238. Therefore, as in the first embodiment, the alignment film 238 exists without interruption even on the high-level portion 244A. Specifically, the height H201 of the high-level portion 244A is set to be, for example, in the range of about 0.1 μm to 0.5 μm.

[0083] Next, the configuration of the photomask 260 used in the exposure process included in the 13th step of the array substrate manufacturing process will be described. As shown in FIG. 22, the first semi-transmitting region of the semi-transmitting region A203 of the photomask 260 has a substantially constant distribution density of the slits 264 over the entire region. Therefore, the exposure amount is substantially constant over the entire region of the second planarization film 236 in the portion overlapping the first semi-transmitting region. Note that the distribution density of the slits 264 in the first semi-transmitting region is lower than the distribution density of the slits 264 in the second semi-transmitting region, as in the first embodiment. When the second planarization film 236 is exposed using such a photomask 260, the exposure amount to the portion of the second planarization film 236 overlapping the first semi-transmitting region is substantially constant over the entire region. As a result, the high-level portion 244A provided by developing the second planarization film 236 has a substantially constant height H201 and a flat upper surface.

[0084] As described above, according to this embodiment, the upper surface of the higher portion 244A is made flat. In this way, the alignment film 238 on the insulating portion 244 is flattened.

[0085] <Embodiment 4> A fourth embodiment will be described with reference to Fig. 23 to Fig. 25. In this fourth embodiment, the configurations of the alignment film 338 and the high-order portion 344A are changed from those of the third embodiment. Note that a duplicated description of the structure, action, and effect similar to those of the third embodiment will be omitted.

[0086] As shown in Figs. 23 and 24, the high-level portion 344A according to this embodiment has a height H301 from the edge of the opening 335A of the first planarization film 335 that is greater than the height H201 (see Fig. 23) in the third embodiment and is greater than the thickness of the alignment film 338. Therefore, as in the second embodiment, the alignment film 338 is not formed at a position where it overlaps with the high-level portion 344A in a plan view. This makes it more difficult for the alignment film 338 to have uneven thickness in positions other than on the insulating portion 344. Specifically, the height H301 of the high-level portion 344A is set to be in the range of about 0.1 µm to 0.5 µm, for example.

[0087] Next, the configuration of the photomask 360 used in the exposure step included in the 13th step of the array substrate manufacturing process will be described. As shown in FIG. 25, the first semi-transmitting region of the semi-transmitting region A303 of the photomask 360 has a lower distribution density of the slits 364 over the entire region than the distribution density of the slits 264 in the first semi-transmitting region described in the above-mentioned third embodiment (see FIG. 22). When the second planarization film 336 is exposed using such a photomask 360, the exposure amount of the portion of the second planarization film 336 overlapping with the first semi-transmitting region becomes smaller than the exposure amount in the third embodiment. As a result, the high-level portion 344A provided by developing the second planarization film 336 becomes higher than the high-level portion 244A described in the third embodiment.

[0088] <Embodiment 5> A fifth embodiment will be described with reference to Fig. 26 to Fig. 28. In the fifth embodiment, the configuration of the higher part 444A is changed from that of the second embodiment. Note that the same structure, action, and effect as those of the second embodiment will not be described again.

[0089] As shown in FIG. 26 and FIG. 27, the high-level portion 444A according to the present embodiment is configured to be gradually higher from the center side toward the outer circumferential end side of the insulating portion 444. The high-level portion 444A is configured to be lowest at the center position in a plan view and highest at the outer circumferential end position. In this way, when forming the alignment film 38, the material of the alignment film 38 is likely to flow from the outer circumferential end side toward the center side of the insulating portion 44. This makes it easier for the alignment film 438 to remain at the center side of the insulating portion 444. In addition, the height H401 of the high-level portion 444A from the opening edge of the opening 435A of the first planarization film 435 is greater than the film thickness of the alignment film 438. Specifically, the height H401 of the high-level portion 444A is set to be in the range of, for example, about 0.1 μm to 0.5 μm. In this way, by making the height H401 of the high-level portion 444A larger than the film thickness of the alignment film 438, the material of the alignment film 438 is less likely to be present on the insulating portion 444 when the alignment film 438 is formed. In this embodiment, the alignment film 438 is substantially not formed at a position where it overlaps with the high-level portion 444A in a plan view. This allows more material of the alignment film 438 to be supplied to positions other than the insulating portion 444, making it more difficult for thickness unevenness of the alignment film 438 to occur at positions other than the insulating portion 444.

[0090] Next, the configuration of the photomask 460 used in the exposure process included in the 13th step of the array substrate manufacturing process will be described. The first semi-transmitting region of the semi-transmitting region A403 of the photomask 460 is configured so that the distribution density of the slits 464 gradually decreases from the outer circumferential edge toward the center, as shown in FIG. 28. In other words, the first semi-transmitting region is configured so that the distribution density of the light-shielding film 462 gradually increases from the outer circumferential edge toward the center. As a result, the amount of transmitted light in the first semi-transmitting region gradually increases from the outer circumferential edge toward the center. Also, the distribution density of the slits 464 in the first semi-transmitting region is equivalent to that in the above-mentioned embodiment 2, and is lower throughout the entire region than the distribution density of the slits 64 in the first semi-transmitting region described in embodiment 1 (see FIG. 15). When the second planarization film 436 is exposed using the photomask 460 having such a configuration, the amount of exposure gradually increases from the outer circumferential edge toward the center in the portion of the second planarization film 436 that overlaps with the first semi-transmitting region. When the second planarization film 436 is developed after the exposure step, the exposed portion of the second planarization film 436 is selectively removed according to the amount of exposure, so that an insulating portion 444 including a high portion 444A that gradually becomes higher from the center toward the outer circumferential edge is provided, as shown in Figs. 26 and 27.

[0091] As described above, according to this embodiment, the high-level portion 444A is configured to become gradually lower from the outer circumferential end side toward the center side of the insulating portion 444. In this way, the alignment film 438 is more likely to remain on the center side of the insulating portion 444.

[0092] <Embodiment 6> A sixth embodiment will be described with reference to Fig. 29 to Fig. 31. In this sixth embodiment, a configuration of a higher part 544A is changed from that of the fifth embodiment. Note that a duplicated description of the structure, action, and effect similar to those of the fifth embodiment will be omitted.

[0093] 29 and 30, the high-order portion 544A according to this embodiment has a height H501 from the edge of the opening 535A of the first planarization film 535 that is smaller than the height H401 (see FIG. 26) in the fifth embodiment and is smaller than the thickness of the alignment film 538. Specifically, the height H501 of the high-order portion 544A is set to be in the range of about 0.1 μm to 0.5 μm, for example. Therefore, the alignment film 538 exists uninterrupted even on the high-order portion 544A, similarly to the first and third embodiments.

[0094] Next, the configuration of the photomask 560 used in the exposure process included in the 13th step of the array substrate manufacturing process will be described. As shown in FIG. 31, the first semi-transmitting region of the semi-transmitting region A503 of the photomask 560 has a higher distribution density of the slits 564 over the entire region than the distribution density of the slits 464 in the first semi-transmitting region described in the above-mentioned embodiment 5 (see FIG. 28). Specifically, the distribution density of the slits 564 at the center of the first semi-transmitting region is higher than the distribution density of the slits 464 at the center of the first semi-transmitting region described in the above-mentioned embodiment 5, and the distribution density of the slits 564 at the outer peripheral edge of the first semi-transmitting region is higher than the distribution density of the slits 464 at the outer peripheral edge of the first semi-transmitting region described in the above-mentioned embodiment 5. When the second planarization film 536 is exposed using such a photomask 560, the exposure amount of the part of the second planarization film 536 overlapping with the first semi-transmitting region is greater than the exposure amount in the embodiment 5. As a result, the high-level portion 544A provided by developing the second planarization film 536 is lower than the high-level portion 444A described in the fifth embodiment.

[0095] <Other embodiments> The technology disclosed in this specification is not limited to the embodiments described above and illustrated in the drawings, and the following embodiments, for example, are also included in the technical scope.

[0096] (1) The specific values ​​of the heights of the high portions 44A, 144A, 244A, 344A, 444A, and 544A and the bumps 44B may be changed as appropriate to values ​​other than those mentioned above.

[0097] (2) The high-order portion 44A, 144A, 244A, 344A, 444A, 544A may be provided so as to form a line extending along the X-axis direction in the insulating portion 44, 144, 244, 344, 444. The high-order portion 44A, 144A, 244A, 344A, 444A, 544A having a linear shape in a plan view may be disposed so as to straddle a plurality of first electrodes 41 and a plurality of second electrodes 42.

[0098] (3) The planar shape of the high-level portions 44A, 144A, 244A, 344A, 444A, and 544A may be a triangle, a rectangle, a polygon having pentagons or more, an ellipse, a semicircle, or the like, other than a circle.

[0099] (4) The specific cross-sectional shapes of the higher portions 44A, 144A, 244A, 344A, 444A, and 544A may be appropriately changed from those shown in the drawings.

[0100] (5) The number and ratio of the high-level portions 44A, 144A, 244A, 344A, 444A, and 544A and the bumps 44B can be appropriately changed to other than those shown in the drawings. For example, the bumps 44B may be provided at a ratio of one for every four or more pixels, or one for every two or less pixels. In this case, the ratio of the high-level portions 44A, 144A, 244A, 344A, 444A, and 544A may be changed so as to be inversely correlated with the ratio of the bumps 44B.

[0101] (6) The insulating portion 44, 144, 244, 344, 444 may not include the bump 44B. In that case, the bump 44B may be formed of an insulating film (for example, the first planarization film 35, 135, 235, 335, 435, 535, etc.) different from the second planarization film 36, 136, 236, 336, 436, 536.

[0102] (7) The openings 35A, 135A, 235A, 335A, 435A, 535A are not limited to a configuration extending along the X-axis direction, and a plurality of openings may be arranged at intervals in the X-axis direction. In this case, the plurality of openings 35A, 135A, 235A, 335A, 435A, 535A arranged at intervals in the X-axis direction may be provided individually for each of the first electrodes 41 and the second electrodes 42, or may be provided so as to cross a plurality of the first electrodes 41 and the second electrodes 42.

[0103] (8) In the exposure step included in the thirteenth step, the photomasks 60, 160, 260, 360, 460, and 560 may be half-tone masks other than gray-tone masks.

[0104] (9) The second planarization film 36, 136, 236, 336, 436, 536 may be made of an organic material having negative photosensitivity.

[0105] (10) The first electrode 41 may be made of a metal film. In that case, a metal film may be formed in place of the first transparent electrode film and then patterned.

[0106] (11) The second electrode 42 may be made of a metal film. In that case, a metal film may be formed and patterned in place of the second transparent electrode film.

[0107] (12) The second light-shielding portion 43 may extend along the Y-axis direction so as to overlap with the source line 26 over substantially the entire length thereof.

[0108] (13) The opposing-side light-shielding portion 20BM of the opposing substrate 20 may be in a vertical stripe shape overlapping with the source wiring 26. Also, the opposing-side light-shielding portion 20BM of the opposing substrate 20 may be in a lattice shape overlapping with both the gate wiring 25 and the source wiring 26.

[0109] (14) The color filter 29 may be provided on the array substrate 21. In other words, the liquid crystal panel 11 may have a COA (Color Filter On Array) structure.

[0110] (15) The number of colors of the color filter 29 may be four or more. The additional color filter 29 may be a yellow color filter that exhibits yellow, a transparent color filter that transmits light in the entire wavelength range, or the like.

[0111] (16) The structure of the TFT 27 may be a bottom gate type, a double gate type, or the like other than the top gate type shown in the drawing.

[0112] (17) Of the pixel electrode 28 and the common electrode 30, the "upper layer electrode" that is the electrode located on the upper layer side may be the pixel electrode 28, and the "lower layer electrode" that is the electrode located on the lower layer side may be the common electrode 30. In this case, a slit is provided in the pixel electrode 28 that is the "upper layer electrode."

[0113] (18) The alignment films 38, 138, 238, 338, 438, and 538 may be subjected to an alignment treatment by rubbing.

[0114] (19) The semiconductor film may be an amorphous silicon thin film or a polycrystalline silicon thin film.

[0115] (20) The display mode of the liquid crystal panel 11 may be VA mode, IPS mode, or the like other than FFS mode.

[0116] (21) The liquid crystal panel 11 may be a reflective or semi-transmissive type other than a transmissive type. When the liquid crystal panel 11 is a reflective type, the backlight device 12 can be omitted.

[0117] (22) In addition to the head mounted display 10 HMD, the present invention can be applied to devices such as head-up displays and projectors that use lenses to enlarge an image displayed on the liquid crystal panel 11. The present invention can also be applied to display devices that do not have a magnification function (such as television receivers, tablet terminals, and smartphones). [Explanation of symbols]

[0118] 10... liquid crystal display device, 20... opposing substrate, 21... array substrate, 22... liquid crystal layer, 35, 135, 235, 335, 435, 535... first planarization film (first insulating film), 35A, 135A, 235A, 335A, 435A, 535A... openings, 36, 136, 236, 336, 436, 536... second planarization film (second insulating film) insulating film), 38, 138, 238, 338, 438, 538... alignment film, 39... spacer, 40... first light-shielding portion, 41... first electrode, 42... second electrode, 43... second light-shielding portion, 44, 144, 244, 344, 444... insulating portion, 44A, 144A, 244A, 344A, 444A, 544A... high-position portion, 44B... bump

Claims

1. A first electrode; a first insulating film disposed on an upper layer side of a first electrode and having an opening at least at a position overlapping the first electrode; a second electrode disposed on an upper layer side of the first insulating film, the second electrode overlapping the first electrode at least in the opening and connected to the first electrode; a second insulating film disposed on an upper layer side of the second electrode; an alignment film disposed above the second insulating film; the second insulating film has an insulating portion provided in the opening, The insulating portion includes a high portion of the first insulating film that is higher than an edge of the opening.

2. The first electrodes and the second electrodes are arranged in a plurality of electrodes spaced apart from each other in a first direction, 2 . The array substrate according to claim 1 , wherein the opening and the insulating portion extend along the first direction and cross a plurality of the first electrodes and a plurality of the second electrodes.

3. a first light-shielding portion disposed below the first electrode and made of a light-shielding material; 3. The array substrate according to claim 2, wherein the first light-shielding portion extends in the first direction and overlaps the insulating portion.

4. a second light-shielding portion disposed on a lower layer side of the alignment film and made of a light-shielding material; a plurality of the second light-shielding portions are arranged at intervals between the first electrode and the second electrode in the first direction; 3. The array substrate according to claim 2, wherein the high-level portion is disposed between two of the second light-shielding portions in the first direction.

5. 5 . The array substrate according to claim 1 , wherein the height of the high portion from an edge of the opening of the first insulating film is greater than a thickness of the alignment film.

6. 5 . The array substrate according to claim 1 , wherein the height of the high portion from an edge of the opening of the first insulating film is smaller than a thickness of the alignment film.

7. 5. The array substrate according to claim 1, wherein the high-level portion is configured to become gradually higher from an outer circumferential edge side toward a center side of the insulating portion.

8. 7. The array substrate according to claim 1, wherein the upper surface of the higher portion is flat.

9. 5. The array substrate according to claim 1, wherein the high-level portion is configured to become gradually lower from an outer circumferential edge side toward a center side of the insulating portion.

10. An array substrate according to any one of claims 1 to 4, A liquid crystal display device comprising: a counter substrate disposed so as to face the array substrate; and a liquid crystal layer disposed between the array substrate and the counter substrate.

11. the opposing substrate is provided with a spacer protruding toward the array substrate, The first electrodes and the second electrodes are arranged in a plurality of electrodes spaced apart from each other in a first direction, the opening and the insulating portion each extend along the first direction and are provided across a plurality of the first electrodes and a plurality of the second electrodes; The liquid crystal display device according to claim 10 , wherein the insulating portion includes a bump that is higher than an edge of the opening of the first insulating film and that is disposed so as to overlap the spacer.

12. The liquid crystal display device according to claim 11 , wherein the high-level portion is lower than the bump.

Images