Active filter device

Abstract

To provide an active filter device in which voltage of a capacitor can be inhibited from reaching an overvoltage detection line during an overload state.SOLUTION: An active filter device includes an inverter unit, a capacitor, a current detection unit, and a control unit 150 that controls the inverter unit. The control unit 150 includes a command value generation unit 151 that generates an output command value d0 of an inverse phase current, a gain generation unit 152 that generates gain G, a computation unit 53 that generates a first command signal d1 obtained by multiplying the output command value d0 by the gain G, a clip unit 154 that generates a second command value d2 by performing clipping processing, and an inverter control unit 155. If the clip unit 154 is performing the clipping processing, the gain generation unit 152 starts gain value reducing processing during the clipping processing so that the gain value of the gain G is reduced by the gain value reducing processing over time.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to an active filter device. [Background technology]

[0002] Known examples of conventional active filter devices include those described in Patent Documents 1 to 5. The active filter device described in Patent Document 1 includes a recorder that records the filter current when the operation of the active filter is stopped by a protection function that protects the active filter from an overcurrent, a decision unit that decides a protection start current based on the filter current, and an adjustment unit that adjusts the compensation rate of harmonic distortion so that the filter current becomes equal to or less than the protection start current when the filter current exceeds the protection start current. With this configuration, the active filter device described in Patent Document 1 can continuously compensate for harmonics in the load current flowing from a three-phase AC power source to a harmonic generating load.

[0003] The active filter device described in Patent Document 2 includes a command output unit that outputs an ON / OFF command to a switching element of the active filter circuit, a duty ratio determination unit that determines whether the duty ratio of the ON / OFF command within a predetermined period is less than a predetermined lower limit value, and a DC voltage adjustment unit that reduces the DC voltage output from the active filter circuit when the duty ratio of the ON / OFF command is less than the predetermined lower limit value. With this configuration, the active filter device described in Patent Document 2 can reduce the DC voltage applied to the electrolytic capacitor connected to the active filter circuit, thereby suppressing ripples while maintaining harmonic suppression performance.

[0004] The active filter device described in Patent Document 3 includes a noise filter, an AC reactor, a U-phase compensation current sensor, a W-phase compensation current sensor, a switching module, an electrolytic capacitor, a DC voltage detection circuit, and an active filter control means. The electrolytic capacitor, like the electrolytic capacitor described in Patent Document 2, is a capacitor for applying a DC voltage to the switching module and transiently charging the compensation current, and is connected to the DC side of the switching module.

[0005] The active filter device described in Patent Document 4 includes an output adjustment unit that throttles down the output of the active filter main circuit when at least one of the output change amount of the first low-pass filter and the output change amount of the second low-pass filter exceeds a predetermined value. With this configuration, the active filter device described in Patent Document 4 can suppress instantaneous active power components and instantaneous reactive power components that are erroneously calculated due to the response time of the first low-pass filter or the second low-pass filter in response to a sudden load fluctuation.

[0006] The active filter device described in Patent Document 5 includes a means for monitoring the power flow direction of the system, and a means for stopping operation of the active filter when the power flow direction is reversed, or a means for reversing a compensation current command value when the power flow direction is reversed. With this configuration, even in the event of reverse power flow, the active filter device described in Patent Document 5 can continue to operate without the device shutting down due to an overcurrent or the compensation performance of the active filter being reduced.

[0007] As described in Patent Documents 1 to 5, an active filter device detects harmonic currents generated from a load and outputs a current of opposite phase to the detected harmonic current to cancel the harmonic current. When the harmonic current becomes larger than expected (when in an overload state), a typical conventional active filter device outputs an opposite-phase current that exceeds the rated current.

[0008] Therefore, conventional active filter devices are provided with a function for clipping the output command value when the device is in an overload state (a clipping function). The clipping process is a process for fixing the current output to an upper limit value when the current output exceeds a preset upper limit value, and fixing the current output to a lower limit value when the current output falls below a preset lower limit value. This clipping process makes it possible to suppress excessive current output.

[0009] However, in an active filter device during clipping, the inverter section outputs a current to the DC end according to the clipping amount. As a result, the voltage of the capacitor connected between the DC ends of the inverter section rises according to the clipping amount. When the capacitor voltage reaches a preset overvoltage detection line, the active filter device's protection function is activated and the operation of the inverter section is stopped (protective stop). [Prior art documents] [Patent documents]

[0010] [Patent Document 1] JP 2019-92287 A [Patent Document 2] JP 2019-205305 A [Patent Document 3] JP 2017-22920 A [Patent Document 4] JP 2000-341857 A [Patent Document 5] Japanese Patent Application Publication No. 11-27863 Summary of the Invention [Problem to be solved by the invention]

[0011] The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide an active filter device that can prevent the capacitor voltage from reaching the overvoltage detection line when an overload condition occurs. [Means for solving the problem]

[0012] In order to solve the above problems, an active filter device according to the present invention comprises: an output terminal connected to a power supply line through which a load current output from the harmonic generating load flows, the output terminal being connected to a three-phase AC power supply and a harmonic generating load; an inverter unit having a pair of DC terminals and an AC terminal connected to the output terminal, the inverter unit outputting an anti-phase current from the AC terminals for suppressing a harmonic current contained in the load current; A capacitor connected between the pair of DC terminals; a current detection unit that detects the anti-phase current and outputs a first signal related to the anti-phase current; a control unit that controls the inverter unit based on the first signal and a second signal related to the load current; An active filter device comprising: The control unit is a command value generating unit that generates an output command value of the antiphase current based on the second signal; a gain generating unit that generates a gain for the output command value based on the first signal; a calculation unit that generates a first command signal by multiplying the output command value by the gain; a clipping unit that performs clipping processing on the first command signal to generate a second command signal; an inverter control unit that generates a control signal for controlling the inverter unit based on the second command signal, The clip portion is a clipping process for setting the signal value of the second command signal to the upper limit signal value when the signal value of the first command signal exceeds a predetermined upper limit signal value, and for setting the signal value of the second command signal to the lower limit signal value when the signal value of the first command signal is less than a predetermined lower limit signal value, The gain generating unit is A gain value reduction process is started during the clip process, and the gain value of the gain is reduced over time by the gain value reduction process.

[0013] In this configuration, the gain generating unit starts the gain value reduction process during the clip process, and the gain value of the gain is reduced over time by the gain value reduction process, so that the signal value of the first command signal obtained by multiplying the output command value by the gain can be reduced to reduce the clipping amount of the clip process. As a result, an excessive voltage rise of the capacitor can be suppressed, and the capacitor voltage can be prevented from reaching the overvoltage detection line.

[0014] In the active filter device, The gain generating unit is A peak value of the antiphase current is compared with a first threshold value that is set in advance, and when the peak value exceeds the first threshold value, the gain value reduction process is performed; Even if the peak value becomes equal to or less than the first threshold value as a result of the gain value reduction process, if a predetermined processing duration has not elapsed since the peak value became equal to or less than the first threshold value, the gain value reduction process can be configured to be continued.

[0015] In the active filter device, The gain generating unit is The gain value reduced by the gain value reduction process can be compared with a preset lower limit value, and if the gain value is less than the lower limit value, a lower limit determination process can be performed to fix the gain value to the lower limit value.

[0016] In the active filter device, The gain generating unit is After the clipping process is completed, a preset gain value fixing time is counted, and during the count, a gain value fixing process is performed to fix the gain value to a fixed value.

[0017] In the active filter device, The gain generating unit is If the peak value of the antiphase current exceeds a preset second threshold during the counting, the count number of the gain value fixing time can be reset and the gain value fixing time can be counted again.

[0018] In the active filter device, The gain generating unit is execute a gain value recovery process for increasing the gain value reduced by the gain value reduction process over time; The amount of change in the gain value during the gain value recovery process may be configured to be smaller than the amount of change in the gain value during the gain value reduction process. Effect of the Invention

[0019] According to the present invention, it is possible to provide an active filter device capable of preventing the capacitor voltage from reaching the overvoltage detection line in an overload state. [Brief description of the drawings]

[0020] [Figure 1] 1 is a diagram showing an active filter device according to the present invention; [Diagram 2] FIG. 2 is a block diagram of a control unit of the active filter device according to the present invention. [Diagram 3] FIG. 11 is a diagram for explaining clipping processing, in which (A) is a waveform diagram of a first command signal input to a clipping unit of the present invention, and (B) is a waveform of a second command signal output from the clipping unit of the present invention. [Figure 4] 4 is a control flow diagram (S1 to S7) performed by a gain generating unit of the active filter device according to the present invention. [Diagram 5] FIG. 4 is a control flow diagram (S8 to S16) performed by a gain generating section of the active filter device according to the present invention. [Figure 6] FIG. 11 is a diagram for explaining an example of the operation of the active filter device according to the present invention, in which (A) is a diagram showing an operating state, (B) is a diagram showing a gain, (C) is a second command signal, and (D) is a diagram showing a voltage between terminals of a capacitor. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an active filter device according to the present invention will now be described with reference to the accompanying drawings.

[0022] 1 shows an active filter device 100 according to one embodiment of the present invention. The active filter device 100 is connected to a power supply line that connects a three-phase AC power supply 1 and a harmonic generating load 2. A load current detector 3 is provided on the power supply line.

[0023] The AC power source 1 is, for example, a commercial power system, and is connected to a harmonic generating load 2 via a three-phase (U-phase, V-phase, W-phase) power line. The AC power source 1 corresponds to the "three-phase AC power source" of the present invention.

[0024] The harmonic generating load 2 is, for example, a device with an inverter, a device with a diode bridge, or a device with a thyristor, and outputs an AC load current to the power line. The load current includes a harmonic current. A harmonic current is a current that has frequency components that are integer multiples of the fundamental frequency (50 or 60 Hz).

[0025] The load current detection unit 3 includes a current sensor (ACCT in this embodiment) 31 provided on the U-phase power supply line, and a current sensor (ACCT in this embodiment) 32 provided on the W-phase power supply line. The ACCTs 31 and 32 are connected in a V-connection. The load current detection unit 3 detects the load currents flowing through the U-phase, V-phase, and W-phase, and outputs current detection signals Iu, Iv, and Iw (corresponding to the "second signal" of the present invention) related to the load currents.

[0026] The active filter device 100 generates an anti-phase current for suppressing harmonic currents contained in a load current, and outputs the generated anti-phase current to three-phase (U-phase, V-phase, W-phase) power lines. The active filter device 100 includes terminals R, S, T, terminals KR, KS, KT, an inverter unit 110, a capacitor C, a reactor unit L, an inter-phase voltage detection unit 120, a current detection unit 130, a capacitor voltage detection unit 140, and a control unit 150.

[0027] The terminal R is connected to a U-phase power supply line. The terminal S is connected to a V-phase power supply line. The terminal T is connected to a W-phase power supply line. The terminals R, S, and T correspond to the "output terminal" of the present invention.

[0028] The terminal KR is connected to a primary side terminal of ACCT 31. The terminal KS is connected to a connection point between the secondary side terminal of ACCT 31 and the secondary side terminal of ACCT 32. The terminal KT is connected to a primary side terminal of ACCT 32. Current detection signals Iu, Iv, Iw are input to the terminals KR, KS, KT, respectively.

[0029] The inverter unit 110 includes a switching circuit configured with switching elements SW1-SW6, and terminals T1-T5. The terminals T1-T3 correspond to the "AC terminals" of the present invention, and the terminals T4, T5 correspond to the "pair of DC terminals" of the present invention. The switching circuit outputs an opposite-phase current for suppressing (cancelling) harmonic currents from the terminals T1-T3, while outputting a charging current for the capacitor C from the terminals T4, T5.

[0030] The switching elements SW1 to SW6 constitute upper and lower arms of a first leg, a second leg, and a third leg that are connected in parallel between terminals T4 and T5. For example, IGBTs (insulated gate bipolar transistors) can be used as the switching elements SW1 to SW6, and diodes are connected in reverse parallel to the current paths of the IGBTs. The connection point of the switching elements SW1 and SW2 is connected to terminal T1, the connection point of the switching elements SW3 and SW4 is connected to terminal T2, and the connection point of the switching elements SW5 and SW6 is connected to terminal T3.

[0031] The switching circuit of the inverter unit 110 is not limited to the configuration of this embodiment, and the configuration can be changed as appropriate. For example, if opposite-phase currents are output from the terminals T1 to T3, while charging currents for the capacitor C are output from the terminals T4 and T5, the number of switching elements SW1 to SW6 can be increased or decreased.

[0032] The capacitor C is connected between the terminals T4 and T5 of the inverter unit 110. The capacitor C applies a DC voltage between the terminals T4 and T5 of the inverter unit 110, and charges a current according to the clipping amount during clipping processing, which will be described later. The capacitor C may be, for example, at least one electrolytic capacitor.

[0033] The reactor section L includes reactors interposed in three-phase lines connecting the terminals R, S, T with the terminals T1, T2, T3 of the inverter section 110. The reactor section L may further include a noise filter formed of an LC circuit.

[0034] The phase-to-phase voltage detection unit 120 is connected to each of the three-phase lines connecting the terminals R, S, T and the reactor unit L, detects the instantaneous value of at least one inter-phase voltage of each of the three-phase lines, and outputs a voltage detection signal Vac related to the inter-phase voltage.

[0035] The current detection unit 130 includes current sensors (DCCTs in this embodiment) 131 to 133 provided between the reactor unit L and the inverter unit 110. The DCCT 131 detects the peak value (wave height value) of the U-phase opposite-phase current output from the terminal T1 of the inverter unit 110, and outputs a current detection signal Ir related to the U-phase opposite-phase current. The DCCT 132 detects the peak value (wave height value) of the V-phase opposite-phase current output from the terminal T2 of the inverter unit 110, and outputs a current detection signal Is related to the V-phase opposite-phase current. The DCCT 133 detects the peak value (wave height value) of the W-phase opposite-phase current output from the terminal T3 of the inverter unit 110, and outputs a current detection signal It related to the W-phase opposite-phase current. The current detection signals Ir, Is, and It correspond to the "first signal" of the present invention.

[0036] The capacitor voltage detection unit 140 detects the voltage across the terminals of the capacitor C, and outputs a voltage detection signal Vc relating to the voltage across the terminals of the capacitor C.

[0037] The control unit 150 generates a control signal D for turning on / off the switching elements SW1 to SW6 of the inverter unit 110 based on the current detection signals Iu, Iv, Iw, the current detection signals Ir, Is, It, the voltage detection signal Vac, and the voltage detection signal Vc, and controls the inverter unit 110. The control unit 150 is composed of an analog circuit and a digital circuit.

[0038] As shown in FIG. 2, the control unit 150 includes a command value generating unit 151, a gain generating unit 152, a calculation unit 153, a clipping unit 154, and an inverter control unit 155.

[0039] The command value generating unit 151 generates an output command value d0 of a three-phase antiphase current based on the current detection signals Iu, Iv, Iw and the voltage detection signal Vac. Specifically, the command value generating unit 151 extracts a signal corresponding to a harmonic current from the current detection signals Iu, Iv, Iw and the voltage detection signal Vac, and generates an output command value d0 of an antiphase current that is in antiphase with respect to the harmonic current. Note that the command value generating unit 151 may perform known processing to generate the output command value d0, and can appropriately acquire signals required for processing (for example, the current detection signals Ir, Is, It and / or the voltage detection signal Vc) in addition to the current detection signals Iu, Iv, Iw and the voltage detection signal Vac.

[0040] The gain generating unit 152 generates a gain G of the output command value d0 based on the current detection signals Ir, Is, and It. In this embodiment, in order to simplify the control, the gain G is common to the three phases. Although details will be described later, the gain generating unit 152 decreases or increases the gain value of the gain G based on the current detection signals Ir, Is, and It.

[0041] The calculation unit 153 multiplies each of the three-phase output command values ​​d0 by a gain G to generate a three-phase first command signal d1 (=d0×G).

[0042] The clip unit 154 performs clipping processing on the three-phase first command signal d1. In the clip unit 154, an upper limit signal value and a lower limit signal value of the first command signal d1 are set in advance. In this embodiment, the upper limit signal value and the lower limit signal value are set in advance so that the signal value of the first command signal d1 is limited to the upper limit signal value and the lower limit signal value when the peak value of the harmonic current reaches a rated current value set in advance according to the specifications of the inverter unit 110.

[0043] When the first command signal d1 as shown in Fig. 3(A) is input, the clip unit 154 generates a second command signal d2 as shown in Fig. 3(B) in which the signal value of the first command signal d1 is set to the upper limit signal value (I1) when the signal value of the first command signal d1 exceeds the upper limit signal value (I1), and the signal value of the first command signal d1 is set to the lower limit signal value (-I1) when the signal value of the first command signal d1 falls below the lower limit signal value (-I1). When the first command signal d1 falls between the upper limit signal value (I1) and the lower limit signal value (-I1), the clip unit 154 does not perform clipping and outputs the second command signal d2 having a waveform identical to that of the first command signal d1.

[0044] The inverter control unit 155 generates a control signal D for controlling the inverter unit 110 based on the three-phase second command signal d2, the current detection signals Ir, Is, It, and the voltage detection signal Vc. The control signal D is, for example, a PWM control signal for controlling the on / off of the switching elements SW1 to SW6.

[0045] Here, when the clipping unit 154 is not performing clipping processing, almost no current flows from the inverter unit 110 to the capacitor C. Therefore, the voltage between the terminals of the capacitor C is approximately a constant value (600 [V] in this embodiment).

[0046] On the other hand, when the clipping unit 154 is performing clipping, a charging current according to the clipping amount (excess amount between the upper limit signal value and the lower limit signal value) caused by the clipping flows to the capacitor C. If the clipping amount is large, the charging current becomes large, and if the clipping amount is small, the charging current becomes small. The voltage between the terminals of the capacitor C rises according to the clipping amount. When the voltage between the terminals of the capacitor C reaches a preset overvoltage detection line (800 [V] in this embodiment), the inverter control unit 155 stops the on / off control of the switching elements SW1 to SW6 (protection stop).

[0047] In this embodiment, in order to prevent a protection stop from occurring during clip processing, the gain generating unit 152 repeatedly executes the processes shown in the control flow diagrams of FIGS. 4 and 5 at a predetermined control period (a control period on the order of μs in this embodiment).

[0048] The processing performed by the gain generating unit 152 includes a start determination processing (S1 to S3), a gain value reduction processing (S4, S5), a lower limit determination processing (S6, S7), a gain value fixation processing (S8 to S11), a gain value recovery processing (S12 to S14), and an end determination processing (S15, S16).

[0049] The gain generating unit 152, which has started the "start determination process", determines whether the signal values ​​of the current detection signals Ir, Is, and It exceed a predetermined first set value, thereby determining whether the peak value of the three-phase anti-phase current exceeds a preset first threshold value (S1). In this embodiment, the first threshold value is set to the rated current value of the inverter unit 110. Therefore, the first set value is set so that the signal values ​​of the current detection signals Ir, Is, and It reach the first set value when the peak value of the anti-phase current reaches the rated current value.

[0050] If the peak value of the antiphase current of at least one phase exceeds the first threshold value (Yes in S1), the gain generating unit 152 sets the flag to 1 and sets the variable C1 to X1 (where X1 is an integer greater than 0) (S2).

[0051] The flag is a variable used to determine whether or not to execute the “gain value reduction process”, and is set to “1” or “0” within the gain generation unit 152 .

[0052] The variable C1 is an off-delay variable related to the "gain value reduction process", and is set in the gain generation unit 152. In this embodiment, the variable C1 is set to X1 so that it takes 20 [ms] (corresponding to an example of the "processing duration" of the present invention) for the variable C1 to change from X1 to 0. That is, in this embodiment, the gain value is reduced by at least 20 [ms] due to the "gain value reduction process". Note that the value of X1 can be changed as appropriate; increasing X1 lengthens the time during which the gain value is reduced, and decreasing X1 shortens the time during which the gain value is reduced.

[0053] When the gain generating unit 152 executes the process of step S2, or when the peak values ​​of the three-phase antiphase currents are equal to or less than the first threshold value (No in S1), it determines whether or not the flag is set to 1 (S3). When the flag is not set to 1 (set to 0) (No in S3), the gain generating unit 152 repeats the processes from step S1 onward according to a predetermined control period. On the other hand, when the flag is set to 1 (Yes in S3), the gain generating unit 152 proceeds to the process of step S4 and starts the "gain value reduction process."

[0054] In step S4, the gain generating unit 152 determines whether the variable C1 is greater than 0, that is, whether 20 [ms] have not elapsed since the variable C1 was set to X1 in step S2 (S4). If the variable C1 is greater than 0 (Yes in S4), that is, if 20 [ms] have not elapsed since the variable C1 was set to X1, the gain generating unit 152 proceeds to the process of step S5.

[0055] In step S5, the gain generating unit 152 reduces the gain value of the gain G and decreases the variable C1 (S5). In this embodiment, the gain generating unit 152 reduces the gain value by 1 and decreases the variable C1 by 1, but at least one of them may be reduced (decreased) by 2 or more.

[0056] In this embodiment, even if the peak values ​​of the three-phase antiphase currents are equal to or lower than the first threshold value (No in S1), if the variable C1 is greater than 0 (Yes in S4), the gain generating unit 152 reduces the gain value (S5). After executing the process of step S5, the gain generating unit 152 proceeds to the process of step S6 and starts the "lower limit determination process".

[0057] In step S6, the gain generating unit 152 determines whether the gain value is less than a preset lower limit (S6). In this embodiment, the lower limit is set to a value that is 20% of the gain value (fixed value) when clipping is not performed, but the lower limit can be changed as appropriate as long as it is smaller than the gain value when clipping is not performed.

[0058] If the gain value is less than the lower limit (Yes in S6), the gain generating unit 152 sets the gain value to the lower limit (S7). If the gain generating unit 152 has executed the process of step S7 or if the gain value is equal to or greater than the lower limit (No in S6), the gain generating unit 152 repeats the processes of step S1 and thereafter according to a predetermined control period.

[0059] In the determination process of step S4, if the variable C1 is equal to or less than 0 (No in S4), the gain generating unit 152 transitions from "A" in FIG. 4 to the process of step S8 in FIG. 5 and starts "gain value fixing process".

[0060] In step S8, the gain generating unit 152 increases the variable C2 (S8). In this embodiment, the variable C2 is increased by 1, but may be increased by 2 or more. The variable C2 is a variable for counting the fixed time of the gain value, and is set in the gain generating unit 152. In this embodiment, the gain value is fixed until the variable C2 becomes from 0 to X2 (where X2 is an integer greater than 0). In addition, in this embodiment, the value of X2 is set so that it takes 10 [s] (corresponding to an example of the "gain value fixed time" of the present invention) for the variable C2 to increase from 0 to X2. Therefore, the gain value is fixed for at least 10 [s]. The value of X2 can be changed as appropriate, and increasing X2 lengthens the gain value fixed time, and decreasing X2 shortens the gain value fixed time.

[0061] After executing the process of step S8, the gain generating unit 152 determines whether the signal values ​​of the current detection signals Ir, Is, and It exceed a predetermined second set value, thereby determining whether the peak value of the anti-phase current exceeds a preset second threshold value (S9). In this embodiment, the second threshold value is set to a value 0.8 times the rated current value of the inverter unit 110. Therefore, the second set value is set so that the signal values ​​of the current detection signals Ir, Is, and It reach the second set value when the peak value of the anti-phase current reaches the rated current value × 0.8. Note that the second threshold value can be changed as appropriate as long as it is a value smaller than the first threshold value.

[0062] If the peak value of the antiphase current of at least one phase exceeds the second threshold value (Yes in S9), the gain generating unit 152 sets the variable C2 to 0 (S10). This resets the count of 10 [s]. If the gain generating unit 152 has executed the process of step S10 or if the peak values ​​of the antiphase currents of the three phases are equal to or less than the second threshold value (No in S9), the gain generating unit 152 proceeds to the process of step S11.

[0063] In step S11, the gain generating unit 152 determines whether the variable C2 is greater than X2, that is, whether 10 seconds have elapsed (S11). If the variable C2 is greater than X2 (Yes in S11), the gain generating unit 152 proceeds to the process of step S12 and starts the "gain value recovery process."

[0064] In step S12, the gain generating unit 152 increases the variable C3 (S12). In this embodiment, the variable C3 is increased by 1, but may be increased by 2 or more. The variable C3 is a variable for the increasing speed of the gain value, and is set in the gain generating unit 152. When the variable C3 exceeds X3 (where X3 is an integer greater than 0), the gain generating unit 152 increases the gain value. In this embodiment, the value of X3 is set so that the amount of change in the gain value during the gain value recovery process is smaller than the amount of change in the gain value during the gain value reduction process.

[0065] After executing the process of step S12, the gain generating unit 152 judges whether the variable C3 is greater than X3 (S13). If the variable C3 is greater than X3 (Yes in S13), the gain generating unit 152 increases the gain value of the gain G and sets the variable C3 to 0 (S14). In this embodiment, the gain value is increased by 1, but it may be increased by 2 or more. When the gain generating unit 152 executes the process of step S14, if the variable C3 is equal to or less than X3 (No in S13) or if the variable C2 is equal to or less than X2 (No in S11), the gain generating unit 152 proceeds to the process of step S15 and starts the "end judgment process".

[0066] In step S15, the gain generating unit 152 determines whether the gain value is the first gain value (S15). The first gain value is the gain value before the "gain value reduction process" is executed, that is, the gain value when the clip process is not executed. In this embodiment, the first gain value is a fixed value, but the first gain value may be increased or decreased according to the peak value of the antiphase current.

[0067] If the gain value has increased (recovered) to the first gain value (Yes in S15), the gain generating unit 152 sets the flag to 0 and also sets the variable C2 to 0 (S16). If the gain generating unit 152 has executed the process of step S16 or if the gain value has not increased (recovered) to the first gain value (No in S15), the process proceeds from "B" in Fig. 5 to "B" in Fig. 4, and the processes from step S1 onwards are repeated according to a predetermined control period.

[0068] Next, the operation of the active filter device 100 will be described with reference to Fig. 6. In Fig. 6, (A) indicates the operating state, (B) indicates the gain G, (C) indicates the second command signal d2, and (D) indicates the voltage between the terminals of the capacitor C.

[0069] There are two operating states: a steady load state and an overload state. The steady load state is a state in which the peak value of the harmonic current is equal to or less than the rated current value of the inverter unit 110. On the other hand, the overload state is a state in which the peak value of the harmonic current exceeds the rated current value of the inverter unit 110.

[0070] In the period before time t1, the operating state is a steady load state. The gain G is set to the first gain value. The second command signal d2 is generated based on the first command signal d1 without clipping. The terminal voltage of the capacitor C is constant at about 600 [V].

[0071] At time t1, when the operating state changes from a steady load state to an overload state, the peak value of the harmonic current calculated by the command value generating unit 151 exceeds the rated current value of the inverter unit 110. Therefore, the clipping unit 154 performs clipping processing on the three-phase first command signal d1 input via the calculation unit 153, and outputs the second command signal d2 after clipping processing. The inverter control unit 155 generates a PWM signal based on the second command signal d2 and the like, and turns on and off the switching elements SW1 to SW6 of the inverter unit 110. As a result, a charging current according to the clipping amount by the clipping processing starts to flow from the inverter unit 110 to the capacitor C, and the terminal-to-terminal voltage of the capacitor C starts to rise.

[0072] At time t2, the gain generating unit 152 starts a gain value reduction process to reduce the gain value. Note that the reason why there is a time difference between the start of the clipping process (time t1) and the start of the gain value reduction process (time t2) is that the clipping process is performed based on the current detection signals Iu, Iv, and Iw, whereas the gain value reduction process is performed based on the current detection signals Ir, Is, and It, which are feedback signals.

[0073] In the period from time t2 to t3, the gain generating unit 152 reduces the gain value. In response to the reduction in the gain value, the clipping amount (the amount by which the first command signal d1 exceeds the upper limit signal value and the lower limit signal value) during clipping processing also decreases. As a result, the charging current flowing from the inverter unit 110 to the capacitor C also decreases, and the rise in the terminal voltage of the capacitor C becomes gradual. Note that the clipping unit 154 stops clipping processing at time ta before time t3.

[0074] During the period from time t3 to time t4, the gain generating unit 152 fixes the gain value to the lower limit. In the example of Fig. 6, in a state in which the gain value is fixed to the lower limit, the clipping unit 154 outputs the second command signal d2 without performing clipping. That is, the clipping amount during clipping is approximately 0. Therefore, the voltage between the terminals of the capacitor C gradually decreases.

[0075] At time t4, when the operating state changes from an overload state to a steady load state, the clipping unit 154 outputs the second command signal d2 without performing clipping processing. Meanwhile, the gain generating unit 152 fixes the gain value for 10 [s] (until the variable C2 becomes larger than X2) after the peak value of the three-phase antiphase current becomes equal to or smaller than the rated current value.

[0076] At time t5, 10 [s] after time t4, the gain generating unit 152 starts the "gain value recovery process." This causes the gain value to increase toward the first gain value. After time t3, the voltage across the terminals of the capacitor C returns to the original voltage (600 [V]) over a period of several minutes.

[0077] In the active filter device 100 according to this embodiment, the gain generating unit 152 starts a gain value reduction process during clipping, and reduces the gain value of the gain G over time by the gain value reduction process, thereby reducing the clipping amount (excess amount of the upper limit signal value and the lower limit signal value) of the clipping process for the first command signal d1 obtained by multiplying the output command value d0 by the gain G. As a result, an excessive voltage rise of the capacitor C can be suppressed, and it is possible to prevent the voltage between the terminals of the capacitor C from reaching the overvoltage detection line (800 [V] in this embodiment).

[0078] Although the embodiment of the active filter device according to the present invention has been described above, the present invention is not limited to the above embodiment.

[0079] For example, a control unit of the present invention is a control unit that controls an inverter unit based on a first signal and a second signal related to an AC current flowing through a power supply line, and the control unit includes a command value generation unit that generates an output command value for an anti-phase current based on the second signal, a gain generation unit that generates a gain for the output command value based on the first signal, a calculation unit that generates a first command signal by multiplying the output command value by the gain, a clip unit that performs clipping processing on the first command signal to generate a second command signal, and an inverter control unit that generates a control signal for controlling the inverter unit based on the second command signal, and the clip unit performs clipping processing such that the signal value of the second command signal is an upper limit signal value when the signal value of the first command signal exceeds a predetermined upper limit signal value, and the signal value of the second command signal is a lower limit signal value when the signal value of the first command signal is less than a predetermined lower limit signal value, and the gain generation unit starts a gain value reduction process during the clipping process, and reduces the gain value of the gain over time by the gain value reduction process.

[0080] In the clip unit 154 of the above embodiment, the upper limit signal value and the lower limit signal value are set in advance so that the signal value of the first command signal d1 is limited to the upper limit signal value and the lower limit signal value when the peak value of the harmonic current reaches the rated current value of the inverter unit 110. However, the upper limit signal value and the lower limit signal value may be set so that the signal value of the first command signal d1 is limited to the upper limit signal value and the lower limit signal value when the peak value of the harmonic current reaches a value that exceeds the rated current value of the inverter unit 110 (for example, the rated current value × 1.2).

[0081] In addition, in the above embodiment, the first threshold for starting the gain value reduction process is set to the rated current value of the inverter unit 110, but it may also be set to a value exceeding the rated current value (for example, the rated current value x 1.1).

[0082] As described above, the first threshold, the upper limit signal value, and the lower limit signal value can be set appropriately, but it is preferable to perform the gain value reduction process after the clipping process, as shown in FIG. [Explanation of symbols]

[0083] 100 Active filter device 110 Inverter section 120 Phase-to-phase voltage detection unit 130 Current detection section 140 Capacitor voltage detection section 150 Control section 151 Command value generator 152 Gain Generation Section 153 Arithmetic section 154 Clip part 155 Inverter control unit

Claims

1. an output terminal connected to a power supply line through which a load current output from the harmonic generating load flows, the output terminal being connected to a three-phase AC power supply and a harmonic generating load; an inverter unit having a pair of DC terminals and an AC terminal connected to the output terminal, the inverter unit outputting an anti-phase current from the AC terminals for suppressing a harmonic current contained in the load current; A capacitor connected between the pair of DC terminals; a current detection unit that detects the anti-phase current and outputs a first signal related to the anti-phase current; a control unit that controls the inverter unit based on the first signal and a second signal related to the load current; An active filter device comprising: The control unit is a command value generating unit that generates an output command value of the antiphase current based on the second signal; a gain generating unit that generates a gain for the output command value based on the first signal; a calculation unit that generates a first command signal by multiplying the output command value by the gain; a clipping unit that performs clipping processing on the first command signal to generate a second command signal; an inverter control unit that generates a control signal for controlling the inverter unit based on the second command signal, The clip portion is a clipping process for setting the signal value of the second command signal to the upper limit signal value when the signal value of the first command signal exceeds a predetermined upper limit signal value, and for setting the signal value of the second command signal to the lower limit signal value when the signal value of the first command signal is less than a predetermined lower limit signal value, The gain generating unit is A gain value reduction process is started during the clip process, and the gain value of the gain is reduced over time by the gain value reduction process.

1. An active filter device comprising:

2. The gain generating unit is A peak value of the antiphase current is compared with a first threshold value that is set in advance, and when the peak value exceeds the first threshold value, the gain value reduction process is performed; Even if the peak value becomes equal to or less than the first threshold value as a result of the gain value reduction process, if a predetermined processing duration has not elapsed since the peak value became equal to or less than the first threshold value, the gain value reduction process is continued.

2. The active filter device according to claim 1 .

3. The gain generating unit is The gain value reduced by the gain value reduction process is compared with a preset lower limit value, and if the gain value is less than the lower limit value, a lower limit determination process is performed to fix the gain value to the lower limit value.

2. The active filter device according to claim 1 .

4. The gain generating unit is After the clipping process is completed, a preset gain value fixing time is counted, and a gain value fixing process is performed to fix the gain value to a fixed value during the count.

2. The active filter device according to claim 1 .

5. The gain generating unit is If the peak value of the antiphase current exceeds a second threshold value set in advance during the counting, the count number of the gain value fixed time is reset, and the gain value fixed time is counted again.

5. The active filter device according to claim 4.

6. The gain generating unit is execute a gain value recovery process for increasing the gain value reduced by the gain value reduction process over time; The amount of change in the gain value during the gain value recovery process is made smaller than the amount of change in the gain value during the gain value reduction process.

2. The active filter device according to claim 1 .

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