Processing circuit, circuit information, and method for repeating operation

Abstract

To provide a processing circuit that enables a repeated calculation using a logic circuit and holding of the results of the calculation.SOLUTION: A processing circuit 11 includes a control circuit 13 configured to receive at least one operation instruction signal SCNT and a base clock Clock, and to generate a write enable signal WE and a read enable signal RE in response to the base clock Clock and the operation instruction signal SCNT, a memory 15 capable of operating in synchronization with a multiplied clock Clk which is a multiplied base clock Clock, and an arithmetic circuit 17 configured to perform an operation on read data DRT received from the memory 15 using a dedicated hardware logic circuit to generate write data, and the memory 15 is configured to read a memory area 25 identified by an address and including at least one memory element in response to the read enable signal RE, and to write write data DWT to the memory area 25 in response to the write enable signal WE.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a processing circuit, circuit information, and a method for repeating an operation. [Background technology]

[0002] Patent Document 1 discloses a counter that allows count data to be restored when it is lost due to a writing error in the counter provided in a non-volatile memory. Patent Document 1 also relates to control using a counter control program. The counter control program operates to select one of a plurality of counters in turn in response to an update request by increment, and update the count data. The count value is divided and held by the plurality of counters. The count data of the plurality of counters is added up, and this sum is output as the count value. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 2603005 Summary of the Invention [Problem to be solved by the invention]

[0004] A counter circuit uses sequential circuits such as registers or flip-flops (hereinafter referred to as "registers") as circuits for holding count values. The number of registers used increases according to the number of counters and the number of counts of the counters.

[0005] Such an increase in the number of counters causes various undesirable problems, such as the following: For example, if a counter circuit is constructed using a standard logic integrated circuit (hereinafter referred to as "IC"), the number of IC components increases. The increase in the number of components results in an increase in the mounting area.

[0006] In addition, for example, if a counter circuit is configured using a field programmable gate array (FPGA), a large-scale FPGA that can be configured will require many registers. Using a large-scale FPGA will result in increased costs. If a counter circuit needs to be added later in the design, and the additional circuit cannot be accommodated within the remaining capacity of the FPGA, the design will have to be redesigned using an even larger FPGA.

[0007] What is desired is to configure a counter circuit without using registers. A counter circuit includes registers whose number of stages corresponds to the number of counts, and updates the serially connected registers using a clock. However, the operation of a counter circuit is reduced to holding the number of counts and updating the number of counts by an operation such as adding a predetermined number to the held value or subtracting a predetermined number from the held value. In accordance with this, the function of a counter circuit is to repeatedly perform logical operations using a logic circuit and hold the results of the operations.

[0008] An object of the present invention is to provide a processing circuit that enables repeated calculations using logic circuits and holding of the results of the calculations, circuit information for configuring the processing circuit, and a method for repeating the calculations. [Means for solving the problem]

[0009] A processing circuit according to a first aspect of the present invention comprises a control circuit configured to receive at least one operation instruction signal and a base clock, and to generate a write enable signal and a read enable signal in response to the base clock and the operation instruction signal; a memory capable of operating in synchronization with a multiplied clock that is a multiplication of the base clock; and an arithmetic circuit configured to perform an operation on read data received from the memory using a dedicated hardware logic circuit to generate write data, wherein the memory is configured to read a first memory area identified by an address and including at least one memory element in response to the read enable signal, and to write the write data to the first memory area in response to the write enable signal.

[0010] Circuit information according to a second aspect of the present invention is circuit information describing a configuration of a circuit, written in a hardware description language, that causes the circuit to function as a processing circuit, the processing circuit comprising: a control circuit configured to receive at least one operation instruction signal and a base clock, and generate a write enable signal and a read enable signal within one period of the base clock in response to the base clock and the operation instruction signal; a memory operable in synchronization with a multiplied clock that is a multiplication of the base clock; and an arithmetic circuit configured to perform an operation on read data received from the memory using a dedicated hardware logic circuit to generate write data, the memory being configured to read a first memory area identified by an address and including at least one memory element in response to the read enable signal, and to write the write data to the first memory area in response to the write enable signal.

[0011] A method for repeating an operation using a processing circuit including a dedicated hardware logic circuit according to a third aspect of the present invention, comprising: generating a read enable signal within one period of a base clock in response to an operation instruction signal and a base clock; in a memory operable in synchronization with a multiplied clock obtained by multiplying the base clock, during a period of the read enable signal, reading a memory area specified by the operation instruction signal; performing an operation on the read data from the memory using the logic circuit to generate write data; generating a write enable signal within one period of the base clock in response to the operation instruction signal and the base clock; writing the write data to the memory area during a period of the write enable signal; and repeating the reading, operation, and writing at least once, wherein performing the operation to generate write data and writing the write data to the memory area are performed during a period after the read data is determined and until the write enable signal ends. Effect of the Invention

[0012] According to the above aspects, it is possible to provide a processing circuit that enables repeated calculations using logic circuits and holding of the calculation results, circuit information for configuring the processing circuit, and a method for repeating the calculations. [Brief description of the drawings]

[0013] [Figure 1] FIG. 1 is a diagram illustrating a processing circuit according to the present embodiment. [Diagram 2] FIG. 2 is a diagram showing the truth values ​​of the operation of the control circuit according to the present embodiment. [Diagram 3] FIG. 3 is a diagram illustrating the operation of the processing circuit shown in FIG. [Figure 4] FIG. 4 is a timing chart showing the operation of the memory according to the present embodiment. [Diagram 5] FIG. 5 is a timing diagram illustrating the operation of the counter circuit of the exemplary processing circuit. [Figure 6] FIG. 6 is a diagram showing the operation of the address selection circuit of the control circuit according to the present embodiment. [Figure 7] FIG. 7 is a diagram showing the operation of the multiplexing circuit of the control circuit according to the present embodiment. [Figure 8] FIG. 8 is a diagram illustrating an operation of the processing circuit shown in FIG. 1 using a plurality of operation instruction signals and a read signal. [Figure 9] FIG. 9 is a timing diagram illustrating the operation of the counter circuit of the exemplary processing circuit. [Figure 10] FIG. 10 is a diagram showing hardware resources for creating circuit information for a processing circuit according to the present embodiment. [Figure 11] FIG. 11 is a flow chart showing a method for updating values ​​by repeating the same calculation according to the present embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description, the same parts are designated by the same reference numerals and duplicated description will be omitted.

[0015] Fig. 1 is a diagram illustrating a processing circuit according to an embodiment of the present invention, and Fig. 2 is a diagram illustrating an operation of the processing circuit illustrated in Fig. 1.

[0016] The processing circuit 11 includes a control circuit 13 , a memory 15 , and an arithmetic circuit 17 .

[0017] The control circuit 13 is configured to receive a basic clock Clock and at least one operation instruction signal SCNT, and to generate a write enable signal WE and a read enable signal RE in response to the basic clock Clock and the operation instruction signal SCNT. The control circuit 13 can also provide an address signal Address to an address input ADR of the memory 15.

[0018] The memory 15 may include a storage area designated by an address value. The memory 15 may operate in synchronization with a multiplied clock Clk obtained by multiplying a basic clock Clock. The multiplied clock Clk is generated from the basic clock Clock by a multiplier circuit 21, which may include, for example, a phase lock loop (PLL). The exemplary multiplier circuit 21 may generate a clock that is doubled. The basic clock Clock may be supplied from a clock generator circuit 23, which may include an oscillator circuit, a divider circuit, or another multiplier circuit.

[0019] The memory 15 is configured to read a first storage area 25 identified by an address and including at least one storage element in response to a read enable signal RE, and to write write data DWT to the first storage area 25 in response to a write enable signal WE.

[0020] The memory 15 may include various types of storage circuits that can operate (specifically, can be rewritten and read) in synchronization with the multiplied clock Clk received at the clock input CLKIN, and may include, for example, a random access memory (hereinafter, referred to as "RAM"). The memory 15 may include volatile and nonvolatile storage elements, as well as a combination of volatile and nonvolatile storage elements. The RAM of the memory 15 may include, for example, a single-port RAM cell.

[0021] The arithmetic circuit 17 is configured to generate the write data DWT by performing an operation on the read data DRT received from the memory 15. The arithmetic circuit 17 can be configured to generate the operation result within a period of a half cycle of the basic clock Clock.

[0022] The arithmetic operations can be performed, for example, using dedicated hardware logic circuits. The arithmetic circuit 17 can include, for example, an adder circuit for performing addition, a subtractor circuit for performing subtraction, an exclusive-or circuit for performing exclusive-or, and a combination of two or more of these. The dedicated hardware of the arithmetic circuit 17 can be configured to perform the arithmetic operations without the intervention of microcode.

[0023] According to this processing circuit 11, the memory 15 reads the first storage area 25 specified by the address to provide read data DRT. The read data DRT is processed by the arithmetic circuit 17, which generates write data DWT. The write data DWT is written to the first storage area 25 specified by the address.

[0024] The processing circuit 11 may further include an output circuit 27 connected to the output DOUT of the memory 15. The output circuit 27 provides a read value from the memory 15, for example, during an active period (for example, an “H” period) of a read enable signal RE.

[0025] The control circuit 13 is configured to receive at least one read signal SRD. The control circuit 13 is configured to generate a read enable signal RE and not generate a write enable signal WE within one period of the basic clock Clock in response to the read signal SRD. The memory 15 reads the storage area of ​​the specified address within the period of the read enable signal RE.

[0026] In the exemplary processing circuit 11, the arithmetic circuit 17 may include at least one arithmetic unit 34. An exemplary operation of the arithmetic circuit 17 may be either an addition count-up operation (e.g., adding 1) or a subtraction count-down operation (e.g., subtracting 1).

[0027] In the exemplary counter circuit, the arithmetic circuit 17 and the calculator 34 may include at least one of a count-up circuit 33 and a count-down circuit 35. The count-up circuit 33 and the count-down circuit 35 may be selected by a selection circuit 36 ​​responsive to a switching signal SSL indicating whether the operation of the arithmetic circuit 17 is a count-up operation or a count-down operation.

[0028] The processing circuit 11 may include an initial value circuit 29 and a selection circuit 31. The initial value circuit 29 may provide an initial value SINT in the calculation of the calculation circuit 17, and may store the initial value SINT or generate it by calculation. The selection circuit 31 may provide either the initial value SINT from the initial value circuit 29 or the calculation result (DWT) from the calculation circuit 17 to the input DIN of the memory 15 in response to a selection signal SSEL.

[0029] FIG. 2 is a diagram showing the truth value of the operation of the control circuit according to the present embodiment. In FIG. 2, the symbol "dc" indicates "don't care". Referring to FIG. 2, the read enable signal RE and the write enable signal WE can be generated, for example, using the operation instruction signal SCNT and the basic clock Clock. An exemplary read enable signal RE is defined by the active period (e.g., "H" period) of the operation instruction signal SCNT and a half period (e.g., "L" period) of the basic clock Clock, and the active period (e.g., "H" period) of the read signal SRD and a half period (e.g., "L" period) of the basic clock Clock. In addition, an exemplary write enable signal WE is defined by the active period (e.g., "H" period) of the operation instruction signal SCNT and a half period (e.g., "H" period) of the basic clock Clock.

[0030] FIG. 3 is a diagram showing a timing chart of the operation of the memory according to the present embodiment. In FIG. 3, the symbol "dc" indicates "don't care". Referring to FIG. 3, three consecutive write sequences and three consecutive read sequences are shown. The consecutive write sequences can be performed, for example, when initializing the storage area of ​​the memory 15. Also, the consecutive read sequences can be performed, for example, in verifying (checking the storage contents) when initializing the storage area of ​​the memory 15. The control circuit 13 receives one or more addresses to be initialized, for example, in response to an initialization address signal ADINT. The control circuit 13 generates the address to be initialized and a write enable signal WE in response to the initialization address signal ADINT. The control circuit 13 can generate a read enable signal RE in addition to the write enable signal WE. The address to be initialized, the write enable signal WE, and the read enable signal RE are provided to the memory 15. The write and read operations to the memory 15 can include consecutive write and subsequent read operations, as well as alternating write and read operations. The control circuit 13 may include one or more address buffers that store the addresses to be initialized.

[0031] In an exemplary write sequence, addresses "0x01", "0x02" and "0x03" are input in sequence to the memory 15. A write operation is performed in synchronization with the input of the addresses to the memory 15, and write data "1", "2" and "3" are provided in sequence to the input DIN. At each address, the stored data in the memory area is determined at the transition edge (e.g., falling edge) of the write enable signal WE.

[0032] In an exemplary read sequence, addresses "0x01", "0x02" and "0x03" are input in sequence to the memory 15. A read operation is performed in synchronization with the input of the addresses to the memory 15, and read data "1", "2" and "3" are provided in sequence to the output DOUT. For each address, the read data is determined at the transition edge (e.g., falling edge) of the read enable signal RE.

[0033] 4 is a timing diagram showing an exemplary operation of the processing circuit according to the present embodiment. In the exemplary processing circuit 11, the signal to the address input of the memory 15 is, for example, "0x0001". This address stores "X1" as an initial value.

[0034] The operation instruction signal SCNT has four active periods (TAC1, TAC2, TAC3, TAC4). In each active period (TAC1 to TAC4), the control circuit 13 provides the memory 15 with a read enable signal RE and a write enable signal WE following the read enable signal RE.

[0035] In response to a read enable signal RE in the first active period (TAC1), the memory 15 reads the storage area 25 at the time indicated by the arrow RD1 to generate read data DRT at the output DOUT. The first read data DRT is "X1." The arithmetic circuit 17 performs an arithmetic operation on the read data DRT to generate write data DWT (the first write data DWT is "X2"). The write data DWT is provided to an input DIN of the memory 15 and written to the storage area 25 at the time indicated by the arrow WR1 in response to a write enable signal WE in the first active period (TAC1).

[0036] In response to a read enable signal RE in the second active period (TAC2), the memory 15 reads out read data DRT "X2" from the storage area 25 at the time indicated by arrow RD2. The arithmetic circuit 17 performs an arithmetic operation on the read data DRT to generate write data DWT "X3". This write data DWT is provided to an input DIN of the memory 15 and written into the storage area 25 at the time indicated by arrow WR2 in response to a write enable signal WE in the active period (TAC2).

[0037] Furthermore, in response to a read enable signal RE in the third active period (TAC3), the memory 15 reads out read data DRT "X3" from the storage area 25 at the time indicated by arrow RD3. The arithmetic circuit 17 performs an arithmetic operation on the read data DRT to generate write data DWT "X4". This write data DWT is provided to the input DIN of the memory 15 and written to the storage area 25 at the time indicated by arrow WR3 in response to a write enable signal WE in the active period (TAC3).

[0038] Furthermore, in response to a read enable signal RE in the fourth active period (TAC4), the memory 15 reads out read data DRT "X4" from the storage area 25 at the time indicated by arrow RD4. The arithmetic circuit 17 performs an arithmetic operation on the read data DRT to generate write data DWT "X5". This write data DWT is provided to an input DIN of the memory 15 and written into the storage area 25 at the time indicated by arrow WR4 in response to a write enable signal WE in the active period (TAC4).

[0039] After the operation instruction signal SCNT transitions to inactive, the control circuit 13 can receive the read signal SRD. The read signal SRD has a single active period (TAC5). Within this active period (TAC5), the control circuit 13 provides the read enable signal RE to the memory 15 without a subsequent write enable signal WE.

[0040] In response to the read enable signal RE in the active period (TAC5), the memory 15 reads out the read data DRT “X5” from the storage area 25 at the time of arrow RD5. The read data DRT “X5” is provided to the outside of the processing circuit 11 by the output circuit 27.

[0041] On the other hand, the exemplary arithmetic circuit 17 performs an operation on the read data DRT to generate the write data DWT “X6”. However, the control circuit 13 does not generate the write enable signal WE from the read signal SRD, so the operation result is not written to the memory 15.

[0042] 5 is a timing chart showing the operation of the counter circuit included in the exemplary processing circuit 11. The exemplary counter circuit can perform a count-up operation.

[0043] First, the address signal Address specifies the address "0x0001" of the memory 15. When the operation instruction signal SCNT is input to the control circuit 13 in synchronization with a transition edge (e.g., a rising edge) of the reference clock clock, the control circuit 13 generates the first write enable signal WE in a half period (e.g., an "H" period) of the reference clock clock in response to the transition of the operation instruction signal SCNT. The counter circuit writes an initial value (initial value of the counting operation) provided from the initial value circuit 29 via the selection circuit 31 to a storage area (e.g., storage area 25) of the memory 15 when the write enable signal WE is in an active state (e.g., "H") in the active state (e.g., "H") of the write enable signal WE. In this counter circuit, the initial value of the storage area of ​​the memory 15 is determined at the time of the arrow WR0 in FIG. 5. In the exemplary initial value storage, no read operation is performed to confirm the value storage.

[0044] The operation instruction signal SCNT is made active for a period including multiple periods of the reference clock. During this period, the address signal Address is not changed and the address of the memory 15 is fixed. The reference clock is input to the processing circuit 11. The control circuit 13 generates an initial write enable signal WE, followed by a read enable signal RE and a write enable signal WE in turn, in accordance with the reference clock and the operation instruction signal SCNT. This generation is terminated when the operation instruction signal SCNT is made inactive in synchronization with a transition edge (e.g., a falling edge) of the reference clock.

[0045] In an exemplary operation of the counter circuit, after the time of the arrow WR0 in Fig. 5, reading is performed at the read times of the arrows RD1, RD2, RD3, RD4, RD5, RD6, and RD7 in Fig. 5. Writing is performed at the write times of the arrows WR1, WR2, WR3, WR4, WR5, WR6, and WR7 in Fig. 5. These reading and writing are performed alternately. The memory 15 provides read data DRT during reading and receives write data DWT during writing.

[0046] In the exemplary counter circuit, the arithmetic circuit 17 performs an arithmetic process, that is, a count-up operation, on the read data DRT from the memory 15. Through this process, the arithmetic circuit 17 updates the read data DRT to a value that is larger by an increment to generate an arithmetic value. The arithmetic circuit 17 outputs this arithmetic value as the write data DWT. The write data DWT is provided to the input DIN of the memory 15 via the selection circuit 31. The memory 15 stores the write data DWT in a storage area.

[0047] The exemplary counter circuit repeatedly updates the value of the storage area by repeating the calculation. This repetition is a count-up operation. In the above description, the count-up operation is replaced with a count-down operation, and the exemplary counter circuit can perform a repeated count-down operation.

[0048] The control circuit 13 continues to fix the address. After the operation instruction signal SCNT transitions to an inactive state, a read signal SRD exclusive to the operation instruction signal SCNT is provided to the control circuit 13. The control circuit 13 generates a read enable signal RE without generating a write enable signal WE from the active state of the read signal SRD that specifies the same address as the operation instruction signal SCNT. In response to the read enable signal RE, the memory 15 reads the contents of the storage area specified by the address and provides it to the output DOUT. The read data DRT of the output DOUT is provided to the operation circuit 17 and the output circuit 27. In response to the read signal SRD, the output circuit 27 provides a count value. The operation circuit 17 performs an operation on this read data DRT, and the operation result is provided to the input DIN of the memory 15. However, since the write enable signal WE is not generated during the active period of the read signal SRD, the contents of the storage area of ​​the memory 15 are not changed.

[0049] In the exemplary counter circuit, the operation circuit 17 may include a count-up circuit 33 and a count-down circuit 35. The count-up circuit 33 and the count-down circuit 35 may be selected in response to a switching signal SSL indicating whether the operation is a count-up operation or a count-down operation.

[0050] As can be understood from the above description, the operation of the exemplary processing circuit 11 is reduced to the following operations. That is, the memory 15 provides read data DRT from a storage area during an active period of the read enable signal RE, and the read data DRT is subjected to an operation by the arithmetic circuit 17. The read data DRT is updated by this operation. This updated value is provided as write data DWT by the arithmetic circuit 17. The write data DWT is provided to an input DIN of the memory 15 via the selection circuit 31. The memory 15 stores the write data DWT in the storage area during an active period of the write enable signal WE.

[0051] According to this, the calculation of the arithmetic circuit 17 is not limited to a count-up operation and a count-down operation, but is reduced to a repeating operation of a series of processes. The operations are, for example, reading data from a storage element, performing an operation on the read data, and storing the operation result in the previous storage element. Examples of such a repeating series of operations include a cyclic redundancy check (CRC) operation and an operation to process data (e.g., an averaging process) while monitoring received data for a long period of time.

[0052] Next, a processing circuit 11 capable of operating the memory 15 while changing addresses will be described.

[0053] Referring to FIG. 1, the exemplary control circuit 13 may include an address selection circuit 41 that receives an operation instruction signal SCNT and a read signal SRD.

[0054] Fig. 6 is a diagram showing the operation of the address selection circuit of the control circuit according to the present embodiment. Fig. 7 is a diagram showing the operation of the multiplexing circuit of the control circuit according to the present embodiment. Fig. 8 is a timing chart showing the operation of the processing circuit shown in Fig. 1 using a plurality of operation instruction signals and a read signal.

[0055] As shown in FIG. 6, in the exemplary control circuit 13, the first operation instruction signal SCNT1, the second operation instruction signal SCNT2, the third operation instruction signal SCNT3, and the fourth operation instruction signal SCNT4 are input to the address selection circuit 41 as operation instruction signals SCNT. The address selection circuit 41 generates the respective addresses based on the first operation instruction signal SCNT1 to the fourth operation instruction signal SCNT4. In addition, in the exemplary control circuit 13, the first read signal SRD1, the second read signal SRD2, the third read signal SRD3, and the fourth read signal SRD4 are input to the address selection circuit 41 as read signals SRD. The address selection circuit 41 generates the respective addresses based on the first read signal SRD1 to the fourth read signal SRD4. In addition, the first operation instruction signal SCNT1 to the fourth operation instruction signal SCNT4 and the first read signal SRD1 to the fourth read signal SRD4 can be provided to the respective inputs of the address selection circuit 41. In any of these cases, the address selection circuit 41 generates the respective addresses based on the first operation instruction signal SCNT1 to the fourth operation instruction signal SCNT4 and the first read signal SRD1 to the fourth read signal SRD4.

[0056] Referring to FIG. 1, an exemplary address selection circuit 41 may include a first multiplexing circuit 43 and a second multiplexing circuit 45 .

[0057] As shown in FIG. 7, when any one of the first operation instruction signal SCNT1 to the fourth operation instruction signal SCNT4 is in an active state, the first multiplexing circuit 43 generates a multiplexing signal SMUXC indicating that any one of the operation instruction signals is in an active state.

[0058] Furthermore, when any one of the first read signal SRD1 to the fourth read signal SRD4 is in an active state, the second multiplexing circuit 45 generates a multiplexing signal SMUXR indicating that any one of the read signals is in an active state.

[0059] Referring to FIG. 1, the exemplary control circuit 13 may further include a write and read control circuit 47 .

[0060] The write / read control circuit 47 generates a read enable signal RE and a write enable signal WE from the multiplexed signal SMUXC. An exemplary read enable signal RE is defined by an active period (e.g., "H" period) of the first multiplexed signal SMUXC and a half period (e.g., "L" period) of the basic clock Clock, and an active period (e.g., "H" period) of the second multiplexed signal SMUXC and a half period (e.g., "L" period) of the basic clock Clock. An exemplary write enable signal WE is defined by an active period (e.g., "H" period) of the first multiplexed signal SMUXC and a half period (e.g., "H" period) of the basic clock Clock.

[0061] Referring to FIG. 1, the exemplary address selection circuit 41 may further include an address generation circuit 51.

[0062] As can be seen from FIG. 6, the address generation circuit 51 operates as follows. When either the first operation instruction signal SCNT1 or the first read signal SRD1 is in an active state, the address generation circuit 51 generates a first address signal a1. When either the second operation instruction signal SCNT2 or the second read signal SRD2 is in an active state, the address generation circuit 51 generates a second address signal a2. When either the third operation instruction signal SCNT3 or the third read signal SRD3 is in an active state, the address generation circuit 51 generates a third address signal a3. When either the fourth operation instruction signal SCNT4 or the fourth read signal SRD4 is in an active state, the address generation circuit 51 generates a fourth address signal a4.

[0063] The first address signal a1 to the fourth address signal a4 are input to an address input ADR of the memory 15 as an address signal Address.

[0064] The addresses of the memory 15 are specified by address signals Address (a1, a2, a3, and a4). The address signals (a1 to a4) specify, for example, memory areas (MEM1, MEM2, MEM3, and MEM4) as shown in FIG.

[0065] With reference to FIG. 8, the operation of the processing circuit 11 will now be described using a number of addresses in the memory 15.

[0066] A plurality of operation instruction signals SCNT (specifically, a first operation instruction signal SCNT1 to a fourth operation instruction signal SCNT4) are input in sequence to the control circuit 13. In the processing circuit 11, the first operation instruction signal SCNT1 to the fourth operation instruction signal SCNT4 can be mutually exclusive signals, and for example, when the first operation instruction signal SCNT1 is active, the second operation instruction signal SCNT2, the third operation instruction signal SCNT3, and the fourth operation instruction signal SCNT4 are inactive. All of the first operation instruction signal SCNT1 to the fourth operation instruction signal SCNT4 can be inactive. The operation instruction signals having these characteristics are provided to the write / read control circuit 47 and the address generation circuit 51 via the first multiplexing circuit 43.

[0067] Further, a plurality of read signals SRD (specifically, the first read signal SRD1, the second read signal SRD2, the third read signal SRD3, and the fourth read signal SRD4) are input in sequence to the control circuit 13. In the processing circuit 11, the first read signal SRD1 to the fourth read signal SRD4 can be mutually exclusive signals, for example, when the first read signal SRD1 is active, the second read signal SRD2 to the fourth read signal SRD4 are inactive. All of the first read signal SRD1 to the fourth read signal SRD4 can be inactive. The read signal SRD is exclusive with the operation instruction signal SCNT. The read signal having these characteristics is provided to the write / read control circuit 47 and the address generation circuit 51 via the second multiplexing circuit 45.

[0068] 8, the memory 15 reads out the storage area MEM1 specified by the first address signal a1 at the time of arrow RD1 in Fig. 8 in response to the read enable signal RE, and generates read data DRT, specifically "X10." The first address signal a1 is associated with the first operation instruction signal SCNT1.

[0069] Furthermore, the arithmetic circuit 17 may include a computing unit corresponding to the operation instruction signal. Specifically, the arithmetic circuit 17 may include computing units corresponding to the first operation instruction signal SCNT1 to the fourth operation instruction signal SCNT4, respectively. The operation results corresponding to the first operation instruction signal SCNT1 to the fourth operation instruction signal SCNT4 are generated by the operation of the computing unit designated by the first operation instruction signal SCNT1 to the fourth operation instruction signal SCNT4 (or the first address signal a1 to the fourth address signal a4).

[0070] The read data DRT is provided to the arithmetic circuit 17 (or to the corresponding arithmetic unit if the arithmetic circuit 17 includes an arithmetic unit for each arithmetic instruction signal), which generates an arithmetic result, specifically, "X11". This arithmetic result is provided to the input DIN of the memory 15 as write data DWT. During the active period of the first arithmetic instruction signal SCNT1, the control circuit 13 cannot change the value of the address signal Address. In response to the write enable signal WE, the memory 15 writes the write data DWT (specifically, "X11") to the memory area MEM1 at the time of arrow WR1 in FIG. 8.

[0071] As shown in Fig. 8, the address of the memory 15 is updated every time the operation instruction signal is updated. Similarly, in response to a read enable signal RE generated from a new operation instruction signal, the memory 15 reads the memory area MEM2 (and further, MEM3 and MEM4) at the time of the arrow RD2 (and further, RD3 and RD4) in Fig. 8 to generate read data DRT, specifically "X20" (and further, "X30" and "X40"). The memory area MEM2 (and further, MEM3 and MEM4) is identified by a second address signal a2 (and further, a3 and a4) associated with the second operation instruction signal SCNT2 (and further, SCNT3 and SCNT4).

[0072] The read data DRT is provided to the arithmetic circuit 17 (or to the corresponding arithmetic unit when the arithmetic circuit 17 includes an arithmetic unit for each arithmetic instruction signal) to generate an arithmetic result, specifically, "X21" (and further, "X31" and "X41"). This arithmetic result is provided to the input DIN of the memory 15 as the write data DWT. In response to the write enable signal WE, the memory 15 writes the write data DWT, specifically, "X21" (and further, "X31" and "X41") to the memory area MEM2 (and further, MEM3 and MEM4) at the time of the arrow WR2 (and further, WR3 and WR4) in FIG. 8. During the active period of the second arithmetic instruction signal SCNT2 (SCNT3 and SCNT4), the address signal Address of the memory area MEM2 (MEM3 and MEM4) is not changed.

[0073] In addition, the memory 15 reads the first memory area 25 identified by the first address signal a1 associated with the first read signal SRD1 in response to the read enable signal RE at the time of arrow RD5 in Figure 8 to generate read data DRT, specifically "X11".

[0074] The address of the memory 15 is updated every time the read signal is updated. Similarly, in response to a read enable signal RE generated from a new read signal, the memory 15 reads the memory area MEM2 (and MEM3 and MEM4) at the time of the arrow RD6 (and RD7 and RD8) in Fig. 8 to generate read data DRT, specifically "X21" (and "X31" and "X41"). The memory area MEM2 (MEM3 and MEM4) is identified by a second address signal a2 (a3 and a4) associated with the second read signal SRD2 (and SRD3 and SRD4).

[0075] Fig. 9 is a timing chart showing the operation of the exemplary counter circuit of the exemplary processing circuit 11. Referring to Fig. 9, the exemplary counter circuit can perform four counting operations, specifically, count-up operations. As in the timing chart of Fig. 8, the memory 15 accesses each memory area (MEM1 to MEM4) by address signals (a1 to a4).

[0076] In the memory 15, the count initial values ​​of the storage areas designated by the address signals (a1 to a4) can be specified by the initialization already described. In the timing chart of FIG. 9, these initialization operations are not depicted. Specifically, each operation instruction signal (SCNT1 to SCNT4) is input to the control circuit 13 in synchronization with a transition edge (e.g., a rising edge) of the reference clock, and the control circuit 13 generates the first write enable signal WE in a half period (e.g., an "H" period) of the reference clock in response to the first multiplexed signal SMUXC of the first multiplexing circuit 43. The counter circuit writes each initial value (four initial values ​​of the count operation) provided from the initial value circuit 29 via the selection circuit 31 to the storage areas (e.g., four storage areas MEM1 to MEM4) of the memory 15 when the write enable signal WE is in an active state (e.g., "H"). Specifically, the memory 15 is initialized by storing, for example, "X10", "X20", "X30" and "X40" as initial values ​​in four storage areas (MEM1 to MEM4).

[0077] A reference clock is input to the processing circuit 11. Referring to Fig. 9, instead of a single operation instruction signal SCNT being activated over a period including multiple cycles of the reference clock, multiple operation instruction signals (SCNT1 to SCNT4) are activated in sequence over a period including multiple cycles of the reference clock. Addresses of the memory 15 are generated from the operation instruction signals (SCNT1 to SCNT4). Storage areas (MEM1 to MEM4) are accessed according to addresses (a1 to a4) from the operation instruction signals (SCNT1 to SCNT4).

[0078] The control circuit 13 alternately generates a read enable signal RE and a write enable signal WE in response to the reference clock and each operation instruction signal (SCNT1 to SCNT4) after the first write enable signal WE for initialization. The read enable signal RE and the write enable signal WE are generated from a first multiplexed signal SMUXC that multiplexes each operation instruction signal (SCNT1 to SCNT4). Specifically, the read enable signal RE and the write enable signal WE are generated from the active period of the first multiplexed signal SMUXC and the low period and high period of the reference clock, respectively.

[0079] In an exemplary update operation of the counter circuit, reading is performed at the read times of the arrows RD1, RD2, RD3, RD4, RD5, RD6, RD7, and RD8. Writing is performed at the write times of the arrows WR1, WR2, WR3, WR4, WR5, WR6, WR7, and WR8. These reading and writing are performed alternately. After two cycles of reading and writing are completed, the operation instruction signal is updated. In response to this update, the address is updated. Also, in an exemplary current value reading operation of the counter circuit, reading is performed in order at the read times of the arrows RD9, RD10, RD11, and RD12.

[0080] The reads at arrows RD1 and RD2, RD3 and RD4, RD5 and RD6, and RD7 and RD8 are related in terms of the memory areas accessed at arrows WR1 and WR2, WR3 and WR4, WR5 and WR6, and WR7 and WR8, respectively. Memory 15 alternates between read and write operations, except that the memory areas accessed are different. Memory 15 provides read data DRT when reading counter values, and receives write data DWT when writing counter values.

[0081] The exemplary counter circuit reads out read data DRT, for example, "10", from the address signal a1 (and a2 to a4) of the memory 15, and performs an arithmetic process, i.e., a count-up operation, on the read data DRT by the arithmetic circuit 17. Through the arithmetic process, the read data DRT is updated to a value that is incremented larger, for example, "X11". The arithmetic circuit 17 outputs the arithmetic value as the write data DWT. The write data DWT is provided to the input DIN of the memory 15 via the selection circuit 31. The memory 15 stores the write data DWT in the memory area MEM1 (and MEM2 to MEM4) specified by the address signal a1 (and a2 to a4) of the memory 15. The memory area MEM1 of the address signal a1 is updated by a two-cycle count-up operation and stores "X12".

[0082] The exemplary counter circuit repeatedly updates the values ​​of multiple storage areas by repeating calculations. These repetitions are count-up operations. Furthermore, the storage areas MEM2, MEM3, and MEM4 specified by the address signals a2, a3, and a4 of the memory 15 store "X20," "X30," and "X40," respectively, upon initialization. When a two-cycle count-up operation is applied to the storage areas MEM2 to MEM4, the storage areas MEM2 to MEM4 store "X22," "X32," and "X42," respectively.

[0083] In the above description, the count-up operation is replaced with a count-down operation, and the exemplary counter circuit is capable of performing a count-down operation.

[0084] After all of the operation instruction signals (SCNT1 to SCNT4) become inactive, the read signals (SRD1 to SRD4) are provided to the control circuit 13, which generates the read enable signal RE from the read signals (SRD1 to SRD4). As already explained, the memory areas (MEM1 to MEM4) to be accessed are identified by the read signals (SRD1 to SRD4), respectively. In an exemplary operation of the counter circuit, the count value is read at the times indicated by the arrows RD9, RD10, RD11, and RD12, but the count value is not updated.

[0085] In response to the read enable signal RE, the memory 15 reads out the count value of the storage area specified by the address and provides read data DRT to the output DOUT. The read data DRT is provided to the arithmetic circuit 17 and the output circuit 27. In response to the read signal SRD, the output circuit 27 provides the current count value. The arithmetic circuit 17 performs an operation on this read data DRT and provides it to the input DIN of the memory 15. However, since the write enable signal WE is not generated during the active period of the read signals (SRD1 to SRD4), the contents of the storage areas of the memory 15 are not changed.

[0086] The switching signal SSL of the operation of the arithmetic circuit 17 can be associated with the operation instruction signals (SCNT1 to SCNT4). Thus, the operation of the arithmetic circuit 17 can differ according to the operation instruction signals (SCNT1 to SCNT4). Specifically, the exemplary arithmetic circuit 17 can include an arithmetic unit corresponding to each of the operation instruction signals (SCNT1 to SCNT4). The arithmetic circuit 17 can receive the operation instruction signals (SCNT1 to SCNT4) and select an arithmetic unit accordingly. For example, a count-up operation and a count-down operation can be specified by the operation instruction signals, respectively.

[0087] 1, such as the control circuit 13, the memory 15, the arithmetic circuit 17, the output circuit 27, and the selection circuit 31, can be implemented, for example, in an FPGA. Alternatively, the circuits shown in FIG. 1, such as the control circuit 13, the memory 15, the arithmetic circuit 17, the output circuit 27, and the selection circuit 31, can be implemented, for example, by a standard logic integrated circuit (IC).

[0088] FIG. 10 is a block diagram illustrating exemplary hardware resources for creating circuit information for a processing circuit according to the present embodiment.

[0089] Hardware resources are used to create circuit information, modify circuit information, and write circuit information to the reconfigurable semiconductor device. Exemplary hardware resources may include a computer 20. Exemplary computer 20 may include a central processing unit (CPU) 141, a memory 142, an input / output port 143, and a network port 144, and may include an input device 145 and a display 146, if necessary. The memory 142 is communicatively coupled to the central processing unit 141. The input / output port 143 is communicatively coupled to the central processing unit 141, and receives data from an external sensor and transmits the received data. The network port 144 is communicatively coupled to the central processing unit 141 and is connected to an (external) network. The input device 145 is communicatively coupled to the central processing unit 141. The display 146 is communicatively coupled to the central processing unit 141 and the memory 142. Circuit information is stored in the memory 142 or provided from a network via the network port 144. The central processing unit 141 , memory 142 , input / output port 143 , network port 144 , input device 145 and display 146 are connected via a system bus 147 .

[0090] The circuit information according to the present embodiment represents the configuration of a circuit described in a hardware description language such as Verilog or VHDL, and includes configuration information for making the circuit function as a processing circuit. The circuit information is written into a reconfigurable semiconductor device, for example, to prepare the reconfigurable semiconductor device.

[0091] The exemplary circuit information 140 is configured to cause the circuit to function as a processing circuit and may include at least one of the following circuit information components: A component of the control circuit 13 configured to receive at least one operation instruction signal SCNT and a base clock Clock, and to generate a write enable signal WE and a read enable signal RE in response to the base clock Clock and the operation instruction signal SCNT; A component of the memory 15 operable in synchronization with a multiplied clock Clk obtained by multiplying the base clock Clock; A component of the arithmetic circuit 17 configured to perform an operation on read data DRT received from the memory 15 using a dedicated hardware logic circuit to generate write data; and The memory 15 is configured to read a memory area 25 identified by an address and including at least one memory element in response to a read enable signal RE, and to write write data DWT to the first memory area 25 in response to a write enable signal WE.

[0092] The circuit information 140 can be written into the reconfigurable semiconductor device 150 to produce a reconfigured semiconductor device 150. The reconfigured semiconductor device 150 can operate as the processing circuit 11.

[0093] FIG. 11 is a flow chart showing a method of repeating an operation on data stored in a memory using dedicated hardware logic circuits according to the present embodiment. According to the method, the operation can be repeated to update the data. The method S100 can include at least one of the following main steps. In the following description, the reference numerals used so far are used for the sake of understanding. The steps arranged in sequence in FIG. 11 are not required to be performed in the order of the arrangement. Any one or more of the steps can be performed in any order, if possible. The steps of the method S100 are described in the order of the arrangement.

[0094] In step S101, initialization is performed on one or more storage areas of the memory 15. In the initialization, any value can be stored in the storage area of ​​the memory 15. The initial value of the storage area is used as the initial value for the subsequent calculation.

[0095] In step S102, in response to the operation instruction signal SCNT and the basic clock Clock, a write enable signal WE and a read enable signal RE are generated within one period of the basic clock Clock.

[0096] In step S103, the memory area 25 specified by the calculation instruction signal SCNT in the memory 15 operable in synchronization with the multiplied clock Clk obtained by multiplying the basic clock Clock is read during the period of the read enable signal RE.

[0097] In step S104, an operation is performed on the read data DRT received from the memory 15 to generate the write data DWT. The operation can be performed, for example, using the operation circuit 17 (a dedicated hardware logic circuit). An exemplary operation can be either a count-up operation or a count-down operation.

[0098] In step S105, the write data WRT is written into the storage area 25 of the memory 15 during the period of the write enable signal WE.

[0099] In step S106, in response to the read signal SRD and the basic clock Clock, a read enable signal RE is generated within one period of the basic clock Clock.

[0100] In step S107, the storage area 25 of the memory 15 specified by the read signal SRD is read during the period of the read enable signal RE.

[0101] In step S108, the read data DRT received from the memory 15 is output.

[0102] Reading the memory 15 during the read enable signal RE can be repeated with each update of the read signal SRD.

[0103] According to these steps, it is possible to perform a calculation using a logic circuit, hold the result of the calculation, and provide the result of the calculation.

[0104] In step S109, the following can be repeated every time the calculation instruction signal SCNT is updated: reading the memory 15 during the period of the read enable signal RE, performing calculations on the read data DRT to generate the write data DWT, and writing the write data WRT to the memory 15 during the period of the write enable signal WE.

[0105] In step S110, the following can be repeated without updating the calculation instruction signal SCNT: reading the memory 15 during the period of the read enable signal RE; performing calculations on the read data DRT to generate write data DWT; and writing the write data WRT to the memory 15 during the period of the write enable signal WE.

[0106] These iterations allow the same operations to be repeated to update values.

[0107] The circuit information 140 (see FIG. 10) already described can be written into the reconfigurable semiconductor device 150 (see FIG. 10) to prepare the reconfigured semiconductor device 150. The reconfigured semiconductor device 150 can operate as the processing circuit 11. After the processing circuit 11 is prepared in this manner, the steps shown in FIG. 11 can be performed.

[0108] According to the above-described embodiment, it is possible to provide a processing circuit 11 that enables repeated calculations and retention of the calculation results using a dedicated hardware logic circuit, circuit information 140 for configuring the processing circuit 11, and a method for repeating calculations using a dedicated hardware logic circuit.

[0109] As can be understood from the above description, the present embodiment can have various aspects.

[0110] The processing circuit of a first aspect of this embodiment comprises a control circuit configured to receive at least one operation instruction signal and a base clock, and to generate a write enable signal and a read enable signal in response to the base clock and the operation instruction signal, a memory capable of operating in synchronization with a multiplied clock that is a multiplication of the base clock, and an arithmetic circuit configured to perform an operation on read data received from the memory using a dedicated hardware logic circuit to generate write data, and the memory is configured to read a first memory area identified by an address and including at least one memory element in response to the read enable signal, and to write the write data to the first memory area in response to the write enable signal.

[0111] In the processing circuit of the second aspect according to the first aspect of the present embodiment, the operation of the arithmetic circuit can be either an addition in a count-up operation or a subtraction in a count-down operation.

[0112] In a processing circuit of a third aspect according to the first aspect or the second aspect of this embodiment, when the calculation instruction signal is made active over a period including multiple cycles of the base clock and the address is fixed, the processing circuit can repeatedly update the value of the first memory area by repeating the calculation.

[0113] In a fourth aspect processing circuit according to any one of the first to third aspects of this embodiment, the operation instruction signal includes a first operation instruction signal and a second operation instruction signal, the first memory area is specified by a first address associated with the first operation instruction signal, the second operation instruction signal is exclusive to the first operation instruction signal, and the memory can be configured to read a second memory area specified by a second address associated with the second operation instruction signal in response to the read enable signal and to write the write data to the second memory area in response to the write enable signal.

[0114] In a processing circuit of a fifth aspect according to a fourth aspect of this embodiment, the control circuit includes a write / read control circuit and an address selection circuit, the write / read control circuit is configured to generate the write enable signal and the read enable signal, the address selection circuit is configured to generate a first address signal based on the first operation instruction signal, and the address selection circuit is configured to generate a second address signal based on the second operation instruction signal, and the memory can have an address input connected to an output of the address selection circuit.

[0115] In a processing circuit of a sixth aspect according to the first to fourth aspects of this embodiment, the control circuit is configured to receive at least one read signal, and the control circuit is configured to generate the read enable signal and not generate the write enable signal within one period of the basic clock in response to the read signal, and the memory is capable of reading a memory area identified by an address within a period of the read enable signal from the read signal.

[0116] In a processing circuit of a seventh aspect according to a sixth aspect of this embodiment, the read signal includes a first read signal and a second read signal, the first memory area is specified by a first address associated with the first read signal, the second read signal is exclusive to the first read signal, and the memory can be configured to read the second memory area identified by a second address associated with the second read signal in response to the read enable signal.

[0117] In a processing circuit of an eighth aspect according to a seventh aspect of this embodiment, the control circuit includes a write / read control circuit and an address selection circuit, the write / read control circuit is configured to generate the read enable signal in response to the first read signal and the second read signal, the address selection circuit is configured to generate a first address signal based on the first read signal, and the address selection circuit is configured to generate a second address signal based on the second read signal, and the memory may have an address input connected to an output of the address selection circuit.

[0118] In a processing circuit according to a ninth aspect in accordance with any one of the first to eighth aspects of the present embodiment, the control circuit, the memory, and the arithmetic circuit can be configured in an FPGA.

[0119] In the processing circuit of the tenth aspect according to any one of the first to ninth aspects of the present embodiment, the memory may include a random access memory.

[0120] In the processing circuit according to an eleventh aspect of any one of the first to tenth aspects of the present embodiment, the arithmetic circuit can generate an arithmetic result within a period of a half cycle of the base clock.

[0121] The circuit information of a twelfth aspect of this embodiment is circuit information describing a configuration of a circuit, written in a hardware description language, which causes the circuit to function as a processing circuit, the processing circuit comprising: a control circuit configured to receive at least one operation instruction signal and a base clock, and to generate a write enable signal and a read enable signal within one period of the base clock in response to the base clock and the operation instruction signal; a memory capable of operating in synchronization with a multiplied clock that is a multiplication of the base clock; and an arithmetic circuit configured to perform an operation on read data received from the memory using a dedicated hardware logic circuit to generate write data, and the memory is configured to read a first memory area identified by an address and including at least one memory element in response to the read enable signal, and to write the write data to the first memory area in response to the write enable signal.

[0122] The circuit information of the twelfth aspect of this embodiment can include circuit information in which a processing circuit according to any one of the first to eleventh aspects described above is described in a hardware description language as circuit information representing the configuration of the circuit.

[0123] A method of repeating an operation using a processing circuit including a logic circuit of dedicated hardware of the thirteenth aspect of this embodiment includes generating a read enable signal within one period of a base clock in response to an operation instruction signal and a base clock, and in a memory capable of operating in synchronization with a multiplied clock obtained by multiplying the base clock, during the period of the read enable signal, reading a memory area identified by the operation instruction signal, performing an operation on the read data from the memory using the logic circuit to generate write data, generating a write enable signal within one period of the base clock in response to the operation instruction signal and the base clock, writing the write data to the memory area during the period of the write enable signal, and repeating the reading, operation, and writing at least once, wherein performing the operation to generate write data and writing the write data to the memory area are performed in a period after the read data is determined and until the write enable signal ends.

[0124] The method of the fourteenth aspect in accordance with the thirteenth aspect of this embodiment may further comprise generating the read enable signal within one period of the base clock in response to a read signal and the base clock, reading a storage area of ​​the memory identified by the read signal during a period of the read enable signal, and outputting the read data received from the memory.

[0125] In the method of the fifteenth aspect according to the thirteenth or fourteenth aspect of this embodiment, the calculation may be either a count-up operation or a count-down operation.

[0126] The method of aspect 16 according to aspect 13, aspect 14 or aspect 15 of this embodiment may further comprise writing the circuit information described in aspect 12 into a reconfigurable semiconductor device to prepare the processing circuit.

[0127] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit and scope of the present invention, all of which are included in the technical concept of the present invention. [Explanation of symbols]

[0128] 11... Processing circuit, 13... Control circuit, 15...Memory, 17... Arithmetic circuit, 21... Multiplier circuit, 23 Clock generation circuit, 25...storage area, 27 Output circuit, 29... Initial value circuit, 31... Selection circuit, 33: Count-up circuit, 34...Arithmetic unit, 35... Countdown circuit, 36... Selection circuit, 41 Address selection circuit, 43...first multiplexing circuit, 45...second multiplexing circuit, 47 Write / read control circuit, 51 Address generation circuit; 140 Circuit information, 150....Reconfigurable semiconductor device, ADR: Address input, Address: Address signal, a1, a2, a3, a4... address signals, CLKIN: Clock input, Clk: Multiplied clock, Clock: Base clock, DIN... Input, DOUT... output, DRT...Read data, DWT: Write data, MEM1, MEM2, MEM3, MEM4...Storage area, RE...read permission signal, WE: Write enable signal, SCNT, SCNT1 to SCNT4... Calculation instruction signals SINT: initial value, SMUXC...first multiplexed signal, SMUXR...Second multiplexed signal, SRD, SRD1 to SRD4... read signal, SSEL: Selection signal, SSL··· switching signal.

Claims

1. a control circuit configured to receive at least one operation instruction signal and a basic clock, and to generate a write enable signal and a read enable signal within one period of the basic clock in response to the basic clock and the operation instruction signal; a memory operable in synchronization with a multiplied clock obtained by multiplying the base clock; an arithmetic circuit configured to perform an arithmetic operation on read data received from the memory using a dedicated hardware logic circuit to generate write data; Equipped with the memory is configured to read a first storage area, the first storage area being specified by an address and including a storage element, in response to the read enable signal, and to write the write data to the first storage area in response to the write enable signal; Processing circuit.

2. The operation of the arithmetic circuit is either an addition for a count-up operation or a subtraction for a count-down operation.

2. A processing circuit as claimed in claim 1.

3. when the operation instruction signal is made active over a period including a plurality of cycles of the base clock and the address is fixed, the processing circuit repeatedly updates the value of the first storage area by repeating the operation; 2. A processing circuit as claimed in claim 1.

4. the operation instruction signal includes a first operation instruction signal and a second operation instruction signal, the second operation instruction signal is exclusive to the first operation instruction signal, the first storage area is designated by a first address associated with the first operation instruction signal; the memory is configured to read a second storage area specified by a second address associated with the second operation instruction signal in response to the read enable signal, and to write the write data to the second storage area in response to the write enable signal.

2. A processing circuit as claimed in claim 1.

5. the control circuit includes a write / read control circuit and an address selection circuit; the write / read control circuit is configured to generate the write enable signal and the read enable signal; the address selection circuit is configured to generate a first address signal based on the first operation instruction signal; the address selection circuit is configured to generate a second address signal based on the second operation instruction signal; the memory having an address input connected to an output of the address selection circuit; 5. A processing circuit as claimed in claim 4.

6. The control circuitry is configured to receive at least one read signal; the control circuit is configured to generate the read enable signal and not generate the write enable signal within one period of the basic clock in response to the read signal; The memory reads a storage area specified by an address during a period of the read enable signal from the read signal.

2. A processing circuit as claimed in claim 1.

7. the read signal includes a first read signal and a second read signal; the second read signal is exclusive of the first read signal; the first storage area is designated by a first address associated with the first read signal; the memory is configured to read a second storage area identified by a second address associated with the second read signal in response to the read enable signal; A processing circuit as claimed in claim 6.

8. the control circuit includes a write / read control circuit and an address selection circuit; the write / read control circuit is configured to generate the read enable signal in response to the first read signal and the second read signal; the address selection circuit is configured to generate a first address signal based on the first read signal; the address selection circuit is configured to generate a second address signal based on the second read signal; the memory having an address input connected to an output of the address selection circuit; A processing circuit as claimed in claim 7.

9. The control circuit, the memory, and the arithmetic circuit are configured in an FPGA.

2. A processing circuit as claimed in claim 1.

10. the memory includes a random access memory; 2. A processing circuit as claimed in claim 1.

11. the arithmetic circuit generates an arithmetic result within a period of a half cycle of the base clock; 2. A processing circuit as claimed in claim 1.

12. Circuit information describing a configuration of a circuit, the circuit being described in a hardware description language, causing the circuit to function as a processing circuit; The processing circuitry includes: a control circuit configured to receive at least one operation instruction signal and a basic clock, and to generate a write enable signal and a read enable signal within one period of the basic clock in response to the basic clock and the operation instruction signal; a memory operable in synchronization with a multiplied clock obtained by multiplying the base clock; an arithmetic circuit configured to perform an arithmetic operation on read data received from the memory using a dedicated hardware logic circuit to generate write data; Equipped with the memory is configured to read a first storage area identified by an address and including at least one storage element in response to the read enable signal, and to write the write data to the first storage area in response to the write enable signal. Circuit information.

13. A method for repeating an operation using a processing circuit including a dedicated hardware logic circuit, comprising: generating a read enable signal within one period of the basic clock in response to the operation instruction signal and the basic clock; In a memory operable in synchronization with a multiplied clock obtained by multiplying the base clock, reading out a storage area specified by the operation instruction signal during a period of the read enable signal; performing an operation on read data from the memory using the logic circuit to generate write data; generating a write enable signal within one period of the basic clock in response to the operation instruction signal and the basic clock; writing the write data to the storage area during a period of the write enable signal; repeating the reading, the computing, and the writing at least once; Equipped with performing an operation to generate write data and writing the write data to the storage area are performed during a period after the read data is determined and before the write enable signal is terminated; method.

14. generating the read enable signal within one period of the basic clock in response to a read signal and the basic clock; reading out a storage area of ​​the memory specified by the read signal during a period of the read enable signal; outputting read data received from said memory; The method of claim 13 further comprising:

15. The calculation is performed by performing either a count-up operation or a count-down operation.

14. The method of claim 13.

16. The method according to claim 13, further comprising: writing the circuit information according to claim 12 into a reconfigurable semiconductor device to prepare the processing circuit.

Images