Liquid crystal display device

Abstract

To reduce the consumption power of a liquid crystal display device, suppress the deterioration of display, and suppress the deterioration of display due to an external factor such as a temperature.SOLUTION: As a transistor provided in each pixel, a transistor whose channel formation region is formed of an oxide semiconductor layer is used. When the oxide semiconductor layer has high purity, the off current value of the transistor at a room temperature can be made 10 aA / μm or less and the off current value thereof at 85°C can be made 100 aA / μm or less. Therefore, the consumption power of the liquid crystal display device can be reduced and the deterioration of display can be suppressed. As described above, the off current value of the transistor can be made 100 aA / μm or less even at a temperature as high as 85°C. Therefore, the deterioration of display of the liquid crystal display device due to an external factor such as a temperature can be suppressed.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a liquid crystal display device and an electronic device having the liquid crystal display device. [Background technology]

[0002] Liquid crystal display devices are used in a wide range of applications, from large displays such as television sets to small displays such as mobile phones. Therefore, the development of liquid crystal display devices requires cost reduction or high added value. In recent years, interest in the global environment has increased, and The development of low power consumption liquid crystal display devices has been attracting attention.

[0003] Patent Document 1 discloses a technique for reducing power consumption in a liquid crystal display device. Specifically, during a pause period in which all the scanning lines and data signal lines are in a non-selected state, all the data signals are A liquid crystal display that electrically disconnects the line from the data signal driver and puts it into a high impedance state An apparatus is disclosed. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2001-312253 A Summary of the Invention [Problem to be solved by the invention]

[0005] Generally, a liquid crystal display device has a pixel section in which a plurality of pixels are arranged in a matrix. The pixel has a transistor for controlling input of an image signal and a a liquid crystal element to which a voltage corresponding to the voltage is applied, and an auxiliary capacitance to hold the voltage applied to the liquid crystal element; The liquid crystal element has a liquid crystal material whose orientation changes in response to an applied voltage. The display of each pixel is controlled by controlling the orientation of the liquid crystal material.

[0006] In the liquid crystal display device disclosed in Patent Document 1, during a pause period, each pixel included in a pixel unit In other words, the image signal is not input to each pixel. The period during which the transistor that controls the input of the image signal remains in the off state becomes longer. The effect of image signal leakage through the transistor on the display of each pixel is obvious. Specifically, the voltage applied to the liquid crystal element is reduced, and the pixel having the liquid crystal element Deterioration (changes) in the display become apparent.

[0007] Furthermore, the leakage of image signals through the transistors varies depending on the operating temperature of the transistors. Specifically, as the operating temperature rises, the relay of the image signal through the transistor Therefore, the liquid crystal display device disclosed in Patent Document 1 is susceptible to large changes in the environment. When used outdoors in poor light conditions, it is difficult to maintain consistent display quality.

[0008] In view of this, one embodiment of the present invention is to reduce the power consumption of a liquid crystal display device and to prevent display degradation ( One of the objectives is to suppress deterioration of display quality.

[0009] In addition, one embodiment of the present invention is a method for preventing deterioration of display (decrease in display quality) due to external factors such as temperature. An object of the present invention is to provide a liquid crystal display device in which noise is suppressed. [Means for solving the problem]

[0010] The above-mentioned problem is that the channel formation region of the transistor provided in each pixel is made of oxide. This can be solved by applying a transistor composed of a semiconductor layer. The semiconductor layer is made by thoroughly removing impurities (such as hydrogen or water) that act as electron donors. The oxide semiconductor layer is highly purified by the above-mentioned process. In the case of 10 μm, the off-current value per 1 μm of channel width at room temperature is 10 aA. (1×10 -17 A) or less (this is expressed as 10 aA / μm).

[0011] In addition, the oxide semiconductor layer has a polarization potential of 2.0 eV or more, preferably 2.5 eV or more, and more preferably In addition, the oxide semiconductor layer has a band gap of 3.0 eV or more. By this, the conductivity type of the oxide semiconductor layer approaches the intrinsic type. This can suppress the generation of carriers due to thermal excitation. It is possible to reduce the increase in off-state current that accompanies an increase in the operating temperature of the transistor. When the channel length is 10 μm, the off-state current per 1 μm of channel width at 85°C is 100aA(1×10 -16 A) or less (this is 100aA / μm (represented as ).

[0012] Specifically, one embodiment of the present invention is a transistor in which switching is controlled by a scan line driver circuit. A signal line driver circuit inputs an image signal to one of its terminals through the transistor. A voltage corresponding to the image signal is applied to the other terminal by supplying a common potential to the other terminal. and a capacitance element for holding a voltage applied to the liquid crystal element. A liquid crystal display device in which pixels are arranged in a matrix, A control circuit is provided to control the operation of a signal line driver circuit and select the input of the image signal to the pixel. The transistor has a channel formation region formed of an oxide semiconductor layer and is in an off state. The leakage of the image signal through the transistor in the above-mentioned state causes the image The liquid crystal display device is characterized in that the signal leakage is smaller than that of the liquid crystal display device. Effect of the Invention

[0013] In the liquid crystal display device according to one embodiment of the present invention, a channel A transistor in which a formation region is formed using an oxide semiconductor layer is used. By purifying the semiconductor layer, the off-state current of the transistor at room temperature was increased to 10A. It is possible to reduce the off-state current value to 100aA / μm or less at 85°C. Therefore, it is possible to reduce leakage of image signals through the transistor. That is, when the frequency of writing image signals to the pixel having the transistor is reduced, As a result, the power consumption of the liquid crystal display device can be reduced. It becomes possible to reduce power consumption and suppress deterioration of the display (decrease in display quality).

[0014] As described above, the transistor has an off-state current value of 1000 V even at a high temperature of 85° C. In other words, the transistor can be The increase in the off-state current value with increasing temperature is extremely small. By using a transistor as a transistor provided in each pixel of a liquid crystal display device, This reduces the effect of external factors such as the temperature on the leakage of image signals from the pixels. In other words, when the liquid crystal display device is used outdoors where the environment changes greatly, Even if the liquid crystal display device is a liquid crystal display device that can suppress deterioration of display (decrease in display quality). . [Brief description of the drawings]

[0015] [Figure 1] 1A and 1B illustrate a liquid crystal display device according to Embodiment 1. [Diagram 2] 1A to 1C illustrate a liquid crystal display device according to Embodiment 1. [Diagram 3] 1A to 1C illustrate a liquid crystal display device according to Embodiment 1. [Figure 4] 1A to 1D illustrate a transistor according to Embodiment 2. [Diagram 5] 1A and 1B illustrate a liquid crystal display device according to Embodiment 3. [Figure 6] 1A to 1F are diagrams illustrating electronic devices according to embodiment 4. [Figure 7] FIG. 4 is a graph showing initial characteristics of a transistor according to Example 1. [Figure 8] 3A and 3B are top views of an evaluation element of a transistor according to Example 1. [Figure 9] 4A and 4B are diagrams showing the Vg-Id characteristics of an evaluation element of the transistor according to Example 1. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and may be modified in any form without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various modifications may be made to the details. The present invention should not be construed as being limited to the description of the following embodiments.

[0017] The source and drain terminals of a transistor depend on the structure and operating conditions of the transistor. Therefore, in this document, the roles of the source and drain of a transistor are In order to distinguish between the two terminals, one of the terminals is referred to as the first terminal and the other as the second terminal.

[0018] In addition, the size, layer thickness, or area of ​​each component shown in the drawings of each embodiment may differ from the actual size, layer thickness, or area shown in the drawings of each embodiment. In some cases, the figures are exaggerated for clarity. Therefore, the figures are not necessarily limited to the scale. In addition, ordinal numbers such as "first," "second," and "third" used in this specification are not limited to the structure. It is added to avoid confusion of the constituent elements, and is not a numerical limitation. do.

[0019] (Embodiment 1) In this embodiment, an example of an active matrix liquid crystal display device will be described. In general, it is an active matrix type that can select the input of an image signal to the pixel section. The liquid crystal display device will be described with reference to FIGS. 1 to 3. FIG.

[0020] An example of the configuration of a liquid crystal display device according to the present embodiment will be described below with reference to FIG. FIG. 1A is a diagram showing a configuration example of a liquid crystal display device. The liquid crystal display device shown in FIG. The display device includes a circuit 10, a scanning line driver circuit 11, a signal line driver circuit 12, and a pixel section 13. Furthermore, the pixel section 13 has a plurality of pixels 14 arranged in a matrix. 1B is a diagram showing an example of the configuration of a pixel 14. The pixel 14 shown in FIG. 1B has a gate terminal connected to a scanning line The first terminal is electrically connected to the driving circuit 11, and the second terminal is electrically connected to the signal line driving circuit 12. A transistor 15, one terminal of which is electrically connected to the second terminal of the transistor 15, and the other terminal of which is electrically connected to the second terminal of the transistor 15. A liquid crystal element 16 having one terminal electrically connected to a wiring that supplies a common potential (Vcom); One terminal is electrically connected to the second terminal of the transistor 15 and one terminal of the liquid crystal element 16. and the other terminal is electrically connected to a wiring that supplies a common potential (Vcom). 17 and

[0021] In the liquid crystal display device of this embodiment, the transistor 15 is switched by the scanning line driving circuit 11. The signal line driving circuit 12 controls switching, and a display is applied to the liquid crystal element 16 via the transistor 15. The liquid crystal element 16 is a liquid crystal element sandwiched between one terminal and the other terminal. A voltage equal to the potential difference between the image signal and a common potential (Vcom) is applied to the liquid crystal layer. The alignment state of the liquid crystal layer is controlled by the voltage applied to the liquid crystal display device of the present embodiment. In this device, the display of each pixel 14 is controlled by utilizing the orientation. It is provided to maintain the voltage applied to the liquid crystal element 16 .

[0022] In addition, in the liquid crystal display device shown in the present embodiment, the control circuit 10 controls the scanning line driving circuit. By controlling the operation of the signal line driver circuit 12 and the signal line driver circuit 13, an image signal is input to the pixel section 13. It is possible to select:

[0023] Next, specific examples of components of the liquid crystal display device of the present embodiment will be described.

[0024] <Control circuit 10> FIG. 2 is a diagram showing an example of the configuration of the control circuit 10. The control circuit 10 shown in FIG. A circuit 20, a memory circuit 21, a comparison circuit 22, a selection circuit 23, and a display control circuit 24. Yes.

[0025] The signal generating circuit 20 operates the scanning line driving circuit 11 and the signal line driving circuit 12 to generate a pixel signal. Specifically, the pixel section 13 is a circuit that generates signals for forming an image. Image signals (Data) input to multiple pixels arranged in a pixel array, scanning line drive A signal for controlling the operation of the circuit 11 or the signal line driving circuit 12 (for example, a start pulse signal ( SP), clock signal (CK), and high power supply potential (Vdd) and This is a circuit that generates and outputs a low power supply potential (Vss) and the like. Note that the control circuit 1 shown in FIG. At 0, the signal generating circuit 20 outputs an image signal (Data) to the memory circuit 21. The display control circuit 24 controls the operation of the scanning line drive circuit 11 or the signal line drive circuit 12. The signal generating circuit 20 outputs a signal to the memory circuit 21. If the signal (Data) is an analog signal, it is converted into a digital signal via an A / D converter, etc. The image signal (Data) can also be converted into a digital signal.

[0026] The memory circuit 21 stores image signals for forming a first image to an n-th image in the pixel portion 13. A plurality of memories for storing image signals for forming an image of The memory 25 is a dynamic random access memory (DRAM). cess Memory), SRAM (Static Random Access M The memory 25 may be configured using a memory element such as a memory cell. The number of memories 25 may be as follows: The number of the image signals stored in the memory 25 is not limited to a specific number. 2 and selectively read out by a selection circuit 23.

[0027] The comparison circuit 22 compares the kth image (k is a natural number equal to or greater than 1 and less than n) stored in the memory circuit 21 with the kth image (k is a natural number equal to or greater than 1 and less than n). ) and an image signal for forming an image k+1. The kth image and the kth image are compared to detect the difference. The k+1th image and the k+1th image are images that are displayed consecutively in the pixel section 13. If a difference is detected by comparing the image signals at On the other hand, the comparison circuit 22 compares the image signals to determine that the difference If no part is detected, the two images formed by the image signal are determined to be still images. That is, the comparison circuit 22 detects the difference between the two signals and continuously displays the difference. The image signal for forming the image to be displayed is an image signal for displaying a moving image or a still image. The comparison circuit 22 is a circuit for determining whether the image signal is for displaying a still image. Even if the difference is set to be detected when it exceeds a certain level, good.

[0028] The selection circuit 23 determines whether or not to output an image signal to the pixel unit based on the difference detected by the comparison circuit 22. Specifically, the selection circuit 23 is a circuit that selects between the two signals when a difference is detected by the comparison circuit 22. An image signal for forming an image is output, and an image signal for forming an image in which no difference is detected is output. This is a circuit that does not output a signal.

[0029] The display control circuit 24 receives a start pulse signal (SP), a clock signal (CK), and a high power supply voltage. A scanning line driving circuit 11 and a signal for controlling signals such as a high power supply potential (Vdd) and a low power supply potential (Vss) This is a circuit that controls the supply to the line driving circuit 12. Specifically, the comparison circuit 22 If it is determined that a difference is detected between the images displayed consecutively, the selection circuit 23 The image signal (Data) supplied from the scanning line 13 is output to the signal line driving circuit 12. A control signal (start pulse signal (SP)) is sent to the drive circuit 11 and the signal line drive circuit 12. , clock signal (CK), high power supply potential (Vdd), and low power supply potential (Vss) On the other hand, if the comparator circuit 22 judges it to be a still image (i.e., if the image is not displayed continuously), If no difference is detected, the selection circuit 23 does not supply an image signal (Data). At the same time, a control signal (start pulse) is sent to the scanning line driving circuit 11 and the signal line driving circuit 12. The pulse signal (SP), clock signal (CK), high power supply potential (Vdd), and low power supply potential (V In other words, if the comparator circuit 22 judges the image to be a still image (continuous If no difference is detected between the images displayed successively, the scanning line driving circuit 11 and the signal line The operation of the driver circuit 12 is completely stopped. However, if the period determined to be a still image is short, The high power supply potential (Vdd) and the low power supply potential (Vss) can be continuously supplied. Note that the supply of the high power supply potential (Vdd) and the low power supply potential (Vss) may be performed in a certain arrangement. The potential of the line is fixed to a high power supply potential (Vdd) or a low power supply potential (Vss). That is, when the wiring in question is in a certain potential state, the wiring is turned off to a high power supply potential (Vdd) or a low power supply potential (Vss Of course, this change in potential consumes power. By stopping and re-supplying the high power supply potential (Vdd) and low power supply potential (Vss), As a result, power consumption may increase. In such a case, a high power supply potential (Vdd ) and the low power supply potential (Vss). In the description, "not supplying" a signal means that a wiring that supplies the signal is at a predetermined potential. This means that a potential different from that of the wiring is supplied, or the potential of the wiring is in a floating state. do.

[0030] In the control circuit 10, the scanning line driving circuit 11 and the signal line driving circuit 12 are By controlling the operation, it is possible to reduce the power consumption of the liquid crystal display device.

[0031] <Transistor 15> The transistor 15 is a transistor in which a channel formation region is formed using an oxide semiconductor layer. In order to suppress the fluctuation of electrical characteristics, the oxide semiconductor layer is formed by absorbing hydrogen, which is a factor of the fluctuation. Impurities such as moisture, hydroxyl groups, and hydrides (also called hydrogen compounds) are intentionally removed, and The main component material that constitutes the oxide semiconductor is also reduced during the process of removing impurities. By supplying oxygen, a highly purified and electrically I-type (intrinsic) oxide semiconductor is obtained. The oxide semiconductor has a polarization energy of 2 eV or more, preferably 2.5 eV or more, and more preferably 1.5 eV or more. More preferably, it has a band gap of 3.0 eV or more.

[0032] In addition, there are very few carriers (close to zero) in the highly purified oxide semiconductor. The carrier density is 1×10 14 / cm 3 Less than 1 x 10 12 / cm 3 The following is the result. In other words, the carrier density of the oxide semiconductor layer is made close to zero. Since the rear is extremely small, the off-state current value can be reduced. Therefore, in the above-mentioned transistor, the channel width (w) is set to 1 μm. The off-state current per unit area at room temperature is 10 aA / μm (1×10 -17 A / μm) or less The off-state current at 85°C was set to 100 aA / μm (1×10 -16 A / μm Generally, it is possible to make the thickness of a transistor having amorphous silicon smaller than 100 nm. The off-state current of the diode at room temperature is 1×10 -13 A / μm or more. Since there is no n-junction and no hot carrier degradation, the electrical characteristics of the transistor are not affected by these factors. This allows the retention period of the image signal of each pixel 14 to be extended. In other words, the interval between rewriting of the image signal when displaying a still image can be lengthened. For example, the interval between writing of image signals is set to 10 seconds or more, preferably 30 seconds or more, and more preferably The writing interval can be set to between 1 minute and 10 minutes. By increasing the writing interval, power consumption can be reduced. This can increase the effectiveness of the device.

[0033] The difficulty in passing an off-state current through a transistor can be expressed as an off-state resistivity. The resistivity is the resistivity of the channel formation region when the transistor is off, and is the off resistivity can be calculated from the off-state current.

[0034] Specifically, if the values ​​of the off-state current and drain voltage are known, the transistor can be calculated from Ohm's law. The resistance value when the transistor is off (off resistance R) can be calculated. The cross-sectional area A of the region and the length L of the channel formation region (corresponding to the distance between the source and drain electrodes) are Once this is known, the off-resistivity ρ can be calculated from the equation ρ=RA / L (R is the off-resistance).

[0035] Here, the cross-sectional area A is given by: It can be calculated from A = dW. Also, the length L of the channel formation region is the channel length L. As described above, the off-state resistivity can be calculated from the off-state current.

[0036] The off-resistance of the transistor including the oxide semiconductor layer of this embodiment is 1×10 11 Ω cm or more is preferable, and 1×10 12 Ω·cm or more is more preferable.

[0037] In this way, the hydrogen contained in the oxide semiconductor layer is thoroughly removed, resulting in a highly purified oxide semiconductor layer. A transistor in which an oxide semiconductor layer is used in a channel formation region of the transistor has an off-state current This means that when the transistor is in the off state, the oxide The conductor layer can be regarded as an insulator when designing a circuit. In the on-state, the transistor is a transistor having an amorphous silicon layer. It is expected to have a higher current supply capacity than a conventional inverter.

[0038] In addition, in the transistor having a low-temperature polysilicon layer, a transistor having an oxide semiconductor layer The off-state current at room temperature is estimated to be about 10,000 times higher than that of a transistor. Therefore, in a transistor including an oxide semiconductor layer, The storage capacitance is equivalent (approximately 0.1 pF) to transistors with a thermal polysilicon layer. In this case, the voltage retention period can be extended by about 10,000 times. When displaying video at 60 frames per second, the retention period for one signal write is 1000 0 times, about 160 seconds. And even with a small number of image signal writes, Still images can be displayed on the display unit.

[0039] By lengthening the retention period, it is possible to reduce the frequency of supplying image signals to pixels. In particular, the liquid crystal display device capable of selectively inputting image signals to pixel portions as described above The effect of applying the above-mentioned transistor to the liquid crystal display device is great. In a display device, there is a possibility that image signals will not be input to the pixels for a long period of time. The transistor thus obtained is used as a transistor for controlling the input of an image signal to a pixel. This makes it possible to suppress deterioration (changes) in the display of the pixel.

[0040] The transistor is also used as a switch for controlling input of an image signal to a pixel. This makes it possible to reduce the size of the capacitance element provided in the pixel. This improves the aperture ratio of the pixel and allows image signals to be input to the pixel at high speed. It will be possible to do things like this.

[0041] <Liquid crystal element 16 and capacitance element 17> When the above-mentioned transistor is used as the transistor 15 for controlling the input of the image signal, In this case, it is preferable to use a substance having a high specific resistivity as the liquid crystal material of the liquid crystal element 16. The reason for this will be explained with reference to FIG. 3. A pixel having a transistor including a silicon layer and a transistor including the oxide semiconductor layer described above are provided. 1 is a schematic diagram showing a path of leakage of an image signal in a pixel having a transistor;

[0042] As shown in FIG. 1B, the pixel includes a transistor 15, a liquid crystal element 16, and a capacitor. When the transistor 15 is in an off state, the That is, the transistor 15 is equivalent to a resistor (R Tr-Off ) The liquid crystal element 16 is then turned on as a resistor (R LC ) and capacity (C LC ) is equivalent to the circuit represented by When an image signal is input to the pixel, the image signal is transferred to the capacitance (C S ) and and the capacitance (C LC ) is stored. Then, the transistor 15 is turned off. Then, as shown in FIG. 3(B) and (C), The image signal leaks. Note that in FIG. 3B, the transistor 15 is made of amorphous silicon. FIG. 3(C) is a schematic diagram showing leakage of an image signal when a transistor having a layer is used. ) is an image signal when the transistor 15 is a transistor including an oxide semiconductor layer. FIG. 1 is a schematic diagram showing leakage current of a transistor having an amorphous silicon layer; The resistance of the pixel is lower than that of the liquid crystal element. Therefore, as shown in FIG. 3(B), The leakage current is mainly due to leakage through transistors with amorphous silicon layers (see Fig. 3(B), the main leaks are via routes A and B. On the other hand, highly purified oxide The off-resistance value of the transistor including the semiconductor layer is higher than the resistance value of the liquid crystal element. As shown in FIG. 3C, the image signal leaks mainly through the liquid crystal element ( In FIG. 3(C), the leak mainly occurs via paths C and D.

[0043] That is, in the conventional liquid crystal display device, the retention characteristics of the image signal in each pixel are The characteristics of the transistors in the pixels were the limiting factor, but the By applying a transistor having a dielectric layer to a transistor provided in each pixel, The resistance value of the element is the rate-limiting point. Therefore, the specific resistance of the liquid crystal material of the liquid crystal element 16 is It is preferable to apply a substance with a high rate.

[0044] Specifically, a pixel includes a transistor including a highly purified oxide semiconductor layer. In liquid crystal displays, the specific resistivity of the liquid crystal material is 1×10 12 Ω cm or more, Preferably 1 x 10 13 Ω cm, and more preferably 1×10 1 4 It is preferable that the resistance of the liquid crystal material is more than Ω·cm. When a device is constructed, the resistance may be affected by impurities from the alignment film and sealing material. 1×10 11 Ω cm or more, and more preferably 1×10 12 Exceeds Ω·cm The specific resistivity values ​​in this specification are measured at 20° C. value.

[0045] During the retention period of the still image display, the common potential to the other terminal of the liquid crystal element 16 is It is also possible to leave the terminal in a floating state without supplying (Vcom). A switch is provided between the terminal and a power supply that provides a common potential (Vcom), and during the write period After turning on the switch and applying the common potential (Vcom) from the power supply, In this case, the switch can be turned off to make the floating state. It is preferable to use a transistor including a purified oxide semiconductor layer. By setting the other terminal of 16 in a floating state, it is possible to prevent a display error in pixel 14 due to an incorrect pulse or the like. This is because the deterioration (change) of the display can be reduced when the transistor 15 is in the off state. When the potential of the first terminal of the transistor 15 is changed by an incorrect pulse, The potential of one terminal of the liquid crystal element 16 also changes due to the change in the potential of the other terminal of the liquid crystal element 16. When a common potential (Vcom) is applied to the liquid crystal element 16, the fluctuation is applied to the liquid crystal element 16. On the other hand, if the other terminal of the liquid crystal element is in a floating state, The potential of the terminal also varies due to capacitive coupling. Therefore, the potential of the first terminal of the transistor 15 is Even if the voltage applied to the liquid crystal element 16 fluctuates due to an incorrect pulse, the change in the voltage Therefore, deterioration (change) of the display in the pixel 14 can be reduced.

[0046] In addition, the capacitance of the capacitive element 17 (C S The size of the transistor in each pixel is However, as mentioned above, the high-purity oxide By applying a transistor having a solid semiconductor layer to a transistor in a pixel, The conditions required for the design of element 17 vary greatly. The content will be explained.

[0047] Generally, a pixel has a transistor having an amorphous silicon layer. The off-resistance value when a stator is applied is 1×10 12 The resistance of the liquid crystal element is about 1 ×1015 Therefore, the transistors in the pixels are made of highly purified oxide. By using a transistor having a semiconductor layer, the leakage of image signals in the pixel can be reduced by 1 That is, the capacitance of the capacitance element 17 (C S ) to about 1 / 1000 of the original size, or to display a still image at that pixel. The frequency of image signal rewriting can be reduced to about 1 / 1000. For example, if you are writing image signals 60 times per second, it will be about once every 15 seconds. It is possible to reduce the frequency of the write to as low as possible. By applying an element with a capacitance of about 50 fF, the image signal is transmitted to the pixel for about 30 seconds. For example, in order to hold an image signal in each pixel for 5 seconds or more and 5 minutes or less, , the capacitance of the capacitive element 17 (C S ) is preferably 0.5 pF or more, and more preferably 1 pF or more. It is more preferable to use the above-mentioned values. Additional notes:

[0048] The contents of this embodiment or a part of the contents may be the same as the contents of other embodiments or the contents of other embodiments. It is possible to freely combine it with any part of the above or with the contents of the examples or any part of the contents.

[0049] (Embodiment 2) In this embodiment, an example of the transistor described in Embodiment 1 will be described with reference to FIGS. Please refer to D) for explanation.

[0050] 4A to 4D show a specific configuration and a manufacturing process of the transistor shown in the first embodiment. It should be noted that the thin film transistor 410 shown in FIGS. It is one of the bottom gate structures called channel etch type and is an inverted staggered thin film transistor. Also, in Fig. 4(A) to (D), a thin film transistor with a single gate structure is shown. However, if necessary, a thin-film transistor having a multi-gate structure having a plurality of channel forming regions may be used. It can be a star.

[0051] Referring to FIGS. 4(A) to 4(D), a thin film transistor 410 is fabricated on a substrate 400. The process for doing so will be described below.

[0052] First, a conductive film is formed on a substrate 400 having an insulating surface, and then a first photolithography process is performed. A gate electrode layer 411 is formed by a resist patterning process. The resist mask may be formed by an inkjet method. When the film is formed by the photolithography method, a photomask is not used, and therefore the manufacturing cost can be reduced.

[0053] There is no significant limitation on the substrate that can be used for the substrate 400 having an insulating surface, but at least At the very least, it is necessary for the material to have heat resistance sufficient to withstand subsequent heat treatment. For example, Glass substrates such as barium borosilicate glass and aluminoborosilicate glass can be used. In addition, when the temperature of the subsequent heat treatment is high, the distortion point of the glass substrate is 73 It is recommended to use a temperature above 0°C.

[0054] An insulating film serving as a base film may be provided between the substrate 400 and the gate electrode layer 411. The silicon nitride film, the silicon oxide film, and the like have a function of preventing the diffusion of impurity elements from the substrate 400. The insulating layer is made of one or more films selected from a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The insulating film can be formed by a laminate structure.

[0055] The material of the gate electrode layer 411 is selected from the group consisting of molybdenum, titanium, chromium, tantalum, and tungsten. Metallic materials such as stainless steel, aluminum, copper, neodymium, scandium, etc., or materials that contain these as their main components The insulating film 10 can be formed as a single layer or a laminated layer using an alloy material.

[0056] For example, the gate electrode layer 411 may have a two-layer laminate structure of molybdenum on an aluminum layer. Two-layer structure with a molybdenum layer on a copper layer, two-layer structure with a titanium nitride layer on a copper layer, Two-layer structure with a titanium nitride layer or a tantalum nitride layer laminated, and a titanium nitride layer and a molybdenum layer laminated A two-layer structure is preferable. A three-layer structure is preferably a tungsten layer or a tungsten nitride layer. A layer of tin and an alloy layer of aluminum and silicon or an alloy layer of aluminum and titanium. It is preferable to use a three-layer structure in which a titanium nitride layer or a titanium layer is laminated.

[0057] Next, the gate insulating layer 402 is formed over the gate electrode layer 411 .

[0058] The gate insulating layer 402 is formed by depositing silicon oxide using a plasma CVD method, a sputtering method, or the like. A silicon layer, a silicon nitride layer, a silicon oxynitride layer, a silicon oxynitride layer, or an aluminum oxide layer. The aluminum layer can be formed as a single layer or a multilayer. Silicon oxide nitride layer is formed by plasma CVD using silicon (SiH4), oxygen and nitrogen. In addition, hafnium oxide (HfO x ), Tantalum oxide ( TaO xThe thickness of the gate insulating layer 402 is The thickness is 100 nm to 500 nm. In the case of a multilayer structure, the thickness is, for example, 50 nm to 200 nm. a first gate insulating layer having a thickness of 5 nm to 300 nm on the first gate insulating layer; The second gate insulating layer is then laminated.

[0059] Here, the gate insulating layer 402 is an oxide film having a thickness of 100 nm or less formed by plasma CVD. A silicon nitride layer is formed.

[0060] In addition, a silicon oxynitride film was formed as the gate insulating layer 402 by using a high density plasma device. Here, the high density plasma device is a device having a density of 1×10 11 / cm 3 More This refers to a device that can achieve a high plasma density. For example, a device that can apply microwave power of 3kW to 6kW The plasma is generated by applying a voltage to deposit an insulating film.

[0061] The chamber is filled with silane (SiH4), nitrous oxide (N2O), and rare gases as material gases. By introducing a gas, high-density plasma is generated under a pressure of 10 Pa to 30 Pa, and the plasma is heated on insulating surfaces such as glass. An insulating film is formed on a substrate having a surface. Then, the supply of silane (SiH4) is stopped and a large Plasma treatment is performed on the insulating film surface by introducing nitrous oxide (N2O) and rare gases without exposing it to air. This can be done by introducing at least nitrous oxide (N2O) and a rare gas onto the insulating film surface. The plasma treatment is performed after the formation of the insulating film. It is an insulating film that can ensure reliability even if it is thin, for example, less than 100 nm.

[0062] When forming the gate insulating layer 402, silane (SiH4) and nitrous oxide are introduced into the chamber. The flow ratio of nitrogen (N2O) is in the range of 1:10 to 1:200. The rare gases that can be used include helium, argon, krypton, and xenon. Of these, it is preferable to use argon, which is inexpensive.

[0063] In addition, the insulating film obtained by the high-density plasma device can be formed with a constant thickness. In addition, the insulating film obtained by the high-density plasma device is a thin film. The thickness can be precisely controlled.

[0064] The insulating film obtained by the above process sequence is the same as that obtained by a conventional parallel plate type PCVD apparatus. When comparing the etching rates using the same etchant, The insulating film obtained by the parallel plate PCVD apparatus is 10% or more or 20% slower than that obtained by the parallel plate PCVD apparatus. The insulating film obtained using a high-density plasma device can be said to be a dense film.

[0065] Note that the oxide semiconductor layer (highly purified oxide) to be made i-type or substantially i-type in a later step Since the oxide semiconductor layer is extremely sensitive to the interface state and interface charge, The interface is important. Therefore, the gate insulating layer in contact with the highly purified oxide semiconductor layer must be highly Therefore, high-density plasma CVD equipment using microwaves (2.45GHz) is required. is preferable because it can form a dense, high-quality insulating film with high dielectric strength. The close contact between the oxide semiconductor layer and the high-quality gate insulating layer reduces the interface state and improves the interface characteristics. The reason is that the quality of the gate insulating layer is good. Of course, it is possible to reduce the interface state density with the oxide semiconductor layer and form a good interface. It is important to:

[0066] Next, an oxide semiconductor film 4 with a thickness of 2 nm to 200 nm is formed on the gate insulating layer 402. Before the oxide semiconductor film 430 is formed by a sputtering method, A reverse sputtering process is performed by introducing an oxygen gas to generate plasma, and a surface of the gate insulating layer 402 is It is preferable to remove any powdery substances (also called particles or dust) adhering to the surface. Putting is a process in which no voltage is applied to the target side, but an RF power source is applied to the substrate side in an argon atmosphere. This is a method of modifying the surface by applying a voltage to generate plasma on the substrate. Instead of the argon atmosphere, nitrogen, helium, oxygen, etc. may be used.

[0067] The oxide semiconductor film 430 may be an In-Ga-Zn-O-based, In-Sn-O-based, or In-Sn- Zn-O, In-Al-Zn-O, Sn-Ga-Zn-O, Al-Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, Sn-Zn-O system, Al-Zn-O system In—O-based, Sn—O-based, or Zn—O-based oxide semiconductor films are used. The oxide semiconductor film 430 was formed by spun using an In-Ga-Zn-O-based metal oxide target. The cross-sectional view at this stage corresponds to FIG. 4(A). The conductive film 430 is formed in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas ( Typically, it is formed by sputtering in a mixed atmosphere of argon and oxygen. In addition, when using the sputtering method, the SiO2 content is 2% by weight or more and 10% by weight or less. The oxide semiconductor film 430 is formed using a target, and the SiO x (X> 0), which crystallizes during the heat treatment for dehydration or dehydrogenation in the subsequent process. This can prevent the item from being put away.

[0068] Here, a metal oxide target containing In, Ga, and Zn (In2O3:Ga2O 3:ZnO=1:1:1[mol], In:Ga:Zn=1:1:0.5[atom]) The distance between the substrate and the target was 100 mm, the pressure was 0.2 Pa, and the direct current (DC) was Power supply: 0.5 kW, argon and oxygen (argon:oxygen = 30 sccm:20 sccm, oxygen The film is formed in an atmosphere with a nitrogen flow rate of 40%). This is preferable because it reduces the amount of powdery material that is generated during deposition and also makes the film thickness distribution uniform. The thickness of the Zn-O-based film is set to 5 nm or more and 200 nm or less. The semiconductor film was deposited by sputtering using an In-Ga-Zn-O metal oxide target. In-Ga-Zn-O system film with a thickness of 20 nm was formed. Metal oxide targets containing In:Ga:Zn=1:1:1[atom] or I It is also possible to use a target with a composition ratio of n:Ga:Zn=1:1:2 [atom]. Cut.

[0069] There are two types of sputtering: RF sputtering, which uses a high-frequency power source as the sputtering power source, and DC sputtering. There is also the pulsed DC sputtering method, which applies a pulsed bias. The DC sputtering method is mainly used for depositing insulating films, while the DC sputtering method is mainly used for depositing metal films. It is used in.

[0070] There are also multi-target sputtering devices that can accommodate multiple targets of different materials. The TA equipment can deposit layers of different materials in the same chamber, or multiple layers in the same chamber. It is also possible to form a film by discharging two different materials simultaneously.

[0071] In addition, a sputtering apparatus using a magnetron sputtering method equipped with a magnet mechanism inside the chamber The plasma generated by microwaves without glow discharge is used for ECR sputtering. There are sputtering devices that use the TA method.

[0072] In addition, as a method for forming a film using a sputtering method, a target material and a sputtering gas are mixed during film formation. Reactive sputtering is a method for forming thin films of compounds by chemically reacting them with each other, and There is also a bias sputtering method in which a voltage is also applied to the substrate.

[0073] Next, the oxide semiconductor film 430 is subjected to a second photolithography process to form an island-shaped oxide semiconductor film. The resist mask used in this process is an inkjet printer. If the resist mask is formed by the inkjet method, the photomask Since no disks are used, manufacturing costs can be reduced.

[0074] Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature of the first heat treatment is 400° C. or more and 750° C. or less, preferably 400° C. or more so as to prevent distortion of the substrate. Here, the substrate is introduced into an electric furnace, which is a type of heat treatment device, and the oxide semiconductor is The conductor layer was heat-treated at 450°C for 1 hour in a nitrogen atmosphere, and then exposed to the air. Therefore, water or hydrogen is prevented from being recontaminated into the oxide semiconductor layer, and the oxide semiconductor layer 431 is obtained. (See Figure 4(B)).

[0075] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction from a heating element such as a resistance heating element or the like. The apparatus may be equipped with a device for heating the object to be treated by thermal radiation. For example, the GRTA (Ga s Rapid Thermal Anneal) equipment, LRTA (Lamp Rapi) d Thermal Anneal (RTA) equipment The LRTA device can be equipped with halogen lamps, metal halide lamps, etc. Iridium lamps, xenon arc lamps, carbon arc lamps, high pressure sodium lamps, This is a device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a pressure mercury lamp. The GRTA device is a device that uses high-temperature gas for heat treatment. Inert gases such as argon or nitrogen that do not react with the workpiece during heat treatment An active gas is used.

[0076] For example, the first heat treatment is performed in an inert gas heated to a high temperature of 650°C to 700°C. The substrate is moved in and heated for a few minutes, then the substrate is moved out and heated to a high temperature inert gas. You can also use GRTA, which is a method of removing the food from inside the container. Using GRTA, high-temperature heat treatment can be performed in a short time. It becomes.

[0077] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the gas does not contain water, hydrogen, etc. or rare gases such as helium, neon, argon, etc., with a purity of 6N (99.9999%) or more Preferably, the concentration of impurities is 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, It is preferable to set the concentration to 0.1 ppm or less.

[0078] In addition, the first heat treatment is performed on the oxide semiconductor film 430 before it is processed into an island-shaped oxide semiconductor layer. In that case, after the first heat treatment, the substrate is removed from the heating device. Then, a second photolithography step is performed.

[0079] The heat treatment for dehydration or dehydrogenation of the oxide semiconductor layer is performed after the formation of the oxide semiconductor layer. After a source electrode layer and a drain electrode layer are stacked on the oxide semiconductor layer, This may be performed either after forming a protective insulating film on the drain electrode layer or after forming a protective insulating film on the drain electrode layer.

[0080] In addition, in the case where an opening is formed in the gate insulating layer 402, the process is performed after the oxide semiconductor film 430 This may be carried out before or after the dehydration or dehydrogenation treatment.

[0081] Note that the etching of the oxide semiconductor film 430 here is not limited to wet etching. Alternatively, dry etching may be used.

[0082] The etching gas used in dry etching is a gas containing chlorine (chlorine-based gas, e.g. For example, chlorine (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4), Carbon (such as CCl4) is preferred.

[0083] In addition, gases containing fluorine (fluorine-based gases, such as carbon tetrafluoride (CF4), sulfur hexafluoride ( SF6), nitrogen trifluoride (NF3), trifluoromethane (CHF3), etc.), hydrogen bromide ( HBr), oxygen (O2), and rare gases such as helium (He) and argon (Ar) A gas having a gas added thereto, etc. can be used.

[0084] As a dry etching method, parallel plate type RIE (Reactive Ion Etc. fing method and ICP (Inductively Coupled Plasma) The inductively coupled plasma etching method can be used. The etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side) were set so that The amount of power used, the temperature of the electrode on the substrate side, etc. are adjusted appropriately.

[0085] The etching solution used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. Alternatively, ITO07N (manufactured by Kanto Chemical Co., Ltd.) may be used.

[0086] In addition, the etching solution after wet etching is washed away together with the etched material. The waste liquid of the etching solution containing the removed material is purified, and the material contained therein is The indium contained in the oxide semiconductor layer may be reused from the waste liquid after the etching. By recovering and reusing materials such as these, we can make effective use of resources and reduce costs. do.

[0087] In order to etch the desired shape, the etching conditions are adjusted according to the material. Adjust the etching conditions (etching solution, etching time, temperature, etc.) as appropriate.

[0088] Next, a metal conductive film is formed over the gate insulating layer 402 and the oxide semiconductor layer 431. The metal conductive film may be formed by sputtering or vacuum deposition. Aluminum (Al), Chromium (Cr), Copper (Cu), Tantalum (Ta), Titanium (Ti ), molybdenum (Mo), tungsten (W), or an element selected from the above elements. In addition, manganese (Mn ), magnesium (Mg), zirconium (Zr), beryllium (Be), yttrium The metal conductive film may be made of one or more materials selected from (Y). The insulating film may have a single layer structure or a laminated structure of two or more layers. For example, aluminum containing silicon A single layer of titanium film, a single layer of copper or copper-based film, a titanium film on an aluminum film, Two-layer structure with copper film laminated on tantalum nitride film or copper nitride film, two-layer structure with copper film laminated on titanium film A three-layer structure in which an aluminum film is laminated on top and a titanium film is laminated on top of the aluminum film. Aluminum (Al) is also known as titanium (Ti), tantalum (Ta), Tungsten (W), Molybdenum (Mo), Chromium (Cr), Neodymium (Nd), Scan A film of a single or multiple combinations of elements selected from Sc, alloy film, or nitride A film containing fluorine may also be used.

[0089] When a heat treatment is performed after forming the metal conductive film, the metal conductive film must have heat resistance to withstand this heat treatment. It is preferable to have it.

[0090] A resist mask is formed on the metal conductive film by a third photolithography process. After etching the source electrode layer 415a and the drain electrode layer 415b, Remove the dysplasia mask (see Figure 4(C)).

[0091] Note that the metal conductive film is etched so as not to remove the oxide semiconductor layer 431. The materials and etching conditions are adjusted accordingly.

[0092] Note that in the third photolithography step, the oxide semiconductor layer 431 is only partly etched. In some cases, the oxide semiconductor layer may be formed having a groove (depression) by etching. The resist mask used in the process may be formed by an ink-jet method. When the film is formed by the jet method, no photomask is used, and therefore the manufacturing cost can be reduced.

[0093] In addition, in order to reduce the number of photomasks and steps used in the photolithography process, Resist formed using a multi-tone mask, an exposure mask that allows light to pass through in multiple intensities The etching process may be performed using a mask. The mask has a shape with multiple film thicknesses, and the shape is further deformed by ashing. Therefore, it can be used in multiple etching processes to process different patterns. Therefore, one multi-tone mask can be used to produce at least two different patterns. Therefore, the number of exposure masks can be reduced. This also eliminates the need for a corresponding photolithography process, making it possible to simplify the process.

[0094] Then, gases such as nitrous oxide (NO), nitrogen (N2), or argon (Ar) are added to The plasma treatment is performed using a fluorine atom. Water adsorbed on the surface is removed. In addition, a mixture of oxygen and argon gas is used to create a plasma. Processing may be carried out.

[0095] After the plasma treatment, a protective film is placed in contact with a part of the oxide semiconductor layer without being exposed to the air. An oxide insulating layer 416 which serves as an insulating film is formed.

[0096] The oxide insulating layer 416 has a thickness of at least 1 nm and is formed by an oxide insulating method such as a sputtering method. The edge layer 416 can be formed by using an appropriate method that does not allow impurities such as water and hydrogen to be mixed into the edge layer 416. When hydrogen is contained in the oxide insulating layer 416, the hydrogen enters the oxide semiconductor layer, and the oxide insulating layer 416 is oxidized. The back channel of the compound semiconductor layer 431 becomes low resistance (N-type), and the parasitic channel Therefore, the oxide insulating layer 416 is formed so as to contain as little hydrogen as possible. It is important that the deposition process does not involve hydrogen.

[0097] Here, a silicon oxide film having a thickness of 200 nm is formed as the oxide insulating layer 416 by sputtering. The substrate temperature during film formation may be set to room temperature or higher and 300° C. or lower. The temperature is set to 100°C in the present state. The deposition of silicon oxide film by sputtering method is carried out using rare gas (typically Argon) atmosphere, oxygen atmosphere, or rare gas (typically argon) and oxygen atmosphere. The target may be a silicon oxide target or A silicon target can be used. For example, a silicon target can be used to A silicon oxide film can be formed by a sputtering method under a nitrogen atmosphere.

[0098] Then, a second heat treatment (preferably 200°C to 400°C (e.g., 250°C to 350°C) is performed. For example, The second heat treatment is performed at 250° C. for 1 hour under atmospheric conditions. A part of the conductor layer (channel formation region) is heated in a state where the part is in contact with the oxide insulating layer 416. As a result, oxygen is supplied to part of the oxide semiconductor layer (a channel formation region).

[0099] Through the above steps, the oxide semiconductor layer is dehydrated or dehydrogenated. After the heat treatment, a part of the oxide semiconductor layer (a channel formation region) is selectively treated with an oxygen excess. As a result, the channel formation region 413 overlapping with the gate electrode layer 411 becomes an I-type. The source region 414a overlaps the source electrode layer 415a, and the drain electrode layer 415b overlaps the drain electrode layer 415b. The overlapping drain region 414b is formed in a self-aligned manner. A separator 410 is formed.

[0100] 85℃, 2×10 6 V / cm, 12-hour gate bias and thermal stress test (BT test In the case of the oxide semiconductor, when impurities are added to the oxide semiconductor, the main component of the oxide semiconductor is the impurities. The bonds between the molecules are broken by a strong electric field (B: bias) and high temperature (T: temperature), and The dangling bonds induce a drift in the threshold voltage (Vth). Impurities in the oxide semiconductor, especially hydrogen and water, are removed as much as possible, and the high-density plasma CVD apparatus described above is used. Using this method, a dense, high-quality insulating film with high dielectric strength is obtained, and the interface characteristics with the oxide semiconductor are improved. By doing so, it is possible to obtain a transistor that is stable even in the BT test.

[0101] Furthermore, heat treatment is performed in air at 100°C to 200°C for 1 hour to 30 hours. Here, the heat treatment is performed at 150°C for 10 hours. The temperature may be maintained at the same temperature, or it may be increased from room temperature to a heating temperature of 100°C to 200°C. The heating temperature may be repeatedly lowered to room temperature several times. The heat treatment may be performed under reduced pressure before the formation of the oxide insulating film. By this heat treatment, the oxide semiconductor layer is converted into an oxide insulating layer. It can capture hydrogen inside.

[0102] Note that in the oxide semiconductor layer overlapping with the drain electrode layer 415b, By forming b, the reliability of the thin film transistor can be improved. In addition, the drain region 414b is formed, so that the drain region 414b is connected to the drain electrode layer 415b. The conductive layer 414b and the channel forming region 413 are configured to have a stepwise change in conductivity. It can be constructed as follows.

[0103] In addition, the source region or the drain region of the oxide semiconductor layer is formed by the film thickness of the oxide semiconductor layer. When the thickness is as thin as 15 nm or less, the oxide semiconductor layer is formed over the entire thickness direction. When the thickness is greater than 30 nm and is less than 50 nm, a part of the oxide semiconductor layer and the source electrode layer Alternatively, the resistance of the region in contact with the drain electrode layer and its vicinity is reduced, and the source region or drain region In addition, a region of the oxide semiconductor layer close to the gate insulating layer can be made to be an I-type. .

[0104] A protective insulating layer may be further formed on the oxide insulating layer 416. For example, the protective insulating layer may be formed by RF sputtering. The RF sputtering method is suitable for mass production, so it is used to form a protective insulating layer. The protective insulating layer is preferably formed by the above-mentioned method. - Impurities such as The silicon nitride film is made of an inorganic insulating film that does not contain any of these elements and blocks their intrusion from the outside. A silicon nitride film, an aluminum nitride film, a silicon nitride oxide film, an aluminum oxynitride film, etc. are used. In this embodiment, the protective insulating layer 403 is formed using a silicon nitride film. (See FIG. 4(D)).

[0105] The contents of this embodiment or a part of the contents may be the same as the contents of other embodiments or the contents of other embodiments. It is possible to freely combine it with any part of the above or with the contents of the examples or any part of the contents.

[0106] (Embodiment 3) In this embodiment mode, a touch panel function is added to the liquid crystal display device shown in Embodiment 1. The structure of the liquid crystal display device having the added structure will be described with reference to FIGS.

[0107] FIG. 5(A) is a schematic diagram of a liquid crystal display device according to the present embodiment. A touch panel unit 502 is superimposed on a liquid crystal display panel 501 which is the liquid crystal display device of the first embodiment. The touch panel unit 503 is attached to the touch panel unit 5. 02 can use resistive film type, surface type capacitive type, projected capacitive type, etc. as appropriate. Cut.

[0108] As shown in FIG. 5A, a liquid crystal display panel 501 and a touch panel unit 502 are separately provided. By fabricating and stacking these devices separately, we have developed a liquid crystal display device with touch panel functionality. Cost reduction can be achieved.

[0109] Regarding the configuration of a liquid crystal display device with a touch panel function different from that shown in FIG. 5(A), The liquid crystal display device 504 shown in FIG. 5B has a plurality of pixels 505. The touch panel has a sensor 506 and a liquid crystal element 507. Since there is no need to fabricate the liquid crystal display device by stacking the liquid crystal units 502, the liquid crystal display device can be made thinner. In addition, a scanning line driver circuit 508, a signal line driver circuit 509, and a light sensor driver circuit 510 By forming the pixel 505 on the same substrate, the liquid crystal display device can be made smaller. The optical sensor 506 is formed using amorphous silicon or the like and an oxide semiconductor. The insulating film may be formed so as to overlap with the transistor used.

[0110] In a liquid crystal display device with a touch panel function, a transistor having an oxide semiconductor layer is provided. By using a transistor, it is possible to improve the image retention characteristics when displaying a still image. During this time, the operation of the drive circuitry is stopped, thereby reducing power consumption. do.

[0111] The contents of this embodiment or a part of the contents may be the same as the contents of other embodiments or the contents of other embodiments. It is possible to freely combine it with any part of the above or with the contents of the examples or any part of the contents.

[0112] (Embodiment 4) In this embodiment, an example of an electronic device equipped with the liquid crystal display device obtained in the first embodiment will be described. The liquid crystal display device according to the first embodiment is used in electronic equipment. It is used as a display unit.

[0113] FIG. 6A is a diagram showing a notebook personal computer. The computer is made up of a main body 2202, a display unit 2203, a keyboard 2204, etc. The liquid crystal display device shown in the first embodiment is applied as a display unit of a personal computer, etc. This not only reduces power consumption, but also reduces eye strain when used for long periods of time. The effect is great. The reasons for this are explained below. Personal computers, etc., are mainly The display changes according to the user's operation. A still image is displayed on the personal computer. In this case, inversion driving is performed to prevent deterioration of the liquid crystal material. If the inversion driving is performed during this period, the user may visually notice flickering in the image. The flickering increases eye strain for the user. In a liquid crystal display device, during a still image display period, image signals are transmitted to each pixel for a long period of time. It is possible to maintain the display quality and reduce flickering that is visible to the user. Therefore, the liquid crystal display device according to the first embodiment is applied to a personal computer or the like. This can be said to be highly effective in reducing eye strain for the user.

[0114] FIG. 6B is a diagram showing a personal digital assistant (PDA), and the main body 2211 has a display unit 22 13, an external interface 2215, and an operation button 2214. In addition, a stylus 2212 is provided as an accessory for operation.

[0115] FIG. 6C is a diagram showing an electronic book 2220 as an example of electronic paper. The board 2220 is composed of two housings, a housing 2221 and a housing 2223. 221 and the housing 2223 are integrated by a shaft portion 2237. With this configuration, the electronic book 2220 can be opened and closed by using the book as an axis. It can be used like a book.

[0116] A display unit 2225 is incorporated in the housing 2221, and a display unit 2227 is incorporated in the housing 2223. The display unit 2225 and the display unit 2227 are configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a text is displayed on the right display (display 2225 in FIG. 6C) and An image can be displayed on the display portion (the display portion 2227 in FIG. 6C).

[0117] FIG. 6C shows an example in which an operation unit and the like are provided in the housing 2221. For example, The housing 2221 includes a power source 2231, operation keys 2233, a speaker 2235, etc. The operation keys 2233 can be used to turn pages. The configuration may include a keyboard, a pointing device, etc. On the side, there are external connection terminals (earphone terminal, USB terminal, or AC adapter and USB A configuration including a terminal that can be connected to various cables such as a cable, a recording medium insertion section, etc. Furthermore, the electronic book 2220 may be configured to have a function as an electronic dictionary. This is also fine.

[0118] The electronic book 2220 may be configured to transmit and receive information wirelessly. The desired book data can be purchased and downloaded from the electronic book server. It is also possible.

[0119] Electronic paper can be applied to any field as long as it displays information. For example, in addition to e-books, posters, in-car advertisements on trains and other vehicles, credit cards, etc. The present invention can be applied to displays on various cards such as credit cards.

[0120] 6D is a diagram showing a mobile phone. The mobile phone includes a housing 2240 and a housing 2241. The housing 2241 includes a display panel 2242 and a speaker. camera 2243, microphone 2244, pointing device 2246, The housing 2240 includes a lens 2247, an external connection terminal 2248, and the like. Equipped with a solar cell 2249 for charging a mobile phone, an external memory slot 2250, etc. In addition, the antenna is built into the housing 2241.

[0121] The display panel 2242 has a touch panel function, and an image is displayed on the display panel 2242 as shown in FIG. The multiple operation keys 2245 are shown by dotted lines. A boost circuit is implemented to boost the voltage output from 2249 to the voltage required for each circuit. In addition to the above configuration, a contactless IC chip, a small recording device, etc. are built in. It is also possible.

[0122] The display direction of the display panel 2242 changes appropriately depending on the usage mode. Since it has a camera lens 2247 on the same surface as the lens 2242, video calls are possible. The speaker 2243 and the microphone 2244 are not limited to voice calls, The housing 2240 and the housing 2241 can be slid together. As shown in Figure 6(D), the device can be folded from the unfolded state to the folded state, making it suitable for carrying. This makes it possible to miniaturize the device.

[0123] The external connection terminal 2248 can be connected to various cables such as AC adapters and USB cables. The external memory slot 2250 can store data and other information. By inserting a recording medium, it is possible to store and transfer a larger amount of data. In addition, it may be equipped with an infrared communication function, a television receiving function, etc.

[0124] FIG. 6E is a diagram showing a digital camera. The digital camera has a main body 2261. , display unit (A) 2267, eyepiece unit 2263, operation switch 2264, display unit (B) 226 5, battery 2266, etc.

[0125] FIG. 6(F) is a diagram showing a television device. In the television device 2270, A display unit 2273 is built into the body 2271. The display unit 2273 displays images. In this embodiment, the housing 2271 is supported by a stand 2275. The configuration is shown.

[0126] The television device 2270 can be operated using an operation switch provided on the housing 2271 or a separate remote. This can be done by using a remote control operation device 2280. The channel and volume can be controlled by the 2279, and the display 2273 shows In addition, the remote control unit 2280 can be used to control the video. A display unit 2277 for displaying information output from the device 2280 may be provided.

[0127] The television device 2270 is preferably configured to include a receiver, a modem, etc. The receiver can receive general television broadcasts. By connecting the device to a wired or wireless communication network, It is used to communicate information either directly (i.e., between a sender and a receiver, or between receivers themselves) or in a two-way manner (i.e., between a sender and a receiver, or between receivers themselves). It is possible to do so.

[0128] The contents of this embodiment or a part of the contents may be the same as the contents of other embodiments or the contents of other embodiments. It is possible to freely combine it with any part of the above or with the contents of the examples or any part of the contents. EXAMPLES

[0129] In this example, the measured values ​​of the off-state current using an evaluation element (also called TEG) are as follows: will explain.

[0130] Figure 7 shows the structure created by connecting 200 transistors with L / W = 3 μm / 50 μm in parallel. The initial characteristics of the transistor with L / W=3μm / 10000μm are shown. FIG. 8(A) shows a partially enlarged top view of the same, and FIG. 8(B) shows a dotted line in FIG. 8(B). The area enclosed in is one stage of transistor with L / W=3μm / 50μm and Lov=1.5μm. Note that Lov here refers to a region where the source or drain overlaps with the oxide semiconductor layer. This represents the length of the region in the channel length direction. The substrate temperature was set to room temperature, and the source-drain voltage (hereinafter referred to as drain voltage or Vd) ) is set to 10 V, and the source-gate voltage (hereafter referred to as gate voltage or Vg) is set to -20 The source-drain current (hereinafter referred to as drain current or I The change characteristic of the Id-Vg characteristic, i.e., the Vg-Id characteristic, was measured. The range shown is from 20V to +5V.

[0131] As shown in FIG. 7, a transistor with a channel width W of 10,000 μm has a Vd of 1 V and At 0V, the off-state current is 1×10 -13 [A] or less, and the measuring instrument (semiconductor parameter The resolution of the data analyzer (Agilent 4156C; Agilent) was 10 In other words, when the channel length is 3 μm, the The off-state current per 1 μm of channel width of the transistor is estimated to be 10 aA / μm or less. If the channel length is 3 μm or more, the off-state current of the transistor is 10 aA / It should also be noted that the thickness is estimated to be less than μm.

[0132] A method for manufacturing the measured transistor will be described.

[0133] First, a silicon nitride layer is formed as a base layer on a glass substrate by a CVD method. A silicon oxynitride layer was formed on the silicon oxynitride layer as a gate electrode layer by a sputtering method. A tungsten layer was then formed. The tungsten layer was then selectively etched to form the gate. An electrode layer was formed.

[0134] Next, a 100 nm thick oxide / nitride layer was formed on the gate electrode layer by CVD as a gate insulating layer. A silicon layer was formed.

[0135] Next, an In-Ga-Zn-O metal oxide target was deposited on the gate insulating layer by sputtering. The thickness of the film was 50 mm. Here, the oxide semiconductor layer was selectively etched to form an island. A shaped oxide semiconductor layer was formed.

[0136] Next, the oxide semiconductor layer was heated in a clean oven under a nitrogen atmosphere at 450°C for 1 hour. A first heat treatment was carried out.

[0137] Next, a titanium layer (thickness 15 mm) was formed on the oxide semiconductor layer as a source electrode layer and a drain electrode layer. A source electrode layer and a drain electrode layer were formed by sputtering. The channel length L of each transistor is 3 μm and the channel width W is 50 μm. m, and 200 pieces are arranged in parallel to make L / W = 3 μm / 10,000 μm. Ta.

[0138] Next, a protective insulating layer was formed by reactive sputtering so as to contact the oxide semiconductor layer. A silicon oxide layer was formed to a thickness of 300 nm. The silicon oxide layer, which is a protective layer, was selectively etched. The gate electrode layer, the source electrode layer, and the drain electrode layer were then etched to form openings. Thereafter, a second heat treatment was carried out in a nitrogen atmosphere at 250° C. for 1 hour.

[0139] Then, before measuring the Vg-Id characteristics, the device was heated at 150° C. for 10 hours.

[0140] Through the above steps, a bottom-gate transistor was manufactured.

[0141] As shown in Figure 7, the off-state current of the transistor is 1×10 -13 [A] is the level This is because the hydrogen concentration in the oxide semiconductor layer can be sufficiently reduced in the manufacturing process. The hydrogen concentration in the oxide semiconductor layer is 1×10 16 atoms / cm 3 The following applies. The hydrogen concentration in the nitride semiconductor layer was measured using secondary ion mass spectrometry (SIMS). The data were obtained using y Ion Mass Spectroscopy.

[0142] Although an example using an In-Ga-Zn-O-based oxide semiconductor has been shown, the present invention is not particularly limited thereto. Other oxide semiconductor materials, such as In-Sn-Zn-O, Sn-Ga-Zn-O, l-Ga-Zn-O series, Sn-Al-Zn-O series, In-Zn-O series, In-Sn-O series , Sn-Zn-O, Al-Zn-O, In-O, Sn-O, Zn-O, etc. In addition, AlO x Mix 2.5 to 10 wt% In-Al-Zn-O system with SiOx mixed in 2.5 to 10 wt% The -O series can also be used.

[0143] In addition, the carrier density of the oxide semiconductor layer measured by a carrier measurement device is 1×10 14 / cm 3 Less than 1 x 10 12 / cm 3 That is, the capacitance of the oxide semiconductor layer is as follows. The rear density can be made as close to zero as possible.

[0144] It is also possible to set the transistor channel length L to between 10 nm and 1000 nm. This enables faster circuit operation and, because the off-current is extremely small, it also reduces power consumption. It is also possible to strengthen the system.

[0145] In addition, when the transistor is off, the oxide semiconductor layer can be regarded as an insulator and This can be done.

[0146] Next, the temperature characteristics of the off-current of the transistor fabricated in this example were evaluated. The temperature characteristics are important when considering the environmental resistance of the final product in which the transistor is used and maintaining its performance. Naturally, the smaller the amount of change, the better, as this increases the degree of freedom in product design.

[0147] The temperature characteristics are measured using a thermostatic chamber at -30, 0, 25, 40, 60, 80, 100, and 12 The substrate on which the transistor was formed was kept at a constant temperature of 60°C. The Vg-Id characteristics were obtained by changing the gate voltage from -20V to +20V.

[0148] Figure 9(A) shows the Vg-Id characteristics measured at each of the above temperatures, overlaid. The area of ​​the off-state current surrounded by the dotted line is shown in enlargement in FIG. The rightmost curve is taken at -30℃, the leftmost curve is taken at 120℃, and the other curves are taken at other temperatures. The curves shown in Fig. 1 are located between the two. The on-current has almost no temperature dependence. As is clear from the enlarged view of Fig. 9(B), the current is constant except for the gate voltage of about -20V. The resolution of the measurement instrument is close to 1×10 at all temperatures. -12 [A] or less, and the temperature Even at a high temperature of 120°C, the off-current is 1×10 -1 2 Considering that the channel width W is 10000 μm, It can be seen that the off-current is very small. That is, when the channel length is 3 μm, The off-state current per 1 μm of transistor channel width is 100 aA / μm or less. If the channel length is 3 μm or more, the off-state current value of the transistor is It is also noted that the estimated value of the dc current is less than 100 aA / μm. The transistor fabricated in this example has an off-state current value of 100% at temperatures of −30° C. or higher and 120° C. or lower. This indicates that the off-state current at 85°C is 1 It should be noted that the estimated value of the dc current is 0.00 aA / μm. A liquid crystal display in which the transistors manufactured in the examples are used as transistors provided in each pixel When the device was subjected to a constant temperature storage test at 85℃, the image signal leakage of the pixel was reduced. This shows that deterioration (change) of the display is suppressed.

[0149] As described above, a transistor using a highly purified oxide semiconductor (purified OS) The off-current of the transistor shows almost no temperature dependence. This is because the oxide semiconductor is highly purified. By this, the conductivity type approaches the intrinsic type and the Fermi level is in the center of the forbidden band. This is because the oxide semiconductor band is located at the same temperature as the oxide semiconductor band. This is also due to the large field gap and the extremely small number of thermally excited carriers. The drain and drain regions are in a degenerate state, which is also the reason why no temperature dependence appears. The operation of a transistor is based on the carriers injected from the degenerate source region into the oxide semiconductor. The above characteristics (O) are mostly due to the fact that the carrier density is not temperature dependent. This can explain the lack of temperature dependence of the gate current.

[0150] The above results indicate that the carrier density is 1×10 14 / cm 3 Less than 1 x 10 12 / cm 3 The transistor has an off-state current of 10 aA / μm or less at room temperature. In addition, the off-state current value at 85°C is 100 aA / μm or less. In addition, the transistor can be used as a transistor included in each pixel of a liquid crystal display device. In this way, the power consumption of the liquid crystal display device is reduced and deterioration of the display (decrease in display quality) is suppressed. Furthermore, it is possible to control the temperature and other external factors. This shows that it is possible to provide a liquid crystal display device in which deterioration (change) of the display caused by the It is something. [Explanation of symbols]

[0151] 10 Control circuit 11 Scanning line driving circuit 12 Signal line driver circuit 13 Pixel section 14 pixels 15 Transistor 16 Liquid crystal element 17 Capacitive element 20 Signal generation circuit 21 Memory circuit 22 Comparison circuit 23 Selection circuit 24 Display control circuit 25 Memory 400 Substrates 402 Gate insulating layer 403 Protective insulation layer 410 Thin Film Transistor 411 Gate electrode layer 413 Channel formation region 414a Source Region 414b Drain region 415a Source electrode layer 415b Drain electrode layer 416 Oxide insulating layer 430 Oxide Semiconductor Film 431 Oxide Semiconductor Layer 501 Liquid crystal display panel 502 Touch panel unit 503 Case 504 Liquid crystal display device 505 pixels 506 Optical Sensor 507 Liquid crystal elements 508 Scanning line driver circuit 509 Signal Line Driver Circuit 510 Driver circuit for optical sensor 2201 Main unit 2202 Case 2203 Display section 2204 Keyboard 2211 Main unit 2212 Stylus 2213 Display section 2214 Operation button 2215 External Interface 2220 E-books 2221 Case 2223 Case 2225 Display section 2227 Display section 2231 Power supply 2233 Operation key 2235 Speaker 2237 Shaft 2240 Case 2241 Case 2242 Display Panel 2243 Speaker 2244 Microphone 2245 Operation Key 2246 Pointing Device 2247 Camera Lenses 2248 External connection terminal 2249 Solar Cell 2250 external memory slot 2261 Main unit 2263 Eyepiece 2264 Operation switch 2265 Display section (B) 2266 Battery 2267 Display section (A) 2270 Television Equipment 2271 Case 2273 Display section 2275 Stand 2277 Display section 2279 Operation Key 2280 Remote Controlled Device

Claims

[Claim 1] a transistor whose switching is controlled by a scanning line driving circuit; a liquid crystal element to which an image signal is input from a signal line driver circuit via the transistor and to which a common potential is supplied to the other terminal, thereby applying a voltage corresponding to the image signal; a capacitance element that holds a voltage applied to the liquid crystal element; and a liquid crystal display device in which a plurality of pixels having the capacitance element and the liquid crystal element are arranged in a matrix, a control circuit for controlling the operation of the scanning line driver circuit and the signal line driver circuit and selecting an input of the image signal to the pixel; the transistor has a channel formation region formed of an oxide semiconductor layer, In the case of the transistor, when the channel length is 10 μm, the off-state current value per 1 μm of the channel width at room temperature is 10 aA (1×10 －１７ A) A liquid crystal display device having the following:

Images