Semiconductor device

Abstract

To provide a semiconductor device having a function as a storage device using the minimum off-state current, capable of reducing a manufacturing cost, saving power consumption, miniaturizing a device, and having excellent reliability in reading data.SOLUTION: In a semiconductor device, an element layer 20 includes: a drive circuit having a plurality of transistors using a silicon substrate as a channel; and transistor layers having a plurality of transistors using a metallic oxide as a channel. The transistor layer 41 arranged on the silicon substrate includes a memory cell 42 having the transistor 43 and a capacitor 44. The transistor 43 is electrically connected to a local bit line LBL. The transistor layer 30 includes: the transistor 31 whose gate is electrically connected to the local bit line; and a correction circuit 35 electrically connected to the transistor 31. The correction circuit is electrically connected to a global bit line GBL, and has a function of allowing a gate to keep a voltage corresponding to a threshold voltage of the transistor 31.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] This specification describes semiconductor devices and the like.

[0002] In this specification, a semiconductor device is a device that utilizes semiconductor characteristics and is a semiconductor element ( Transistors, diodes, photodiodes, etc.) and devices that have such circuits It also refers to any device that can function by utilizing the characteristics of semiconductors. For example, integrated circuits A chip equipped with an integrated circuit or an electronic component that houses a chip in a package is a type of semiconductor device. These are just a few examples. In addition, storage devices, display devices, light-emitting devices, lighting devices, electronic devices, etc. The body may be a semiconductor device or may have a semiconductor device. [Background technology]

[0003] Metal oxides are attracting attention as semiconductors that can be used in transistors. In-Ga-Zn oxide, also known as "Ixo", is a representative multi-component metal oxide. In research on IGZO, the CAAC (c- axis aligned crystalline structure, and nc (nanocrystal A ystalline structure was found (for example, Non-Patent Document 1).

[0004] A transistor having a metal oxide semiconductor in the channel formation region (hereinafter referred to as an oxide semiconductor transistor) These transistors are called “transistors” or “OS transistors.” It has been reported that OS transistors are used Various semiconductor devices have been fabricated (for example, Non-Patent Documents 3 and 4).

[0005] The manufacturing process for OS transistors is the same as the CMOS process used for conventional Si transistors. The OS transistors can be stacked on top of the silicon transistors. For example, in Patent Document 1, a layer of a memory cell array having an OS transistor is formed by using a Si transistor. It discloses a structure in which multiple layers are stacked on a substrate provided with resistors. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] US Patent Application Publication No. 2012 / 0063208 [Non-patent literature]

[0007] [Non-Patent Document 1] S. Yamazaki et al., “Properties of crystalline In-Ga-Zn-oxide semiconductor and its transistor characteristics,” Jpn.J.Appl.Phys.,vol.53,04ED18(2014). [Non-Patent Document 2] K. Kato et al., “Evaluation of Off-State Current Characteristics of Transistor Using Oxide Semiconductor Material, Indium-Gallium-Zinc Oxide,” Jpn.J.Appl.Phys., vol. 51, 021201 (2012). [Non-Patent Document 3] S. Amano et al., “Low Power LC Display Using In-Ga-Zn-Oxide TFTs Based on Variable Frame Frequency,” SID Symp. Dig. Papers, vol. 41, pp. 626-629 (2010). [Non-Patent Document 4] T. Ishizu et al., “Embedded Oxide Semiconductor Memories: A Key Enabler for Low-Power ULSI,” ECS Tran., vol.79, pp.149-156 (2017). Summary of the Invention [Problem to be solved by the invention]

[0008] An object of one embodiment of the present invention is to provide a semiconductor device or the like having a novel structure. One embodiment of the present invention is a semiconductor device that functions as a memory device utilizing an extremely small off-state current. It is therefore possible to provide a semiconductor device or the like having a novel configuration, which can reduce manufacturing costs. Another object of the present invention is to provide a memory device that functions as a memory device utilizing extremely small off-state current. To provide a semiconductor device having a novel configuration and excellent low power consumption in a semiconductor device. Another object of one embodiment of the present invention is to provide a memory device that functions as a memory device utilizing an extremely small off-state current. A semiconductor device having a novel configuration that can reduce the size of the device. Another object of the present invention is to provide a semiconductor device using a very small off-state current. A new semiconductor device that functions as a memory device and has excellent reliability of data read out It is an object of the present invention to provide a semiconductor device or the like having a novel structure.

[0009] The description of a plurality of problems does not preclude the existence of each problem. It is not necessary to solve all of the problems shown. Also, problems other than those listed may be solved by the present invention. This will become apparent from the above, and such a problem can also be one aspect of the present invention. [Means for solving the problem]

[0010] One embodiment of the present invention is a driver circuit including a plurality of transistors each having a channel formed using a silicon substrate. a first transistor layer having a plurality of transistors each having a metal oxide channel; and a second transistor layer, the first transistor layer and the second transistor layer being A first transistor layer is provided on the silicon substrate, and includes a first transistor and a first capacitor. a first memory cell having a first transistor electrically connected to a first local bit line; the second transistor layer has a gate electrically connected to the first local bit line; a second transistor; and a first correction circuit electrically connected to the second transistor; The first correction circuit is electrically connected to the first global bit line. A function to hold a voltage corresponding to the threshold voltage of the first transistor at the gate of the second transistor. The semiconductor device has a

[0011] One embodiment of the present invention is a driver circuit including a plurality of transistors each having a channel formed using a silicon substrate. and an element layer in which a plurality of transistor layers are stacked, the element layer being made of a metal oxide. A first transistor layer and a second transistor layer each having a plurality of transistors each using a nitride as a channel. a first transistor layer and a second transistor layer on a silicon substrate; the first transistor layer includes a first transistor and a first capacitor; a first transistor electrically connected to a first local bit line; The second transistor layer includes a second transistor having a gate electrically connected to the first local bit line. a first correction circuit electrically connected to the second transistor, The path is electrically connected to the first global bit line, and the first correction circuit includes a second transistor. A semiconductor device having a function of holding a voltage corresponding to the threshold voltage of the second transistor at the gate of the second transistor. It is a semiconductor device.

[0012] In one embodiment of the present invention, the first local bit line is perpendicular to the surface of the silicon substrate. Preferably, the semiconductor device is disposed in a direction or substantially perpendicular to the substrate.

[0013] In one aspect of the present invention, a first global bit line connects the first correction circuit and the driving circuit. A semiconductor device having an electrical connection function is preferred.

[0014] In one embodiment of the present invention, the first global bit line is perpendicular to the surface of the silicon substrate. Semiconductor devices that are oriented perpendicular or generally vertical are preferred.

[0015] In one embodiment of the present invention, the metal oxide is a semiconductor device containing In, Ga, and Zn. Positioning is preferred.

[0016] In one aspect of the present invention, the first correction circuit includes a third transistor to a fifth transistor. The third transistor is connected to the gate of the second transistor and the source of the second transistor. The fourth transistor has a function of controlling a conductive state between the first transistor and one of the drain and the second transistor. The other of the source or drain of the second transistor and the second transistor The fifth transistor has a function of controlling electrical continuity between the first transistor and a wiring to which a potential is applied. Between one of the source or drain of the second transistor and the first global bit line A semiconductor device having a function of controlling the conduction state is preferable.

[0017] In one embodiment of the present invention, the first transistor is non-conductive during a period in which the correction operation is performed. A semiconductor device that is brought into a state where the semiconductor device is in a non-contact state is preferred.

[0018] In one aspect of the present invention, a second memory cell, a second local bit line, and a second correction circuit a second global bit line, a fifth transistor, a sixth transistor, and a seventh transistor; and a driver circuit for driving a first bit line and a second bit line which function as a bit line pair. a sense amplifier electrically connected to the bit line; and a second memory cell, the first local bit line is electrically connected to the second correction circuit; The second compensation circuit is electrically connected to the second global bit line, and the fifth transistor is A sixth transistor has a function of controlling a conductive state between the bit line and the first global bit line. The transistor controls a conductive state between the second bit line and the second global bit line. The seventh transistor has a function of connecting the first global bit line and the second global bit line. A semiconductor device having a function of controlling the conduction state between and is preferable.

[0019] In one embodiment of the present invention, the fifth to seventh transistors are made of metal oxide. A semiconductor device in which the transistor is used in a semiconductor device having a large current flowing through the semiconductor device is preferred.

[0020] Other aspects of the present invention will be described in the following embodiments and and the drawings. Effect of the Invention

[0021] One embodiment of the present invention can provide a semiconductor device or the like having a novel structure. One embodiment of the present invention is a semiconductor device that functions as a memory device utilizing an extremely small off-state current, It is possible to provide a semiconductor device or the like having a novel configuration, which can reduce costs. Another embodiment of the present invention is a semiconductor device that functions as a memory device utilizing an extremely small off-state current. It is possible to provide a semiconductor device or the like having a novel configuration that is excellent in low power consumption in the One embodiment of the present invention is a semiconductor device that functions as a memory device utilizing extremely low off-state current. It is possible to provide a semiconductor device having a novel configuration that can reduce the size of the device. Another embodiment of the present invention is a semiconductor device that functions as a memory device utilizing extremely small off-state current. The present invention provides a semiconductor device having a novel configuration and excellent reliability of data read out therefrom. It is possible.

[0022] The description of a plurality of effects does not preclude the existence of other effects. However, it is not necessary to have all of the effects exemplified above. Other problems, advantages, and novel features than those mentioned above can be understood from the description and drawings of this specification. It will become clear as time goes on. [Brief description of the drawings]

[0023] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of a semiconductor device. [Diagram 2] 2A and 2B are a block diagram and a circuit diagram showing a configuration example of a semiconductor device. [Diagram 3] 3A, 3B, and 3C are diagrams for explaining the operation of the semiconductor device. [Figure 4] 4A and 4B are a flow diagram and a circuit diagram showing a configuration example of a semiconductor device. [Diagram 5] 5A and 5B are a flow diagram and a circuit diagram showing a configuration example of a semiconductor device. [Figure 6] 6A and 6B are circuit diagrams showing configuration examples of a semiconductor device. [Figure 7] FIG. 7 is a flow diagram showing a configuration example of a semiconductor device. [Figure 8] 8A and 8B are a flow diagram and a circuit diagram showing a configuration example of a semiconductor device. [Figure 9] 9A and 9B are a flow diagram and a circuit diagram showing a configuration example of a semiconductor device. [Figure 10] 10A and 10B are schematic diagrams showing configuration examples of a semiconductor device. [Figure 11] FIG. 11 is a schematic diagram showing a configuration example of a semiconductor device. [Figure 12] 12A and 12B are circuit diagrams showing configuration examples of a semiconductor device. [Figure 13] 13A and 13B are a block diagram and a circuit diagram showing a configuration example of a semiconductor device. [Figure 14] 14A and 14B are block diagrams showing configuration examples of a semiconductor device. [Figure 15] 15A, 15B, 15C, and 15D are circuit diagrams for explaining configuration examples of a semiconductor device. [Figure 16] 16A and 16B are circuit diagrams for explaining a configuration example of a semiconductor device. [Figure 17] FIG. 17 is a circuit diagram for explaining a configuration example of a semiconductor device. [Figure 18] FIG. 18 is a timing chart for explaining a configuration example of a semiconductor device. [Figure 19] 19A, 19B, and 19C are circuit diagrams and timing charts for explaining a configuration example of a semiconductor device. [Figure 20] FIG. 20 is a timing chart for explaining a configuration example of a semiconductor device. [Figure 21] FIG. 21 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 22]22A and 22B are schematic cross-sectional views showing configuration examples of a semiconductor device. [Figure 23] 23A, 23B, and 23C are schematic cross-sectional views showing configuration examples of a semiconductor device. [Figure 24] FIG. 24 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Diagram 25] FIG. 25 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 26] 26A, 26B, and 26C are a top view and a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 27] 27A, 27B, 27C, and 27D are top views for explaining configuration examples of a semiconductor device. [Figure 28] 28A, 28B, and 28C are diagrams for explaining the classification of IGZO crystal structures, diagrams for explaining the XRD spectrum of silica glass, and diagrams for explaining the XRD spectrum of crystalline IGZO. [Figure 29] FIG. 29 is a block diagram illustrating a configuration example of a semiconductor device. [Diagram 30] FIG. 30 is a conceptual diagram showing a configuration example of a semiconductor device. [Diagram 31] 31A and 31B are schematic diagrams illustrating an example of an electronic component. [Diagram 32] FIG. 32 is a diagram illustrating an example of an electronic device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] Hereinafter, an embodiment of the present invention will be described. However, one embodiment of the present invention is not limited to the following description. The present invention is not limited to the above, and various modifications and variations in form and detail are possible without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that the present invention can be modified to the following: However, it should not be construed as being limited to the description of the embodiments shown below.

[0025] In this specification, the ordinal numbers "first," "second," and "third" refer to the components of the The above is added to avoid confusion, and does not limit the number of components. In addition, the order of the components is not limited. The element referred to as "first" in one embodiment may be used in another embodiment or in the claims. In addition, for example, the second component may be the component referred to in the present specification. A component referred to as "first" in one embodiment may be used in another embodiment, or It may be omitted in the claims.

[0026] In the drawings, elements that are the same or have similar functions, elements of the same material, or In some cases, elements formed at the same time may be given the same reference numerals, and repeated explanations thereof will be omitted. This may be the case.

[0027] In this specification, for example, the power supply potential VDD is abbreviated to potential VDD, VDD, etc. This may be due to the presence of other components (e.g., signals, voltages, circuits, elements, electrodes, wiring, etc.). The same applies to (etc.).

[0028] In addition, when the same reference numerals are used for several elements, particularly when it is necessary to distinguish between them, For the code, identification codes such as “_1”, “_2”, "[n]”, "[m,n]” etc. are added to the code. For example, the second wiring GL is written as wiring GL[2].

[0029] (Embodiment 1) Structural examples of a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS. do.

[0030] A semiconductor device is a device that utilizes the characteristics of semiconductors. In this embodiment, the present invention is a circuit including a photodiode, a photodiode, etc., and a device having the circuit. The semiconductor device to be described functions as a memory device using a transistor with extremely low off-state current. It is possible.

[0031] FIG. 1 is a block diagram for explaining a schematic cross-sectional structure of a semiconductor device 10. As shown in FIG.

[0032] The semiconductor device 10 includes a plurality of element layers 20_1 to 20_M (M is a self-representative layer) on a silicon substrate 50. The element layers 20_1 to 20_M each include a transistor layer 30 and a transistor The transistor layer 40 includes a plurality of transistor layers 41_1 to It consists of 41_k (k is a natural number greater than or equal to 2).

[0033] In the schematic diagram shown in FIG. 1, the z-axis direction is defined in order to explain the arrangement of each component. The direction refers to a direction perpendicular or approximately perpendicular to the surface of the silicon substrate 50. "Straight" refers to a state in which the angle is between 85 degrees and 95 degrees. Therefore, the z-axis direction is sometimes called the vertical direction. It corresponds to a plane formed by the x-axis and y-axis, which are defined in a direction perpendicular or approximately perpendicular to the y-axis. For ease of understanding, the x-axis direction is sometimes called the depth direction and the y-axis direction is sometimes called the horizontal direction. .

[0034] The transistor layer 40 is composed of a plurality of transistor layers 41_1 to 41_k. The transistor layer has a plurality of memory cells (not shown). The capacitor is sometimes called a capacitance element. The element layer is a layer in which elements such as capacitors and transistors are provided. The layer includes a material such as a dielectric, an insulator, etc.

[0035] The memory cells of each of the transistor layers 41_1 to 41_k are formed in a channel forming region. In the present invention, a transistor having an oxide semiconductor (hereinafter referred to as an OS transistor) is used as a memory. DOSRAM (Dynamic Oxide Semiconductor Rand One transistor and one Since it can be configured with one capacity, it is possible to realize high memory density. By using a transistor, the data retention period can be increased.

[0036] In one embodiment of the present invention, a memory cell including an OS transistor is used. This reduces the leakage current (hereinafter referred to as off-current) that flows between the source and drain when the device is off. By utilizing this, a charge corresponding to the desired voltage is transferred to the capacitor on the other side of the source or drain. In other words, data once written in a memory cell can be retained. It can be retained for a long time, which reduces the frequency of data refresh and reduces power consumption. It is possible to achieve this.

[0037] In addition, in memory cells using OS transistors, the charge can be charged or discharged. This allows data to be rewritten and read, so data can be written and read an unlimited number of times. The memory cell using OS transistors is a magnetic memory Unlike silicon or resistive memory, this does not involve structural changes at the atomic level, so writing In addition, memory cells using OS transistors have excellent resistance to flash memory. Thus, no instability due to an increase in electron trap centers is observed even with repeated rewrite operations.

[0038] In addition, memory cells using OS transistors have silicon in the channel formation region. It can be freely placed on a silicon substrate that has a transistor (hereinafter referred to as Si transistor). Since the OS transistor has a large capacitance, it can be easily integrated. Since it can be manufactured using the same manufacturing equipment as the FT-IR filter, it can be manufactured at low cost. .

[0039] In addition to the gate electrode, source electrode, and drain electrode, the OS transistor also has a buffer If a backgate electrode is included, it can be a four-terminal semiconductor element. The input and output of signals flowing between the source and drain are independent depending on the voltage applied to the gate electrode. Therefore, it is possible to design circuits with the same concept as LSI. In addition, OS transistors can perform the same thermal design as Si transistors in high-temperature environments. Specifically, it can withstand high temperatures of 125°C to 150°C. Since the ratio of on-current to off-current is large even at high temperatures, good switching operation can be achieved. This can be done.

[0040] The transistor layer 30 selects one of the memory cells included in the transistor layer 40. The function of writing and reading data to and from the memory cells that have been Yes.

[0041] The transistor layer 30 includes a read transistor for reading data and a data A correction function that writes data, reads data, and corrects the data that is read A gate of the read transistor is connected to one of the memory cells. By using this configuration, the read transistor When reading data, the small potential difference between the local bit lines is amplified to The correction circuit can output the signal to the gate of the read transistor. A potential corresponding to a threshold voltage of the transistor is held. This allows the read transistor to reduce the variation in data read from the memory cell. It can be reduced.

[0042] The local bit line is a bit line that is directly connected to the memory cell. The local bit line GBL is connected to the correction circuit by selecting one of the local bit lines. The global bit line GBL or local bit line is electrically connected to the memory cell. The data signal applied to the local bit line is the signal to be written to the memory cell, or the memory This corresponds to the signal read from the cell. The data signal corresponds to data 1 or data 0. The data signal will be described as a binary signal having a high or low potential. The code may be multi-valued, having three or more values.

[0043] As shown in FIG. 1, the transistor layer 40 is The transistor layer 40 included in each of the element layers 20_1 to 20_M is The transistor layer 30 includes a correction circuit. The path utilizes the difference in the amount of current flowing through the read transistor in the transistor layer 30. By this, the data signal written in the memory cell is set to the potential of the global bit line GBL. The silicon substrate 50 has a function of converting the change in the voltage into a voltage change and outputting it to a driving circuit. The resistor layer 30 converts the data signal output by the drive circuit of the silicon substrate 50 into a correction circuit. It has the function of providing a selected local bit line.

[0044] The silicon substrate 50 is used for writing data to a memory cell selected by the transistor layer 30. In order to read or write data through the global bit line GBL and the local bit line GBL, The driving circuit has a plurality of Si transistors using the silicon substrate 50 as a channel. The transistor is

[0045] In one embodiment of the present invention, a transistor provided in each element layer has an extremely low off-state current. OS transistors are used. This reduces the frequency of refreshing data stored in memory cells. The OST can be reduced, and a semiconductor device with low power consumption can be obtained. The transistors can be stacked and fabricated using the same manufacturing process in a vertically repeatable fashion. In addition, the present invention can be applied to a memory device. The transistors that make up the recells are arranged vertically instead of horizontally to increase memory density. In addition, the OS transistor can be used in high temperature environments. Compared to silicon transistors, the electrical characteristics of these transistors fluctuate less even under extreme conditions, making them more reliable. In addition, the semiconductor device can function as a memory device. By using a configuration in which the threshold voltage of the transistor for reading the data is corrected, The semiconductor device can function as a storage device with excellent data reliability.

[0046] 2A, a device layer corresponding to any one of the device layers 20_1 to 20_M in FIG. A block diagram of 20 is shown.

[0047] As shown in FIG. 1, in the element layer 20 according to one embodiment of the present invention, the transistor A plurality of transistor layers 40 each having a memory cell are provided on the memory cell layer 30. By adopting this configuration, the distance between the transistor layer 30 and the transistor layer 40 can be shortened. The shorter local bit lines can reduce parasitic capacitance. The transistor layers 41_1 to 41_k are repeatedly fabricated in the vertical direction using the same manufacturing process. This makes it possible to reduce manufacturing costs.

[0048] FIG. 2B is a diagram showing, by circuit symbols, each component in the element layer 20 shown in FIG. 2A.

[0049] The transistor layer 30 includes a read transistor 31 and a correction circuit 35. The circuit 35 includes a transistor 32, a transistor 33, and a transistor . Each of the transistor layers 41_1 to 41_k includes a plurality of memory cells 42. The rechargeable cell 42 includes a transistor 43 and a capacitor 44. The transistor 43 is In response to the control of the word line WL connected to the gate, the local bit line LBL and the capacitor It functions as a switch to switch between a conductive state (ON) and a non-conductive state (OFF) between 44 The local bit line LBL is connected to the gate of the transistor 31. The word line W L is a signal that is transmitted by a word signal (sometimes called a signal WL) given to a word line WL. The transistor 43 is turned on or off. The capacitor 44 is a wiring that provides a fixed potential. CSL is connected.

[0050] The transistors in the correction circuit 35 are connected as shown in FIG. In this case, either the source or the drain of the transistor 33 is connected to the gate of the transistor 31. The other of the source and drain of the transistor 33 is connected to the source of the transistor 34. connected to either the source or drain of transistor 31. The source or drain of the transistor 33 is connected to the source of the transistor 31. The other of the source and drain of the transistor 32 is connected to The other of the source and drain of the transistor 34 is connected to the global The transistors 32, 33, and 34 are connected to the gates of the The conduction state between the source and drain is controlled by the input signals RE, WE, and MUX. The signals RE, WE, and MUX function as switches to switch between a conducting state and a non-conducting state. are used to turn on or off the transistor that acts as a switch. It is a signal, and as an example, the signal can be turned on when it is at H level and turned off when it is at L level.

[0051] The transistor 43 is the OS transistor described above. The electrodes are made of conductors sandwiched between insulators. In addition to metals, semiconductor layers that have been given electrical conductivity can be used. The position of the transistor 43 is described in detail below. In addition to the above, a part of the semiconductor layer or the electrodes constituting the transistor 43 may be formed as a capacitor. The electrode 44 can be used as one of the electrodes.

[0052] The transistor 31 is turned on or off in response to the potential of the local bit line LBL. The transistor 31 has a function of passing a current between its source and drain. When the threshold voltage of the transistor 31 is exceeded, a current flows between the source and drain. .

[0053] The compensation circuit 35 compensates for the current flowing between the source and drain of the transistor 31 via the line S L and the global bit line GBL, or It has a function of transmitting the potential of the bit line GBL to the local bit line LBL. The potential of the gate of the transistor 31 is provided between the source and drain of the transistor 31. It has the function of discharging to line SL.

[0054] The transistors 31 to 34 in the transistor layer 30 are also The element layer 20 using the OS transistor is preferably composed of an OS transistor. The transistor layers 30 and 40 constituting the above-mentioned are formed on a silicon substrate having a Si transistor. Since the semiconductor device can be stacked on top of one another, integration can be easily achieved.

[0055] FIG. 3A is a diagram for explaining the operation of the semiconductor device 10. As shown in FIG. The operation of the semiconductor device 10 is carried out during a period 11 during which an operation for writing data into a memory cell is carried out. 0, a period in which a correction operation for reading data is performed 120, a period in which a data read operation is performed It can be broadly divided into 130 sections.

[0056] The operation of the semiconductor device 10 is not limited to the order shown in FIG. By turning off each transistor in the correction circuit 35, the gate of the transistor 31 The potential held in the transistor 31, for example, the potential corresponding to the threshold voltage of the transistor 31, is maintained. Therefore, for example, as shown in FIG. 3B, a period 120 and a period 130 A period 140 during which the operation is stopped while the threshold voltage is maintained may be provided between the first and second gate electrodes. Alternatively, as shown in FIG. 3C, for example, the period 120 can be divided into periods 120_1 and 120_2. By repeating the operation multiple times, such as 120_2 and period 140, the transition The potential held at the gate of transistor 31 corresponds to, for example, the threshold voltage of transistor 31. A potential refresh operation can be performed.

[0057] 4A and 4B are flowcharts for explaining a period 110, that is, a data write operation. and a circuit diagram.

[0058] In a data write operation, first, as shown in FIG. 4A, the signals WE and MUX are set The local bit line WL is set to H level, and the signal RE is set to L level (operation 111). The local bit line LBL is electrically connected to the global bit line GBL. The line LBL is charged by the global bit line GBL. is set to a voltage according to the data to be written in the memory cell 42.

[0059] Next, as shown in FIG. 4A, the signals WL, WE and MUX are set to the H level, The signal RE is set to the L level (operation 112). The capacitor 44 is electrically connected to the local bit line LBL. The local bit line LBL is supplied with a voltage according to the data to be written in the memory cell 42. Then, data is written to the memory cell 42 (operation 113). A schematic operation is shown in FIG. 4B. In FIG. 4B, the dashed arrow indicates the write operation of the memory cell 42. Voltage V according to the input data DATA In addition, in Fig. 4B, the trans- formation marked with a cross The crossed transistor symbol represents the off state, and the uncrossed transistor symbol represents the on state. represent.

[0060] Next, as shown in FIG. 4A, the signals WE and MUX are set to the H level, the signals WL and The signal RE is set to the L level (operation 114). The voltage V DATA Then, as shown in FIG. 4A, the signals WE, MUX, and The signal WL and the signal RE are set to the L level (operation 115), and the data write operation is completed. When moving to the correction operation, it is possible to omit the operation 115.

[0061] 5A, 5B, 6A, 6B, and 7 illustrate period 120, i.e., the correction operation. 1 is a flow chart and circuit diagram for explaining the present invention.

[0062] In the correction operation, first, as shown in FIG. 5A, the signals WE and MUX are set to the H level, The signals WL and RE are set to the L level (operation 121). The local bit line LBL is The local bit line LBL is electrically connected to the global bit line GBL. The global bit line GBL is charged by the local The precharge voltage of the global bit line LBL is Vpre1. The GBL and the local bit line LBL are precharged (operation 122: GBL, LB A schematic diagram of operation 122 is shown in FIG. In the middle, the dashed arrow indicates the pre-write to the global bit line GBL and the local bit line LBL. It represents the charge voltage Vpre1. Also, in FIG. 5B, the transistor symbol marked with a cross represents the off state, and an uncrossed transistor symbol represents the on state.

[0063] Next, as shown in FIG. 5A, the signals WE and RE are set to the H level, and the signals WL and The signal MUX is set to the L level (operation 123). The local bit line LBL is connected to the transistor 33, the transistor 31, and the transistor 32 are electrically connected to the wiring SL. The local bit line LBL is connected to the transistors 33, 31, and Through the transistor 32, the charge according to the precharge voltage Vpre1 ​​is discharged. The potential of the local bit line LBL becomes equal to the threshold voltage (Vth) of the transistor 31. When this occurs, the discharge stops and the threshold voltage Vth is held at the gate of transistor 31. (Operation 124: threshold correction). The potential of the wiring SL is discharged by the local bit line LBL. A schematic operation of operation 124 is shown in FIG. In FIG. 6A, the dashed arrow indicates the discharge from the local bit line LBL to the wiring SL. In Figure 6A, the transistor symbol with a cross indicates that the transistor is off. A transistor symbol without a cross represents an on state, and a transistor symbol without a cross represents an on state.

[0064] Then, as shown in FIG. 5A, the signals WE, RE, WL and MUX are set to L. The local bit line LBL sets the potential of the line SL to V SL ,to If the threshold voltage of the transistor 31 is Vth, then the gate-source voltage Vgs is Vth. (Vgs=Vth), that is, (Vth+V SL ) is held. A schematic operation of 125 is illustrated in FIG. 6B. In FIG. 6B, the crossed transistors A cross represents the off state, and a non-crossed transistor symbol represents the on state. vinegar.

[0065] Note that the operational flow shown in FIG. 5A can be configured differently. For example, in FIG. The flow shown in FIG. 7 differs from that shown in FIG. 5A in that the wiring SL Specifically, the potential of the operation 121 corresponding to the operation 121 is switched. In operation 125A, which corresponds to operation 125, the line SL is connected to a potential V SL0 Keep it as In operation 123A corresponding to operation 123, the line SL is set to a potential V SL0 Greater than Potential V SL By adopting this configuration, when the potential of the local bit line LBL is small, Even if the voltage Vcc is 1, a current can flow through the wiring SL.

[0066] 8A and 8B are flow charts for explaining the period 130, that is, the data read operation. and a circuit diagram.

[0067] In a data read operation, first, as shown in FIG. 8A, the signal WL is set to the H level, and the signal WE Then, the signals MUX and RE are set to the L level (operation 131). The local bit line LBL is connected to the voltage V SL +Vth and capacitor 4 Voltage of 4 V DATA and are added together through charge sharing (operation 132). The potential (V DATA +Vth+V SL )

[0068] Next, as shown in FIG. 8A, the signals WL, RE and MUX are set to the H level, The signal WE is set to the L level (operation 133). The transistor 31 is DAT A +Vth+V SL The current (Idata) flows according to the global bit The precharge line GBL is applied with a precharge voltage Vpre1 ​​and is in an electrically floating state (floating The potential of the global bit line GBL is set to the value Id The voltage varies from Vpre1 ​​depending on the ata (operation 134). The signal is read out by the driving circuit as Vread (operation 135). This is illustrated in FIG. 8B. In FIG. 8B, the crossed transistor symbol represents the off state. , a transistor symbol without a cross represents the on state.

[0069] 9A and 9B are flow charts and circuits for explaining period 140, i.e., the pause operation. FIG.

[0070] In the sleep mode, first, as shown in FIG. 9A, the signals WL, WE, MUX, and The signal RE is set to the L level (operation 141). Voltage (V SL +Vth) and the voltage V of the capacitor 44 DATA and is maintained (operation 142). A schematic diagram of operation 142 is shown in FIG. 9B. The crossed transistor symbol represents the off state, while the uncrossed transistor symbol represents the Indicates the on state.

[0071] In FIG. 10A, the element layers 20_1 to 20_M shown in FIG. FIG. 10A illustrates a perspective view of the semiconductor device 10 arranged in a vertical direction (z-axis direction). It represents the depth direction (x-axis direction) and the horizontal direction (y-axis direction).

[0072] In FIG. 10A, memory cells 42 included in transistor layers 41_1 and 41_2 are illustrated by dotted lines. It shows.

[0073] As shown in FIG. 10A, a semiconductor device 10 according to an embodiment of the present invention has an OS transistor. Therefore, the same fabrication process can be repeated in the vertical direction. The present invention can be produced by using a conventional manufacturing process, and therefore the production cost can be reduced. In one embodiment of the semiconductor device 10, a transistor layer 40 having a memory cell 42 is formed in a planar direction. Instead, they can be stacked vertically to increase memory density, making it possible to miniaturize devices. It is possible to plan this.

[0074] In addition, in FIG. 10B, each configuration of the element layers 20_1 to 20_M shown in FIG. 10A is In FIG. 10B, the circuitry is omitted and is provided on the silicon substrate 50. A control logic circuit 6, which is composed of Si transistors on a silicon substrate 50 1, row driver circuit 62, column driver circuit 63 and output circuit 64. The logic circuit 61, row driving circuit 62, column driving circuit 63 and output circuit 64 are This will be described in detail in the fourth embodiment.

[0075] 11, the transistor layers 30, 41_1 of the semiconductor device 10 shown in FIG. 11 corresponds to a diagram in which the transistor layers 41_1, 41_2 are extracted and illustrated. The memory cell in 41_2 has a transistor 43 and a capacitor 44, and a local The bit lines LBL and the word lines WL are shown. The LBL is shown by a dashed line to improve visibility. Also shown is a global bit line GBL that penetrates each transistor layer. As described above, the global bit line GBL is made thicker than the other lines to improve visibility. This is illustrated in the figure.

[0076] As shown in FIG. 11, in a semiconductor device 10, a transistor 4 3, the local bit line LBL connected to the transistor layer 30, the compensation circuit and the silicon The global bit line GBL connected to the substrate 50 is By using this configuration, the local bit lines connected to each memory cell are arranged in the vertical direction. Therefore, the parasitic capacitance of the local bit line LBL can be significantly reduced. Therefore, even if the data signal stored in the memory cell is multi-valued, the potential can be read out. In addition, according to one embodiment of the present invention, data stored in a memory cell can be read as a current. Therefore, even if the data is multi-valued, it can be easily read out.

[0077] 12A and 12B show the transistor 31 and the compensation circuit 35 shown in FIG. 2B. A circuit diagram for explaining an example is shown in FIG. 2B. In FIG. 2B, each transistor has a back gate. Although the transistors shown in the figures are of a top-gate structure or bottom-gate structure without electrodes, The structure of the transistor is not limited to this. For example, as shown in FIG. The transistor layer 30A may have a back gate electrode connected to the back electrode line BGL. By using the configuration of FIG. 12A, the electrical characteristics such as the threshold voltage of each transistor can be externally controlled. It can be made easier to control.

[0078] Alternatively, as shown in FIG. 12B, a back gate electrode is connected to the gate electrode. By using the configuration of FIG. 12B, each transistor may be The amount of current that flows can be increased.

[0079] Although the semiconductor device 10 of FIG. 1 has been described as having one type of memory cell, it may be possible to use two or more types of memory cells. FIG. 13A shows a semiconductor device corresponding to a modified example of the semiconductor device 10. 1 shows a block diagram of a semiconductor device 10A.

[0080] The semiconductor device 10A has different circuit structures between the transistor layer 20 and the transistor layer 30. The semiconductor device 20 differs from the semiconductor device 10 in that a transistor layer 90 having memory cells of the same structure is provided.

[0081] FIG. 13B is a circuit diagram showing a configuration example of a memory cell included in the transistor layer 90. The memory cell 91 includes a transistor 92, a transistor 93, and a capacitor 94. do.

[0082] One of the source and drain of the transistor 92 is connected to the gate of the transistor 93. The gate of the transistor 93 is connected to one electrode of a capacitor 94. The other of the source or drain of the transistor 92 and the source One of the source and drain of the transistor 93 is connected to the wiring BL2. The other electrode of the capacitor 94 is connected to the wiring SL2. The source or drain of the transistor 92 is electrically connected to the line CAL. One of the electrodes is connected to the gate of the transistor 93 and one of the electrodes of the capacitor 94. Let the node be node N.

[0083] The wiring CAL is used as a wiring for applying a predetermined potential to the other electrode of the capacitor 94. The potential of the wiring CAL when reading data from the memory cell 91 is set to the potential of the memory cell 92. When writing data to the cell 91 and while the data is being held in the memory cell 91, This makes the potential of the line CAL different from that of the line CAL. The apparent threshold voltage of the transistor 93 is set to 0 when writing data to the memory cell 91 and and the apparent threshold voltage of transistor 93 while data is being stored in memory cell 91. The pressure can be different.

[0084] When the memory cell 91 has the configuration shown in FIG. 13B, data is written to the memory cell 91. When data is written to the memory cell 91, or while the data is being held in the memory cell 91, Regardless of the data stored in the memory cell, no current flows between the wiring SL2 and the wiring BL2. When reading data from the memory cell 91, the data stored in the memory cell 91 is inserted between the wiring SL2 and the wiring BL2. A current corresponding to the stored data flows.

[0085] The transistors 92 and 93 are preferably OS transistors. The OS transistor has an extremely low off-state current. The charge corresponding to the memory cell 9 can be held at the node N for a long time. In 1, data written once can be retained for a long time. The frequency of refreshing can be reduced, and the power consumption of the semiconductor device of one embodiment of the present invention can be reduced. Cut.

[0086] The memory cell 91 shown in FIG. 13B is a NOSR memory cell using OS transistors. AM (Nonvolatile Oxide Semiconductor RAM) NOSRAM has the advantage of being able to perform non-destructive readout. On the other hand, when reading the stored data in the DOSRAM, the read is destructive. become.

[0087] The semiconductor device 10A includes a memory cell 91, which stores data that is frequently read out. You can write from SRAM to NOSRAM. As mentioned before, NOSRAM is non-destructive. Since destructive readout is possible, the frequency of data refresh can be reduced. As a result, the power consumption of the semiconductor device of one embodiment of the present invention can be reduced. Transistor 92 and transistor 93 shown in FIG. 3B each have one gate. The transistors shown are illustrative but not limiting. For example, transistor 92 and transistor Either or both of the transistors 93 are transistors having two gates (floor a transistor having a front gate and a back gate opposed to the front gate It is also possible to use the following.

[0088] 14A and 14B are schematic diagrams for explaining a modification of the semiconductor device 10 shown in FIG. The formula is shown below.

[0089] FIG. 14A shows the structure of the element layers 20_1 to 20_M in the semiconductor device 10 shown in FIG. In the semiconductor device 10B, the transistor layer 40 is disposed below the transistor layer 30. The semiconductor device 10B shown in FIG. The transistor layer 49 includes transistor layers 49_1 to 49_k. Even if the read transistor is turned on, the threshold voltage of the read transistor can be corrected.

[0090] FIG. 14B shows the structure of the element layers 20_1 to 20_M in the semiconductor device 10 shown in FIG. In addition to the transistor layer 40, the transistor layer 49 described in FIG. 14A is added to the semiconductor device. In this configuration, the threshold voltage of the read transistor is compensated for. It is possible to perform a corrective action.

[0091] 15A and 15B are circuit diagrams corresponding to the memory cell 42 described in FIG. 2B and the like. The circuit blocks corresponding to the circuit diagram are shown in FIG. 15A and FIG. 15B. Thus, memory cells 42 may be represented as blocks in the drawings and the like.

[0092] 15C and 15D show the transistor 31 and the correction circuit 3 described with reference to FIG. 2B and the like. 5, a circuit diagram corresponding to a transistor layer 30 having a transistor block diagram corresponding to the circuit diagram; As shown in FIG. 15C and FIG. 15D, the transistor 31 and The transistor layer 30 having the correction circuit 35 is shown as a block of the circuit 36 ​​in the drawings. It may be expressed as:

[0093] FIG. 16A shows a silicon substrate 50 having a memory cell formed of a Si transistor. 1 shows an example of the circuit configuration of a control circuit 51 for controlling the writing and reading of data. The control circuit 51 includes a switch circuit 52, a precharge circuit 53, a precharge circuit 54, and a sensor. a global bit line SA_GBL connected to the control circuit 51; The bit line SA_GBLB, bit lines BL and BLB are illustrated.

[0094] As shown in FIG. 16A, the switch circuit 52 is, for example, an n-channel transistor. The transistors 52_1 and 52_2 are A wiring pair of a global bit line SA_GBL and a global bit line SA_GBLB, The conductive state of the wiring pair of bit lines BL and BLB is switched.

[0095] The precharge circuit 53 includes an n-channel transistor 5 as shown in FIG. The precharge circuit 53 is configured to charge the bits 3_1 to 3_3 in response to the signal EQ. The potential between the line BL and the bit line BLB is set to the intermediate potential VPRE, which corresponds to VDD / 2. This is a circuit for charging.

[0096] The precharge circuit 54 includes a p-channel transistor 5 as shown in FIG. The precharge circuit 54 is configured to charge the bits 4_1 to 54_3 in response to a signal EQB. The potential between the output line BL and the bit line BLB is set to the intermediate potential VPRE, which corresponds to VDD / 2. This is a circuit for charging.

[0097] The sense amplifier 55 is connected to the wiring SAP or the wiring SAN as shown in FIG. 16A. The p-channel transistors 55_1 and 55_2 and the n-channel transistor The wiring SAP or wiring SAN is connected to VDD or V The transistors 55_1 to 55_4 are inverters. The transistor that constitutes the loop.

[0098] FIG. 16B illustrates a circuit block corresponding to the control circuit 51 described in FIG. 16A and the like. As shown in FIG. 16B, the control circuit 51 is shown as a block in the drawing. It may be expressed as:

[0099] FIG. 17 is a circuit diagram for explaining an example of the operation of the semiconductor device 10 of FIG. 15A to 15D, and 16A and 16B. It shows.

[0100] As shown in FIG. 17, the transistor layer 40 including the transistor layer 41_k includes a plurality of The memory cell 42 is connected to a pair of local bit lines LBL and The memory cell connected to the local bit line LBL_pre The local bit 42 is a memory cell to which data is written or read. Line LBL_pre is a local bit line to be precharged. The memory cells connected to LBL_pre continue to hold the data.

[0101] The local bit line LBL is electrically connected to the global bit line GBL via a circuit 36. The local bit line LBL_pre is connected to the global bit line 36_pre via the circuit 36_pre. The bit line GBLB is electrically connected to the bit line GBLB.

[0102] The transistor 97 is connected between the global bit line GBL and the global bit line GBLB. The transistor 97 functions as a switch for switching the conductive state of the signal SW 0 toggles it on or off.

[0103] The transistor 98 is connected to the global bit line GBL and the global It functions as a switch for switching the conductive state between the bit line SA_GBL. Transistor 98 is switched on or off by signal SW1.

[0104] The transistor 99 is connected between the global bit line GBLB and the global It functions as a switch for switching the conduction state between the bit line SA_GBLB and the Transistor 99 is switched on or off by signal SW2.

[0105] FIG. 18 is a timing chart for explaining the operation of the circuit diagram shown in FIG. In the timing chart of Figure 18, the global bit line SA_GBL and The wiring pair of the global bit line SA_GBLB, the global bit line GBL, For the GBLB line pair, when the data is at H level (data=H), The figures are divided into two cases:

[0106] In the timing chart shown in FIG. 18, the period from time T11 to time T13 is for writing data. That is, it corresponds to the period during which the operation described in FIG. 4A is performed. The period from time T16 to time T16 corresponds to a correction period. In other words, it corresponds to a period in which the operation described in FIG. 5A is performed. The period from time T16 to time T18 corresponds to the data read period. This corresponds to the period in which the above-described operation is performed. , H level.

[0107] At time T11, the signals MUX and WE are set to H level. The signals SW1 and SW2 are set to H level. The signal SW0 is set to the L level. Then, the power supply voltage (VDD, V SS) to the global bit line SA_GBL or the global bit line SA One of the wiring pairs of _GBLB, the global bit line GBL or the global bit line GBL One of the pair of lines B is charged. The potential of the local bit line LBL rises. The word line W The potential of L is set to H level, and the potential applied to the local bit line LBL (H in the case of FIG. 18) level) is written to memory cell 42.

[0108] At time T12, the potential of the word line WL is set to the L level. It will be held.

[0109] At time T13, both wiring SAP and SAN are set to VDD, and signals EQ and EQB are inverted. In addition, the wiring of the global bit line SA_GBL and the global bit line SA_GBLB The wiring pairs of the global bit line GBL and the global bit line GBLB are both at the H level. The local bit line LBL_pre is precharged to a high-level potential. After that, the signal MUX is set to the L level, and the signal WE may also be set to the low level.

[0110] At time T14, the signals RE and WE are set to the H level. The potential of the local bit line LBL_pre is discharged through the transistor 31. This discharge occurs when the voltage between the gate and source of transistor 31 drops below the threshold of transistor The current stops when the threshold voltage of the transistor 31 is reached.

[0111] At time T15, the signals WE and RE are both set to the L level. BL and the local bit line LBL_pre are connected in response to the threshold voltage of the transistor 31. The signals EQ and EQB are inverted again to stop the precharge. That is, the global bit line SA_GBL and the global bit line SA_GBLB The wiring pair of the global bit line GBL and the wiring pair of the global bit line GBLB are The object is placed in a floating state.

[0112] At time T16, the word line WL is set to the H level to perform charge sharing. The potential of the bit line LBL changes according to the data written in the memory cell 42. When data of the local bit line LBL is written to the memory cell 42, the potential of the local bit line LBL rises. When data of L level is written to the memory cell 42, the potential of the local bit line LBL On the other hand, in the local bit line LBL_pre, the voltage Vcc is increased by the operation of the word line WL. Since no charge sharing is performed, the potential does not change.

[0113] At time T17, the signals RE and MUX are set to the H level, so that the local bit line L In response to the potentials of the BL and the local bit line LBL_pre, the transistor of the circuit 36 A current flows through the local bit 31 and the transistor 31 included in the circuit 36_pre. Since the potentials of the line LBL and the local bit line LBL_pre are different, the transistor of the circuit 36 A difference occurs between the current flowing through the transistor 31 in the circuit 36_pre and the current flowing through the transistor 31 in the circuit 36_pre. This current difference is the current difference between the local bit line LBL The potential of the memory cell 42 depends on the data read from the memory cell 42. The data in the memory cell 42 is transferred to the global bit line SA_GB L, a pair of wirings of the global bit line SA_GBLB, the global bit line GBL, The amount of change in potential of the pair of bit lines GBLB can be converted into the amount of change in potential of the pair of bit lines GBLB.

[0114] At time T18, the signal RE is set to the L level. Then, the power supply voltage ( VDD, VSS) to operate the sense amplifier 55. By operating, the global bit lines SA_GBL and SA_GB LB line pair, the global bit line GBL and the global bit line GBLB line pair The potential is determined.

[0115] At time T19, the signal SW0 is set to the L level and the signal SW1 is set to the H level. The potential of the global bit line GBL and the global bit line GBLB is changed according to the read data. Specifically, when data is at the H level, the global bit line GBL and The potentials of the wiring pairs of the global bit line GBLB and the global bit line GBLB are both switched to the H level. When data is at the L level, the global bit line GBL and the global bit line GBLB In this state, the potentials of the word line WL are both switched to the L level. By doing so, a voltage corresponding to the logic of the read data is written back to the memory cell 42. This can be done.

[0116] At time T20, the signals MUX, WL, and WE are set to the L level. In this case, the data can be refreshed according to the logic of the read data.

[0117] In the semiconductor device 10 according to one embodiment of the present invention, the transistor layer 4 having the memory cell 42 This configuration is a stack of the local bit lines LBL. In addition, the capacitance of the capacitor 44 of the memory cell 42 can be reduced. In the resistor 42, the parasitic capacitance between the gate of the transistor 43 and the source or drain Depending on the amount, there is a risk of potential fluctuations occurring.

[0118] FIG. 19A shows a transistor 43 and a capacitor 44 included in a memory cell 42. 19A shows a circuit diagram of the transistors 19A and 19B, and the local bit line LBL is extracted. The parasitic capacitance between the gate and the source or drain of the transistor 43 is defined as Ctd and Ct This is illustrated as s.

[0119] In response to the change in the potential of the word line WL, the local bit line LBL, which is in an electrically floating state, The potential of varies depending on the capacitive coupling of the capacitances Ctd and Cts. The change in potential shortens the local bit line LBL and the capacitor 44 of the memory cell 42. This becomes particularly large when the capacitance is reduced.

[0120] FIG. 19B shows a schematic diagram of a waveform for explaining the fluctuation of the potential according to the capacitive coupling. In FIG. 19B, in the period T16 to T17 of the timing chart shown in FIG. The potential of the local bit line LBL and the local bit line LBL change in response to the change in the potential of the word line WL. 1 illustrates the change in potential of the local bit line LBL_pre. In this operation, the data written to the memory cell 42 is switched between H level (data=H) and L level ( The figures are shown separately for the cases where data = L) and where data = L.

[0121] As described above, according to one aspect of the present invention, the local bit line LBL is shortened, and the memory cell Since the capacitance of the capacitor 44 of the local bit line LBL The parasitic capacitance of the word line WL and the capacitance of the capacitor 44 can be reduced. The change in the potential of the local bit line LBL is steeper than the change in the potential of the During charge sharing at time T16, the potential of the local bit line LBL fluctuates as follows: This is steeper than the change in the potential of the word line WL (time T16_2). During this period, both the local bit line LBL and the capacitor 44 are in an electrically floating state. Therefore, as the potential of the word line WL rises, the potential of the local bit line LBL rises. The potential of the word line WL does not change, and the potential of the local There is no change in the potential of the bit line LBL_pre.

[0122] The potential of the local bit line LBL increases with the increase in the potential of the word line WL at time T1. In 7, the potentials of the local bit line LBL and the local bit line LBL_pre are The magnitude relationship is inverted. For example, when reading out the L level potential of the local bit line LBL, This can cause problems such as the potential of the local bit line LBL_pre rising above the Rub.

[0123] Therefore, the word line WL is switched from H level to L level at time T17. In other words, the transistor 43 is preferably configured to supply a current to the transistor 31. During the period in which the transistor 34 is made conductive to pass the current and perform data reading, In FIG. 19C, the potential of the word line WL at time T17 is The change in the potential of the local bit line LBL when the 1 illustrates a schematic diagram of a waveform for

[0124] In FIG. 19C, the change in the potential of the word line WL from time T16 to time T16_2 and The fluctuations in the potential of the local bit line LBL and the potential of the local bit line LBL_pre are shown in FIG. At time T17, the potential of the word line WL is changed from the H level to the L level. At time T17, the local bit line LBL and the capacitor 44 are switched to Since both the word line WL and the local bit line WL are electrically floating, the local bit The potential of the line LBL drops when the data is at both H and L levels. Without a change in the potential of the WL, there is no change in the potential of the local bit line LBL_pre. By inverting the potential of the word line WL at time T17, the local bit line This makes it possible to prevent the potential relationship between the local bit line LBL and the local bit line LBL_pre from being inverted. Cut.

[0125] By applying the operation of the word line WL in FIG. 19C to FIG. 18, the timing chart in FIG. 20 is obtained. This can be the action of the

[0126] In one embodiment of the present invention, a transistor layer having a memory cell and a correction circuit includes a data The data can be read out as a signal with the threshold voltage of the readout transistor corrected. By adopting this configuration, data read from the memory cell to the driver circuit is In addition, in the semiconductor device according to one embodiment of the present invention, By arranging multiple switches between the global bit lines, the The data can then be written back to the memory cell using the logic of the data.

[0127] (Embodiment 2) An example of a semiconductor device that functions as a memory device according to one embodiment of the present invention will be described below. Reveal.

[0128] FIG. 21 shows a semiconductor device having a memory unit 311 on an element layer 411 having a circuit formed thereon. The memory unit 470 (memory unit 470_1 to memory unit 470_m:m are two or more FIG. 21 is a diagram showing an example of a semiconductor device in which an element layer 411 is stacked. A plurality of memory units 470 are stacked on the element layer 411. The transistor layers 413 (transistor layers 413_1 to up to transistor layer 413_m), and a plurality of memory devices on each transistor layer 413 Layer 415 (memory device layer 415_1 to memory device layer 415_n: n is 2 or more In addition, in each memory unit 470, a transistor In the illustrated example, the memory device layer 415 is provided on the data layer 413. The present invention is not limited to this. A transistor layer 413 is provided on a plurality of memory device layers 415. Alternatively, memory device layers 415 may be provided above and below the transistor layer 413. .

[0129] The element layer 411 includes a transistor 300 provided on a semiconductor substrate 311. It can function as a circuit for a device (sometimes called a peripheral circuit). Examples of circuits include , column driver, row driver, column decoder, row decoder, sense amplifier, Charge circuit, amplifier circuit, word line driver circuit, output circuit, control logic circuit etc.

[0130] The transistor layer 413 includes a transistor 200T, which controls each memory unit 470. The memory device layer 415 can function as a circuit for controlling the memory device 4. The memory device 420 shown in this embodiment has a transistor 200M and a capacitor It has a capacitance element 292.

[0131] The value of m is not particularly limited, but is from 2 to 100, preferably from 2 to 100. It is preferably 50 or less, and more preferably 2 to 10. There is no restriction, but it is 2 or more and 100 or less, preferably 2 or more and 50 or less, and more preferably 2 or more and 100 or less. The product of m and n is 4 to 256, preferably 4 to 12. It is preferably 8 or less, and more preferably 4 to 64.

[0132] FIG. 21 also shows a transistor 200T included in the memory unit and a transistor 1 shows a cross-sectional view of the channel length direction of the 200M transistor.

[0133] As shown in FIG. 21, a transistor 300 is provided on a semiconductor substrate 311. On the memory unit 470, a transistor layer 413 and a memory device A layer 415 is provided, and the transistor layer 413 in one memory unit 470 The transistor 200T and the memory device 420 included in the memory device layer 415 are The conductor 424 electrically connects the transistor 300 and each memory unit 47 The transistor 200T included in the transistor layer 413 in FIG. The conductor 426 is electrically connected to the source and drain of the transistor 200T. , and the transistor 200T through a conductor 428 electrically connected to one of the gates. The conductors 424 are preferably electrically connected to each layer of the memory device layer 415. In addition, the conductor 426 is preferably provided between the transistor layer 413 and the memory It is preferable that the second layer is provided in each layer of the device layer 415.

[0134] In addition, as will be described later in detail, the side surfaces of the conductor 424 and the side surfaces of the conductor 426 are not wettable. It is preferable to provide an insulator that suppresses the permeation of impurities such as hydrogen and oxygen. Examples of such insulators include silicon nitride, aluminum oxide, and silicon nitride oxide. etc. can be used.

[0135] The memory device 420 includes a transistor 200M and a capacitive element 292. The transistor 200M has a structure similar to that of the transistor 200T in the transistor layer 413. In addition, the transistors 200T and 200M can be collectively called transistors It is sometimes called Sta 200.

[0136] Here, the transistor 200 has a region in which a channel is formed (hereinafter, a channel forming region A metal oxide (hereinafter, oxide semiconductor) that functions as an oxide semiconductor is added to a semiconductor containing the metal oxide. It is preferable to use a conductive material such as a conductor.

[0137] As an oxide semiconductor, for example, In-M-Zn oxide (element M is aluminum, gallium, Sodium, Yttrium, Tin, Copper, Vanadium, Beryllium, Boron, Titanium, Iron, Nickel , Germanium, Zirconium, Molybdenum, Lanthanum, Cerium, Neodymium, Hafnium One or more selected from aluminum, tantalum, tungsten, magnesium, etc. In addition, as the oxide semiconductor, indium oxide, In- Ga oxide and In-Zn oxide may also be used. By using a compound semiconductor, the on-current or field effect mobility of the transistor can be increased. It is possible.

[0138] The transistor 200 having an oxide semiconductor in a channel formation region is in a non-conducting state. Since the leakage current is extremely small, a semiconductor device with low power consumption can be provided. Conductors can be formed into films using methods such as sputtering, making them ideal for constructing highly integrated semiconductor devices. The transistor 200 may be used.

[0139] On the other hand, in a transistor using an oxide semiconductor, impurities and oxygen vacancies in the oxide semiconductor (V O The electrical properties of the material change depending on the oxygen vacancy. -Marine-on characteristic (a channel exists even when no voltage is applied to the gate electrode, and a transistor current flows through the resistor.

[0140] Therefore, an oxide semiconductor in which the impurity concentration and the density of defect states are reduced is preferably used. In this specification and the like, a low impurity concentration and a low defect level density are referred to as high purity intrinsic or or essentially high purity intrinsic.

[0141] Therefore, it is preferable that the impurity concentration in the oxide semiconductor be reduced as much as possible. Impurities in the oxide semiconductor include, for example, hydrogen, nitrogen, alkali metals, alkaline earth metals, and the like. Examples of rare earth metals include iron, nickel, and silicon.

[0142] In particular, hydrogen, which is an impurity contained in an oxide semiconductor, forms oxygen vacancies in the oxide semiconductor. In addition, defects in which hydrogen is inserted into oxygen vacancies (hereafter referred to as V O Sometimes called H. ) may generate electrons that act as carriers. In addition, some of the hydrogen atoms bond to metal atoms. In some cases, it reacts with oxygen to generate electrons that act as carriers.

[0143] Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is a normally-on transistor. In addition, hydrogen in the oxide semiconductor is easily degraded by stress such as heat or an electric field. Because hydrogen is easily mobile, the reliability of transistors deteriorates when a large amount of hydrogen is contained in an oxide semiconductor. There is also a risk that this may happen.

[0144] Therefore, the oxide semiconductor used in the transistor 200 does not contain impurities such as hydrogen and oxygen. It is preferable to use a high-purity intrinsic oxide semiconductor with reduced defects.

[0145] <Sealing structure> Therefore, in order to prevent the intrusion of impurities from the outside, materials that suppress the diffusion of impurities (hereinafter The transistor 200 is preferably sealed using a material having a barrier property against impurities. stomach.

[0146] In this specification, the term "barrier property" refers to the function of suppressing the diffusion of a corresponding substance (permeability). Or, the corresponding substance is captured and fixed (gettering). This function is also called "check".

[0147] For example, aluminum oxide is a material that has the function of suppressing the diffusion of hydrogen and oxygen. Minium, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride Silicon nitride or silicon oxide nitride, etc. In particular, silicon nitride or silicon oxide nitride Since it has a high barrier property against hydrogen, it is preferable to use it as a sealing material.

[0148] Furthermore, for example, aluminum oxide is used as a material having the function of capturing and fixing hydrogen. Metal oxides such as ZnO, hafnium oxide, gallium oxide, and indium gallium zinc oxide There is.

[0149] Between the transistor 300 and the transistor 200, an insulating layer having a barrier property is provided. Preferably, an insulator 211, an insulator 212, and an insulator 214 are provided. 1. At least one of the insulator 212 and the insulator 214 is free from the diffusion or permeation of impurities such as hydrogen. By using a material that suppresses overshoot, the semiconductor substrate 311, the transistor 300, etc. This can prevent impurities such as hydrogen and water from diffusing into the transistor 200. At least one of the insulating material 211, the insulating material 212, and the insulating material 214 is made of a material that suppresses oxygen permeation. By using the material, the channel of the transistor 200 or the transistor layer 413 It is possible to prevent oxygen from diffusing into the element layer 411. The insulator 212 is made of a material that suppresses the permeation of impurities such as hydrogen and water. It is preferable to use a material that suppresses the permeation of oxygen by using hydrogen as the insulator 214. It is more preferable to use a material having absorbing and occluding properties. As the insulator 212, for example, a nitride such as silicon nitride or silicon oxynitride is used. The insulator 214 may be, for example, aluminum oxide, hafnium oxide, or oxide. Metal oxides such as gallium oxide, indium gallium zinc oxide, etc. can be used. In particular, it is preferable to use aluminum oxide as the insulator 214 .

[0150] In addition, the side surfaces of the transistor layer 413 and the memory device layer 415, i.e., the memory unit The sides of the knit 470 are preferably provided with an insulator 287, and the memory unit 47 It is preferable that an insulator 282 is provided on the upper surface of the insulating layer 282. It is preferable that the insulator 287 contacts the insulator 211, the insulator 212, and the It is preferable that the insulator 287 and the insulator 214 are in contact with each other. It is preferable to use a material that can be used for the insulator 214 as the material 282 .

[0151] Also, the insulator 283 and the insulator 287 are disposed so as to cover the insulator 282 and the insulator 287. 84 is preferably provided, and the insulator 283 is the insulator 211, the insulator 212, and In FIG. 21, the insulator 287 is preferably in contact with at least one of the insulators 214. The side of the insulator 214, the side of the insulator 212, and the top and side of the insulator 211 are in contact with each other. In the example in which the insulator 283 contacts the upper surface and side surface of the insulator 287 and the upper surface of the insulator 211, However, the present embodiment is not limited to this. and the upper and side surfaces of the insulator 212, and the insulator 283 contacts the upper and side surfaces of the insulator 287. The insulator 282 may be in contact with the side surface and the top surface of the insulator 28. As the insulating layer 7, a material that can be used for the insulators 211 and 212 can be used. preferable.

[0152] In the above structure, the insulator 287 and the insulator 282 are made of a material that suppresses oxygen permeation. It is preferable to use a material that can capture hydrogen as the insulator 287 and the insulator 282. It is even more preferable to use a material that has good adhesion properties. By using a material that has the function of capturing and fixing hydrogen on the side close to the substrate, The hydrogen in the resistor 200 or the memory unit 470 is insulated by the insulators 214 and 287. , and insulator 282, trapping and attaching the hydrogen concentration in transistor 200. The degree of the heat can be reduced. In addition, hydrogen, water, etc. can be used as the insulator 283 and the insulator 284. It is preferable to use a material that inhibits the permeation of any impurities.

[0153] With the above-described structure, the memory unit 470 includes the insulator 211, the insulator 21 2, insulator 214, insulator 287, insulator 282, insulator 283, and insulator 284 More specifically, the memory unit 470 is surrounded by an insulator 214, an insulator 287, and The memory unit 281 is surrounded by an insulating material 282 (which may be referred to as a first structure). The first structure includes the insulator 211, the insulator 212, the insulator 283, and the The second structure is surrounded by an insulator 284 (sometimes referred to as a second structure). In addition, a structure in which the memory unit 470 is surrounded by a plurality of structures of two or more layers is called a nested structure. Here, the memory unit 470 being surrounded by a plurality of structures is called a memory The unit 470 may be described as being encapsulated by multiple insulators.

[0154] In addition, the second structure seals the transistor 200 via the first structure. The hydrogen existing outside the second structure is absorbed by the second structure into the inside ( The diffusion of the first structure toward the second structure (the transistor 200 side) is suppressed. It can efficiently capture and fix hydrogen present in the internal structure of the body.

[0155] Specifically, the first structure is made of a metal oxide such as aluminum oxide. The first structure may be made of a nitride such as silicon nitride. In the second embodiment, an aluminum oxide film is disposed between the transistor 200 and the silicon nitride film. It is good.

[0156] Furthermore, the hydrogen concentration in the film can be controlled by appropriately setting the film formation conditions for the material used for the structure. can be reduced.

[0157] Generally, films formed using the CVD method have higher thermal conductivity than films formed using the sputtering method. On the other hand, the compound gas used in the CVD method often contains hydrogen, and The film formed by the VD method has a higher hydrogen content than the film formed by the sputtering method. The quantity is large.

[0158] Therefore, for example, a film having a reduced hydrogen concentration in the film adjacent to the transistor 200 may be used. (Specifically, a film formed by sputtering) is preferably used. As a film for suppressing diffusion, a film with high film-forming properties but a relatively high hydrogen concentration in the film (specifically In the case of using a film formed by a CVD method, the hydrogen concentration is compared with that of the transistor 200. The film has high performance and high covering ability, and has the function of capturing and fixing hydrogen. It is advisable to provide a film having a reduced elemental concentration.

[0159] In other words, the film disposed adjacent to the transistor 200 has a relatively low hydrogen concentration. On the other hand, a film having a relatively high hydrogen concentration may be used at a distance from the transistor 200. It is advisable to place them apart.

[0160] Specifically, the transistor 200 is formed of a nitride film formed by using a CVD method. When sealing with silicon, the transistor 200 and a nitride film formed by a CVD method are An aluminum oxide film formed by sputtering is disposed between the silicon film. More preferably, the silicon nitride film is formed by a CVD method and the sputtering method is formed by a CVD method. A thin film was formed by sputtering between the aluminum oxide film formed by the annealing method and the aluminum oxide film formed by the sputtering method. A silicon nitride film may be disposed.

[0161] In addition, when the film is formed by the CVD method, it does not contain hydrogen atoms or the content of hydrogen atoms is By depositing the film using a compound gas with low hydrogen concentration, the hydrogen concentration in the deposited film is reduced. This is also fine.

[0162] Also, between each transistor layer 413 and the memory device layer 415 or between each memory device It is also preferable that an insulator 282 and an insulator 214 are provided between the insulating layers 415 . In addition, it is preferable that an insulator 296 is provided between the insulator 282 and the insulator 214. The insulator 296 may be made of the same material as the insulators 283 and 284. Alternatively, silicon oxide or silicon oxynitride can be used. Insulating materials may be used. Here, insulator 282, insulator 296, and insulator 214 may be elements constituting the transistor 200. The insulator 214 also serves as a component of the transistor 200, thereby making it possible to manufacture a semiconductor device. This is preferable because it can reduce the number of steps required.

[0163] Also, between each transistor layer 413 and the memory device layer 415 or between each memory device Insulators 282, 296, and 214 are provided between the insulating layers 415. The side of the transistor is preferably in contact with the insulator 287. The resistor layer 413 and the memory device layer 415 are respectively covered with the insulator 282 and the insulator 296. , the insulator 214, the insulator 287, the insulator 283, and the insulator 284. will be done.

[0164] In addition, an insulator 274 may be provided around the insulator 284. A conductor 430 is provided so as to be embedded in the insulators 284, 283, and 211. The conductor 430 may be a transistor 300, i.e., a circuit included in the element layer 411. and electrically connect it to.

[0165] In the memory device layer 415, the capacitance element 292 is disposed in the same layer as the transistor 200M. Therefore, the height of the memory device 420 can be made to be approximately the same as that of the transistor 200M. This can prevent the height of each memory device layer 415 from becoming excessively large. This allows the number of memory device layers 415 to be increased relatively easily. For example, a stack of a transistor layer 413 and a memory device layer 415 is It may be possible to set the number of layers to about 0.

[0166] <Transistor 200> 22A, the transistor 200T and the memory The transistor 200M included in the re-device 420 can be used as the transistor 200. Let me explain 0.

[0167] As shown in FIG. 22A, the transistor 200 includes an insulator 216 and a conductor 205 ( The oxide 23 is made of a conductor 205a and a conductor 205b, an insulator 222, an insulator 224, and an oxide 23. 0 (oxide 230a, oxide 230b, and oxide 230c) and conductor 242 (conductive The oxide 243 (oxide 243a and oxide 243b), an insulator 272, an insulator 273, an insulator 250, and a conductor 260 (conductor 260a, and 260b).

[0168] In addition, the insulator 216 and the conductor 205 are provided on the insulator 214, and the insulator 27 An insulator 280 and an insulator 282 are provided on the insulator 214. , and insulator 282 can be considered to be part of transistor 200. do.

[0169] In addition, in the semiconductor device of one embodiment of the present invention, The conductor 240 (conductor 240a and conductor 240b) functions as a The insulator 241 (insulator 241a, In addition, on the insulator 282 and the conductor 240, The conductor 246 (conductor 246a) is electrically connected to the conductor 240 and functions as a wiring. , and conductor 246b) are provided.

[0170] The conductors 240a and 240b are made of tungsten, copper, or aluminum. It is preferable to use a conductive material mainly composed of rubber. The body 240b may be a laminate structure.

[0171] In addition, when the conductor 240 has a layered structure, impurities such as water or hydrogen, and oxygen It is preferable to use a conductive material that has a function of suppressing transmission. For example, tantalum, nitride, etc. Tantalum oxide, titanium, titanium nitride, ruthenium, or ruthenium oxide may be used. In addition, it is preferable that the porous membrane has a function of suppressing the permeation of impurities such as water or hydrogen, and oxygen. The conductive material may be used in a single layer or a multilayer structure. Impurities such as water or hydrogen diffused from the conductor 280 etc. are absorbed in the conductor 240a and the conductor 2 40b, it is possible to further reduce the inclusion of the oxide 230. 280 from being absorbed by the conductors 240a and 240b. This can be done.

[0172] The insulator 241 provided in contact with the side surface of the conductor 240 is, for example, silicon nitride. Silicon, aluminum oxide, silicon nitride oxide, or the like may be used. is provided in contact with the insulator 272, the insulator 273, the insulator 280, and the insulator 282. Therefore, impurities such as water or hydrogen from the insulator 280 are absorbed into the conductor 240a and the conductor It is possible to suppress the inclusion of silicon nitride in the oxide 230 through the body 240b. The insulator 280 is preferably made of polycarbonate because of its high blocking ability against hydrogen. This can prevent oxygen from being absorbed into the conductors 240a and 240b.

[0173] The conductor 246 is made of a conductive material based on tungsten, copper, or aluminum. The conductor may have a laminated structure, for example, titanium or Alternatively, the conductive material may be a laminate of titanium nitride and the conductive material. The insulating film 11 may be formed so as to be embedded in the opening.

[0174] In transistor 200, conductor 260 functions as a first gate of the transistor. The conductor 205 functions as a second gate of the transistor. 2a and the conductor 242b function as a source electrode and a drain electrode.

[0175] The oxide 230 functions as a semiconductor having a channel formation region.

[0176] Insulator 250 serves as the first gate insulator and is connected to insulator 222 and insulator 22. 4 acts as the second gate insulator.

[0177] Here, the transistor 200 shown in FIG. 22A includes an insulator 280, an insulator 273, an insulator 272, the conductor 242, etc., in an opening, the conductor 260 is oxide 230c and It is formed in a self-aligned manner through the insulator 250 .

[0178] That is, the conductor 260 is connected to the insulator 280 via the oxide 230c and the insulator 250. Since the conductive material 242 is formed to fill the openings provided in the conductive material 242a and the conductive material 242b, In this region, alignment of the conductor 260 is not required.

[0179] Here, it is preferable to provide an oxide 230c in an opening provided in the insulator 280 or the like. Therefore, the insulator 250 and the conductor 260 are connected to the oxide 230c via the oxide 230c. 0b and an area overlapping with the stacked structure of oxide 230a. In this case, the oxide 230c and the insulator 250 can be formed by successive film formation. Therefore, the interface between the oxide 230 and the insulator 250 can be kept clean. As a result, the effect on carrier conduction is reduced, and the transistor 200 has a high on-state current and a high Wave number characteristics can be obtained.

[0180] In addition, in the transistor 200 shown in FIG. 22A, the bottom and side surfaces of the conductor 260 are insulated. The bottom and side surfaces of the insulator 250 are in contact with the oxide 230c. .

[0181] The transistor 200 also includes an insulator 282 and an oxide 230 as shown in FIG. 22A. c is in direct contact with the insulating material 280. The diffusion of oxygen into the conductor 260 can be suppressed.

[0182] Therefore, the oxygen contained in the insulator 280 is transferred to the oxide 230a and the oxide 230c through the oxide 230c. Since the oxide 230a and the oxide 230b can be efficiently supplied with the oxygen, the oxygen can be efficiently supplied to the oxide 230a and the oxide 230b. The oxygen vacancies in the material 230b are reduced, and the electrical characteristics and reliability of the transistor 200 are improved. It is possible to do so.

[0183] The following describes in detail the configuration of a semiconductor device including a transistor 200 according to one embodiment of the present invention. This article explains:

[0184] The transistor 200 includes an oxide 230 (oxide 230a, oxide The oxide 230c is provided with a metal oxide (hereinafter It is preferable to use a semiconductor material other than the above-mentioned which is a nitride semiconductor.

[0185] For example, metal oxides that function as oxide semiconductors have an energy gap of 2 eV or more. It is preferable to use an energy gap of 2.5 eV or more. By using a thin metal oxide, the leakage current (on) of the transistor 200 in the non-conducting state is By using such transistors, It is possible to provide a semiconductor device with low power consumption.

[0186] Specifically, the oxide 230 is an In-M-Zn oxide (wherein the element M is aluminum, Gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel Kel, Germanium, Zirconium, Molybdenum, Lanthanum, Cerium, Neodymium, Hafnium One or more selected from the group consisting of tungsten, tantalum, magnesium, etc. In particular, the element M may be an oxide of a metal such as aluminum, gallium, yttrium, or the like. Thorium or tin may be used. In-M oxide, In -Zn oxide or M-Zn oxide may also be used.

[0187] As shown in FIG. 22A, the oxide 230 is formed of an oxide 230a on the insulator 224 and an oxide 230a on the oxide 230b, and a metal oxide layer 230c disposed on the oxide 230b, at least partially and an oxide 230c in contact with the upper surface of 230b. The side of 30c is made of oxide 243a, oxide 243b, conductor 242a, conductor 242b, It is preferable that the insulating material 272, the insulating material 273, and the insulating material 280 are provided in contact with each other. stomach.

[0188] That is, the oxide 230 is composed of an oxide 230a, an oxide 230b on the oxide 230a, The oxide 230c is on the oxide 230b. The oxide 230a is placed under the oxide 230b. By having the oxide 230a, the structure formed below the oxide 230a can be prevented from being transferred to the oxide 230b. The diffusion of impurities can be suppressed. By this, impurities from the structure formed above the oxide 230c are transferred to the oxide 230b. It is possible to suppress the diffusion of substances.

[0189] In the transistor 200, the oxide 23 is formed in the channel formation region and in the vicinity thereof. 1 shows a structure in which three layers of oxide 230a, oxide 230b, and oxide 230c are laminated. However, the present invention is not limited to this. For example, a single layer of oxide 230b, oxide 23 a two-layer structure of oxide 230b and oxide 230a, a two-layer structure of oxide 230b and oxide 230c, or For example, the oxide 230c may have a two-layer structure. In this case, a four-layer laminate structure may be provided.

[0190] In addition, the oxide 230 has a laminated structure of multiple oxide layers with different atomic ratios of each metal atom. Specifically, in the metal oxide used for the oxide 230a, The atomic ratio of element M in the metal oxide used for oxide 230b is It is preferable that the atomic ratio of the metal oxide used for the oxide 230a is larger than that of the element M. In the oxide 230b, the atomic ratio of element M to In is In the oxide 230b, the atomic ratio of element M to In is preferably larger than that of element M. In the metal oxide used in the present invention, the atomic ratio of In to the element M is In the metal oxide, the atomic ratio of In to the element M is preferably larger than that of In. The oxide 230c is a metal oxide that can be used for the oxide 230a or the oxide 230b. Compounds such as fluorine-containing fluorine compounds can be used.

[0191] Specifically, the oxide 230a has an atomic ratio of In:Ga:Zn=1:3:4. or a metal with a composition of 1:1:0.5 or ... An oxide may be used.

[0192] The oxide 230b is In:Ga:Zn=4:2:3 [atomic ratio] or or a metal oxide having a composition of 1:1:1 or ... In addition, the oxide 230b may have an atomic ratio of In:Ga:Zn=5:1:3. Or a composition close to that, or In:Ga:Zn=10:1:3 [atomic ratio] or Metal oxides with compositions close to those may be used. Oxides (e.g., In:Zn=2:1 [atomic ratio] or a composition close to that, In:Zn = 5:1 [atomic ratio] or a composition close to that, or In:Zn = 10:1 [atomic ratio] ] or a composition close thereto) may be used as the oxide 230b. may also be used.

[0193] In addition, the oxide 230c is In:Ga:Zn=1:3:4 [atomic ratio or its or a composition close to that, Ga:Zn=2:1 [atomic ratio] or a composition close to that, or Ga: A metal oxide having a composition of Zn=2:5 [atomic ratio] or a composition close to that may be used. The oxide 230c is formed of a material that can be used for the oxide 230b, and may be formed in a single layer or a multilayer. For example, a specific example of the oxide 230c having a laminated structure is In. :Ga:Zn=4:2:3 [atomic ratio] or a composition close to that, and In:Ga:Zn= 1:3:4 [atomic ratio] or a laminate structure with a composition close to that, Ga:Zn=2:1 [atomic ratio] In:Ga:Zn=4:2:3 [atomic ratio] or a composition close to that. The composition is a laminated structure with a composition close to that, Ga:Zn=2:5 [atomic ratio] or a combination close to that. and a laminated structure with a composition of In:Ga:Zn=4:2:3 [atomic ratio] or a composition close to that. , gallium oxide and In:Ga:Zn=4:2:3 [atomic ratio] or a composition close to that and a laminated structure.

[0194] Note that the structure of the OS transistor included in the memory cell 42 shown in Embodiment 1 and the transistor The structure of the OS transistor in the memory cell layer 30 may be different from that of the OS transistor in the memory cell layer 30. The oxide 230c of the OS transistor provided in the resonator 42 is made of In:Ga:Z A metal oxide with a composition of n=4:2:3 [atomic ratio] or close to that is used to fabricate a transistor. The oxide 230c of the OS transistor provided in the layer 30 has In:Ga:Zn= 5:1:3 [atomic ratio] or a composition close to that, In:Ga:Zn=10:1:3 [atomic ratio] In:Zn=10:1 [atomic ratio] or nearby composition, In:Zn=10:1 [atomic ratio] or nearby Composition: In:Zn=5:1 [atomic ratio] or a composition close to that, In:Zn=2:1 It is sufficient to use a metal oxide having a composition of [atomic ratio] or close thereto.

[0195] In addition, the ratio of indium in the oxide 230b and the oxide 230c is increased. This can increase the on-state current or field effect mobility of the transistor, The aforementioned "nearby composition" includes a range of ±30% of the desired atomic ratio.

[0196] The oxide 230b may have crystallinity. For example, the oxide 230b may have crystallinity. S(c-axis aligned crystalline oxide semic It is preferable to use a crystalline oxide such as CAAC-OS. The material has few impurities and defects (such as oxygen vacancies), is highly crystalline, and has a dense structure. Therefore, the extraction of oxygen from the oxide 230b by the source electrode or the drain electrode In addition, even if a heat treatment is performed, oxygen is not removed from the oxide 230b. Since the transistor 200 can be manufactured at high temperatures ( It is stable against the so-called thermal budget.

[0197] The conductor 205 is disposed so as to overlap the oxide 230 and the conductor 260. Preferably, the conductor 205 is embedded in the insulator 216 .

[0198] When the conductor 205 functions as a gate electrode, the potential applied to the conductor 205 is By changing the potential applied to the transistor 20 independently of the potential applied to the body 260, the In particular, the threshold voltage (Vth) of 0 can be controlled by applying a negative potential to the conductor 205. By applying this, the Vth of the transistor 200 is increased and the off-current is reduced. Therefore, it is better to apply a negative potential to the conductor 205 than not to apply a negative potential to the conductor 205. The drain current when the potential applied to the conductor 260 is 0 V is smaller than that when the potential applied to the conductor 260 is 0 V. can be done.

[0199] As shown in FIG. 22A, the conductor 205 is a conductor 242a of the oxide 230 and It is preferable that the area is set larger than the area that does not overlap with the conductor 242b. However, the conductor 205 is formed on the oxide 230a and the oxide 230b in the channel width direction of the oxide 230. It is preferable that the oxide 230b extends to the outer region. On the outside of the side surface of the channel width direction of the semiconductor substrate 100, the conductor 205 and the conductor 260 are It is preferable that the conductor 205 overlaps with an insulator. In the plasma processing in the manufacturing process after the formation of the conductor 205, local charge However, one aspect of the present invention is that The conductor 205 is at least a conductor 242a and a conductor 242b. It is sufficient to overlap with the oxide 230 located between them.

[0200] In addition, with the bottom surface of the insulator 224 as a reference, the oxide 230a and the oxide 230b and the conductor The height of the bottom surface of the conductor 260 in the region where the conductor 260 does not overlap the oxide 230b is It is preferable that the bottom surface of the substrate is located at a position lower than the height of the bottom surface of the substrate.

[0201] Although not shown, the conductor 260 functioning as a gate in the channel width direction is The side and top surfaces of the oxide 230b in the panel formation region are covered with the oxide 230c and the insulator 250. By using a structure in which the conductor 260 is covered with the oxide 230b, the electric field generated by the conductor 260 is generated in the oxide 230b. Therefore, the on-state current of the transistor 200 is increased. In this specification, the conductor 260 can increase the current and improve the frequency characteristics. , and the electric field of the conductor 205 electrically surrounds the channel forming region. The structure of the FET is called the surrounded channel (S-channel) structure. .

[0202] The conductor 205a has a conductive property that suppresses the permeation of impurities such as water or hydrogen and oxygen. For example, titanium, titanium nitride, tantalum, or tantalum nitride may be used. The conductor 205b can be made of tungsten, copper, or aluminum. It is preferable to use a conductive material having a thickness of 100 μm and a thickness of 100 μm. A multi-layer structure having more than one layer may also be used.

[0203] Here, the oxide semiconductor, the insulator or conductor located under the oxide semiconductor, and the oxide The insulating or conductive material on the upper layer of the oxide semiconductor is separated into different layers without being exposed to the atmosphere. By continuously depositing the seeds, the concentration of impurities (especially hydrogen and water) is reduced, resulting in a substantially high-purity This is preferable because a highly intrinsic oxide semiconductor film can be formed.

[0204] At least one of the insulator 222, the insulator 272, and the insulator 273 is water or Preventing impurities such as hydrogen from entering the transistor 200 from the substrate side or from above. Therefore, the insulator 222 preferably functions as a barrier insulating film that suppresses the At least one of the body 272 and the insulator 273 is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen Diffusion of impurities such as atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms It is preferable to use an insulating material that has a function of suppressing diffusion (i.e., the impurities are unlikely to penetrate). Alternatively, the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) is suppressed. It is preferable to use an insulating material that has the function of preventing oxygen from permeating therethrough (the insulating material is less permeable to the oxygen).

[0205] For example, silicon nitride or silicon oxynitride is used as the insulator 273. The body 222 and the insulator 272 are made of aluminum oxide or hafnium oxide. It is preferable that

[0206] As a result, impurities such as water or hydrogen pass through the insulator 222 and enter the transistor 200 Alternatively, oxygen contained in the insulator 224 can be prevented from diffusing to the other side. Diffusion to the substrate side via the insulator 222 can be suppressed.

[0207] In addition, impurities such as water or hydrogen are arranged through the insulators 272 and 273. This can suppress the diffusion of the insulating material 280 and the like to the transistor 200 side. In this way, the transistor 200 is protected from impurities such as water or hydrogen, and from the diffusion of oxygen. The structure is surrounded by an insulator 272 having a function of suppressing the noise and an insulator 273. preferable.

[0208] Here, it is preferable that the insulator 224 in contact with the oxide 230 is heated to release oxygen. In this specification, the oxygen released by heating may be referred to as excess oxygen. The insulator 224 may be made of silicon oxide or silicon oxynitride as appropriate. By providing an insulator containing the oxide 230 in contact with the oxide 230, oxygen vacancies in the oxide 230 are reduced. Therefore, the reliability of the transistor 200 can be improved.

[0209] Specifically, the insulator 224 is made of an oxide material from which some oxygen is released when heated. It is preferable that the oxides which desorb oxygen by heating are those which are determined by thermal desorption spectrometry (TDS). Thermal Desorption Spectroscopy (TDS) analysis revealed that oxygen The amount of molecules desorbed is 1.0×10 18 molecules / cm 3 More than 1.0x, preferably 10 19 molecules / cm 3 More preferably, 2.0×10 19 mole cules / cm 3or more than 3.0×10 20 molecules / cm 3 That's all. The surface temperature of the film during the TDS analysis was 100°C or higher. A temperature range of 700° C. or lower, or 100° C. to 400° C. is preferred.

[0210] The insulator 222 prevents impurities such as water or hydrogen from entering the transistor 200 from the substrate side. For example, the insulator 222 is preferably a barrier insulating film that suppresses the Preferably, the insulator 222 has a lower hydrogen permeability than the insulator 224. 3, the insulator 224 and the oxide 230 are surrounded, and water or Impurities such as hydrogen can be prevented from entering the transistor 200 .

[0211] Further, the insulator 222 is made of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). It is preferable that the material has a function of suppressing diffusion (i.e., the oxygen is less likely to permeate). For example, Preferably, the body 222 has a lower oxygen permeability than the insulator 224. The oxide 230 has a function of suppressing the diffusion of impurities and oxygen contained in the insulator 2. This is preferable because it can reduce diffusion below 22. This can suppress reaction with the body 224 and the oxygen contained in the oxide 230.

[0212] The insulator 222 is made of one or both of aluminum and hafnium, which are insulating materials. It is recommended to use an insulator containing oxide. Insulators containing oxides include aluminum oxide, hafnium oxide, aluminum and hafnium oxide, and It is preferable to use an oxide containing hafnium (hafnium aluminate). When the insulator 222 is formed using such a material, the insulator 222 is oxidized by the oxide 230. The emission of hydrogen and the incorporation of impurities such as hydrogen into the oxide 230 from the periphery of the transistor 200 are prevented. It acts as a suppressing layer.

[0213] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, etc. may be added to these insulators. tungsten oxide, yttrium oxide, Zirconium oxide may be added, or these insulators may be nitrided. Silicon oxide, silicon oxynitride or silicon nitride may be laminated on the insulator. .

[0214] The insulator 222 may be, for example, aluminum oxide, hafnium oxide, tantalum oxide, Zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrT These include so-called high-k materials such as (Ba,Sr)TiO3 (BST) or (Ba,Sr)TiO3 (BST). For example, when the insulator 222 is a laminate, the insulator may be made of an acid. A three-layer stack in which zirconium oxide, aluminum oxide, and zirconium oxide are formed in this order. Layers of zirconium oxide, aluminum oxide, zirconium oxide, aluminum oxide The insulator 222 may be a four-layer laminate in which a ferrite layer and a ferrite layer are formed in sequence. A compound containing fluorine and zirconium may also be used. As integration density increases, the gate insulator and the dielectric material used in the capacitor element become thinner. This can cause problems such as leakage currents in transistors and capacitors. and the use of high-k materials for the insulators that function as dielectrics in the capacitor elements. While maintaining the physical film thickness, the gate potential during transistor operation is reduced and the capacitance element is It becomes possible to secure capacity.

[0215] The insulator 222 and the insulator 224 may have a laminated structure of two or more layers. In this case, the laminated structure is not limited to the same material, and may be made of different materials. good.

[0216] Also, the oxide 230b and the conductor 242 functioning as a source electrode or a drain electrode are (conductor 242a and conductor 242b) and oxide 243 (oxide 243a and The conductor 242 and the oxide 230b may be arranged in such a manner that the conductor 242 and the oxide 230b are not in contact with each other. This structure can suppress the conductor 242 from absorbing oxygen from the oxide 230b. In other words, by preventing the oxidation of the conductor 242, the decrease in the conductivity of the conductor 242 can be suppressed. Therefore, the oxide 243 has a function of suppressing the oxidation of the conductor 242. is preferred.

[0217] The oxide layer 230b is formed between the conductor 242, which functions as a source electrode or a drain electrode, and the oxide layer 230b. By disposing the oxide 243 having the function of suppressing the transmission of This is preferable because the electrical resistance between the conductor 230 and the conductor 230b is reduced. The electrical characteristics and reliability of the transistor 200 can be improved. do.

[0218] Oxide 243: Aluminum, gallium, yttrium, tin, copper, vanadium, Beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum , lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium Using a metal oxide having one or more elements M selected from the group consisting of tungsten, sodium, etc. In particular, the element M may be aluminum, gallium, yttrium, or tin. It is preferable that the oxide 243 has a higher concentration of the element M than the oxide 230b. Alternatively, gallium oxide may be used as the oxide 243. Metal oxides such as -M-Zn oxide may be used. In the metal oxide, the atomic ratio of element M to In is In the oxide, the atomic ratio of element M to In is preferably larger than that of element In. The thickness of 43 is preferably 0.5 nm or more and 5 nm or less, and more preferably 1 nm or more and 3 nm or less. m or less. In addition, it is preferable that the oxide 243 has crystallinity. In the case where the oxide 230 has the above-mentioned property, the release of oxygen from the oxide 230 can be suitably suppressed. For example, If the oxide 243 has a crystalline structure such as a hexagonal crystal, it can release oxygen from the oxide 230. It may be possible to suppress it.

[0219] The oxide 243 is not necessarily provided. In that case, the conductor 242 (conductor 2 When the oxide 230 comes into contact with the conductor 242a and the conductor 242b, the oxide in the oxide 230 The hydrogen may diffuse into the conductor 242, causing the conductor 242 to oxidize. As a result, the conductivity of the conductor 242 is likely to decrease. The conductor 242 absorbs the oxygen in the oxide 230. This can be rephrased.

[0220] In addition, oxygen in the oxide 230 is converted into conductor 242 (conductor 242a and conductor 242b ) between the conductor 242a and the oxide 230b and between the conductor 242b A foreign layer may be formed between the conductor 242 and the oxide 230b. Since the layer also contains a large amount of oxygen, it is presumed that the layer has insulating properties. The three-layer structure of the oxide 230b, the hetero layer, and the oxide 230b is a three-layer structure consisting of a metal, an insulator, and a semiconductor. It can be considered as a MIS (Metal-Insulator-Semiconductor) structure. In some cases, this is called a diode junction structure, or a MIS structure. be.

[0221] The above-mentioned different layer is not limited to being formed between the conductor 242 and the oxide 230b. For example, a different layer may be formed between the conductor 242 and the oxide 230c, or between the conductor 242 and the oxide 230c. 42 and oxide 230b, and between conductor 242 and oxide 230c. There are cases.

[0222] On the oxide 243, a conductor 242 ( The conductor 242 has a thickness of, for example, , 1 nm or more and 50 nm or less, preferably 2 nm or more and 25 nm or less.

[0223] The conductor 242 may be aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, etc. Ru, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, Magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium A metal element selected from rontium and lanthanum, or an alloy containing the above metal elements Alternatively, it is preferable to use an alloy of the above-mentioned metal elements. For example, titanium nitride tantalum, titanium nitride, tungsten, nitrides containing titanium and aluminum, tantalum and aluminum Ruthenium nitrides, ruthenium oxide, ruthenium nitride, strontium and ruthenium It is preferable to use an oxide containing lanthanum and nickel. Tantalum oxide, titanium nitride, titanium and aluminum nitride, tantalum and aluminum Nitrides containing ruthenium, ruthenium oxide, ruthenium nitride, and oxides containing strontium and ruthenium. The oxides containing lanthanum and nickel are conductive materials that are difficult to oxidize or absorb oxygen. This is preferable because it is a material that maintains its conductivity even when absorbed.

[0224] The insulator 272 is provided in contact with the upper surface of the conductor 242 and functions as a barrier layer. With this configuration, the conductor 242 can effectively suppress the overcurrent of the insulator 280. Absorption of excess oxygen can be suppressed. In addition, by suppressing oxidation of the conductor 242, It is possible to suppress an increase in the contact resistance between the transistor 200 and the wiring. This can provide the transistor 200 with good electrical characteristics and reliability.

[0225] Therefore, it is preferable that the insulator 272 has a function of suppressing the diffusion of oxygen. For example, Preferably, the insulator 272 has a function of suppressing oxygen diffusion more effectively than the insulator 280. The insulator 272 may be, for example, aluminum or hafnium. It is preferable to form an insulator containing oxide. Also, as the insulator 272, for example, aluminum nitride is used. An insulator containing minium may be used.

[0226] As shown in FIG. 22A, the insulator 272 is formed on a part of the upper surface of the conductor 242b and the conductor Although not shown, the insulator 272 is in contact with the side surface of the conductor 242a. The insulator 272 is in contact with a part of the conductor 242a and a side surface of the conductor 242a. In this way, for example, oxygen added to the insulator 280 becomes conductive. The absorption by the body 242 can be suppressed.

[0227] The insulator 250 functions as a gate insulator. The insulator 250 is formed on the oxide 230c. The insulator 250 is preferably disposed in contact with the surface. , silicon oxynitride, silicon nitride, silicon oxide doped with fluorine, and oxide doped with carbon. Silicon oxide doped with carbon and nitrogen, and silicon oxide with vacancies were used. In particular, silicon oxide and silicon oxynitride are stable against heat. This is preferable.

[0228] Like the insulator 224, the insulator 250 is made of an insulator that releases oxygen when heated. It is preferable to form the insulating material 250 as an insulating material from which oxygen is released by heating. By providing it in contact with the upper surface of the oxide 230c, the channel forming region of the oxide 230b In addition, the insulator 250 can effectively supply oxygen to the insulator 224. It is preferable that the concentration of impurities such as water or hydrogen is reduced. , preferably 1 nm or more and 20 nm or less.

[0229] A metal oxide may be provided between the insulator 250 and the conductor 260. The material preferably suppresses oxygen diffusion from the insulator 250 to the conductor 260. By providing a metal oxide that suppresses the diffusion of oxygen from the insulator 250 to the conductor 260, the diffusion of oxygen from the insulator 250 to the conductor 260 can be suppressed. In other words, the decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. In addition, oxidation of the conductor 260 due to oxygen in the insulator 250 can be suppressed.

[0230] The metal oxide may also function as a part of the gate insulator. Therefore, when silicon oxide or silicon oxynitride is used for the insulator 250, the metal oxide It is preferable to use a metal oxide, which is a high-k material with a high relative dielectric constant, as the oxide. By making the base insulator have a laminated structure of the insulator 250 and the metal oxide, the base insulator is stable against heat. Therefore, the physical properties of the gate insulator can be improved. It is possible to reduce the gate potential applied during transistor operation while maintaining the film thickness. In addition, it is possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator. do.

[0231] Specifically, hafnium, aluminum, gallium, yttrium, zirconium, tantalum, tin, titanium, tantalum, nickel, germanium, magnesium, etc. The metal oxide may contain one or more metals selected from the following: Aluminum oxide, an insulator containing oxides of either or both of aluminum and hafnium Aluminum, hafnium oxide, oxides containing aluminum and hafnium (hafnium oxide) It is preferable to use a material such as a laminate.

[0232] Alternatively, the metal oxide may function as a part of the gate. In the above, it is preferable to provide a conductive material containing oxygen on the channel formation region side. By providing the conductive material on the channel formation region side, oxygen released from the conductive material forms a channel. This makes it easier for the area to be supplied.

[0233] In particular, the metal oxide in which the channel is formed is used as a conductor that functions as a gate. It is preferable to use a conductive material containing the metal element and oxygen. Conductive materials containing silicon and nitrogen may also be used. Indium tin oxide, tungsten oxide, etc. Indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, titanium oxide Indium oxide containing tungsten, indium tin oxide containing titanium oxide, indium zinc oxide Indium tin oxide doped with silicon may also be used. The use of such a material allows the channel to be formed. In some cases, hydrogen can be captured from the metal oxide that is formed. It may be possible to capture hydrogen that is mixed in through insulators, etc.

[0234] Although the conductor 260 is shown as having a two-layer structure in FIG. 22A, it may have a single layer structure or a three-layer structure. It may have a laminated structure of more than one layer.

[0235] The conductor 260a is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, or a nitrogen oxide molecule. (N2O, NO, NO2, etc.), conductive material with the function of suppressing the diffusion of impurities such as copper atoms It is preferable to use a material containing a small amount of oxygen (e.g., oxygen atoms, oxygen molecules, etc.). It is preferable to use a conductive material having a function of suppressing the diffusion of at least one of the above-mentioned elements.

[0236] In addition, the conductor 260a has a function of suppressing the diffusion of oxygen, so that the insulator 250 The oxygen contained therein can suppress the conductor 260b from being oxidized and the conductivity from decreasing. Examples of conductive materials that have the function of suppressing oxygen diffusion include tantalum, nitride, and the like. It is preferable to use tantalum chloride, ruthenium, ruthenium oxide, or the like.

[0237] The conductor 260b is a conductive material mainly composed of tungsten, copper, or aluminum. In addition, since the conductor 260 also functions as wiring, It is preferable to use a highly conductive material, such as tungsten, copper, or aluminum. The conductive material 260b may be a laminated material. For example, a laminate of titanium or titanium nitride and the above conductive material may be used.

[0238] <<Metal oxides>> As the oxide 230, it is preferable to use a metal oxide that functions as an oxide semiconductor. Metal oxides applicable to the oxide 230 according to the present invention will be described below.

[0239] The metal oxide preferably contains at least indium or zinc. In addition to these, gallium, yttrium, and zinc are preferably included. It is preferable that the alloy contains boron, titanium, iron, nickel, germanium, etc. nium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum Contains one or more of the following: tungsten, magnesium, etc. Good too.

[0240] Here, the metal oxide is an In-M-Zn oxide having indium, element M and zinc. (Element M is aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, Aluminum, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum cerium, neodymium, hafnium, tantalum, tungsten, or magnesium In particular, the element M is aluminum. Preferably, aluminum, gallium, yttrium, or tin is used.

[0241] In this specification, metal oxides containing nitrogen are also referred to as metal oxides. Metal oxides containing nitrogen are also called metal oxynitrides (MEs). It may also be called tal oxynitride.

[0242] <Transistor 300> The transistor 300 will be described with reference to FIG. A conductor 316 is provided on the gate 311 and functions as a gate insulator. The insulator 315, the semiconductor region 313 consisting of a portion of the semiconductor substrate 311, and the source region The low resistance region 314a functions as a drain region, and the low resistance region 314b functions as a gate electrode. The transistor 300 can be either a p-channel or an n-channel type.

[0243] Here, the transistor 300 shown in FIG. 22B has a semiconductor region 313 in which a channel is formed. The semiconductor region 313 (part of the semiconductor substrate 311) has a convex shape. The surface of the substrate 31 is covered with a conductor 316 via an insulator 315. The transistor 300 may be a semiconductor device. Since it utilizes the protruding portion of the substrate 311, it is also called a FIN type transistor. Even if an insulator is provided in contact with the top of the protrusion and functions as a mask for forming the protrusion, In addition, although the case where a protrusion is formed by processing a part of the semiconductor substrate 311 has been shown here, Alternatively, a semiconductor film having a convex shape may be formed by processing an SOI substrate.

[0244] Note that the transistor 300 shown in FIG. 22B is just an example, and the structure is not limited to this. Appropriate transistors may be used depending on the configuration and driving method.

[0245] <Memory Device 420> Next, a memory device 420 shown in FIG. 21 will be described. Regarding the transistor 200M of the semiconductor memory device 20, the description overlapping with that of the transistor 200 is omitted. do.

[0246] In the memory device 420, the conductor 242a of the transistor 200M is a capacitive element. 292 serves as one of the electrodes, and insulators 272 and 273 serve as dielectrics. The insulator 272 and the insulator 273 are sandwiched between the conductor 242a and the insulator 273, and the conductor 242a is overlapped with the insulator 272 and the insulator 273. The conductor 290 is provided as shown in FIG. 2 and functions as the other electrode of the capacitor 292. 0 is used as the other electrode of the capacitance element 292 of the adjacent memory device 420. Alternatively, the conductor 290 may be a conductor 290 of an adjacent memory device 420. may be electrically connected to

[0247] The conductor 290 is disposed on the upper surface of the conductor 242a with the insulators 272 and 273 sandwiched therebetween. In this case, the capacitance element 292 is disposed on the side of the conductor 242a. Since a capacitance larger than the capacitance obtained by the overlapping area of ​​a and the conductor 290 can be obtained, I wish.

[0248] The conductor 424 is electrically connected to the conductor 242b and is connected to the lower layer via the conductor 205. 424.

[0249] The dielectric of the capacitance element 292 may be silicon nitride, silicon oxynitride, or aluminum oxide. Also, these materials can be laminated to form a When the dielectric of the capacitance element 292 has a laminated structure, aluminum oxide and nitride A lamination of hafnium oxide and silicon oxide or a lamination of hafnium oxide and silicon oxide can be used. For example, silicon nitride is stacked on aluminum oxide. Alternatively, aluminum oxide may be laminated on silicon nitride.

[0250] In addition, zirconium oxide having a higher dielectric constant than the above materials is used as the dielectric of the capacitance element 292. Zirconium oxide may be used as a single layer for the dielectric of the capacitance element 292. For example, zirconium oxide and aluminum oxide may be used as a part of a laminate. The dielectric of the capacitance element 292 may be a three-layer laminate. In a preferred embodiment, zirconium oxide is used for the first layer and the third layer. A second layer in between may be aluminum oxide.

[0251] By using zirconium oxide having a high dielectric constant as the dielectric of the capacitance element 292, The area that the capacitance element 292 occupies in the memory device 420 can be reduced. This is preferable because it can reduce the area required for the device 420 and improve the bit cost.

[0252] In addition, the conductor 290 includes the conductor 205, the conductor 242, the conductor 260, and the conductor 42. Materials that can be used for 4, etc. can be used.

[0253] In this embodiment, the transistor 200M and the capacitor element 200B are sandwiched between the conductor 424. In this example, the pair of transistors 200M and 92 are arranged symmetrically. By disposing the capacitance element 292, a conductor electrically connected to the transistor 200M is 424, thereby reducing the area required for the memory device 420. This is preferable because it allows for an improvement in bit cost.

[0254] When the insulator 241 is provided on the side of the conductor 424, the conductor 424 is It is connected to at least a portion of the upper surface of 42b.

[0255] The conductor 424 and the conductor 205 are used to form a transistor in the memory unit 470. The master 200T and the memory device 420 can be electrically connected.

[0256] <Modification 1 of memory device 420> Next, referring to FIG. 23B, a memory device 420 will be described. The memory device 420A includes a transistor 200M and a transistor 200C. The capacitance element 292A is a transistor. It is located below the 200M turbine.

[0257] In the memory device 420A, the conductor 242a is formed by the oxide 243a, the oxide 230b, The oxide 230a, the insulator 224, and the insulator 222 are disposed in an opening therein. The bottom of the opening is electrically connected to the conductor 205. The conductor 205 is electrically connected to the capacitive element 292A. Connect to the target.

[0258] The capacitance element 292A includes a conductor 294 that functions as one of the electrodes and a dielectric The conductor 297 has an insulator 295 that serves as the other electrode and a conductor 297 that serves as the other electrode. The conductor 297 overlaps with the conductor 294 with an insulator 295 sandwiched therebetween. 5 and electrically connected.

[0259] The conductor 294 is disposed at the bottom of an opening formed in an insulator 298 disposed on an insulator 296. The insulator 295 is provided on the front and rear sides of the conductor 294 so as to cover the insulator 298 and the conductor 294. The conductor 297 is provided so as to be embedded in a recess of the insulator 295. can be done.

[0260] In addition, a conductor 299 is provided so as to be embedded in the insulator 296. 9 electrically connects to the conductor 294. The conductor 299 electrically connects to the adjacent memory device 42. 10A conductor 294.

[0261] The conductor 297 is disposed on the upper surface of the conductor 294 and the lower surface of the conductor 294 with the insulator 295 interposed therebetween. At this time, the capacitance element 292A is formed by overlapping the conductor 294 and the conductor 297. This is preferred because it provides a larger capacity than would be obtained with a smaller area.

[0262] The insulator 295 that functions as a dielectric of the capacitance element 292A may be silicon nitride, oxynitride, or the like. Silicon oxide, aluminum oxide, and hafnium oxide can be used. In the case where the insulator 295 has a layered structure, the oxide The layered structure of aluminum nitride and silicon nitride, and the layered structure of hafnium oxide and silicon oxide are used. Here, the top and bottom of the stack is not limited. For example, a nitride layer can be stacked on an aluminum oxide layer. Silicon may be laminated, or aluminum oxide may be laminated on silicon nitride. stomach.

[0263] In addition, zirconium oxide, which has a higher dielectric constant than the above materials, is used as the insulator 295. The insulator 295 may be a single layer of zirconium oxide or a multilayer. For example, a laminate of zirconium oxide and aluminum oxide may be used. Alternatively, the insulator 295 may be a three-layer laminate, with the first layer and the third layer being zirconium oxide is used for the first layer and aluminum oxide is used for the second layer between the first layer and the third layer. may also be used.

[0264] By using zirconium oxide having a high dielectric constant as the insulator 295, the capacitance element 2 92A can reduce the area occupied by the memory device 420A. This is preferable because it reduces the area required for 420A and improves the bit cost.

[0265] In addition, the conductor 297, the conductor 294, and the conductor 299 include the conductor 205, the conductor The material that can be used for the conductor 242, the conductor 260, the conductor 424, etc. can be used. Cut.

[0266] The insulator 298 may include the insulator 214, the insulator 216, the insulator 224, and the insulator Any material that can be used for the body 280, etc. can be used.

[0267] <Modification 2 of memory device 420> Next, referring to FIG. 23C, a memory device 420 will be described. The memory device 420B includes a transistor 200M and a transistor 200C. The capacitance element 292B is a transistor. It is located above turbine 200M.

[0268] The capacitance element 292B includes a conductor 276 that functions as one of the electrodes and a dielectric The conductor 278 has an insulator 277 that serves as the other electrode and a conductor 278 that serves as the other electrode. The conductor 276 overlaps with an insulator 277 sandwiched therebetween.

[0269] An insulator 275 is provided on the insulator 282, and a conductor 276 is provided on the insulator 275, the insulator 2 82, the insulator 280, the insulator 273, and the bottom of the opening formed in the insulator 272; The insulator 277 is provided so as to cover the insulator 282 and the conductor 276. In addition, the conductor 278 overlaps with the conductor 276 in the recess of the insulator 277. At least a part of the insulating material 275 is provided on the insulating material 277. The conductor 278 is connected to the capacitance element 292B of the adjacent memory device 420B. Alternatively, the conductor 278 may be used as the other pole of the adjacent memory device 420. It may be electrically connected to the conductor 278 of B.

[0270] The conductor 278 is disposed on the upper surface of the conductor 276 and the lower surface of the conductor 276 with the insulator 277 interposed therebetween. At this time, the capacitive element 292B is formed by overlapping the conductor 276 and the conductor 278. This is preferred because it provides a larger capacity than would be obtained with a smaller area.

[0271] In addition, an insulator 279 may be provided so as to fill the recess of the conductor 278 .

[0272] The insulator 277 functioning as the dielectric of the capacitance element 292B may be silicon nitride, oxynitride, or the like. Silicon oxide, aluminum oxide, and hafnium oxide can be used. In the case where the insulator 277 has a laminated structure, the oxide The layered structure of aluminum nitride and silicon nitride, and the layered structure of hafnium oxide and silicon oxide are used. Here, the top and bottom of the stack is not limited. For example, a nitride layer can be stacked on an aluminum oxide layer. Silicon may be laminated, or aluminum oxide may be laminated on silicon nitride. stomach.

[0273] In addition, zirconium oxide, which has a higher dielectric constant than the above materials, is used as the insulator 277. The insulator 277 may be a single layer of zirconium oxide or a laminate of zirconium oxide. For example, a laminate of zirconium oxide and aluminum oxide may be used. Alternatively, the insulator 277 may be a three-layer laminate, with the first layer and the third layer being zirconium oxide is used for the first layer and aluminum oxide is used for the second layer between the first layer and the third layer. may also be used.

[0274] By using zirconium oxide having a high dielectric constant as the insulator 277, the capacitance element 2 92B can reduce the area occupied by the memory device 420B. This is preferable because it reduces the area required for 420B and improves the bit cost.

[0275] In addition, the conductor 276 and the conductor 278 include the conductor 205, the conductor 242, and the conductor Any material that can be used for the body 260, the conductor 424, etc. can be used.

[0276] In addition, the insulators 275 and 279 may include the insulators 214, 216, and Any material that can be used for the body 224, the insulator 280, etc. can be used.

[0277] <Connection between memory device 420 and transistor 200T> In the region 422 surrounded by the dashed line in FIG. 24 and electrically connected to the gate of the transistor 200T via the conductor 205. However, the present embodiment is not limited to this.

[0278] FIG. 24 illustrates a memory device 420 including conductors 424, 205, 246b, and via a conductor 240b as one of the source and drain of a transistor 200T. 2 shows an example of electrically connecting to a conductor 242b that functions as a

[0279] In this way, the memory device 420 is configured according to the function of the circuit of the transistor layer 413. and the method of connecting transistor 200T can be determined.

[0280] FIG. 25 illustrates a memory unit 470 including a transistor layer 41 having a transistor 200T. 3 and the fourth memory device layer 415 (memory device layers 415_1 to 415_2). 4 shows an example having a layer 415_4).

[0281] The memory device layers 415_1 to 415_4 each include a plurality of memory The device 420 is also included.

[0282] The memory device 420 is connected to different memory devices via electrical conductors 424 and electrical conductors 205. The memory device 420 in the device layer 415 and the transistor layer 413 include a transistor Electrically connect to transistor 200T.

[0283] The memory unit 470 includes an insulator 211, an insulator 212, an insulator 214, an insulator 287, and an insulator 289. , and is sealed by insulator 282, insulator 283, and insulator 284. An insulator 274 is provided around the periphery. In addition, the insulators 274, 284, and 283 A conductor 430 is provided in the insulator 211 and is electrically connected to the element layer 411 .

[0284] An insulator 280 is provided inside the sealing structure. The insulator 280 is heated. The insulator 280 has a function of releasing oxygen, or has an excess oxygen region.

[0285] The insulators 211, 283, and 284 have blocking properties against hydrogen. Insulators 214, 282, and 283 are preferably made of a material having high elasticity. The insulator 287 is preferably a material having a function of capturing hydrogen or fixing hydrogen. It is appropriate.

[0286] For example, the material having a high blocking property against hydrogen is silicon nitride, Silicon oxide nitride, etc. can also be used. Materials that have this function include aluminum oxide, hafnium oxide, and aluminum and Examples include oxides containing hafnium (hafnium aluminate).

[0287] In this specification, the term "barrier property" refers to the function of suppressing the diffusion of a corresponding substance (permeability). Or, the corresponding substance is captured and fixed (gettering). This function is also called "check".

[0288] In addition, the insulators 211, 212, 214, 287, 282, The crystal structure of the material used for the insulator 283 and the insulator 284 is not particularly limited. For example, the hydrogen trapping or hydrogen fixation may be performed by using a structure having amorphous or crystalline properties. As a material having an adhesive function, an amorphous aluminum oxide film is preferably used. Amorphous aluminum oxide has a higher hydrogen trapping capacity and The amount of adhesion may be large.

[0289] Here, the excess oxygen in the insulator 280 is converted to hydrogen in the oxide semiconductor in contact with the insulator 280. The following model for diffusion can be considered:

[0290] Hydrogen present in the oxide semiconductor is absorbed by other The diffusion of hydrogen occurs when excess oxygen in the insulator 280 is absorbed by the oxide semiconductor. It reacts with hydrogen to form an OH bond, and the hydrogen diffuses through the insulator 280. Hydrogen atoms are trapped in materials that have the ability to capture or fix hydrogen (typically insulators). When the hydrogen atom reaches the insulator 282, it reacts with an atom in the insulator 282 (e.g., a metal atom). The oxygen atoms react with the OH bonds and are captured or fixed in the insulator 282. It is assumed that the oxygen atoms of the excess oxygen remain in the insulator 280 as excess oxygen. In other words, the excess oxygen in the insulator 280 plays a bridging role in the diffusion of the hydrogen. High probability.

[0291] In order to satisfy the above model, the manufacturing process of the semiconductor device is one of the important factors. .

[0292] As an example, an insulator 280 having excess oxygen is formed on an oxide semiconductor, and then an insulating After that, a heat treatment is preferably performed. Specifically, in an atmosphere containing oxygen, an atmosphere containing nitrogen, or a mixture of oxygen and nitrogen, The temperature is 350° C. or higher, preferably 400° C. or higher. The heat treatment time is 1 hour or more. The time is preferably 4 hours or more, and more preferably 8 hours or more.

[0293] By the above heat treatment, hydrogen in the oxide semiconductor is converted into the insulators 280, 282, and and the insulator 287. In addition, the absolute amount of hydrogen present in the vicinity of the oxide semiconductor can be reduced.

[0294] After the heat treatment, the insulator 283 and the insulator 284 are formed. The insulator 284 is a material having a high blocking property against hydrogen. The hydrogen diffused outward or present on the outside is then transferred to the inside, specifically, the oxide semiconductor. It is possible to prevent the air from penetrating into the body or the insulator 280 side.

[0295] Regarding the above heat treatment, the following is performed after the insulator 282 is formed: For example, after the formation of the transistor layer 413 or after the memory After the formation of the re-device layer 415_1 to the memory device layer 415_3, the above-mentioned heating In addition, when hydrogen is diffused outward by the above heat treatment, Hydrogen is diffused upward or laterally into the transistor layer 413. Similarly, the memory device layer In the case where heat treatment is performed after forming the memory device layers 415_1 to 415_3, water The elements are diffused upwards or laterally.

[0296] In the above-mentioned manufacturing process, the insulator 211 and the insulator 283 are bonded to each other. Thus, the above-mentioned sealing structure is formed.

[0297] As described above, the hydrogen concentration is reduced by using the above structure and the above manufacturing process. Therefore, a semiconductor device using an oxide semiconductor having good reliability can be provided. According to one embodiment of the present invention, a semiconductor device having good electrical characteristics can be provided. It is possible to provide a semiconductor device having the above structure.

[0298] 26A to 26C are diagrams showing an example in which the arrangement of the conductors 424 is different from that in FIG. FIG. 26A shows a layout diagram of the memory device 420 as viewed from above, and FIG. 26B shows 26A is a cross-sectional view of a portion indicated by a dashed line A1-A2 in FIG. 26A. FIG. 26C is a cross-sectional view of a portion indicated by a dashed line A1-A2 in FIG. 26A is a cross-sectional view of a portion indicated by a dashed line along B1-B2. For clarity, the conductor 205 is omitted in the illustration. has an overlapping area with conductor 260 and conductor 424.

[0299] As shown in FIG. 26A, the opening in which the conductor 424 is provided, i.e., the conductor 424, is The oxide 230a and the oxide 230b are not only overlapped with the oxide 230a, but also with the oxide 230b. In FIG. 26A, the conductor 424 is disposed on the outside of the oxide 230b. 1, the oxide 230a and the oxide 230b are provided so as to extend to the B2 side. The embodiment is not limited thereto. The conductor 424 is made of the oxide 230a and the oxide 230 b may be provided so as to protrude to the B1 side, or may be provided so as to protrude to both the B1 side and the B2 side. The sensor may be provided as follows.

[0300] 26B and 26C show memory device layer 415_p-1 and memory device layer 415_p-2. 4 shows an example in which a layer 415_p is stacked (p is a natural number between 2 and n). The memory device 420 of 415_p-1 includes a conductor 424 and a conductor 205. The memory device layer 415_p is electrically connected to the memory device 420 through the .

[0301] In FIG. 26B, in the memory device layer 415_p-1, the conductor 424 is The conductor 242 of the memory device layer 415_p-1 and the conductor 242 of the memory device layer 415_p 05. Here, the conductor 424 is connected to the conductor 242 and the oxide 243. , oxide 230b, and the memory device layer 415_p on the outer side of the B2 side of the oxide 230a. It is also connected to the -1 conductor 205.

[0302] In FIG. 26C, conductor 424 is made up of conductor 242, oxide 243, oxide 230b, and The oxide 230a is formed along the B2 side of the insulator 280, the insulator 273, the insulator 272, the insulator 224, and the opening formed in the insulator 222 are connected to the conductor 205. Here, the conductor 424 is electrically connected to the conductor 242 and the oxide 24 3, an example in which the oxide 230b and the oxide 230a are provided along the B2 side of the oxide 230a is shown in FIG. In FIG. 6B, the conductor 242, the oxide 243, the oxide 230b, and the oxide Between the object 230a, the insulator 224, and the B2 side of the insulator 222 and the conductor 424, , an insulator 241 may be formed.

[0303] By providing the conductor 424 in an area that does not overlap with the conductor 242, etc., 420 is electrically connected to the memory device 420 provided in the different memory device layer 415. The memory device 420 is provided in the transistor layer 413. The transistor 200T can also be electrically connected to the gate electrode 200G.

[0304] In addition, when the conductor 424 is used as a bit line, the conductor 424 does not overlap with the conductor 242, etc. By providing the bit lines in the B1-B2 direction in the area where the bit lines are not present, As shown in FIG. 26A, the distance between the conductor 4 on the conductor 242 can be increased. The distance between the oxide 230a and the insulator 224 is d1. The distance between the conductors 424 located in the openings formed in the insulator 222 is d2. The distance d2 is greater than d1. By setting the distance d2, the parasitic capacitance of the conductor 424 is reduced compared to the case where the distance d2 is set to d2. By reducing the parasitic capacitance of the conductor 424, the capacitance required for the capacitor 292 can be reduced. This is preferable because it can reduce

[0305] In the memory device 420, it functions as a common bit line for two memory cells. A conductor 424 is provided. The dielectric constant of the dielectric material used for the capacitance and the parasitic capacitance between the bit lines are By appropriately adjusting the channel length, the cell size of each memory cell can be reduced. Estimated cell size of memory cell when the device is 30 nm (also called the 30 nm node) We will explain the estimation of bit density and bit cost. 27A to 27D, the conductor 205 is not shown in order to facilitate understanding of the figures. In the case where the conductor 205 is provided, the conductor 205 includes the conductor 260 and the conductor 424.

[0306] FIG. 27A shows a capacitor dielectric layer of 10 nm thick hafnium oxide with 1 nm thick SiO2. The silicon oxide layers are stacked in order to form the conductors 24 of the memory cells of the memory device 420. 2, a slit is provided between the oxide 243, the oxide 230a, and the oxide 230b. conductor 242 and conductor 424 functioning as a bit line so as to overlap the slit. The memory cell 432 thus obtained is called cell A.

[0307] The cell size in cell A is 45.25F 2 It is.

[0308] FIG. 27B shows a capacitor with a zirconium oxide layer and an aluminum oxide layer on top of it as a dielectric. A first zirconium oxide layer is laminated on top of the first zirconium oxide layer, and the memory device 420 has The conductor 242, oxide 243, oxide 230a, and oxide 230b of each memory cell A slit is provided between the conductor 242 and the bit line so as to overlap the slit. The memory cell 4 thus obtained is shown in FIG. Let's call 33 cell B.

[0309] Cell B has a higher dielectric constant than cell A, which reduces the area of ​​the capacitor. Therefore, the cell size of cell B can be reduced compared to cell A. The cell size is 25.53F. 2 It is.

[0310] Cell A and cell B are the memory cells shown in FIG. 21, FIG. 23A to FIG. 23C, and FIG. The memory device 420, the memory device 420A, or the memory device 420B Supports resale.

[0311] FIG. 27C shows a capacitor having a first zirconium oxide layer and an aluminum oxide layer thereon as a dielectric. A second zirconium oxide layer is laminated on the first zirconium oxide layer, and the conductive layer of the memory device 420 is Each memory cell shares a body 242, an oxide 243, an oxide 230a, and an oxide 230b. The bead is arranged so as to overlap a portion of the conductor 242 and an outer portion of the conductor 242. In this example, a conductor 424 is provided to function as a bit line. Recell 434 is referred to as cell C.

[0312] The spacing of the conductors 424 in cell C is smaller than that above the oxide 230 compared to above the conductors 242. Therefore, the parasitic capacitance of the conductor 424 can be reduced. In addition, the conductor 242, the oxide 243, the oxide 230a, and The oxide 230b has no slits. In comparison, the cell size can be reduced. The cell size in cell C is 17.20F. 2 Yes do.

[0313] FIG. 27D shows an example in which the conductor 205 and the insulator 216 are not provided in the cell C. Such a memory cell 435 is referred to as cell D.

[0314] By not providing the conductor 205 and the insulator 216 in the cell D, the memory device 4 Therefore, the memory device 20 having the memory device 420 can be thinned. The layer 415 can be thinned, and a memory unit in which multiple memory device layers 415 are stacked The height of 470 can be reduced. Conductor 424 and conductor 205 are considered as bit lines. When this is done, the bit lines can be shortened in the memory unit 470. This reduces the parasitic loading of the bit lines, further reducing the parasitic capacitance of conductor 424. The area of ​​the capacitor can be reduced. No slits are provided in the oxide 230b and the oxide 230a. The cell size can be reduced compared to cells B and C. Cell size in cell D is 15.12F 2 It is.

[0315] Cells C and D are included in the memory device 420 shown in FIGS. 26A to 26C. It corresponds to a memory cell.

[0316] Here, for cells A to D and cell E which has been multi-valued in cell D, Density, and bit cost C bThe estimates were also Compared to the bit density and bit cost estimates for currently available DRAMs .

[0317] The bit cost C in the semiconductor device according to one embodiment of the present invention b was estimated using Eq. .

[0318]

number

[0319] where n is the number of stacked memory device layers, P c The common portion is mainly the element layer 411. Number of turns, P s The memory device layer 415 and the transistor layer 413 are The number of patternings, D d is the bit density of the DRAM, D 3d is the memory device layer 415 The bit density of one layer of d indicates the number of patterning times for the DRAM. d In , including the increment due to scaling.

[0320] Table 1 shows the expected bit densities of commercially available DRAMs and the semiconductor The bit density of the commercially available DRAM is estimated based on the process no. The thicknesses of the semiconductor device according to one embodiment of the present invention are two types: 18 nm and 1X nm. The process node is set to 30 nm, and the number of stacked memory device layers in Cell A to Cell E is set to 5. Bit density estimates were performed for 1, 10, and 20 layers.

[0321] [Table 1]

[0322] Table 2 shows the bit cost of the semiconductor device according to one embodiment of the present invention based on the bit cost of commercially available DRAM. The results of estimating the relative bit cost are shown below. The DRAM used had a 1X nm data rate. The thickness is 30 nm, and the number of stacked memory device layers in cells A to D is 5 layers, 10 layers, and , and 20 layers were estimated.

[0323] [Table 2]

[0324] Table 3 also shows bit density estimates for commercially available DRAMs that are different from those in Table 1. 1 shows an expected value of the bit density of the semiconductor device according to one embodiment of the present invention, and The process node of commercially available DRAM is 1X nm. The process node of the semiconductor device is set to 30 nm, and the memory device layer 41 in the cell C is 5 and the number of layers of the transistor layer 413 is 5 layers, 10 layers, and 10 layers and 4 bit / The estimation was made assuming that the cell was multi-valued. The relative bit cost of the semiconductor device according to one embodiment of the present invention was estimated from the bit cost of the AM. Similar to the bit density, the process node of the semiconductor device according to one embodiment of the present invention is 30 nm, and the number of stacked layers of the memory device layer 415 and the transistor layer 413 in the cell C is The estimated values ​​are 5 layers, 10 layers, and 10 layers with 4 bits / cell multi-value. The following was carried out.

[0325] [Table 3]

[0326] Although there is a limit to miniaturization of DRAM, the semiconductor device according to one embodiment of the present invention is, in principle, By achieving the impossible multi-level processing, we can achieve high-resolution images that exceed DRAM without reaching the limits of miniaturization. It is possible to achieve high data density, low cost, and extremely low power consumption. Approximately 1 / 60,000 of the AM (DRAM: once every 64 ms, semiconductor device of one embodiment of the present invention: once Therefore, even if the memory capacity increases significantly, it is necessary to use memory that can save power. can be done.

[0327] The structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. It is possible.

[0328] (Embodiment 3) In this embodiment, the present invention can be applied to the OS transistor described in the above embodiment. Cloud-Aligned Composite Silicon-Oxide (CAC-OS) Oxide Semiconductor), and CAAC-OS (c-axis A The composition of the ligned Crystal Oxide Semiconductor I will explain it below.

[0329] <Metal oxide composition> CAC-OS or CAC-metal oxide is a material that has a conductive function in some parts. The material has a function of insulating in part and a function of semiconductor in the whole material. In addition, CAC-OS or CAC-metal oxide is used as the active layer of a transistor. When used in a layer, the conductive function is to allow the flow of electrons (or holes) that serve as carriers. The insulating function is to prevent the flow of electrons, which act as carriers. By making the function of the material and the function of the material complement each other, the material can be switched (On / Off). ff function) to CAC-OS or CAC-metal oxide. In CAC-OS or CAC-metal oxide, By separating the functions, the functionality of both can be maximized.

[0330] In addition, CAC-OS or CAC-metal oxide is a conductive area and an insulating area. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. In addition, the conductive and insulating regions in the material are formed by nanoparticles. The conductive and insulating regions may be separated by different materials. In addition, the conductive area may be observed as a cloud-like connected area with a blurred periphery. This may be the case.

[0331] In addition, in the CAC-OS or CAC-metal oxide, a conductive region and The insulating regions are each 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm. They may be dispersed in the material at sizes of less than one millimeter.

[0332] In addition, CAC-OS or CAC-metal oxide has different band gaps For example, CAC-OS or CAC-metal ox The ide consists of a wide gap component due to the insulating region and a conductive region. In this configuration, when the carrier flows, In addition, carriers mainly flow in the narrow gap component. The component with a gap acts complementary to the component with a wide gap to produce a narrow gap. Carriers also flow to the wide gap component in conjunction with the component with a large gap. CAC-OS or CAC-metal oxide is used as the channel formation region of the transistor. When used in a transistor, it has a high current driving force in the on-state, i.e., a large on-current. , and high field effect mobility can be obtained.

[0333] That is, CAC-OS or CAC-metal oxide is a matrix composite. matrix composite, or metal matrix composite It can also be called a composite matrix.

[0334] <Metal oxide structure> Oxide semiconductors can be divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, for example, CAAC-OS (c-axis all-crystalline oxide semiconductor) igned crystalline oxide semiconductor), Crystalline oxide semiconductor, nc-OS (nanocrystalline oxide semiconductor) iconductor), pseudo-amorphous oxide semiconductor (a-like OS:amorph crystalline-like oxide semiconductors and amorphous oxide semiconductors There are bodies, etc.

[0335] In addition, when focusing on the crystal structure, oxide semiconductors may be classified differently from the above. Here, the classification of crystal structures in oxide semiconductors will be explained with reference to FIG. FIG. 28A shows an oxide semiconductor, typically IGZO (containing In, Ga, and Zn). FIG. 1 is a diagram for explaining the classification of crystal structures of metal oxides.

[0336] As shown in Figure 28A, IGZO is roughly divided into Amorphous and Crystal. Amorphous is classified into three types: alline and crystal. , completely amorphous. Crystallin e includes CAAC (c-axis aligned crystalline), n c(nanocrystalline), and CAC(Cloud-Aligned Also, in Crystal, there are single crystal Includes crystalline, crystalline, and poly crystal.

[0337] The structure within the bold frame in FIG. 28A is a new crystalline phase This structure is on the boundary between Amorphous and Crystal. In other words, it is in the energetically unstable Amorphous and Crystal regions. In other words, it is a structure that is completely different from a line.

[0338] The crystal structure of the film or substrate was determined by X-ray diffraction (XRD). The evaluation can be performed using the ion image. XRD of IGZO (also called crystalline IGZO) with a crystal structure classified as line The spectra are shown in Figures 28B and 28C. Figure 28B shows the quartz glass and Figure 28C shows the crystal. The XRD spectrum of crystalline IGZO shown in FIG. The composition is In:Ga:Zn=4:2:3 [atomic ratio]. The IGZO has a thickness of 500 nm.

[0339] As shown by the arrows in Figure 28B, the peaks in the XRD spectrum of quartz glass are almost symmetrical. On the other hand, as shown by the arrow in Figure 28C, crystalline IGZO has a peak in the XRD spectrum. The asymmetric peaks in the XRD spectrum clearly indicate the presence of crystals. In other words, if the peaks in the XRD spectrum are not symmetrical, Amorph It cannot be said to be ous.

[0340] CAAC-OS has a c-axis orientation and multiple nanocrystals are connected in the ab-plane direction. The nanocrystals are connected together to form a distorted crystal structure. In a region, a lattice arrangement is formed between a region having a uniform lattice arrangement and another region having a uniform lattice arrangement. This refers to the point where the direction of the

[0341] Nanocrystals are basically hexagonal, but are not limited to regular hexagons and may have non-regular hexagonal shapes. In addition, the distortion may have lattice arrangements such as pentagons and heptagons. In addition, in the CAAC-OS, clear grain boundaries (grain bows) were observed even in the vicinity of the strain. In other words, the crystal grains are distorted due to the distortion of the lattice arrangement. This is because the CAAC-OS has a lattice structure in the ab-plane direction. The oxygen atoms are not densely packed, and the bond distance between atoms is shortened by the substitution of metal elements. This is because the material can tolerate distortion by changing its shape. The crystal structure in which grain boundaries are observed is called polycrystalline. The grain boundaries act as recombination centers, where carriers are captured and This is highly likely to cause a decrease in the on-state current or a decrease in the field effect mobility of the transistor. In contrast, the CAAC-OS, which does not have clear grain boundaries, is a material suitable for use in the semiconductor layer of a transistor. CAAC-OS is a crystalline oxide with a Z crystal structure. For example, In-Zn oxide and In-Ga-Zn oxide are preferred. is preferable because it can suppress the generation of crystal grain boundaries more effectively than In oxide.

[0342] In addition, the CAAC-OS has a layer containing indium and oxygen (hereinafter, the In layer) and an elemental A layered crystal consisting of layers containing element M, zinc, and oxygen (hereinafter referred to as the (M,Zn) layer). Indium and element M tend to have a layered structure. When the element M in the (M,Zn) layer is replaced with indium, (In,M,Zn ) layer. Also, when the indium in the In layer is replaced with the element M, (In, M) layer.

[0343] CAAC-OS is a highly crystalline oxide semiconductor. Since it is not possible to confirm the grain boundaries, the decrease in electron mobility caused by the grain boundaries occurs. In addition, the crystallinity of oxide semiconductors can be easily affected by impurities and defects. Therefore, CAAC-OS is an oxidized material with few impurities and defects (oxygen vacancies, etc.). Therefore, oxide semiconductors with CAAC-OS have stable physical properties. Therefore, oxide semiconductors having CAAC-OS are resistant to heat and have high reliability. In addition, CAAC-OS is designed to withstand the high temperatures (so-called thermal budget) in the manufacturing process. Therefore, when CAAC-OS is used for an OS transistor, This allows for greater freedom.

[0344] nc-OS is a material that is used in microscopic regions (e.g., regions between 1 nm and 10 nm, especially regions between 1 nm and The atomic arrangement has periodicity in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be classified as a-like OS or amorphous oxide semiconductor. Sometimes it is indistinguishable from the body.

[0345] The a-like OS is an oxide semiconductor that has a structure between the nc-OS and the amorphous oxide semiconductor. A-like OS has voids or low density areas. e-OS has a lower crystallinity than nc-OS and CAAC-OS.

[0346] The oxide semiconductor has various structures and has different characteristics. The oxide semiconductors in The compound may have two or more of c-OS and CAAC-OS.

[0347] <Transistor Having Oxide Semiconductor> Next, the case where the oxide semiconductor is used for a transistor will be described.

[0348] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility can be obtained. In addition, a highly reliable transistor can be realized.

[0349] In addition, the transistor is preferably formed using an oxide semiconductor with a low carrier concentration. In the case of decreasing the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film is In the present specification and the like, the impurity concentration is low, and the defect level density is low. A low density of defect states is called high purity intrinsic or substantially high purity intrinsic.

[0350] In addition, a highly-purified intrinsic or substantially highly-purified intrinsic oxide semiconductor film has a low density of defect states. Since the density of the trap states is low, the density of the trap states may also be low.

[0351] In addition, the time required for the charge trapped in the trap level of the oxide semiconductor to disappear is Therefore, the trap level density is high. A transistor in which a channel formation region is formed in an oxide semiconductor has unstable electrical characteristics. There may be cases where this occurs.

[0352] Therefore, in order to stabilize the electrical characteristics of a transistor, the impurity concentration in the oxide semiconductor In order to reduce the impurity concentration in the oxide semiconductor, It is preferable to reduce the impurity concentration in the adjacent film. These include alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0353] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0354] When oxide semiconductors contain silicon or carbon, which is one of the group 14 elements, they become oxidized. Defect levels are formed in oxide semiconductors. The concentration of silicon and carbon near the interface with the oxide semiconductor (secondary ion mass spectrometry) (SIMS: Secondary Ion Mass Spectrometry) The concentration that can be obtained is 2 x 10 18 atoms / cm 3 Less than or equal to 2 x 10 17 a toms / cm 3 The following applies.

[0355] In addition, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, the defect level is reduced. Therefore, alkali metals or alkaline earth metals A transistor using an oxide semiconductor containing such an element tends to be normally-on. Therefore, it is possible to reduce the concentration of alkali metals or alkaline earth metals in the oxide semiconductor. Specifically, it is preferable to use an alkali metal or The concentration of alkaline earth metals is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 To the following:

[0356] In addition, when nitrogen is contained in an oxide semiconductor, electrons that serve as carriers are generated, and As a result, the nitrogen-containing oxide semiconductor is easily converted to n-type. Therefore, the transistor used in the oxide semiconductor In this case, it is preferable that the nitrogen content is reduced as much as possible. For example, the nitrogen content in the oxide semiconductor is The concentration is 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3Less than or equal to 1×10 18 atoms / cm 3 Below, More preferably 5×10 17 atoms / cm 3 The following applies.

[0357] In addition, hydrogen contained in oxide semiconductors reacts with oxygen that bonds with metal atoms to form water. When hydrogen enters the oxygen vacancy, the carrier, In some cases, hydrogen atoms are formed by bonding with oxygen atoms that bond with metal atoms. Therefore, it is necessary to use an oxide semiconductor that contains hydrogen. Therefore, the hydrogen in the oxide semiconductor tends to cause a transistor to be normally on. It is preferable that the Si content in the oxide semiconductor is as low as possible. The hydrogen concentration obtained by MS is 1×10 20 atoms / cm 3 Less than 1x, preferably 10 19 atoms / cm 3 less than 5×10 18 atoms / cm 3 less than , and more preferably 1×10 18 atoms / cm 3 Less than.

[0358] By using an oxide semiconductor in which impurities are sufficiently reduced for a channel formation region of a transistor, This makes it possible to impart stable electrical characteristics.

[0359] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0360] (Embodiment 4) In this embodiment, the silicon substrate 50 in the semiconductor device 10 described in the first embodiment is A control logic circuit 61, a row driver circuit 62, a column driver circuit 63 and an output The circuit 64 will now be described.

[0361] FIG. 29 is a block diagram showing a configuration example of a semiconductor device that functions as a memory device. The semiconductor device 10E includes a peripheral circuit 80 and a memory cell array 70. includes a control logic circuit 61, a row driving circuit 62, a column driving circuit 63, and an output circuit 64. Yes.

[0362] The memory cell array 70 includes a plurality of memory cells 42. The column driver circuit 63 includes a column decoder 71 and a word line driver circuit 72. The circuit has a pre-transistor 81, a pre-charge circuit 82, an amplifier circuit 83, and a write circuit 84. The charge circuit 82 connects the global bit line GBL or the local bit line LBL. The amplifier circuit 83 has a function of precharging the global bit line GBL or The function of the memory cell is to amplify the data signal read from the local bit line LBL. The data signal is output to the semiconductor device via an output circuit 64 as a digital data signal RDATA. The signal is output to the outside of the device 10E.

[0363] The semiconductor device 10E is supplied with a low power supply voltage (VSS) from the outside as a power supply voltage, and a peripheral circuit 80 A high power supply voltage (VDD) for the memory cell array 70 and a high power supply voltage (VIL) for the memory cell array 70 are supplied. do.

[0364] The semiconductor device 10E also includes control signals (CE, WE, RE), an address signal ADDR, A data signal WDATA is input from the outside. An address signal ADDR is input to a row decoder 7. 1 and the column decoder 81, and WDATA is input to the write circuit 84.

[0365] The control logic circuit 61 processes input signals (CE, WE, RE) from the outside. The CE generates control signals for the row decoder 71 and the column decoder 81. WE is the write enable signal, RE is the read enable signal, The signals processed by the control logic circuit 61 are not limited to these. Instead, other control signals may be input as necessary. For example, A control signal is input for the purpose of controlling the readout of data signals from specific memory cell addresses. They may be identified as good bits.

[0366] It should be noted that the above-mentioned circuits and signals can be appropriately selected or omitted as necessary.

[0367] Generally, in semiconductor devices such as computers, various memory devices are used depending on the application. Figure 30 shows various storage devices by hierarchy. The lower the storage device, the larger the storage capacity and the higher the recording speed. In Figure 30, the density is calculated by dividing the number of registers by the number of registers. SRAM (Static Random Access Memory) mory), DRAM (Dynamic Random Access Memory) , showing 3D NAND memory.

[0368] The memory embedded as a register in a CPU or other arithmetic processing unit is used to temporarily store the results of calculations. Therefore, the frequency of access from the processor is high. The registers hold the setting information of the processor. It also has functions.

[0369] SRAM is used, for example, for caches. Caches are data held in main memory. It has the function of duplicating and storing part of the information stored in the cache. By duplicating the data, you can increase the speed at which data can be accessed.

[0370] DRAM is used, for example, as main memory. Main memory reads data from storage. DRAM has the function of storing programs and data. The recording density of DRAM is approximately 0.1~0.3Gbit / mm 2 It is.

[0371] 3D NAND memory is used, for example, for storage. Storage is for long-term storage. It has the function of storing necessary data and various programs used by the processing unit. Therefore, storage requires a larger memory capacity and a higher recording density rather than an increased operating speed. The recording density of memory devices used for storage is approximately 0.6 to 6.0 Gbit / m m 2 It is.

[0372] A semiconductor device functioning as a memory device of one embodiment of the present invention has high operating speed and can be used for a long period of time. The semiconductor device according to one embodiment of the present invention is capable of holding data. Suitable as a semiconductor device located in the boundary area 901 including both the hierarchical layer where the in-memory is located In addition, in the semiconductor device of one embodiment of the present invention, As a semiconductor device located in a boundary area 902 including both a tier and a tier in which a storage is located, It can be suitably used.

[0373] (Embodiment 5) This embodiment mode relates to an electronic component incorporating the semiconductor device or the like shown in the above embodiment mode, and An example of an electronic device is shown.

[0374] <Electronic components> First, an example of an electronic component incorporating the semiconductor device 10 or the like will be described with reference to FIGS. 31A and 31B. Explanations will be given.

[0375] FIG. 31A shows electronic component 700 and a substrate (mounting substrate 704) on which electronic component 700 is mounted. The electronic component 700 shown in FIG. The semiconductor device 10 has an element layer 20 laminated on a substrate 70. In order to show the inside of the electronic component 700, some parts are not shown in the figure. The land 712 is electrically connected to an electrode pad 713. The electrode pad 713 is electrically connected to the semiconductor device 10 by a wire 714. The sub-component 700 is mounted on, for example, a printed circuit board 702. The components are then electrically connected to each other on the printed circuit board 702 to form a mounting board 7 04 is completed.

[0376] 31B shows a perspective view of the electronic component 730. The electronic component 730 is a SiP (System in Package) in package) or MCM (Multi Chip Module) The electronic component 730 is mounted on a package substrate 732 (printed circuit board) in the form of an interposer. A semiconductor device 735 and a plurality of semiconductor devices are provided on the interposer 731. A station 10 is provided.

[0377] In the electronic component 730, the semiconductor device 10 is a high bandwidth memory (HBM). The semiconductor device 735 is used as a C Integrated circuits (semiconductor devices) such as PUs, GPUs, and FPGAs can be used.

[0378] The package substrate 732 is a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 731 may be a silicon interposer, a resin interposer, or the like. A resin interposer or the like can be used.

[0379] The interposer 731 has a plurality of wirings and electrically connects a plurality of integrated circuits having different terminal pitches. The wiring has a function of electrically connecting the wiring. The wiring is provided in a single layer or in multiple layers. The interposer 731 supports the integrated circuit provided on the interposer 731 on the package substrate 7 The interposer has a function of electrically connecting to the electrode provided on the interposer. The interposer is sometimes called a "rewiring board" or "intermediate board." 1, a through electrode is provided, and the integrated circuit and the package substrate 732 are electrically connected by the through electrode. In addition, in silicon interposers, TSV ( Through Silicon Via can also be used.

[0380] It is preferable to use a silicon interposer as the interposer 731. Since there is no need to provide active elements in the interposer, it can be manufactured at a lower cost than an integrated circuit. On the other hand, the wiring of the silicon interposer is formed by the semiconductor process. This makes it easy to form fine wiring that is difficult to achieve with a resin interposer.

[0381] In HBM, a large number of wirings must be connected to achieve a wide memory bandwidth. For this reason, the interposer that mounts HBM requires fine, high-density wiring. Therefore, it is recommended to use a silicon interposer for mounting the HBM. is preferred.

[0382] In addition, in SiP and MCM using silicon interposers, the integrated circuit and the interposer The reliability is less likely to decrease due to the difference in the expansion coefficient between the silicon interposers. The silicon interposer has a highly flat surface, so the integrated circuit mounted on the silicon interposer and the silicon Connection failures between interposers are unlikely to occur. In particular, it is possible to mount multiple integrated circuits on an interposer. In a 2.5D package (2.5-dimensional mounting) where the devices are arranged side by side, the silicon interposer It is preferable to use the

[0383] A heat sink (heat dissipation plate) may be provided on top of the electronic component 730. When providing an interposer 731, it is preferable to align the height of the integrated circuits provided on the interposer 731. For example, in the electronic component 730 shown in the present embodiment, the semiconductor device 10 and the semiconductor device 73 It is preferable to align the height of the 5.

[0384] In order to mount the electronic component 730 on another substrate, electrodes 733 are provided on the bottom of the package substrate 732. FIG. 31B shows an example in which the electrode 733 is formed of a solder ball. By providing solder balls in a matrix on the bottom of the package board 732, a BGA (Ball Gauge) l Grid Array) mounting can be realized. In addition, the electrode 733 is formed with a conductive pin. By providing conductive pins in a matrix on the bottom of the package substrate 732, ,PGA (Pin Grid Array) implementation can be realized.

[0385] The electronic component 730 is not limited to BGA and PGA, and may be mounted on other substrates using various mounting methods. For example, SPGA (Staggered Pin Grid Arrangement) ray), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ(Quad Flat J-leaded package) or QFN (Quad Flat Non-leaded package) A mounting method can be used.

[0386] <Electronic equipment> Next, an example of an electronic device including the above electronic components will be described with reference to FIG.

[0387] The robot 7100 is equipped with a light sensor, a microphone, a camera, a speaker, and a display. , various sensors (infrared sensors, ultrasonic sensors, acceleration sensors, piezo sensors, optical sensors, The electronic component 730 includes a processor, etc. For example, the electronic component 700 may be a sensor. It has the function of storing the obtained data.

[0388] The microphone has a function of detecting acoustic signals such as the user's voice and environmental sounds. The speaker also has the function of emitting audio signals such as voice and warning sounds. The bot 7100 analyzes the audio signal input via the microphone and The audio signal can be emitted from the speaker. It is possible to communicate with the user using a microphone and speaker. It is.

[0389] The camera has a function of capturing images of the surroundings of the robot 7100. The robot 7100 has a function of moving using a moving mechanism. It can capture images of the vehicle and analyze them to detect the presence or absence of obstacles when moving around. .

[0390] The flying object 7120 has a propeller, a camera, a battery, etc., and flies autonomously. The electronic component 730 has a function of controlling these peripheral devices.

[0391] For example, image data captured by a camera is stored in the electronic component 700. The robot can analyze image data and detect the presence or absence of obstacles when moving. In addition, the remaining battery charge can be estimated from the change in the battery charge capacity by the electronic component 730. This can be done.

[0392] The cleaning robot 7140 has a display on the top surface and multiple cameras on the sides. The device has a cleaning machine, a brush, operation buttons, various sensors, etc. The cleaning robot 7300 is equipped with tires, a suction port, etc. It can detect dust and suck it up through a suction port provided on the bottom.

[0393] For example, the electronic component 730 analyzes the image captured by the camera and detects obstacles such as walls, furniture, or steps. In addition, image analysis can be used to detect wires and other objects that may be entangled in the brush. If it detects an object that is likely to move, it can stop the brush from rotating.

[0394] The car 7160 has an engine, tires, brakes, steering, a camera, etc. For example, electronic components 730 may provide navigation information, speed, engine status, gear selection status, etc. Optimize the driving conditions of the car 7160 based on data such as the frequency of braking and other factors. For example, image data captured by a camera is stored in the electronic component 700. .

[0395] The electronic component 700 and / or the electronic component 730 may be a TV device 7200 (a television receiver imaging device), smartphone 7210, PC (personal computer) 7220, 723 0, game machine 7240, game machine 7260, etc.

[0396] For example, the electronic component 730 built into the TV device 7200 functions as an image engine. For example, the electronic components 730 can perform functions such as noise reduction, resolution up-conversion, etc. The image processing is performed as follows.

[0397] The smartphone 7210 is an example of a portable information terminal. Includes a microphone, camera, speaker, various sensors, and a display unit. Electronic Components 73 0 controls these peripherals.

[0398] The PC7220 and PC7230 are examples of notebook PCs and desktop PCs, respectively. The C7230 is equipped with a keyboard 7232 and a monitor device 7233, which can be connected wirelessly or by wire. The game machine 7240 is an example of a portable game machine. This is an example of a stationary game machine. The game machine 7260 includes a controller that can be used wirelessly or wired. The controller 7262 is connected to the electronic component 700 and / or the power supply 7262. Sub-parts 730 may also be incorporated.

[0399] This embodiment may be implemented in appropriate combination with the configurations described in other embodiments. is possible.

[0400] (Additional notes regarding the present specification, etc.) The following additional notes will be given regarding the above embodiment and each configuration in the embodiment. .

[0401] The configurations shown in each embodiment may be appropriately combined with the configurations shown in other embodiments or examples. In addition, one embodiment may include a plurality of configurations. Where examples are given, the configuration examples can be combined as appropriate.

[0402] In addition, the contents (or even a part of the contents) described in one embodiment may be used in the embodiment. Another content (or a part of the content) described in the form, and / or one or more other The contents (or a part of the contents) described in the embodiment of the present invention may be applied, combined, or Replacement etc. can be done.

[0403] The contents described in the embodiments are explained in detail with reference to various figures in each embodiment. This refers to the content stated in the specification or using the text in the description.

[0404] In addition, a figure (or a part of it) described in one embodiment may be replaced with another part of the figure. Another figure (or a part of it) described in the embodiment, and / or one or more The figures may be combined with the figures (or a part of them) described in multiple different embodiments. This allows even more figures to be constructed.

[0405] In the present specification and the like, in the block diagrams, components are classified by function and are independent of each other. However, in actual circuits, the components are divided into functional blocks. In some cases, it is difficult to separate the functions into individual circuits, and multiple functions are involved in one circuit, or multiple circuits are involved in a single circuit. Therefore, the blocks in the block diagram may be expressed as The present invention is not limited to the described components, and may be rephrased appropriately depending on the situation.

[0406] In addition, in the drawings, the size, layer thickness, and area are arbitrarily sized for convenience of explanation. The drawings are not necessarily limited to the scale shown. The drawings are merely schematic for the sake of convenience, and are not limited to the shapes or values ​​shown in the drawings. For example, noise may cause signal, voltage, or current variations, or timing errors. This may include variations in signal, voltage, or current due to the

[0407] In addition, the positional relationship of the components shown in the drawings is relative. When describing components with reference to them, the terms "above" and "below" that indicate the positional relationship are used for convenience. The positional relationship of the components is not limited to the contents described in this specification, and may vary depending on the situation. It can be rephrased appropriately depending on the situation.

[0408] In this specification, when describing the connection relationship of a transistor, "the other of the source or drain" (or the first electrode, or the first terminal), The term "second electrode" or "second terminal" is used to refer to the source and drain of a transistor. This is because the drain varies depending on the structure or operating conditions of the transistor. The names of the source and drain of a transistor are source (drain) terminal and source (drain In) electrodes, etc., can be rephrased appropriately depending on the situation.

[0409] In addition, the terms "electrode" and "wiring" used in this specification and the like refer to these components functionally. This is not intended to be limiting. For example, an "electrode" may be used as a part of a "wire." , and vice versa. Furthermore, the terms "electrode" and "wiring" may be used interchangeably to refer to the plural "electrodes" and "wirings." This also includes cases where the wiring is formed integrally.

[0410] In this specification and the like, the terms voltage and potential can be interchanged as appropriate. This is the potential difference from the reference potential. For example, the reference potential is the ground voltage (earth If we use the term "voltage", we can say that the voltage is equivalent to the potential. The ground potential is not necessarily 0V. It is important to note that potential is relative, and depending on the reference potential, The potential applied to wiring etc. may be changed.

[0411] In this specification, a node may be a terminal, a wiring, or the like depending on a circuit configuration, a device structure, or the like. In other words, a terminal, a wiring, a conductive layer, a conductor, an impurity region, etc. Lines and the like can be referred to as nodes.

[0412] In this specification, "A and B are connected" means that A and B are electrically connected. Here, A and B being electrically connected means that A and B are in a mutually exclusive relationship. Objects (switches, transistor elements, diodes, etc.) When there is a connection between A and B, the connection is capable of transmitting electrical signals. If A and B are electrically connected, it is considered that A and B are directly connected. Here, A and B being directly connected means that the object is interposed between them. Instead, electrical signals can be transmitted between A and B via wiring (or electrodes) between A and B. In other words, a direct connection is a connection that can be seen as the same circuit diagram when expressed as an equivalent circuit. This refers to the connection that can be made.

[0413] In this specification, a switch refers to a device that can be in a conductive state (on state) or a non-conductive state (off state). It refers to a device that has the function of controlling whether or not a current flows by switching to a non-operating state. A switch has a function of selecting and switching a path through which a current flows.

[0414] In this specification and the like, the channel length is, for example, the length of a semiconductor the body (or the part of the semiconductor through which current flows when the transistor is on) and the gate The distance between the source and drain in the region where they overlap or where the channel is formed. It means separation.

[0415] In this specification, the channel width refers to, for example, the width of a semiconductor (or a transistor) when it is in an on-state. The region where the gate electrode overlaps with the gate electrode (the part of the semiconductor through which current flows when the semiconductor is in the insulated state), or the channel This refers to the length of the portion where the source and drain face each other in the region where the MOSFET is formed. .

[0416] In this specification, the terms "film" and "layer" are used in some cases or in other situations. For example, the term "conductive layer" can be used interchangeably with the term "conductive layer" In some cases, it may be possible to change the term to "conductive film." Or, for example, to "insulating film." In some cases, the term "insulating layer" may be changed to the term "insulating layer." [Explanation of symbols]

[0417] :BL2: Wiring, SL2: Wiring, SW0: Signal, SW1: Signal, SW2: Signal, T11: Time, T12:Time, T13:Time, T14:Time, T15:Time, T16:Time, T1 7: time, T18: time, T19: time, 10: semiconductor device, 10A: semiconductor device, 10 B: semiconductor device, 10C: semiconductor device, 10E: semiconductor device, 20: element layer, 20_M: Element layer, 20_1: element layer, 30: transistor layer, 30A: transistor layer, 30B: Transistor layer, 31: transistor, 32: transistor, 33: transistor, 34 : transistor, 35: compensation circuit, 36: circuit, 36_pre: circuit, 40: transistor layer, 41_k: transistor layer, 41_1: transistor layer, 41_2: transistor Layer, 42: memory cell, 43: transistor, 44: capacitor, 49: transistor layer , 49_k: transistor layer, 49_1: transistor layer, 50: silicon substrate, 51: Control circuit, 52: switch circuit, 52_1: transistor, 52_2: transistor, 5 3: precharge circuit, 53_1: transistor, 53_3: transistor, 54: pre Charge circuit, 54_1: Transistor, 54_3: Transistor, 55: Sense amplifier , 55_1: Transistor, 55_2: Transistor, 55_3: Transistor, 55_ 4: Transistor, 61: Control logic circuit, 62: Row drive circuit, 63: Column drive circuit, 64: Output circuit, 70: Memory cell array, 71: Row decoder, 72: Word line driver circuit, 80: Peripheral circuit, 81: Column decoder, 82: Precharge circuit, 83 : Amplification circuit, 84: Circuit, 90: Transistor layer, 91: Memory cell, 92: Trans istor, 93: Transistor, 94: Capacitor, 97: Transistor, 98: Transistor , 99: Transistor, 100: Memory device, 110: Period, 111: Operation, 112: Operation , 113: Operation, 114: Operation, 115: Operation, 120: Period, 120_1: Period, 12 0_2: Period, 121: Operation, 121A: Operation, 122: Operation, 123: Operation, 123A : Operation, 124: Operation, 125: Operation, 125A: Operation, 130: Period, 131: Operation, 132: Operation, 133: Operation, 134: Operation, 135: Operation, 140: Period, 141: Mov ement, 142: Operation, 144: Capacitor, 200: Transistor, 200M: Trans istor, 200T: Transistor, 205: Conductor, 205a: Conductor, 205b: Conductor, 211: Insulator, 212: Insulator, 214: Insulator, 216: Insulator, 222: Insulator, 224: Insulator, 230: Oxide, 230a: Oxide, 230b: Oxide, 230c: Oxi de, 240: Conductor, 240a: Conductor, 240b: Conductor, 241: Insulator, 241 a: Insulator, 241b: Insulator, 242: Conductor, 242a: Conductor, 242b: Conductor , 243: Oxide, 243a: Oxide, 243b: Oxide, 246: Conductor, 246a: Conductor, 246b: Conductor, 250: Insulator, 260: Conductor, 260a: Conductor, 26 0b: conductor, 272: insulator, 273: insulator, 274: insulator, 275: insulator, 2 76: conductor, 277: insulator, 278: conductor, 279: insulator, 280: insulator, 2 82: Insulator, 283: Insulator, 284: Insulator, 287: Insulator, 290: Conductor, 2 92: Capacitance, 292A: Capacitance, 292B: Capacitance, 294: Conductor, 295: Insulator, 29 6: insulator, 297: conductor, 298: insulator, 299: conductor, 300: transistor 311: semiconductor substrate, 313: semiconductor region, 314a: low resistance region, 314b: low resistance Region, 315: insulator, 316: conductor, 411: element layer, 413: transistor layer, 4 13_m: transistor layer, 413_1: transistor layer, 415: memory device layer, 415_n: memory device layer, 415_p: memory device layer, 415_p-1: memory re-device layer, 415_1: memory device layer, 415_3: memory device layer, 415 _4: memory device layer, 420: memory device, 420A: memory device, 420 B: memory device, 422: area, 424: conductor, 426: conductor, 428: conductor , 430: conductor, 432: memory cell, 433: memory cell, 434: memory cell, 4 35: memory cell, 470: memory unit, 470_m: memory unit, 470_1 : memory unit, 700: electronic components, 702: printed circuit board, 704: mounting board, 71 1: mold, 712: land, 713: electrode pad, 714: wire, 730: electronic part product, 731: interposer, 732: package substrate, 733: electrode, 735: semiconductor Device, 820: peripheral circuit, 901: boundary area, 902: boundary area, 7100: robot, 7120: Flying object, 7140: Cleaning robot, 7160: Automobile, 7200: TV device, 7210: Smartphone, 7220: PC, 7230: PC, 7232: Keyboard, 7233: monitor device, 7240: game machine, 7260: game machine, 7262: controller 7300: Cleaning robot

Claims

1. A first transistor layer; a second transistor layer having a region located on the first transistor layer, the first transistor layer includes a first transistor having a gate electrically connected to a local bit line, and a correction circuit electrically connected to the first transistor; the second transistor layer includes memory cells; The memory cell includes a second transistor; the second transistor is electrically connected to the local bit line; the second transistor has an oxide semiconductor in a channel formation region, the correction circuit is electrically connected to a global bit line; the correction circuit has a function of holding a voltage corresponding to a threshold voltage of the first transistor at a gate of the first transistor.

2. A first transistor layer; a second transistor layer having a region located on the first transistor layer, the first transistor layer includes a first transistor having a gate electrically connected to a local bit line, and a correction circuit electrically connected to the first transistor; the second transistor layer includes memory cells; The memory cell includes a second transistor; the second transistor is electrically connected to the local bit line; the second transistor has an oxide semiconductor in a channel formation region, the oxide semiconductor is indium oxide; the correction circuit is electrically connected to a global bit line; the correction circuit has a function of holding a voltage corresponding to a threshold voltage of the first transistor at a gate of the first transistor.

3. In claim 1 or 2, the correction circuit includes third to fifth transistors, the third transistor has a function of controlling a conduction state between a gate of the first transistor and one of a source and a drain of the first transistor; the fourth transistor has a function of controlling a state of conduction between the other of the source and the drain of the first transistor and a wiring to which a potential for causing a current to flow through the first transistor is applied; the fifth transistor has a function of controlling a conductive state between one of a source or a drain of the first transistor and the global bit line.

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