Semiconductor laminate, semiconductor element, and method for manufacturing semiconductor laminate

Abstract

To obtain a high-quality semiconductor laminate and a semiconductor element.SOLUTION: A semiconductor laminate comprises a substrate made of silicon carbide and having a main surface, a first layer provided on the main surface of the substrate and consisting of aluminum nitride crystals, a second layer provided on the first layer and consisting of either aluminum gallium nitride, aluminum indium nitride, or aluminum indium gallium nitride crystals, and a third layer provided on the second layer and consisting of gallium nitride crystals, and the first layer has tensile strain in the direction along the principal plane at 27°C.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor laminate, a semiconductor device, and a method for manufacturing a semiconductor laminate. [Background technology]

[0002] III-nitride high electron mobility transistors (HEMTs) are widely used as power amplifiers for mobile phone base stations (see, for example, Patent Document 1). III-nitride HEMTs can greatly increase the power that can be input per element compared to conventionally used Si-based devices. This allows base stations to be made smaller and installation costs to be significantly reduced. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2017-228642 A Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present disclosure is to obtain a high-quality semiconductor laminate and semiconductor device. [Means for solving the problem]

[0005] According to one aspect of the present disclosure, a substrate made of silicon carbide and having a primary surface; a first layer formed on the main surface of the substrate and made of aluminum nitride crystals; a second layer formed on the first layer and made of any one of aluminum gallium nitride, aluminum indium nitride, and aluminum indium gallium nitride crystals; a third layer formed on the second layer and made of gallium nitride crystal; Equipped with The first layer has a tensile strain in a direction along the major surface at 27°C. A semiconductor stack is provided.

[0006] According to another aspect of the present disclosure, There is provided a semiconductor device including the third layer of the semiconductor laminate according to the above aspect as at least a part of an operating layer.

[0007] According to yet another aspect of the present disclosure, (a) providing a substrate made of silicon carbide and having a primary surface; (b) growing a first layer composed of aluminum nitride crystals on the primary surface of the substrate; (c) annealing the first layer; (d) growing a second layer of aluminum gallium nitride, aluminum indium nitride, or aluminum indium gallium nitride crystal on the first layer; (e) growing a third layer of gallium nitride crystal on the second layer; Equipped with In step (c), the first layer is annealed to reduce the dislocation density in the main surface of the first layer to a value lower than the dislocation density in the main surface of the first layer immediately after step (b). A method for producing a semiconductor laminate is provided. Effect of the Invention

[0008] According to the present disclosure, a high-quality semiconductor laminate and semiconductor element can be obtained. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a schematic cross-sectional view showing a semiconductor laminate according to an embodiment of the present disclosure. [Diagram 2] FIG. 2 is a schematic cross-sectional view showing a semiconductor device according to an embodiment of the present disclosure. [Diagram 3]FIG. 3 is a flowchart showing a method for manufacturing a semiconductor laminate and a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. [Figure 4A] FIG. 4A is a diagram showing the full width at half maximum of the (0002) diffraction of the electron traveling layer by X-ray rocking curve measurement with respect to the Al composition ratio of the intermediate layer. [Figure 4B] FIG. 4B is a diagram showing the full width at half maximum of the (0002) diffraction of the electron traveling layer by X-ray rocking curve measurement with respect to the (0002) diffraction angle 2θ of the electron traveling layer. [Figure 5A] FIG. 5A is a diagram showing the full width at half maximum of the (0002) diffraction of the electron traveling layer by X-ray rocking curve measurement with respect to the thickness of the electron traveling layer. [Figure 5B] FIG. 5B is a diagram showing the full width at half maximum of the (10-12) diffraction of the electron traveling layer by X-ray rocking curve measurement with respect to the thickness of the electron traveling layer.

DETAILED DESCRIPTION OF THE INVENTION

[0010] <Findings obtained by the inventors> First, the findings obtained by the inventors will be described.

[0011] Silicon carbide (SiC), aluminum nitride (AlN), and gallium nitride (GaN) that constitute III-nitride-based HEMTs have the following linear expansion coefficients, a-axis lengths (lattice constants in the a-axis direction), and c-axis lengths (lattice constants in the c-axis direction) in the bulk state, as shown in Table 1 below. Note that the linear expansion coefficient has a large change with temperature and also has a concentration dependence on doping, so the uncertainty is large. However, the magnitude relationship of the absolute values of the linear expansion coefficients (6H-SiC < GaN < AlN) is certain.

[0012]

Table 1

[0013] In the laminate for manufacturing HEMT, the lattice constants of each crystal, the linear expansion coefficients of each crystal, and the state of each layer depending on temperature affect the crystal quality.

[0014] Here, with reference to Table 2 below, a comparison is made between a conventional laminate for manufacturing a HEMT, the laminate of Patent Document 1, and the laminate of the present disclosure discovered by the inventors.

[0015] [Table 2]

[0016] [Conventional laminates] A conventional laminate includes, in this order, a SiC substrate, an AlN layer as an underlayer, a GaN layer as an electron transport layer, and an aluminum gallium nitride (AlGaN) layer as an electron supply layer.

[0017] In a conventional AlN layer growth process, for example, an AlN layer is grown on a SiC substrate to a thickness of, for example, 100 nm or less. 9 ~10 10 cm -2 The AlN layer had a very high threading dislocation density of about 100 μm, and was poor in crystallinity. It is known that with conventional methods, the dislocation density of the AlN layer cannot be easily improved, even if the thickness of the AlN layer is increased to several μm.

[0018] In the conventional GaN layer growth process, the GaN layer is grown on the AlN layer, which has a high dislocation density. 9 cm -2 The crystallinity was poor, at least one unit.

[0019] Furthermore, in the conventional GaN layer growth process, a GaN layer with a relatively large lattice constant is grown on an AlN layer with a relatively small lattice constant, so compressive strain is applied to the GaN layer during growth. This causes new dislocations due to crystal strain in the GaN layer. As a result, the crystallinity of the GaN layer is reduced in the conventional stack.

[0020] Even with the conventional method, when the GaN layer was grown to a thickness of 2 μm or more, the dislocations decreased as the GaN layer grew thicker. 8 cm -2 However, when the thickness of the GaN layer was less than 2 μm, the dislocation density of the GaN layer was reduced to 10 8 cm -2 It was difficult to achieve a level below that.

[0021] [Laminate of Patent Document 1] The laminate in Patent Document 1 had, in this order, a SiC substrate, an AlN layer as an underlayer, a first AlGaN layer as an intermediate layer, a GaN layer as an electron transport layer, and a second AlGaN layer as an electron supply layer.

[0022] In Patent Document 1, no special treatment for reducing the dislocation density of the AlN layer is performed, so the dislocation density of the AlN layer is 10 9 ~10 10 cm -2 It is presumed that the AlN layer had a very high threading dislocation density of about 100 nm and poor crystallinity. Since no special measures were taken to reduce dislocation density in the growth of the AlGaN layer and GaN layer on the AlN layer, the GaN layer, which is the electron transport layer, also had a dislocation density of 100 nm. 9 cm -2 It is believed that the crystallinity was poor, at least to the extent that

[0023] In Patent Document 1, the lattice constant of the AlGaN layer is converted to a value close to that of the bulk GaN crystal by doping the AlGaN layer with impurities. This is thought to have been intended to suppress the generation of new dislocations in the GaN layer due to lattice distortion. However, as described above, the dislocation density of the AlN layer as the underlayer and the dislocation density of the AlGaN layer, which inherits the dislocation density of the AlN layer, are high from the beginning. For this reason, even if the AlGaN layer is doped with impurities, the dislocation density of the GaN layer is 10 9 cm -2 It is believed that the price remained at a high level of more than 10,000 units.

[0024] Furthermore, Patent Document 1 states that the lattice constant of the entire GaN layer is substantially equal to the lattice constant of the bulk GaN crystal, that is, the GaN layer is lattice-relaxed at room temperature (paragraph 0016). In other words, the lattice-relaxed GaN layer at room temperature corresponds to compressive strain being applied to the GaN layer at the growth temperature of the GaN layer based on the magnitude relationship of the linear expansion coefficients and their absolute values ​​described above. For this reason, new dislocations due to crystal strain were generated in the GaN layer during the GaN layer growth process. As a result, it is believed that the crystallinity of the GaN layer was reduced in the laminate of Patent Document 1.

[0025] [Overview of the Laminate of the Present Disclosure] The present inventors have investigated, as a laminate for manufacturing a HEMT, a semiconductor laminate having, in this order, a SiC substrate, an AlN layer that has been subjected to an annealing treatment as a base layer, an AlGaN layer as an intermediate layer, a GaN layer as an electron transport layer, and an AlGaN layer as an electron supply layer.

[0026] As a result of extensive investigation, the present inventors have succeeded in finding the following configuration.

[0027] In the configuration of the present disclosure, the dislocation density of the AlN layer is reduced by subjecting the AlN layer to annealing treatment. As a result, the AlN layer has tensile strain in a direction along the main surface of the SiC substrate at 27° C. With this configuration, the low dislocation density of the AlN layer is inherited by the layers above the AlN layer (the AlGaN layer and the GaN layer), so that the layers above the AlN layer can be grown with low dislocation density at the growth temperature of the Group III nitride crystal.

[0028] Furthermore, in the configuration of the present disclosure, an AlGaN layer having an intermediate composition between the AlN layer and the GaN layer is interposed between them. The AlGaN layer has a low dislocation density inheriting the dislocation density of the AlN layer as described above, and contains Ga, which weakens the bonding strength between atoms. This allows the GaN layer to be grown on the AlGaN layer in a nearly strain-free state at the growth temperature of the group III nitride crystal.

[0029] As a result, the GaN layer has tensile strain in the direction along the main surface of the SiC substrate at 27° C. The fact that the GaN layer has tensile strain at room temperature corresponds to the GaN layer having grown in a nearly strain-free state at the growth temperature of the GaN layer, based on the magnitude relationship of the linear expansion coefficients and their absolute values ​​described above.

[0030] By growing the GaN layer in a nearly strain-free state, the generation of new dislocations due to crystal strain can be suppressed in the GaN layer having a low dislocation density inherited from the AlN layer via the AlGaN layer. As a result, the configuration of the present disclosure makes it possible to obtain a GaN layer with good crystallinity.

[0031] The present disclosure below is based on the above findings made by the present inventors.

[0032] [Details of the embodiment of the present disclosure] Next, an embodiment of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, but is defined by the claims, and is intended to include all modifications within the meaning and scope of the claims.

[0033] <One embodiment of the present disclosure> Hereinafter, an embodiment of the present disclosure will be described with reference to the drawings.

[0034] (1) Semiconductor laminate With reference to FIG. 1, a semiconductor laminate (III nitride laminate substrate) 1 according to this embodiment will be described.

[0035] In the following, in crystals such as Group III nitride semiconductors having a wurtzite structure, <0001> The axis is called the "c-axis" and the (0001) plane is called the "c-plane". The (0001) plane is sometimes called the "+c-plane (III group element polar plane)" and the (000-1) plane is sometimes called the "-c-plane (nitrogen (N) polar plane)". The <1-100> axis (e.g., the [1-100] axis) is called the "m-axis" and the {1-100} plane is called the "m-plane". The <11-20> axis (e.g., the [11-20] axis) is called the "a-axis" and the {11-20} plane is called the "a-plane".

[0036] Hereinafter, the lattice constant in a state where no lattice distortion occurs in the crystal (unstrained state) may be referred to as the "bulk lattice constant" or the "fully relaxed lattice constant".

[0037] 1, the semiconductor laminate 1 of this embodiment (hereinafter also referred to as "laminate 1") includes, for example, a substrate 10, a base layer (first layer) 20, an intermediate layer (second layer, buffer layer) 30, an electron transit layer (third layer) 40, and an electron supply layer (fourth layer) 50. The laminate 1 may further include a cap layer (fourth layer) 60. However, as described below, the cap layer 60 does not necessarily have to be provided.

[0038] (substrate) The substrate 10 is made of, for example, silicon carbide (SiC). The polytype of the SiC substrate as the substrate 10 is not limited, but may be, for example, 4H, 6H, or 3C. Alternatively, the substrate 10 may be a composite substrate made of, for example, Si or sapphire other than SiC, with only the outermost surface being 4H, 6H, or 3C.

[0039] The substrate 10 is not particularly limited in terms of conductivity, but is preferably semi-insulating.

[0040] The substrate 10 has a primary surface (base surface) 11. In this embodiment, the low-index crystal plane closest to the primary surface 11 is, for example, the c-plane ((0001) plane, Si plane).

[0041] The c-axis of substrate 10 may be inclined at a predetermined off angle with respect to the normal to primary surface 11. The magnitude of the off angle of primary surface 11 may be, for example, more than 0° and not more than 1°, or more than 0° and not more than 0.1°. The off angle of primary surface 11 may have an in-plane distribution within the above-mentioned range. In addition, the inclination direction (off direction) of the off angle of primary surface 11 is not limited, and may be, for example, the a-axis direction or the m-axis direction.

[0042] The diameter of the substrate 10 may be, for example, 2 inches (50.8 mm) or more, or 4 inches (100 mm) or more, or 6 inches (150 mm) or more.

[0043] The thickness of the substrate 10 is not particularly limited, but depends on the diameter of the substrate 10. Specifically, the thickness of a substrate 10 with a diameter of 2 inches is, for example, 300 μm or more and 500 μm or less (typically 430 μm), the thickness of a substrate 10 with a diameter of 4 inches is, for example, 400 μm or more and 1000 μm or less (typically 500 μm), and the thickness of a substrate 10 with a diameter of 6 inches is, for example, 400 μm or more and 1500 μm or less (typically 600 μm).

[0044] The root mean square roughness RMS of a 5 μm square area of ​​the main surface 11 of the substrate 10 measured by an atomic force microscope (AFM) is, for example, 1 nm or less, or may be 0.5 nm or less.

[0045] (base layer) The underlayer 20 is configured to convert the crystals of the primary surface 11 of the substrate 10, which are, for example, 4H, 6H, or 3C, into 2H of a wurtzite-structured Group III nitride semiconductor. Specifically, the underlayer 20 is provided on the primary surface 11 of the substrate 10, for example, and is made of AlN crystals. The underlayer 20 is formed by heteroepitaxially growing AlN crystals on the primary surface 11 of the substrate 10, for example.

[0046] The underlayer 20 has a primary surface 21. The low-index crystal plane closest to the primary surface 21 of the underlayer 20 is, for example, the c-plane ((0001) plane, Al plane).

[0047] The underlayer 20 is provided, for example, continuously over the entire main surface 11 of the substrate 10. In other words, the underlayer 20 is not separated into, for example, a plurality of islands. This allows the underlayer 20 to be converted into a 2H structure over the entire main surface 21.

[0048] In this embodiment, as described later, by performing the annealing step S30 after the underlayer forming step S20, the dislocation density in the main surface 21 of the underlayer 20 after the annealing step S30 is reduced compared to the dislocation density in the main surface 21 of the underlayer 20 immediately after the underlayer forming step S20. 10 cm -2 The dislocation density in the main surface 21 of the underlayer 20 after the annealing step S30 is, for example, 1×10 10 cm -2 or less, or 1×10 9 cm -2 or less. This allows the intermediate layer 30 made of AlGaN crystal and the electron transit layer 40 made of GaN crystal to be grown above the underlayer 20 with a low dislocation density at the growth temperature of the group III nitride crystal. As a result of this annealing step S30, the underlayer 20 made of AlN crystal has tensile strain in a direction along the main surface 11 of the substrate 10 (for example, the a-axis direction) at 27°C, for example.

[0049] The amount of strain in the a-axis direction of the underlayer 20 and the amount of strain in the c-axis direction of the underlayer 20 depend on, for example, the lattice constants of the substrate 10 and the underlayer 20, the linear expansion coefficients of the substrate 10 and the underlayer 20, and the conditions of the annealing step S30.

[0050] The "amount of strain in the a-axis direction" here means, for example, the percentage change in the a-axis length (lattice constant in the a-axis direction) of the crystal constituting a given layer from the a-axis length of an unstrained bulk crystal. When the amount of strain is a positive value, it means that the crystal has tensile strain. When the amount of strain is a negative value, it means that the crystal has compressive strain. The "amount of strain in the c-axis direction" is defined in the same way as the "amount of strain in the a-axis direction," except that the a-axis direction is replaced with the c-axis direction.

[0051] In this embodiment, as described above, at 27° C., the underlayer 20 has a tensile strain in the direction along the main surface 11, and therefore the amount of strain of the underlayer 20 in the a-axis direction is a positive value.

[0052] On the other hand, in this embodiment, at 27° C., the underlayer 20 has a compressive strain in a direction perpendicular to the main surface 11, that is, the amount of strain of the underlayer 20 in the c-axis direction is a negative value.

[0053] The strain amount ε1 (%) of the underlayer 20 in the c-axis direction at 27° C. is calculated, for example, by the following formula (1). ε1=(c1-c AlN ) / c AlN ×100 (1) Here, c1 is the c-axis length of the AlN crystal constituting the underlayer 20. c1 is obtained by measuring the diffraction angle of the (0002) plane of the underlayer 20 by X-ray diffraction measurement (2θ-ω scan). AlN is the c-axis length of an unstrained bulk AlN crystal.

[0054] Specifically, the strain amount ε1 (%) of the underlayer 20 in the c-axis direction at 27° C. depends on the linear expansion coefficient of the substrate 10, but is typically, for example, not less than −0.1% and less than −0.01%.

[0055] In this embodiment, the thickness of the underlayer 20 may be, for example, not less than 200 nm and not more than 800 nm, or not less than 300 nm and not more than 500 nm.

[0056] By setting the thickness of the underlayer 20 to 200 nm or more, the underlayer 20 can be grown by a hydride vapor phase epitaxy (HVPE) method while stably covering the main surface 11 of the substrate 10. Furthermore, the thickness of the underlayer 20 can be stably controlled by the HVPE method.

[0057] By setting the thickness of the underlayer 20 to 200 nm or more, it is possible to suppress the diffusion of impurities from the substrate 10 toward the electron transit layer 40 through the underlayer 20. Specifically, when the substrate 10 is a SiC substrate, it is possible to suppress the diffusion of Si from the substrate 10 toward the electron transit layer 40. This makes it possible to suppress buffer leakage without doping with high concentrations of impurities such as Fe and C that form deep energy levels between the underlayer 20 made of AlN crystals and the electron transit layer 40 made of GaN crystals.

[0058] On the other hand, by setting the thickness of the underlayer 20 to 800 nm or less, a decrease in productivity can be suppressed.

[0059] By setting the thickness of the underlayer 20 to 800 nm or less, warping of the laminate 1 and cracks in the underlayer 20 and the like due to differences in the linear expansion coefficient between the underlayer 20 and other layers can be suppressed.

[0060] In this embodiment, the underlayer 20 is grown using the HVPE method, which allows high-speed growth. With the conventional MOVPE method, it takes several hours to grow the underlayer 20 made of AlN crystals with a thickness of 200 nm to 800 nm. In contrast, in this embodiment, by using the HVPE method, the underlayer 20 can be grown in a few minutes.

[0061] In this embodiment, the underlayer 20 is grown by the HVPE method that does not use an organic raw material, thereby making it possible to suppress the incorporation of excess carbon (C) into the underlayer 20. Specifically, the C concentration in the underlayer 20 is, for example, 1×10 19 cm -3 or less than or equal to 1×10 18 cm-3 or less, or 1×10 17 cm -3 It may be the following.

[0062] In this embodiment, the underlayer 20 having a thickness within the above range is grown by the HVPE method, and then the annealing step S30 described later is performed, thereby making it possible to improve the crystallinity of the underlayer 20.

[0063] When the full width at half maximum (FWHM) of the diffraction from a given crystal plane of AlN measured by X-ray rocking curve measurement is plotted against the thickness of underlayer 20, the X-ray diffraction half width of AlN tends to be downwardly convex.

[0064] Specifically, for example, when the thickness of the underlayer 20 is 200 nm or more and 800 nm or less, the half-width of the (0002) diffraction of the underlayer 20 measured by X-ray rocking curve measurement is 200 arc seconds or less, and the half-width of the (10-12) diffraction of the underlayer 20 measured by X-ray rocking curve measurement is 400 arc seconds or less.

[0065] For example, when the thickness of the underlayer 20 is 300 nm or more and 500 nm or less, the half-width of the (0002) diffraction of the underlayer 20 measured by X-ray rocking curve measurement is 180 arc seconds or less, and the half-width of the (10-12) diffraction of the underlayer 20 measured by X-ray rocking curve measurement is 380 arc seconds or less.

[0066] By improving the crystallinity of the underlayer 20 in this manner, the crystallinity of each layer grown on the underlayer 20 can be improved.

[0067] (Middle class) The intermediate layer 30 is provided on the primary surface 21 of the underlayer 20, for example, and is made of AlGaN crystals. The intermediate layer 30 is formed, for example, by heteroepitaxially growing AlGaN crystals on the primary surface 21 of the underlayer 20. That is, the intermediate layer 30 made of AlGaN crystals having an intermediate composition between the underlayer 20 and the electron transit layer 40 is interposed between them. This makes it possible to further reduce lattice distortion caused by lattice mismatch between the underlayer 20 made of AlN crystals and the electron transit layer 40 made of GaN crystals.

[0068] The intermediate layer 30 has a primary surface 31. The low-index crystal plane closest to the primary surface 31 of the intermediate layer 30 is, for example, the c-plane ((0001) plane, a group III element polar plane).

[0069] In this embodiment, the intermediate layer 30 made of AlGaN crystals is provided coherently (coherently grown) on the primary surface 21 of the underlayer 20 having a tensile strain. In other words, the intermediate layer 30 is pseudomorphic to the underlayer 20 having a tensile strain.

[0070] The state of being "coherently provided (coherently grown)" or "pseudo lattice matched" here refers to a state in which the upper layer is grown so that the crystal axis of the upper layer is pseudo-aligned with the crystal axis of the lower layer. In this embodiment, this state refers to a state in which the a-axis length of the intermediate layer 30 made of AlGaN crystals matches the a-axis length of the underlayer 20 made of AlN crystals in a reciprocal lattice map near the (11-24) diffraction of AlN obtained by X-ray diffraction measurement.

[0071] As described above, since the intermediate layer 30 is provided coherently on the underlayer 20, the excellent crystallinity of the underlayer 20 can be inherited by the intermediate layer 30. As a result, the crystallinity of the electron transit layer 40 made of GaN crystal can be improved via the intermediate layer 30.

[0072] In this embodiment, the intermediate layer 30 made of AlGaN crystal is coherently disposed on the primary surface 21 of the base layer 20 made of AlN crystal having tensile strain, so that the intermediate layer 30 has tensile strain in a direction along the primary surface 11 (e.g., the a-axis direction) at 27°C, for example.

[0073] In this embodiment, as described above, at 27° C., the intermediate layer 30 has a tensile strain in a direction along the main surface 11 (eg, the a-axis direction), and therefore the amount of strain of the underlayer 20 in the a-axis direction is a positive value.

[0074] On the other hand, in this embodiment, at 27° C., the intermediate layer 30 has a compressive strain in a direction perpendicular to the main surface 11, that is, the amount of strain of the intermediate layer 30 in the c-axis direction is a negative value.

[0075] The strain amount ε2 (%) of the intermediate layer 30 in the c-axis direction is calculated, for example, by the following formula (2). ε2=(c2-c AlGaN ) / c AlGaN ×100 (2) Here, c2 is the c-axis length of the AlGaN crystal constituting the intermediate layer 30. c2 is obtained by measuring the diffraction angle of the (0002) plane of the intermediate layer 30 by X-ray diffraction measurement (2θ-ω scan). AlN is the c-axis length of an unstrained bulk AlGaN crystal.

[0076] Specifically, the strain amount ε2 (%) in the c-axis direction of the intermediate layer 30 at 27°C depends on the linear expansion coefficient of the SiC substrate as the substrate 10 and the Al composition ratio x of the intermediate layer 30 made of AlGaN crystal, but is typically greater than or equal to -0.1% and less than -0.01%.

[0077] In this embodiment, the intermediate layer 30 is made of Al x Ga 1-x The intermediate layer 30 is made of crystals represented by the composition formula: N. The Al composition ratio x in the intermediate layer 30 is, for example, not less than 0.75 and not more than 0.96.

[0078] By setting the Al composition ratio x in the intermediate layer 30 to 0.75 or more, it is possible to suppress overlapping in X-ray diffraction measurement between the (0006) diffraction peak of SiC as the substrate 10 and the (0002) diffraction peak of AlGaN as the intermediate layer 30. This allows the Al composition ratio in the intermediate layer 30 to be stably controlled.

[0079] By setting the Al composition ratio x in the intermediate layer 30 to 0.75 or more, the intermediate layer 30 can be stably grown coherently on the underlayer 20 made of AlN crystals having tensile strain. This allows the excellent crystallinity of the underlayer 20 to be stably inherited by the intermediate layer 30.

[0080] On the other hand, when the Al composition ratio x in the intermediate layer 30 exceeds 0.96, the electron transit layer 40 made of GaN crystal grows coherently with the intermediate layer 30 made of AlGaN crystal, at least in the initial stage of growth of the electron transit layer 40. This may cause the GaN crystal constituting the electron transit layer 40 to distort during growth of the electron transit layer 40, resulting in new dislocations being generated in the electron transit layer 40. As a result, the effect of improving the crystallinity of the electron transit layer 40 by the presence of the intermediate layer 30 made of AlGaN crystal may not be fully achieved.

[0081] In contrast, by setting the Al composition ratio x in the intermediate layer 30 to 0.96 or less, the electron transit layer 40 made of GaN crystals can be stably grown on the intermediate layer 30 made of AlGaN crystals in a state that is nearly strain-free at the growth temperature of the electron transit layer 40. This makes it possible to suppress the occurrence of new dislocations during the growth of the electron transit layer 40. As a result, the effect of improving the crystallinity of the electron transit layer 40 by the presence of the intermediate layer 30 made of AlGaN crystals can be stably obtained.

[0082] In this embodiment, the thickness of the intermediate layer 30 is, for example, 30 nm or more and 600 nm or less. By making the thickness of the intermediate layer 30 30 nm or more, the effect of relaxing the lattice distortion of the electron transit layer 40 by the intermediate layer 30 can be stably obtained. On the other hand, by making the thickness of the intermediate layer 30 600 nm or less, the intermediate layer 30 can be stably grown coherently on the underlayer 20.

[0083] In this embodiment, the intermediate layer 30 may be doped with impurities that are elements other than Al, Ga, and N that constitute the matrix. Examples of the impurities include oxygen (O), carbon (C), silicon (Si), and iron (Fe). Specifically, the total concentration of impurities in the intermediate layer 30 is, for example, 3×10 19 cm -3 When the total concentration of impurities in the intermediate layer 30 is within the above-mentioned range, it has been confirmed by X-ray diffraction measurement that the lattice constant of the intermediate layer 30 made of an AlGaN crystal is equivalent to the lattice constant of an AlGaN crystal when an undoped AlGaN crystal is coherently grown on an AlN crystal.

[0084] (Electron transport layer) The electron transit layer 40 is configured to generate a two-dimensional electron gas (2DEG) in a region close to the electron supply layer 50, for example, as described below, and to enable electrons to transit when the semiconductor device 2 is driven. Specifically, the electron transit layer 40 is provided, for example, on the primary surface 31 of the intermediate layer 30, and is made of GaN crystals. The electron transit layer 40 is formed, for example, by heteroepitaxially growing GaN crystals on the primary surface 31 of the intermediate layer 30.

[0085] The electron transit layer 40 has, for example, a primary surface 41. In this embodiment, the low-index crystal plane closest to the primary surface 41 of the electron transit layer 40 is, for example, the c-plane ((0001) plane, Ga plane).

[0086] In this embodiment, the electron transit layer 40 is epitaxially grown on the main surface 31 of the intermediate layer 30, so that the electron transit layer 40 has tensile strain in a direction along the main surface 11 (e.g., the a-axis direction) at 27° C., for example. The electron transit layer 40 is not lattice-matched with the intermediate layer 30.

[0087] In this embodiment, as described above, the electron transit layer 40 has tensile strain in the direction along the main surface 11 at 27° C., so that the strain amount of the electron transit layer 40 in the a-axis direction is a positive value.

[0088] On the other hand, in this embodiment, at 27° C., the electron transit layer 40 has a compressive strain in a direction perpendicular to the major surface 11, that is, the amount of strain in the c-axis direction of the underlayer 20 is a negative value.

[0089] The strain ε3 (%) of the electron transit layer 40 in the c-axis direction is calculated, for example, by the following formula (3). ε3=(c3-c GaN ) / c GaN ×100 (3) Here, c3 is the c-axis length of the GaN crystal constituting the electron transit layer 40. c3 is obtained by measuring the diffraction angle of the (0002) plane of the electron transit layer 40 by X-ray diffraction measurement (2θ-ω scan). GaN is the c-axis length of an unstrained bulk GaN crystal.

[0090] Specifically, the strain ε3 (%) in the c-axis direction of the electron transit layer 40 at 27° C. may be, for example, −0.1% or more and less than −0.01%, or −0.06% or more and −0.02% or less.

[0091] As described above, the strain ε3 in the c-axis direction of the electron transit layer 40 at room temperature being within the above range corresponds to the electron transit layer 40 being grown in a nearly strain-free state at the growth temperature of the electron transit layer 40.

[0092] In this way, by growing the electron transit layer 40 in a nearly strain-free state at the growth temperature of GaN, it is possible to grow a high-quality electron transit layer 40 even if the thickness of the electron transit layer 40 is reduced.

[0093] In this embodiment, the thickness of the electron transit layer 40 is, for example, 1 μm or less. In this embodiment, by setting the thickness of the electron transit layer 40 to 1 μm or less, it is possible to suppress warping of the laminate 1 caused by the difference in linear expansion coefficient between the electron transit layer 40 and other layers. This makes it possible to improve lithography accuracy. In addition, in this embodiment, by setting the thickness of the electron transit layer 40 to 1 μm or less, it is possible to suppress buffer leakage current caused by the slight conductivity of the GaN itself that constitutes the electron transit layer 40.

[0094] There is no lower limit to the thickness of the electron transit layer 40. However, from the viewpoint of generating a predetermined two-dimensional electron gas (2DEG) in the electron transit layer 40, the thickness of the electron transit layer 40 may be, for example, 100 nm or more.

[0095] In this embodiment, even if the thickness of the electron transit layer 40 is within the above-mentioned range, the half width of the diffraction peak of the electron transit layer 40 measured by X-ray rocking curve measurement is small. Specifically, the half width of the (0002) diffraction of the electron transit layer 40 measured by X-ray rocking curve measurement is, for example, 300 seconds or less, or 270 seconds or less, or 250 seconds or less. The half width of the (10-12) diffraction of the electron transit layer 40 measured by X-ray rocking curve measurement is, for example, 410 seconds or less, or 380 seconds or less, or 350 seconds or less.

[0096] In this embodiment, the dislocation density of the electron transport layer 40 can be reduced by growing the electron transport layer 40 in a nearly strain-free state.

[0097] In the conventional method, when the electron transit layer 40 is grown three-dimensionally, dislocation density can be reduced by causing dislocations to meet during the three-dimensional growth. However, in this case, there is a possibility that impurities such as O may be mixed in through facets other than the c-plane during the three-dimensional growth.

[0098] When the electron transit layer 40 is grown by step-flow growth rather than three-dimensional growth, the dislocation density decreases as the grown film thickness increases. However, in this case, the degree of reduction in dislocation density is lower than in the case of three-dimensional growth. Therefore, the dislocation density cannot be sufficiently reduced unless the electron transit layer 40 is grown very thick.

[0099] In contrast, in this embodiment, the electron transit layer 40 is grown in a nearly strain-free state on the intermediate layer 30 made of AlGaN crystals having a low dislocation density, so that the dislocation density of the electron transit layer 40 can be reduced without three-dimensionally growing the electron transit layer 40 and without growing it thick.

[0100] Specifically, even if the thickness of the electron transit layer 40 is within the above-mentioned range, the dislocation density on the main surface 41 of the electron transit layer 40 is, for example, 1×10 9 cm -2 or less than 5 × 10 8 cm -2 or less, or 1×10 8 cm -2 The dislocation density on the primary surface 41 of the electron transit layer 40 can be measured, for example, by a multiphoton excitation microscope.

[0101] As described above, by reducing the dislocation density on the main surface 41 of the electron transit layer 40, it is possible to reduce the gate leakage when the semiconductor element 2 is operated. This makes it possible to suppress deterioration of the gate electrode when the semiconductor element 2 is operated. As a result, it is possible to improve the reliability of the semiconductor element 2 as a HEMT.

[0102] The lower limit of the dislocation density on the main surface 41 of the electron transit layer 40 is set to, for example, 1×10 7 cm -2 It can be considered that:

[0103] In this embodiment, the electron transit layer 40 is grown (step-flow growth) using the c-plane as the growth plane by a manufacturing method described below, without three-dimensionally growing the electron transit layer 40, thereby suppressing the incorporation of impurities such as O through facets other than the c-plane. Specifically, the O concentration in the electron transit layer 40 is, for example, 1×10 throughout the entire electron transit layer 40 except for a region from the main surface 41 of the electron transit layer 40 to a depth of 200 nm. 16 cm -3 The above is the case. In this way, by suppressing the incorporation of O, which acts as an n-type impurity (donor) in the electron transit layer 40, it is possible to suppress an increase in the free electron concentration in the electron transit layer 40. The reason for "excluding the region up to a depth of 200 nm" is as follows. Secondary ion mass spectrometry (SIMS), which is normally used for impurity analysis, is affected by contamination of the sample surface. This reduces the reliability of the analysis results in the region up to a depth of 200 nm. As a result, the impurity concentration in this region tends to be measured as higher than the actual concentration. Therefore, in this embodiment, the actual O concentration in the electron transit layer 40 is 1×10 16 cm -3 It is speculated to be as follows:

[0104] In this embodiment, the thickness of the underlayer 20 is set to 200 nm or more, thereby suppressing the diffusion of Si from the substrate 10 toward the electron transit layer 40. Specifically, the Si concentration in the electron transit layer 40 is, for example, 1×10 over the entire electron transit layer 40 except for a region from the main surface 41 of the electron transit layer 40 to a depth of 200 nm. 16 cm -3The following is the reason why the "region up to a depth of 200 nm is excluded" is stated. Therefore, in this embodiment, the actual Si concentration in the electron transit layer 40 is 1×10 16 cm -3 It is speculated to be as follows:

[0105] In this way, by suppressing the increase in the free electron concentration in the electron transit layer 40, it is possible to suppress an increase in the buffer leakage current. By suppressing the increase in the buffer leakage current when the 2DEG of the second layer is pinched off, it is possible to suppress a decrease in the On / Off current ratio. Furthermore, by suppressing the increase in the buffer leakage current, it is possible to suppress the leakage current between elements, and thus the interference of operations between adjacent elements.

[0106] In this embodiment, as described above, by suppressing the inclusion of Si and O, which act as n-type impurities in the electron transit layer 40, it is not necessary to dope the electron transit layer 40 with high concentrations of impurities such as Fe and C, which form deep energy levels. Specifically, the Fe concentration and C concentration in the electron transit layer 40 are each, for example, 1×10 to 1000 Å over the entire electron transit layer 40 except for a region extending to a depth of 200 nm from the main surface 41 of the electron transit layer 40. 16 cm -3 The reason for "excluding the region up to a depth of 200 nm" is the same as that for the O concentration. Therefore, in this embodiment, the Fe concentration and C concentration in the actual electron transit layer 40 are each 1×10 to 1×10 up to the main surface 41 of the electron transit layer 40. 16 cm -3 It is speculated to be as follows:

[0107] In this embodiment, by growing the electron transport layer 40 with the c-plane as the growth plane (step-flow growth) by the manufacturing method described later, the electron transport layer 40 has good surface flatness. Specifically, the root mean square roughness RMS measured by an atomic force microscope (AFM) for a 5-μm square region of the main surface 41 of the electron transport layer 40 is, for example, 1 nm or less, or may be 0.5 nm or less.

[0108] (Electron supply layer) The electron supply layer 50 is configured to generate 2DEG in the electron transport layer 40, for example. Specifically, the electron supply layer 50 is composed of a crystal of a group-III nitride having a wider bandgap than GaN constituting the electron transport layer 40 and a lattice constant smaller than the lattice constant of GaN. Examples of the group-III nitride constituting the electron supply layer 50 include AlN, AlGaN, InAlN, or AlInGaN, and Al x In y Ga 1-x-y N (where 0 < x ≤ 1, 0 ≤ y < 1, 0 < x + y ≤ 1). Further, the group-III nitride constituting the electron supply layer 50 may contain scandium (Sc) as a constituent element. The electron supply layer 50 is provided on the electron transport layer 40, for example. The electron supply layer 50 is formed, for example, by heteroepitaxially growing the above-described crystal of the group-III nitride on the main surface 41 of the electron transport layer 40.

[0109] The electron supply layer 50 has a main surface 51. In this embodiment, the low-index crystal plane closest to the main surface 51 of the electron supply layer 50 is, for example, the c-plane ((0001) plane, group-III element polar plane).

[0110] The electron supply layer 50 is provided coherently (growing coherently) on the main surface 41 of the electron transport layer 40 made of a GaN crystal, for example. In other words, the electron supply layer 50 is pseudomorphic with respect to the electron transport layer 40, for example.

[0111] The thickness of the electron supply layer 50 may be, for example, 5 nm to 50 nm, or 10 nm to 30 nm. By making the thickness of the electron supply layer 50 5 nm or more, or 10 nm or more, it is possible to reduce the gate leakage current. On the other hand, by making the thickness of the electron supply layer 50 50 nm or less, or 30 nm or less, it is possible to make the threshold voltage a predetermined value or less and improve the switching characteristics.

[0112] In this embodiment, the electron supply layer 50 has good surface flatness, similar to the electron transit layer 40. Specifically, the root-mean-square roughness RMS of a 5 μm square region of the main surface 51 of the electron supply layer 50 measured by an atomic force microscope (AFM) is equivalent to that of the electron transit layer 40, for example.

[0113] (Cap layer) The cap layer 60 is provided on the electron supply layer 50 and is made of GaN, for example. The cap layer 60 is formed, for example, by heteroepitaxially growing GaN crystals on the primary surface 51 of the electron supply layer 50. By forming the cap layer 60 on the primary surface 51 of the electron supply layer 50 in this manner, for example, when the electron supply layer 50 is made of AlGaN crystals, selective evaporation of Ga from the AlGaN surface during cooling after growth can be suppressed, and the formation of an Al-rich AlGaN layer can be suppressed.

[0114] The thickness of the cap layer 60 may be, for example, 1 nm or more and 10 nm or less, or 2 nm or more and 5 nm or less. By making the thickness of the cap layer 60 1 nm or more, or 2 nm or more, evaporation of the Ga component or the In component can be stably suppressed. On the other hand, by making the thickness of the cap layer 60 10 nm or less, or 5 nm or less, generation of a current component flowing in the cap layer 60 can be suppressed. This makes it possible to suppress inhibition of device operation caused by the cap layer 60.

[0115] In the laminate 1 configured as above, by reducing the thickness of the electron transit layer 40 as described above, the warpage of the laminate 1 can be reduced. Specifically, the warpage per 50.8 mm length of the laminate 1 is, for example, 20 μm or less, or may be 10 μm or less. This makes it possible to suppress a decrease in lithography accuracy caused by the warpage of the laminate 1. As a result, it becomes possible to improve the manufacturing yield of the semiconductor elements 2.

[0116] The smaller the warpage of the laminate 1, the better, and is, for example, 0 μm or more.

[0117] (2) Semiconductor elements Next, the semiconductor device of this embodiment will be described with reference to FIG.

[0118] 2, the semiconductor device 2 of this embodiment is manufactured using, for example, the above-mentioned laminate 1, and is configured as a HEMT. Specifically, the semiconductor device 2 has, for example, a substrate 10, an underlayer 20, an intermediate layer 30, an electron transit layer 40, an electron supply layer 50, a cap layer 60, a gate electrode 61, a source electrode 62, and a drain electrode 63. That is, the semiconductor device 2 has the above-mentioned electron transit layer 40 made of GaN crystal as at least a part of the operating layer.

[0119] (electrode) The gate electrode 61 is provided on the electron supply layer 50. The gate electrode 61 may be in contact with the electron supply layer 50, or may be provided on the electron supply layer 50 via a cap layer 60. The gate electrode 61 has, for example, a multi-layer structure (Ni / Au) of nickel (Ni) and gold (Au).

[0120] The source electrode 62 is provided on the electron supply layer 50 via, for example, a cap layer 60. The source electrode 62 is disposed at a position spaced a predetermined distance from the gate electrode 61. The source electrode 62 has, for example, a multi-layer structure (Ti / Al) of titanium (Ti) and aluminum (Al).

[0121] The drain electrode 63 is provided on the electron supply layer 50 via, for example, a cap layer 60. The drain electrode 63 is disposed at a position on the opposite side of the gate electrode 61 to the source electrode 62 at a predetermined distance from the gate electrode 61. The drain electrode 63 has, for example, a multi-layer structure of Ti and Al, similar to the source electrode 62. Note that in the source electrode 62 and the drain electrode 63, a multi-layer structure of Ni / Au may be laminated on the multi-layer structure of Ti / Al.

[0122] (3) Method for manufacturing a semiconductor laminate and method for manufacturing a semiconductor element Next, a method for manufacturing a semiconductor laminate and a method for manufacturing a semiconductor element according to this embodiment will be described with reference to FIGS.

[0123] The method for manufacturing a semiconductor element according to this embodiment includes, for example, a substrate preparation process S10, a base layer formation process S20, an annealing process S30, an intermediate layer formation process S40, an electron transit layer formation process S50, an electron supply layer formation process S60, a cap layer formation process S70, and an electrode formation process S80.

[0124] (S10: Board preparation process) First, prepare the substrate 10. As the substrate 10, for example, a semi-insulating SiC substrate of polytype 6H is prepared.

[0125] (S20: Base layer formation process) Next, the underlayer 20 made of AlN crystals is heteroepitaxially grown on the main surface 11 of the substrate 10. The underlayer 20 is grown by, for example, the HVPE method.

[0126] As the group III (Al) source gas, for example, aluminum monochloride (AlCl) gas or aluminum trichloride (AlCl3) gas is used. AlCl gas or AlCl3 gas can be generated by supplying hydrogen chloride (HCl) gas onto metal Al placed in the HVPE apparatus. As the N source gas, for example, ammonia (NH3) gas is used. These source gases may be supplied in a mixed state with a carrier gas containing hydrogen (H2) gas, nitrogen (N2) gas, or a mixture of these gases.

[0127] As the crystal growth conditions, for example, at least one of the growth temperature, the V / III ratio, the growth rate, and the growth pressure is appropriately controlled. This allows the growth of a high-quality underlayer 20. Note that the "V / III ratio" here refers to the ratio of the supply amount (partial pressure) of the V (N) source gas to the supply amount (partial pressure) of the III (Al) source gas.

[0128] Specifically, the crystal growth conditions are set as follows, for example. Growth temperature: 900℃ or higher and 1300℃ or lower V / III ratio: 0.2 or more and 200 or less Growth rate: 0.5nm / min or more and 3000nm / min or less Growth pressure: 0.9 atm to 1.3 atm

[0129] At this time, by setting the growth pressure to 0.9 atmospheres or more, that is, by growing under a pressure higher than that in the case of using a reduced pressure growth apparatus, it is possible to easily grow the underlayer 20 with good surface flatness. On the other hand, since a growth apparatus that can withstand high pressure needs a pressure-resistant structure, from the viewpoint of manufacturing costs, the growth pressure may be set to 1.3 atmospheres or less.

[0130] At this time, HCl gas may be flowed in order to prevent AlN from adhering to the nozzle of the gas supply pipe that introduces various gases into the growth chamber of the HVPE apparatus. In this case, the ratio of the supply amount of HCl gas to AlCl gas or AlCl3 gas is set to, for example, 0.1 to 100.

[0131] By controlling the crystal growth conditions as described above, the surface flatness of the underlayer 20 can be improved.

[0132] Immediately after the underlayer forming step S20, the underlayer 20 is 10 cm -2 It has a dislocation density as high as 10 ...

[0133] (S30: Annealing process) After the underlayer formation step S20 is completed, the underlayer 20 is annealed.

[0134] The annealing step S30 is performed, for example, in the growth chamber of the same HVPE apparatus without lowering the temperature after the base layer forming step S20. Note that the annealing step S30 may be performed in a separate apparatus after the base layer forming step S20.

[0135] In the annealing step S30 of this embodiment, the atoms in the underlayer 20 move relatively freely due to the annealing treatment of the underlayer 20, and the atomic arrangement changes. This causes the atoms to be rearranged so as to reduce dislocations in a high-energy state. As a result, the dislocation density in the main surface 21 of the underlayer 20 is reduced below the dislocation density in the main surface 21 of the underlayer 20 immediately after the underlayer forming step S20. Specifically, the dislocation density in the main surface 21 of the underlayer 20 is reduced to, for example, 1×10 10 cm -2 or less, or 1×10 9 cm -2 The following applies.

[0136] During this process, the underlayer 20 undergoes lattice relaxation at the annealing temperature from a state in which compressive strain was generated in the underlayer 20 at the growth temperature of the underlayer 20 in the underlayer formation step S20. As a result, after the annealing step S30, tensile strain is generated in the underlayer 20 in the direction along the main surface 11 of the substrate 10 at 27°C.

[0137] At this time, in this embodiment, the underlayer 20 is annealed in an atmosphere containing, for example, nitrogen (N2) gas. In other words, the annealing is performed in an atmosphere containing substantially no H2 gas without supplying hydrogen (H2) gas and NH3 gas to the growth chamber. Here, "substantially no H2 gas" means, for example, that the partial pressures of H2 gas in the growth chamber and NH3 gas that decomposes to release H2 gas are each less than 1% of the total pressure. By performing the process in such an atmosphere, it is possible to suppress the occurrence of point defects in the underlayer 20 caused by H2 gas. Note that N2 gas may be mixed with an inert gas such as argon gas (Ar gas) and the like and then supplied.

[0138] At this time, in this embodiment, the temperature of the annealing treatment may be, for example, 1350°C or more and 1550°C or less, or 1390°C or more and 1490°C or less. By setting the temperature of the annealing treatment to 1350°C or more, or 1390°C or more, the above-mentioned atomic rearrangement is performed so as to reduce dislocations in a high energy state. In this process, the lattice relaxation of the underlayer 20 occurs at the annealing treatment temperature from a state in which compressive strain occurs in the underlayer 20 at the growth temperature of the underlayer 20 in the underlayer formation step S20. On the other hand, by setting the temperature of the annealing treatment to 1550°C or less, or 1490°C or less, decomposition of the substrate 10 made of SiC can be suppressed.

[0139] In this embodiment, the annealing time is, for example, 10 minutes or more and 300 minutes or less. By setting the annealing time to 10 minutes or more, the underlayer 20 can be sufficiently lattice-relaxed. On the other hand, by setting the annealing time to 300 minutes or less, the deterioration of the flatness of the main surface 21 of the underlayer 20 can be suppressed.

[0140] By annealing the underlayer 20 under the above-mentioned conditions, atoms in the underlayer 20 move freely, and the underlayer 20 is lattice-relaxed at the annealing temperature. As a result, tensile strain is generated in the underlayer 20 in the direction along the main surface 11 of the substrate 10 at 27° C. due to the difference in linear expansion coefficient between the substrate 10 and the underlayer 20 when the temperature is decreased after the annealing step S30.

[0141] Furthermore, by annealing the underlayer 20 under the conditions described above, the crystallinity of the underlayer 20 can be improved.

[0142] Specifically, for example, when the thickness of the underlayer 20 is 200 nm or more and 800 nm or less, the half-width of the (0002) diffraction of the underlayer 20 measured by X-ray rocking curve can be set to 200 arc seconds or less, and the half-width of the (10-12) diffraction of the underlayer 20 measured by X-ray rocking curve can be set to 400 arc seconds or less.

[0143] For example, when the thickness of the underlayer 20 is 300 nm or more and 500 nm or less, the half-width of the (0002) diffraction of the underlayer 20 measured by X-ray rocking curve measurement can be 180 arc seconds or less, and the half-width of the (10-12) diffraction of the underlayer 20 measured by X-ray rocking curve measurement can be 380 arc seconds or less.

[0144] (S40: Intermediate layer formation process) After the annealing step S30 is completed, the intermediate layer 30 made of AlGaN crystals is heteroepitaxially grown on the primary surface 21 of the annealed underlayer 20. The intermediate layer 30 is grown by, for example, metalorganic vapor phase epitaxy (MOVPE).

[0145] As the group III source gas, for example, trimethylaluminum (Al(CH3)3, TMA) gas and trimethylgallium (Ga(CH3)3, TMG) ​​gas are used. As the N source gas, for example, NH3 gas is used. These source gases may be mixed with a carrier gas containing H2 gas, N2 gas, or a mixture of these gases and then supplied.

[0146] At this time, in this embodiment, the growth temperature of the intermediate layer 30 is set to be lower than the temperature of the annealing step S30. Specifically, the growth temperature of the intermediate layer 30 is set to be, for example, 900° C. or higher and 1200° C. or lower.

[0147] At this time, in this embodiment, the intermediate layer 30 is coherently grown on the main surface 21 of the underlayer 20, for example.

[0148] As described above, the intermediate layer forming step S40 is performed at a growth temperature lower than the temperature of the annealing step S30. Therefore, the underlayer 20 that has become strain-free in the annealing step S30 has tensile strain at the growth temperature of the intermediate layer forming step S40 due to the difference in linear expansion coefficient between the substrate 10 and the underlayer 20. The intermediate layer 30 is coherently grown on the underlayer 20 in which the tensile strain has been generated.

[0149] As the crystal growth conditions, for example, at least one of the V / III ratio, the growth rate, and the growth pressure is appropriately controlled in addition to the above-mentioned growth temperature. This allows the intermediate layer 30 to be coherently grown on the underlayer 20.

[0150] Specifically, other crystal growth conditions are set, for example, as follows: V / III ratio: 1 or more and 10000 or less Growth rate: 0.1nm / min or more and 100nm / min or less Growth pressure: 0.01 atm to 1 atm

[0151] In this embodiment, the Al composition ratio x in the intermediate layer 30 is set to, for example, not less than 0.75 and not more than 0.96.

[0152] At this time, in this embodiment, the thickness of the intermediate layer 30 is set to, for example, 30 nm to 600 nm.

[0153] (S50: Electron transport layer formation process) After the intermediate layer formation step S40 is completed, the electron transit layer 40 made of GaN crystals is heteroepitaxially grown on the primary surface 31 of the intermediate layer 30. The growth of the electron transit layer 40 is performed, for example, by MOVPE, and is performed continuously in the growth chamber of the same MOVPE apparatus as the intermediate layer formation step S40.

[0154] At this time, TMG gas is used as the Ga source gas. The other gases used in the electron transport layer forming step S50 are the same as those in the intermediate layer forming step S40.

[0155] In this embodiment, by interposing the intermediate layer 30 made of AlGaN crystals between the underlayer 20 and the electron transit layer 40, the occurrence of compressive strain in the electron transit layer 40 made of GaN can be suppressed, and the electron transit layer 40 can be grown in a nearly strain-free state.

[0156] Furthermore, in this embodiment, the electron transit layer 40 is grown by step-flow growth (two-dimensional growth) rather than three-dimensional growth. That is, the electron transit layer 40 is grown using the c-plane as the growth plane without generating facets other than the c-plane in the electron transit layer 40.

[0157] As the crystal growth conditions, for example, at least one of the growth temperature, growth rate, and growth pressure is appropriately controlled.

[0158] Specifically, the crystal growth conditions are set as follows, for example. Growth temperature: 900℃ or higher and 1200℃ or lower V / III ratio: 1 or more and 30000 or less Growth rate: 0.1nm / min or more and 10nm / min or less Growth pressure: 0.01 atm to 1 atm

[0159] By the above-described crystal growth, the electron transit layer 40 can be formed with high crystallinity while being thin in thickness.

[0160] Specifically, for example, the electron transit layer 40 can be formed so that the thickness of the electron transit layer 40 is 1 μm or less, the half-width of the (0002) diffraction of the electron transit layer 40 measured by X-ray rocking curve measurement is 300 seconds or less, and the half-width of the (10-12) diffraction of the electron transit layer 40 measured by X-ray rocking curve measurement is 410 seconds or less.

[0161] In this embodiment, the electron transit layer 40 is grown in a nearly strain-free state, so that the dislocation density on the main surface 41 of the electron transit layer 40 is reduced to 1×10 9 cm -2 or less, or 5 x 10 8 cm -2 It can be as follows:

[0162] In this embodiment, the above-described crystal growth can reduce the impurity concentration in the electron transit layer 40 as follows. O concentration in the electron transport layer 40: 1×10 16 cm -3 below, Si concentration in the electron transport layer 40: 1×10 16 cm -3 below, Fe concentration and C concentration in the electron transport layer 40: 1×10 16 cm -3 below.

[0163] (S60: Electron supply layer formation step) Next, an electron supply layer 50 made of a group III nitride crystal having a band gap wider than that of the GaN constituting the electron transit layer 40 is heteroepitaxially grown on the primary surface 41 of the electron transit layer 40. The electron supply layer 50 is grown by, for example, MOVPE, continuously in the growth chamber of the same MOVPE apparatus as the electron transit layer formation step S50.

[0164] In this embodiment, the electron supply layer 50 is grown from, for example, AlN, AlGaN, InAlN, or AlInGaN crystals.

[0165] At this time, the Al source gas is, for example, TMA gas. The In source gas is, for example, trimethylindium (In(CH3)3, TMI) gas. Other gases used in the electron supply layer forming step S60 are the same as those in the electron transport layer forming step S50.

[0166] At this time, in this embodiment, the electron supply layer 50 is coherently grown on the major surface 41 of the electron transit layer 40, for example.

[0167] As the crystal growth conditions, for example, at least one of the growth temperature, the V / III ratio, the growth rate, and the growth pressure is appropriately controlled.

[0168] Specifically, the crystal growth conditions are set as follows, for example. Growth temperature: 900℃ or higher and 1200℃ or lower V / III ratio: 1 or more and 10000 or less Growth rate: 0.1nm / min or more and 10nm / min or less Growth pressure: 0.01 atm to 1 atm

[0169] At this time, in this embodiment, the thickness of the electron supply layer 50 is set to, for example, 5 nm or more and 50 nm or less.

[0170] (S70: Cap layer formation process) Next, a cap layer 60 made of GaN is grown on the primary surface 51 of the electron supply layer 50. The growth of the cap layer 60 is performed by, for example, MOVPE, and is performed consecutively in the growth chamber of the same MOVPE apparatus as the electron supply layer formation step S60.

[0171] At this time, the thickness of the cap layer 60 is set to, for example, 1 nm or more and 10 nm or less.

[0172] In this manner, the laminate 1 of the present embodiment is manufactured.

[0173] (S80: Electrode formation process) After the laminate 1 is manufactured, a gate electrode 61 , a source electrode 62 and a drain electrode 63 are formed above the electron supply layer 50 .

[0174] In this manner, the semiconductor device 2 of the present embodiment is manufactured.

[0175] (4) Summary of this embodiment According to this embodiment, one or more of the following advantages can be obtained.

[0176] (a) In this embodiment, by annealing the underlayer 20 made of AlN crystals on the substrate 10 made of SiC, the dislocation density in the main surface 21 of the underlayer 20 can be reduced by the above-mentioned atomic rearrangement.

[0177] During this process, the underlayer 20 undergoes lattice relaxation at the annealing temperature from the state in which compressive strain was generated in the underlayer 20 at the growth temperature of the underlayer 20 in the underlayer formation step S20. As a result, after the annealing step S30, tensile strain is generated in the underlayer 20 in the direction along the main surface 11 of the substrate 10 at 27° C. due to the difference in linear expansion coefficient between the substrate 10 and the underlayer 20.

[0178] With this configuration, the low dislocation density of the underlayer 20 can be inherited by the layers (the intermediate layer 30 and the electron transit layer 40) above the underlayer 20 made of AlN crystal, so that the layers above the underlayer 20 can be grown with a low dislocation density at the growth temperature of the Group III nitride crystal.

[0179] (b) Furthermore, in this embodiment, an intermediate layer 30 made of AlGaN crystal, which has an intermediate composition between the underlayer 20 made of AlN crystal and the electron transit layer 40 made of GaN crystal, is interposed between them. The intermediate layer 30 has a low dislocation density inheriting the dislocation density of the underlayer 20 as described above, and contains Ga, which weakens the bonding strength between atoms. This allows the electron transit layer 40 made of GaN crystal to be grown in a nearly strain-free state on the intermediate layer 30 made of AlGaN crystal at the growth temperature of Group III nitride crystal.

[0180] Here, the mechanism by which the intermediate layer 30 made of AlGaN crystals, which have a low dislocation density, allows the electron transit layer 40 made of GaN crystals to grow in a nearly strain-free state is not clear at present. However, the following mechanism, for example, is thought to be the case.

[0181] The atomic bonds in AlN are stronger than those in GaN, which means that atomic planes are less likely to slide between the AlN and GaN layers, allowing the GaN layer to grow coherently on the AlN layer.

[0182] In contrast, the AlGaN layer contains GaN, which weakens the interatomic bond. This makes it easier for atomic planes to slide between the AlGaN layer and the GaN layer. This atomic plane sliding phenomenon is thought to relieve the crystal distortion in the GaN layer when the GaN layer grows on the AlGaN layer.

[0183] In another study, the AlN crystal underlayer had a high dislocation density (e.g., 10 10 cm -2 It has also been confirmed that when the AlGaN layer has a strain-free interface (for example, when the Al composition ratio x of the AlGaN layer is in the range of 0.5 to 1), the GaN layer grown on the AlGaN layer does not become strain-free. This is thought to be because, when there are many dislocations, the dislocations hinder slippage at the interface between the GaN layer and the AlGaN layer.

[0184] Conversely, in this embodiment, the phenomenon in which the electron transit layer 40 made of GaN crystal grows in a nearly strain-free state on the intermediate layer made of AlGaN crystal having a low dislocation density is considered to be a phenomenon specific to the presence of the underlayer 20 made of AlN crystal having a low dislocation density.

[0185] In this embodiment, by using the mechanism described above, the electron transit layer 40 made of GaN crystal is grown in a nearly strain-free state on the intermediate layer 30 made of AlGaN crystal, so that the electron transit layer 40 made of GaN crystal has tensile strain in the direction along the main surface 11 of the substrate 10 at 27° C. based on the magnitude relationship and absolute value of the linear expansion coefficients described above.

[0186] As described above, by growing the electron transit layer 40 made of GaN crystal in a nearly strain-free state, it is possible to suppress the occurrence of new dislocations due to crystal strain in the electron transit layer 40, which has a low dislocation density inherited from the underlayer 20 via the intermediate layer 30. As a result, it is possible to obtain an electron transit layer 40 with good crystallinity.

[0187] As described above, according to this embodiment, it is possible to obtain a high-quality semiconductor laminate 1 and semiconductor element 2.

[0188] (c) In this embodiment, the electron transit layer 40 is grown in a nearly strain-free state at the growth temperature of GaN, so that the crystallinity of the electron transit layer 40 can be improved even if the thickness of the electron transit layer 40 is made thin. Specifically, the thickness of the electron transit layer 40 is 1 μm or less, the half-width of the (0002) diffraction of the electron transit layer 40 measured by X-ray rocking curve is 300 seconds or less, and the half-width of the (10-12) diffraction of the electron transit layer 40 measured by X-ray rocking curve is 410 seconds or less. By improving the crystallinity of the electron transit layer 40 in this way, the mobility of the electron transit layer 40 can be improved, and degradation of the gate electrode can be suppressed, thereby improving the reliability of the element.

[0189] <Other embodiments> The above describes the embodiments of the present disclosure in detail. However, the present disclosure is not limited to the above-described embodiments, and various modifications are possible without departing from the spirit of the present disclosure. Note that "the above-described embodiments" includes the first embodiment and the second embodiment.

[0190] In the above embodiment, the intermediate layer 30 is made of AlGaN crystal, but the present disclosure is not limited to this case. The intermediate layer 30 may be made of, for example, either aluminum indium nitride (AlInN) or aluminum indium gallium nitride (AlInGaN) crystal. InN crystal is also known as a crystal with weaker bonding strength than AlN crystal. Therefore, even when the intermediate layer 30 is made of AlIN crystal or AlInGaN crystal, it is possible to obtain the strain relaxation effect due to the sliding phenomenon of atomic planes, similar to the case where the intermediate layer 30 is made of AlGaN crystal.

[0191] In the above embodiment, the cap layer 60 is provided, but the cap layer 60 may be omitted.

[0192] In the above embodiment, nothing is provided on the region of the upper surface of the cap layer 60 other than the electrodes, but a protective film may be provided so as to cover the region of the upper surface of the cap layer 60 other than the electrodes. Examples of the protective film include silicon nitride (SiN).

[0193] In the above embodiment, the semiconductor element 2 is configured as a so-called MES gate (Metal-Semiconductor) type in which the gate electrode 61 is in direct contact with a semiconductor layer such as the electron supply layer 50. However, the semiconductor element 2 may be configured as a so-called MIS gate (Metal-Insulator-Semiconductor) type in which an insulating layer made of silicon oxide (SiO2), aluminum oxide (Al2O3), or the like is inserted between a semiconductor layer such as the electron supply layer 50 and the gate electrode 61.

[0194] In the above embodiment, the case where the underlayer 20 is grown by the HVPE method has been described, but the underlayer 20 may also be grown by the MOVPE method.

[0195] In the above embodiment, the intermediate layer 30 and the electron transit layer 40 are grown by MOVPE. However, at least one of the intermediate layer 30 and the electron transit layer 40 may be grown by HVPE. EXAMPLES

[0196] Various experimental results that support the effects of the present disclosure will be described below.

[0197] (1) Experiment 1 (1-1) Preparation of semiconductor laminate Under the following conditions, multiple stacked structures with different Al composition ratios in the intermediate layer made of AlGaN crystal were produced.

[0198] [Laminate manufacturing conditions] (substrate) Material: SiC (semi-insulating) Diameter: 4 inches Thickness: 400μm The closest low-index crystal plane to the main surface: c-plane (no patterning on the main surface) Poly type: 6H

[0199] (base layer) Material:AlN Growth method: HVPE method Growth temperature: 1020℃ Growth pressure: 0.987atm (100kPa) V / III ratio: 50 Growth rate: 100nm / min Thickness: 400nm

[0200] (Annealing process) Atmosphere: N2 gas Annealing temperature: 1400℃ Annealing time: 60 minutes

[0201] (Middle class) Material: AlGaN (or AlN) Growth method: MOVPE method Growth temperature: 1020℃ Growth pressure: 0.1atm V / III ratio: 10 Growth rate: 5nm / min Thickness: 80nm Furthermore, there is no intentional doping of impurities. Al composition ratio: varied within the range of 65% to 100%.

[0202] (Electron transport layer) Material: GaN Growth method: MOVPE method Growth conditions: The following conditions are used for step-flow growth of GaN crystals. Growth temperature: 1120℃ Growth pressure: 0.4atm TMG flow rate: 50sccm V / III ratio: 5000 Growth rate: 20nm / min Furthermore, there is no intentional doping of impurities. Thickness: 400nm

[0203] (1-2) Evaluation (X-ray diffraction measurement: 2θ-ω scan) X-ray diffraction measurements (2θ-ω scan) were performed on each of the laminates in Experiment 1 described above. As a result, the distortion of the underlayer was confirmed based on the angle of the (0002) diffraction peak of AlN constituting the underlayer. The Al composition ratio of the intermediate layer was calculated based on the angle of the diffraction peak of Al(Ga)N constituting the intermediate layer. Furthermore, the angle 2θ of the (0002) diffraction peak of GaN constituting the electron transport layer was calculated.

[0204] (X-ray rocking curve measurement) For each of the laminates in the above-mentioned Experiment 1, X-ray rocking curve measurements were performed for the (0002) diffraction of the GaN constituting the electron transit layer, and for the (10-12) diffraction of the GaN constituting the electron transit layer. As a result, the full width at half maximum (FWHM) of the (0002) diffraction of the GaN and the full width at half maximum of the (10-12) diffraction of the GaN were obtained.

[0205] (1-3) Results (Distortion of the base layer) As a result of 2θ-ω scanning as an X-ray diffraction measurement, the angle of the (0002) diffraction peak of the AlN constituting the underlayer was smaller than the angle of the (0002) diffraction peak of fully relaxed AlN (bulk AlN) in all the laminates. This means that at room temperature, the c-axis length of the underlayer has shrunk, i.e., the a-axis length of the underlayer has expanded. This confirmed that at room temperature, the underlayer made of AlN crystals has tensile strain in the direction along the main surface of the substrate.

[0206] (Dependence of strain in the electron transport layer on the Al composition ratio of the intermediate layer) As shown in FIG. 4B, when the Al composition ratio of the intermediate layer is 100%, the angle 2θ of the (0002) diffraction peak of GaN constituting the electron transit layer is slightly smaller than the angle (34.567°) of the (0002) diffraction peak of fully relaxed GaN (bulk GaN). This means that the c-axis length of the electron transit layer is elongated, that is, the a-axis length of the electron transit layer is shortened. From this, it was confirmed that when the intermediate layer is AlN, the electron transit layer has compressive strain in the direction along the main surface of the substrate at room temperature. Considering that the linear expansion coefficients of GaN and AlN are larger than the linear expansion coefficient of SiC constituting the substrate, in this case, it is considered that the electron transit layer made of GaN crystals was subjected to strong compressive strain at the growth temperature of the electron transit layer. Considering that the lattice constant of AlN is smaller than that of GaN, it is considered that the electron transit layer made of GaN crystals was coherently grown on the intermediate layer made of AlN crystals at least in the initial growth stage, and therefore the electron transit layer was subjected to compressive strain at the growth temperature of the electron transit layer.

[0207] In contrast, when the Al composition ratio of the intermediate layer was made smaller than 100%, particularly when it was set to 96% or less, the angle 2θ of the (0002) diffraction peak of the GaN constituting the electron transit layer was larger than the angle of the (0002) diffraction peak of fully relaxed GaN. This means that the c-axis length of the electron transit layer was shortened, i.e., the a-axis length of the electron transit layer was lengthened. This confirmed that the presence of the intermediate layer made of AlGaN crystals caused the electron transit layer to have tensile strain in the direction along the main surface of the substrate at room temperature.

[0208] As the Al composition ratio of the intermediate layer decreased, the angle 2θ of the (0002) diffraction peak of the GaN constituting the electron transit layer gradually increased. This means that as the Al composition ratio of the intermediate layer decreased, the c-axis length of the electron transit layer gradually decreased, i.e., the a-axis length of the electron transit layer gradually increased. From this, it was confirmed that the absolute value of the strain amount as the tensile strain of the electron transit layer increased as the Al composition ratio of the intermediate layer decreased.

[0209] (Dependence of crystallinity of electron transport layer on Al composition ratio of intermediate layer) 4A, when the Al composition ratio of the intermediate layer was 100%, the half-width of the (0002) diffraction of the GaN constituting the electron transport layer was more than 270 arc seconds, and the half-width of the (10-12) diffraction was more than 410 arc seconds. From this, it is considered that when the Al composition ratio of the intermediate layer was 100%, that is, when no intermediate layer made of AlGaN crystal was provided, compressive strain was generated in the electron transport layer at the growth temperature of the electron transport layer, and the crystallinity of the electron transport layer was reduced (the dislocation density was increased).

[0210] In contrast, when the Al composition ratio of the intermediate layer was less than 100%, the half-width of the (0002) diffraction of the GaN constituting the electron transit layer was 270 arc seconds or less, and the half-width of the (10-12) diffraction was 410 arc seconds or less. This confirmed that the inclusion of an intermediate layer made of AlGaN crystals enabled the electron transit layer to be grown in a nearly distortion-free state at the growth temperature of the electron transit layer, improving the crystallinity of the electron transit layer.

[0211] As the Al composition ratio of the intermediate layer decreased within the range of 96% or less, the half-width of each diffraction of the electron transport layer gradually decreased. This confirmed that as the Al composition ratio of the intermediate layer decreased, the lattice distortion of the electron transport layer could be further alleviated at the growth temperature of the electron transport layer, and the crystallinity of the electron transport layer could be stably improved.

[0212] (2) Experiment 2 (2-1) Preparation of semiconductor laminate Except for varying the thickness of the electron transport layer within the range of 100 nm to 1 μm, multiple laminates were fabricated under the same conditions as in Experiment 1. In Experiment 2, the Al composition ratio of the intermediate layer was set to 84%.

[0213] (2-2) Evaluation (X-ray rocking curve measurement) For each of the laminates in the above-mentioned Experiment 2, X-ray rocking curve measurements were performed for the (0002) diffraction of the GaN constituting the electron transit layer, and for the (10-12) diffraction of the GaN constituting the electron transit layer. As a result, the full width at half maximum (FWHM) of the (0002) diffraction of the GaN and the full width at half maximum of the (10-12) diffraction of the GaN were obtained.

[0214] (Observation by multiphoton excitation microscope) In each of the laminates in the above-described Experiment 2, the main surface of the electron supply layer was observed using a multiphoton excitation microscope, and the dislocation density in the main surface of the electron supply layer was obtained.

[0215] (1-3) Results (Dependence of crystallinity of electron transport layer on thickness of electron transport layer) 5A and 5B, when the thickness of the electron transit layer was in the range of 100 nm to 1 μm, the half-width of the (0002) diffraction of the GaN constituting the electron transit layer was 300 arc seconds or less, and the half-width of the (10-12) diffraction was 410 arc seconds or less. This confirmed that by growing the electron transit layer in a nearly strain-free state, the crystallinity of the electron transit layer could be improved even when the thickness of the electron transit layer was 1 μm or less.

[0216] (dislocation density) Observation using a multiphoton excitation microscope revealed that the dislocation density on the main surface of the electron supply layer was 5×10 8 cm -2 From this, it was confirmed that by growing the electron transport layer in a nearly strain-free state, it was possible to reduce the dislocation density of the electron transport layer without three-dimensionally growing the layer thickly.

[0217] <Preferred aspects of the present disclosure> Preferred aspects of the present disclosure will be described below.

[0218] (Appendix 1) a substrate made of silicon carbide and having a primary surface; a first layer formed on the main surface of the substrate and made of aluminum nitride crystals; a second layer formed on the first layer and made of any one of aluminum gallium nitride, aluminum indium nitride, and aluminum indium gallium nitride crystals; a third layer formed on the second layer and made of gallium nitride crystal; Equipped with The first layer has a tensile strain in a direction along the major surface at 27°C. Semiconductor laminate.

[0219] (Appendix 2) The third layer has a tensile strain at 27° C. in a direction along the main surface. 2. The semiconductor laminate of claim 1.

[0220] (Appendix 3) The third layer has a thickness of 1 μm or less, the third layer has a (0002) diffraction full width at half maximum of 300 arc seconds or less as measured by an X-ray rocking curve; The (10-12) diffraction half-width of the third layer measured by X-ray rocking curve measurement is 410 arcseconds or less. 3. The semiconductor laminate according to claim 1 or 2.

[0221] (Appendix 4) The dislocation density on the main surface of the third layer is 1×10 9 cm -2 Is less than or equal to 4. The semiconductor laminate according to claim 1,

[0222] (Appendix 5) The thickness of the first layer is 200 nm or more and 800 nm or less. 5. The semiconductor laminate according to claim 1,

[0223] (Appendix 6) The second layer is coherently disposed on the first layer. 6. The semiconductor laminate according to claim 1,

[0224] (Appendix 7) The second layer is Al x Ga 1-x It consists of crystals represented by the formula N, The Al composition ratio x in the second layer is 0.75 or more and 0.96 or less. 7. The semiconductor laminate according to claim 1,

[0225] (Appendix 8) The oxygen concentration in the third layer is 1×10 16 cm -3 Is less than or equal to 8. The semiconductor laminate according to claim 1,

[0226] (Appendix 9) The silicon concentration in the third layer is 1×10 16 cm -3 Is less than or equal to 9. The semiconductor laminate according to claim 1,

[0227] (Appendix 10) The iron concentration and the carbon concentration in the third layer are each 1×10 16 cm -3 Is less than or equal to 10. The semiconductor laminate according to claim 1,

[0228] (Appendix 11) At 27° C., the strain ε3 in the c-axis direction of the third layer calculated by the following formula (3) is −0.1% or more and less than −0.01%. ε3=(c3-c GaN ) / c GaN ×100 (3) Where: c3 is the c-axis length of the GaN crystal constituting the third layer, c GaN is the c-axis length of an unstrained bulk GaN crystal 11. The semiconductor laminate according to claim 1.

[0229] (Appendix 12) The semiconductor device further includes a fourth layer formed on the third layer and made of a Group III nitride crystal having a band gap wider than that of gallium nitride. 12. The semiconductor laminate according to claim 1.

[0230] (Appendix 13) The third layer of the semiconductor laminate according to any one of Supplementary Note 1 to Supplementary Note 12 is included as at least a part of an operating layer. Semiconductor element.

[0231] (Appendix 14) (a) providing a substrate made of silicon carbide and having a primary surface; (b) growing a first layer composed of aluminum nitride crystals on the primary surface of the substrate; (c) annealing the first layer; (d) growing a second layer of aluminum gallium nitride, aluminum indium nitride, or aluminum indium gallium nitride crystal on the first layer; (e) growing a third layer of gallium nitride crystal on the second layer; Equipped with In step (c), the first layer is annealed to reduce the dislocation density in the main surface of the first layer to a value lower than the dislocation density in the main surface of the first layer immediately after step (b). A method for producing a semiconductor laminate.

[0232] (Appendix 15) (c) Later, A tensile strain is applied to the first layer in a direction along the main surface of the substrate at 27°C. A method for producing a semiconductor laminate according to claim 14.

[0233] (Appendix 16) In (e), The third layer is grown at 27° C. such that the third layer is under tensile strain in a direction along the major surface of the substrate. A method for producing a semiconductor laminate according to claim 14 or 15. [Explanation of symbols]

[0234] 1. Semiconductor laminate (laminate) 2. Semiconductor elements 10 Substrate 20 Base layer 30 Middle Class 40 Electron transport layer 50 Electron supply layer 60 Cap Layer

Claims

1. a substrate made of silicon carbide and having a primary surface; a first layer formed on the main surface of the substrate and made of aluminum nitride crystals; a second layer provided on the first layer and made of any one of aluminum gallium nitride, aluminum indium nitride, and aluminum indium gallium nitride crystals; a third layer formed on the second layer and made of gallium nitride crystal; Equipped with The first layer has a tensile strain in a direction along the major surface at 27°C. Semiconductor laminate.

2. The third layer has a tensile strain at 27° C. in a direction along the main surface. The semiconductor laminate according to claim 1 .

3. The third layer has a thickness of 1 μm or less, the third layer has a (0002) diffraction half width of 300 arc seconds or less as measured by an X-ray rocking curve; The third layer has a (10-12) diffraction half-width of 410 seconds or less as measured by an X-ray rocking curve. The semiconductor laminate according to claim 1 or 2.

4. The dislocation density in the main surface of the third layer is 1×10 ９ cm －２ is less than or equal to The semiconductor laminate according to claim 1 or 2.

5. The thickness of the first layer is 200 nm or more and 800 nm or less. The semiconductor laminate according to claim 1 or 2.

6. The second layer is coherently disposed on the first layer. The semiconductor laminate according to claim 1 or 2.

7. The second layer is Al ｘ G １－ｘ The crystal is represented by the formula: The Al composition ratio x in the second layer is 0.75 or more and 0.96 or less. The semiconductor laminate according to claim 1 or 2.

8. The oxygen concentration in the third layer is 1×10 １６ cm －３ is less than or equal to The semiconductor laminate according to claim 1 or 2.

9. The silicon concentration in the third layer is 1×10 throughout the third layer except for a region from the main surface of the third layer to a depth of 200 nm. １６ cm －３ is less than or equal to The semiconductor laminate according to claim 1 or 2.

10. The iron concentration and the carbon concentration in the third layer are each 1×10 to 1×10 throughout the third layer except for a region from the main surface of the third layer to a depth of 200 nm. １６ cm －３ is less than or equal to The semiconductor laminate according to claim 1 or 2.

11. At 27° C., the strain ε in the c-axis direction of the third layer is calculated by the following formula (3): ３ is -0.1% or more and less than -0.01%; ε ３ =(c ３ -c ＧａＮ ) / c ＧａＮ ×100 ・・・(3) Where: c ３ is the c-axis length of the GaN crystal constituting the third layer, c ＧａＮ is the c-axis length of the unstrained bulk GaN crystal The semiconductor laminate according to claim 1 or 2.

12. The third layer of the semiconductor laminate according to claim 1 or 2 is provided as at least a part of an operating layer. Semiconductor element.

13. (a) providing a substrate made of silicon carbide and having a primary surface; (b) growing a first layer of aluminum nitride crystals on the primary surface of the substrate; (c) annealing the first layer; (d) growing a second layer of aluminum gallium nitride, aluminum indium nitride, or aluminum indium gallium nitride crystal on the first layer; (e) growing a third layer of gallium nitride crystal on the second layer; Equipped with In step (c), the first layer is annealed to reduce the dislocation density in the main surface of the first layer to a level lower than the dislocation density in the main surface of the first layer immediately after step (b). A method for producing a semiconductor laminate.

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