DC / DC converter

Abstract

To provide a DAB-based DC / DC converter capable of realizing synchronous rectification control that can reduce loss without involving an increase in the size and the cost of a circuit.SOLUTION: A control circuit 3 of a converter according to the present invention performs synchronous rectification control on a switching circuit 2 for, during a switching operation based on DAB, turning on a switching element (S8 / S7) of a lower arm or an upper arm to which a first or second capacitor (Cc / Cd) of a switching circuit 2 is not connected in parallel on the basis of a timing of turning on a switching element (S1 / S2) of the upper arm or the lower arm to which a first or second capacitor (Ca / Cb) of a switching circuit 1 is not connected in parallel, and making an off-timing of the switching element (S8 / S7) earlier than the turning off the switching element (S1 / S2) of the upper or lower arm to which the first or second capacitor (Ca / Cb) of the switching circuit 1 is not connected in parallel.SELECTED DRAWING: Figure 11

Description

[Technical field]

[0001] The present disclosure relates to a DC / DC converter of a DAB (Dual Active Bridge) type. [Background technology]

[0002] In a DC / DC converter in which the input and output sides are isolated by a transformer, when synchronous rectification control is applied to a switching element on the secondary side, a common method is to detect the current flowing through the body diode of the switching element to which synchronous rectification control is applied, and turn on the gate (switch element) when the current value exceeds a certain threshold, and turn off the gate (switch element) when the value falls below the threshold (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 5818235 [Patent Document 2] JP 2014-075944 A Summary of the Invention [Problem to be solved by the invention]

[0004] Among DC / DC converters, there are DAB DC / DC converters capable of bidirectional power conversion (see, for example, Patent Document 2). It is conceivable to apply synchronous rectification control to such DAB DC / DC converters. Here, if an attempt is made to provide the DAB DC / DC converter with a dedicated circuit for detecting the current flowing through the body diode in order to perform synchronous rectification control, as in Patent Document 1, this would result in an increase in the size of the circuit and an increase in costs. Furthermore, in the case of synchronous rectification control using current detection, setting the current detection threshold lower shortens the period during which current flows through the body diode of the switching element, thereby reducing losses, but there is a possibility that a delay in the gate off timing will occur due to a delay in current detection. For this reason, there is a limit to how low the current detection threshold can be set in consideration of the current detection delay, and there is also the issue that it is difficult to further reduce losses in the rectification operation.

[0005] Therefore, in order to solve the above problems, an object of the present invention is to provide a DAB type DC / DC converter that can realize synchronous rectification control that can reduce losses in the rectification operation without increasing the size and cost of the circuit. [Means for solving the problem]

[0006] In order to achieve the above object, a DC / DC converter according to the present invention determines the on / off timing of a switching element used for synchronous rectification by utilizing signals that turn other switching elements on and off and measured values ​​of input / output voltages.

[0007] Specifically, the DC / DC converter according to the present invention comprises: A transformer (11) having a primary winding and a secondary winding; A first leg (12) and a second leg (13) are connected in parallel between two terminals (Ter1 & Ter2) as upper and lower arms of switching elements (S1-S4) each having a switch element (Q1-Q4) to which an anti-parallel diode (D1-D4) and a parallel capacitor (C1-C4) are connected in parallel, respectively. One of the switching elements (S1 / S2 / S3 / S4) of the upper or lower arm of the first leg or the second leg (12 / 13) or one of the switching elements (S1 / S2 / S3 / S4) of the upper arm or the lower arm of the first leg and the second leg (12 & 13) is connected in parallel. a first capacitor (Ca) connected in parallel to the other switching element (S1 / S2 / S3 / S4) of the upper or lower arm of the first leg or the second leg (12 / 13), and a second capacitor (Cb) connected in parallel to the other switching element (S1 / S2 / S3 / S4) of the upper arm or the lower arm of the first leg and the second leg (12&13), the two switching circuits (1&2) being connected to the primary winding (11a) side of the transformer and the secondary winding (11b) side of the transformer, respectively; an inductance means (L) connected between a connection point of the upper and lower arms of the first leg (12) and a connection point of the upper and lower arms of the second leg (13) on the primary winding (11a) side or the secondary winding (11b) side of the transformer, via the primary winding (11a) or the secondary winding (11b); A control circuit (3) for controlling the switching of the switching circuits (1 & 2); The control circuit includes: a zero-voltage switching control for one of the switching circuits (1 / 2) in which a switching element (S1 / S3) of an upper arm of the first or second leg (12 / 13) and a switching element (S4 / S2) of a lower arm of the second or first leg (13 / 12) are alternately turned on and off in a pair to convert a direct current input from the two terminals (Ter1&Ter2) into an alternating current and output it from the switching circuit (1 / 2), and in alternately controlling the on and off of the pair of switching elements (S1&S4 / S3&S2), among the pair of the switching element (S1 / S3) of the upper arm of the first or second leg (12 / 13) and the switching element (S4 / S2) of the lower arm of the second or first leg (13 / 12) that are in an on state, the switching element (S3 / S4) to which the first capacitor or the second capacitor (Ca / Cb) is connected in parallel is turned off first; synchronous rectification control for turning on the switching element (S2 / S1[S8 / S7]) of the lower arm or upper arm to which the first capacitor or the second capacitor (Ca / Cb[Cc / Cd]) of the other switching circuit (2 / 1) is not connected in parallel based on a timing of turning on the switching element (S1 / S2) of the upper arm or lower arm to which the first capacitor or the second capacitor (Ca / Cb) of one of the switching circuits (1 / 2) is not connected in parallel, and setting the off timing of the switching element (S2 / S1[S8 / S7]) to be earlier than the turning off of the switching element (S1 / S2) of the upper arm or lower arm to which the first capacitor or the second capacitor (Ca / Cb) of one of the switching circuits (1 / 2) is not connected in parallel; The present invention is characterized by carrying out the following steps.

[0008] This DC / DC converter operates the switching elements used for synchronous rectification control using signals that turn the switching elements on and off and measured values ​​of input and output voltages, so there is no need for a circuit to detect the current flowing through the body diode of the switching element (i.e., a current detection circuit for synchronous rectification control).As a result, this DC / DC converter can avoid the increase in circuit size and cost that accompanies the introduction of synchronous rectification control.

[0009] In addition, this DC / DC converter does not use detection of the current flowing through the body diode of the switching element for synchronous rectification control, so there is no need to consider detection delays and it is possible to extend the gate-on period of the switching element used for synchronous rectification. As a result, this DC / DC converter can reduce losses in the rectification operation.

[0010] Therefore, the present invention can provide a DAB DC / DC converter that can realize synchronous rectification control that can reduce losses in the rectification operation without increasing the size and cost of the circuit. Effect of the Invention

[0011] The present invention can provide a DAB DC / DC converter that can realize synchronous rectification control that can reduce losses in the rectification operation without increasing the size and cost of the circuit. [Brief description of the drawings]

[0012] [Figure 1] 1 is a configuration diagram of a DC / DC converter (bidirectional converter) according to the present invention. [Diagram 2] FIG. 11 is a waveform diagram showing an example of drive signals for switching elements S1 to S4 of switching circuit 1 and switching elements S5, S6 of switching circuit 2 when switching elements S5, S6 of switching circuit 2 are turned on and off in the DC / DC converter according to the present invention. [Diagram 3]2 is a waveform diagram showing an example of the voltages and currents of switching elements S1 to S4 of switching circuit 1 and the excitation current of transformer 11 when switching elements S5 and S6 of switching circuit 2 are turned on and off in the DC / DC converter according to the present invention. FIG. [Figure 4] FIG. 11 is a waveform diagram showing an example of the voltage and current of the switching elements S5 and S6 of the switching circuit 2 and the voltage and current of the anti-parallel diodes D7 and D8 when the switching elements S5 and S6 of the switching circuit 2 are turned on and off in the DC / DC converter according to the present invention. [Diagram 5] FIG. 4 is an enlarged waveform diagram of a part of the waveform diagram of FIG. 3. [Figure 6] 3 is a circuit diagram formed at each timing when switching elements S5, S6 of a switching circuit 2 are turned on and off in a DC / DC converter according to the present invention. FIG. [Figure 7] FIG. 13 is an example of a waveform diagram showing drive signals for switching elements S1 to S4 of switching circuit 1 and switching elements S5 to S8 of switching circuit 2 in an operation for lowering the voltage output between the third terminal Ter3 and the fourth terminal Ter4 to be lower than the output voltage obtained by turning on and off switching elements S5, S6 of switching circuit 2 in a DC / DC converter according to the present invention. [Figure 8] FIG. 11 is a waveform diagram showing an example of the voltages and currents of the switching elements S1 to S4 of the switching circuit 1 and the excitation current of the transformer 11 in the DC / DC converter according to the present invention, in an operation for making the voltage output between the third terminal Ter3 and the fourth terminal Ter4 lower than the output voltage obtained by the operation for turning on and off the switching elements S5, S6 of the switching circuit 2. [Figure 9] FIG. 11 is a waveform diagram showing an example of the voltages and currents of the anti-parallel diodes D5 to D8 of the switching circuit 2 in the DC / DC converter according to the present invention, in an operation for making the voltage output between the third terminal Ter3 and the fourth terminal Ter4 lower than the output voltage obtained by the operation for turning on and off the switching elements S5, S6 of the switching circuit 2. [Figure 10]FIG. 11 is a circuit diagram formed at each timing for an operation of making the voltage output between the third terminal Ter3 and the fourth terminal Ter4 lower than the output voltage obtained by turning on and off the switching elements S5, S6 of the switching circuit 2 in the DC / DC converter according to the present invention. [Figure 11] 3 is a diagram for explaining synchronous rectification control performed by a control circuit of the DC / DC converter according to the present invention. FIG. [Figure 12] 3 is a diagram for explaining synchronous rectification control performed by a control circuit of the DC / DC converter according to the present invention. FIG. [Figure 13] 3 is a diagram for explaining synchronous rectification control performed by a control circuit of the DC / DC converter according to the present invention. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] The embodiments of the present invention will be described with reference to the accompanying drawings. The embodiments described below are examples of the present invention, and the present invention is not limited to the following embodiments. Note that components with the same reference numerals in this specification and drawings indicate the same components.

[0014] (Circuit configuration) FIG. 1 is a diagram illustrating a DC / DC converter 301 according to this embodiment. Converter 301 includes a transformer 11, a switching circuit 1 connected to a primary winding 11a of the transformer 11, a second circuit 2 connected to a secondary winding 11b of the transformer 11, an inductance means L, and a control circuit 3. This converter converts DC input from the first terminal Ter1 and the second terminal Ter2 to AC and outputs it from the switching circuit 1, and converts the AC to DC in the switching circuit 2 via the transformer 11 to supply power to the third terminal Ter3 and the fourth terminal Ter4 on the output side. Note that in this explanation, two terminals (Ter1 and Ter2) are the input side and two terminals (Ter3 and Ter4) are the output side, but since the circuit configuration is symmetrical with respect to the transformer 11, the converter operates in the same way even if the input and output are reversed.

[0015] The switching circuit 1 includes a first leg (12) and a second leg (13) in which upper and lower arms are connected in parallel between two terminals (Ter1 & Ter2) with switching elements (S1-S4) having switch elements (Q1-Q4) with anti-parallel diodes (D1-D4) and parallel capacitors (C1-C4) connected in parallel, respectively, and a switching element (S1 / S2 / S3 / S4) in one of the upper and lower arms of the first leg or the second leg (12 / 13) or a switching element (S1 / S2 / S3 / S4) in one of the upper and lower arms of the first leg and the second leg (12 / 13). The first leg (12&13) has a first capacitor (Ca) connected in parallel to one of the switching elements (S1 / S2 / S3 / S4) of the upper arm or the lower arm of the first leg (12&13), and a second capacitor (Cb) connected in parallel to the other of the switching elements (S1 / S2 / S3 / S4) of the upper or lower arm of the first leg (12&13) or the other of the switching elements (S1 / S2 / S3 / S4) of the upper arm or the lower arm of the first leg and the second leg (12&13).

[0016] The first leg 12 and the second leg 13 are connected in parallel between the first terminal and the second terminal, respectively. The first leg 12 has switching elements S1 and S2 as upper and lower arms, and the second leg 13 has switching elements S3 and S4 as upper and lower arms. In Fig. 1, switching elements S1 to S4 are used, in which anti-parallel diodes D1 to D4 and parallel capacitors C1 to C4 are connected in parallel to the switching elements Q1 to Q4, respectively. That is, the anti-parallel diodes D1 to D4 are internal diodes of the switching elements S1 to S4, and the parallel capacitors C1 to C4 are parasitic capacitances of the switching elements S1 to S4.

[0017] In the present invention, the anti-parallel diodes D1 to D4 connected in parallel to the switching elements Q1 to Q4 may be internal diodes of the switching elements S1 to S4 as shown in Fig. 1, or external diodes separately from the switching elements S1 to S4, or a combination of these. Similarly, the parallel capacitors C1 to C4 connected in parallel to the switching elements Q1 to Q4 may be parasitic capacitances of the switching elements S1 to S4 as shown in Fig. 1, or external capacitors separately from the switching elements S1 to S4, or a combination of these.

[0018] The first capacitor Ca and the second capacitor Cb are connected in parallel to the switching elements S1 and S4 or S2 and S3 that are to be turned off first in a pair of switching circuits 1. In Fig. 1, the first capacitor Ca and the second capacitor Cb are connected in parallel to the switching elements S3 and S4 of the upper and lower arms of the second leg 13 that are to be turned off first, respectively.

[0019] Electric power is input from an external power supply to the first terminal Ter1 and the second terminal Ter2. A capacitor 16 is connected between the first terminal Ter1 and the second terminal Ter2 to provide a DC voltage. Furthermore, a switching circuit 1 is connected between the first terminal Ter1 and the second terminal Ter2, and as described above, the switching circuit 1 is a full-bridge circuit in which the upper and lower arms of the first leg 12 and the second leg 13 are configured with switching elements S1 to S4.

[0020] Furthermore, the detection means 19 detects the voltage between the first terminal Ter1 and the second terminal Ter2, or the current or power input to or output from the switching circuit 1 via the first terminal Ter1 and the second terminal Ter2.

[0021] The switching circuit 2 has a circuit configuration that is a mirror image of the switching circuit 1 with a transformer 11 in between. However, for ease of explanation, different reference symbols are used in this embodiment as follows. The left column indicates the reference symbols of the switching circuit 1, and the right column indicates the reference symbols of the corresponding switching circuit 2. 1st terminal Ter1 3rd terminal Ter3 2nd terminal Ter2 4th terminal Ter4 1st leg 12 4th leg 25 2nd Leg 13 3rd Leg 24 Switching element S1 Switching element S7 Switching element S2 Switching element S8 Switching element S3 Switching element S5 Switching element S4 Switching element S6 Switch element Q1 Switch element Q7 Switch element Q2 Switch element Q8 Switch element Q3 Switch element Q5 Switch element Q4 Switch element Q6 Anti-parallel diode D1 Anti-parallel diode D7 Anti-parallel diode D2 Anti-parallel diode D8 Anti-parallel diode D3 Anti-parallel diode D5 Anti-parallel diode D4 Anti-parallel diode D6 Parallel capacitor C1 Parallel capacitor C7 Parallel capacitor C2 Parallel capacitor C8 Parallel capacitor C3 Parallel capacitor C5 Parallel capacitor C4 Parallel capacitor C6 First capacitor Ca Third capacitor Cc Second capacitor Cb Fourth capacitor Cd

[0022] That is, the switching circuit 2 includes a first leg (25) and a second leg (24) in which upper and lower arms are connected in parallel between two terminals (Ter3 & Ter4) using switching elements (S5-S8) each having a switching element (Q5-Q8) in which an anti-parallel diode (D5-D8) and a parallel capacitor (C5-C8) are connected in parallel, respectively, and one of the switching elements (S7 / S8 / S5 / S6) of the upper and lower arms of the first leg or the second leg (25 / 24) or the first leg (25 / 24) is connected in parallel with the switching element (S7 / S8 / S5 / S6) of the upper and lower arms of the first leg or the second leg (25 / 24). a third capacitor (Cc) connected in parallel to one of the switching elements (S7 / S8 / S5 / S6) of the upper arm or the lower arm of the first leg and the second leg (25&24), and a fourth capacitor (Cd) connected in parallel to the other switching element (S7 / S8 / S5 / S6) of the upper or lower arm of the first leg or the second leg (25 / 24) or the other switching element (S7 / S8 / S5 / S6) of the upper arm or the lower arm of the first leg and the second leg (25&24).

[0023] In addition, like switching circuit 1, in switching circuit 2, anti-parallel diodes D5 to D8 and parallel capacitors C5 to C8 connected in parallel to switch elements Q5 to Q8 may be internal diodes, external diodes, or a combination of these, as well as parasitic capacitances, external capacitors, or a combination of these.

[0024] When the third terminal Ter3 and the fourth terminal Ter4 are on the input side, the third capacitor Cc and the fourth capacitor Cd are connected in parallel to the switching elements S7 and S6 or S8 and S5 that are to be turned off first in a pair of switching circuits 2. In Fig. 1, the third capacitor Cc and the fourth capacitor Cd are connected in parallel to the switching elements S5 and S6 of the upper and lower arms of the second leg 24 that are to be turned off first, respectively.

[0025] A capacitor 17 is connected between the third terminal Ter3 and the fourth terminal Ter4 to provide a DC voltage. Furthermore, a switching circuit 2 is connected between the third terminal Ter3 and the fourth terminal Ter4, and as described above, the switching circuit 2 is a full-bridge circuit in which the upper and lower arms of the first leg 25 and the second leg 24 are configured with switching elements S5 to S8.

[0026] Furthermore, the detection means 18 detects the voltage between the third terminal Ter3 and the fourth terminal Ter4, or the current or power input to or output from the switching circuit 2 via the third terminal Ter3 and the fourth terminal Ter4. In the following description, the detection target is voltage, but the present invention is not limited to voltage, and the same operation and effect can be obtained even if current or power is detected.

[0027] The inductance means L is connected to the connection point side of the upper and lower arms of the first leg 12 and the connection point side of the upper and lower arms of the second leg 13 via the primary winding 11a of the transformer 11. This inductance means L may be connected to the connection point side where the anti-parallel diodes D5 and D6 are connected in series with the same polarity and the other connection point side where the anti-parallel diodes D7 and D8 are connected in series with the same polarity in the bridge connection circuit of the switching circuit 2 via the secondary winding 11b of the transformer 11. Also, in FIG. 1, one end of the inductance means L is connected to the connection point side of the upper and lower arms of the first leg 12 and the other end is connected to the primary winding 11a of the transformer 11, but one end of the inductance means L may be connected to the connection point side of the upper and lower arms of the second leg 13 and the other end to the primary winding 11a of the transformer 11. The same applies to the case where the inductance means L is connected via the secondary winding 11b.

[0028] The control circuit 3 supplies drive signals to the switching elements S1 to S4 of the switching circuit 1 and the switching elements S5 and S6 of the switching circuit 2, respectively, to control the on / off of each switching element.

[0029] (Basic operation) First, the zero voltage switching (ZVS) control will be described. The control circuit 3 includes: For one of the switching circuits (1 / 2), a switching element (S1 / S3) of the upper arm of the first or second leg (12 / 13) and a switching element (S4 / S2) of the lower arm of the second or first leg (13 / 12) are paired and alternately turned on and off to convert the direct current input from the two terminals (Ter1&Ter2) into alternating current and output it from the switching circuit (1 / 2). In controlling the alternate on and off of the switching elements (S1&S4 / S3&S2) constituting the pair, among the switching element (S1 / S3) of the upper arm of the first or second leg (12 / 13) and the switching element (S4 / S2) of the lower arm of the second or first leg (13 / 12) that are in the on state, the switching element (S3 / S4) to which the first capacitor or the second capacitor (Ca / Cb) is connected in parallel is turned off first.

[0030] 1, a switching element S1 or S3 in the upper arm of the first leg 12 or the second leg 13 and a switching element S4 or S2 in the lower arm of the second leg 13 or the first leg 12 are paired and alternately turned on and off. Of the switching elements S1 and S4 of the switching circuit 1 that form a pair, the switching element S4 or S1 is turned off first, and then the switching element S1 or S4 is turned off later. Similarly, of the switching elements S2 and S3 of the switching circuit 1 that form the other pair, the switching element S3 or S2 is turned off first, and then the switching element S2 or S3 is turned off later.

[0031] Next, the energy transition switching control will be described. The detection means 18 of the switching circuit 2 shown in FIG. 1 detects the output voltage of the switching circuit 2 output between the third terminal Ter3 and the fourth terminal Ter4. This output voltage detection value is input to the control circuit 3. The control circuit 3 controls the output voltage of the switching circuit 2 by turning on and off the switching elements S1 to S4 of the switching circuit 1 and the switching elements S5, S6 of the switching circuit 2 based on the output voltage detection value. For example, the control circuit 3 performs pulse control to modulate the pulse width, phase, etc. of the switching elements S1 to S4 of the switching circuit 1 and the switching elements S5, S6 of the switching circuit 2 so that the output voltage detection value approaches a target voltage value according to the load conditions. The detection means 18 of the switching circuit 2, for example, connects a resistor to the output side and detects the voltage applied to this resistor.

[0032] The control circuit 3 controls the amount of energy stored in the inductance means L from the first terminal Ter1 and the second terminal Ter2 side by pulse control of the drive signal given to the switching element S5 or S6 of the switching circuit 2. In this case, during a period in which the switching elements S1 and S4 or the switching elements S2 and S3 of the paired switching circuit 1 are in an on state, the switching element S5 or S6 of the switching circuit 2 is turned on, thereby shorting the secondary winding 11b side of the transformer 11. As a result, the energy input from the first terminal Ter1 and the second terminal Ter2 side is stored in the inductance means L. Next, during a period in which the switching elements S1 and S4 or the switching elements S2 and S3 of the paired switching circuit 1 continue to be in an on state, the switching element S5 or S6 of the switching circuit 2 is turned off. As a result, the energy stored in the inductance means L is supplied to the third terminal Ter3 and the fourth terminal Ter4 side.

[0033] Furthermore, when the control circuit 3 operates to make the voltage output between the third terminal Ter3 and the fourth terminal Ter4 lower than the output voltage obtained by turning on and off the switching elements S5 and S6 of the switching circuit 2, the control circuit 3 pulse-controls the switching elements of the switching circuit 1 and operates the switching elements S5 and S6 of the switching circuit 2 so as not to conduct in the forward direction. Specifically, during a period in which the switching elements S1 and S4 or the switching elements S2 and S3 of a pair of the switching circuit 1 are in the on state, the control circuit 3 pulse-controls the switching elements of the switching circuit 1 so as to supply energy input from the first terminal Ter1 and the second terminal Ter2 to the third terminal Ter3 and the fourth terminal Ter4 via the inductance means L, and operates the switching elements S5 and S6 of the switching circuit 2 so as not to conduct in the forward direction. In this operation, the control circuit 3 does not cause the switching elements S5 and S6 of the switching circuit 2 to conduct in the forward direction, so that the bridge connection circuit of the switching circuit 2 functions as a full-bridge rectifier circuit in which the anti-parallel diodes D5 to D8 are conductive.

[0034] The drive signals will be described below with the drive signal for turning on the switching elements of switching circuit 1 and switching circuit 2 as an on signal, and the drive signal for turning them off as an off signal. Voltage, current, etc. are used as the drive signal. The on signal, off signal, etc. may be a signal given throughout the on / off period, or a signal given for a short time as a trigger, and are not particularly limited.

[0035] Next, an example of the operation (ZVS control and energy transition control) of the converter 301 according to the first embodiment of the present invention will be described. First, a case where the switching elements S5 and S6 of the switching circuit 2 of the converter 301 are turned on and off will be described with reference to Figs. 2 to 6. In the first embodiment, the switching elements S7 and S8 of the switching circuit 2 are always off. Fig. 2 is a waveform diagram showing an example of the driving signals of the switching elements S1 to S4 of the switching circuit 1 and the switching elements S5 and S6 of the switching circuit 2. Fig. 3 is a waveform diagram showing an example of the voltage and current of the switching elements S1 to S4 of the switching circuit 1 and the excitation current of the transformer 11. Fig. 4 is a waveform diagram showing an example of the voltage and current of the switching elements S5 and S6 of the switching circuit 2 and the voltage and current of the anti-parallel diodes D7 and D8. Fig. 5 is an enlarged view of a part of the waveform diagram of Fig. 3, which corresponds to a time Tx portion. Fig. 6 is a circuit diagram formed at each timing. In the current waveforms shown in Figures 3 to 5, the current flowing in the forward direction through switching elements S1 to S4 of switching circuit 1 and switching elements S5 and S6 of switching circuit 2 is positive, and the current flowing in the reverse direction through switching elements S1 to S4 of switching circuit 1 and switching elements S5 and S6 of switching circuit 2 and the current flowing in the forward direction through anti-parallel diodes D7 and D8 are negative.

[0036] At time t1, it is assumed that an ON signal is given to the switching elements S1 and S4 of the paired switching circuit 1. It is assumed that an ON signal is already given to the switching element S6 of the switching circuit 2 before time t1. Then, the switching elements Q1, Q4, and Q6 are forward-conducting. In this state, as shown in FIG. 6(a), a current flows from the first terminal Ter1 side to the switching element Q1, the inductance means L, the primary winding 11a, the switching element Q4, and the second terminal Ter2 side by the input power supplied from the first terminal Ter1 and the second terminal Ter2 side. On the secondary winding 11b side of the transformer 11, a current flows through the secondary winding 11b, the switching element Q6, and the anti-parallel diode D8, and the secondary winding 11b side is in a short-circuit state. Therefore, energy is stored in the inductance means L by the input power supplied from the first terminal Ter1 and the second terminal Ter2 side. Moreover, power is supplied from the capacitor 17 to the third terminal Ter3 and the fourth terminal Ter4.

[0037] At time t2, for example, if an off signal is given to the switching element S6 of the switching circuit 2 at a timing determined by the control circuit 3 so that the voltage detection value between the third terminal Ter3 and the fourth terminal Ter4 detected by the detection means 18 of the switching circuit 2 approaches a target value, the energy stored in the inductance means L starts to be supplied to the output side of the switching circuit 2. As shown in FIG. 6(b), a current continues to flow through the same path on the primary winding 11a side of the transformer 11 from time t1, but the switching element Q6 is in an off state on the secondary winding 11b side. As shown in FIG. 4, at this time t2, the switching element Q6 of the switching circuit 2 is turned off in a state where a large current flows through the switching element S6, so switching loss becomes a problem. As a means for reducing this switching loss, it is considered to lower the voltage across the switching element S6 when the switching element S6 is off.

[0038] In the present invention, the parallel capacitor C6 and the fourth capacitor Cd are connected in parallel to the switching element Q6 to increase the capacitance of the capacitor. Similarly, the parallel capacitor C5 and the third capacitor Cc are connected in parallel to the switching element Q5 to increase the capacitance of the capacitor. When the switching element Q6 is turned off at time t2, as shown in FIG. 6(b), on the secondary winding 11b side, a current flows from the secondary winding 11b through the parallel capacitor C6, the fourth capacitor Cd, and the anti-parallel diode D8 in a direction to charge the parallel capacitor C6 and the fourth capacitor Cd connected in parallel to the turned-off switching element Q6. On the other hand, a discharge current flows from the parallel capacitor C5 and the third capacitor Cc through the third terminal Ter3, the fourth terminal Ter4 side, the anti-parallel diode D8, and the secondary winding 11b. By increasing the capacitance of the capacitor, the rise in the voltage across the switching element S6 of the switching circuit 2 due to the charging and discharging operations of the parallel capacitor C6, the fourth capacitor Cd, the parallel capacitor C5, and the third capacitor Cc can be made gentle. This makes it possible to reduce the switching loss when the switching element S6 of the switching circuit 2 is turned off.

[0039] When the charging and discharging of the parallel capacitor C6 and the fourth capacitor Cd and the parallel capacitor C5 and the third capacitor Cc of the switching circuit 2 ends at time t3, the anti-parallel diode D5 becomes conductive as shown in FIG. 6(c). The current on the secondary winding 11b side flows from the secondary winding 11b through the anti-parallel diode D5, the third terminal Ter3, the fourth terminal Ter4, and the anti-parallel diode D8. The energy stored in the inductance means L is supplied to the output side of the switching circuit 2 between time t1 and time t2. The energy stored in the inductance means L supplies the energy to the load connected to the third terminal Ter3 and the fourth terminal Ter4, and charges the capacitor 17 discharged between time t1 and time t2. The current on the primary winding 11a side continues to flow through the same current path during the period from time t1 to time t4 when the switch element Q4 is turned off.

[0040] At time t4, the control circuit 3 sends an off signal to the switching element S4 of the switching circuit 1, which is to be turned off first among the pair of switching elements S1 and S4 of the switching circuit 1. For this reason, as shown in Fig. 3, the switching element Q4 is turned off when the current value is relatively large, and therefore switching loss occurs when the switching element S4 of the switching circuit 1 is turned off. One possible method for reducing this switching loss is to lower the voltage across the switching element S4 of the switching circuit 1 when the switching element S4 of the switching circuit 1 is turned off.

[0041] In the present invention, the second capacitor Cb is connected in parallel to the switch element Q4 in addition to the parallel capacitor C4 to increase the capacitance of the capacitor. Similarly, the first capacitor Ca is connected in parallel to the switch element Q3 in addition to the parallel capacitor C3 to increase the capacitance of the capacitor. Therefore, when the switch element Q4 is turned off at time t4, as shown in FIG. 6(d), on the primary winding 11a side, a current flows from the inductance means L, the primary winding 11a, the parallel capacitor C4 and the second capacitor Cb, the second terminal Ter2, and the first terminal Ter1 side through the switch element Q1 in a direction to charge the parallel capacitor C4 and the second capacitor Cb connected in parallel to the turned-off switch element Q4. On the other hand, a discharge current flows from the parallel capacitor C3 and the first capacitor Ca through the switch element Q1, the inductance means L, and the primary winding 11a. By increasing the capacitance of the capacitor, the voltage rise across the switching element S4 caused by the charging and discharging operations of the parallel capacitor C4 and the second capacitor Cb, the parallel capacitor C3, and the first capacitor Ca can be made gentle. Therefore, the switching loss when the switching element S4 of the switching circuit 1 is turned off can be reduced.

[0042] At time t5, when the discharge of the parallel capacitor C3 and the first capacitor Ca and the charging of the parallel capacitor C4 and the second capacitor Cb are completed, the anti-parallel diode D3 connected in parallel to the switch element Q3 becomes conductive as shown in Fig. 6(e). On the primary winding 11a side, due to the energy stored in the inductance means L and the excitation current of the transformer 11, a current flows from the inductance means L, the primary winding 11a through the anti-parallel diode D3 and the switch element Q1 in the same direction as the current flowing through the primary winding 11a and the inductance means L immediately before time t5. The current on the secondary winding 11b side continues to flow from time t3 through the secondary winding 11b, the anti-parallel diode D5, the third terminal Ter3 side, the fourth terminal Ter4 side and the anti-parallel diode D8. The period during which the current flows through the current path on the secondary winding 11b side continues from the time when the anti-parallel diode D5 is conductive until the current flowing through the anti-parallel diode D5 becomes almost zero.

[0043] At time t6, the drive signal of the switching element S1, which is to be turned off later among the switching elements S1 and S4 of the paired switching circuit 1, is set to an off signal. Since the switching element Q1 is turned off, a current flows from the primary winding 11a through the anti-parallel diode D3, the parallel capacitor C1, and the inductance means L due to the excitation current of the transformer that was flowing immediately before time t6, and the parallel capacitor C1 is charged. On the other hand, a discharge current flows from the parallel capacitor C2 through the inductance means L, the primary winding 11a, the anti-parallel diode D3, the first terminal Ter1 side, and the second terminal Ter2 side. At this time, the switching element Q1 is turned off while a current is still flowing therethrough, but this current can be made into an excitation current of the transformer 11 with a very small value. Therefore, since the switching element S1 can be turned off later, the current value at the time of turning off can be reduced, and the switching loss can be reduced compared to when the switching element Q4, which is turned off first, is turned off.

[0044] When the charging and discharging of the parallel capacitors C1 and C2 ends at time t7, the anti-parallel diode D2 becomes conductive as shown in Fig. 6(g). On the primary winding 11a side, a current flows from the primary winding 11a through the anti-parallel diode D3, the first terminal Ter1 side, the second terminal Ter2 side, the anti-parallel diode D2, and the inductance means L in the same direction as the current flowing through the primary winding 11a immediately before time t7 due to the excitation current of the transformer 11. Note that the current on the secondary winding 11b side continues to flow from time t3 through the secondary winding 11b, the anti-parallel diode D5, the third terminal Ter3 side, the fourth terminal Ter4 side, and the anti-parallel diode D8. The period during which the current flows through the current path on the secondary winding 11b side continues from the time when the anti-parallel diode D5 is conductive until the current flowing through the anti-parallel diode D5 becomes almost zero.

[0045] At time t8, the drive signals of the switching elements S2 and S3 of the switching circuit 1, which constitute the other pair, are set to ON signals. As shown in FIG. 6(h), on the primary winding 11a side, the switch element Q2 and the switch element Q3 are conducted in the forward direction, and a current flows through the first terminal Ter1 side, the switch element Q3, the primary winding 11a, the inductance means L, the switch element Q2, and the second terminal Ter2 side. On the secondary winding 11b side, an ON signal is given to the drive signal of the switching element S5 of the switching circuit 2 before time t8, and at time t8, the switch element Q5 is in a state in which it can be conducted in the forward direction. Therefore, when the switch element Q5 is conducted in the forward direction, a current flows from the secondary winding 11b through the anti-parallel diode D7 and the switch element Q5, and the secondary winding 11b side is short-circuited. Therefore, energy is stored in the inductance means L by the power input between the first terminal Ter1 and the second terminal Ter2.

[0046] In the present invention, immediately before time t8, the anti-parallel diodes D2 and D3 connected in parallel to the switching elements Q2 and Q3, respectively, are conductive. As a result, as shown in FIG. 5, the switching elements S2 and S3 of the switching circuit 1 can achieve zero voltage switching (ZVS) when turned on.

[0047] Also, since the anti-parallel diode D5 in parallel with the switching element Q5 is conducting immediately before time t8, the switching element Q5 can be turned on at zero voltage. Note that, in order to realize zero voltage switching (ZVS) of the switching element Q5, an on signal which is a drive signal for the switching element S5 of the switching circuit 2 should be provided during the period from time t3 to time 8 during which the anti-parallel diode D5 is conducting.

[0048] The operation of the switching elements S2 and S3 of the switching circuit 1 that constitutes the other pair after time t8 is performed in the same manner as the switching elements S1 and S4 that constitute the above-mentioned pair from time t1 to time t8. That is, during the period in which the switching elements Q2 and Q3 are conductive, an off signal is given to the switching element S5 of the switching circuit 2 at a timing determined by the control circuit 3 so that the voltage detection value between the third terminal Ter3 and the fourth terminal Ter4, which are the output side of the switching circuit 2, becomes a predetermined value. As a result, the energy stored in the inductance means L is supplied to the third terminal Ter3 and the fourth terminal Ter4. Thereafter, the switching element Q3 of the pair of switching elements S2 and S3, to which the first capacitor Ca is connected in parallel, is turned off first, and then the switching element Q2 is turned off.

[0049] In the present invention, as shown in Fig. 1, the switching elements S1 and S2 of the switching circuit 1 that are to be turned off later are connected in series. In order to realize zero voltage switching for the switching elements S1 and S2 that are to be turned off later, for example, when switching element S1 is turned off, the voltage across switching element S2 of the other lower arm in the same first leg is reduced to zero and then an on signal is applied to switching element Q2. Here, the period from when an off signal is applied to switching element Q1 to when an on signal is applied to switching element Q2, that is, the period during which both switching elements S1 and S2 are turned off, is defined as Td.

[0050] The discharge operation of lowering the voltage across the switching element S2 to zero, that is, discharging until the voltage of the capacitor C2 becomes zero, is due to the flow of the excitation current described above. Therefore, in order to realize zero-voltage switching of the switching element S2 to be turned off later, it is first necessary to set the excitation current to a value that can lower the voltage across the switching element S2 to zero. Furthermore, it is necessary to provide a period Td during which both switching elements S1 and S2 are turned off so that the voltage across the switching element S2 can be lowered to zero by the excitation current. The same is true when realizing zero-voltage switching (ZVS) for the switching element S1 of the switching circuit 1 to be turned off later. It is necessary to provide an excitation current of a value that can lower the voltage across the switching element S1 to zero and a period Td during which both switching elements S1 and S2 are turned off.

[0051] If the period Td during which both switching elements S1 and S2 of the switching circuit 1 are turned off is set to a large value, the voltage across the switching element S1 or S2 may rise again after it has dropped to zero, i.e., the capacitor C1 or C2 may be charged after it has been discharged to zero. For this reason, it is preferable that the period Td during which both switching elements S1 and S2 are turned off is set to a period during which the voltage across the switching element S1 or S2 drops to zero. In addition, the parallel capacitors C1 and C2, which are connected in parallel to the switching elements Q1 and Q2 that are turned off later, have small capacitance values, such as in the case of parasitic capacitances built into the switching elements S1 and S2, and may vary depending on the parts. For this reason, a separate capacitor may be connected in parallel to the parasitic capacitances built into the switching elements S1 and S2, and the combined capacitance of these may be used as the parallel capacitors C1 and C2.

[0052] Next, an operation of making the switching circuit 2 function as a full-bridge rectifier circuit when the voltage output between the third terminal Ter3 and the fourth terminal Ter4 is made lower than the output voltage obtained by the operation of turning on and off the switching elements S5 and S6 of the switching circuit 2 described above will be described with reference to the circuit diagram of the converter 301 in FIG. 1 and FIGS. 7 to 10. FIG. 7 is a waveform diagram showing an example of the drive signals of the switching elements S1 to S4 of the switching circuit 1 and the switching elements S5 and S6 of the switching circuit 2 in this operation. FIG. 8 is a waveform diagram showing an example of the voltages and currents of the switching elements S1 to S4 of the switching circuit 1 and the excitation current of the transformer 11 in this operation. FIG. 9 is a waveform diagram showing an example of the voltages and currents of the anti-parallel diodes D5 to D8 of the switching circuit 2 in this operation. FIG. 10 is a circuit diagram formed at each timing for this operation of the converter 301 according to the first embodiment of the present invention. In the current waveforms shown in Figures 8 and 9, the current flowing in the forward direction through the switching elements S1 to S4 of the switching circuit 1 is positive, and the current flowing in the reverse direction through the switching elements S1 to S4 of the switching circuit 1 and the current flowing in the forward direction through the anti-parallel diodes D5 to D8 are negative.

[0053] 1 functions as a full-bridge rectifier circuit in which the bridge-connected circuit of the switching circuit 2 conducts anti-parallel diodes D5 to D8. Therefore, in the converter 301 of the first embodiment, at least the anti-parallel diodes D5 to D8 are required for the switching circuit 2, and therefore, as shown in FIG 7, no on signals are applied to the drive signals of the switching elements S5 to S8 of the switching circuit 2.

[0054] Time t21 is a time point when an on signal is given to the switching elements S1 and S4 of the paired switching circuit 1. At this time, an on signal is not given to the switching elements S5 and S6 of the switching circuit 2. As shown in FIG. 10(a), on the primary winding 11a side of the transformer 11, a current flows from the first terminal Ter1 side to the switching element Q1, the inductance means L, the primary winding 11a, the switching element Q4, and the second terminal Ter2 side. On the secondary winding 11b side of the transformer 11, a current flows from the secondary winding 11b to the anti-parallel diode D5, the third terminal Ter3, and the fourth terminal Ter4 side through the anti-parallel diode D8. The input power supplied from the first terminal Ter1 and the second terminal Ter2 side is supplied to the third terminal Ter3 and the fourth terminal Ter4 side via the inductance means L.

[0055] At time t22, for example, the control circuit 3 provides an off signal to the switching element S4 to be turned off first among the switching elements S1 and S4 of the paired switching circuit 1 so that the voltage detection value between the third terminal Ter3 and the fourth terminal Ter4 detected by the detection means 18 of the switching circuit 2 approaches the target value. Therefore, as shown in FIG. 8, the switching element Q4 is turned off when the current value is relatively large, and a switching loss occurs when the switching element S4 is turned off. In the present invention, as described above in the operation of turning on and off the switching elements S5 and S6 of the switching circuit 2, the second capacitor Cb is also connected in parallel to the switching element Q4 in addition to the parallel capacitor C4 to increase the capacitance of the capacitor. Similarly, the first capacitor Ca is also connected in parallel to the switching element Q3 in addition to the parallel capacitor C3 to increase the capacitance of the capacitor.

[0056] 10(b), on the primary winding 11a side, a current flows from the inductance means L, the primary winding 11a, the parallel capacitor C4 and the second capacitor Cb, the second terminal Ter2, and the first terminal Ter1 through the switch element Q1 in a direction to charge the parallel capacitor C4 and the second capacitor Cb connected in parallel to the switched-off switch element Q4. On the other hand, a discharge current flows from the parallel capacitor C3 and the first capacitor Ca through the switch element Q1, the inductance means L, and the primary winding 11a. By increasing the capacitance of the capacitors connected in parallel to the switching elements S4 and S3 of the switching circuit 1 that are turned off first and gradual increase in the voltage across the switching element S4, the switching loss when the switching element S4 of the switching circuit 1 is turned off is reduced.

[0057] At time t23, when the discharge of the parallel capacitor C3 and the first capacitor Ca and the charging of the parallel capacitor C4 and the second capacitor Cb are completed, the anti-parallel diode D3 connected in parallel to the switch element Q3 becomes conductive as shown in Fig. 10(c). On the primary winding 11a side, due to the energy stored in the inductance means L and the excitation current of the transformer 11, a current flows from the inductance means L, the primary winding 11a through the anti-parallel diode D3 and the switch element Q1 in the same direction as the current that flowed through the primary winding 11a and the inductance means L immediately before time t5. Note that the current on the secondary winding 11b side continues to flow from time t21 through the secondary winding 11b, the anti-parallel diode D5, the third terminal Ter3 side, the fourth terminal Ter4 side and the anti-parallel diode D8.

[0058] At time t24, the drive signal of the switching element S1, which is to be turned off later among the switching elements S1 and S4 of the paired switching circuit 1, is set to an off signal. Since the switching element Q1 is turned off, as shown in FIG. 10(d), a current flows from the primary winding 11a through the anti-parallel diode D3, the parallel capacitor C1, and the inductance means L due to the excitation current of the transformer that was flowing immediately before time t23, and charges the parallel capacitor C1. On the other hand, a discharge current flows from the parallel capacitor C2 through the inductance means L, the primary winding 11a, the anti-parallel diode D3, the first terminal Ter1, and the second terminal Ter2. At this time, the switching element Q1 is turned off while a current is still flowing therethrough, but the current can be made smaller than that of the switching element Q4 that was turned off earlier. Therefore, the switching loss of the switching element Q1 that is to be turned off later can be reduced compared to when the switching element Q4 that is to be turned off earlier is turned off.

[0059] When the charging and discharging of the parallel capacitors C1 and C2 ends at time t25, the anti-parallel diode D2 becomes conductive, as shown in Fig. 10(e). On the primary winding 11a side, due to the excitation current of the transformer 11, a current flows from the primary winding 11a through the anti-parallel diode D3, the first terminal Ter1, the second terminal Ter2 side, the anti-parallel diode D2, and the inductance means L in the same direction as the current that flowed through the primary winding 11a immediately before time t25. Note that the current on the secondary winding 11b side continues to flow from time t21 through the secondary winding 11b, the anti-parallel diode D5, the third terminal Ter3 side, the fourth terminal Ter4 side, and the anti-parallel diode D8.

[0060] At time t26, an ON signal is given to the switching elements S2 and S3 of the switching circuit 1 that constitutes the other pair. As shown in FIG. 10(f), on the primary winding 11a side, the switching element Q2 and the switching element Q3 are conducted in the forward direction, and a current flows through the first terminal Ter1 side, the switching element Q3, the primary winding 11a, the inductance means L, the switching element Q2, and the second terminal Ter2 side. Since the current flowing through the primary winding 11a is reversed from the previous direction, on the secondary winding 11b side, the anti-parallel diode D6 and the anti-parallel diode D7 are conducted in the forward direction, and a current flows from the secondary winding 11b through the anti-parallel diode D7, the third terminal Ter3, and the fourth terminal Ter4 side through the anti-parallel diode D6. As in the case of FIG. 10(a), the power input between the first terminal Ter1 and the second terminal Ter2 is supplied to the third terminal Ter3 and the fourth terminal Ter4 side via the inductance means L.

[0061] Similar to the operation of turning on and off the switching elements S5 and S6 of the switching circuit 2 described above, in the operation of causing the bridge connection circuit of the switching circuit 2 to function as a full-bridge rectifier circuit, the anti-parallel diodes D2 and D3 connected in parallel to the switch elements Q2 and Q3, respectively, are conductive immediately before time t26, and therefore, as shown in FIG. 8, the switching elements S2 and S3 of the switching circuit 1 can achieve zero voltage switching when they are on.

[0062] The operation of the switching elements S2 and S3 of the switching circuit 1 that constitutes the other pair after time t26 is performed in the same manner as the switching elements S1 and S4 that constitute the above-mentioned pair from time t21 to time t26. That is, for example, the control circuit 3 first turns off the switch element Q3, of the pair of switching elements S2 and S3, to which the first capacitor Ca is connected in parallel, and then turns off the switch element Q2, so that the output voltage between the third terminal Ter3 and the fourth terminal Ter4 becomes a desired value.

[0063] In the converter 301, when the control circuit 3 is performing an operation to make the bridge connection circuit of the switching circuit 2 function as a full-bridge rectifier circuit, if the detected value of the voltage output from the third terminal Ter3 and the fourth terminal Ter4 does not approach the target value even if the pulse width and frequency of the switching elements of the switching circuit 1 are modulated, the control circuit 3 switches to an operation to turn on and off the switching elements S5 and S6 of the switching circuit 2. Conversely, when the control circuit 3 is performing an operation to turn on and off the switching elements S5 and S6 of the switching circuit 2, if the detected value of the voltage output from the third terminal Ter3 and the fourth terminal Ter4 does not approach the target value even if the pulse width and frequency of the switching elements S5 and S6 of the switching circuit 2 are modulated, the control circuit 3 switches to an operation to make the bridge connection circuit of the switching circuit 2 function as a full-bridge rectifier circuit. By switching between the two operations, it is possible to accommodate a wide range of input and output voltages and currents without being restricted by circuit constants such as the turns ratio of the transformer 11 or load conditions.

[0064] As in the case of the operation of turning on and off the switching elements S5 and S6 of the switching circuit 2 described above, in the operation of making the bridge connection circuit of the switching circuit 2 function as a full-bridge rectifier circuit, the capacitance of the capacitor connected in parallel to the switching element to be turned off first among the pair of switching elements of the switching circuit 1 is set to be larger than the capacitance of the capacitor connected in parallel to the switching element to be turned off later. In order to realize zero-voltage switching for the switching elements S1 and S2 of the switching circuit 1 to be turned off later, it is first necessary to set the excitation current to a value that can reduce the voltage across the switching element S2 or S1 to zero. Furthermore, it is necessary to provide a period Td during which both switching elements S1 and S2 are turned off so that the voltage across the switching element S2 or S1 can be reduced to zero by the excitation current.

[0065] The period Td during which both switching elements S1 and S2 of the switching circuit 1 are turned off is preferably set to approximately the period during which the voltage across the switching element S1 or S2 drops to zero. Also, the parallel capacitors C1 and C2, which are connected in parallel to the switching elements Q1 and Q2 that are turned off later, have small capacitance values, such as the parasitic capacitances built into the switching elements S1 and S2, and there may be variations depending on the components. For this reason, a separate capacitor may be connected in parallel to the parasitic capacitances built into the switching elements S1 and S2, and the combined capacitance of these may be used as the parallel capacitors C1 and C2.

[0066] 2 and 7 show an example of an operation in which the ON signals, which are drive signals for the switching elements S2 and S3 of the switching circuit 1, are simultaneously given at time t8 and time t26, and the switching elements Q2 and Q3 start to conduct in the forward direction. However, without being limited to the example of the operation of the above embodiment, the ON signals for the switching elements S2 and S3 do not have to be given at the same time. Also, the ON signals for the switching elements S2 and S3 may be given during a period in which the anti-parallel diodes D2 and D3 are conducting. In this case, the time when the ON signals for the switching elements S2 and S3 are given does not coincide with the time when the switching elements Q2 and Q3 start to conduct in the forward direction, and for example, the current that conducts the anti-parallel diodes D2 and D3 becomes zero before the current starts to flow in the forward direction through the switching elements Q2 and Q3. In addition, if the voltage drop of the switching elements Q2 and Q3 when a current flows in the reverse direction is smaller than the forward voltage, which is the voltage drop of the anti-parallel diodes D2 and D3 when a forward current flows, an on signal is given to the switching elements S2 and S3 to make the switching elements Q2 and Q3 conductive in the reverse direction, thereby reducing the conduction loss of the switching elements S2 and S3. The same is true for the switching elements S1 and S4 of the other switching circuit 1.

[0067] In the above basic operation, the switching elements S4 and S3 of the upper and lower arms of the second leg 13 among the switching elements S1 and S4, and S2 and S3 of the paired switching circuit 1 are turned off first, but the switching elements S1 and S2 of the upper and lower arms of the first leg 12 may be turned off first. In this case, the first capacitor Ca and the second capacitor Cb are connected to the switching elements S1 and S2 to be turned off first, respectively. Also, the switching elements of the switching circuit 1 to be turned off first may be the switching elements S1 and S3 of the upper arms of the first leg 12 and the second leg 13, or the switching elements S2 and S4 of the lower arms of the first leg 12 and the second leg 13. In this case, the first capacitor Ca and the second capacitor Cb are connected in parallel to the switching elements S1 and S3 or the switching elements S2 and S4 to be turned off first, respectively.

[0068] In the above basic operation, the positions of the series circuit of switching elements S5 and S6 connected between the third terminal Ter3 and the fourth terminal Ter4 and the series circuit of switching elements S7 and S8 may be interchanged in the bridge connection circuit of the switching circuit 2 shown in Fig. 1. In this case as well, the third capacitor Cc and the fourth capacitor Cd are connected in parallel to the switching elements of the switching circuit 2 that are turned on and off.

[0069] In the above description of the operation of making the bridge-connected circuit of the switching circuit 2 function as a full-bridge rectifier circuit, for example, during the period when the anti-parallel diodes D5 and D6 are conductive, an on signal may be given to the switching elements S5 and S6 in FIG. 1 to make the switching elements Q5 and Q6 conductive in the reverse direction, that is, in the forward direction of the anti-parallel diodes D5 and D6. If the voltage drop of the switching elements Q5 and Q6 when a current flows in the reverse direction is smaller than the forward voltage, which is the voltage drop of the anti-parallel diodes D5 and D6 when a forward current flows, the conduction loss can be reduced to less than that of the anti-parallel diodes D5 and D6. Similarly, when the switching elements S7 and S8 including the anti-parallel diodes D7 and D8 or the switching elements S7 and S8 connected in parallel with the anti-parallel diodes D7 and D8 are used, the conduction loss of the anti-parallel diodes D7 and D8 can be reduced to less than that of the anti-parallel diodes D7 and D8 by making the switching elements Q7 and Q8 conductive in the reverse direction.

[0070] The converter 301 of the present invention can handle a wide range of input and output voltages and currents by using an inductance means connected to the primary winding or secondary winding side of the transformer to realize an operation of turning on and off the switching elements of the switching circuit 2 and an operation of making the bridge connection circuit of the switching circuit 2 function as a full-bridge rectifier circuit. In addition, it can reduce switching loss that occurs when a switching element is turned off while a current is flowing, and can reduce switching loss that occurs when one of the switching elements of a pair of the switching circuit 1 is turned off later. Furthermore, it can reduce switching loss by realizing zero voltage switching.

[0071] (Embodiment 1) In this embodiment, synchronous rectification control (part 1) during boost operation will be described. Fig. 11 is a diagram for explaining synchronous rectification control (part 1) during boost operation, illustrating drive signals for driving each switching element and a current flowing through the secondary winding 11b of the transformer 11. Note that boost operation is an operation for making the output voltage higher than the input voltage.

[0072] In basic operation, switching elements S7 and S8 of switching circuit 2 are not operated, and the secondary winding current passes through the anti-parallel diodes (D7 and D8) of switching elements S7 and S8. Here, loss can be reduced by turning on switching elements S7 and S8 when the secondary winding current passes through the anti-parallel diodes (D7 and D8).

[0073] The control circuit 3 includes: For the other switching circuit (2 / 1), based on the timing of turning on the switching element (S1 / S2) of the upper arm or lower arm to which the first capacitor or the second capacitor (Ca / Cb) of one of the switching circuits (1 / 2) is not connected in parallel, synchronous rectification control is performed in which the switching element (S2 / S1[S8 / S7]) of the lower arm or upper arm to which the first capacitor or the second capacitor (Ca / Cb[Cc / Cd]) of the other switching circuit (2 / 1) is not connected in parallel is turned on, and the off timing of the switching element (S2 / S1[S8 / S7]) is set to be earlier than the turning off of the switching element (S1 / S2) of the upper arm or lower arm to which the first capacitor or the second capacitor (Ca / Cb) of one of the switching circuits (1 / 2) is not connected in parallel.

[0074] And the control circuit 3: The switching element (S3 / S4 [S5 / S6]) to which the first capacitor or the second capacitor (Ca / Cb [Cc / Cd]) of the other switching circuit (2 / 1) is connected in parallel is made to conduct in a forward direction so that the energy input from the two terminals (Ter1&Ter2) side of the pair of switching elements (S1&S4 / S3&S2) in one of the switching circuits (1 / 2) is stored in the inductance means (L) during a period in which the pair of switching elements (S1&S4 / S3&S2) is in an on state in one of the switching circuits (1 / 2) so that a detection value of a voltage, current or power output from between the two terminals (Ter3&Ter4) of the other switching circuit (2 / 1) or a detection value of a voltage, current or power input from between the two terminals (Ter1&Ter2) of one of the switching circuits (1 / 2) approaches a target value, and the other switching circuit (2 / 1) that was made to conduct in the forward direction before turning off the switching element (S3 / S4) of the one of the switching circuits (1 / 2) to be turned off first is turned off. When performing a boost operation control to turn off the switching element (S3 / S4 [S5 / S6]) to which the first capacitor or the second capacitor (Ca / Cb [Cc / Cd]) is connected in parallel, The off-timing of the synchronous rectification control is determined based on the timing of turning off the switching element (S3 / S4) of one of the switching circuits (1 / 2) that is to be turned off first.

[0075] In this embodiment, as the synchronous rectification control, the period Ton during which the switching element used for the synchronous control is turned on is set based on the drive signals of the other switching elements. That is, the control circuit 3 turns on the switching element in the switching circuit 2 that is not parallel to the third capacitor Cc and the fourth capacitor Cd from the timing when the switching element that turns off after the paired switching element in the switching circuit 1 turns on to the timing when the switching element that turns off first turns off.

[0076] Specifically, the control circuit 3 determines the period from when the switching element S1 is turned on (at time t1) until the switching element S4 is turned off (at time t4) as the period Ton during which the switching element S8 is turned on. Similarly, the control circuit 3 determines the period from when the switching element S2 is turned on until the switching element S3 is turned off as the period Ton during which the switching element S7 is turned on. The start time of the period Ton is not limited to the same time as the switching elements (S1 / S2) are turned on. The control circuit 3 determines the timing of turning on the switching elements (S8 / S7) based on the timing of turning on the switching elements (S1 / S2). Therefore, the switching elements (S8 / S7) may be turned on before (e.g., a time Td before) the switching elements (S1 / S2) are turned on, or after (e.g., a time Td after) the switching elements (S1 / S2) are turned on. Similarly, the end point of the period Ton is not limited to the same time as the switching elements (S4 / S3) are turned off. Since the control circuit 3 determines the timing of turning off the switching elements (S8 / S7) based on the timing of turning off the switching elements (S4 / S3), the switching elements (S8 / S7) may be turned off before turning off the switching elements (S4 / S3) (for example, a time period Td before), or the switching elements (S8 / S7) may be turned off after turning off the switching elements (S4 / S3) and before the secondary winding current value decreases and reaches zero, for example. The synchronous rectification control of this embodiment can keep the switching element S7 or S8 on for the entire period during which the secondary winding current flows, which is highly effective in reducing losses.

[0077] (Embodiment 2) In this embodiment, the synchronous rectification control (part 2) during the voltage boost operation will be described. Fig. 12 is a diagram for explaining the synchronous rectification control (part 2) during the voltage boost operation, and is for explaining the drive signals for driving the switching elements and the current flowing through the secondary winding 11b of the transformer 11.

[0078] The control circuit 3 includes: For the other switching circuit (2 / 1), synchronous rectification control is performed in which, at the same time as turning on the switching element (S1 / S2) of the upper arm or lower arm to which the first capacitor or the second capacitor (Ca / Cb) of one of the switching circuits (1 / 2) is not connected in parallel, the switching element (S2 / S1[S8 / S7]) of the lower arm or upper arm to which the first capacitor or the second capacitor (Ca / Cb[Cc / Cd]) of the other switching circuit (2 / 1) is not connected in parallel is turned on, and the off timing of the switching element (S2 / S1[S8 / S7]) is set to be earlier than the turning off of the switching element (S1 / S2) of the upper arm or lower arm to which the first capacitor or the second capacitor (Ca / Cb) of one of the switching circuits (1 / 2) is not connected in parallel.

[0079] And the control circuit 3: The switching element (S3 / S4 [S5 / S6]) to which the first capacitor or the second capacitor (Ca / Cb [Cc / Cd]) of the other switching circuit (2 / 1) is connected in parallel is made to conduct in a forward direction so that the energy input from the two terminals (Ter1&Ter2) side of the pair of switching elements (S1&S4 / S3&S2) in one of the switching circuits (1 / 2) is stored in the inductance means (L) during a period in which the pair of switching elements (S1&S4 / S3&S2) is in an on state in one of the switching circuits (1 / 2) so that a detection value of a voltage, current or power output from between the two terminals (Ter3&Ter4) of the other switching circuit (2 / 1) or a detection value of a voltage, current or power input from between the two terminals (Ter1&Ter2) of one of the switching circuits (1 / 2) approaches a target value, and the other switching circuit (2 / 1) that was made to conduct in the forward direction before turning off the switching element (S3 / S4) of the one of the switching circuits (1 / 2) to be turned off first is turned off. When performing a boost operation control to turn off the switching element (S3 / S4 [S5 / S6]) to which the first capacitor or the second capacitor (Ca / Cb [Cc / Cd]) is connected in parallel, The off timing of the synchronous rectification control is determined based on the timing of turning off the switching element (S3 / S4 [S5 / S6]) to which the first capacitor or the second capacitor (Ca / Cb [Cc / Cd]) of the other switching circuit (2 / 1) is connected in parallel.

[0080] In the present embodiment, the period Ton during which the switching element used for synchronous control is turned on is set based on the drive signals of the other switching elements as the synchronous rectification control. That is, the control circuit 3 turns on the switching element in the switching circuit 2 that is not parallel to the third capacitor Cc and the fourth capacitor Cd from the timing when the switching element that turns off after the paired switching element in the switching circuit 1 turns on to the timing when the switching element used for phase shift control in the switching circuit 2 (the switching element in which the third capacitor Cc and the fourth capacitor Cd are parallel to each other) turns off.

[0081] Specifically, the control circuit 3 determines the period from when the switching element S1 is turned on (at time t1) until the phase-shift switching element S6 is turned off (at time t2) as the period Ton during which the switching element S8 is turned on. Similarly, the control circuit 3 determines the period from when the switching element S2 is turned on until the phase-shift switching element S5 is turned off as the period Ton during which the switching element S7 is turned on. As described in the first embodiment, the start time of the period Ton is not limited to the same time as the switching elements (S1 / S2) are turned on. Similarly, the end point of the period Ton is not limited to the same time as the switching elements (S6 / S5) are turned off. The control circuit 3 determines the timing of turning off the switching elements (S8 / S7) based on the timing of turning off the switching elements (S6 / S5). Therefore, the switching elements (S8 / S7) may be turned off before (e.g., a time Td before) the switching elements (S6 / S5) are turned off, or after (e.g., a time Td after) the switching elements (S6 / S5) are turned off. In the synchronous rectification control of this embodiment, the period Ton changes depending on the phase of the switching element for phase shifting, so that even if the load fluctuates, it can follow the fluctuation.

[0082] (Embodiment 3) In this embodiment, the synchronous rectification control during the step-down operation will be described. Fig. 13 is a diagram for explaining the synchronous rectification control during the step-down operation, and for explaining the drive signals for driving the switching elements and the current flowing through the secondary winding 11b of the transformer 11. Note that the step-down operation is an operation for lowering the output voltage below the input voltage.

[0083] In the basic operation, the operation of all switching elements of the switching circuit 2 is stopped (OFF), and the secondary winding current passes through the anti-parallel diodes (D5 to D8) of those switching elements. As described above, during the period when the anti-parallel diodes D5 and D6 are conducting, an ON signal may be given to the switching elements S5 and S6 to cause the switching elements Q5 and Q6 to conduct in the reverse direction, that is, in the forward direction of the anti-parallel diodes D5 and D6 (see the switching elements Q5 and Q6 in FIG. 13).

[0084] During the period when the anti-parallel diodes D7, D8 are conductive, an on signal is provided to the switching elements S7, S8 to make the switching elements Q7, Q8 conductive in the reverse direction, thereby reducing the conduction loss of the anti-parallel diodes D7, D8.

[0085] The control circuit 3 includes: For the other switching circuit (2 / 1), synchronous rectification control is performed in which, at the same time as turning on the switching element (S1 / S2) of the upper arm or lower arm to which the first capacitor or the second capacitor (Ca / Cb) of one of the switching circuits (1 / 2) is not connected in parallel, the switching element (S2 / S1[S8 / S7]) of the lower arm or upper arm to which the first capacitor or the second capacitor (Ca / Cb[Cc / Cd]) of the other switching circuit (2 / 1) is not connected in parallel is turned on, and the off timing of the switching element (S2 / S1[S8 / S7]) is set to be earlier than the turning off of the switching element (S1 / S2) of the upper arm or lower arm to which the first capacitor or the second capacitor (Ca / Cb) of one of the switching circuits (1 / 2) is not connected in parallel.

[0086] And the control circuit 3: The off timing of the synchronous rectification control is the period from the timing of turning off the switching element (S3 / S4) of one of the switching circuits (1 / 2) that is to be turned off first to the timing of turning off the switching element (S1 / S2) of the upper arm or lower arm to which the first capacitor or the second capacitor (Ca / Cb) of one of the switching circuits (1 / 2) is not connected in parallel, and is determined by a step-down ratio that makes the voltage output from between the two terminals (Ter3&Ter4) of the other switching circuit (2 / 1) lower than the voltage input from between the two terminals (Ter1&Ter2) of one of the switching circuits (1 / 2).

[0087] In this embodiment, the period Ton during which the switching element used for synchronous control is turned on is set based on the drive signal and step-down ratio of the other switching elements. That is, the control circuit 3 turns on the switching element in the switching circuit 2 in which the third capacitor Cc and the fourth capacitor Cd are not connected in parallel at the timing when the switching element that turns off after the paired switching element in the switching circuit 1 turns on. On the other hand, the timing t 22(b) is a timing t 22 (a) Timing t when the switching elements (S1 / S2) are turned off 24 Set it between.

[0088] A more detailed description will be given. During step-down operation, a sufficient synchronous rectification ON time cannot be ensured for the secondary winding current based only on the ON period of the switching elements (S4 / S3) described in the first embodiment. Therefore, the control circuit 3 determines whether the switching elements (S1 / S2) are ON (time t 21 ) and then at time t 22 The period up to (b) is the ON period Ton of the switching element (S8 / S7). 22 (b) is calculated using the following formula. t 22 (b)-t 21 =(Vin / Vout)×(Ns / Np)×Tmin however, Np is the number of turns on the primary side of the transformer 11 (the primary winding 11a in this embodiment), Ns is the number of turns on the secondary side of the transformer 11 (secondary winding 11b in this embodiment), Tmin is time t 21 From 22 Time to (a) It is.

[0089] (Other embodiments) In the electric circuit of the present invention, the connection point refers to a portion that is electrically connected and has the same potential, and does not refer to a point that is physically connected. Furthermore, the configuration, structure, number, arrangement, shape, material, etc. of each part of the converter and bidirectional converter of the present invention are not limited to the above specific examples, and those that are appropriately selected and adopted by a person skilled in the art are also included in the scope of the present invention as long as they include the gist of the present invention.

[0090] More specifically, for example, the semiconductor elements exemplified by symbols are not limited to these specific electric elements, but can be configured as a single electric element or an electric circuit including multiple electric elements having the same function or action, and all of these modifications are included in the scope of the present invention. Similarly, the number and layout of each circuit element, including diodes, capacitors, switching elements, and the like, as appropriately modified by a person skilled in the art are also included in the scope of the present invention. [Explanation of symbols]

[0091] Ter1: Terminal 1 Ter2: Terminal 2 Ter3: Terminal 3 Ter4: 4th terminal 1, 2: Switching circuit 3: Control circuit 11: Trance 12: First leg (first leg of switching circuit 1) 13: Second leg (second leg of switching circuit 1) 24: Third leg (second leg of switching circuit 2) 25: 4th leg (1st leg of switching circuit 2) 16, 17: Capacitor 18: Detection means for switching circuit 2 19: Detection means for switching circuit 1 S1 to S4: switching elements of switching circuit 1 Q1 to Q4: Switch elements D1 to D4: Anti-parallel diodes C1 to C4: Parallel capacitors S5 to S8: switching elements of switching circuit 2 Q5 to Q8: Switch elements D5 to D8: Anti-parallel diodes C5~C8: Parallel capacitors Ca: first capacitor of switching circuit 1 Cb: second capacitor of switching circuit 1 Cc: The first capacitor of the switching circuit 2 (sometimes referred to as the "third capacitor"). Cd: The second capacitor of the switching circuit 2 (sometimes referred to as the "fourth capacitor") L: Inductance means

Claims

1. a transformer having a primary winding and a secondary winding; two switching circuits including a first leg and a second leg connected in parallel between two terminals as upper and lower arms each having a switching element with an anti-parallel diode and a parallel capacitor connected in parallel, a first capacitor connected in parallel to one of the switching elements of the upper or lower arm of the first leg or the second leg or one of the switching elements of the upper arm or the lower arm of the first leg and the second leg, and a second capacitor connected in parallel to the other switching element of the upper or lower arm of the first leg or the second leg or the other switching element of the upper arm or the lower arm of the first leg and the second leg, and connected respectively to the primary winding side and the secondary winding side of the transformer; an inductance means connected between a connection point of the upper and lower arms of the first leg and a connection point of the upper and lower arms of the second leg via the primary winding or the secondary winding of the transformer; A control circuit that controls switching of the switching circuit; Equipped with The control circuit includes: a zero-voltage switching control for one of the switching circuits, in which a switching element of an upper arm of the first or second leg and a switching element of a lower arm of the second or first leg are alternately turned on and off in a pair to convert a direct current input from the two terminal sides into an alternating current to be output from the switching circuit, and in alternately controlling the on and off of the pair of switching elements, a switching element to which the first capacitor or the second capacitor is connected in parallel is first turned off among the switching elements of the upper arm of the first or second leg and the switching elements of the lower arm of the second or first leg that are in an on state in the pair; synchronous rectification control for turning on the switching elements of a lower arm or upper arm to which the first capacitor or the second capacitor of the other switching circuit is not connected in parallel, based on a timing for turning on the switching elements of an upper arm or lower arm to which the first capacitor or the second capacitor of one of the switching circuits is not connected in parallel, and setting an off timing of the switching elements to be earlier than a timing for turning off the switching elements of the upper arm or lower arm to which the first capacitor or the second capacitor of the one switching circuit is not connected in parallel; A DC / DC converter comprising:

2. The control circuit includes: when performing boost operation control, the switching element to which the first capacitor or the second capacitor of the other switching circuit is connected in parallel is made to conduct in a forward direction so that energy input from the two terminals during a period in which the pair of switching elements in one switching circuit is in an on state is stored in the inductance means so that a detected value of a voltage, current or power output from the two terminals of the other switching circuit or a detected value of a voltage, current or power input from the two terminals of one of the switching circuits approaches a target value, and before turning off the switching element of one of the switching circuits to be turned off first, the switching element to which the first capacitor or the second capacitor of the other switching circuit is connected in parallel, which has been made to conduct in the forward direction, is turned off The off-timing of the synchronous rectification control is determined based on a timing to turn off the switching element of the one of the switching circuits that is to be turned off first.

2. The DC / DC converter according to claim 1 .

3. The control circuit includes: when performing boost operation control, the switching element to which the first capacitor or the second capacitor of the other switching circuit is connected in parallel is made to conduct in a forward direction so that energy input from the two terminals during a period in which the pair of switching elements in one switching circuit is in an on state is stored in the inductance means so that a detected value of a voltage, current or power output from the two terminals of the other switching circuit or a detected value of a voltage, current or power input from the two terminals of one of the switching circuits approaches a target value, and before turning off the switching element of one of the switching circuits to be turned off first, the switching element to which the first capacitor or the second capacitor of the other switching circuit is connected in parallel, which has been made to conduct in the forward direction, is turned off The off-timing of the synchronous rectification control is determined based on a timing to turn off the switching element to which the first capacitor or the second capacitor of the other switching circuit is connected in parallel.

2. The DC / DC converter according to claim 1 .

4. The control circuit sets the off timing of the synchronous rectification control as a period from a timing to turn off a switching element of one of the switching circuits to be turned off first to a timing to turn off the switching element of an upper arm or a lower arm to which the first capacitor or the second capacitor of one of the switching circuits is not connected in parallel, the timing being determined by a step-down ratio that makes a voltage output from the two terminals of the other of the switching circuits lower than a voltage input from the two terminals of one of the switching circuits.

2. The DC / DC converter according to claim 1 .

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