Staggered pin connector

Abstract

To provide a connector having a staggered arrangement of pins along edges of the substrate, that can increase a distance between pins on adjacent substrates, reduce alien near-end crosstalk and increase performance, especially at high data speeds.SOLUTION: The present invention provides a connector for providing a staggered arrangement of pins, in which a substrate 124 contains: a first edge 139; and a second edge 142 opposite the first edge. A plurality of first edge pins 133a is positioned proximate the first edge. A first sub-set of the first edge pins is positioned at a first distance D1 from the first edge. A second sub-set of the first edge pins is positioned at a second distance D2 from the first edge, different than the first distance. A plurality of second edge pins 133b is positioned proximate the second edge. The first sub-set of the second edge pins is positioned at the first distance from the second edge. The second sub-set of the second edge pins is positioned at the second distance from the second edge, different than the first distance.SELECTED DRAWING: Figure 7

Description

[Technical field]

[0001] Magnetic jacks, modular jacks (modjacks), and similar connectors include one or more ports that can accept Ethernet connections, using, for example, RJ-11 or RJ-45 connectors. Magnetic jacks, modular jacks, and similar connectors include various circuit boards, printed circuit boards (PCBs), integrated circuits (ICs), or similar substrates positioned in close proximity to one another that utilize magnetic elements and circuitry to handle signals and / or power (e.g., power-over-ethernet (PoE)) transmitted through the connector. The proximity of conductive substrates within a connector creates alien near-end crosstalk (NEXT), among other potential types of signal interference. At data rates below 1 GbE, alien near-end crosstalk typically has minimal impact on data transmission. However, as data rates increase (e.g., 2.5 GbE, 5 GbE, 10 GbE, and beyond), alien near-end crosstalk can interfere with data signal integrity and impair the performance of Ethernet-enabled devices. Summary of the Invention

[0002] Various embodiments are disclosed for a connector having a staggered arrangement of pins for improved performance. In a first aspect, a connector is described that includes a plurality of substrates positioned proximate to one another, at least one of the substrates including a first edge and a second edge opposite the first edge, a plurality of first edge pins positioned proximate to the first edge, a first subset of the first edge pins positioned a first distance from the first edge and a second subset of the first edge pins positioned a second distance from the first edge that is different from the first distance, and a plurality of second edge pins positioned proximate to a second edge, the first subset of the second edge pins positioned a first distance from the second edge and a second subset of the second edge pins positioned a second distance from the second edge that is different from the first distance.

[0003] At least one of the plurality of substrates is a printed circuit board (PCB). Each pin in the first subset of the first edge pins has a diameter smaller than a diameter of each pin in the second subset of the first edge pins. Each pin in the first subset of the second edge pins has a diameter larger than a diameter of each pin in the second subset of the second edge pins. Each of the first edge pins and the second edge pins are positioned within the through hole.

[0004] The connector may further include a first plurality of through holes positioned proximate the first edge and having a first diameter, where a first subset of the first edge pins are positioned within the first plurality of through holes, and a second plurality of through holes positioned proximate the first edge and having a second diameter different from the first diameter, where a second subset of the first edge pins are positioned within the second plurality of through holes.

[0005] In a further aspect, the connector can further include a first plurality of through holes positioned proximate the second edge and having a first diameter, where a first subset of the second edge pins are positioned within the first plurality of through holes, and a second plurality of through holes positioned proximate the second edge and having a second diameter different from the first diameter, where a second subset of the second edge pins are positioned within the second plurality of through holes.

[0006] The connector may further include a plurality of port terminals coupled to the substrate configured to engage with a housing of an external connector. Each of the plurality of substrates may include an electrical trace coupled to one of the plurality of port terminals, and the first edge pin and the second edge pin couple the electrical trace to the downstream magnetic element. The number of the plurality of port terminals may be four, six, or eight, and the external connector may be an RJ-45 connector.

[0007] Each pin of the first subset of the first edge pins can have a first predetermined offset relative to each pin of the second subset of the first edge pins, the first predetermined offset being a predetermined distance selected for optimal performance, and each pin of the first subset of the second edge pins can have a second predetermined offset relative to each pin of the second subset of the second edge pins, the second predetermined offset being a predetermined distance selected for optimal performance.

[0008] In a second aspect, a connector is described that includes a plurality of substrates positioned proximate to one another, at least one of the plurality of substrates including a first edge and a second edge opposite the first edge, and a plurality of first edge pins positioned proximate to the first edges, a first subset of the first edge pins positioned a first distance from the first edge and a second subset of the first edge pins positioned a second distance from the first edge that is different from the first distance.

[0009] The connector can further include a plurality of second edge pins positioned proximate the second edge, a first subset of the second edge pins positioned a first distance from the second edge and a second subset of the second edge pins positioned a second distance from the second edge that is different from the first distance. At least one of the plurality of substrates can be a printed circuit board (PCB).

[0010] Each pin in the first subset of the first edge pins can have a diameter smaller than a diameter of each pin in the second subset of the first edge pins. Each pin in the first subset of the second edge pins can have a diameter larger than a diameter of each pin in the second subset of the second edge pins. Each of the first edge pins and the second edge pins can be positioned within the through hole.

[0011] The connector may further include a first plurality of through holes positioned proximate the first edge and having a first diameter, where a first subset of the first edge pins are positioned within the first plurality of through holes, and a second plurality of through holes positioned proximate the first edge and having a second diameter different from the first diameter, where a second subset of the first edge pins are positioned within the second plurality of through holes.

[0012] In some aspects, the connector can further include a first plurality of through holes positioned proximate the second edge and having a first diameter, where a first subset of the second edge pins are positioned within the first plurality of through holes, and a second plurality of through holes positioned proximate the second edge and having a second diameter different from the first diameter, where a second subset of the second edge pins are positioned within the second plurality of through holes.

[0013] The connector may further include a plurality of port terminals coupled to the substrate configured to engage with a housing of an external connector. Each of the plurality of substrates may include an electrical trace coupled to one of the plurality of port terminals, and the first edge pin and the second edge pin couple the electrical trace to a downstream magnetic element. The number of the plurality of port terminals may be four, six, or eight, and the external connector may be an RJ-45 connector. Each pin of the first subset of the first edge pins may have a first predetermined offset relative to each pin of the second subset of the first edge pins, the first predetermined offset being a predetermined distance selected for optimal performance, and each pin of the first subset of the second edge pins may have a second predetermined offset relative to each pin of the second subset of the second edge pins, the second predetermined offset being a predetermined distance selected for optimal performance.

[0014] In a third aspect, a connector is described that includes a substrate, the substrate including a plurality of first edge pins positioned in a staggered array proximate a first edge, a first subset of the first edge pins being positioned a first distance from the first edge, and a second subset of the first edge pins being positioned a second distance from the first edge that is different from the first distance. [Brief description of the drawings]

[0015] Many aspects of the present disclosure can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of the present disclosure. Moreover, in the drawings, like reference numbers indicate corresponding parts throughout the several views.

[0016] [Figure 1] 1 is a top perspective view of a connector according to various embodiments of the present disclosure. FIG. [Diagram 2] 2 is a bottom perspective view of the connector of FIG. 1 according to various embodiments of the present disclosure. [Diagram 3] FIG. 2 is a front view of the connector of FIG. 1 according to various embodiments of the present disclosure. [Figure 4] 2 is a rear view of the connector of FIG. 1 according to various embodiments of the present disclosure. [Diagram 5] FIG. 2 is a top perspective view of the connector of FIG. 1 with the housing omitted according to various embodiments of the present disclosure. [Figure 6] FIG. 2 is a bottom perspective view of the connector of FIG. 1 with the housing omitted, according to various embodiments of the present disclosure. [Figure 7] 2 is a top view of a substrate of the connector of FIG. 1 according to various embodiments of the present disclosure. [Figure 8] FIG. 1 is a pin diagram of a board according to the related art; [Figure 9] 2 is a pin diagram of a substrate of the connector of FIG. 1 according to various embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] The present disclosure relates to connectors having a staggered arrangement of pins for improved performance, as described below. A Jack-45 connector, also commonly referred to as an RJ-45 connector, is a wired connector that interfaces with network-enabled devices on a local area network (LAN), including but not limited to Ethernet. An RJ-45 connector generally includes a male plug that plugs into or is otherwise positioned within a female port. The RJ-45 connector includes a housing having an array of parallel electrical contacts that mates with a port having correspondingly aligned electrical contacts. Springs or tabs positioned on the housing are used to couple the RJ-45 connector to a corresponding plug in a biased and interference manner.

[0018] As mentioned above, the proximity of PCBs or other substrates in a connector having multiple plugs (including but not limited to Ethernet jacks or plugs) can generate alien near-end crosstalk (NEXT). Alien near-end crosstalk can cause undesirable interference in data communication signals. Although alien near-end crosstalk does not tend to interfere with lower data rate, power, or data transmission due to recent increases in data rates (e.g., 2.5 GbE, 5 GbE, 10 GbE, and above), alien near-end crosstalk can interfere with signal integrity and impair signal or power performance of devices utilizing the connector, especially in high data rate applications.

[0019] A common method of addressing alien near-end crosstalk in connectors involves positioning a metallic conductive shield between adjacent terminal box assemblies (TBAs). Each TBA contains two ports, an upper port and a lower port. A PCB in each assembly routes to the magnetics for the upper and lower ports. A positioned metallic conductive shield is typically placed between each assembly spanning most, if not the entire height of the TBA to reduce alien near-end crosstalk from the entire TBA, including the magnetics of the device and the pins in the board. This shield can improve signal performance, but it also increases the overall cost of the connector by requiring more material and making manufacturing more difficult.

[0020] Accordingly, various embodiments are described herein for connectors having a staggered arrangement of pins for improved signal and power performance. The connectors, which may include Ethernet or modular jack connectors, for example, have multiple boards positioned adjacent to one another in a horizontally side-by-side arrangement. One or more of the boards include a first edge, a second edge opposite the first edge, a first edge pin positioned along the first edge, and a second edge pin positioned along the second edge.

[0021] Additionally, various embodiments may use a single continuous substrate that can be used for horizontally aligned TBAs, where the distance of the first edge pin and the second edge pin from one TBA to an adjacent TBA matters since there is no substrate edge between the TBAs.

[0022] A first subset of the first edge pins can be positioned a first distance from the first edge. Similarly, a second subset of the first edge pins can be positioned a second distance from the first edge that is different from the first distance, thereby providing a staggered arrangement along the first edge. Similarly, a second edge pin can be positioned proximate to the second edge, and a first subset of the second edge pins can be positioned a first distance from the second edge, and a second subset of the second edge pins can be positioned a second distance from the second edge that is different from the first distance. Thus, a staggered arrangement along the second edge is provided.

[0023] One or more of the substrates in the connector may include a circuit board, a printed circuit board (PCB), an integrated circuit (IC), or a similar substrate. In some embodiments, each pin in the first subset of the first edge pins may have a diameter greater than a diameter of each pin in the second subset of the first edge pins. Similarly, in some embodiments, each pin in the first subset of the second edge pins may have a diameter greater than a diameter of each pin in the second subset of the second edge pins.

[0024] The substrate may further include first through holes, each having a first diameter. A first subset of the first edge pins may be positioned within the first through holes. The substrate may further include second through holes, each having a second diameter different from the first diameter. A second subset of the first edge pins may be positioned within the second through holes. The staggered arrangement of pins along the edge of the substrate increases the distance between pins on adjacent substrates, reducing alien near-end crosstalk and improving performance, especially at high data rates.

[0025] Referring now to the drawings, FIG. 1 illustrates a top perspective view, FIG. 2 illustrates a bottom perspective view, FIG. 3 illustrates a front view, and FIG. 4 illustrates a rear view of a connector 100 according to various embodiments of the present disclosure. As can be appreciated, the connector 100 can be coupled to or positioned with an electronic device to make the device a network-enabled device. Thus, the connector 100 can be referred to as a network connector, an Ethernet connector, or similar names. The connector 100 can also include a magnetic jack, a modular jack, or similar connector. In some embodiments, the connector 100 is IEEE® 802.3 Ethernet 10 / 100 / 1000 compatible, IEEE® 802.3at (PoE Plus) compatible, and / or IEEE® 802.3af (PoE Ethernet) compatible.

[0026] 1-4 collectively, connector 100 can include a housing 103 and a housing shield 106 that together define a number of ports 109 positioned on a front face 112 of the connector. Ports 109 can receive a suitable connector, such as an RJ-45 connector, although other types of connectors are contemplated within the scope of the present disclosure. Although two rows and six columns of ports 109 are shown, it will be understood that connector 100 can include one or more ports 109 in various embodiments.

[0027] The housing 103 may be formed of a non-conductive material such as plastic, although other materials can be used. Similarly, the housing shield 106 may be formed of a metallic conductive material such as aluminum, although other materials that provide shielding can be used. The housing shield 106 may be formed with spring fingers 107 and / or other tabs to engage and secure the various components together when the connector 100 is placed in place within a larger housing (not shown), such as, for example, the housing of an electronic device.

[0028] Each port 109 of connector 100 can include port terminals 115 configured to make electrical contact with corresponding contacts on a mating plug (e.g., an RJ-45 connector) when the mating plug is inserted. The number of port terminals 115 in each port 109 can vary depending on the type of connector. Some exemplary configurations include four, six, or eight port pins for Ethernet and RJ-45 connectors. In the particular embodiment shown in FIGS. 1-4, eight port terminals 115 are shown, although other numbers of port terminals 115 can be implemented.

[0029] The connector 100 can convert the serially transmitted data signals into Ethernet signals that can be transmitted to downstream circuitry (e.g., a motherboard, PCB, or other device) via the board mounting terminals 118 by positioning the connector 100 on a surface mount device (not shown) and soldering or otherwise fastening the connector 100 to a desired board through corresponding through holes. In some embodiments, the board mounting terminals 118 can extend downwardly from or through the housing 103, as shown in FIG. 2. However, it is understood that other configurations can be used.

[0030] According to various embodiments, the connector 100 can include support posts 121 that can hold the housing 103 at a predetermined distance from the surface mount device. The support posts 121 can be formed of a non-conductive material, such as a polymeric material. In some implementations, the support posts 121 can be positioned within corresponding openings located on the surface mount device.

[0031] 5 and 6 show top and bottom perspective views, respectively, of the connector 100, with the housing 103 and housing shield 106 omitted for illustrative purposes. Within the housing 103, the connector 100 may include a number of substrates 124a...124n (collectively "substrates 124") to which the port terminals 115 may be attached. The substrates 124 may further include electrical traces 127, through holes 130, pins 133, and other components, as best seen in the top perspective view of FIG. 5. Other components that may be formed on or otherwise included on the substrates 124 may include active or passive elements, such as inductors and capacitors, light-emitting diodes (LEDs), and other components. The port terminals 115 are coupled to the electrical traces 127 on each substrate 124, and the pins 133 couple the electrical traces 127 to the magnetic elements 136 or other downstream electronics of the connector 100. The magnetic elements 136 provide, for example, signal isolation, impedance matching, signal transformation, surge protection, and other functions, thereby providing signals through the board mounting terminals 118 .

[0032] Referring now to FIG. 7, FIG. 7 illustrates a top view of a representative board 124 of the connector 100, again with the housing 103 and housing shield 106 omitted for purposes of illustration. As shown in FIG. 5, the boards 124 can be positioned adjacent to other boards 124. For example, the boards 124 can be arranged horizontally, with each of the boards 124 in a particular row positioned in a side-by-side configuration along the same plane. Referring again to FIG. 7, the boards 124 can include a first edge 139 and a second edge 142 opposite the first edge 139. For example, the first edge 139 and the second edge 142 are on opposite sides of the board 124.

[0033] The first edge pins 133a are positioned along or proximate to the first edge 139. For example, the first edge pins 133a are closer to the first edge 139 than the second edge 142. A first subset of the first edge pins 133a are positioned a first distance D1 from the first edge 139, and a second subset of the first edge pins 133a are positioned a second distance D2 from the first edge 139. In various embodiments, the second distance D2 is different from the first distance D1, thus providing a staggered arrangement of the first edge pins 133a, as shown in FIG. In particular, as shown in FIG. 7, a pair of first edge pins 133a are at a greater distance (D1) to the first edge 139, in contrast to isolated first edge pins 133a positioned closer (D2) to the first edge 139 (although other staggered arrangements are possible).

[0034] The second edge pins 133b are positioned along or proximate to the second edge 142. For example, the second edge pins 133b are closer to the second edge 142 than to the first edge 139, as can be seen in FIG. 7. Similar to the first edge pins 133a described above, a first subset of the second edge pins 133b are positioned a first distance D3 from the second edge 142 and a second subset of the second edge pins 133b are positioned a second distance D4 from the second edge 142, where the second distance D4 is different from the first distance D3.

[0035] Thus, a staggered arrangement of second edge pins 133b is shown along the second edge 142. For example, the pair of second edge pins 133b shown in FIG. 7 are a greater distance to the second edge 142 as opposed to the spaced apart second edge pins 133b positioned closer to the second edge 142. However, it is understood that the spaced apart ones of the second edge pins 133b may be positioned farther from the second edge 142 than the pair of second edge pins 133b in an alternative staggered arrangement. In particular, not all of the first edge pins 133a are aligned along a common axis positioned parallel to the first edge 139 and / or not all of the first edge pins 133a are aligned along a common axis positioned parallel to the second edge 142.

[0036] Additionally, in some embodiments, each pin 133 in the first subset of first edge pins 133a can have a diameter smaller than the diameter of each pin 133 in the second subset of first edge pins 133a. For example, first edge pins 133a arranged in pairs along the horizontal direction of the substrate 124 have a diameter smaller than the diameter of isolated first edge pins 133a positioned near the first edge 139 of the first edge pins 133a. In some implementations, the diameters do not differ from each other. Because the pins 133 are offset, the pads on the larger pins can be of a standard size instead of a unique oval shape that may not connect to the through-hole 130 on all sides.

[0037] Similarly, in some embodiments, each pin 133 in the first subset of second edge pins 133b can have a diameter smaller than the diameter of each pin 133 in the second subset of second edge pins 133b. For example, second edge pins 133b arranged in pairs along the horizontal direction of the substrate 124 have a diameter smaller than the diameter of an isolated one of the second edge pins 133b positioned near the second edge 142. The ground pin 145 can be positioned at a distal end of the substrate 124 opposite the distal end of the port terminal 115.

[0038] Each pin 133, the first edge pins 133a and / or the second edge pins 133b, may be positioned within a through-hole 130, allowing the pins 133 to couple the electrical traces 127 to a magnetic element 136 or other downstream portion of the connector 100. In some embodiments, a first group of through-holes 130 has a first diameter, a first subset of the first edge pins 133a is positioned within the first group of through-holes 130, and a second group of through-holes 130 has a second diameter different than the first diameter. A second subset of the first edge pins 133a may be positioned within the second group of through-holes 130.

[0039] Referring now to FIG. 8, FIG. 8 illustrates a pin diagram of an exemplary substrate 124 of the related art. As can be seen, all pins located along a first side of the substrate are aligned along a common axis a1 positioned parallel to the first side. All pins located along a second side of the substrate are aligned along a common axis a2 positioned parallel to the second side. Furthermore, each of the pins, whether on the first side or the second side, is of uniform size positioned in a uniformly sized through hole. It is understood that even when multiple substrates 124 of the related art are positioned adjacent to each other or stacked on top of each other in a vertical arrangement, the proximity of the pins between adjacent substrates 124 creates alien near-end crosstalk, which impairs transmission capabilities, especially at high data rates of 2.5 GbE and above. In the related art, moving the location of the pins is difficult and undesirable, and such movement of the pins could interfere with trace routing, among other difficulties.

[0040] In contrast, FIG. 9 shows a pin diagram of a first substrate 124a positioned adjacent to a second substrate 124b, according to various embodiments described herein. Generally, pairs of pins 133 along the first edge 139 or second edge 142 of the substrate 124a are positioned further from the edge, and the spacing between the pins 133 on the second substrate 124b is increased. The isolated ones of the pins 133 have an increased center tap plated through hole size and / or an increased pin diameter. The pins 133 positioned in pairs (e.g., a first subset of the first edge pins 133a) have an offset O1 relative to the isolated ones of the pins 133 (e.g., a second subset of the first edge pins 133a). In some embodiments, the offset O1 is 0.5 mm, 1 mm, 1.5 mm, 2 mm, or other dimension that maintains improved performance.

[0041] The above-described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments, and features discussed in various embodiments may be interchangeable where possible. In the following description, numerous specific details are provided to fully understand the embodiments of the present disclosure. However, those skilled in the art will understand that the technical solutions of the present disclosure may be implemented without one or more of the specific details, or other methods, components, materials, etc. may be used. In other instances, well-known structures, materials, or operations have not been shown or described in detail to avoid obscuring aspects of the present disclosure.

[0042] Although relative terms such as "on", "below", "upper", "lower" and the like are used herein to describe the relative relationship of one component to another, these terms are used herein only for convenience, e.g., as directions in the examples shown in the drawings. It should be understood that if the device were turned upside down, the "upper" components described above would become "lower" components. When a structure is "on" another structure, the structure can be integrally formed on the other structure, or the structure can be "directly" disposed on the other structure, or the structure can be "indirectly" disposed on the other structure via the other structure.

[0043] As used herein, terms such as "a," "an," "the," and "said" are used to indicate the presence of one or more elements or components. The terms "comprise," "include," "have," "contain," and variations thereof are used to be open-ended and mean to include additional elements, components, etc., in addition to the recited elements, components, etc., unless otherwise specified in the appended claims.

[0044] The terms "first," "second," and the like are used only as labels and not to limit the number of referents. It is understood that when multiple components are presented, those components may be referred to as a "first" component, a "second" component, etc., to the extent applicable.

[0045] The above-described embodiments of the present disclosure are merely possible examples of implementations set forth for a clear understanding of the principles of the present disclosure. Many changes and modifications can be made to the above-described embodiments without substantially departing from the spirit and principles of the present disclosure. All such modifications and modifications are intended to be included herein within the scope of the present disclosure and protected by the following claims.

Claims

1. A plurality of substrates positioned adjacent to one another, at least one of the plurality of substrates comprising: a first edge and a second edge opposite the first edge; a plurality of first edge pins positioned proximate to the first edge, a first subset of the first edge pins being positioned a first distance from the first edge and a second subset of the first edge pins being positioned a second distance from the first edge that is different from the first distance; a plurality of second edge pins positioned proximate to the second edge, a first subset of the second edge pins being positioned a first distance from the second edge and a second subset of the second edge pins being positioned a second distance from the second edge that is different from the first distance; A connector comprising a plurality of substrates.

2. The connector of claim 1 , wherein at least one of the plurality of substrates is a printed circuit board (PCB).

3. 2. The connector of claim 1, wherein each pin in the first subset of the first edge pins has a diameter smaller than a diameter of each pin in the second subset of the first edge pins.

4. 4. The connector of claim 1 or 3, wherein each pin in the first subset of second edge pins has a diameter greater than a diameter of each pin in the second subset of second edge pins.

5. The connector of claim 1 , wherein each of the first edge pin and the second edge pin is positioned within a through hole.

6. a first plurality of through holes positioned proximate the first edge and having a first diameter, a first subset of the first edge pins positioned within the first plurality of through holes; a second plurality of through holes positioned proximate the first edge and having a second diameter different than the first diameter, a second subset of the first edge pins positioned within the second plurality of through holes; The connector of claim 1 further comprising:

7. a first plurality of through holes positioned proximate the second edge and having a first diameter, a first subset of the second edge pins positioned within the first plurality of through holes; a second plurality of through holes positioned proximate the second edge and having a second diameter different from the first diameter, a second subset of the second edge pins positioned within the second plurality of through holes; The connector of claim 1 or 6, further comprising:

8. The connector of claim 1 , further comprising a plurality of port terminals coupled to the substrate configured to mate with a housing of an external connector.

9. 9. The connector of claim 8, wherein each of a plurality of substrates includes an electrical trace coupled to one of the plurality of port terminals, and the first edge pin and the second edge pin couple the electrical trace to a downstream magnetic element.

10. 2. The connector of claim 1, wherein the number of the plurality of port terminals is four, six, or eight, and the external connector is an RJ-45 connector.

11. each pin of the first subset of edge pins has a first predetermined offset relative to each pin of the second subset of edge pins, the first predetermined offset being a predetermined distance selected for optimal performance; each pin of the first subset of second edge pins has a second predetermined offset relative to each pin of the second subset of second edge pins, the second predetermined offset being a predetermined distance selected for optimum performance; The connector of claim 1 .

12. A plurality of substrates positioned adjacent to one another, at least one of the plurality of substrates comprising: a first edge and a second edge opposite the first edge; a plurality of first edge pins positioned proximate to the first edge, a first subset of the first edge pins being positioned a first distance from the first edge and a second subset of the first edge pins being positioned a second distance from the first edge that is different from the first distance; A connector comprising a plurality of substrates.

13. 13. The connector of claim 12, further comprising a plurality of second edge pins positioned proximate to the second edge, a first subset of the second edge pins positioned a first distance from the second edge and a second subset of the second edge pins positioned a second distance from the second edge that is different from the first distance.

14. 14. The connector of claim 12 or 13, wherein at least one of the plurality of substrates is a printed circuit board (PCB).

15. 14. The connector of claim 12 or 13, wherein each pin in the first subset of the first edge pins has a diameter smaller than a diameter of each pin in the second subset of the first edge pins.

16. 16. The connector of claim 15, wherein each pin in the first subset of second edge pins has a diameter greater than a diameter of each pin in the second subset of second edge pins.

17. The connector of claim 13 , wherein each of the first edge pin and the second edge pin is positioned within a through hole.

18. a first plurality of through holes positioned proximate the first edge and having a first diameter, a first subset of the first edge pins positioned within the first plurality of through holes; a second plurality of through holes positioned proximate the first edge and having a second diameter different than the first diameter, a second subset of the first edge pins positioned within the second plurality of through holes; The connector of claim 13 further comprising:

19. a first plurality of through holes positioned proximate the second edge and having a first diameter, a first subset of the second edge pins positioned within the first plurality of through holes; a second plurality of through holes positioned proximate the second edge and having a second diameter different from the first diameter, a second subset of the second edge pins positioned within the second plurality of through holes; The connector of claim 18 further comprising:

20. The connector of claim 12 further comprising a plurality of port terminals coupled to the substrate configured to mate with a housing of an external connector.

21. 21. The connector of claim 20, wherein each of a plurality of substrates includes an electrical trace coupled to one of the plurality of port terminals, and the first edge pin and the second edge pin couple the electrical trace to a downstream magnetic element.

22. 22. The connector of claim 21, wherein the number of the plurality of port terminals is four, six, or eight, and the external connector is an RJ-45 connector.

23. each pin of the first subset of edge pins has a first predetermined offset relative to each pin of the second subset of edge pins, the first predetermined offset being a predetermined distance selected for optimal performance; each pin of the first subset of second edge pins has a second predetermined offset relative to each pin of the second subset of second edge pins, the second predetermined offset being a predetermined distance selected for optimum performance; The connector of claim 13.

24. A connector comprising a substrate, the substrate comprising:

1. A connector comprising a plurality of first edge pins positioned in a staggered arrangement proximate a first edge, a first subset of the first edge pins being positioned a first distance from the first edge and a second subset of the first edge pins being positioned a second distance from the first edge that is different from the first distance.

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