Semiconductor device

Abstract

To provide a storage device capable of retaining data for a long period of time.SOLUTION: A storage device comprises a storage element and a transistor which function as a switching element for controlling supply, retention and emission of charge by the storage element. The transistor includes other than a normal gate electrode, a second gate electrode for controlling a threshold voltage; and has an extremely low off-state current since an active layer includes an oxide semiconductor. In the above-described storage device, data is stored not by implantation of charge at a high voltage to a floating gate surrounded by an insulation film but by controlling a charge amount of the storage element via the transistor having extremely low off-state current.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a non-volatile semiconductor memory device, and to the configuration of a memory cell that holds data. [Background technology]

[0002] Semiconductor memory devices (hereafter simply referred to as memory devices) include DRAM, which is classified as volatile memory. , SRAM, Mask ROM, EPROM, EEPROM, Flash, which are classified as non-volatile memory These include flash memory and ferroelectric memory, which are formed using single-crystal semiconductor substrates. Many of these memories are already in practical use. Among the above semiconductor memories, flash Memory allows data to be written and erased repeatedly, and can operate without a power supply. Since it is a non-volatile memory that can retain data, it is highly convenient and resistant to physical shock. Because of its strength, it is mainly used in portable storage media such as USB memory and memory cards, and is It is widely available in.

[0003] There are two types of flash memory: NAND type, which has a structure in which multiple memory cells are connected in series, and There are two types of NOR type, which has a structure in which multiple memory cells are connected in a matrix. Each flash memory has a transistor that functions as a memory element in each memory cell. The transistor that functions as this memory element is called a floating gate. The electrode for storing electric charges is provided between the gate electrode and the semiconductor film which is the active layer. Thus, data can be stored by accumulation of charge on the floating gate.

[0004] The following Patent Documents 1 and 2 disclose floating gates formed on a glass substrate. A thin film transistor having [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 6-021478 [Patent Document 2] JP 2005-322899 A Summary of the Invention [Problem to be solved by the invention]

[0006] By the way, in non-volatile memory, the absolute value of the voltage applied to the memory element when writing data However, it tends to be around 20V, which is generally larger than volatile memory. In the case of flash memory, which can perform this process repeatedly, When erasing data, it is necessary to apply a large voltage to the transistors used as memory elements. Therefore, when the flash memory is operated, such as when writing or erasing data, The power consumed is high, which is a factor in the design of electronic devices that use flash memory as a storage device. This is one of the factors that hinders the reduction of power consumption, especially in portable electronic devices such as cameras and mobile phones. When using flash memory for this purpose, the high power consumption comes at the expense of shortening the continuous operating time. Connected to Litt.

[0007] Although flash memory is a non-volatile memory, data can be lost due to minute leakage of electric charges. Therefore, the current data retention period is said to be about 5 to 10 years. Therefore, there is a demand for a flash memory that can ensure a longer data retention period.

[0008] Furthermore, flash memory allows data to be written and erased repeatedly. However, when charges are stored in the floating gate, the gate insulating film is deteriorated by the tunnel current. Therefore, the number of times data can be rewritten in one memory element is tens of thousands to hundreds of thousands. Realization of flash memory that can withstand many more rewrites, with a limit of about 1000 times is desired.

[0009] In view of the above-mentioned problems, the present invention provides a storage device capable of suppressing power consumption, It is an object of the present invention to provide a semiconductor device using the same. One of the objects of the present invention is to provide a memory device capable of storing data and a semiconductor device using the memory device. The invention relates to a storage device that can increase the number of times data can be rewritten, and a semiconductor device using the storage device. One of the objects is to provide a semiconductor device. [Means for solving the problem]

[0010] A memory device according to one embodiment of the present invention includes a memory element and a memory for supplying and holding charge to the memory element. and a transistor that functions as a switching element for controlling the emission. In memory devices, charges are injected at high voltage into a floating gate surrounded by an insulating film. Instead, the amount of charge in a memory element is controlled via a transistor with extremely low off-state current. , and stores the data.

[0011] Specifically, the transistor has a wider band gap and higher intrinsic carrier density than silicon. The semiconductor material has a lower conductivity than silicon in the channel forming region. By including a semiconductor material having the above-mentioned characteristics in the channel formation region, Such semiconductor materials include: For example, oxide semiconductors and silicon carbide semiconductors have a band gap three times larger than that of silicon. Silicon, gallium nitride, etc. Transistors using the above semiconductor materials are usually Compared with transistors made of semiconductor materials such as silicon or germanium, The flow can be made extremely low.

[0012] Furthermore, the transistor that functions as a switching element has a threshold voltage in addition to the normal gate electrode. The transistor is characterized in that it is provided with a second gate electrode for controlling the voltage. The transistor may be an insulated gate field effect transistor, specifically, a first gate a second gate electrode and a semiconductor layer located between the first gate electrode and the second gate electrode; a first insulating film located between the first gate electrode and the semiconductor film; and a second gate electrode. a second insulating film located between the source electrode and the semiconductor film; and a source electrode and a drain electrode connected to the semiconductor film. With the above configuration, the potential difference between the source electrode and the second gate electrode can be controlled. By this, the threshold voltage can be adjusted so that the off-state current of the transistor is reduced. .

[0013] By reducing the off-state current of the transistor that functions as a switching element, During the period during which the data is held (the holding period), the charge stored in the memory element is This can prevent leakage through the transistor.

[0014] In addition, impurities such as moisture and hydrogen, which act as electron donors, are reduced, and oxygen is eliminated. The reduced defects result in a highly purified oxide semiconductor. Semiconductors are i-type (intrinsic semiconductors) or very close to i-type. Therefore, a transistor including the oxide semiconductor has the characteristic of having an extremely low off-state current. Specifically, the highly purified oxide semiconductor was analyzed by secondary ion mass spectrometry (SIMS: Measurement of hydrogen concentration by condary ion mass spectrometry The value is 5 x 10 19 / cm 3 Less than or equal to 5×10 18 / cm 3 The following is more preferable: is 5 x 10 17 / cm 3 More preferably, 1×10 16 / cm 3 The following applies. Also, The carrier density of the oxide semiconductor film that can be measured by Hall effect measurement is 1×10 14 / cm 3 Less than 1 x 10 12 / cm 3 less than 1×10 11 / cm 3 Not yet The band gap of the oxide semiconductor is 2 eV or more, preferably 2.5 eV or more. The concentration of impurities such as moisture and hydrogen is sufficiently reduced. In addition, the oxide semiconductor film is highly purified by reducing oxygen vacancies. As a result, the off-state current of the transistor can be reduced.

[0015] Here, an analysis of the hydrogen concentration in the oxide semiconductor film will be described. Hydrogen concentration is measured using SIMS. SIMS, by its very nature, is unable to measure hydrogen near the surface of a sample or in areas of different materials. It is known that it is difficult to obtain accurate data on the vicinity of the laminated interface with the other film. When analyzing the distribution of hydrogen concentration in the thickness direction of a film by SIMS, In the range where there is no extreme fluctuation in the value, the value is almost constant. The average value is adopted as the hydrogen concentration. When it is not possible to find a region where a nearly constant value is obtained due to the influence of the hydrogen concentration in the adjacent film In this case, the maximum or minimum value of the hydrogen concentration in the region where the film exists is determined as The hydrogen concentration in the film is taken as the maximum value. If there is no mountain-shaped peak or valley-shaped peak with a minimum value, the value of the inflection point is taken as the hydrogen concentration. It will be adopted as such.

[0016] Specifically, the off-state current of a transistor using a highly purified oxide semiconductor film as an active layer The low value of can be proved by various experiments. For example, when the channel width is 1×10 6 μm Even if the channel length of the device is 10 μm, the voltage between the source and drain electrodes (drain When the on-state voltage is in the range of 1V to 10V, the off-state current is Below the measurement limit, i.e. 1×10 -13 In this case, the characteristic of A or less can be obtained. The off-current density, which is the off-current divided by the channel width of the transistor, is 100 It can be seen that the capacitance is less than zA / μm. A circuit that controls the charge flowing into or out of a capacitor using the transistor is used. The off-state current density was measured. In this measurement, the highly purified oxide semiconductor was The capacitance element is used in the active layer of a transistor, and the charge amount per unit time of the capacitance element is used to determine the capacitance of the transistor. The off-state current density of the transistor was measured. It was found that an even lower off-current density of several tens of yA / μm could be obtained at a voltage of 3 V. Therefore, in the semiconductor device according to one embodiment of the present invention, a highly purified oxide semiconductor film is The off-state current density of the transistor used as the active layer was measured by the voltage between the source and drain electrodes. Depending on the circumstances, it is 100 yA / μm or less, preferably 10 yA / μm or less, and more preferably 1 Therefore, the highly purified oxide semiconductor film can be used as the active layer. The transistor used as the gate insulating film is a transistor using crystalline silicon. is significantly lower than

[0017] As the oxide semiconductor, an oxide semiconductor containing In or Zn is preferably used. It is preferable to use an oxide semiconductor containing In and Ga, or an oxide semiconductor containing In and Z. In order to make the oxide semiconductor film i-type (intrinsic), Dehydration or dehydrogenation, which will be described later, is effective. In addition, gallium arsenide is used as a stabilizer to reduce the variation in the electrical characteristics of the gallium arsenide. It is preferable that the alloy contains tin (Sn) as a stabilizer. It is also preferable that the stabilizer contains hafnium (Hf). It is also preferable that the stabilizer contains aluminum (Al).

[0018] Other stabilizers include the lanthanides lanthanum (La) and cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Ho, Erbium, Thulium, Ytterbium, Ru It may contain one or more of the elements tetraethium (Lu).

[0019] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and oxides of binary metals. In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Oxides, Sn-Mg oxides, In-Mg oxides, In-Ga oxides, ternary metal oxides In-Ga-Zn oxide (also written as IGZO), In-Al-Zn oxide Oxides, In-Sn-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides oxides, Sn-Al-Zn oxides, In-Hf-Zn oxides, In-La-Zn oxides In-Ce-Zn oxides, In-Pr-Zn oxides, In-Nd-Zn oxides , In-Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy-Zn oxide, In-Ho-Zn oxide, I n-Er-Zn oxide, In-Tm-Zn oxide, In-Yb-Zn oxide, In -Lu-Zn ​​oxides, In-Sn-Ga-Zn oxides, which are oxides of quaternary metals, I n-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al- Zn-based oxide, In-Sn-Hf-Zn-based oxide, In-Hf-Al-Zn-based oxide are used. The oxide semiconductor may contain silicon.

[0020] For example, In-Ga-Zn oxide means an oxide containing In, Ga, and Zn. The ratio of In, Ga, and Zn is not important. In addition, metal elements other than In, Ga, and Zn In-Ga-Zn oxides have a sufficiently high resistance when no electric field is present, and therefore, Since the current can be made sufficiently small and the mobility is high, it is suitable for use in storage devices or semiconductor devices. It is suitable as a semiconductor material for use in semiconductor devices.

[0021] Alternatively, the oxide semiconductor may be represented by the chemical formula InMO 3 (ZnO) m Materials expressed as (m>0) M is one or more metal elements selected from Ga, Al, Mn, and Co. For example, M may be Ga, Ga and Al, Ga and Fe, Ga and Ni, Ga and In, Mn, Ga, Co, etc. can be used as the oxide semiconductor. 3 SnO 5 (ZnO) n (n>0, and n is an integer) may be used. Please note that the above composition is derived from the crystal structure and is merely an example. The following is added.

[0022] For example, In:Ga:Zn=1:1:1 (=1 / 3:1 / 3:1 / 3) or In:G In-Ga-Zn system oxide with an atomic ratio of a:Zn=2:2:1 (=2 / 5:2 / 5:1 / 5) Alternatively, In:Sn:Zn=1 :1:1(=1 / 3:1 / 3:1 / 3), In:Sn:Zn=2:1:3(=1 / 3:1 / 6:1 / 2) or In:Sn:Zn=2:1:5(=1 / 4:1 / 8:5 / 8) It is advisable to use an In--Sn--Zn-based oxide having an atomic ratio or an oxide having a composition close to that.

[0023] However, the present invention is not limited to these, and can be applied to any semiconductor characteristics (mobility, threshold, variation, etc.) required. In order to obtain the required semiconductor characteristics, the appropriate composition should be used. Carrier density, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic bond length, density It is preferable to make the above appropriate. Effect of the Invention

[0024] The transistor with low off-state current is used as a switch for holding charge stored in a memory element. By using it as a switching element, it is possible to prevent leakage of electric charge from the memory element. The present invention provides a memory device capable of storing data for a long period of time and a semiconductor device using the memory device. It can be provided.

[0025] The voltage required to write and read data to the memory element is determined by the switching element and The operating voltage of the transistor that functions as the A storage device capable of reducing power consumption by significantly lowering the operating voltage compared to a conventional storage device. A semiconductor device using the memory device can be provided.

[0026] In addition, the degradation of the gate insulating film caused by tunnel current is suppressed compared to conventional flash memory. Therefore, the number of times data can be rewritten can be increased. It is possible to provide a semiconductor device using the device. [Brief description of the drawings]

[0027] [Figure 1] 1A and 1B are a circuit diagram of a memory cell and a cross-sectional view of a transistor. [Diagram 2] A circuit diagram of a transistor and a graph showing the value of drain current Id versus gate voltage Vgs. [Diagram 3] FIG. 1 is a circuit diagram of a cell array. [Figure 4] 4 is a timing chart of a cell array. [Diagram 5] 4 is a timing chart of a cell array. [Figure 6] FIG. 1 is a circuit diagram of a cell array. [Figure 7] FIG. 4 is a diagram showing a configuration of a second word line driving circuit. [Figure 8] FIG. 1 is a circuit diagram of a memory cell. [Figure 9] 1A to 1C are diagrams illustrating a method for manufacturing a memory device. [Figure 10] 1A to 1C are diagrams illustrating a method for manufacturing a memory device. [Figure 11] 1A to 1C are diagrams illustrating a method for manufacturing a memory device. [Figure 12] 1A to 1C are diagrams illustrating a method for manufacturing a memory device. [Figure 13] FIG. [Figure 14] FIG. 1 is a block diagram of a storage device. [Figure 15] FIG. [Figure 16] Block diagram of an RF tag. [Figure 17] FIG. 2 is a diagram showing the configuration of a storage medium. [Figure 18] Electronic devices illustration. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and the embodiments and aspects of the present invention may be modified without departing from the spirit and scope of the present invention. Various modifications of the details will be readily apparent to those skilled in the art. The present invention is not to be construed as being limited to the description of the following embodiment.

[0029] In addition, microprocessors, integrated circuits such as image processing circuits, RF tags, storage media, semiconductor Any and all semiconductor devices that can use memory devices, such as display devices, can be used in the present invention. In addition, the semiconductor display device includes liquid crystal display devices and organic light emitting diodes (OLEDs). Light-emitting devices with light-emitting elements such as l Micromirror Device), PDP (Plasma Display) Panel), FED (Field Emission Display), etc. A semiconductor display device having a circuit element using a thin film in a pixel section or a driving circuit falls into this category. Included.

[0030] (Embodiment 1) FIG. 1A is a circuit diagram illustrating an example of a memory cell configuration of a memory device according to one embodiment of the present invention. In the circuit diagram shown in FIG. 1A, a memory cell 100 functions as a switching element. A transistor 101 functioning as a memory element, a transistor 103 functioning as a capacitor element, The transistor 103 functioning as a memory element has a gate electrode and an active layer Data is stored by accumulating charges in the gate capacitance formed between the gate electrodes.

[0031] The transistor 101 functioning as a switching element has a first gate electrode and a threshold A second gate electrode is provided for controlling the voltage. a second gate electrode, and a semiconductor located between the first gate electrode and the second gate electrode. a first insulating film located between the first gate electrode and the semiconductor film; and a second gate electrode. A second insulating film is disposed between the semiconductor film, and a source electrode and a drain electrode are connected to the semiconductor film. The transistor 101 has a first gate electrode, a second gate electrode, a source Various operations of the memory device can be controlled by applying potentials to the source and drain electrodes.

[0032] The memory cell 100 may include transistors, diodes, resistors, capacitors, etc., as necessary. It may also include other circuit elements such as inductors.

[0033] The source electrode and the drain electrode of the transistor are determined by the polarity and the potential of the transistor. The name is changed depending on the difference in potential between the electrodes. Generally, n-channel In a transistor with a low potential, the electrode to which a high potential is applied is called the source electrode. The electrode that is connected to the drain electrode is called the drain electrode. The electrode to which a low potential is applied is called the drain electrode, and the electrode to which a high potential is applied is called the source electrode. In the following, either the source electrode or the drain electrode is referred to as the first terminal, and the other is referred to as the second terminal. The memory cell 100 includes a transistor 101, a capacitor 102, and a transistor 10 The connection relationship of 3 is explained below.

[0034] In the memory cell 100 shown in FIG. 1A, A potential of a signal including data is applied to a node connected to the second terminal of the transistor 101. The gate electrode of the transistor 103 is connected to a gate electrode of the transistor 103. One of the electrodes is connected to the gate electrode of the transistor 103, and the other is given a predetermined potential. is connected to a node that is

[0035] The transistor 103 may be either an n-channel type or a p-channel type.

[0036] Note that the memory cell 100 shown in FIG. 1A does not necessarily include the capacitor 102 as a component. By providing the capacitor element 102 in the memory cell 100, a longer retention period can be achieved. On the other hand, by not providing the capacitor element 102 in the memory cell 100, This allows for increased storage capacity per unit area.

[0037] FIG. 1B is a circuit diagram showing an example of a memory cell configuration different from that shown in FIG. In the circuit diagram shown in FIG. 1B, the memory cell 100 functions as a switching element. The memory element includes a transistor 101 that functions as a memory element and a capacitor 102 that functions as a memory element. Data is stored by accumulating charges in the capacitor 102 which functions as a charge storage element.

[0038] The transistor 101 illustrated in FIG. 1B has the same structure as the transistor 101 illustrated in FIG. In addition to the first gate electrode, a second gate electrode is provided for controlling the threshold voltage. The poles are provided.

[0039] In the memory cell 100 shown in FIG. 1B, A potential of a signal including data is applied to the node where the capacitor 102 is connected. One of the pair of electrodes is connected to the second terminal of the transistor 101, and the other is connected to a predetermined potential. is connected to the given node.

[0040] In this specification, the term "connection" means electrical connection, and the current, voltage, or potential is This corresponds to a state where the signal can be supplied or transmitted. Therefore, the connected state is a direct connection. does not necessarily refer to the state in which a current, voltage or potential is available or transferable. To make it possible to transmit signals, the devices must be wired, conductive, resistors, diodes, transistors, etc. This also includes situations where the connection is indirectly made via another means.

[0041] In addition, even if components that are independent on the circuit diagram are connected, For example, when a part of a wiring functions as an electrode, one conductive film is a In this specification, the term "connection" refers to such a single conductive film. However, cases where the functions of multiple components are combined are also included in this category.

[0042] In one embodiment of the present invention, a semiconductor device that functions as the switching element shown in FIG. 1(A) or FIG. The channel formation region of the transistor 101 has a wider band gap than silicon. The semiconductor material has a lower intrinsic carrier density than silicon. By including a semiconductor material having such characteristics in the channel formation region, the off-current is extremely low. The transistor 101 can be realized.

[0043] Note that, as in one embodiment of the present invention, the amount of charge stored in the memory element is controlled, In the case of a storage device that stores data, the supply of charge to the storage element and the transfer of charge from the storage element are The discharge of the charge and the retention of the charge in the memory element are controlled by a transistor that functions as a switching element. The length of the data retention period is controlled by the transistor 101. The amount of charge stored in the transistor 101 depends on the amount of charge that leaks through the transistor 101. In this manner, the off-state current of the transistor 101 can be significantly reduced as described above. Therefore, the leakage of the electric charge can be prevented, and the data retention period can be extended. .

[0044] Unless otherwise specified, in this specification, the off-state current is In this case, the drain electrode is set at a higher potential than the source and gate electrodes. When the potential of the gate electrode is 0 or less with respect to the potential of the source electrode, The off-state current in this specification refers to the current that flows between the drain electrode and the p In a channel type transistor, the drain electrode is lower than the source electrode and the gate electrode. When the potential of the gate electrode is set to a reference potential, the potential of the gate electrode is less than 0. This refers to the current that flows between the source and drain electrodes when the potential is above the threshold.

[0045] A semiconductor material with a wider band gap and lower intrinsic carrier density than silicon Examples of materials include oxide semiconductors, silicon carbide (SiC), gallium nitride (GaN Compound semiconductors such as silicon carbide and gallium nitride are examples of oxide semiconductors. Unlike compound semiconductors such as GaN, they can be produced by sputtering or wet methods. It has the advantage of being easy to mass-produce. Also, unlike silicon carbide or gallium nitride, Since oxide semiconductors can be formed at room temperature, they can be formed on glass substrates or silicon substrates. It is possible to form a film on an integrated circuit using a SiO2 film. It is also possible to accommodate larger substrates. Therefore, oxide semiconductors are particularly suitable for mass production compared to the above-mentioned silicon carbide and gallium nitride. In addition, it has the advantage of improving the performance of transistors (e.g., field effect mobility). Even when trying to obtain a crystalline oxide semiconductor, it requires heat treatment at 250 to 800 degrees Celsius. A crystalline oxide semiconductor can be easily obtained by the treatment.

[0046] In the following description, an oxide semiconductor film having the above-mentioned advantages is used as the semiconductor film of the transistor 101. The case where a semiconductor material is used is given as an example.

[0047] In one embodiment of the present invention, at least a transistor functioning as a switching element 101 has an active layer made of a wide-gap semiconductor material such as the oxide semiconductor described above. On the other hand, the transistor 103 functioning as a memory element may have an oxide semiconductor A conductor may be used, or an amorphous, microcrystalline, or polycrystalline material other than an oxide semiconductor may be used. Semiconductors such as silicon or germanium, either solid or single crystal, may also be used. By using an oxide semiconductor film for the active layer of all the transistors in the memory cell 100, In addition, the transistor 103 functioning as a memory element can be The active layer is made of a material having a higher conductivity than an oxide semiconductor, such as polycrystalline or single-crystalline silicon. By using a semiconductor material that provides mobility, data can be read from the memory cell 100. can be performed at high speed.

[0048] In FIG. 1B, the memory cell 100 is a transistor that functions as a switching element. Although the present invention is not limited to a single configuration, the present invention is not limited to this configuration. In one embodiment of the present invention, at least one transistor that functions as a switching element is provided in each memory cell. It is sufficient to provide one transistor, and the number of the transistors may be more than one. When the 00 has a plurality of transistors functioning as switching elements, The transistors may be connected in parallel, in series, or in both series and Parallel connections may also be combined.

[0049] In this specification, the state in which transistors are connected in series refers to, for example, a first Only one of the first terminal and the second terminal of the first transistor is connected to the first terminal of the second transistor. This means that the transistor is connected to only one of the terminals. A state in which transistors are connected in parallel is when the first terminal of a first transistor is connected to the a second terminal of the first transistor connected to a first terminal of the second transistor; It means that it is connected to a child.

[0050] The transistor 103 functioning as a memory element functions as a switching element. Unlike the transistor 101, the transistor has at least a gate electrode that is present on only one side of the active layer. However, the present invention is not limited to this configuration, and any transistor that functions as a memory element may be used. The transistor 103 is also an active transistor, similar to the transistor 101 that functions as a switching element. There may be a pair of gate electrodes with the layer between them.

[0051] Next, FIG. 1C shows a cross-sectional view of the transistor 101 shown in FIG. An example of the figure is shown.

[0052] In FIG. 1C, the transistor 101 is a first A gate electrode 111, an insulating film 112 on the first gate electrode 111, and a semiconductor device having the insulating film 112 therebetween. an oxide semiconductor film 113 functioning as an active layer, which overlaps the first gate electrode 111; , a source electrode 114 and a drain electrode 115 on the oxide semiconductor film 113, and the oxide semiconductor film 113, an insulating film 116 on the source electrode 114 and the drain electrode 115, The second gate electrode 117 overlaps with the oxide semiconductor film 113 . In FIG. 1C, an insulating film 118 is formed on the second gate electrode 117. The transistor 101 may include an insulating film 118 as one of its components.

[0053] Note that FIG. 1C illustrates the case where the transistor 101 has a single-gate structure. However, the transistor 101 has a plurality of gate electrodes electrically connected to each other. A multi-gate structure having a plurality of channel forming regions may also be used.

[0054] Then, the threshold voltage of the transistor 101 is changed by changing the potential of the second gate electrode. First, a circuit diagram of a transistor 101 is shown in FIG. In FIG. 2A, the potential of the first gate electrode is Vcg, the potential of the second gate electrode is Vbg, The potential of the source electrode is Vs and the potential of the drain electrode is Vd. The potential of each electrode is shown.

[0055] FIG. 2B shows the value of the drain current Id of the transistor 101 versus the gate voltage Vgs. The gate voltage Vgs is the first gate potential Vs when the potential of the source electrode is taken as the reference. This corresponds to the difference between the potential Vcg of the gate electrode and the potential Vs of the source electrode.

[0056] The solid line 120 indicates the potential Vbg of the second gate electrode and the potential Vs of the source electrode. The figure shows the value of the drain current Id relative to the gate voltage Vgs when the The dashed line 121 indicates the potential Vbg of the second gate electrode and the potential Vs of the source electrode. The figure shows the value of the drain current Id relative to the gate voltage Vgs when the gate voltage Vgs is lower than The line 120 and the line 121 are connected to each other such that the source electrode potential Vs is the same and the drain The potentials Vd of the electrodes are also assumed to be the same.

[0057] As shown in FIG. 2B, the potential Vbg of the second gate electrode of the transistor 101 is low. Indeed, the threshold voltage is shifted to the positive side and the off-current is reduced. The threshold voltage of the transistor 101 becomes negative as the potential Vbg of the second gate electrode becomes higher. side, and the off-current increases, that is, the on-resistance decreases.

[0058] In the storage device according to one embodiment of the present invention, as described above, the length of the data retention period is determined by the storage element The amount of charge stored in the transistor 101 leaks through the transistor 101. In one embodiment, the potential Vbg of the second gate electrode of the transistor 101 is controlled. Since the off-state current of the device can be significantly reduced, the leakage of the charge can be prevented. This allows the data to be retained for a longer period.

[0059] Next, an example of a configuration of a memory device having a plurality of memory cells and a method of driving the memory device will be described. do.

[0060] FIG. 3 is a circuit diagram of a cell array 200 having a plurality of memory cells 100 shown in FIG. The configuration of the memory cell 100 is the same as that described in the first embodiment. can be taken into consideration.

[0061] In the cell array 200 shown in FIG. CG , a plurality of second word lines W LBG , a plurality of bit lines BL, a plurality of capacitance lines CL, a plurality of source lines SL, and other wirings. A signal or potential from the driving circuit is applied to each memory cell 10 via these wirings. 0 is provided.

[0062] First word line WL CG is connected to the first gate electrode of the transistor 101. 2 word lines WL BG is connected to the second gate electrode of the transistor 101. The output line BL is connected to a first terminal of the transistor 101 and a first terminal of the transistor 103. The source line SL is connected to the second terminal of the transistor 103. L is one of the pair of electrodes of the capacitor 102 connected to the second terminal of the transistor 101. The electrode connected to the other electrode is different from the electrode connected to the other electrode.

[0063] The number of wirings can be determined depending on the number and arrangement of the memory cells 100. Specifically, in the case of the cell array 200 shown in FIG. 3, memory cells are arranged in a matrix of y rows and x columns. connected to the first word line WL CG 1~WL CG y, second word line WL BG 1~WL BG y, capacitance lines CL1 to CLy, source lines SL1 to SLy, and bit lines BL1 to BLx. The case where it is arranged in a cell array 200 is illustrated.

[0064] Next, the operation of the cell array 200 shown in FIG. 3 will be described with reference to the timing chart of FIG. In FIG. 4, the memory cell in the first row and the first column, the memory cell in the first row and the xth column, Data is written and stored in the memory cell in the yth row and the 1st column and the memory cell in the yth row and the xth column. In FIG. 4, the transistor 103 is a p-channel transistor. 4 shows an example of a multi-channel transistor.

[0065] The shaded areas in the timing chart of Figure 4 indicate whether the potential is high or low. But it means a good period.

[0066] First, the operation of the cell array 200 in the data write period Ta will be described.

[0067] Data is written row by row. In FIG. 4, the memory cell in the first row and the first column The data is written to the memory cell in the yth row and the 1st column first. 13 illustrates an example in which data is written to a memory cell in the yth row and the xth column.

[0068] First, the first word line WL CG 1 and capacitance line CL1 is selected. Specifically, in FIG. 4, the first word line WL CG 1 has a high-level potential V H is applied to the first word line WL CG 2~WL CG The ground potential GND is applied to y. Therefore, the first word line WL CG A transistor having a first gate electrode connected to Only the resistor 101 is selectively turned on. The ground potential GND is applied to the capacitance line CL1. A high-level potential VDD is applied to the other capacitance lines CL2 to CLy.

[0069] And the first word line WL CG During the period when bit 1 and capacitance line CL1 are selected, A potential of a signal including data is applied to the bit lines BL1 and BLx. The level of the potential applied to the bit line B naturally differs depending on the data content. A high-level potential VDD is applied to L1, and a ground potential GND is applied to the bit line BLx. The potential applied to the bit lines BL1 and BLx is One of the electrodes of the capacitor 102 and the gate of the transistor 103 are connected to each other through the capacitor 101. Then, one of the electrodes of the capacitor 102 and the transistor 103 If the node to which the gate electrode of is connected is the node FG, then according to the potential of the above signal, By controlling the amount of charge stored in the node FG, the memory cell in the first row and the first column Data is written to the memory cells in the xth column.

[0070] Next, the first word line WL CG A ground potential GND is applied to the first word line WL CG 1 The transistor 101, having a first gate electrode connected to the first gate electrode, is turned off.

[0071] Next, the first word line WL CG y and capacity Specifically, in FIG. 4, the first word line WL CG High level potential on y VH is applied to the first word line WL CG 1~WL CG (y-1) is at ground potential GND is applied. Therefore, the first word line WL CG The first gate electrode is connected to y. Only the transistor 101 connected to the capacitance line CLy is selectively turned on. GND is applied, and the other capacitance lines CL1 to CL(y-1) are applied with a high-level potential VDD. can be obtained.

[0072] And the first word line WL CG During the period when the bit line CLy and the capacitance line CLy are selected, A potential of a signal including data is applied to the bit lines BL1 and BLx. A ground potential GND is applied to the bit line BL1, and a high-level potential VDD is applied to the bit line BLx. The potential applied to the bit lines BL1 and BLx is the same as that of the on-transistor. One of the electrodes of the capacitor 102 and the gate electrode of the transistor 103 are connected via the gate electrode 101. The amount of charge stored in the node FG is controlled according to the potential of the signal. By controlling this, data is written to the memory cell in the yth row, column 1 and the memory cell in the yth row, column x. The inclusion takes place.

[0073] During the write period Ta, the ground potential GND is applied to all the source lines SL. With the above configuration, when the ground potential GND is applied to the node FG, the bit line BL This can suppress the generation of a current in the source line SL.

[0074] In addition, in order to prevent erroneous data from being written to the memory cell, the first word line WL CG After the selection period of the capacitance line CL is ended, the potential of a signal including data is input to the bit line BL. It is advisable to end the period during which the

[0075] Next, the operation of the cell array 200 during the data retention period Ts will be described.

[0076] During the retention period Ts, all the first word lines WL CG At this time, transistor 101 is off. A potential of a certain level, specifically, a ground potential GND, is applied. During the retention period Ts, the second word line WLBG All of the resistors have a lower potential than the ground potential GND. Therefore, the transistor 101 has a threshold voltage of 100V. The off-state current of the transistor 101 is low because the off-state current of the transistor 101 is shifted to the positive side. Then, the charge stored in node FG is less likely to leak, so data is stored for a long period of time. Retention can be performed.

[0077] Next, the operation of the cell array 200 in the data read period Tr will be described.

[0078] First, the capacitance line CL1 of the memory cell in the first row from which data is to be read is selected. In FIG. 4, the ground potential GND is applied to the capacitance line CL1, and the other capacitance lines CL2 to CLy are In the read period Tr, the potential VDD of all the first word lines is applied. W.L. CG The pins are in a non-selected state when the ground potential GND is applied. During the period when the control line CL1 is selected, a high-level voltage is applied to all the source lines SL. The potential VR is given. The potential VR is either the same as the potential VDD or is lower than the potential VDD. It is assumed that the potential is lower and higher than the ground potential GND.

[0079] The resistance between the source and drain electrodes of the transistor 103 is a function of the current stored at the node FG. Therefore, the bit lines BL1 and BLx depend on the charge stored in the node FG. Then, by reading the difference in the amount of charge from the potential, Data can be read from the memory cell in the first row and first column and the memory cell in the first row and xth column. do.

[0080] Next, the capacitance line CLy of the memory cell in the y-th row from which data is to be read is selected. In FIG. 4, the capacitance line CLy is applied with a ground potential GND, and the other capacitance lines CL1 to CL(y A high-level potential VDD is applied during the read period T In r, all the first word lines WL CG When the ground potential GND is applied, the pin is put into the unselected state. In addition, while the capacitance line CLy is selected, all the sources A high-level potential VR is applied to the line SL.

[0081] The resistance between the source and drain electrodes of the transistor 103 is a function of the current stored at the node FG. Therefore, the bit lines BL1 and BLx depend on the charge stored in the node FG. Then, by reading the difference in the amount of charge from the potential, Data can be read from the memory cell in row y, column 1 and the memory cell in row y, column x. do.

[0082] A read circuit is connected to the tip of each bit line BL, and the output signal of the read circuit is contains the data actually read from the cell array.

[0083] In addition, in FIG. 4, the write period Ta, the hold period Ts, and the read period Tr are all And the second word line WL BG For example, assume that the low-level potential VSS is applied to all of the However, in one embodiment of the present invention, the second word line WL BG For example, a low-level potential VSS may be applied to the memory cell. In order to speed up data writing, the second word is written to the row where data is written. Do line WLBG The potential of the transistor 101 is made higher than the potential VSS to lower the threshold voltage of the transistor 101. It may be possible to do so.

[0084] The timing chart shown in FIG. 5 shows the second word line WL BG Electricity Only the position is different from that in FIG. 4. Specifically, in FIG. 5, in the write period Ta, W.L. CG During the period when 1 is selected, the second word of the memory cell in the row to be written line WL BG A ground potential GND is applied to the first word line WL CG y selected During this period, the second word line WL BG y A ground potential GND is applied to the MOS transistor. Data is written using the above configuration. Since the threshold voltage of the transistor 101 can be lowered during the hold period Ts While suppressing the leakage of charge during the write period Ta, This can speed up writing.

[0085] Next, another example of the configuration of a memory device having a plurality of memory cells and a driving method thereof will be described. explain.

[0086] FIG. 6 is a circuit diagram of a cell array 300 having a plurality of memory cells 100 shown in FIG. The configuration of the memory cell 100 is the same as that described in the first embodiment. can be taken into consideration.

[0087] In the cell array 300 shown in FIG. CG , a plurality of second word lines W L BG, a plurality of bit lines BL, a plurality of capacitance lines CL, and other wirings are provided. A signal or potential from the circuit is supplied to each memory cell 100 via these wirings.

[0088] First word line WL CG is connected to the first gate electrode of the transistor 101. 2 word lines WL BG is connected to the second gate electrode of the transistor 101. The capacitance line BL is connected to a first terminal of the transistor 101. One of the pair of electrodes of the transistor 102 is connected to the second terminal of the transistor 101. is connected to a different electrode.

[0089] The number of wirings can be determined depending on the number and arrangement of the memory cells 100. Specifically, in the case of the cell array 300 shown in FIG. 6, memory cells are arranged in a matrix of y rows and x columns. connected to the first word line WL CG 1~WL CG y, second word line WL BG 1~WL BG y, capacitance lines CL1 to CLy, and bit lines BL1 to BLx are arranged in the cell array 300. This shows an example of a case where

[0090] Next, the operation of the cell array 300 shown in FIG. 6 will be described.

[0091] First, the operation of the cell array 300 during the data write period will be described. During the write period, the first word line WL CG When a signal with a pulse is input to 1, the The potential of the first word line WL CG Connected to 1 This is applied to the first gate electrode of the transistor 101. Thus, the first word line WL CG 1 All of the transistors 101 having their first gate electrodes connected to

[0092] Next, a signal including data is input to the bit lines BL1 to BLx. The potential level of the signal input to BLx naturally differs depending on the data content. The potential input to BL1 to BLx is supplied to the capacitance element 101 via the transistor 101 that is turned on. A fixed potential is applied to all the capacitance lines CL. The amount of charge stored in the capacitance element 102 is controlled according to the potential of the signal. By controlling this, data is written to the capacitor 102.

[0093] First word line WL CG When the input of the pulsed signal to the first word line W L CG All of the transistors 101 having their first gate electrodes connected to terminal 1 are turned off. And the first word line WL CG 2~WL CG A signal having a pulse is input to y in sequence, First word line WL CG 2~WL CG In the memory cell 100 having y, the above-described operation is repeated in the same manner.

[0094] Next, the operation of the cell array 300 during the data retention period will be described. In this case, all the first word lines WL CG 1~WL CG In y, transistor 101 is off. A potential of a level at which the potential becomes low, specifically, a low-level potential, is applied. In this embodiment, during the retention period, all the second word lines WL BG A low-level potential VSS is applied to Therefore, the threshold voltage of the transistor 101 is shifted to the positive side. When the off-state current of the transistor 101 is low, the charge stored in the capacitor 102 is reduced. The stored charge is less likely to leak, so data can be retained for a long period of time. do.

[0095] Next, the operation of the cell array 300 during the data read period will be described. During the data read period, the first word line WL CG 1~WL CG To y A signal having a pulse is input in sequence. The potential of the pulse, specifically, the high level potential However, the first word line WL CG 1 to the first gate electrode of transistor 101 connected to When applied, all of the transistors 101 are turned on.

[0096] When the transistor 101 is turned on, the charge stored in the capacitance element 102 is transferred through the bit line BL. The charge is extracted. The difference in the amount of charge is then read from the potential of the bit line BL. The data can be read out by

[0097] A read circuit is connected to the tip of each bit line BL, and the output signal of the read circuit is contains the data actually read from the store.

[0098] In this embodiment, each operation of writing, holding, and reading is performed on a plurality of memory cells 100. In the above, a driving method in which the driving is performed in sequence has been described, but the present invention is not limited to this configuration. Alternatively, the above operation may be performed only in the memory cell 100 at the specified address.

[0099] As in the case of the timing chart shown in FIG. 5, data is written to the memory cell. In order to increase the speed of the write operation, the second word line WL BG Electricity The threshold voltage of the transistor 101 can be reduced by setting the potential higher than the potential VSS. good.

[0100] Note that a memory device according to one embodiment of the present invention has the configuration of the memory cell 100 shown in FIGS. Not limited.

[0101] FIG. 8A shows another example of the configuration of the memory cell 100. The rechargeable cell 100 includes a transistor 101, a capacitor 102, and a transistor 103. The first gate electrode of the transistor 101 is connected to the first word line WL CG Connected to The second gate electrode of the transistor 101 is connected to the second word line WL BG Connected to A first terminal of the transistor 101 is connected to the bit line BL. The second terminal of the transistor 101 is connected to the gate electrode of the transistor 103. The first terminal of the transistor 103 is connected to the data line DL. The second terminal of the transistor 103 is The capacitor 102 has a pair of electrodes, one of which is connected to a transistor. The other end is connected to the gate electrode of the transistor 103 and the other end is connected to the capacitance line CL.

[0102] In the case of the memory cell 100 shown in FIG. 8A, a capacitor 102 and a The amount of charge held by the transistor 103 is read by the potential of the data line DL. It is possible.

[0103] Next, FIG. 8B shows another example of the configuration of the memory cell 100. The memory cell 100 shown in FIG. 1 includes a transistor 101, a capacitor 102, and a transistor 103. In addition, a transistor that functions as a switching element to control data reading is also included. The first gate electrode of the transistor 101 is connected to the first word line W.L. CG The second gate electrode of the transistor 101 is connected to a second word line W L BG The first terminal of the transistor 101 is connected to the bit line BL. The second terminal of the transistor 101 is connected to the gate electrode of the transistor 103. The first terminal of the transistor 103 is connected to the second terminal of the transistor 104. The second terminal of the transistor 103 is connected to the source line SL. The first terminal of transistor 104 is connected to data line DL. , the third word line WL SW The capacitor 102 has a pair of electrodes, one of which is connected to The first terminal is connected to the gate electrode of the transistor 103, and the other terminal is connected to the capacitance line CL. do.

[0104] In the case of the memory cell 100 shown in FIG. 8B, when data is read, the third word line WL SW The transistor 104 is turned on by changing the potential of the The amount of charge held by the functioning capacitor 102 and transistor 103 is The potential of the data line DL can be read.

[0105] A storage device according to one aspect of the present invention is configured to write new data to the storage device so as to overwrite previously written data. Therefore, unlike conventional flash memory, data can be written One of the advantages is that there is no need to erase previously written data when rewriting. It is.

[0106] In addition, in the case of typical flash memory, the floating gate that stores the charge is an insulating Therefore, the floating gate is insulated by using the tunnel effect. In order to store electric charges, a high voltage of about 20 V must be applied to the memory element. However, in one embodiment of the present invention, a highly purified oxide semiconductor film is used as an active layer of a transistor. The switching element used as the switching element can write and read data. Therefore, the voltage required for the memory device to operate is only a few volts, significantly reducing power consumption. It is possible to do so.

[0107] In a semiconductor device using a general flash memory, Because the required voltage (operating voltage) is high, a boost circuit is usually used to However, in the memory device according to one embodiment of the present invention, the operation of the memory device is Since the operating voltage can be kept low, the power consumption can be reduced. This reduces the load on external circuits, such as a boost circuit, involved in the operation of the storage device. This allows the functionality of the external circuit to be expanded, thereby enabling the semiconductor device to have higher performance. .

[0108] In this embodiment, the driving method for handling binary digital data has been described. However, the storage device of the present invention can also handle multi-valued data with three or more values. In the case of multi-value data with more than 1000 values, the charge between each value increases as the value increases to 4, 5, etc. Since the difference between the off-state current and the off-state current is small, it is difficult to maintain the accuracy of the data. However, in one embodiment of the present invention, the off-state current is significantly Since a significantly reduced transistor is used as a switching element, the holding period associated with multi-value is reduced. This can prevent the shortening of the interval.

[0109] Next, the second word line WL BG Regarding the configuration of the second word line driving circuit for controlling the potential of An example of a circuit diagram of the second word line driving circuit 150 will be described below. vinegar.

[0110] The second word line driving circuit 150 shown in FIG. 1 (transistor for driving circuit) and a capacitance element 152 (capacitance element for driving circuit). A first terminal of the transistor 151 is supplied with the potential VSS via a terminal A. The first gate electrode and the second gate electrode of the transistor 151 are The capacitor element 152 has a pair of electrodes. One of the electrodes is connected to the second terminal of the transistor 151, and the other A predetermined potential is applied to the second terminal of the transistor 151. Wire WL BG is connected to

[0111] Specifically, in FIG. 7, the second word line driver circuit 150 includes a transistor 151 and a capacitor element 15 The second transistor 151 has m pairs of 2 (m is a natural number of 2 or more). The terminal has n (n is a natural number greater than or equal to 1) second word lines WL BG is connected.

[0112] Second word line WL BG When the potential of the first input is higher than the potential VSS, the first input is connected to the first output through the transistor 151. 2 word lines WL BG Therefore, a current flows from the second word line WL B G The potential is set to a potential higher than the potential VSS by the threshold voltage of the transistor 151. This potential is sufficiently lower than the potential of the source electrode of the transistor 101 in the memory cell 100. If it is possible to set the threshold voltage of the transistor 101 to be higher, The off-state current of the transistor 101 is reduced. Therefore, the retention characteristics of the memory device can be improved. This can be done.

[0113] The supply of the potential VSS to the second word line driving circuit 150 is stopped, and the potential of the terminal A becomes the second Word line WL BG If the potential of the transistor 151 becomes higher than the potential of the transistor 151, the transistor 151 becomes reverse biased. Since a voltage of 1 V is applied, the current flowing through the transistor 151 is only an off-state current. The current charges the capacitance element 152, and the second word line WL BG The potential of Finally, the source electrode and the second gate electrode of the transistor 101 are connected to Since the potential difference between the transistor 101 and the transistor 102 is small, the off-state current of the transistor 101 can be sufficiently reduced. However, the capacitive element 152 is not connected to the outside of the cell array. Since it can be arranged in the memory cell, it has a larger capacitance value than the capacitance element 102 in the memory cell. Therefore, the capacitance of the capacitor 152 can be secured within the memory cell. If the capacitance of the capacitance element 102 is increased by, for example, 100 times, the capacitance of the second word line WL BG Electricity This makes it possible to increase the time it takes for the rank to reach its upper limit by 100 times. If the period during which the supply of the potential VSS is stopped is short, the data stored in the storage device is This allows you to avoid losing data.

[0114] Note that the transistor 151 does not necessarily have to have a second gate electrode. As shown in FIG. 7, a second gate electrode is provided to the transistor 151. Connecting the electrode to the second terminal of transistor 151 is desirable for the following reasons. When the above configuration is adopted, the transistor 151, which functions as a diode, is forward biased. When a voltage of 0 V is applied to the transistor 151, the transistor 151 is turned on because its threshold voltage is low. The current becomes high and the second word line WL BG It is possible to increase the current supply capacity to the When the above configuration is adopted, a reverse bias voltage is applied to the transistor 151. At this time, the threshold voltage of the transistor 151 becomes high, so that the off-state current becomes low, and the second Wire WL BG This can extend the time it takes for the potential of the electrode to reach its upper limit.

[0115] In addition, in FIG. 7, as shown in the timing chart of FIG. BG Constant 1 illustrates an example of the configuration of the second word line driving circuit 150 when supplying the potential VSS. As shown in the timing chart of FIG. 5, in the write period, the second word line WL BG To When supplying a power supply voltage VSS and a ground potential GND, terminal A in Figure 7 is used as a DC power supply. Connect to a signal source.

[0116] (Embodiment 2) In this embodiment, a transistor 101 using an oxide semiconductor and a transistor 102 using silicon are A method for manufacturing a memory device having the transistor 103 will be described.

[0117] However, the transistor 103 may be made of germanium, silicon germanium, or Semiconductor materials such as single crystal silicon carbide may also be used. The transistor 103 is made of a single crystal semiconductor substrate such as a silicon wafer by an SOI method. The silicon thin film is formed by using a silicon thin film fabricated by a vapor phase growth method, etc. Alternatively, in one embodiment of the present invention, all the transistors constituting the memory cell can be An oxide semiconductor may be used for the second insulating film 111 .

[0118] In this embodiment, first, as shown in FIG. 9A, an insulating film 701 and a single layer are formed on a substrate 700. An island-like semiconductor film 702 separated from a crystalline semiconductor substrate is formed.

[0119] There is no particular limitation on the material that can be used for the substrate 700, but at least the material that can be used for subsequent processing should be The substrate 700 must have sufficient heat resistance to withstand heat treatment. Glass substrates manufactured by the fusion method or float method, quartz substrates, semiconductor substrates, ceramic A glass substrate can be used if the temperature of the subsequent heat treatment is high. It is advisable to use a material with a strain point of 730°C or higher.

[0120] In this embodiment mode, the semiconductor film 702 is made of single crystal silicon. A method for manufacturing the transistor 103 will be described below. An example of a method for manufacturing the film 702 will be briefly described. An ion beam consisting of ions accelerated by an electric field is injected into the bond substrate, and the surface of the bond substrate is A brittle layer is formed in a region at a certain depth from the surface, where the crystal structure is disrupted and weakened locally. The depth of the region where the embrittlement layer is formed depends on the acceleration energy of the ion beam and the The incident angle can be adjusted. Then, a bond substrate and an insulating film 701 are formed. The insulating film 701 is sandwiched between the substrate 700 and the insulating film 701. After the bond substrate and the substrate 700 are superimposed, a 1N / cm 2 More than 500N / cm 2 Less than 11N / cm, preferably 11N / cm 2 More than 20N / cm 2 below When pressure is applied to a part, the bond substrate and the insulating film 701 are separated from that part. The bonding process begins, and eventually the bonding spreads over the entire contact surface. As a result, the microvoids in the embrittlement layer expand and join together. At the embrittlement layer, the single crystal semiconductor film, which is a part of the bond substrate, is separated from the bond substrate. The temperature of the heat treatment is set to a temperature not exceeding the distortion point of the substrate 700. The semiconductor film is processed into a desired shape by etching or the like to form an island-shaped semiconductor film 702. It can be achieved.

[0121] The semiconductor film 702 is doped with boron, aluminum, gallium, or the like in order to control the threshold voltage. Impurity elements that impart p-type conductivity, or elements such as phosphorus and arsenic that impart n-type conductivity An impurity element may be added. The addition of an impurity element for controlling the threshold voltage is performed by patterning. This may be performed on the semiconductor film before it is patterned, or on the semiconductor film 7 formed after patterning. The doping of impurity elements for controlling the threshold voltage may be performed on the BON. Alternatively, the doping of impurity elements may be performed on the substrate to roughly adjust the threshold voltage. To fine-tune the threshold voltage, a bond substrate was used. This can be performed on the previous semiconductor film or on the semiconductor film 702 formed by patterning. That's fine.

[0122] In this embodiment mode, an example in which a single crystal semiconductor film is used is described. For example, a multilayer film formed on the insulating film 701 by vapor deposition may be used. A crystalline, microcrystalline, or amorphous semiconductor film may be used, and the semiconductor film may be fused by a known technique. Known crystallization methods include laser crystallization using a laser beam, and a method using a catalyst element. Alternatively, a crystallization method using a catalytic element and a laser crystallization method may be combined. In addition, when a substrate having excellent heat resistance such as quartz is used, In this case, the thermal crystallization method using an electric furnace, the lamp annealing crystallization method using infrared light, and the catalytic element Alternatively, a crystallization method using a high-temperature annealing method at about 950° C. may be used. stomach.

[0123] Next, as shown in FIG. 9B, after forming a gate insulating film 703 on the semiconductor film 702, A mask 705 is formed on the gate insulating film 703, and an impurity element that gives conductivity is doped on the semiconductor film By doping a part of 702 , an impurity region 704 is formed.

[0124] The gate insulating film 703 is formed by performing high density plasma treatment, heat treatment, etc. The surface of the 2 can be oxidized or nitrided. For example, rare gases such as He, Ar, Kr, and Xe, oxygen, nitrogen oxide, ammonia, nitrogen, and hydrogen. In this case, the plasma is excited by the introduction of microwaves. This allows the generation of high-density plasma at low electron temperature. Zuma-generated oxygen radicals (which may also contain OH radicals) and nitrogen radicals (NH The surface of the semiconductor film is oxidized or nitrided by a method that may include radicals. An insulating film having a thickness of 1 to 20 nm, preferably 5 to 10 nm, can be formed so as to be in contact with the semiconductor film. For example, nitrous oxide (N 2 O) is diluted 1 to 3 times (flow ratio) with Ar and kept at 10 to 30 Pa The semiconductor film 702 was heated by applying microwave (2.45 GHz) power of 3 to 5 kW at a pressure of 1000 MPa. The surface is oxidized or nitrided. This treatment reduces the thickness by 1 nm to 10 nm (preferably 2 nm to Then, a nitrous oxide (N 2 O) and silane (SiH 4 ) was introduced. , and 3 to 5 kW microwave (2.45 GHz) power was applied at a pressure of 10 to 30 Pa. A silicon oxynitride film is formed by vapor phase growth to form a gate insulating film. By combining the reaction by the growth method, the gate insulating film with low interface state density and excellent dielectric strength is obtained. A velum can be formed.

[0125] The oxidation or nitridation of the semiconductor film by the above-mentioned high-density plasma treatment proceeds as a solid-phase reaction. The interface state density between the insulating film 703 and the semiconductor film 702 can be made extremely low. The insulating film formed by directly oxidizing or nitriding the semiconductor film 702 by high-density plasma treatment In addition, when the semiconductor film has crystallinity, it is possible to suppress the variation in the thickness of the insulating film. By using a plasma treatment to oxidize the surface of the semiconductor film through a solid-phase reaction, This prevents oxidation from progressing too quickly at the interface, and provides a gate with good uniformity and low interface state density. The insulating film formed by the high density plasma treatment is then applied to the gate The transistor formed by including the insulating film in part or in whole can suppress the variation in characteristics. can be done.

[0126] In addition, silicon oxide, silicon nitride oxide, and oxide can be formed by using a plasma CVD method or a sputtering method. Silicon nitride, silicon nitride, hafnium oxide, aluminum oxide or tantalum oxide, yttrium oxide Thorium, hafnium silicate (HfSixOy(x>0,y>0)), nitrogen doped Hafnium silicate (HfSixOy(x>0,y>0)), nitrogen-doped hafnium A film containing fluorine aluminate (HfAlxOy (x>0, y>0)) etc. is used as a single layer or The gate insulating film 703 may be formed by stacking.

[0127] In this specification, an oxynitride is a material having a composition in which oxygen is more abundant than nitrogen. Nitrogen oxide is a substance that contains more nitrogen than oxygen. It means substance.

[0128] The thickness of the gate insulating film 703 is, for example, 1 nm or more and 100 nm or less, preferably 10 nm or less. In this embodiment, the thickness can be set to 50 nm or less by using a plasma CVD method. A single layer insulating film containing silicon oxide is used as the gate insulating film 703 .

[0129] Next, after removing the mask 705, as shown in FIG. 9(C), The portion is removed, and an opening 706 is formed in the region overlapping the impurity region 704 by etching or the like. After that, a gate electrode 707 and a conductive film 708 are formed.

[0130] The gate electrode 707 and the conductive film 708 are formed by forming a conductive film so as to cover the opening 706. The conductive film can be processed (patterned) into a predetermined shape to form the conductive film. The film 708 is in contact with the impurity region 704 at the opening 706. The deposition method may be a CVD method, a sputtering method, a vapor deposition method, a spin coating method, or the like. The conductive film is made of tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (M o), aluminum (Al), copper (Cu), chromium (Cr), niobium (Nb), etc. An alloy containing the above metal as a main component may be used, or a compound containing the above metal may be used. Alternatively, a semiconductor film doped with an impurity element such as phosphorus that provides electrical conductivity may be used. Alternatively, the insulating film 12 may be formed using a semiconductor such as polycrystalline silicon.

[0131] In this embodiment mode, the gate electrode 707 and the conductive film 708 are formed of a single-layer conductive film. However, this embodiment is not limited to this structure. It may be formed of a plurality of layered conductive films.

[0132] The combination of two conductive layers is tantalum nitride or tantalum for the first layer and tantalum for the second layer. In addition to the above examples, tungsten nitride and tungsten, nitride can be used. Examples include molybdenum and molybdenum, aluminum and tantalum, and aluminum and titanium. Tungsten and tantalum nitride have high heat resistance, so they can be used in the process after forming the two-layer conductive film. In the process, a heat treatment for the purpose of thermal activation can be performed. As a combination, for example, silicon doped with an impurity element that imparts n-type conductivity and nickel silicide, and silicon and tantalum doped with impurity elements that give n-type conductivity. Alternatively, tungsten silicide or the like can be used.

[0133] In the case of a three-layer structure in which three or more conductive films are laminated, a molybdenum film, an aluminum film, and a molybdenum film are laminated. It is advisable to adopt a laminated structure of a dielectric film.

[0134] The gate electrode 707 and the conductive film 708 are made of indium oxide or a mixture of indium oxide and tin oxide. Indium oxide zinc oxide mixture, zinc oxide, zinc aluminum oxide, zinc aluminium oxynitride A light-transmitting conductive oxide film such as aluminum or zinc gallium oxide can also be used. do.

[0135] In addition, the gate electrode 707 and the conductive film 70 are selectively formed by a droplet discharge method without using a mask. The droplet ejection method is a method in which droplets containing a predetermined composition are ejected or sprayed from a fine hole. This refers to a method of forming a specified pattern by using a laser, and the inkjet method falls into this category. Included.

[0136] The gate electrode 707 and the conductive film 708 are formed by ICP (Inductively Coupled Plasma) deposition after the conductive film is formed. Using the inductively coupled plasma (ICP) etching method, Etching conditions (power applied to the coil-type electrode layer, power applied to the substrate side electrode layer) By appropriately adjusting the pressure, the electrode temperature on the substrate side, etc., it is possible to obtain the desired taper shape. The angle of the tapered shape can also be adjusted depending on the shape of the mask. The etching gas can be controlled using chlorine, boron chloride, silicon chloride, etc. fluoride, sulfur fluoride, nitrogen fluoride, etc. A fluorine-based gas or oxygen can be used as appropriate.

[0137] Next, as shown in FIG. 9(D), a conductive film 708 is formed on the gate electrode 707 using the gate electrode 707 and the conductive film 708 as a mask. By adding an impurity element that imparts electrical conductivity to the semiconductor film 702, A channel forming region 710 and a pair of impurity regions 70 sandwiching the channel forming region 710 therebetween. 9 and an impurity region 711 in which an impurity element is further added to a part of the impurity region 704. It is formed on the conductive film 702 .

[0138] In this embodiment, an impurity element (for example, boron) that imparts p-type conductivity is added to the semiconductor film 702. Let us take an example where:

[0139] FIG. 12A is a top view of the memory cell after the above steps are completed. The cross-sectional view taken along the dashed line A1-A2 in FIG. 12(A) corresponds to FIG. 9(D).

[0140] Next, as shown in FIG. 10(A), a gate insulating film 703, a gate electrode 707, a conductive film 7 Insulating films 712 and 713 are formed to cover the insulating film 08. The insulating film 713 is made of silicon oxide, silicon nitride, silicon nitride oxide, silicon oxynitride, or aluminum nitride. In particular, an inorganic insulating film such as aluminum oxide nitride can be used. By using a low-k material for the insulating film 713, the thickness of various electrodes and wirings can be reduced. This is preferable because it is possible to sufficiently reduce the capacitance caused by the insulator film 71. 2. The insulating film 713 may be a porous insulating film made of the above-mentioned material. In the case of a thin film, the dielectric constant is lower than that of a dense insulating film, so parasitic Further reduction in capacitance is possible.

[0141] In this embodiment, the insulating film 712 is made of silicon oxynitride, and the insulating film 713 is made of silicon nitride oxide. In this embodiment, the gate electrode 707 and the conductive film 70 In the illustrated example, an insulating film 712 and an insulating film 713 are formed on the gate 8. Only one insulating film may be formed over the conductive electrode 707 and the conductive film 708, or three or more insulating films may be formed over the conductive film 708. A plurality of insulating films may be laminated.

[0142] Next, as shown in FIG. 10B, the insulating film 712 and the insulating film 713 are subjected to CMP (chemical mechanical polishing). By performing mechanical polishing or etching, the gate electrode 707 and the conductive film 708 are The surface is exposed. In order to improve the characteristics of the transistor 101 to be formed later, It is preferable that the surfaces of the insulating films 712 and 713 be as flat as possible.

[0143] Through the above steps, the transistor 103 can be formed.

[0144] Next, a method for manufacturing the transistor 101 will be described. As shown in FIG. 1, the gate electrode 714 is formed on the insulating film 712 or the insulating film 713. 14 is formed using the same material and the same stacked structure as the gate electrode 707 and the conductive film 708. It is possible to do so.

[0145] The thickness of the gate electrode 714 is 10 nm to 400 nm, preferably 100 nm to 200 nm. In this embodiment, a 150 nm sputtering method using a tungsten target is used. After forming a conductive film for the gate electrode of m, the conductive film is etched into a desired shape. The gate electrode 714 is formed by patterning. It is preferable that the end of the electrode is tapered, since this improves the coverage of the gate insulating film to be laminated thereon. The resist mask may be formed by an ink-jet method. When the film is formed by the jet method, no photomask is used, and therefore the manufacturing cost can be reduced.

[0146] Next, as shown in FIG. 10(D), a gate insulating film 715 is formed on the gate electrode 714. Then, an island-shaped oxide film is formed on the gate insulating film 715 at a position overlapping the gate electrode 714. A semiconductor film 716 is formed.

[0147] The gate insulating film 715 is formed using the same material and the same layered structure as the gate insulating film 703. However, the gate insulating film 715 is preferably formed to prevent impurities such as moisture and hydrogen as much as possible. It is preferable that the silicon oxide film does not contain any oxide. A silicon target or a quartz target is used as the target, and oxygen or uses a mixture of oxygen and argon gas.

[0148] A highly purified oxide semiconductor is obtained by removing impurities and reducing oxygen vacancies. Since the body is extremely sensitive to interface states and interface charges, highly purified oxide semiconductors The interface characteristics between the film 716 and the gate insulating film 715 are important. The gate insulating film 715 in contact with the semiconductor film 716 is required to have high quality.

[0149] For example, high-density plasma CVD using μ-waves (frequency 2.45 GHz) produces dense, high-insulation This is preferable because it allows the formation of a high-quality insulating film with high pressure. By closely contacting the gate insulating film, the interface state is reduced and the interface characteristics are improved. Because it is possible.

[0150] Of course, if a good insulating film can be formed as the gate insulating film 715, sputtering is also possible. Other film formation methods such as the ring method and plasma CVD method can be applied. The insulating film may be one whose film quality or interface characteristics with an oxide semiconductor are improved by heat treatment. In any case, the quality of the gate insulating film must be good. Any material that can reduce the interface state density between the film and the oxide semiconductor and form a good interface is acceptable. .

[0151] Insulating films made of materials with high barrier properties, silicon oxide films with low nitrogen content, and silicon oxynitride films Alternatively, a gate insulating film 715 having a structure in which an insulating film such as a silicon oxide film is laminated may be formed. In this case, insulating films such as silicon oxide films and silicon oxynitride films have high barrier properties and are oxide semiconductors. The insulating film 716 is formed between the insulating film 716 and the insulating layer 716. As an insulating film having high barrier properties, for example, a silicon nitride film or a nitride oxide film is used. Examples of the barrier film include a silicon film, an aluminum nitride film, and an aluminum oxide nitride film. By using an insulating film with high thermal conductivity, impurities in the atmosphere such as moisture or hydrogen, or impurities contained in the substrate Impurities such as alkali metals and heavy metals contained in the oxide semiconductor film 716 and the gate insulating film 7 15 or the interface between the oxide semiconductor film 716 and another insulating film or its vicinity. In addition, when an oxide semiconductor film having a low nitrogen content is formed in contact with the oxide semiconductor film 716, By forming an insulating film such as a silicon film or a silicon oxynitride film, the insulating film with high barrier properties is directly oxidized. This can prevent the semiconductor layer from coming into contact with the nitride semiconductor film 716 .

[0152] For example, the first gate insulating film is formed by sputtering to a thickness of 50 nm to 200 nm. The following silicon nitride films (SiN y (y>0) is formed, and a second gate insulating film is formed on the first gate insulating film. The insulating film is a silicon oxide film (SiO x (x>0) The gate insulating film 715 may be formed with a thickness of 100 nm. can be appropriately set depending on the characteristics required for the transistor, and is 350 nm to 400 It may be on the order of nm.

[0153] In this embodiment, a silicon nitride film having a thickness of 50 nm is formed by sputtering. A gate insulating film 71 having a structure in which a silicon oxide film having a thickness of 100 nm formed by the above method is laminated. Form 5.

[0154] Note that the gate insulating film 715 is in contact with an oxide semiconductor film 716 to be formed later. The gate insulating film 715 is made of a material that is free of hydrogen, since hydrogen can adversely affect the characteristics of the gate insulating film 716. It is preferable that the gate insulating film 715 does not contain hydrogen, hydroxyl groups, or moisture. In order to prevent the inclusion of moisture as much as possible, sputtering is used as a pretreatment for film formation. The substrate 700 on which the gate electrode 714 is formed is preheated in a preheating chamber of the apparatus. It is preferable to desorb and exhaust impurities such as moisture and hydrogen adsorbed on the surface of the substrate. The temperature is 100°C or higher and 400°C or lower, preferably 150°C or higher and 300°C or lower. The exhaust means provided in the preheating chamber is preferably a cryopump. The reason can be omitted.

[0155] The island-shaped oxide semiconductor film 716 is formed by forming an oxide semiconductor film over a gate insulating film 715. The oxide semiconductor film can be formed by processing the oxide semiconductor film into a shape having a thickness of 2 nm. 3 nm or more and 200 nm or less, preferably 3 nm or more and 50 nm or less, and more preferably 3 nm or more and 2 The oxide semiconductor film is formed by sputtering using an oxide semiconductor as a target. The oxide semiconductor film is formed by a method in a rare gas (for example, argon) atmosphere and an oxygen It is sputtered under a mixed atmosphere of rare gas (e.g. argon) and oxygen. It can be formed.

[0156] Note that before the oxide semiconductor film is formed by a sputtering method, argon gas is introduced to the plasma The reverse sputtering is performed to generate a mask, and the dust adhering to the surface of the gate insulating film 715 is removed. In reverse sputtering, the target is sputtered in an argon atmosphere without applying a voltage to the target. A voltage is applied to the substrate side using an RF power source under atmospheric pressure to form plasma near the substrate and modify the surface. It is to be noted that nitrogen, helium, or the like may be used in place of the argon atmosphere. Alternatively, the treatment may be carried out in an atmosphere in which oxygen, nitrous oxide, etc. are added to an argon atmosphere. Alternatively, the treatment may be carried out in an atmosphere in which chlorine, carbon tetrafluoride, etc. have been added to the argon atmosphere.

[0157] The oxide semiconductor film may be formed of any of the above-mentioned indium oxide, tin oxide, zinc oxide, and binary gold oxide. In-Zn oxides, Sn-Zn oxides, Al-Zn oxides, Zn -Mg oxide, Sn-Mg oxide, In-Mg oxide, In-Ga oxide, ternary In-Ga-Zn oxide (also written as IGZO), which is an oxide of In-Al -Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga- Zn-based oxide, Sn-Al-Zn-based oxide, In-Hf-Zn-based oxide, In-La-Z n-type oxide, In-Ce-Zn-type oxide, In-Pr-Zn-type oxide, In-Nd-Zn In-Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide Oxide, In-Tb-Zn oxide, In-Dy-Zn oxide, In-Ho-Zn oxide oxides, In-Er-Zn oxides, In-Tm-Zn oxides, In-Yb-Zn oxides In-Lu-Zn ​​oxides, In-Sn-Ga-Zn oxides, which are oxides of quaternary metals oxides, In-Hf-Ga-Zn oxides, In-Al-Ga-Zn oxides, In-Sn -Al-Zn oxide, In-Sn-Hf-Zn oxide, In-Hf-Al-Zn oxide Compounds such as fluorine-containing fluorine compounds can be used.

[0158] In this embodiment, a tantalum containing In (indium), Ga (gallium), and Zn (zinc) is used. A 30 nm thick In-Ga-Zn oxide semiconductor was obtained by sputtering using a Zn-type target. A thin film of a conductor is used as an oxide semiconductor film. When the film is formed by the ion-spraying method, the atomic ratio of In:Ga:Zn is preferably 1:1:1. In-, indicated as 4:2:3, 3:1:2, 1:1:2, 2:1:3, or 3:1:4 A target of Ga-Zn oxide is used. In-Ga-Zn oxide with the above-mentioned atomic ratio is used. By forming an oxide semiconductor film using an oxide target, a polycrystalline or CAAC film can be obtained. In addition, the filling rate of the target containing In, Ga, and Zn is 90% or more. The filling rate is preferably 95% or more and less than 100%. By using such a material, the formed oxide semiconductor film becomes a dense film.

[0159] When an In-Zn oxide material is used as the oxide semiconductor, the target to be used is The composition ratio is In:Zn=50:1 to 1:2 in atomic ratio (In in mole ratio). 2 O 3 ZnO=25:1 to 1:4), preferably In:Zn=20:1 to 1:1 (molar ratio Converted to In 2 O 3 In:ZnO=10:1 to 1:2), more preferably In:Zn= 1.5:1 to 15:1 (converted to molar ratio: In 2 O 3 :ZnO=3:4~15:2) For example, the target used for forming an oxide semiconductor film made of an In-Zn oxide is When the atomic ratio is In:Zn:O=X:Y:Z, Z>1.5X+Y. The ratio of Zn Within the above range, it is possible to improve the mobility.

[0160] In this embodiment, the substrate is held in a processing chamber that is maintained in a reduced pressure state, and residual moisture in the processing chamber is removed. While removing the hydrogen and moisture, a sputtering gas from which hydrogen and moisture have been removed is introduced, and the above target is used. During the deposition, the substrate temperature is set to 100° C. or higher and 600° C. or lower, preferably. The deposition temperature may be 200° C. or more and 400° C. or less. In addition, the concentration of impurities in the oxide semiconductor film can be reduced. To remove residual moisture in the processing chamber, a suction-type vacuum pump is used. For example, a cryopump, an ion pump, a titanium sublimation pump, etc. It is preferable to use a displacement pump as the exhaust means. A cryopump may be used to evacuate the processing chamber. For example, hydrogen atoms, water (H 2 O), etc. (more preferably, a compound containing a carbon atom Since the exhaust gas contains the compound containing the compound, the oxide semiconductor film formed in the treatment chamber is The concentration of impurities can be reduced.

[0161] As an example of the deposition conditions, the distance between the substrate and the target is 100 mm, and the pressure is 0.6 Pa. The conditions were: DC power supply 0.5kW, oxygen (oxygen flow rate 100%) atmosphere. In addition, if a pulsed direct current (DC) power supply is used, dust generated during film formation can be reduced, and the film can be This is preferable since the thickness distribution is also uniform.

[0162] In order to prevent hydrogen, a hydroxyl group, and moisture from being contained in the oxide semiconductor film as much as possible, As a pre-treatment for film formation, the gate insulating film 715 is formed in the pre-heating chamber of the sputtering device. The substrate 700 is preheated to remove impurities such as moisture or hydrogen adsorbed on the substrate 700. The preheating temperature is preferably 100°C or higher and 400°C or lower. The temperature is preferably 150°C or higher and 300°C or lower. A pump is preferable. However, this preheating process can be omitted. Heating is performed on the conductive films 719 and 720 before the formation of the gate insulating film 721, which is performed later. The same process may be performed on the formed substrate 700 .

[0163] Note that the etching for forming the island-shaped oxide semiconductor film 716 is performed by dry etching. Dry etching may be performed by wet etching or by both. The gas used is a gas containing chlorine (chlorine-based gas, e.g., chlorine (Cl 2 ), boron trichloride ( BCl 3 ), silicon tetrachloride (SiCl 4 ), carbon tetrachloride (CCl 4 ) is preferred. In addition, gases containing fluorine (fluorine-based gases, such as carbon tetrafluoride (CF 4 ), sulfur hexafluoride (SF 6 ), nitrogen trifluoride (NF 3 ), trifluoromethane (CHF 3 ), Hydrogen bromide (HB r), oxygen (O 2 ), and rare gases such as helium (He) and argon (Ar) are added to these gases. A gas containing , etc. can be used.

[0164] As a dry etching method, parallel plate type RIE (Reactive Ion Etch) ing method and ICP (Inductively Coupled Plasma) A method of etching a silicon wafer using a plasma-coupled plasma (PPS) can be used. As shown in the figure, the etching conditions (the amount of power applied to the coil-shaped electrode, the amount of power applied to the electrode on the substrate side) The amount of power, the temperature of the electrode on the substrate, etc. are adjusted appropriately.

[0165] The etching solution used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. In the present embodiment, an organic acid such as phosphoric acid or oxalic acid can be used. (Kanto Chemical Co., Ltd.) is used.

[0166] A resist mask for forming the island-shaped oxide semiconductor film 716 is formed by an inkjet method. If the resist mask is formed by the inkjet method, no photomask is required. This reduces manufacturing costs.

[0167] Note that reverse sputtering is performed before a conductive film is formed in the next step, and the island-shaped oxide semiconductor film 716 and It is also preferable to remove resist residues adhering to the surface of the gate insulating film 715. .

[0168] Note that moisture or hydrogen (water) may be contained as an impurity in the oxide semiconductor film formed by sputtering or the like. Water or hydrogen tends to form donor levels. Therefore, in one embodiment of the present invention, In order to reduce impurities such as moisture or hydrogen in the conductor film (dehydration or dehydrogenation), The oxide semiconductor film 716 is heated under a reduced pressure atmosphere with an inert gas atmosphere such as nitrogen or a rare gas. Under oxygen gas atmosphere or ultra dry air (CRDS (Cavity Ring Down Laser Separator) When measured using a dew point meter using the optical method, the moisture content is 20 ppm (-55°C in dew point equivalent). In an atmosphere of less than 1 ppm, preferably less than 10 ppb, the island-shaped The oxide semiconductor film 716 is subjected to heat treatment.

[0169] By performing heat treatment on the island-shaped oxide semiconductor film 716, Specifically, the temperature is 250° C. or higher and 750° C. or lower, preferably Alternatively, the heat treatment may be performed at a temperature of 400° C. or higher but lower than the distortion point of the substrate. If the RTA method is used for the heat treatment, the delamination can be performed in a short time. Since hydration or dehydrogenation can be performed, processing can be performed even at temperatures exceeding the strain point of the glass substrate. do.

[0170] In this embodiment mode, an electric furnace, which is one of the heat treatment devices, is used.

[0171] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat radiation from a heating element such as a resistance heating element. The apparatus may be equipped with a device for heating the object to be treated by irradiation. For example, a GRTA (Gas Rapid Thermal Annealing) equipment, LRTA (Lamp Rap) Rapid Thermal Annealing (RTA) equipment The LRTA device can be used with a halogen lamp. lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high pressure sodium The treated object is irradiated with light (electromagnetic waves) emitted from lamps such as mercury lamps and high-pressure mercury lamps. The GRTA device is a device that uses high-temperature gas to perform heat treatment. The gas may be a rare gas such as argon or nitrogen, which is capable of reacting with the object to be treated by the heat treatment. A non-reactive inert gas is used.

[0172] In the heat treatment, nitrogen or rare gas such as helium, neon, or argon is mixed with water or water. It is preferable that the nitrogen or helium introduced into the heat treatment device is not included. The purity of rare gases such as neon and argon is 6N (99.9999%) or more, preferably 7N (99.9999%) or more. N (99.99999%) or more (i.e., impurity concentration is 1 ppm or less, preferably 0.1 ppm pm or less).

[0173] In addition, oxide semiconductors are insensitive to impurities, and the film contains a considerable amount of metal impurities. There is no problem with using sodalite, which is inexpensive and contains a large amount of alkali metals such as sodium. It has been pointed out that ash glass can also be used (Kamiya, Nomura, Hosono, "Amorphous Oxide Semiconductors" "Current status of physical properties and device development," Solid State Physics, September 2009, Vol. 44, pp. 62 1-633.) However, this is not an appropriate indication. Alkali metals form oxide semiconductors. Alkaline earth metals are not constituent elements of oxide semiconductors and are therefore considered impurities. In particular, Na, an alkali metal, is an impurity when it is not an element that is included in the alloy. When the insulating film in contact with the semiconductor film is an oxide, Na diffuses into the insulating film. + It becomes. In addition, Na separates the bonds between the metal and oxygen that constitute the oxide semiconductor in the oxide semiconductor film. As a result, for example, the threshold voltage may shift in the negative direction. The shift leads to degradation of transistor characteristics such as normally on and reduced mobility. In addition, the transistor characteristics may vary. The deterioration and variation in characteristics occur when the hydrogen concentration in the oxide semiconductor film is sufficiently low. Therefore, when the hydrogen concentration in the oxide semiconductor film is 5×10 19 cm -3 Below Below, especially 5×10 18 cm -3If the concentration of the impurities is less than or equal to the above, the concentration of the impurities can be reduced. Specifically, the measured value of Na concentration by secondary ion mass spectrometry is 5×10 16 / cm 3 Less than or equal to 1×10 16 / cm 3 More preferably, 1×10 15 / cm 3 Similarly, the measured value of Li concentration should be 5×10 15 / cm 3 The following is preferred: 1×10 15 / cm 3 Similarly, the measured value of K concentration should be 5×10 15 / cm 3 Less than or equal to 1×10 15 / cm 3 The following should be used.

[0174] Through the above steps, the hydrogen concentration in the island-shaped oxide semiconductor film 716 can be reduced. In addition, the carrier density caused by hydrogen is low when the material is heated below the glass transition temperature, and the bumps are Therefore, it is possible to form an oxide semiconductor film having a wide band gap. The above-mentioned heat treatment can be carried out by the following steps: The thermal treatment can be performed at any time after the formation of the oxide semiconductor film.

[0175] In the case where the oxide semiconductor film is heated, depending on the material of the oxide semiconductor film and heating conditions, Plate-like crystals may be formed on the surface of the oxide semiconductor film. It is preferable that the single crystal has a c-axis oriented substantially vertically. It is preferable that the crystals are polycrystalline with the c-axis oriented substantially perpendicular to the surface of the oxide semiconductor film. In addition to the c-axis orientation, the ab planes of the crystals of the polycrystalline body coincide with each other. It is preferable that the a-axis or the b-axis of the oxide semiconductor film coincide with each other. If the surface is uneven, the plate crystals will become polycrystalline. Therefore, the substrate surface should be as flat as possible. It is hoped that there is.

[0176] Next, as shown in FIG. 11(A), a part of the gate insulating film 715 is removed to form an opening 717. By forming the opening 718, a part of the gate electrode 707 and a part of the conductive film 708 are Then, the oxide film 714 is exposed. A conductive film 719 which is also in contact with the semiconductor film 716 and is in contact with the conductive film 708 in the opening 718. In addition, a conductive film 720 is formed in contact with the oxide semiconductor film 716. The conductive film 720 functions as a source electrode or a drain electrode.

[0177] Specifically, the conductive film 719 and the conductive film 720 are formed so as to cover the openings 717 and 718. After forming a conductive film on the gate insulating film 715 by a sputtering method or a vacuum deposition method, the conductive film is It can be formed by processing (patterning) into a specific shape.

[0178] The conductive films to be the conductive films 719 and 720 may be formed using a material selected from the group consisting of aluminum, chromium, copper, tantalum, and the like. An element selected from titanium, molybdenum, and tungsten, or a composite material containing the above elements. The metal layer may be a gold layer or an alloy layer made of a combination of the above elements. In addition, the metal layer may be a aluminum layer, a copper layer, etc. Chromium, tantalum, titanium, molybdenum, tungsten, etc. on the underside or on the top of the metal film The metal film may be a laminate of any high melting point metal film. To avoid problems with corrosion, it is recommended to use it in combination with high melting point metal materials. Metal materials include molybdenum, titanium, chromium, tantalum, tungsten, neodymium, Scandium, yttrium, etc. can be used.

[0179] The conductive films to be the conductive films 719 and 720 may have a single-layer structure or a stacked structure of two or more layers. For example, a single layer structure of an aluminum film containing silicon, A two-layer structure in which a titanium film is laminated on top of the titanium film, and an aluminum film is laminated on top of the titanium film. Examples include a three-layer structure in which a titanium film is formed on top of the first layer.

[0180] The conductive films 719 and 720 are formed using a conductive metal oxide. The conductive metal oxide may be indium oxide, tin oxide, zinc oxide, indium oxide, or zinc oxide. Indium tin oxide mixture, indium oxide zinc oxide mixture or the above metal oxide material with silicon It is possible to use a material containing silicon or silicon oxide.

[0181] When a heat treatment is performed after the conductive film is formed, the conductive film is required to have heat resistance to withstand the heat treatment. It is preferable that

[0182] Note that the conductive film is etched so as not to remove the oxide semiconductor film 716 as much as possible. The materials and etching conditions are adjusted appropriately. Depending on the etching conditions, island-shaped The exposed portion of the oxide semiconductor film 716 is partially etched to form a groove (a depression). It may also be achieved.

[0183] In this embodiment mode, a titanium film is used as the conductive film. The conductive film can be selectively wet-etched using a solution containing However, the oxide semiconductor film 716 may also be partly etched. Specifically, the solution is 31% by weight of hydrogen peroxide, 28% by weight of ammonia water, and water. Use an aqueous solution of chlorine (Cl) mixed in a volume ratio of 5:2:2. 2 ), boron chloride (BCl 3 The conductive film may be dry-etched using a gas containing .

[0184] In order to reduce the number of photomasks and steps used in the photolithography process, A resist mask formed by a multi-tone mask that gives multiple levels of intensity to the light is used. The resist mask formed using the multi-tone mask may be a multi-layer mask. The shape can be further modified by etching. Therefore, it can be used in multiple etching processes to process different patterns. A resist that corresponds to at least two different patterns using a single multi-tone mask Therefore, the number of exposure masks can be reduced, and the corresponding Since the photolithography process can also be eliminated, the process can be simplified.

[0185] In addition, the oxide semiconductor film 716 and the conductive film 71 functioning as a source electrode or a drain electrode Between the conductive film 720 and the conductive film 720, an oxide conductive film serving as a source region and a drain region is formed. The material of the oxide conductive film may contain zinc oxide as a component. It is preferable that the oxide does not contain indium oxide. Conductive films include zinc oxide, zinc aluminum oxide, zinc aluminum oxynitride, and zinc oxide gallium. Lithium, etc. can be applied.

[0186] For example, in the case of forming an oxide conductive film, a patterning process for forming the oxide conductive film is performed. The conductive film 719 and the conductive film 720 are patterned together. is also good.

[0187] By providing an oxide conductive film functioning as a source region and a drain region, Since the resistance between the film 716 and the conductive film 719 and between the film 720 and the conductive film 720 can be reduced, In addition, the source and drain regions can be formed by the same material. By providing a functioning oxide conductive film, the withstand voltage of the transistor can be increased.

[0188] Next, N 2 O, N 2 Alternatively, plasma treatment using a gas such as Ar may be performed. The plasma treatment removes water and the like attached to the exposed surface of the oxide semiconductor film. Alternatively, a plasma treatment may be performed using a mixed gas of oxygen and argon.

[0189] FIG. 12B is a top view of the memory cell after the above steps are completed. The cross-sectional view taken along the dashed line A1-A2 in FIG. 12(B) corresponds to FIG. 11(A).

[0190] After the plasma treatment, the conductive film 719 and the conductive film 7 A gate insulating film 721 is formed to cover the oxide semiconductor film 716 and the gate insulating film 721. A gate electrode 72 is disposed over the gate insulating film 721 so as to overlap with the oxide semiconductor film 716. 2 is formed, and a conductive film 723 is formed in a position overlapping with the conductive film 719.

[0191] The gate insulating film 721 is formed using the same material and the same layered structure as the gate insulating film 703. Note that the gate insulating film 721 is formed by removing impurities such as moisture and hydrogen as much as possible. It is preferable that the insulating film does not include a single insulating film, and the insulating film may be a single insulating film or may be a laminate of multiple insulating films. When hydrogen is contained in the gate insulating film 721, the hydrogen is absorbed into the oxide semiconductor Hydrogen penetrates into the oxide semiconductor film 716 or extracts oxygen from the oxide semiconductor film 716. The film 716 may become low-resistance (n-type), and a parasitic channel may be formed. Therefore, in order to make the gate insulating film 721 a film that contains as little hydrogen as possible, the film forming method is set to include hydrogen. It is important not to use a material with high barrier properties for the gate insulating film 721. For example, a silicon nitride film, a silicon oxynitride film, or a silicon nitride film may be used as an insulating film having a high barrier property. An aluminum nitride film, an aluminum nitride oxide film, or the like can be used. When using a layered insulating film, a silicon oxide film or a silicon oxynitride film having a low nitrogen content is used. The insulating film is formed closer to the oxide semiconductor film 716 than the insulating film with high barrier property. Then, the conductive film 719, the conductive film 720, and the conductive film 721 are formed with an insulating film having a low nitrogen content therebetween. An insulating film having a high barrier property is formed so as to overlap with the oxide semiconductor film 716. By using a thick insulating film, the oxide semiconductor film 716, the gate insulating film 721, or Impurities such as moisture or hydrogen enter the interface between the oxide semiconductor film 716 and another insulating film or the vicinity thereof. In addition, the ratio of nitrogen to the oxide semiconductor film 716 can be reduced. By forming insulating films such as low-temperature silicon oxide films and silicon oxynitride films, materials with high barrier properties can be used. This can prevent the insulating film from being in direct contact with the oxide semiconductor film 716.

[0192] In this embodiment, a silicon oxide film having a thickness of 200 nm is formed by sputtering. The gate insulating film 7 has a structure in which a silicon nitride film having a thickness of 100 nm is laminated by the method. The substrate temperature during film formation may be set to room temperature or higher and 300° C. or lower. In this case, the temperature is 100°C.

[0193] Note that heat treatment may be performed after the gate insulating film 721 is formed. , ultra-dry air or rare gas (argon, helium, etc.) atmosphere, preferably The temperature is 200°C to 400°C, for example, 250°C to 350°C. The content is 20 ppm or less, preferably 1 ppm or less, and more preferably 10 ppb or less. In this embodiment, for example, heating is performed at 250° C. for 1 hour in a nitrogen atmosphere. Alternatively, before the conductive films 719 and 720 are formed, moisture or hydrogen may be reduced. Similar to the previous heat treatment performed on the oxide semiconductor film to reduce the After the gate insulating film 721 containing oxygen is provided, heat treatment is performed. By this, the oxide semiconductor film 716 is turned into an oxide semiconductor film by the heat treatment. Even if oxygen vacancies occur in the semiconductor film 716, the oxide semiconductor Oxygen is supplied to the oxide semiconductor film 716. In the oxide semiconductor film 716, oxygen vacancies serving as donors are reduced and the stoichiometric composition ratio is As a result, the oxide semiconductor film 716 can be highly purified to have a conductivity close to i-type. This reduces the variation in the electrical characteristics of the transistors caused by oxygen deficiency, and improves the electrical characteristics The timing of this heat treatment is set to the timing when the gate insulating film 721 There are no particular limitations on the process as long as it is after the formation of the transparent conductive film. This process also serves as a heat treatment to reduce the resistance of the conductive film, so that the oxide can be formed without increasing the number of processes. The semiconductor film 716 can be made closer to i-type.

[0194] In addition, by performing heat treatment on the oxide semiconductor film 716 in an oxygen atmosphere, the oxide semiconductor In this case, oxygen vacancies serving as donors in the oxide semiconductor film 716 may be reduced by adding oxygen. The temperature of the heat treatment is, for example, 100° C. or higher and lower than 350° C., preferably 150° C. or higher and lower than 250° C. The oxygen gas used in the heat treatment in the oxygen atmosphere contains water, hydrogen, etc. It is preferable that the purity of the oxygen gas introduced into the heat treatment device is not more than 6N (9 9.9999%) or more, preferably 7N (99.99999%) or more (i.e., impurities in oxygen It is preferable to keep the concentration of impurities at 1 ppm or less, and preferably at 0.1 ppm or less.

[0195] Alternatively, an oxide semiconductor film 716 may be formed by adding an oxide to the oxide semiconductor film 716 by an ion implantation method, an ion doping method, or the like. The oxygen vacancies acting as donors may be reduced by adding 2.45GH Oxygen plasma generated by microwaves at 1000 nm may be added to the oxide semiconductor film 716 .

[0196] The gate electrode 722 and the conductive film 723 are formed by forming a conductive film over the gate insulating film 721. Then, the conductive film is patterned. The conductive film 723 is made of the same material as the gate electrode 714, or the conductive film 719 and the conductive film 720. Similar structures can be used to form.

[0197] The thickness of the gate electrode 722 and the conductive film 723 is 10 nm to 400 nm, preferably 100 For example, a structure in which a titanium film, an aluminum film, and a titanium film are laminated is used. After forming a conductive film having a structure, a resist mask is formed by photolithography or the like. Then, unnecessary parts are removed by etching to process the conductive film into a desired shape (patterning). The gate electrode 722 and the conductive film 723 may be formed by performing a photolithography process.

[0198] Through the above steps, the transistor 101 is formed.

[0199] Note that the conductive film 719 and the conductive film 723 overlap with each other with the gate insulating film 721 therebetween. It corresponds to the capacitive element 102 .

[0200] FIG. 12C is a top view of the memory cell after the above steps are completed. The cross-sectional view taken along the dashed line A1-A2 in FIG. 11(C) corresponds to FIG. 11(B).

[0201] In addition, the transistor 101 has a single gate structure. Optionally, a plurality of electrically connected gate electrodes 714 may be provided to form a channel. A transistor having a multi-gate structure having a plurality of regions can also be formed.

[0202] Note that the insulating film in contact with the oxide semiconductor film 716 (the gate insulating film 7 15, gate insulating film 721 corresponds to the above.) is made of an insulating material containing a group 13 element and oxygen. Many oxide semiconductor materials contain Group 13 elements. The insulating material containing the element has good compatibility with the oxide semiconductor, and this is used as an insulating material in contact with the oxide semiconductor film. By using the oxide semiconductor film as the insulating film, the state of the interface with the oxide semiconductor film can be kept favorable.

[0203] An insulating material containing a Group 13 element means that the insulating material contains one or more Group 13 elements. Examples of insulating materials containing Group 13 elements include gallium oxide and aluminum oxide. gallium oxide, aluminum gallium oxide, and gallium aluminum oxide. Aluminum gallium is a metal whose aluminum content (atomic percent) is higher than its gallium content (atomic percent). %), and gallium aluminum oxide is a material with a high gallium content (atomic %). This indicates an aluminum content (atomic percent) or higher.

[0204] For example, when an insulating film is formed in contact with an oxide semiconductor film containing gallium, By using a material containing gallium oxide, the interface characteristics between the oxide semiconductor film and the insulating film can be kept good. For example, an oxide semiconductor film and an insulating film containing gallium oxide can be provided in contact with each other. As a result, the pile-up of hydrogen at the interface between the oxide semiconductor film and the insulating film can be reduced. In addition, when an element of the same group as the component element of the oxide semiconductor is used for the insulating film, the same can be said. For example, it is possible to form an insulating film using a material containing aluminum oxide. It is also effective to form a thin film of aluminum oxide, which has the characteristic of being difficult for water to pass through. Therefore, the use of this material is advantageous in terms of preventing water from entering the oxide semiconductor film. It is also preferred in

[0205] The insulating film in contact with the oxide semiconductor film 716 is subjected to heat treatment in an oxygen atmosphere or oxygen doping. It is preferable to make the insulating material have more oxygen than the stoichiometric composition by, for example, a vacuum. Oxygen doping refers to adding oxygen to the bulk. The term is used to clarify that the acid is added not only to the surface of the thin film but also to the inside of the thin film. The elemental doping includes oxygen plasma doping in which oxygen in the form of plasma is added to the bulk. The oxygen doping may be performed by ion implantation or ion doping.

[0206] For example, when gallium oxide is used as an insulating film in contact with the oxide semiconductor film 716, By performing heat treatment under atmospheric conditions and oxygen doping, the composition of gallium oxide is changed to Ga 2 O X (X=3+α, 0<α<1).

[0207] In addition, when aluminum oxide is used as the insulating film in contact with the oxide semiconductor film 716, oxygen By performing heat treatment under atmospheric conditions and oxygen doping, the composition of aluminum oxide is changed to Al 2 O X (X=3+α, 0<α<1).

[0208] In addition, an insulating film in contact with the oxide semiconductor film 716 is made of gallium aluminum oxide (AlO 2 ). When using tritium gallium, heat treatment in an oxygen atmosphere or oxygen doping should be performed. The composition of gallium aluminum oxide (aluminum gallium oxide) is Ga X Al 2 -X O 3+α (0 <X<2、0<α<1)とすることができる。

[0209] By performing oxygen doping treatment, an insulating film having a region in which oxygen is more abundant than the stoichiometric composition ratio is formed When the insulating film having such a region is in contact with the oxide semiconductor film, As a result, excess oxygen in the insulating film is supplied to the oxide semiconductor film, and the oxide semiconductor film or the oxygen The oxide semiconductor film is made i-type or i-type by reducing oxygen defects at the interface between the oxide semiconductor film and the insulating film. It is possible to make it as close as possible to the mold.

[0210] Note that the insulating film having a region containing more oxygen than the stoichiometric composition is the oxide semiconductor film 716. Of the insulating films in contact with each other, either the insulating film located in the upper layer or the insulating film located in the lower layer It may be used in only one of the insulating films, but it is preferable to use it in both insulating films. The insulating film having a region with a large amount of oxygen is formed on the upper and lower insulating films in contact with the oxide semiconductor film 716. The above effect can be obtained by using the oxide semiconductor film 716 between the insulating film 716 and the insulating film 718. It can be further increased.

[0211] In addition, the insulating films used as the upper and lower layers of the oxide semiconductor film 716 have the same composition. The insulating film may have one element, or may have a different element. The composition of both the upper and lower layers is Ga. 2 O X As gallium oxide (X=3+α, 0<α<1) Alternatively, one of the upper and lower layers may be made of Ga. 2 O X (X=3+α, 0<α<1) Oxidized gallium The other has a composition of Al. 2 O X (X=3+α, 0<α<1) aluminum oxide That's fine.

[0212] In addition, the insulating film in contact with the oxide semiconductor film 716 may be a stack of insulating films having a region where oxygen is more abundant than the stoichiometric composition ratio. For example, gallium oxide with a composition of Ga 2 O X (X = 3 + α, 0 < α < 1) may be formed on the upper layer of the oxide semiconductor film 716, and gallium aluminum oxide (aluminum gallium oxide) with a composition of Ga X Al 2 -X O 3+α (0 < X < 2, 0 < α < 1) may be formed thereon. Note that the lower layer of the oxide semiconductor film 716 may also be a stack of insulating films having a region where oxygen is more abundant than the stoichiometric composition ratio, or both the upper and lower layers of the oxide semiconductor film 716 may be a stack of insulating films having a region where oxygen is more abundant than the stoichiometric composition ratio. Next, as shown in FIG. 11(C), an insulating film 724 is formed so as to cover the gate insulating film 721, the conductive film 723, and the gate electrode 72 2. The insulating film 724 can be formed using a method such as PVD or CVD. Further, it can be formed using a material containing an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, gallium oxide, or aluminum oxide. Note that it is desirable to use a material having a low dielectric constant or a structure having a low dielectric constant (such as a porous structure) for the insulating film 724. By reducing the dielectric constant of the insulating film 724, the parasitic capacitance generated between wirings and electrodes can be reduced, and the operation speed can be increased. In this embodiment, the insulating film 724 has a single-layer structure, but one aspect of the disclosed invention is not limited thereto, and a stacked structure of two or more layers may be used. Next, as shown in FIG. 11(C), an insulating film 724 is formed so as to cover the gate insulating film 721, the conductive film 723, and the gate electrode 72 2. The insulating film 724 can be formed using a method such as PVD or CVD. Further, it can be formed using a material containing an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, gallium oxide, or aluminum oxide. Note that it is desirable to use a material having a low dielectric constant or a structure having a low dielectric constant (such as a porous structure) for the insulating film 724. By reducing the dielectric constant of the insulating film 724, the parasitic capacitance generated between wirings and electrodes can be reduced, and the operation speed can be increased. In this embodiment, the insulating film 724 has a single-layer structure, but one aspect of the disclosed invention is not limited thereto, and a stacked structure of two or more layers may be used.

[0213] Next, as shown in FIG. 11(C), an insulating film 724 is formed so as to cover the gate insulating film 721, the conductive film 723, and the gate electrode 72 2. The insulating film 724 can be formed using a method such as PVD or CVD. Further, it can be formed using a material containing an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, gallium oxide, or aluminum oxide. Note that it is desirable to use a material having a low dielectric constant or a structure having a low dielectric constant (such as a porous structure) for the insulating film 724. By reducing the dielectric constant of the insulating film 724, the parasitic capacitance generated between wirings and electrodes can be reduced, and the operation speed can be increased. In this embodiment, the insulating film 724 has a single-layer structure, but one aspect of the disclosed invention is not limited thereto, and a stacked structure of two or more layers may be used. Next, as shown in FIG. 11(C), an insulating film 724 is formed so as to cover the gate insulating film 721, the conductive film 723, and the gate electrode 72 2. The insulating film 724 can be formed using a method such as PVD or CVD. Further, it can be formed using a material containing an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, gallium oxide, or aluminum oxide. Note that it is desirable to use a material having a low dielectric constant or a structure having a low dielectric constant (such as a porous structure) for the insulating film 724. By reducing the dielectric constant of the insulating film 724, the parasitic capacitance generated between wirings and electrodes can be reduced, and the operation speed can be increased. In this embodiment, the insulating film 724 has a single-layer structure, but one aspect of the disclosed invention is not limited thereto, and a stacked structure of two or more layers may be used. Next, as shown in FIG. 11(C), an insulating film 724 is formed so as to cover the gate insulating film 721, the conductive film 723, and the gate electrode 72 2. The insulating film 724 can be formed using a method such as PVD or CVD. Further, it can be formed using a material containing an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, gallium oxide, or aluminum oxide. Note that it is desirable to use a material having a low dielectric constant or a structure having a low dielectric constant (such as a porous structure) for the insulating film 724. By reducing the dielectric constant of the insulating film 724, the parasitic capacitance generated between wirings and electrodes can be reduced, and the operation speed can be increased. In this embodiment, the insulating film 724 has a single-layer structure, but one aspect of the disclosed invention is not limited thereto, and a stacked structure of two or more layers may be used. Next, as shown in FIG. 11(C), an insulating film 724 is formed so as to cover the gate insulating film 721, the conductive film 723, and the gate electrode 72 2. The insulating film 724 can be formed using a method such as PVD or CVD. Further, it can be formed using a material containing an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, gallium oxide, or aluminum oxide. Note that it is desirable to use a material having a low dielectric constant or a structure having a low dielectric constant (such as a porous structure) for the insulating film 724. By reducing the dielectric constant of the insulating film 724, the parasitic capacitance generated between wirings and electrodes can be reduced, and the operation speed can be increased. In this embodiment, the insulating film 724 has a single-layer structure, but one aspect of the disclosed invention is not limited thereto, and a stacked structure of two or more layers may be used. Next, as shown in FIG. 11(C), an insulating film 724 is formed so as to cover the gate insulating film 721, the conductive film 723, and the gate electrode 72

[0214] Next, an opening 725 is formed in the gate insulating film 721 and the insulating film 724, and a part of the conductive film 720 is After that, a conductive film 720 is formed on the insulating film 724 in the opening 725. Then, a wiring 726 is formed.

[0215] The wiring 726 is formed by forming a conductive film using a PVD method or a CVD method, and then patterning the conductive film. The conductive film is formed by etching. Elements selected from the group consisting of aluminum, copper, tantalum, titanium, molybdenum, and tungsten, and the above-mentioned elements Manganese, magnesium, zirconium, and other alloys containing these elements can be used. Beryllium, neodymium, or scandium, or a combination of these materials It may be used.

[0216] More specifically, for example, a titanium film is thinly formed by a PVD method in a region including the opening of the insulating film 724. After forming a thin titanium film (about 5 nm) by the PVD method, A method of forming an aluminum film so as to fill the gap can be applied. The titanium film formed by the method reduces the oxide film (such as the native oxide film) on the surface on which it is formed, and It has a function of reducing the contact resistance with the electrode (conductive film 720 in this example). In addition, it is possible to prevent the formation of burrs on the titanium film. After the aluminum film is formed, a copper film may be formed by plating.

[0217] The opening 725 formed in the insulating film 724 can be formed in a region overlapping with the conductive film 708. By forming the opening 725 in such a region, the contact region can be prevented from being formed. An increase in the element area can be suppressed.

[0218] Here, the conductive film 708 is not used, and the connection between the impurity region 704 and the conductive film 720 and the conductive film A case will be described in which the connection between the impurity region 720 and the wiring 726 overlaps with each other. An opening (called a lower opening) is formed in the insulating film 712 and the insulating film 713 formed on the region 704. After forming a conductive film 720 so as to cover the lower opening, a gate insulating film 721 and In the insulating film 724, an opening (called an upper opening) is formed in a region overlapping with the lower opening. The upper opening is formed in a region overlapping the lower opening, forming a wiring 726. When forming the conductive film 720, the conductive film 720 formed in the lower opening is broken by etching. To avoid this, make sure that the lower opening and the upper opening do not overlap. However, forming the element at a large area increases the element area.

[0219] As shown in this embodiment, the conductive film 708 is used to prevent the conductive film 720 from being broken. This allows the upper opening to be formed without forming the lower opening and the upper opening. Since the openings can be overlapped, an increase in the element area due to the openings can be suppressed. In other words, the degree of integration of the semiconductor device can be increased.

[0220] Next, an insulating film 727 is formed so as to cover the wiring 726. It is possible to create a memory device.

[0221] In the above manufacturing method, the conductive films 719 and 720 functioning as a source electrode and a drain electrode are The conductive film 720 is formed after the oxide semiconductor film 716. As shown in the figure, the transistor 101 obtained by the above manufacturing method has a conductive film 719 and a conductive The oxide semiconductor film 716 is formed on the oxide semiconductor film 720. In FIG. 1, a conductive film functioning as a source electrode and a drain electrode is provided under an oxide semiconductor film 716. That is, the insulating film 714 may be provided between the oxide semiconductor film 716 and the gate insulating film 715.

[0222] In FIG. 13, a conductive film 719 and a conductive film 720 functioning as a source electrode and a drain electrode are , the memory cell The transistor 101 shown in FIG. Then, the conductive films 719 and 720 are formed, and then the oxide semiconductor film 716 is formed. This can be obtained by doing so.

[0223] This embodiment mode can be implemented in combination with the above embodiment modes.

[0224] (Embodiment 3) An example of a specific configuration of a driver circuit in a memory device according to one embodiment of the present invention will be described.

[0225] FIG. 14 is a block diagram illustrating a specific configuration example of a memory device according to one embodiment of the present invention. In the block diagram shown in Figure 14, the circuits in the memory device are classified by function and are mutually Although they are shown as independent blocks, the actual circuit can be completely separated by function. It is difficult, and one circuit may be involved in multiple functions.

[0226] A memory device 800 shown in FIG. The drive circuit 802 is a read circuit that generates a signal including data read from the cell array 801. a first word line driving circuit 804 for controlling the potential of the first word line; A second word line driver circuit 820 for controlling the potential of the word line and a cell array 801 for selecting and a bit line driver circuit 805 for controlling writing of data in a selected memory cell. Further, the driving circuit 802 includes a read circuit 803, a first word line driving circuit 804, A control circuit 806 for controlling the operation of the second word line driving circuit 820 and the bit line driving circuit 805 It has.

[0227] In the memory device 800 shown in FIG. 14, the first word line driving circuit 804 is connected to the decoder 80. 7, a level shifter 808, and a buffer 809. The circuit includes a decoder 810 , a level shifter 811 , and a selector 812 .

[0228] The memory device 800 according to one embodiment of the present invention includes at least a cell array 801 as its configuration. Furthermore, the memory device 800 according to one embodiment of the present invention may include a cell array 801. A memory module in which a part or all of the driver circuit 802 is connected to the The memory module is provided with connection terminals that can be mounted on a printed wiring board, etc. The semiconductor device may be in a so-called packaged state, that is, protected by a resin or the like.

[0229] Also, a cell array 801, a read circuit 803, a first word line driving circuit 804, a second word The bit line driver circuit 820, the bit line driver circuit 805, and the control circuit 806 are all formed on a single substrate. Alternatively, one or all of the layers may be formed using different substrates. It's fine if it is.

[0230] If different substrates are used, FPC (Flexible Printed Circuit) In this case, the electrical connection of the driving circuit 802 can be ensured through a A part of it may be connected to the FPC using a COF (Chip On Film) method. Alternatively, the COG (Chip On Glass) method can be used to ensure electrical connection. This can be done.

[0231] A signal A, which includes the address (Ax, Ay) of the cell array 801 as information, is input to the memory device 800. When D is input, the control circuit 806 drives the bit line Ax, which is information on the column direction of the address. 805, and sends address row direction information Ay to the first word line driving circuit 804. The control circuit 806 also transmits a signal DAT containing the data input to the storage device 800. A is sent to the bit line driver circuit 805 .

[0232] The selection of data write and read operations in the cell array 801 is performed by the control circuit 80 The RE (Read enable) and WE (Write enable) signals are supplied to Furthermore, when there are multiple cell arrays 801, the control circuit A signal CE (Chip Enable) for selecting the cell array 801 is input to 806. In this case, the operation selected by the signal RE and the signal WE may be input to the The process is executed in the cell array 801 selected by

[0233] In the cell array 801, when a write operation is selected by the signal WE, the control circuit 806 In response to the instruction from the first word line driver circuit 804, the decoder 807 in the first word line driver circuit 804 A signal is generated to select the memory cell corresponding to the address Ay. The signal is level After the amplitude is adjusted by shifter 808, the waveform is processed in buffer 809, On the other hand, in the bit line driver circuit 805, the control circuit 806 In accordance with the instruction from the address Ax, the memory cell selected by the decoder 810 is A signal for selecting a memory cell corresponding to the level shifter 8 is generated. After the amplitude is adjusted by the amplifier 11, the signal is input to the selector 812. The selector 812 The signal DATA is sampled according to the input signal and corresponds to the address (Ax, Ay). The sampled signal is input to the corresponding memory cell.

[0234] In addition, in the cell array 801, when a read operation is selected by a signal RE, the control circuit In accordance with the instruction from 806, a decoder 807 included in the first word line driver circuit 804 A signal for selecting a memory cell corresponding to the address Ay is generated. After the amplitude is adjusted by the level shifter 808, the waveform is processed in the buffer 809. The read circuit 803 is connected to a control circuit 806. In accordance with the instruction from the decoder 807, the memory cell with the address Ax Then, select the memory cell corresponding to the address (Ax, Ay). The data stored in the buffer is read and a signal containing the data is generated.

[0235] The second word line driving circuit 820 supplies the potential of the second word line to the cell array 801 .

[0236] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes.

[0237] (Embodiment 4) In this embodiment, an example of a specific configuration of the readout circuit will be described.

[0238] The potential read from the cell array is determined according to the data written in the memory cell. Therefore, ideally, multiple memory cells would store the same digital value. If the voltages are stored in the memory cells, the voltages read from the memory cells are all at the same level. However, in reality, a transistor functioning as a memory element, a capacitor element, or a read The characteristics of the transistor that functions as a switching element when reading out In this case, the data to be read may not all be the same digital data. Even if the value is the same, the actual potential read out varies, so the distribution has a certain range. Therefore, even if there is some variation in the potential read from the cell array, the The signal contains the necessary data and has its amplitude and waveform processed to meet the desired specifications. The read-out circuitry is preferably provided in the drive circuitry.

[0239] FIG. 15 is a circuit diagram showing an example of a readout circuit. The readout circuit shown in FIG. A switch for controlling the input of the potential Vdata read from the A transistor 260 functions as a switching element, and a transistor 261 functions as a resistor. 15 includes an operational amplifier 262.

[0240] Specifically, the transistor 261 has a gate electrode and a drain electrode (or drain region) is connected, and a high level is applied to the gate electrode and the drain electrode. The transistor 261 has a source electrode connected to the op amp. The transistor 261 is connected to the non-inverting input terminal (+) of the amplifier 262. , a node to which the power supply potential Vdd is applied, and the non-inverting input terminal (+) of the operational amplifier 262 In FIG. 15, the gate electrode and the drain electrode are connected to each other, and function as a resistor. In the above embodiment, a transistor having a connected pole is used as a resistor, but the present invention is not limited to this. Any element that functions as such can be substituted.

[0241] The transistor 260, which functions as a switching element, has a gate electrode provided with A potential Vda to the source electrode of the transistor 260 is applied according to the potential of the signal Sig. Control the supply of ta.

[0242] For example, when the transistor 260 is turned on, the potential Vdata and the power supply potential Vdd are connected to the transistor 260. The potential obtained by dividing the resistance of the transistor 260 and the transistor 261 is The voltage is applied to the non-inverting input terminal (+) of the amplifier 262. The level of the power supply potential Vdd is Since the potential level obtained by resistive division is fixed, the potential Vdata level is The digital value of the read data is reflected.

[0243] On the other hand, the inverting input terminal (-) of the operational amplifier 262 is supplied with a reference potential Vref. And the potential applied to the non-inverting input terminal (+) is higher than the reference potential Vref. Depending on whether the output terminal potential Vout is low or high, the level of the output terminal potential Vout can be made different. It is possible to indirectly obtain a signal containing data.

[0244] Note that even if the same data value is stored in memory cells, there may be variations in the characteristics between the memory cells. Due to the variation, the level of the read potential Vdata also varies, and the distribution becomes wider. Therefore, the level of the reference potential Vref is important for reading the data value accurately. In order to achieve this, the variation in the node potential Vdata is taken into consideration.

[0245] Also, since FIG. 15 shows an example of a read circuit that handles binary digital values, The operational amplifiers used to read the data are connected to the nodes to which the potential Vdata is applied. However, the number of operational amplifiers is not limited to this. When dealing with data, the number of operational amplifiers for the node to which the potential Vdata is applied is n- Let's say it's 1.

[0246] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes.

[0247] (Embodiment 5) In this embodiment mode, an example of the configuration of an RF tag, which is one of the semiconductor devices of the present invention, will be described. Reveal.

[0248] FIG. 16 is a block diagram showing an embodiment of the RF tag of the present invention. The antenna circuit 551 and the integrated circuit 552 are connected to the antenna 551 and the integrated circuit 552. power supply circuit 553, demodulation circuit 554, modulation circuit 555, regulator 556, and arithmetic circuit 557 , a memory device 558, and a booster circuit 559.

[0249] Next, an example of the operation of the RF tag 550 will be described. The radio waves are converted into AC voltage in the antenna circuit 551. The AC voltage from the antenna circuit 551 is rectified to generate a power supply voltage. The power supply voltage generated by the above is applied to the arithmetic circuit 557 and the regulator 556. The regulator 556 stabilizes or adjusts the level of the power supply voltage from the power supply circuit 553. Then, a demodulation circuit 554, a modulation circuit 555, an arithmetic circuit 557, a memory device The output of the output terminal 554 is supplied to various circuits such as a voltage regulator 558 or a booster circuit 559.

[0250] The demodulation circuit 554 demodulates the AC signal received by the antenna circuit 551 and outputs it to the downstream arithmetic circuit The arithmetic circuit 557 performs arithmetic processing according to the signal input from the demodulation circuit 554. When performing the above-mentioned calculation processing, the storage device 558 stores the primary cache. The arithmetic circuit 557 can be used as a flash memory or a secondary cache memory. The signal input from the demodulation circuit 554 is analyzed, and the command sent from the interrogator is processed according to the command. Thus, the output of information in the memory device 558 or the execution of the contents of the instructions in the memory device 558 The signal output from the arithmetic circuit 557 is encoded and sent to the modulation circuit 555. The modulation circuit 555 modulates the radio wave received by the antenna circuit 551 according to the signal. The radio waves modulated in the antenna circuit 551 are received by the interrogator.

[0251] In this way, the communication between the RF tag 550 and the interrogator uses radio waves as a carrier. This is done by modulating the carrier. The carriers are 125kHz, 13.56MHz, and 950MHz. The modulation method also varies depending on the standard, and can be amplitude modulation, frequency modulation, phase modulation, etc. There are various modulation methods, such as 100-MHz modulation, but any modulation method that complies with the standard can be used. .

[0252] The signal transmission method is electromagnetic coupling method, electromagnetic induction method, microwave method, etc. depending on the carrier wavelength. They can be classified into various types, such as:

[0253] The boost circuit 559 boosts the voltage output from the regulator 556 and outputs it to the storage device 558. We are supplying it.

[0254] When the RF tag 550 is a passive type, a direct current is supplied from an external power source to the RF tag 550. Therefore, the second word line driving circuit 150 shown in FIG. When the RF tag 550 is provided with the potential VSS, the potential VSS is supplied to the terminal A from the outside. Therefore, in one embodiment of the present invention, when the RF tag 550 is a passive type, the charge A circuit for generating a negative potential, such as a pump circuit, is provided in the power supply circuit 553. A potential VSS is supplied from the power supply circuit 553 to a terminal A of the second word line driving circuit 150 shown in FIG. This can improve the retention characteristics of the storage device.

[0255] In one embodiment of the present invention, the memory device 558 has the structure described in the above embodiment. It is possible to retain data for a long period of time and increase the number of times data can be rewritten. Therefore, the RF tag 550 according to one embodiment of the present invention can store the following information using the storage device 558: This can increase the reliability of the data.

[0256] In one embodiment of the present invention, the memory device 558 has the structure described in any of the above embodiments. Therefore, the power consumption can be reduced. Since the power consumed inside the RF tag 550 can be kept small, The communication distance between the interrogator and the RF tag 550 can be increased accordingly.

[0257] In this embodiment, the configuration of an RF tag 550 having an antenna circuit 551 will be described. However, the RF tag according to one embodiment of the present invention does not necessarily include an antenna circuit as a component. It is not necessary to provide an oscillator circuit or a secondary battery in the RF tag shown in FIG.

[0258] This embodiment mode can be implemented in appropriate combination with the above embodiment modes or embodiment modes. It is.

[0259] (Embodiment 6) In this embodiment, a semiconductor device using a memory device according to one embodiment of the present invention, An example of a strip-type storage medium will be described.

[0260] FIG. 17A shows an example of the structure of a storage medium according to one embodiment of the present invention. The storage medium shown in A) is a storage device 751 according to one embodiment of the present invention, a drive device, and a storage medium. A connector 752 for electrical connection and a connector 753 for various signals input and output via the connector 752 , and an interface 753 that processes signals according to the specifications, and an interface 754 that processes signals according to the operating state of the storage medium, etc. Therefore, the light emitting diode 754 is turned on, and the memory device 751, the interface 753, the A controller that controls the operation of various circuits and semiconductor elements in the storage medium, such as a photodiode 754. A controller 755 is mounted on a printed wiring board 756. A quartz crystal used to generate a clock signal to control the operation of the 755, memory A regulator for controlling the level of the power supply potential in the medium may be provided. stomach.

[0261] The printed wiring board 756 shown in FIG. 17(A) is connected to the connector 7 as shown in FIG. 52 and the light emitting diode 754 are covered with a cover material 757 made of resin or the like so that they are partially exposed. It is also possible to provide protection by doing so.

[0262] The memory device 751 according to one embodiment of the present invention is capable of suppressing power consumption during operation. This allows for lower power consumption of the storage medium using the storage device 751, and therefore reduces the power consumption of the storage medium. It is possible to reduce the power consumption of a driving device connected to the driving device. The storage device 751 is capable of storing data for a long period of time and is also capable of writing data. Since the number of replacements can be increased, the reliability of the storage medium can be improved.

[0263] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes. EXAMPLES

[0264] By using the semiconductor device according to one embodiment of the present invention, highly reliable electronic devices and low power consumption can be achieved. It is possible to provide electronic devices that can operate at high speed and that can be powered continuously. In the case of portable electronic devices in which it is difficult to install a semiconductor device having low power consumption according to one embodiment of the present invention, By adding the device to the components, the continuous use time can be extended. Obtained.

[0265] The semiconductor device according to one embodiment of the present invention is applicable to a display device, a notebook personal computer, a recording medium, Image playback device equipped with a medium (typically DVD: Digital Versatile (Devices with a display that can play back recording media such as discs and display the images) In addition, a semiconductor device according to one embodiment of the present invention can be used in a power As child devices, mobile phones, portable game consoles, personal digital assistants, electronic books, video cameras, Digital still cameras and other cameras, goggle-type displays (head-mounted displays) (car audio, digital audio player), navigation systems, audio playback devices Layers, etc.), copiers, facsimiles, printers, multifunction printers, ATM machines Examples of such electronic devices include ATMs and vending machines. show.

[0266] FIG. 18A shows a portable game machine. The portable game machine includes a housing 7031, a housing 7032, a display portion 7033, A display unit 7034, a microphone 7035, a speaker 7036, an operation key 7037, a star The semiconductor device according to one embodiment of the present invention is a driving circuit for a portable game machine. The present invention can be used in an integrated circuit for controlling a portable game machine. By using a semiconductor device according to one embodiment of the present invention for an integrated circuit of a portable game device, a highly reliable portable game device can be realized. It is possible to provide a portable game machine with high functionality. The portable game machine has two display units 7033 and 7034. The number of display units that the game machine has is not limited to this.

[0267] FIG. 18B shows a mobile phone. The mobile phone includes a housing 7041, a display unit 7042, an audio input unit 7043, The device has a voice output unit 7044, an operation key 7045, a light receiving unit 7046, etc. By converting the light received in the sensor into an electrical signal, an external image can be captured. The semiconductor device according to one embodiment of the present invention can be used in an integrated circuit for controlling the operation of a mobile phone. The semiconductor device according to one aspect of the present invention can be used in an integrated circuit for controlling the operation of a mobile phone. By using this device, it is possible to provide highly reliable mobile phones and mobile phones with advanced functions. Cut.

[0268] FIG. 18C shows a portable information terminal, which includes a housing 7051, a display unit 7052, and operation keys 7053. The portable information terminal shown in FIG. 18C has a modem built in a housing 7051. The semiconductor device according to one embodiment of the present invention may be a semiconductor device for controlling the driving of a portable information terminal. The present invention can be used in an integrated circuit for controlling the operation of a portable information terminal. By using the semiconductor device according to one embodiment, a highly reliable portable information terminal, a highly functional portable information terminal, It is possible to provide a portable information terminal.

[0269] This embodiment can be implemented in appropriate combination with any of the above embodiment modes. [Explanation of symbols]

[0270] 100 memory cells 101 Transistor 102 Capacitive element 103 Transistor 104 Transistor 110 Substrate 111 Gate electrode 112 Insulating film 113 Oxide Semiconductor Film 114 Source Electrode 115 Drain electrode 116 Insulating film 117 Gate electrode 118 Insulating film 120 lines 121 line 150 Second word line driving circuit 151 Transistor 152 Capacitive element 200 Cell Array 260 Transistors 261 Transistor 262 Operational Amplifier 300 Cell Array 550 RF Tag 551 Antenna Circuit 552 Integrated Circuits 553 Power supply circuit 554 Demodulation Circuit 555 Modulation Circuit 556 Regulator 557 Arithmetic circuit 558 Storage device 559 Boost Circuit 700 Substrates 701 Insulating film 702 Semiconductor film 703 Gate insulating film 704 Impurity region 705 Mask 706 Opening 707 Gate electrode 708 Conductive Film 709 Impurity region 710 Channel formation region 711 Impurity region 712 Insulating film 713 Insulating film 714 Gate electrode 715 Gate insulating film 716 Oxide Semiconductor Film 717 Opening 718 Opening 719 Conductive Film 720 Conductive Film 721 Gate insulating film 722 Gate electrode 723 Conductive Film 724 Insulating film 725 Opening 726 Wiring 727 Insulating Film 751 Storage device 752 Connector 753 Interface 754 Light Emitting Diode 755 Controller 756 Printed Wiring Board 757 Cover material 800 storage device 801 Cell Array 802 Drive circuit 803 Circuit 804 First word line driving circuit 805 Bit Line Driver Circuit 806 Control circuit 807 Decoder 808 Level Shifter 809 Buffer 810 Decoder 811 Level Shifter 812 Selector 820 Second word line driving circuit 7031 Case 7032 Case 7033 Display section 7034 Display section 7035 Microphone 7036 Speaker 7037 Operation Key 7038 Stylus 7041 Case 7042 Display section 7043 Audio input section 7044 Audio output section 7045 Operation key 7046 Light receiving section 7051 Case 7052 Display section 7053 Operation key

Claims

1. A plurality of circuits are included. the circuit includes a first transistor, a second transistor, and a capacitance element; a gate electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor and to the capacitance element, a silicon layer having a channel formation region of the first transistor; a first conductive layer disposed above the silicon layer and having a region that functions as a gate electrode of the first transistor; a second conductive layer disposed in the same layer as the first conductive layer; a first insulating layer disposed above the silicon layer and having a region in contact with a side surface of the first conductive layer and a region in contact with a side surface of the second conductive layer; a second insulating layer having a region disposed above the first insulating layer; a third conductive layer disposed above the second insulating layer and having a region that functions as one of a source electrode and a drain electrode of the second transistor; a fourth conductive layer disposed in the same layer as the third conductive layer and having a region functioning as the other of the source electrode and the drain electrode of the second transistor; an oxide semiconductor layer including a region in contact with a top surface of the third conductive layer, a region in contact with a side surface of the third conductive layer, a region in contact with a side surface of the fourth conductive layer, and a region in contact with a top surface of the fourth conductive layer, and including a channel formation region of the second transistor; a fifth conductive layer disposed above the oxide semiconductor layer and having a region functioning as a gate electrode of the second transistor; a sixth conductive layer disposed in the same layer as the fifth conductive layer and having a region that functions as an electrode of the capacitance element; a third insulating layer having a region disposed above the fifth conductive layer; a seventh conductive layer having a region disposed above the third insulating layer; the first conductive layer is electrically connected to the third conductive layer; the second conductive layer is disposed so as to overlap the seventh conductive layer via the fourth conductive layer; the seventh conductive layer has a function of electrically connecting a source or a drain of the first transistor to a source or a drain of the first transistor in an adjacent circuit.

2. A plurality of circuits are included. the circuit includes a first transistor, a second transistor, and a capacitance element; a gate electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor and to the capacitance element, a silicon layer having a channel formation region of the first transistor; a first conductive layer disposed above the silicon layer and having a region that functions as a gate electrode of the first transistor; a second conductive layer disposed in the same layer as the first conductive layer; a first insulating layer disposed above the silicon layer and having a region in contact with a side surface of the first conductive layer and a region in contact with a side surface of the second conductive layer; a second insulating layer having a region disposed above the first insulating layer; a third conductive layer disposed above the second insulating layer and having a region that functions as one of a source electrode and a drain electrode of the second transistor; a fourth conductive layer disposed in the same layer as the third conductive layer and having a region functioning as the other of the source electrode and the drain electrode of the second transistor; an oxide semiconductor layer including a region in contact with a top surface of the third conductive layer, a region in contact with a side surface of the third conductive layer, a region in contact with a side surface of the fourth conductive layer, and a region in contact with a top surface of the fourth conductive layer, and including a channel formation region of the second transistor; a fifth conductive layer disposed above the oxide semiconductor layer and having a region functioning as a gate electrode of the second transistor; a sixth conductive layer disposed in the same layer as the fifth conductive layer and having a region that functions as an electrode of the capacitance element; a third insulating layer having a region disposed above the fifth conductive layer; a seventh conductive layer having a region disposed above the third insulating layer; the first conductive layer is electrically connected to the third conductive layer; the second conductive layer is disposed so as to overlap the seventh conductive layer via the fourth conductive layer; the seventh conductive layer has a function of electrically connecting a source or a drain of the first transistor to a source or a drain of the first transistor of an adjacent circuit; a direction connecting a source region and a drain region of the first transistor in a plan view is a first direction; In a plan view, a width of the second conductive layer in the first direction is larger than a width of the first conductive layer in the first direction; A semiconductor device, wherein, in a plan view, the width of the fifth conductive layer in the first direction is larger than the width of the sixth conductive layer in the first direction.

3. In claim 1 or 2, The semiconductor device, wherein the oxide semiconductor layer contains In.

4. In claim 1 or 2, The oxide semiconductor layer contains In, Ga, and Zn.

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