Image sensor

Abstract

To provide an image sensor of which a size is miniaturized.SOLUTION: An image sensor includes: a first layer; and a second layer that is bonded to the first layer. The first layer includes: a first substrate including a first front surface and a first back surface; a floating diffusion region that is formed in the first substrate; a first pad; and a first conductive line that is provided between the floating diffusion region and the first pad. The second layer includes: a second substrate that includes a second front surface and a second back surface; pixel transistors that are formed on the second substrate; a second pad; and a second conductive line that is provided between any one of the pixel transistors and the second pad. The second conductive line penetrates the second substrate and is electrically coupled to a lower part of the pixel transistor.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to an image sensor. [Background technology]

[0002] Image sensors are devices that convert optical image signals into electrical signals and include CCD (charge coupled device) image sensors and CMOS (complementary metal oxide semiconductor) image sensors. Image sensors include a number of pixels. Each pixel includes a light receiving area that receives incident light and converts it into an electrical signal, and a pixel circuit that outputs a pixel signal using the charges generated in the light receiving area.

[0003] Recently, as the integration density of image sensors increases, the size of each pixel is becoming smaller, but this can cause image transmission delays due to the layout and shape of components within a pixel, resulting in a degradation in image sensor quality. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] US Patent No. 11,600,651 B2 Summary of the Invention [Problem to be solved by the invention]

[0005] The problem to be solved is to provide an image sensor whose size is minimized.

[0006] However, the problem to be solved is not limited to this. [Means for solving the problem]

[0007] In one aspect, an image sensor may be provided that includes a first layer and a second layer bonded to the first layer, the first layer including a first substrate having a first front surface and a first rear surface, a floating diffusion region formed in the first substrate, a first pad, and a first conductive line provided between the floating diffusion region and the first pad, and the second layer including a second substrate having a second front surface and a second rear surface, pixel transistors formed on the second substrate, a second pad, and a second conductive line provided between any one of the pixel transistors and the second pad, the second conductive line penetrating the second substrate and electrically connected to a lower portion of the pixel transistor.

[0008] In one aspect, an image sensor may be provided that includes a pixel array in which a plurality of pixels are arranged, the plurality of pixels including a first pixel and a second pixel disposed adjacent to each other, each of the first pixel and the second pixel including a first layer and a second layer bonded to the first layer, the first layer including a first substrate including a first front surface and a first rear surface, a floating diffusion region formed in the first substrate, a first pad, and a first conductive line provided between the floating diffusion region and the first pad, the second layer including a second substrate including a second front surface and a second rear surface, pixel transistors formed on the second substrate, a second pad, and a second conductive line provided between any one of the pixel transistors and the second pad, the second conductive line penetrating the second substrate and electrically connected to a lower portion of the pixel transistor.

[0009] In one aspect, the image sensor may include a pixel array region and a pad region, each of the pixel array region and the pad region including a first layer and a second layer bonded to the first layer. In the pixel array region, the first layer may include a first substrate including a first front surface and a first rear surface, a floating diffusion region formed in the first substrate, a first pad, and a first conductive line provided between the floating diffusion region and the first pad. The second layer may include a second substrate including a second front surface and a second rear surface, pixel transistors formed on the second substrate, a second pad, and a second conductive line provided between any one of the pixel transistors and the second pad, the second conductive line penetrating the second substrate and being electrically connected to a lower portion of the pixel transistor. In the pad region, the first layer may include a main via penetrating the first substrate and a signal pad provided on the main via. Effect of the Invention

[0010] The present invention can provide an image sensor whose size is minimized.

[0011] However, the effects of the invention are not limited to this. [Brief description of the drawings]

[0012] [Figure 1] FIG. 1 is a block diagram of an image sensor according to an embodiment of the present invention. [Diagram 2] 2 is a circuit diagram of a pixel in an image sensor according to an embodiment of the present invention. [Diagram 3] 1 is a diagram conceptually illustrating a layout of an image sensor according to an embodiment of the present invention. [Figure 4] FIG. 4 is a plan view showing the image sensor of FIG. 3. [Diagram 5] 1 is a cross-sectional view of an image sensor according to an example embodiment. [Figure 6] FIG. 6 is an enlarged view of a portion AA in FIG. 5. [Figure 7]1 is a cross-sectional view of an image sensor according to an example embodiment. [Figure 8] 1 is a cross-sectional view of an image sensor according to an example embodiment. [Figure 9] 1 is a cross-sectional view of an image sensor according to an example embodiment. [Figure 10] 1 is a cross-sectional view of an image sensor according to an example embodiment. [Figure 11] 1 is a cross-sectional view of an image sensor according to an example embodiment. [Figure 12] 1 is a cross-sectional view of an image sensor according to an example embodiment. [Figure 13] 1 is a cross-sectional view of an image sensor according to an example embodiment. [Figure 14] 11 is a flow chart illustrating a method for manufacturing the first layer of FIG. 10. [Figure 15] 15 is a diagram for explaining the manufacturing method of FIG. 14. [Figure 16] 15 is a diagram for explaining the manufacturing method of FIG. 14. [Figure 17] 15 is a diagram for explaining the manufacturing method of FIG. 14. [Figure 18] 11 is a flow chart illustrating a method for manufacturing the second layer of FIG. 10. [Figure 19] 19 is a diagram for explaining the manufacturing method of FIG. 18. [Figure 20] 19 is a diagram for explaining the manufacturing method of FIG. 18. [Figure 21] 19 is a diagram for explaining the manufacturing method of FIG. 18. [Figure 22] 11 is a flowchart illustrating a method for manufacturing the third layer of FIG. 10. [Figure 23] 23 is a diagram for explaining the manufacturing method of FIG. 22. [Figure 24] 23 is a diagram for explaining the manufacturing method of FIG. 22. [Diagram 25] 11 is a flow chart illustrating a method for manufacturing the bonded second and third layers of FIG. 10. FIG. [Figure 26] 25 is a diagram for explaining the manufacturing method of FIG. 24. [Figure 27] 25 is a diagram for explaining the manufacturing method of FIG. 24. [Figure 28] FIG. 28 is an enlarged view of a portion BB in FIG. 27. [Figure 29] 25 is a diagram for explaining the manufacturing method of FIG. 24. [Diagram 30] 11 is a flow chart illustrating a method for manufacturing the bonded first to third layers of FIG. 10. FIG. [Diagram 31] 31 is a diagram for explaining the manufacturing method of FIG. 30. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following, embodiments of the present invention are described clearly and in detail to the extent that those skilled in the art can easily practice the present invention.

[0014] FIG. 1 is a block diagram of an image sensor according to an embodiment of the present invention.

[0015] Referring to FIG. 1, an image sensor according to an embodiment of the present invention includes a pixel array (1), a row decoder (2), a row driver (3), a column decoder (4), a timing generator (5), a correlated double sampler (CDS; 6), an analog to digital converter (ADC; 7), and an input / output buffer (I / O buffer; 8).

[0016] The pixel array 1 includes a plurality of unit pixels arranged two-dimensionally, and converts an optical signal into an electrical signal. The pixel array 1 can be driven by a plurality of driving signals, such as a pixel selection signal, a reset signal, and a charge transfer signal, from a row driver 3. The converted electrical signal is provided to a correlated double sampler 6.

[0017] The row driver 3 provides a number of driving signals for driving a number of unit pixels to the pixel array 1 according to the result of decoding by the row decoder 2. When the unit pixels are arranged in a matrix, a driving signal can be provided for each row.

[0018] A timing generator 5 provides timing and control signals to the row decoder 2 and the column decoder 4 .

[0019] The correlated double sampler 6 receives and holds and samples the electrical signal generated by the pixel array 1. The correlated double sampler 6 double samples a specific noise level and a signal level according to the electrical signal, and outputs a difference level corresponding to the difference between the noise level and the signal level.

[0020] The analog-to-digital converter 7 converts the analog signal corresponding to the difference level output from the correlated double sampler 6 into a digital signal and outputs it.

[0021] The input / output buffer 8 latches digital signals and sequentially outputs the latched digital signals to an image signal processor (not shown) according to the decoding result of the column decoder 4 .

[0022] FIG. 2 is a circuit diagram of a pixel in an image sensor according to an embodiment of the present invention.

[0023] 2, the pixel PXL may include a photoelectric conversion element PD1, PD2, PD3, PD4, a floating diffusion region FD, and a pixel transistor. The pixel transistor may include a transfer transistor TX1, TX2, TX3, TX4, a reset transistor RX, a source follower transistor SF, a selection transistor SEL, and a dual conversion gain transistor DCX.

[0024] Although it has been disclosed that the pixel PXL includes four transfer transistors TX1, TX2, TX3, and TX4 and four photoelectric conversion elements PD1, PD2, PD3, and PD4, this is not intended to be limiting. In other examples, the pixel PXL may include fewer or more than four transfer transistors and photoelectric conversion elements. The photoelectric conversion elements PD may generate and accumulate charges corresponding to incident light. The photoelectric conversion elements PD1, PD2, PD3, and PD4 may include, for example, a photo diode, a photo transistor, a photo gate, a pinned photo diode, or a combination thereof.

[0025] The transfer transistors TX1, TX2, TX3, and TX4 may be configured to transfer charges accumulated in the photoelectric conversion elements PD1, PD2, PD3, and PD4 to the floating diffusion region FD in response to transfer signals applied to the transfer gates TG1, TG2, TG3, and TG4. The sources of the transfer transistors TX1, TX2, TX3, and TX4 may be electrically connected to the corresponding photoelectric conversion elements PD1, PD2, PD3, and PD4. The drains of the transfer transistors TX1, TX2, TX3, and TX4 may be electrically connected to the floating diffusion region FD.

[0026] The floating diffusion region FD may be configured to accumulate charges transferred from the photoelectric conversion elements PD1, PD2, PD3, and PD4. The source follower transistor SF may be controlled according to the amount of photocharge accumulated in the floating diffusion region FD.

[0027] The reset transistor RX may be configured to reset charges accumulated in the floating diffusion region FD in response to a reset signal applied to the reset gate RG. The drain of the reset transistor RX may be electrically connected to the source of the dual conversion gain transistor DCX. The source of the reset transistor RX may be connected to a pixel power supply voltage Vdd. When the reset transistor RX and the dual conversion gain transistor DCX are turned on, the pixel power supply voltage Vdd is transferred to the floating diffusion region FD. Thus, charges accumulated in the floating diffusion region FD may be discharged and the floating diffusion region FD may be reset.

[0028] The dual conversion gain transistor DCX may be provided between the floating diffusion region FD and the reset transistor RX. The drain of the dual conversion gain transistor DCX may be electrically connected to the floating diffusion region FD. The dual conversion gain transistor DCX may adjust the capacitance of the floating diffusion region FD in response to a dual conversion gain control signal applied to the dual conversion gain control gate DCG. When the dual conversion gain transistor DCX is turned off with the reset transistor RX turned off, the floating diffusion region FD may extend to the drain of the dual conversion gain transistor DCX. Thus, the floating diffusion region FD may have a relatively small first capacitance. When the dual conversion gain transistor DCX is turned on with the reset transistor RX turned off, the floating diffusion region FD may extend to the drain of the reset transistor RX. Thus, the floating diffusion region FD may have a relatively large second capacitance. In one example, the difference between the second capacitance and the first capacitance may be caused by a natural capacitance of a conductive line between the drain of the reset transistor RX and the source of the dual conversion gain transistor DCX. In one example, the difference between the second capacitance and the first capacitance can be generated by a capacitor disposed on a conductive line branched from the conductive line between the drain of the reset transistor RX and the source of the dual conversion gain transistor DCX. The conversion gain of the pixel PXL can be changed by adjusting the capacitance of the floating diffusion region FD.

[0029] The dual conversion gain transistor DCX may be configured to change the capacitance of the floating diffusion region FD according to the illumination environment. When the dual conversion gain transistor DCX is turned off, the pixel PXL may have a first conversion gain. When the dual conversion gain transistor DCX is turned on, the pixel PXL may have a second conversion gain lower than the first conversion gain. Depending on the operation of the dual conversion gain transistor DCX, different conversion gains may be provided in a first conversion gain mode (or a low illumination mode) and a second conversion gain mode (or a high illumination mode).

[0030] The source follower transistor SF may be configured to output a sampling voltage corresponding to the charge amount of the floating diffusion region FD. For example, the source follower transistor SF may be a source follower buffer amplifier that generates a source-drain current proportional to the charge amount of the floating diffusion region FD input to the source follower gate SFG. The source follower transistor SF may be configured to amplify a potential change in the floating diffusion region FD and output the amplified sampling voltage to an output line Vout through the selection transistor SEL. The drain of the source follower transistor SF may be connected to a pixel power supply voltage Vdd, and the source of the source follower transistor SF may be electrically connected to an input node of the selection transistor SEL.

[0031] The selection transistor SEL may be configured to output a sampling voltage to an output node. The selection transistor SEL may select a unit pixel to be read out on a row-by-row basis. When the selection transistor SEL is turned on by a selection signal applied to the gate of the selection transistor, the selection transistor SEL may output an electrical signal output to the source of the source follower transistor SF to the output line Vout.

[0032] In an embodiment of the present invention, the pixel PXL may be implemented on at least one structure including a semiconductor substrate. The structure may be formed as one or more structures. When the structure is formed as a plurality of structures, they may be stacked in sequence.

[0033] FIG. 3 is a diagram conceptually illustrating a layout of an image sensor according to an embodiment of the present invention, and FIG. 4 is a plan view of the image sensor of FIG.

[0034] 3 and 4, the image sensor may include a plurality of structures stacked sequentially along one direction. For example, the image sensor may include first to third structures S1, S2, and S3 stacked along a third direction D3. The plurality of structures may be provided in the form of a chip, and the sizes of the structures may be the same or different from each other. The first direction D1 and the second direction D2 may be two directions intersecting each other on a plane perpendicular to the third direction D3. The first to third structures S1, S2, and S3 may include a pixel array region APS and a pad region PDA adjacent to the pixel array region APS. For example, the pixel array region APS may be disposed in the center of the image sensor from the perspective along the third direction D3. The pixel array region APS may include a plurality of pixels PXL. The pixels PXL may sense incident light and output a photoelectric signal. The pixels PXL may form rows and columns arranged two-dimensionally. For example, within each row, the pixels PXL may be arranged along the first direction D1. For example, within each of the columns, the pixels PXL may be arranged along the second direction D2.

[0035] The pad area PDA may be located at an edge portion of the image sensor. The pad area PDA may be provided in at least one of the first structure S1 to the third structure S3. In terms of the third direction D3, the pad area PDA may surround the pixel array area APS. A signal pad SPD may be provided on the pad area PDA. The signal pad SPD may output an electrical signal generated in the pixel PXL to the outside. Alternatively, an external electrical signal or voltage may be transmitted to the pixel PXL through the signal pad SPD. Since the pad area PDA is an edge area of ​​the image sensor, the signal pad SPD may be easily connected to the outside.

[0036] In the present invention, components within one pixel may be provided in different structures and connected to each other. Some components may be provided in a first structure S1, other components in a second structure S2, and the remaining structures in a third structure S3. For example, a photoelectric conversion element, a transfer transistor, and a floating diffusion region may be provided in a first structure S1, pixel transistors (e.g., a reset transistor, a source follower transistor, a selection transistor, and a dual conversion gain transistor) may be provided in a second structure S2, and a logic circuit including logic transistors may be provided in a third structure S3. The logic circuit may include a circuit for processing pixel signals from the pixel. For example, the logic circuit may include a control register block, a timing generator, a row driver, a readout circuit, a ramp signal generator, an image signal processor, etc.

[0037] In an embodiment of the present invention, a memory element may be further disposed in the second and / or third structures S2, S3. As the memory element, a dynamic random access memory (DRAM) element, a static random access memory (SRAM) element, a spin transfer torque magnetic random access memory (STT-MRAM) element, a flash memory element, etc. may be formed in an embedded form. The image sensor temporarily stores a frame image using such a memory element and performs signal processing, thereby reducing or minimizing the zero effect and improving the operating characteristics of the image sensor. In addition, the memory element of the image sensor is formed together with a logic element in an embedded form, thereby simplifying the manufacturing process and reducing the size of the product.

[0038] Fig. 5 is a cross-sectional view of an image sensor according to an exemplary embodiment, and Fig. 6 is an enlarged view of a portion AA in Fig. 5.

[0039] 5 and 6, a first layer 100 and a second layer 200 arranged along a third direction D3 may be provided. In one example, the first layer 100 and the second layer 200 may be the first structure S1 and the second structure S2, respectively, described with reference to FIG. 3. The first layer 100 and the second layer 200 may be configured to be bonded to each other. For example, the first layer 100 and the second layer 200 may be bonded by copper (Cu)-copper (Cu) bonding.

[0040] The first layer 100 may include a first substrate 102. The first substrate 102 may be a semiconductor substrate. For example, the first substrate 102 may include silicon (Si), germanium (Ge), or silicon-germanium (SiGe). The first substrate 102 may include a first front surface 102a and a first rear surface 102b facing in opposite directions. The first front surface 102a and the first rear surface 102b may extend along a first direction D1 and a second direction D2. The first front surface 102a and the first rear surface 102b may be spaced apart from each other along a third direction D3. The third direction D3 may be perpendicular to the first direction D1 and the second direction D2. The first substrate 102 may have a first conductivity type. For example, the first conductivity type may be p-type or n-type. When the first substrate 102 has a p-type conductivity, the first substrate 102 may be a silicon (Si) substrate containing a group III element (e.g., boron (B), aluminum (Al), gallium (Ga), indium (In), etc.) or a group II element as an impurity. When the first substrate 102 has an n-type conductivity, the first substrate 102 may be a silicon (Si) substrate containing a group V element (e.g., phosphorus (P), arsenic (As), antimony (Sb), etc.), a group VI element, or a group VII element as an impurity. Hereinafter, the region having an n-type conductivity may contain a group V, group VI, or group VII element as an impurity. Hereinafter, the impurities that cause the first substrate 102 to have a first conductivity type and a second conductivity type may be referred to as a first impurity and a second impurity, respectively. When the first conductivity type is a p-type or n-type, the second conductivity type may be referred to as an n-type or p-type, respectively. The first substrate 102 may be an epi layer formed by an epitaxial growth process. For ease of explanation, the first conductivity type is hereinafter described as P type and the second conductivity type is hereinafter described as N type.

[0041] The first layer 100 may include a first isolation layer 104. The first isolation layer 104 may be provided on the first substrate 102. The first isolation layer 104 may define an active region. The active region may be a region in which a transfer gate electrode 112, a transfer gate insulating layer 114, and a floating diffusion region 110, which will be described later, are provided. In a plan view, the first isolation layer 104 may surround the active region. The first isolation layer 104 may have a thickness along a third direction D3. The thickness of the first isolation layer 104 may be smaller than the thickness of a pixel isolation layer, which will be described later. For example, the first isolation layer 104 may be a shallow trench isolation (STI). In one example, one surface of the first isolation layer 104 may be located at substantially the same level as the first front surface 102a. The first isolation layer 104 may include silicon nitride, silicon oxide, silicon oxynitride, or a combination thereof.

[0042] The first layer 100 may include a pixel isolation layer 106. The pixel isolation layer 106 may be provided between the pixels PXL. The pixel isolation layer 106 may extend along a third direction D3. In one example, both surfaces of the pixel isolation layer 106 spaced apart from each other along the third direction D3 may be positioned at substantially the same level as the first front surface 102a and the first rear surface 102b, respectively. The pixel isolation layer 106 may prevent or reduce an electric crosstalk phenomenon that reduces a signal-to-noise ratio due to charge carrier exchange between adjacent pixels PXL. For example, the pixel separation layer 106 may include a conductive material (e.g., at least one of doped polysilicon, metal, metal silicide, metal nitride, or metal-containing material), an insulating material (e.g., a silicon-based insulating material (e.g., silicon nitride, silicon oxide, and / or silicon oxynitride), or a high dielectric material (e.g., a metal oxide including at least one metal selected from the group consisting of hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), titanium (Ti), yttrium (Y), and lanthanide (La). In one example, the sidewall of the pixel separation layer 106 is doped with a material having a high reflectivity to reduce optical crosstalk detected by pixels adjacent to the pixel where light is incident. The crosstalk phenomenon can be prevented or reduced. For example, the material having high reflectivity can be boron. When the pixel separation layer 106 includes a conductive material, for example, a negative fixed charge layer can be provided between the pixel separation layer 106 and the first substrate 102. The negative fixed charge layer can include a metal oxide including at least one metal selected from the group consisting of hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), titanium (Ti), yttrium (Y), and lanthanoid (La). However, the structure of the pixel separation layer 106 can be determined as necessary. In one embodiment, the pixel separation layer 106 can be an insulating film having a single structure. In one embodiment, the pixel separation layer 106 can include a plurality of insulating films.

[0043] The first layer 100 may include a photoelectric conversion region 108. The photoelectric conversion region 108 may be provided in the first substrate 102. The photoelectric conversion region 108 may be disposed in each pixel PXL. In an embodiment, the photoelectric conversion region 108 may include at least one photodiode. For example, the photoelectric conversion region 108 may include a pn photodiode. In an example, the p-type region of the photoelectric conversion region 108 is the first substrate 102, and the n-type region may be formed by injecting a second impurity into the first substrate 102. In an example, the p-type region may be formed by injecting a first impurity into the first substrate 102. In this case, the doping concentration of the p-type region may be higher than the doping concentration of the first substrate 102. In an example, the first impurity may be further injected into the first substrate 102 to form a plurality of pn junctions located at different depths. However, it is merely exemplary that the photoelectric conversion region 108 includes a photodiode. In an embodiment, the photoelectric conversion region 102 may include phototransistors, photogates, or pinned photodiodes. When light is incident on the photoelectric conversion region 108, electron-hole pairs (EHPs) may be generated in the photoelectric conversion region 108. For example, the electron-hole pairs may be generated in a depletion region formed in a region adjacent to a pn junction. Since light penetrates the first substrate 102 to different depths depending on its wavelength, light having different wavelengths may be efficiently detected when multiple pn junctions located at different depths are used. The stronger the intensity of light incident on the photoelectric conversion region 108, the more electron-hole pairs may be generated. When a reverse bias is applied to the photoelectric conversion region 108, charge carriers (electrons or holes) may be accumulated in the photoelectric conversion region 108. Charge carriers stored in the photoelectric conversion region 108 can be transferred to the floating diffusion region 110 by a voltage applied to a transfer gate electrode 112 .

[0044] The first layer 100 may include a floating diffusion region 110. The floating diffusion region 110 may be provided in the first substrate 102. The floating diffusion region 110 may be provided in a region adjacent to the first front surface 102a. The floating diffusion region 110 may have a second conductivity type. In an embodiment, the floating diffusion region 110 may be formed by implanting a second impurity into the first substrate 102. The floating diffusion region 110 may be separated from the photoelectric conversion region 108. A region between the floating diffusion region 110 and the photoelectric conversion region 108 (i.e., a region of the first substrate 102) may have the first conductivity type. The floating diffusion region 110 may receive and accumulate charge carriers provided from the photoelectric conversion region 108.

[0045] The first layer 100 may include a transfer gate electrode 112. The transfer gate electrode 112 may be provided adjacent to the floating diffusion region 110 and the photoelectric conversion region 108. The transfer gate electrode 112 may be inserted into the first substrate 102. In one example, a portion of the transfer gate electrode 112 may protrude above the first front surface 102a, and another portion may be inserted into the first substrate 102. The transfer gate electrode 112 may extend along a third direction D3. The transfer gate electrode 112 may include an electrically conductive material. For example, the transfer gate electrode 112 may include doped polysilicon or a metal (e.g., copper (Cu), aluminum (Al), molybdenum (Mo), platinum (Pt), titanium (Ti), tantalum (Ta), tungsten (W), or a combination thereof). The transfer gate electrode 112 may be referred to as a vertical transfer gate (VTG).

[0046] The first layer 100 may include a transfer gate insulating film 114. The transfer gate insulating film 114 may be provided between the transfer gate electrode 112 and the first substrate 102. The transfer gate insulating film 114 may extend along a surface of the transfer gate electrode 112. The transfer gate insulating film 114 may be configured to electrically isolate the transfer gate electrode 112 from the first substrate 102. For example, the transfer gate insulating film 114 may include a silicon-based insulating material (e.g., silicon nitride, silicon oxide, and / or silicon oxynitride) or a high dielectric material (e.g., a metal oxide including at least one metal selected from the group consisting of hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), titanium (Ti), yttrium (Y), and lanthanides (La)).

[0047] The transfer gate electrode 112, the transfer gate insulating film 114, the photoelectric conversion region 108, and the floating diffusion region 110 may form a transfer transistor. The transfer gate electrode 112, the photoelectric conversion region 108, and the floating diffusion region 110 may form a gate, a source, and a drain of the transfer transistor, respectively. When a voltage is applied to the transfer gate electrode 112, a channel of a second conductivity type may be formed in a region of the first substrate 102 adjacent to the transfer gate electrode 112. The channel may be configured to move charge carriers generated in the photoelectric conversion region 108 to the floating diffusion region 110. When no voltage is applied to the transfer gate electrode 112, charge carriers generated in the photoelectric conversion region 108 may be accumulated in the photoelectric conversion region 108.

[0048] In an embodiment, the first layer 100 may include a ground region (not shown). The ground region may be provided on the first substrate 102. The ground region may have a second conductivity type. The ground region may be formed by implanting a second impurity into the first substrate 102. The ground region may be spaced apart from the photoelectric conversion region 108. The ground region may be configured to apply a ground voltage to the first substrate 102.

[0049] The first layer 100 may include a first insulating layer 142. The first insulating layer 142 may be provided on the first front surface 102a. The first insulating layer 142 may include an electrically insulating material. For example, the first insulating layer 142 may include silicon nitride, silicon oxide, silicon oxynitride, or a combination thereof.

[0050] The first layer 100 may include a first conductive line 150. The first conductive line 150 may be provided in the first insulating layer 142. The first conductive line 150 may include a conductive line 1a 150a and a conductive line 1b 150b. The conductive line 1a 150a may be electrically connected to the floating diffusion region 110. The conductive line 1b 150b may be electrically connected to the transfer gate electrode 112. Each of the conductive line 1a 150a and the conductive line 1b 150b may include a first vertical conductive line 152 and a first horizontal conductive line 154. The first vertical conductive line 152 may extend along a third direction D3. The first horizontal conductive lines 154 may be disposed between the first vertical conductive lines 152 and electrically connect the first vertical conductive lines 152 immediately adjacent to each other. The first horizontal conductive line 154 may extend along a direction parallel to the first front surface 102a. For example, the first horizontal conductive line 154 may extend along a first direction D1 or a second direction D2. In one example, the first vertical conductive lines 152 that are immediately adjacent to each other and directly connected to different floating diffusion regions 110 may be electrically connected to each other by one first horizontal conductive line 154. The first vertical conductive line 152 and the first horizontal conductive line 154 may include an electrically conductive material. For example, the first vertical conductive line 152 and the first horizontal conductive line 154 may include doped polysilicon or a metal (e.g., copper (Cu), aluminum (Al), molybdenum (Mo), platinum (Pt), titanium (Ti), tantalum (Ta), tungsten (W), or a combination thereof).

[0051] The first layer 100 may include a first pad 162. The first pad 162 may be provided on the first vertical conductive line 152 disposed furthest from the first front surface 100a. The first pad 162 may include copper (Cu) or a copper alloy. The first pad 162 may be configured to form a copper (Cu)-copper (Cu) bond with a second pad 262 described below. Although one first pad 162 is illustrated, this is exemplary. The number of the first pads 162 may be determined as needed. For example, the number of the first pads 162 may be the same as the number of the second pads 262.

[0052] The second layer 200 may include a second substrate 202. The second substrate 202 may be provided on the first insulating layer 142. The second substrate 202 may be a semiconductor substrate. For example, the second substrate 202 may include silicon (Si), germanium (Ge), or silicon-germanium (SiGe). The second substrate 202 may include a second front surface 202a and a second rear surface 202b facing in opposite directions. The second front surface 202a and the second rear surface 202b may extend along a first direction D1 and a second direction D2. The second front surface 202a and the second rear surface 202b may be spaced apart from each other along a third direction D3. The second rear surface 202b may be disposed opposite to the first front surface 102a. The second front surface 202a may be disposed opposite to the second rear surface 202b. The second substrate 202 may have a first conductivity type.

[0053] The second layer 200 may include a second isolation layer 204. The second isolation layer 204 may be provided on the second substrate 202. The second isolation layer 204 may define an active region. The active region may be a region in which a pixel transistor 210, which will be described later, is provided. In a plan view, the second isolation layer 204 may surround the active region. The second isolation layer 204 may have a thickness along the third direction D3. For example, the second isolation layer 204 may be a shallow trench isolation layer STI. In one example, an upper surface of the second isolation layer 204 may be located at substantially the same level as the second front surface 202a. The second isolation layer 204 may include silicon nitride, silicon oxide, silicon oxynitride, or a combination thereof.

[0054] The second layer 200 may include a pixel transistor 210. The pixel transistor 210 may be used to drive an image sensor. The pixel transistor 210 may be provided adjacent to the second front surface 202a. The pixel transistor 210 may include a first pixel transistor 210a and a second pixel transistor 210b. The first pixel transistor 210a may be electrically connected to the floating diffusion region 110. For example, the first pixel transistor 210a may include a dual conversion gain transistor and a source follower transistor. The floating diffusion region 110 may be electrically connected to a drain terminal of the dual conversion gain transistor and a gate terminal of the source follower transistor. The second pixel transistor 210b may be electrically connected to at least one of the first pixel transistors 210a. For example, the second pixel transistor 210b may include a reset transistor and a selection transistor. The drain terminal of the reset transistor may be electrically connected to a source terminal of the dual conversion gain transistor. The input terminal of the selection transistor may be electrically connected to the source terminal (output terminal) of the source follower transistor. For ease of explanation, a reset transistor is illustrated in the second pixel transistor 210b.

[0055] The pixel transistor 210 may include a gate-all-around type transistor. Each of the first pixel transistor 210a and the second pixel transistor 210b may include a pair of pixel source / drain regions 211, a pixel gate electrode 213, a pixel gate insulating film 214, a pixel channel region 215, and a pixel spacer 216. The pair of pixel source / drain regions 211 may be a source region and a drain region of the pixel transistor 210, respectively. The pair of pixel source / drain regions 211 may be spaced apart from each other via the pixel gate electrode 213. The pair of pixel source / drain regions 211 may be connected by the pixel channel region 215. Although the pair of pixel source / drain regions 211 is illustrated as being spaced apart from each other along the first direction D1, this is merely an example. The direction in which the pair of pixel source / drain regions 211 are spaced apart from each other may be determined according to the shape of the pixel transistor 210. The pair of pixel source / drain regions 211 may be an epi layer formed by an epitaxial growth process. For example, the pair of pixel source / drain regions 211 may include silicon (Si), germanium (Ge), or silicon-germanium (SiGe). The pair of pixel source / drain regions 211 may have a second conductivity type.

[0056] The pixel gate electrode 213 may be provided between a pair of pixel source / drain regions 211. The pixel gate electrode 213 may include an electrically conductive material. For example, the pixel gate electrode 213 may include doped polysilicon or a metal (e.g., copper (Cu), aluminum (Al), molybdenum (Mo), platinum (Pt), titanium (Ti), tantalum (Ta), tungsten (W), or a combination thereof). When the pixel transistor 210 is a source follower transistor, the pixel gate electrode 213 may be electrically connected to the floating diffusion region 110. A voltage according to an amount of charge stored in the floating diffusion region may be a gate voltage. When the pixel transistor 210 is a reset transistor, a reset signal voltage may be applied to the pixel gate electrode 213 to apply an initial voltage to the floating diffusion region 110. Applying the initial voltage to the floating diffusion region 110 may be referred to as a reset operation. When the pixel transistor 210 is a selection transistor, a selection signal voltage may be applied to the pixel gate electrode 213 to output a signal. A channel of the pixel transistor 210 may be formed between a pair of pixel source / drain regions 211 by a voltage applied to the pixel gate electrode 213 .

[0057] The pixel channel region 215 may be provided on the second front surface 202a. The pixel channel region 215 may be spaced apart from the second front surface 202a. The pixel channel region 215 may penetrate the pixel gate electrode 213. For example, the pixel channel region 215 may extend along a first direction D1 to connect a pair of pixel source / drain regions 211. A side of the pixel channel region 215 extending along the first direction D1 may be surrounded by the pixel gate electrode 213. Thus, a side of the pixel channel region 215 extending along the first direction D1 may be used as a channel of the pixel transistor 210. Although three pixel channel regions 215 are illustrated, this is merely exemplary. In other examples, the number of pixel channel regions 215 may be less than three or more than three. The pixel channel region 215 may be an epi layer formed by an epitaxial growth process. For example, the pixel channel region 215 may include silicon (Si), germanium (Ge), or silicon-germanium (SiGe). The pixel channel region 215 may have a first conductivity type.

[0058] The pixel gate insulating layer 214 may be provided between the pixel gate electrode 213 and the pixel channel region 215. The pixel gate insulating layer 214 may include an electrically insulating material. For example, the pixel gate insulating layer 214 may include silicon oxide, silicon nitride, or silicon oxynitride. The pixel gate insulating layer 214 may be configured to electrically isolate the pixel gate electrode 213 and the pixel channel region 215.

[0059] A pixel spacer 216 may be disposed between the first pixel source / drain region 211 and the pixel gate electrode 213, and between the second pixel source / drain region 211 and the pixel gate electrode 213, respectively. The pixel spacer 216 may include an electrically insulating material. For example, the pixel spacer 216 may include an insulating material (e.g., a silicon-based insulating material (e.g., silicon nitride, silicon oxide, and / or silicon oxynitride) or a high-k material (e.g., a metal oxide including at least one metal selected from the group consisting of hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), titanium (Ti), yttrium (Y), and lanthanide (La)). The pixel spacer 216 may be configured to electrically isolate a pair of pixel source / drain regions 211 from the pixel gate electrode 213.

[0060] The second layer 200 can include a second insulating layer 222. The second insulating layer 222 can be provided on the second back surface 202b. The second insulating layer 222 can include an electrically insulating material. For example, the second insulating layer 222 can include silicon nitride, silicon oxide, silicon oxynitride, or a combination thereof.

[0061] The second layer 200 may include a second pad 262. The second pad 262 may be in direct contact with the first pad 162. The second pad 262 may include copper (Cu) or a copper alloy. The second pad 262 may be configured to form a copper (Cu)-copper (Cu) bond with the first pad 162. Although one second pad 262 is illustrated, this is for illustrative purposes only. The number of the second pads 262 may be determined as needed. For example, the number of the second pads 262 may be the same as the number of the first pads 162.

[0062] The second layer 200 may include a second conductive line 230. The second conductive line 230 may be provided in the second insulating layer 222. The second conductive line 230 may be electrically connected to the second pad 262 and the first pixel transistor 210a. The second conductive line 230 may include a second vertical conductive line 232 and a second horizontal conductive line 234.

[0063] The second vertical conductive line 232 may be configured to penetrate the second insulating layer 222. The second vertical conductive line 232 may extend along the third direction D3. The second vertical conductive line 232 immediately adjacent to the second pad 262 may be configured to be in direct contact with the second pad 262. The second vertical conductive line 232 immediately adjacent to the first pixel transistor 210a may penetrate the second substrate 202 and be electrically connected to the first pixel transistor 210a. For example, the second vertical conductive line 232 immediately adjacent to the first pixel transistor 210a may penetrate the second substrate 202 and be connected to the bottom of the first pixel transistor 210a. The bottom of the first pixel transistor 210a may refer to a portion of the first pixel transistor 210a adjacent to the second front surface 202a. The second vertical conductive line 232 immediately adjacent to the first pixel transistor 210a may overlap the first pixel transistor 210a along the third direction D3. The second vertical conductive line 232 immediately adjacent to the first pixel transistor 210a may be separated from a third insulating layer 242, which will be described later. The second vertical conductive line 232 may include an electrically conductive material. For example, the second vertical conductive line 232 may include doped polysilicon or a metal (e.g., copper (Cu), aluminum (Al), molybdenum (Mo), platinum (Pt), titanium (Ti), tantalum (Ta), tungsten (W), or a combination thereof).

[0064] The second vertical conductive line 232 immediately adjacent to the source follower transistor in the first pixel transistor 210a may overlap with the pixel gate electrode 213 of the source follower transistor along the third direction D3. The second vertical conductive line 232 immediately adjacent to the source follower transistor may directly contact a back surface of the pixel gate electrode 213 of the source follower transistor. The back surface of the pixel gate electrode 213 of the source follower transistor may be a surface of the pixel gate electrode 213 immediately adjacent to the second front surface 202a.

[0065] The second vertical conductive line 232 immediately adjacent to the dual conversion gain transistor in the first pixel transistor 210a may overlap with one of the pair of pixel source / drain regions 211 of the dual conversion gain transistor along the third direction D3. One of the pair of pixel source / drain regions 211 may be the drain of the dual conversion gain transistor. The second vertical conductive line 232 immediately adjacent to the dual conversion gain transistor may directly contact a back surface of one of the pair of pixel source / drain regions 211 of the dual conversion gain transistor. The back surface of one of the pair of pixel source / drain regions 211 of the dual conversion gain transistor may be a surface of one of the pair of pixel source / drain regions 211 immediately adjacent to the second front surface 202a.

[0066] The second horizontal conductive lines 234 may be provided between the second vertical conductive lines 232. The second horizontal conductive lines 234 may electrically connect the second vertical conductive lines 232 immediately adjacent to each other. Although one second horizontal conductive line 234 is illustrated, this is for illustrative purposes. The number of the second horizontal conductive lines 234 may be determined as needed. The second horizontal conductive lines 234 may extend along a direction parallel to the second back surface 202b. For example, the second horizontal conductive lines 234 may extend along a first direction D1 or a second direction D2. The second horizontal conductive lines 234 may include an electrically conductive material. For example, the second horizontal conductive lines 234 may include doped polysilicon or a metal (e.g., copper (Cu), aluminum (Al), molybdenum (Mo), platinum (Pt), titanium (Ti), tantalum (Ta), tungsten (W), or a combination thereof).

[0067] The second layer 200 can include a third insulating layer 242. The third insulating layer 242 can be provided on the second front surface 202a. The third insulating layer 242 can include an electrically insulating material. For example, the third insulating layer 242 can include silicon nitride, silicon oxide, silicon oxynitride, or a combination thereof.

[0068] The second layer 200 may include a third conductive line 250. The third conductive line 250 may be provided in the third insulating layer 242. The third conductive line 250 may be electrically connected to the first pixel transistor 210a and the second pixel transistor 210b. In one example, the third conductive line 250 may be electrically connected to a second pad 262 disposed in the pad area PDA. The third conductive line 250 may include a third vertical conductive line 252 and a third horizontal conductive line 254.

[0069] The third vertical conductive line 252 may be configured to penetrate the third insulating layer 242. The third vertical conductive line 252 may extend along a third direction D3. The third vertical conductive line 252 may include an electrically conductive material. For example, the third vertical conductive line 252 may include doped polysilicon or a metal (e.g., copper (Cu), aluminum (Al), molybdenum (Mo), platinum (Pt), titanium (Ti), tantalum (Ta), tungsten (W), or a combination thereof).

[0070] The third horizontal conductive line 254 may be provided between the third vertical conductive lines 252. The third horizontal conductive line 254 may electrically connect the third vertical conductive lines 252 immediately adjacent to each other. The third horizontal conductive line 254 may extend along a direction parallel to the second back surface 202b. For example, the third horizontal conductive line 254 may extend along a first direction D1 or a second direction D2. The third horizontal conductive line 254 may include an electrically conductive material. For example, the third horizontal conductive line 254 may include doped polysilicon or a metal (e.g., copper (Cu), aluminum (Al), molybdenum (Mo), platinum (Pt), titanium (Ti), tantalum (Ta), tungsten (W), or a combination thereof).

[0071] A color filter 132 and a microlens 134 may be provided on the first rear surface 102b of the first substrate 102. The color filters 132 may be provided at positions corresponding to the photoelectric conversion regions 108. Each of the color filters 132 may include any one of a red filter, a blue filter, and a green filter, but is not limited thereto, and filters of other colors may be provided. The color filters 132 may form a color filter array. For example, the color filters 132 may form an array arranged along a first direction D1 and a second direction D2 in a plan view.

[0072] The microlens 134 may be disposed on the color filter 132. The microlens 134 may include a lens pattern and a planarized portion. The planarized portion of the microlens 134 may be provided on the color filter 132. The lens pattern may be provided on the planarized portion. The lens pattern may be formed integrally with the planarized portion and connected without an interface. The lens pattern may include the same material as the planarized portion. As another example, the planarized portion may be omitted, and the lens pattern may be disposed directly on the color filter 132. The lens pattern may be hemispherical. The lens pattern may focus incident light. The lens pattern may be provided at a position corresponding to the photoelectric conversion region 108. The microlens 134 is transparent, and therefore may transmit light. The microlens 134 may include an organic material such as a polymer. For example, the microlens 134 may include a photoresist material or a thermosetting resin. Although not shown, a protective layer may be provided on the microlens 134, and the protective layer may include an organic material and / or an inorganic material. According to an embodiment, the protective layer may include a silicon-containing material such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbon-oxide, silicon carbon-nitride, and / or silicon carbon-oxynitride. As another example, the protective layer may include aluminum oxide, zinc oxide, and / or hafnium oxide. The protective layer may have insulating properties, but is not limited thereto. The protective layer may be light-transmitting.

[0073] In the present invention, the second conductive line 230 may be configured to directly contact the back surface of one of the pixel gate electrode 213 of the first pixel transistor 210a or the pair of pixel source / drain regions 211. Unlike the present invention, when the second conductive line 230 directly contacts the front surface of the pixel gate electrode 213 of the first pixel transistor 210a or the pair of pixel source / drain regions 211, the second conductive line 230 is configured to pass through the second insulating layer 222, the second substrate 202, and the third insulating layer 242. In order for the second conductive line 230 to extend through the second substrate 202 to the third insulating layer 242, a region of the second substrate 202 horizontally separated from the first pixel transistor 210a must be used for the second conductive line 230. In the present invention, since the second conductive line 230 penetrates the second substrate 202 and is directly connected to the pixel gate electrode 213 or the pair of pixel source / drain regions 211 of the first pixel transistor 210a, no region of the second substrate 202 is required for disposing the second conductive line 230 in a plan view. Therefore, a miniaturized image sensor 10 can be provided.

[0074] 7 is a cross-sectional view of an image sensor according to an exemplary embodiment. For ease of explanation, differences from those described with reference to FIGS.

[0075] 7, a first layer 100 and a second layer 200 arranged along a third direction D3 may be provided. Unlike what has been described with reference to FIGS. 5 and 6, a pixel transistor 210 may be a FINFET type. The pixel transistor 210 may include a pair of pixel source / drain regions 211, a pixel gate electrode 213, a pixel gate insulating film 214, a pixel channel region 215, and a pixel spacer 216.

[0076] The pixel channel region 215 may be connected to the second substrate 202. The pixel channel region 215 may protrude from the second front surface 202a. The pixel channel region 215 may be connected to the second substrate 202. For example, a rear surface of the pixel channel region 215 may contact the second front surface 202a. The rear surface of the pixel channel region 215 may face the second front surface 202a. The pixel channel region 215 may connect a pair of pixel source / drain regions 211. The pixel channel region 215 may extend along a first direction D1. A side surface (not shown) of the pixel channel region 215 extending along the first direction D1 may be covered by the pixel gate electrode 213. Therefore, the side surface of the pixel channel region 215 extending along the first direction D1 may be used as a channel of the pixel transistor 210.

[0077] Unlike the description with reference to Figs. 5 and 6, the pixel gate electrode 213 of the source follower transistor and one of the pair of pixel source / drain regions 211 of the dual conversion gain transistor may be electrically connected to each other by a third conductive line 250 instead of the second conductive line 230. For example, the second conductive line 230 may be provided between the second pad 262 and one of the pair of pixel source / drain regions 211 of the dual conversion gain transistor, and the third conductive line 250 may be provided between the pixel gate electrode 213 of the source follower transistor and one of the pair of pixel source / drain regions 211 of the dual conversion gain transistor. The third vertical conductive line 252 immediately adjacent to the dual conversion gain transistor may directly contact the front surface of one of the pair of pixel source / drain regions 211 of the dual conversion gain transistor. The front surface of one of the pair of pixel source / drain regions 211 of the dual conversion gain transistor may be the surface of one of the pair of pixel source / drain regions 211 immediately adjacent to the second front surface 202a.

[0078] In the present invention, since the second conductive line 230 penetrates the second substrate 202 and is directly connected to one of the pair of pixel source / drain regions 211 of the first pixel transistor 210a, no region of the second substrate 202 is required for disposing the second conductive line 230 in a plan view, so that a miniaturized image sensor 11 can be provided.

[0079] 8 is a cross-sectional view of an image sensor according to an exemplary embodiment. For ease of explanation, differences from those described with reference to FIGS.

[0080] Referring to FIG. 8, the first layer 100 and the second layer 200 arranged along the third direction D3 may be provided. Unlike what has been described with reference to FIG. 5 and FIG. 6, the pixel transistor 210 may include a planar type transistor. A pair of pixel source / drain regions 211 may be provided on the upper portion of the second substrate 202. A pixel channel region may be provided in the second substrate 202 between the pair of pixel source / drain regions 211. A pixel gate electrode 213 may be provided on the second front surface 202a of the second substrate 202. A pixel gate insulating film 214 may be provided between the pixel gate electrode 213 and the second front surface 202a. In terms of the third direction D3, the pair of pixel source / drain regions 211 may be spaced apart from each other via the pixel gate electrode 213. Although the pair of pixel source / drain regions 211 are illustrated as being spaced apart from each other along the first direction D1, this is merely an example. The direction of spacing between the pair of pixel source / drain regions 211 may be determined according to the shape of the pixel transistor 210. The pair of pixel source / drain regions 211 may have a second conductivity type.

[0081] The pixel gate electrode 213 of the source follower transistor and one of the pair of pixel source / drain regions 211 of the dual conversion gain transistor may be electrically connected to each other by a third conductive line 250 instead of the second conductive line 230. For example, the second conductive line 230 may be provided between the second pad 262 and one of the pair of pixel source / drain regions 211 of the dual conversion gain transistor, and the third conductive line 250 may be provided between the pixel gate electrode 213 of the source follower transistor and one of the pair of pixel source / drain regions 211 of the dual conversion gain transistor. The third vertical conductive line 252 immediately adjacent to the dual conversion gain transistor may directly contact a front surface of one of the pair of pixel source / drain regions 211 of the dual conversion gain transistor. The front surface of one of the pair of pixel source / drain regions 211 of the dual conversion gain transistor may be a surface of one of the pair of pixel source / drain regions 211 immediately adjacent to the second front surface 202a.

[0082] In the present invention, since the second conductive line 230 penetrates the second substrate 202 and is directly connected to one of the pair of pixel source / drain regions 211 of the first pixel transistor 210a, no region of the second substrate 202 is required for disposing the second conductive line 230 in a plan view, so that a miniaturized image sensor 12 can be provided.

[0083] 9 is a cross-sectional view of an image sensor according to an exemplary embodiment. For ease of explanation, differences from those described with reference to FIGS.

[0084] 9, a first layer 100 and a second layer 200 arranged along a third direction D3 may be provided. Unlike what has been described with reference to FIGS. 5 and 6, first vertical conductive lines 152 that are immediately adjacent to each other and directly connected to different floating diffusion regions 110 may each be connected to a first horizontal conductive line 154. The pixels PXL may be configured not to share the pixel transistor 210. For example, each of the pixels PXL may include a dual conversion gain transistor, a source follower transistor, a reset transistor, and a selection transistor.

[0085] In the present invention, since the second conductive line 230 penetrates the second substrate 202 and is directly connected to one of the pair of pixel source / drain regions 211 of the first pixel transistor 210a, no region of the second substrate 202 is required for disposing the second conductive line 230 in a plan view, so that a miniaturized image sensor 13 can be provided.

[0086] 10 is a cross-sectional view of an image sensor according to an exemplary embodiment. For ease of explanation, differences from those described with reference to FIGS.

[0087] 10, an image sensor 14 including a pixel array region APS and a pad region PDA may be provided. The image sensor 14 may be provided with a first layer 100, a second layer 200, and a third layer 300 arranged along a third direction D3. The first layer 100 and the second layer 200 of the pixel array region APS may be substantially the same as the first layer 100 and the second layer 200 described with reference to FIGS. 5 and 6.

[0088] The third layer 300 of the pixel array region APS may include a third substrate 302. The third substrate 302 may be provided on the third insulating layer 242. The third substrate 302 may be a semiconductor substrate. For example, the third substrate 302 may include silicon (Si), germanium (Ge), or silicon-germanium (SiGe). The third substrate 302 may include a third front surface 302a and a third rear surface 302b facing in opposite directions. The third front surface 302a may be configured to face the second front surface 202a. The third front surface 302a and the third rear surface 302b may extend along a first direction D1 and a second direction D2. The third front surface 302a and the third rear surface 302b may be spaced apart from each other along a third direction D3. The third substrate 302 may have a first conductivity type. For example, the first conductivity type may be a p-type or an n-type. When the third substrate 302 has a p-type conductivity, the third substrate 302 may be a silicon (Si) substrate containing a group III element (e.g., boron (B), aluminum (Al), gallium (Ga), indium (In), etc.) or a group II element as an impurity. When the third substrate 302 has an n-type conductivity, the third substrate 302 may be a silicon (Si) substrate containing a group V element (e.g., phosphorus (P), arsenic (As), antimony (Sb), etc.), a group VI element, or a group VII element as an impurity.

[0089] A logic transistor 310 may be provided on the third substrate 302. The logic transistor 310 may include a first logic source / drain region 311, a second logic source / drain region 312, a logic gate electrode 313, a logic gate insulating film 314, and a logic spacer 315. The first logic source / drain region 311 and the second logic source / drain region 312 may be provided on the third substrate 302. In a plan view, the first logic source / drain region 311 and the second logic source / drain region 312 may be spaced apart from each other via the logic gate electrode 313. A logic channel region may be provided in the third substrate 302 between the first logic source / drain region 311 and the second logic source / drain region 312. Although the first logic source / drain region 311 and the second logic source / drain region 312 are illustrated as being spaced apart from each other along the first direction D1, this is merely an example. A direction in which the first logic source / drain region 311 and the second logic source / drain region 312 are spaced apart may be determined according to the shape of the logic transistor 310. The first logic source / drain region 311 and the second logic source / drain region 312 may have a second conductivity type. One of the first logic source / drain region 311 and the second logic source / drain region 312 may be a source region, and the other may be a drain region.

[0090] The logic gate electrode 313 may be provided between the first logic source / drain region 311 and the second logic source / drain region 312. The logic gate electrode 313 may be provided on the third substrate 302. The logic gate electrode 313 may include an electrically conductive material. For example, the logic gate electrode 313 may include doped polysilicon or a metal (e.g., copper (Cu), aluminum (Al), molybdenum (Mo), platinum (Pt), titanium (Ti), tantalum (Ta), tungsten (W), or a combination thereof).

[0091] The logic gate insulating film 314 may be provided between the logic gate electrode 313 and the third front surface 302a. The logic gate insulating film 314 may include an electrically insulating material. For example, the logic gate insulating film 314 may include silicon oxide, silicon nitride, or silicon oxynitride. The logic gate insulating film 314 may be configured to electrically isolate the logic gate electrode 313 and the third substrate 303.

[0092] A logic spacer 315 may be disposed between the first logic source / drain region 311 and the logic gate electrode 313, and between the second logic source / drain region 312 and the logic gate electrode 313, respectively. The logic spacer 315 may include an electrically insulating material. For example, the logic spacer 315 may include an insulating material (e.g., a silicon-based insulating material (e.g., silicon nitride, silicon oxide, and / or silicon oxynitride) or a high dielectric material (e.g., a metal oxide including at least one metal selected from the group consisting of hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), titanium (Ti), yttrium (Y), and lanthanoid (La)). The logic spacer 315 may be configured to electrically isolate the first logic source / drain region 311 and the second logic source / drain region 312 from the logic gate electrode 313.

[0093] The third layer 300 may include a fourth insulating layer 322. The fourth insulating layer 322 may be provided on the third front surface 302a. The fourth insulating layer 322 may be provided between the third insulating layer 242 and the third substrate 302. The fourth insulating layer 322 may include an electrically insulating material. For example, the fourth insulating layer 322 may include silicon nitride, silicon oxide, silicon oxynitride, or a combination thereof.

[0094] The third layer 300 may include a fourth conductive line 330. The fourth conductive line 330 may be provided in a fourth insulating layer 322. The fourth conductive line 330 may be electrically connected to the logic transistor 310. In one example, the fourth conductive line 330 may be electrically connected to a first logic source / drain region 311, a second logic source / drain region 312, and a logic gate electrode 313 of the logic transistor 310.

[0095] The fourth conductive line 330 may be electrically connected to the second pad 262 disposed in the pad area PDA. The fourth conductive line 330 may include a third vertical conductive line 332 and a third horizontal conductive line 334.

[0096] The third vertical conductive line 332 may be configured to penetrate the fourth insulating layer 322. The third vertical conductive line 332 may extend along a third direction D3. The third vertical conductive line 332 may include an electrically conductive material. For example, the third vertical conductive line 332 may include doped polysilicon or a metal (e.g., copper (Cu), aluminum (Al), molybdenum (Mo), platinum (Pt), titanium (Ti), tantalum (Ta), tungsten (W), or a combination thereof).

[0097] The third horizontal conductive line 334 may be provided between the third vertical conductive lines 332. The third horizontal conductive line 334 may electrically connect the third vertical conductive lines 332 immediately adjacent to each other. The third horizontal conductive line 334 may extend along a direction parallel to the second back surface 202b. For example, the third horizontal conductive line 334 may extend along a first direction D1 or a second direction D2. The third horizontal conductive line 334 may include an electrically conductive material. For example, the third horizontal conductive line 334 may include doped polysilicon or a metal (e.g., copper (Cu), aluminum (Al), molybdenum (Mo), platinum (Pt), titanium (Ti), tantalum (Ta), tungsten (W), or a combination thereof).

[0098] The first substrate 102, the first insulating layer 142, the second insulating layer 222, the second substrate 202, the third insulating layer 242, the fourth insulating layer 322, and the third substrate 302 may extend to the pad area PDA. A main via 520 may be provided in the pad area PDA. The main via 520 may extend along a third direction D3. The main via 520 may be configured to penetrate the first substrate 102. One end of the main via 520 may be exposed on the first back surface 102b. One end of the main via 520 may directly contact the signal pad 510. The other end of the main via 520 may be inserted into the first insulating layer 142. The main via 520 may be configured to have a low resistance. For example, the main via 520 may have a larger cross-sectional area than the first to fourth vertical conductive lines 332.

[0099] The first conductive line 150, the first pad 162, the second pad 262, the second conductive line 230, the third conductive line 250, the third pad 264, the fourth pad 342, and the fourth conductive line 330 may be further provided in the pad area PDA. The first pad 162 and the second pad 262 may be disposed adjacent to the bonding surfaces of the first insulating layer 142 and the second insulating layer 222, respectively. The first pad 162 and the second pad 262 may be configured to contact each other to form copper (Cu)-copper (Cu) bonding.

[0100] The first conductive line 150 may be provided between the first pad 162 and the main via 520 and configured to electrically connect the first pad 162 and the main via 520. In one embodiment, the first conductive line 150 may have a lattice shape in terms of the third direction D3. For example, the first horizontal conductive lines 154 may be connected to each other to form a lattice. Depending on process conditions, the width of the first conductive line 150 may be smaller than that of the main via 520. Since the first conductive line 150 is configured in a lattice shape, a resistance to an electrical signal transmitted along the first conductive line 150 may be reduced.

[0101] The second conductive line 230 may be electrically connected to a second pad 262. In one embodiment, the second vertical conductive line 232 immediately adjacent to the second pad 262 may be electrically connected to one second horizontal conductive line 234.

[0102] The third pad 264 and the fourth pad 342 may be disposed adjacent to a bonding surface of the third insulating layer 242 and the fourth insulating layer 322, respectively. The third pad 264 and the fourth pad 342 may be configured to contact each other to form a copper (Cu)-copper (Cu) bond. The third conductive line 250 may be electrically connected to the third pad 264.

[0103] An intermediate via 530 may be provided between the second conductive line 230 and the third conductive line 250. The intermediate via 530 may be configured to electrically connect the second conductive line 230 and the third conductive line 250 to each other. For example, one end of the intermediate via 530 may be in direct contact with the second horizontal conductive line 234 immediately adjacent to the second back surface 202b, and the other end may be in direct contact with the third horizontal conductive line 254 immediately adjacent to the second front surface 202a.

[0104] The fourth conductive line 330 may be provided between the fourth pad 342 and the logic transistor 310. The fourth conductive line 330 may be configured to electrically connect the fourth pad 342 and the logic transistor 310.

[0105] The present invention can provide a miniaturized image sensor 14 .

[0106] 11 is a cross-sectional view of an image sensor according to an exemplary embodiment. For ease of explanation, differences between what has been described with reference to FIG. 10 and what has been described with reference to FIG. 7 will be mainly described.

[0107] 11, an image sensor 15 including a pixel array region APS and a pad region PDA may be provided. Unlike what has been described with reference to FIG 10, the first layer 100 and the second layer 200 of the pixel array region APS may be substantially the same as the first layer 100 and the second layer 200 described with reference to FIG 7. For example, unlike what has been described with reference to FIG 5 and FIG 6, the pixel transistor 210 may be of a FINFET type.

[0108] 12 is a cross-sectional view of an image sensor according to an exemplary embodiment. For ease of explanation, differences between what has been described with reference to FIG. 10 and what has been described with reference to FIG. 8 will be mainly described.

[0109] 12, an image sensor 16 including a pixel array region APS and a pad region PDA may be provided. Unlike what has been described with reference to FIG 10, the first layer 100 and the second layer 200 of the pixel array region APS may be substantially the same as the first layer 100 and the second layer 200 described with reference to FIG 8. For example, unlike what has been described with reference to FIG 5 and FIG 6, the pixel transistor 210 may include a planar type transistor.

[0110] 13 is a cross-sectional view of an image sensor according to an exemplary embodiment. For ease of explanation, differences between what has been described with reference to FIG. 10 and what has been described with reference to FIG. 9 will be mainly described.

[0111] 13, an image sensor 17 including a pixel array region APS and a pad region PDA may be provided. Unlike what has been described with reference to FIG 10, the first layer 100 and the second layer 200 of the pixel array region APS may be substantially the same as the first layer 100 and the second layer 200 described with reference to FIG 9. For example, unlike what has been described with reference to FIG 5 and FIG 6, first vertical conductive lines 152 that are directly connected to different floating diffusion regions 110 that are immediately adjacent to each other may each be connected to a first horizontal conductive line 154.

[0112] Figure 14 is a flow chart for explaining the manufacturing method of the first layer of Figure 10. Figures 15 to 17 are views for explaining the manufacturing method of Figure 14. For the sake of simplicity, the contents that are substantially the same as those described with reference to Figure 10 will not be described.

[0113] 14 and 15, a first substrate 102 may be provided. The first substrate 102 may include a pixel array region APS and a pad region PDA. The first substrate 102 may have a first conductivity type. A first device isolation layer 104, a pixel isolation layer 106, a photoelectric conversion region 108, and a floating diffusion region 110 may be formed in the first substrate 102 in the pixel array region APS (S110). The first device isolation layer 104 may be configured to define an active region. For example, the first device isolation layer 104 may be formed by etching a region of the first substrate 102 adjacent to the first front surface 102a and then filling the etched region with an insulating material.

[0114] The pixel isolation layer 106 is formed between pixels to electrically and optically isolate the pixels. For example, the pixel isolation layer 106 may be formed by etching the first substrate 102 to a required depth and then filling the etched region with a conductive material, an insulating material, or a high dielectric material. In one example, the sidewall of the pixel isolation layer 106 may be doped with a material having high reflectivity (e.g., boron). When the pixel isolation layer 106 includes a conductive material, a negative fixed charge layer may be formed between the pixel isolation layer 106 and the first substrate 102. In one example, when the pixel isolation layer 106 is formed, a main via isolation layer 522 that defines a region in which the main via 520 is to be formed may be formed.

[0115] The photoelectric conversion region 108 may include, for example, a pn photodiode. In one example, the pn photodiode may be formed by injecting a second impurity (i.e., an impurity that causes the first substrate 102 to have the second conductivity type) into the first substrate 102 of the first conductivity type. In one example, a first impurity (i.e., an impurity that causes the first substrate 102 to have the first conductivity type) may be further injected into the first substrate 102.

[0116] The floating diffusion region 110 may be formed in a region adjacent to the first front surface 102a. The floating diffusion region 110 may be formed by implanting a second impurity into the first substrate 102.

[0117] 14 and 16, a transfer gate insulating film 114 and a transfer gate electrode 112 may be formed on the first substrate 102 in the pixel array region APS (S120). For example, the transfer gate insulating film 114 and the transfer gate electrode 112 may be formed by etching a region of the first substrate 102 adjacent to the first front surface 102a, sequentially depositing an insulating film and an electrically conductive material film on a surface of the etched region, and patterning the insulating film and the electrically conductive material film.

[0118] 14 and 17, a first insulating layer 142, a first conductive line 150, and a first pad 162 may be formed on the first front surface 102a (S130). For example, after forming a portion of the first insulating layer 142 on the first front surface 102a, a first vertical conductive line 152 penetrating a portion of the first insulating layer 142 and a first horizontal conductive line 154 extending in the first direction D1 or the second direction D2 on a portion of the first insulating layer 142 may be formed, and the process may be repeated to form another portion of the first insulating layer 142 on a portion of the first insulating layer 142 to cover the first horizontal conductive line 154. A first pad 162 may be formed on the first vertical conductive line 152 disposed farthest from the first front surface 102a. A portion of the first conductive line 150 may be electrically connected to the transfer gate electrode 112. Another portion of the first conductive line 150 may be electrically connected to the floating diffusion region 110. Another portion of the first conductive line 150 may be electrically connected to a main via 520, which will be described later.

[0119] Figure 18 is a flow chart for explaining the method for manufacturing the second layer of Figure 10. Figures 19 to 21 are views for explaining the method for manufacturing Figure 18. For the sake of simplicity, the contents that are substantially the same as those described with reference to Figure 10 will not be described.

[0120] 18 and 19, a second substrate 202 may be provided. The second substrate 202 may include a pixel array region APS and a pad region PDA. The second substrate 202 may have a second conductivity type. A second device isolation layer 204 and a sacrificial pattern 272 may be formed on the second substrate 202 in the pixel array region APS (S210).

[0121] The second isolation layer 204 may be configured to electrically isolate adjacent pixel transistors from each other. For example, the second isolation layer 204 may be formed by etching an area of ​​the second substrate 202 adjacent to the second front surface 202a and then filling the etched area with an insulating material.

[0122] The sacrificial pattern 272 may be configured to specify a position where the second vertical conductive line 232 is to be formed. For example, the sacrificial pattern 272 may be formed at a position overlapping one of a pair of source / drain regions of the dual conversion gain transistor and a gate electrode of the source follower transistor along the third direction D3. For example, the sacrificial pattern 272 may be formed by etching the second substrate 202 from the second front surface 202a to a required depth and then filling the etched region with a sacrificial material. The sacrificial material may be removed by wet etching. For example, the sacrificial material may include, for example, photoresist, silicon oxide, or silicon nitride.

[0123] 18 and 20, pixel transistors 210 may be formed on the second substrate 202 in the pixel array region APS (S220). The pixel transistors may be of a gate-all-around type. Each of the pixel transistors 210 may include a first pixel source / drain region 211, a second pixel source / drain region 211, a pixel channel region 215, a pixel gate electrode 213, a pixel gate insulating film 214, and a pixel spacer 216.

[0124] 18 and 21, a third insulating layer 242, a third conductive line 250, and a third pad 264 may be formed on the second front surface 202a (S230). For example, after forming a portion of the third insulating layer 242 on the second front surface 202a, a third vertical conductive line 252 penetrating a portion of the third insulating layer 242 and a third horizontal conductive line 254 extending in the first direction D1 or the second direction D2 on a portion of the third insulating layer 242 may be formed, and the process may be repeated to form another portion of the third insulating layer 242 on a portion of the third insulating layer 242 to cover the third horizontal conductive line 254. A third pad 264 may be formed on the third vertical conductive line 252 disposed farthest from the second front surface 202a in the pad area PDA.

[0125] Figure 22 is a flow chart for explaining the method for manufacturing the third layer of Figure 10. Figures 23 and 24 are views for explaining the manufacturing method of Figure 22. For the sake of simplicity, the contents that are substantially the same as those described with reference to Figure 10 will not be described.

[0126] 22 and 23, a third substrate 302 may be provided. The third substrate 302 may include a pixel array region APS and a pad region PDA. The third substrate 302 may have a second conductivity type. A third device isolation layer 304 and a logic transistor 310 may be formed on the third substrate 302 (S310). The third device isolation layer 304 may be configured to electrically isolate adjacent logic transistors from each other. For example, the third device isolation layer 304 may be formed by etching a region of the third substrate 302 adjacent to the third front surface 302a and then filling the etched region with an insulating material.

[0127] 22 and 24, a fourth insulating layer 322, a fourth conductive line 330, and a fourth pad 342 may be formed on the third front surface 302a (S320). For example, the following steps may be repeated: forming a part of the fourth insulating layer 322 on the third front surface 302a, forming a fourth vertical conductive line 332 penetrating a part of the fourth insulating layer 322 and a fourth horizontal conductive line 334 extending in the first direction D1 or the second direction D2 on a part of the fourth insulating layer 322, and forming another part of the fourth insulating layer 322 on a part of the fourth insulating layer 322 to cover the fourth horizontal conductive line 334. A fourth pad 342 may be formed on the fourth vertical conductive line 332 disposed farthest from the third front surface 302a in the pad area PDA.

[0128] Figure 25 is a flow chart for explaining a method for manufacturing the bonded second and third layers of Figure 10. Figures 26, 27, and 29 are views for explaining the manufacturing method of Figure 24. Figure 28 is an enlarged view of a portion BB of Figure 27. For ease of explanation, the contents substantially the same as those explained with reference to Figure 10 will not be explained.

[0129] 25 and 26, the second layer 200 and the third layer 300 may be bonded together such that the second front surface 202a and the third front surface 302a face each other (S410). The third pad 264 and the fourth pad 342 may form copper (Cu)-copper (Cu) bonding with each other.

[0130] An etching process may be performed on the second rear surface 202b (S420) to reduce the thickness of the second substrate 202. For example, the etching process on the second rear surface 202b may be performed until the sacrificial pattern 272 is exposed.

[0131] 25 to 27 and 28, the sacrificial pattern 272 may be removed (S430). For example, the sacrificial pattern 272 may be selectively removed by an etching material having an etching selectivity with respect to the sacrificial pattern 272. When the sacrificial pattern 272 is removed, a hole 272h may be formed. The hole 272h may expose one of the pixel gate electrode 213 of the source follower transistor and the pixel source / drain region 211 of the dual conversion gain transistor.

[0132] 25 and 29, a second insulating layer 222, a second conductive line 230, a second pad 262, and an intermediate via 530 may be formed on the second back surface 202b (S440). For example, after forming a portion of the second insulating layer 222 on the second back surface 202b, a second vertical conductive line 232 may be formed penetrating a portion of the second insulating layer. A second horizontal conductive line 234 extending in the first direction D1 or the second direction D2 may be formed on a portion of the second insulating layer 222. The process of forming another portion of the second insulating layer 222 on a portion of the second insulating layer 222 to cover the second horizontal conductive line 234 may be repeated. A second vertical conductive line 232 may be formed in the region where the sacrificial pattern 272 is removed. The second vertical conductive line 232 may be electrically connected to the pixel gate electrode 213 of the source follower transistor and one of the pixel source / drain regions 211 on one of the dual conversion gain transistors. A second pad 262 may be formed on the second vertical conductive line 232 disposed furthest from the second front surface 202a.

[0133] Before the second horizontal conductive line 234 immediately adjacent to the second rear surface 202b is formed, an intermediate via 530 penetrating the second substrate 202 may be formed in the pad area PDA. For example, the intermediate via 530 may be formed by forming a hole penetrating a portion of the second insulating layer 222, the second substrate 202, and a portion of the third insulating layer 242, and then filling the hole with an electrically conductive material. The hole may expose the third horizontal conductive line 254 immediately adjacent to the second front surface 202a. In one example, an insulating film may be formed on a side of the intermediate via 530. The intermediate via 530 may be electrically connected to the second horizontal conductive line 234 immediately adjacent to the second rear surface 202b and the third horizontal conductive line 254 immediately adjacent to the second front surface 202a.

[0134] Figure 30 is a flow chart for explaining a method for manufacturing the bonded first to third layers of Figure 10. Figure 31 is a diagram for explaining the manufacturing method of Figure 30. For ease of explanation, the contents that are substantially the same as those described with reference to Figure 10 will not be described.

[0135] 30 and 31, the first layer 100 and the second layer 200 may be bonded together such that the first front surface 102a and the second rear surface 202b face each other. The first pad 162 and the second pad 262 may form copper (Cu)-copper (Cu) bonding with each other (S510).

[0136] An etching process may be performed on the first rear surface 102b (S520) to reduce the thickness of the first substrate 102. For example, the etching process on the first rear surface 102b may be performed until the first substrate 102 has a desired thickness.

[0137] 30 and 10, a main via 520, a signal pad 510, a color filter 132, and a microlens 134 may be formed (S530). The main via 520 may be formed to penetrate the first substrate 102 in the pad area PDA. For example, the main via 520 may be formed by forming a hole penetrating the first substrate 102 and a portion of the first insulating layer 142, and then filling the hole with an electrically conductive material. The hole may expose the first horizontal conductive line 154 immediately adjacent to the first front surface 102a. In one example, an insulating film may be formed on a side of the main via 520. The main via 520 may be electrically connected to the first horizontal conductive line 154 immediately adjacent to the first front surface 102a.

[0138] The signal pad 510 may be formed on the main via 520. In one example, the signal pad 510 may form a single structure with the main via 520. For example, the signal pad 510 may be formed by forming an electrically conductive material layer on the first back surface 102b and then patterning the electrically conductive material layer when forming the main via 520.

[0139] A color filter 132 and a microlens 134 may be formed on the first rear surface 102b. The color filter 132 and the microlens 134 may be substantially the same as the color filter 132 and the microlens 134 described with reference to FIGS.

[0140] The above is a specific embodiment for carrying out the present invention. In addition to the above-described embodiment, the present invention also includes embodiments that can be simply modified or easily modified. The present invention also includes techniques that can be easily modified and carried out using the embodiment. Therefore, the scope of the present invention is not limited to the above-described embodiment, but should be defined by not only the claims described below, but also equivalents to the claims of the present invention. [Explanation of symbols]

[0141] 10. Image Sensor 100 1st layer 102 First board 104 First element isolation film 106 Pixel separation membrane 108 Photoelectric conversion area 110 Floating Diffusion Region 112 Transfer gate electrode 114 Transfer gate insulating film 132 Color Filter 134 Microlens 142 First insulating layer 150 First Conductive Line 162 1st Pad 200 2nd layer 202 Second board 204 Second element isolation film 210 pixel transistor 211 pixel source / drain area 213 Pixel gate electrode 214 Pixel gate insulating film 215 pixel channel area 216 pixel spacer 222 Second insulating layer 230 Second conductive line 242 Third insulating layer 250 3rd Conductive Line 262 2nd Pad

Claims

1. 1. An image sensor comprising a first layer and a second layer bonded to the first layer, the first layer includes a first substrate having a first front surface and a first back surface, a floating diffusion region formed in the first substrate, a first pad, and a first conductive line provided between the floating diffusion region and the first pad; the second layer includes a second substrate having a second front surface and a second rear surface, pixel transistors formed on the second substrate, a second pad, and a second conductive line provided between any one of the pixel transistors and the second pad; The second conductive line passes through the second substrate and is electrically connected to a lower portion of the pixel transistor.

2. The second conductive line is a vertical conductive line extending along a direction parallel to a stacking direction of the first layer and the second layer; a horizontal conductive line extending along a direction perpendicular to the vertical conductive line; 2. The image sensor of claim 1, wherein the vertical conductive line immediately adjacent the one of the pixel transistors passes through the second substrate.

3. The image sensor of claim 1 , wherein the second conductive line is electrically connected to the gate electrode of any one of the pixel transistors.

4. The image sensor of claim 1 , wherein the second conductive line is electrically connected to the drain region of any one of the pixel transistors.

5. the second conductive line includes a vertical conductive line extending along a direction parallel to a stacking direction of the first layer and the second layer, and a horizontal conductive line extending along a direction perpendicular to the vertical conductive line; The vertical conductive lines are a first vertical conductive line passing through the second substrate and electrically connected to any one of the gate electrodes of the pixel transistors; a second vertical conductive line passing through the second substrate and electrically connected to another drain region of the pixel transistor; 2. The image sensor of claim 1, wherein the first vertical conductive line and the second vertical conductive line are electrically connected to each other by a horizontal conductive line.

6. In an image sensor including a pixel array in which a plurality of pixels are arranged, The plurality of pixels include a first pixel and a second pixel arranged adjacent to each other, Each of the first pixel and the second pixel is a first layer and a second layer bonded to the first layer; the first layer includes a first substrate having a first front surface and a first back surface, a floating diffusion region formed in the first substrate, a first pad, and a first conductive line provided between the floating diffusion region and the first pad; the second layer includes a second substrate having a second front surface and a second rear surface, pixel transistors formed on the second substrate, a second pad, and a second conductive line provided between any one of the pixel transistors and the second pad; The second conductive line passes through the second substrate and is electrically connected to a lower portion of the pixel transistor.

7. 7. The image sensor of claim 6, wherein the floating diffusion region of the first pixel and the floating diffusion region of the second pixel are electrically connected to the same first pad.

8. The image sensor of claim 6 , wherein the floating diffusion region of the first pixel and the floating diffusion region of the second pixel are electrically connected to different first pads.

9. The first conductive line is a vertical conductive line extending along a direction parallel to a stacking direction of the first layer and the second layer; a horizontal conductive line extending along a direction perpendicular to the vertical conductive line; The vertical conductive lines are a first vertical conductive line electrically connected to the floating diffusion region of the first pixel; a second vertical conductive line electrically connected to the floating diffusion region of the second pixel; 7. The image sensor of claim 6, wherein the first vertical conductive line and the second vertical conductive line are electrically connected to a same horizontal conductive line.

10. In an image sensor including a pixel array region and a pad region, each of the pixel array region and the pad region includes a first layer and a second layer bonded to the first layer; In the pixel array region, the first layer includes a first substrate having a first front surface and a first back surface, a floating diffusion region formed in the first substrate, a first pad, and a first conductive line provided between the floating diffusion region and the first pad; the second layer includes a second substrate having a second front surface and a second rear surface, pixel transistors formed on the second substrate, a second pad, and a second conductive line provided between any one of the pixel transistors and the second pad, the second conductive line penetrating the second substrate and electrically connected to a lower portion of the pixel transistor; In the pad region, the first layer includes a main via penetrating the first substrate and a signal pad provided on the main via.

Images