Nonvolatile semiconductor memory device

Abstract

To provide a nonvolatile semiconductor memory device or the like capable of narrowing a distribution width of a cell voltage while suppressing write delay.SOLUTION: A nonvolatile semiconductor memory device 1 has a plurality of gate lines, a plurality of bit lines intersecting with the plurality of gate lines, and a plurality of memory cells connected in correspondence with intersections between the gate lines and the bit lines. The plurality of memory cells are connected to a selected one of the plurality of gate lines by different bit lines, and a plurality of write bit line current or voltage control circuits 100, 100b are provided to control each bit line current in order to simultaneously write the plurality of memory cells.SELECTED DRAWING: Figure 10

Description

[Technical field]

[0001] The present disclosure relates to a non-volatile semiconductor memory device. [Background technology]

[0002] Flash memory is a non-volatile memory that uses a semiconductor element called a floating gate MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and records data by storing electrons in the floating gate.

[0003] Multi-level technology, which allows for larger flash memory capacities, has been attracting attention. In general multi-level programming, data is written to many cells in the same row at the same time. Since each memory cell has physical variations, the cell voltage may have a programming distribution width. In multi-level cells (MLC) and the like, controlling this programming distribution width is important from the standpoint of reliability, etc.

[0004] The mainstream method for controlling the write speed is to gradually increase the gate voltage. This is because, if other conditions are the same, Vtm increases along with the gate voltage, there is no load current, so it is easier to control compared to SL / BL, and the voltage range is large, making it easier to control. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2023-92938 A Summary of the Invention [Problem to be solved by the invention]

[0006] However, in the conventional technology, due to a lack of operating margin (i.e., write / erase window), a problem occurs in that, for example, when an attempt is made to narrow the distribution width of the write intermediate level of a multi-level cell (MLC) or the like by reducing the increase width of the pulse voltage, the write time becomes slow.

[0007] The present disclosure has been made to solve such problems, and has an object to provide a nonvolatile semiconductor memory device and the like that is capable of narrowing the distribution width of cell voltages while suppressing write delays.

[0008] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0009] A non-volatile semiconductor memory device according to an embodiment of the present invention includes: A plurality of gate lines; a plurality of bit lines intersecting the plurality of gate lines; a plurality of memory cells connected to corresponding intersections of the gate lines and the bit lines, a plurality of memory cells are connected to a selected one of the plurality of gate lines by different bit lines; In order to simultaneously write to the plurality of memory cells, a plurality of write bit line current or voltage control circuits are provided for controlling the respective bit line currents. Effect of the Invention

[0010] According to one embodiment, it is possible to provide a non-volatile semiconductor memory device or the like that is capable of narrowing the distribution width of cell voltages while suppressing write delays. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is a distribution diagram of a cell current for explaining a data write operation of a flash memory based on a reference current type. [Diagram 2]FIG. 2 shows a cross-sectional structure of a cell of an exemplary memory chip. [Diagram 3] FIG. 3 is a diagram for explaining general multi-value writing. [Figure 4] FIG. 4 is a circuit diagram for explaining general multi-value writing. [Diagram 5] FIG. 5 is a graph for explaining general multi-value writing. [Figure 6] FIG. 6 is a graph for explaining general multi-value writing. [Figure 7] FIG. 7 is a circuit diagram for explaining multi-value writing according to the embodiment. [Figure 8] FIG. 8 is a graph for explaining multi-value writing according to the embodiment. [Figure 9] FIG. 9 is a diagram illustrating an electronic device including a nonvolatile semiconductor memory device according to this embodiment. [Figure 10] FIG. 10 is a circuit diagram including a write bit line current control circuit according to the present embodiment. [Figure 11] FIG. 11 is a circuit diagram showing details of the write bit line current control circuit according to the present embodiment. [Figure 12] FIG. 12 is a graph illustrating a write operation at the beginning of writing. [Figure 13] FIG. 13 is a circuit diagram for explaining a write operation at the beginning of writing. [Figure 14] FIG. 14 is a graph illustrating a write operation in the middle of writing. [Figure 15] FIG. 15 is a circuit diagram for explaining a write operation in the middle of writing. [Figure 16] FIG. 16 is a graph illustrating a write operation at the end of the write operation. [Figure 17] FIG. 17 is a circuit diagram for explaining a write operation at the final stage of writing. [Figure 18] FIG. 18 is a flowchart of distribution narrowing writing according to this embodiment. [Figure 19] FIG. 19 is a diagram for explaining general multi-value writing according to another embodiment. [Figure 20]FIG. 20 is a graph illustrating a write operation according to another embodiment. [Figure 21] FIG. 21 is a circuit diagram illustrating a write operation according to another embodiment. [Figure 22] FIG. 22 is a circuit diagram illustrating a write operation according to another embodiment. [Figure 23] FIG. 23 is a circuit diagram including a write bit line voltage control circuit according to another embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] For clarity of explanation, the following description and drawings are omitted and simplified as appropriate. In addition, in each drawing, the same elements are given the same reference numerals, and duplicate explanations are omitted as necessary.

[0013] First, an overview of flash memory will be given. Flash memory is a storage medium that can read and write data, and there are various types, from built-in to portable. Types of flash memory include USB memory, SD cards, memory cards, memory sticks, and solid-state drives (SSDs). Flash memory is classified into NAND type and NOR type, depending on the difference in the electrical circuit structure. Flash memory has more than billions of cells, and each cell stores data "0" or "1". The smaller the cell size and the more cells there are in a memory chip, the larger the capacity of the storage medium.

[0014] In a flash memory memory cell, in the erased state where charge has been released from the floating gate, the threshold voltage (Vt) becomes negative and the stored data becomes "1". On the other hand, in the erased state, when a write operation is performed to inject charge into the floating gate, the memory cell enters the written state. In the written state, the threshold voltage (Vt) of the memory cell becomes positive and the stored data becomes "0". In other words, the threshold voltage (Vt) of a memory cell composed of a field effect transistor in the erased state is lower than the threshold voltage in the written state.

[0015] When a read voltage (positive voltage) is input to the gate of the memory cell to be read, it generates a cell current (also called source-drain current) that depends on the threshold voltage. For the same memory cell, the cell current in the erased state is greater than the cell current in the written state, where the threshold voltage rises due to charge injection (see Figure 1). The sense amplifier compares the reference current with the cell current to read out the data "1" or "0".

[0016] FIG. 1 is a cell current distribution diagram for explaining the data write operation by the reference current type of flash memory. FIG. 1 shows the cell current distribution curve when the stored data is "0" and the cell current distribution curve when the stored data is "1" for all the memory cells constituting the nonvolatile memory device. The cell current distribution curve when the stored data is "1" is also called the erased cell distribution curve, and the cell current distribution curve when the stored data is "0" is also called the written cell distribution curve. In the reference current read type, it is required to set the reference current in a current region where the erased cell distribution curve and the written cell distribution curve do not overlap. This is because if a current region occurs where the erased cell distribution curve and the written cell distribution curve overlap, erroneous determination of stored data may occur.

[0017] 2 shows a cross-sectional structure of a cell of an exemplary memory chip, and is a diagram illustrating typical potential arrangements during reading, writing, and erasing. The cell includes a transistor structure made of an n-type semiconductor and a p-type semiconductor, a gate structure, and a tunnel oxide film sandwiched between the transistor structure and the gate structure. The gate structure has a control gate (CG), a floating gate (FG), and a memory gate (MG).

[0018] In normal programming, for example, when performing SSI (Source Side Injection) programming as in FMONOS (Flash Metal Oxide Nitride Oxide Semiconductor) cells, programming is performed with the potential arrangement shown in the middle diagram of Figure 2. That is, the MG voltage is set to a high voltage (for example, 10.5V), and the CG voltage is set to 1.0V. The source voltage is set to 4.5V, and the drain voltage is set to 0.7V. With this potential arrangement, electrons flowing out from the source (S) penetrate the tunnel oxide film and are stored in the floating gate FG. In this way, in the programming state, the threshold voltage (Vt) becomes positive, and the stored data becomes "0". In MLC (Multi-Level Cell) and the like, there are cases where it is desired to control programming more precisely (by gradually changing the MG voltage) due to the demand for reliability.

[0019] On the other hand, when erasing data, the drain voltage is set to 0 V, the source voltage to 7 V, and the MG voltage to -7 V. The high voltage applied to the source generates holes near the source by band-to-band tunneling, and the negative voltage of the MG pulls these holes into the floating gate FG, thereby offsetting the electrons in the floating gate FG.

[0020] Furthermore, during readout, the MG voltage is set to 0V and the CG voltage is set to a low voltage (1.5V). Additionally, the drain voltage is set to 1.5V. This allows the current flowing from the source to the drain to be detected. If electrons are stored in the floating gate FG, current does not flow easily, and the stored data is detected as "0". On the other hand, if there are no electrons in the floating gate FG, current flows easily, and the stored data is detected as "1".

[0021] Fig. 3 is a diagram for explaining general multi-level writing. The vertical axis indicates the drain current Ion flowing between the source and drain in Fig. 2. The left diagram of Fig. 3 shows the cell distribution in a single level cell (SLC), and the right diagram of Fig. 3 shows the cell distribution in a multi-level cell (MLC).

[0022] Single-level cell (SLC) is a type of NAND flash memory that stores one bit of data consisting of two values ​​in one memory element (memory cell). In the case of an erased cell, electrons are not stored in the floating gate FG, so a relatively high current flows. In the case of a written cell, electrons are stored in the floating gate FG, so a relatively low current flows. In SLC, the width of writing and erasing is determined by the relationship between the minimum value of the cell current in the distribution curve of the erased cell and the maximum value of the cell current in the distribution curve of the written cell, and the reliability such as the number of writes is determined. Even in SLC, if the written cell is too deep, the memory cell deteriorates significantly, so there are cases where it is desirable to narrow the width of the writing distribution to prevent cell deterioration.

[0023] On the other hand, a multi-level cell (MLC) is a method of storing multi-bit data consisting of three or more values ​​in one memory element (memory cell). In the example of FIG. 3, there are four distributions. In this MLC, four states (i.e., two bits) of 00, 01, 10, and 11 can be stored. Specifically, in the 00 erase cell, electrons are not accumulated in the floating gate FG, so a relatively high current flows. On the other hand, in the 10 write cell, 01 write cell, and 00 write cell, electrons are gradually accumulated in the floating gate FG in this order, so a relatively low current flows. In the MLC, if the cell Vt distribution between the 00 write cell and the 11 erase cell becomes large, the cell write and erase window will become large as it is. Therefore, reliability and operational problems become large. In some embodiments, a quad level cell (QLC) or a triple level cell (TLC) may be used in multi-value writing, and the present disclosure is applicable.

[0024] FIG. 4 is a circuit diagram for explaining general multi-value writing. Vcg and Vsl are fixed potentials, and in this example, Vcg is 1.0 V and Vsl is 4.5 V. The Vmg potential is variable and can be gradually increased from 4.0 V to 10.5 V by a voltage source. Each Vbl is about 0.7 V, and Ibl is 1.66 uA.

[0025] For example, in the case of SLC, the data of a cell to be written is "0", and data that is not written (left erased) is "1". Writing "0" or "1" is controlled by the bit line write current. When writing to all cells (cells A, B, and C), a bit line current is passed through all cells as shown in Figure 4. In this case, the bit line voltage is approximately 0.7V. On the other hand, when not writing to an individual cell, the bit line current to that individual cell is stopped.

[0026] FIG. 5 is a graph for explaining general multi-value writing. As shown in FIG. 4, a write operation is performed by applying a predetermined Vmg pulse voltage and a predetermined write bit line current Ibl to a target memory cell for multiple cells (cells A, B, and C). As electrons accumulate in the floating gate FG, the cell voltage Vt gradually rises. The cell voltage Vt is the lower limit of the gate voltage through which the drain current flows, and is also called the "threshold voltage." After that, when the Vmg voltage (or reference current) is applied to each cell (cells A, B, and C) and a read is performed, it is possible to determine whether or not the write operation has been completed for each cell based on whether or not the drain current corresponding to the cell Vt verify level flows. This is called verify. Therefore, it is possible to determine whether or not the cell voltage exceeds the target cell Vt verify level for each cell. In FIG. 5, a verify period indicated as (Verify) is shown between the Vmg pulse voltages. If the cell Vt has not reached the verify level, the Vmg pulse voltage is increased by a predetermined amount and applied, and then a verify operation is performed to determine whether or not the cell voltage Vt has reached the verify level indicating the end of the write operation. In this manner, the Vmg pulse voltage is gradually increased and the verify operation is repeated to perform multi-value writing.

[0027] In the case of MLC, the same write level (e.g., 10) may be written to all cells (cells A, B, C). In this case, as shown in FIG. 5, the verify level indicating the end of writing is the same for all cells (cells A, B, C). Also, different write levels (e.g., 10 for cell A, 01 for cell B, and 00 for cell C) may be written to each cell (cells A, B, C). In this case, the verify level indicating the end of writing may be different for each cell (cells A, B, C).

[0028] As shown in Fig. 6, in order to reduce the distribution of cell Vt, the increase in the Vmg pulse voltage must be reduced. However, as a result, the number of repetitions of programming and retry increases, and it takes time for the cell Vt (for the cell where programming is finally completed (cell A in Fig. 6)) to reach the verify level, delaying multi-value programming.

[0029] Generally, in multi-level programming, many cells on the same word line are programmed simultaneously. Since there is variation in the programming speed and initial position of each cell, the cell voltage Vt has a certain distribution width. Among the many cells programmed simultaneously, programming is terminated in order from the cell whose cell voltage Vt reaches the verify level. In particular, if the increase width of the Vmg pulse voltage is reduced in order to reduce the distribution of cell Vt, the cell that finishes programming last (cell A in FIG. 6) among the many cells programmed simultaneously will be significantly delayed.

[0030] By narrowing the distribution width of the cell voltage Vt, it is possible to suppress the deterioration of the memory cells, and by storing a larger number of bits in the memory, it is possible to increase the amount of information.

[0031] As described above, in the conventional technology, due to a lack of operating margin (program / erase window), there is a problem that the programming time becomes slow when an attempt is made to narrow the distribution width of the MLC programming intermediate level.

[0032] FIG. 7 is a circuit diagram for explaining multi-value writing according to the embodiment. In this embodiment, the current flowing through each bit line bl is controlled to a plurality of levels (two levels in this example, i.e., 1.66uA or 0.83uA). Since the Vmg voltage is common to the word lines wl in the row direction, it is not possible to apply different voltages to each cell (to each of cells A, B, and C in FIG. 7). Therefore, in this embodiment, by adjusting the current flowing through each bit line bl to a plurality of levels, it is possible to apply different voltages to each cell (to each of cells A, B, and C in FIG. 7). As a result, in the MLC, the current Ibl is reduced and the write speed is slowed down for cells other than the cell whose cell Vt has exceeded the verify level indicating the end of writing. As a result, the write distribution width of the cell voltage can be narrowed.

[0033] FIG. 8 is a graph for explaining multi-value writing according to the embodiment. In this embodiment, a different verify level (verify level B in FIG. 8) is provided that is lower than the verify level (verify level A in FIG. 8) of the cell Vt that indicates the end of writing. This verify level B is used to control the current Ibl that flows through each bit line bl. Specifically, a Vmg voltage (or a reference current) corresponding to the verify level A / B of the cell voltage Vt is determined in advance. When the predetermined Vmg voltage (or reference current) is applied and read, it can be determined whether the target cell Vt level is exceeded. That is, if a cell voltage corresponding to the verify level A or B is applied to the cell and current value data corresponding to the verify level A or B can be read, it can be determined that the target cell Vt level is exceeded. On the other hand, if a cell voltage corresponding to the verify level A or B is applied to the cell and current value data corresponding to the verify level A or B cannot be read, it can be determined that the target cell Vt level is not exceeded.

[0034] Therefore, the Vmg pulse voltage is gradually increased, and after it reaches the Vmg pulse voltage at which the cell Vt reaches the verify level B, the cell voltage is applied to the cell and data is read. If the desired current value data can be read, the current Ibl is reduced (from 1.66uA to 0.83uA). This makes it possible to slow down the write speed and narrow the distribution width of the cell voltage. For example, if it is desired to halve the distribution width, the terminal write speed is halved and the number of writes increases by a maximum of one, but since the number of retries is several tens in total (more than 20 in the design this time), this does not make a big difference. In other words, it is possible to suppress the delay in the write time in the MLC while narrowing the distribution width. The change in the write speed at this time is performed by the bit line current Ibl. Although the bit line does not allow for many levels of level adjustment, the current can be controlled if the resolution is roughly at the first half of a single digit level. In addition, since the current can be controlled for each bit line, there is no need to start writing again from the beginning.

[0035] FIG. 9 shows an electronic device 3 including a non-volatile semiconductor memory device 1. The electronic device 3 includes at least one control circuit 5 that controls the operation of the entire circuit. The processing circuit in the control circuit 5 can be based on one or more microprocessors, application processors, microcontrollers, digital signal processors, baseband processors, power management units, audio chips, application specific integrated circuits, etc. Specifically, the processing circuit can control a Y-selector, which will be described later, instruct (write Flags 1 and 2) the gate driver circuit of the write bit line current or voltage control circuit, control a voltage source, etc. The control circuit can be used to run software such as an operating system or an application on the device.

[0036] FIG. 10 is a circuit diagram illustrating a memory device according to the embodiment. The nonvolatile semiconductor memory device 1, which is a flash memory, includes a memory cell array 10, a plurality of Y-selectors 50, a plurality of write bit line current control circuits 100, and a gate driver circuit 30. Each write bit line current control circuit 100 is provided corresponding to each Y-selector 50.

[0037] The Y-selector 50 receives an externally input bit line address signal (from the control circuit 5) and selects one write or read bit line from among a plurality of write or read word lines. The write bit line current control circuit 100 controls the write word line current supplied to the bit line selected by the Y-selector 50. The gate driver circuit 30 is configured to turn on write Flag1 or write Flag2 for each transistor of the write bit line current control circuit 100.

[0038] FIG. 11 is an enlarged view of the write bit line current control circuit 100. As shown in FIG. The bit line bl coupled to the Y selector 50 is connected to transistors Tr3 and Tr4 for a current (Inor in FIG. 11) during normal writing. Also, the bit line bl coupled to the Y selector 50 is connected to transistors Tr5 and Tr6 for a current during normal writing. The transistors Tr3 and Tr4 are parallel to the transistors Tr5 and Tr6. The gate electrode of the transistor Tr3 and the gate electrode of the transistor Tr5 are connected to each other. During normal writing, when a gate voltage exceeding the threshold voltage is applied as the write Flag1, a normal writing current Inor (Ibl=1.66 uA) flows through the transistors Tr3, Tr4, Tr5, and Tr6.

[0039] On the other hand, the bit line bl coupled to the Y selector 50 is connected to transistors Tr1 and Tr2 for a current during slow writing (Ilow in FIG. 11). During slow writing, when a gate voltage exceeding the threshold voltage is applied as the write Flag2, a slow writing current Ilow (Ibl=0.83uA) flows through the transistors Tr1 and Tr2. The slow writing current Ilow (Ibl=0.83uA) can be half of the normal writing current Inor (Ibl=1.66uA).

[0040] Although not shown in FIG. 10, a voltage source is provided for applying the Vmg voltage by increasing it step by step. The gate driver circuit 30 may be implemented as a part of an integrated circuit. Each Vbl is about 0.7V, and Ibl is 1.66uA. The gate lines of the transistors Tr2 and Tr6 of each write bit line current control circuit 100 are connected to a transistor Tr7.

[0041] FIG. 12 is a graph illustrating a write operation in the initial stage of writing, and FIG. 13 is a circuit diagram illustrating the write operation in the initial stage of writing. At the beginning of writing (i.e., until the cell voltage Vt exceeds the verify level B), the Vmg voltage is increased stepwise, and the cell is written with the Ibl current (i.e., 1.66 uA) using the current source for normal writing. As shown in the circuit diagram of Fig. 13, for all of cells A, B, and C, when a gate voltage exceeding the threshold voltage is applied as write Flag1 during normal writing, each write bit line current control circuit 100 controls transistors Tr3, Tr4, Tr5, and Tr6 to pass a normal write current Inor (Ibl = 1.66 uA).

[0042] FIG. 14 is a graph for explaining a write operation in the middle of writing, and FIG. 15 is a circuit diagram for explaining a write operation in the middle of writing. In the middle of the write operation, the Vmg voltage is increased stepwise, and a cell (cell B in FIG. 14) appears whose cell voltage Vt exceeds the verify level B. Note that the cell voltage Vt of cell C exceeds the verify level A, so the write operation ends. As shown in the circuit diagram of FIG. 15, for cell A, when a gate voltage exceeding the threshold voltage is applied as write Flag1 during normal write operation, the write bit line current control circuit 100 controls transistors Tr3, Tr4, and transistors Tr5 and Tr6 to pass a normal write current Inor (Ibl=1.66 uA). For cell B, when a gate voltage exceeding the threshold voltage is applied as write Flag2 during slow write operation, the write bit line current control circuit 100 controls transistors Tr1 and Tr2 to pass a slow write current Ilow (Ibl=0.83 uA). As for the cell C, since the writing has been completed, the write bit line current control circuit 100 does not supply the normal write current Inor (Ibl=1.66 uA) or the slow write current Ilow (Ibl=0.83 uA).

[0043] FIG. 16 is a graph illustrating a write operation in the final stage of writing, and FIG. 17 is a circuit diagram illustrating the write operation in the final stage of writing. At the end of the write operation, the Vmg voltage is increased stepwise, and the cell voltages Vt of almost all the cells exceed the verify level B (FIG. 16). As shown in FIG. 17, for cell A, when a gate voltage exceeding the threshold voltage is applied as write Flag2 during the slow write operation, the write bit line current control circuit 100 controls the transistors Tr1 and Tr2 to pass a slow write current Ilow (Ibl=0.83uA). For cells B and C, the cell voltages Vt of cells B and C exceed the verify level A and the write operation is completed, so that each write bit line current control circuit 100 passes neither the normal write current Inor (Ibl=1.66uA) nor the slow write current Ilow (Ibl=0.83uA).

[0044] When the cell voltages of all the cells (cells A, B, and C) exceed the verify level A, all the write bit line current control circuits 100 stop the current, and the write operation ends.

[0045] FIG. 18 is a flowchart of distribution narrowing writing. This flow chart can be executed by at least one control circuit 5 (FIG. 9) that controls the operation of the entire circuit. The control circuit 5 receives data to be written to each memory cell from the outside (step S101). The control circuit 5 checks whether the write flag 1 is H (when writing) or L (when not writing) for each memory cell, and whether the write flag 2 is H (when writing) or L (when not writing) (step S102). If the write flag 1 is H (when writing) and the write flag 2 is H (when writing) (NO in step S102), the control circuit 5 checks whether the cell voltage exceeds the verify level A based on the read result of each memory cell (step S104). If the cell voltage does not exceed the verify level A (NO in step S105), the control circuit 5 checks whether the cell voltage exceeds the verify level B based on the read result of the cell (step S106). On the other hand, if the cell voltage exceeds the verify level A (YES in step S105), the control circuit 5 sets both write flags 1 and 2 to L (non-write) (step S1051), thereby stopping writing to the cell.

[0046] If the cell voltage exceeds level B (YES in step S107), the write flag 2 becomes H (when writing) and the write flag 1 becomes L (when not writing), and the control circuit 5 causes the write bit line current control circuit 100 to pass a slow write current to the bit line to the corresponding cell, and executes a slow write (step S108). On the other hand, if the cell voltage does not exceed level B (NO in step S107), the write flag 1 becomes H (when writing), and the control circuit 5 causes the write bit line current control circuit 100 to pass a normal write current to the bit line to the corresponding cell, and executes a normal write (step S109). If the write data 1 / 2 is L (when not writing) in all IOs (YES in step S110), the process ends. On the other hand, if the write data 1 / 2 is not L (non-write) in all IOs (that is, if any of them is H (write)) (NO in step S110), the write operation is executed (step S111), and the processes from step S102 to step S110 are repeated.

[0047] The above-described embodiment can narrow the distribution of cell voltage Vt. Furthermore, the present disclosure can be used for high-speed writing, as described below. Also, the memory cells can include at least one of a multi-level cell (MLC), a triple-level cell (TLC), and a quad-level cell (QLC).

[0048] Other embodiments FIG. 19 is a diagram for explaining general multi-value writing according to another embodiment. In the case of a typical MLC, multiple cell voltage levels are written simultaneously, so the write start voltage is started according to distribution B corresponding to verify level B, which is lower than verify level A, which indicates the end of writing. Since the Vmg voltage needs to start from a relatively low value, it takes a long time until writing of distribution A, which corresponds to verify level A, which indicates the end of writing, is completed.

[0049] Therefore, in this embodiment, the same write bit line current control circuit 100 as in the above-described embodiment is used to control the write current Ibl for each target distribution corresponding to each memory cell, thereby realizing a high-speed write operation.

[0050] FIG. 20 is a graph illustrating a write operation according to another embodiment. For a cell corresponding to distribution A (e.g., cell A or cell C), a normal write current Inor (Ibl=1.66uA) is set to achieve a normal write speed. On the other hand, for a cell corresponding to distribution B (e.g., cell B) whose cell voltage level is lower than distribution A, a slow write current Inor (Ibl=0.83uA) is set to achieve a slow write speed. Distribution A may correspond to the 01 write cell in FIG. 3, and distribution B may correspond to the 10 write cell in FIG. 3, for example.

[0051] This allows the Vmg voltage at the start of writing to be set relatively higher than in the case of FIG. 19, and the number of write retries can be reduced, thereby making it possible to speed up the write operation.

[0052] FIG. 21 is a circuit diagram illustrating a write operation according to this embodiment. The circuit diagram in FIG. 21 is similar to the circuit diagram in FIG. 10 etc., but instead of changing the write speed midway as in the above-mentioned embodiment, in this embodiment, either a normal write current or a slow write current can be selected according to a target distribution that differs for each memory cell.

[0053] FIG. 22 is a circuit diagram illustrating a write operation according to this embodiment. For cell A or cell C corresponding to distribution A, a normal write current Inor (Ibl = 1.66uA) is set to obtain a normal write speed. On the other hand, for cell B corresponding to distribution B, which has a lower cell voltage level than distribution A, a slow write current Inor (Ibl = 0.83uA) is set to obtain a slow write speed.

[0054] 22, for cell A, the write bit line current control circuit 100 controls the transistors Tr3, Tr4, Tr5, and Tr6 to pass a normal write current Inor (Ibl=1.66 uA) when a gate voltage exceeding the threshold voltage is applied as normal writing corresponding to distribution A. Similarly, for cell C, the write bit line current control circuit 100 controls the transistors Tr3, Tr4, Tr5, and Tr6 to pass a normal write current Inor (Ibl=1.66 uA) when a gate voltage exceeding the threshold voltage is applied during normal writing corresponding to distribution A.

[0055] On the other hand, for cell B, when a gate voltage exceeding the threshold voltage is applied as a slow write corresponding to distribution B, the write bit line current control circuit 100 controls transistors Tr1 and Tr2 to pass a slow write current Ilow (Ibl=0.83 uA).

[0056] As shown in Fig. 20, the same Vmg voltage is applied to cells A, B, and C in a stepwise manner. In this case, since the initial Vmg voltage can be set higher than that in the comparative example of Fig. 19, the write operation can be completed in a short time.

[0057] In some embodiments, a normal write current corresponding to target distribution A may be applied to cell A, a medium speed write current corresponding to target distribution B may be applied to cell B, and a low speed write current corresponding to target distribution C may be applied to cell C. In this case, the write bit line current control circuit may have a circuit for normal write current, a circuit for medium speed write current, and a circuit for low speed write current arranged in parallel. In this case, the circuit for normal write current may have at least three transistors arranged in parallel. The circuit for medium speed write current may have at least two transistors arranged in parallel. The circuit for low speed write current may have at least one transistor arranged in parallel. In this way, as can be understood by those skilled in the art, the present disclosure may also be applied to nbit (n is any integer) MLC cells, i.e., TLC, QLC, etc.

[0058] FIG. 23 is a circuit diagram including a write bit line voltage control circuit according to another embodiment. The write bit line current control circuit 100 described above with reference to Fig. 10 etc. can be replaced with a write bit line voltage control circuit 100b shown in Fig. 23. The basic operating principle is similar to that of the embodiment described with reference to Fig. 10 etc.

[0059] A bit line bl coupled to the Y selector 50 is connected to a transistor Tr2 for a current (Inor in FIG. 11) during normal writing. A write voltage V1 is applied to the source electrode of the transistor Tr2. During normal writing, when a gate voltage exceeding the threshold voltage is applied as the write Flag1, a normal write current Inor flows through the transistor Tr2.

[0060] On the other hand, a transistor Tr1 for a current (Ilow in FIG. 11) during slow writing is connected to the bit line bl coupled to the Y selector 50. A write voltage V2 is applied to the source electrode of the transistor Tr1. Here, the write bit line voltage control circuit 100b controls the write voltage V1 for normal writing to be smaller than the write voltage V2 for slow writing. During slow writing, when a gate voltage exceeding the threshold voltage is applied as the write Flag2, a slow writing current Ilow flows through the transistor Tr2.

[0061] According to some embodiments, a non-volatile semiconductor memory device may be provided. The non-volatile semiconductor memory device includes a plurality of gate lines, a plurality of bit lines intersecting the plurality of gate lines, and a plurality of memory cells connected to corresponding intersections of the gate lines and the bit lines. The non-volatile semiconductor memory device includes a plurality of write bit line current or voltage control circuits that control each bit line current in order to simultaneously write the plurality of memory cells to a selected one of the plurality of gate lines through different bit lines. In another embodiment, the non-volatile semiconductor memory device may be configured to have a plurality of cell voltage verify levels for checking the state of the cell for each of a plurality of target cell voltage distributions, and the write bit line current or voltage control circuit may be configured to control the write speed with a plurality of bit line currents selected based on a plurality of gate voltages and a read result corresponding to the verify level. In addition, for the target cell voltage distribution, a first cell voltage verify level indicating the end of cell writing and a second cell voltage verify level lower than the first cell voltage verify level are provided, and the write bit line current or voltage control circuit may be configured to control the write bit line current of the corresponding memory cell to a current lower than the normal current when it is determined from the read result of the corresponding memory cell that the cell voltage has exceeded the second cell voltage verify level.

[0062] In still another embodiment, the write bit line current control circuit 100 may include a first transistor Tr4 and a second transistor Tr6 connected in parallel to each other, each having a gate receiving a reference potential, for passing a first write bit line current, and a third transistor Tr2 having a gate receiving a reference potential and passing a second write bit line current smaller than the first write bit line current (see FIG. 11). The write bit line current control circuit 100 may further include a fourth transistor Tr3 and a fifth transistor Tr5 each having a gate receiving a write flag signal, connected in series with the first transistor Tr4 and the second transistor Tr6, respectively, and a sixth transistor Tr1 having a gate receiving a write flag signal and connected directly to the third transistor Tr2 (see FIG. 11).

[0063] The write bit line voltage control circuit 100b includes a first transistor Tr1 having a gate for receiving a first write flag signal and a source for receiving a write voltage, for passing a first write bit line current, and a second transistor Tr2 having a gate for receiving a second write flag signal and a source for receiving a write voltage, for passing a second write bit line current smaller than the first write bit line current, and the source potential V1 of the first transistor Tr1 may be controlled to be lower than the source potential V2 of the second transistor Tr2 (see FIG. 23).

[0064] In yet another embodiment, the device may include a first Y-selector that selects one of the multiple gate lines, a second Y-selector that selects one of the multiple gate lines, and a third Y-selector that selects one of the multiple gate lines, and may include a first write bit line current or voltage control circuit, a second write bit line current or voltage control circuit, and a third write bit line current or voltage control circuit corresponding to the first Y-selector, the second Y-selector, and the third Y-selector.

[0065] A pulse voltage is applied to the gate electrodes of the memory cells through the gate line a plurality of times, the pulse voltage is applied so as to increase stepwise, and a verify period during which verify is performed may be provided between the applications of the pulse voltage a plurality of times. The memory cells may be at least one of a multi-level cell (MLC), a triple-level cell (TLC), and a quad-level cell (QLC).

[0066] The invention made by the inventor has been specifically described above based on the embodiments, but the present invention is not limited to the embodiments already described, and various modifications are possible without departing from the gist of the invention. [Explanation of symbols]

[0067] 1. Non-volatile semiconductor memory device 3 Electronic equipment 5 Control circuit 10 Memory Cell Array 30 Gate driver circuit 50 Y Selector 100 Write bit line current control circuit 100b Write bit line voltage control circuit

Claims

1. A plurality of gate lines; a plurality of bit lines intersecting the plurality of gate lines; a plurality of memory cells connected to corresponding intersections of the gate lines and the bit lines, a plurality of memory cells are connected to a selected one of the plurality of gate lines by different bit lines; a plurality of write bit line current or voltage control circuits for controlling respective bit line currents in order to simultaneously write the plurality of memory cells; Non-volatile semiconductor memory device.

2. a plurality of cell voltage verify levels for verifying the state of the cells for each of a plurality of target cell voltage distributions; The write bit line current or voltage control circuit includes:

2. The nonvolatile semiconductor memory device according to claim 1, wherein a write speed is controlled by a plurality of bit line currents selected based on a plurality of gate voltages and a read result corresponding to said verify level.

3. For the target cell voltage distribution, a first cell voltage verify level indicating the end of programming of the cell; a second cell voltage verify level that is lower than the first cell voltage verify level; and is established, The write bit line current or voltage control circuit includes:

3. The non-volatile semiconductor memory device according to claim 2, configured to control a write bit line current of the corresponding memory cell to a current lower than a normal current when it is determined from the read result of the corresponding memory cell that the cell voltage has exceeded a verify level of the second cell voltage.

4. The write bit line current control circuit includes: a first transistor and a second transistor connected in parallel to each other, each having a gate receiving a reference potential, for conducting a first write bit line current; a third transistor having a gate receiving a reference potential and conducting a second write bit line current smaller than the first write bit line current; 4. The non-volatile semiconductor memory device according to claim 2.

5. 5. The nonvolatile semiconductor memory device according to claim 4, wherein the write bit line current control circuit includes a fourth transistor and a fifth transistor each having a gate for receiving a write flag signal and connected in series with the first transistor and the second transistor, respectively, and a sixth transistor having a gate for receiving a write flag signal and connected directly to the third transistor.

6. The write bit line voltage control circuit includes: a first transistor having a gate for receiving a first write flag signal and a source for receiving a write voltage, the first transistor being for conducting a first write bit line current; a second transistor having a gate for receiving a second write flag signal and a source for receiving a write voltage, the second transistor for conducting a second write bit line current less than the first write bit line current; 4. The nonvolatile semiconductor memory device according to claim 2, wherein a source potential of said first transistor is controlled to be lower than a source potential of said second transistor.

7. a pulse voltage is applied to the gate electrodes of the memory cells a plurality of times via the gate lines; The plurality of pulse voltages are configured to be applied so as to increase stepwise; 2. The nonvolatile semiconductor memory device according to claim 1, wherein a verify period in which verify is performed is provided between the applications of said pulse voltages a plurality of times.

8. The plurality of memory cells are n-bit (n is an arbitrary integer) multi-level cells (MLCs).

2. The non-volatile semiconductor memory device according to claim 1, wherein the cell is at least one of a triple level cell (TLC) and a quad level cell (QLC).

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