Liquid crystal display device

Abstract

To provide a new shift register.SOLUTION: One aspect of the invention comprises a transistor 101, a transistor 102, a transistor 103 and a transistor 104. A first terminal of the transistor 101 is connected to a wire 111, and a second terminal of the transistor 101 is connected to a wire 112. A first terminal of the transistor 102 is connected to a wire 113, and a second terminal of the transistor 102 is connected to the wire 112. A first terminal of the transistor 103 is connected to the wire 113, and a gate of the transistor 103 is connected to the wire 111 or the wire 119. A first terminal of the transistor 104 is connected to a second terminal of the transistor 103 and a second terminal of the transistor 104 is connected to a gate of the transistor 101, and a gate of the transistor 104 is connected to a gate of the transistor 102.SELECTED DRAWING: Figure 10

Description

[Technical field]

[0001] One embodiment of the present invention relates to a semiconductor device, a display device, a display module, and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field relates to an article, a method, or a manufacturing method. is a process, machine, manufacture, or composition of matter. Therefore, one aspect of the present invention disclosed in the present specification more specifically relates to a The technical fields of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, and the like. One example is a driving method or a manufacturing method thereof. [Background technology]

[0003] In recent years, the development of shift registers consisting of transistors of the same polarity has progressed. Patent Documents 1 and 2 disclose technologies related to such shift registers. As shown. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2004-103226 A [Patent Document 2] JP 2005-050502 A Summary of the Invention [Problem to be solved by the invention]

[0005] In the shift register shown in FIG. 7 of Patent Document 1, transistor M2 is turned on. However, when GOUT[N-1] is at a high level, the voltage VOFF is output. During this period, the transistor M2 is turned off, and the voltage VOFF is output. The gate of transistor M2 is connected to the gate of transistor M4. Therefore, when the transistor M2 is turned on, the transistor M4 is also turned on. When transistor M2 is turned on while GOUT[N-1] is at a high level, , the shift register does not work.

[0006] In the shift register shown in FIG. 7 of Patent Document 2, transistor Q53 or When the transistor Q56 turns on, the voltage VOFF is output. During a certain period, transistor Q53 is off, but transistor Q56 is on. is on, the voltage VOFF is output. However, to achieve this, Two transistors, Q53 and Q56, are required. , and has a large number of transistors.

[0007] An object of one embodiment of the present invention is to provide a novel circuit configuration. A novel circuit configuration that can be applied to a part of a shift register or a part of a sequential circuit included in the shift register One object of the present invention is to provide a method for outputting a voltage in a long period of time. Another object of the present invention is to provide a circuit configuration capable of realizing the above. , to lengthen the period during which a transistor for outputting a voltage is turned on, or to realize the same It is an object of the present invention to provide a circuit configuration in which the number of transistors can be reduced. An object of one embodiment of the present invention is to reduce power consumption. An object of one embodiment of the present invention is to reduce a layout area. One object of the present invention is to reduce the number of manufacturing steps. One of the objectives of the project is to

[0008] The description of these problems does not preclude the existence of other problems. It is not necessary for the embodiment to solve all of these problems. The above will become apparent from the description in the specification, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0009] One embodiment of the present invention is a semiconductor device including first to fourth transistors. One of the source and drain of the first transistor is electrically connected to the first wiring. The other of the source and drain of the second transistor is electrically connected to the second wiring. Either the source or the drain of the second transistor is electrically connected to the third wiring. The other of the source and drain of the third transistor is electrically connected to the second wiring. Either the source or the drain of the fourth transistor is electrically connected to the third wiring. The source or drain of the first transistor is connected to the source or drain of the second transistor. The other of the source and the drain of the fourth transistor is electrically connected to the first transistor. The gate of the fourth transistor is electrically connected to the gate of the second transistor. The gate of the transistor is electrically connected to the gate of the transistor.

[0010] In the semiconductor device, the gate of the third transistor is electrically connected to the first wiring. This may also be the case.

[0011] In the semiconductor device, the gate of the third transistor is electrically connected to a fourth wiring. This may also be the case.

[0012] In the above semiconductor device, the W (channel width) / L (channel length) of the fourth transistor is , may be larger than the W / L of the third transistor.

[0013] In the above semiconductor device, the area where the semiconductor layer of the fourth transistor overlaps with the gate electrode is , may be larger than the area where the semiconductor layer and the gate electrode of the third transistor overlap.

[0014] In the semiconductor device, at least one of the first to fourth transistors is made of an oxide semiconductor The semiconductor device may have a channel formation region. Effect of the Invention

[0015] One embodiment of the present invention can provide a novel circuit configuration. [Brief description of the drawings]

[0016] [Figure 1] Circuit diagram of a sequential circuit. [Diagram 2] 1 is a timing chart of a sequential circuit. [Diagram 3] Circuit diagram of a sequential circuit. [Figure 4] Circuit diagram of a sequential circuit. [Diagram 5] Circuit diagram of a sequential circuit. [Figure 6] Circuit diagram of a sequential circuit. [Figure 7] Circuit diagram of a sequential circuit. [Figure 8] Circuit diagram of a sequential circuit. [Figure 9] Circuit diagram of a sequential circuit. [Figure 10] Circuit diagram of a sequential circuit. [Figure 11] FIG. 1 is a circuit diagram of a shift register. [Figure 12] 1 is a timing chart of a shift register. [Figure 13] FIG. 1 is a diagram showing a configuration of a semiconductor display device. [Figure 14] Top view of a pixel. [Figure 15] FIG. [Figure 16] 1A and 1B are diagrams illustrating a cross-sectional structure of a transistor. [Figure 17] FIG. [Figure 18] FIG. [Figure 19] Electronics illustration DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and the embodiments and aspects of the present invention may be modified without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various modifications may be made to the details. However, the present invention should not be construed as being limited to the description of the following embodiment.

[0018] One embodiment of the present invention is a semiconductor device using a transistor, such as an integrated circuit, an RF tag, or a semiconductor display device. The category includes all kinds of semiconductor devices. Processing circuit, DSP (Digital Signal Processor), Microcomputer LSI (Large Scale Integrated Circuit) including controller it), FPGA (Field Programmable Gate Array) and Programmable logic circuits (PLD: Programmable Logic Devices) such as CPLD (Complex PLD) Rammable Logic Devices (RAMDs) are included in this category. Display devices include liquid crystal displays and organic light-emitting devices (OLEDs), which use light-emitting elements as pixels. Light-emitting devices, electronic paper, DMD (Digital Micromirror Device), PDP (Plasma Display Panel), FED (Fi Circuit elements using semiconductor films, such as low-emission displays, are used as driving circuits. This category includes semiconductor display devices having a semiconductor display circuit.

[0019] In this specification, the term "semiconductor display device" refers to a display device in which display elements such as liquid crystal elements and light emitting elements are formed in pixels. The panel is a module with ICs, including a controller, mounted on the panel. This category includes both.

[0020] For example, in this specification, when it is explicitly stated that X and Y are connected, When X and Y are electrically connected, when X and Y are functionally connected, This includes the case where X and Y are directly connected. Therefore, a given connection relationship, For example, the present invention is not limited to the connection relationships shown in the drawings or text, and may be modified in any way without departing from the spirit or scope of the present invention. This also includes matters other than those involved.

[0021] Here, X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.). , etc.).

[0022] An example of a case where X and Y are electrically connected is The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, One or more elements (such as an electrode, a display element, a light-emitting element, or a load) can be connected between X and Y. It is possible. The switch has a function that allows it to be turned on and off. A switch can be in a conductive state (on state) or a non-conductive state (off state) and can either pass current or not. The switch has the function of controlling whether or not current flows. It has the function of switching between these modes.

[0023] An example of a case where X and Y are functionally connected is a case where a functional connection between X and Y is possible. Circuits that perform the above functions (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits ( power supply circuits (voltage boost circuits, voltage drop circuits, etc.), level shifter circuits that change the potential level of signals, etc.) , voltage sources, current sources, switching circuits, amplifier circuits (which can increase the signal amplitude or current amount, etc.) circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation One or more devices (such as a memory circuit, a control circuit, etc.) can be connected between X and Y. For example, even if another circuit is inserted between X and Y, the signal output from X X and Y are said to be functionally connected if

[0024] In addition, when it is explicitly stated that X and Y are connected, it means that X and Y are electrically connected. (That is, there is another element or circuit between X and Y.) (i.e., there is no other element or device between X and Y) and (i.e., X and Y are functionally connected). (X and Y are functionally connected via another circuit) and (X and Y are directly connected) (i.e., when X and Y are connected without any other element or circuit between them) In other words, when it is explicitly stated that they are electrically connected, it is not enough to simply It is the same as if it were explicitly stated that the item is connected.

[0025] For example, the source (or the first terminal, etc.) of the transistor is connected via Z1 (or The drain (or second terminal, etc.) of the transistor is electrically connected to Z 2 (or not), it may be electrically connected to Y, or the source of the transistor (or the first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 is directly connected to X. The drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2. and another part of Z2 is directly connected to Y, It is possible to do so.

[0026] For example, "X and Y and the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor The terminals of the transistor (or the first terminal, etc.) are electrically connected to each other, and X, the source of the transistor (or the first terminal, etc.) 1 terminal, etc.), the drain (or second terminal, etc.) of the transistor, and Y. "The source (or the third) of the transistor is connected to the The drain (or second terminal, etc.) of the transistor is electrically connected to X. The transistor source (or first terminal, etc.) is electrically connected to Y, and the transistor source (or first terminal, etc.) is electrically connected to X. The drain (or second terminal, etc.) of the transistor, Y, is electrically connected in this order. " Alternatively, "X is the source (or first terminal, etc.) of a transistor. The transistor is electrically connected to Y via a drain (or a second terminal, etc.) and a transistor is electrically connected to X via a drain (or a second terminal, etc.). The source (or first terminal, etc.) of a resistor, the drain (or second terminal, etc.) of a transistor ), Y is provided in this connection order. By using a simple expression method and specifying the order of connections in the circuit configuration, Distinguish between the source (or first terminal, etc.) and the drain (or second terminal, etc.) of a transistor. The technical scope can be determined by the above expressions. Here, X, Y, Z1, and Z2 are the object (e.g., the device , elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0027] The source of a transistor is a source region that is a part of a semiconductor film that functions as an active layer, or The term "source electrode" means a source electrode electrically connected to the semiconductor film. The drain refers to a drain region that is a part of a semiconductor film that functions as an active layer, or It means a drain electrode electrically connected to a conductor film. Also, a gate means a gate electrode. do.

[0028] The source and drain of a transistor are determined by the channel type of the transistor and the characteristics of each terminal. The name is changed depending on the level of the potential applied. Generally, n-channel transistors are In a transistor, the terminal to which a low potential is applied is called the source, and the terminal to which a high potential is applied is called the drain. In addition, in a p-channel transistor, the terminal to which a low potential is applied is called a drain. The terminal to which the high potential is applied is called the drain, and the terminal to which the high potential is applied is called the source. Assuming that the source and drain are fixed, explain the connection relationship of the transistor. In some cases, the source and drain are named according to the above potential relationship. Replace.

[0029] (Embodiment 1) In this embodiment mode, a sequential circuit (also referred to as a semiconductor device) will be described.

[0030] An example of the configuration of a sequential circuit will be described with reference to FIG. 1. FIG. 1 is an example of a circuit diagram of a sequential circuit. The sequential circuit in FIG. 1 through 115 .

[0031] Note that the transistors 101 to 107 illustrated in FIG. 1 are n-channel transistors. However, the present invention is not limited to this, and the transistors 101 to 107 are P-channel. The transistors 101 to 107 may be of the same conductivity type. This simplifies the manufacturing process and reduces costs compared to CMOS circuits. It is possible.

[0032] If the transistors 101 to 107 are N-channel transistors, The semiconductor region may be made of an oxide semiconductor, amorphous silicon, or microcrystalline silicon. This simplifies the manufacturing process compared to when polycrystalline silicon is used for the channel formation region. In particular, the channel forming region can be formed without using an oxide semiconductor. By using a conductor, the off-state current of the transistors 101 to 107 can be made extremely small. This allows for a reduction in power consumption.

[0033] The connection relationship of each transistor will be described. The first terminal of the transistor 101 is connected to the wiring. The first terminal of the transistor 102 is connected to the wiring 111 and the second terminal is connected to the wiring 112. The first terminal of the transistor 1 is connected to a wiring 113, and the second terminal of the transistor 1 is connected to a wiring 112. A first terminal of transistor 03 is connected to a wiring 113, and a gate of transistor 03 is connected to a wiring 111. The first terminal of the transistor 104 is connected to the second terminal of the transistor 103. is connected to the gate of transistor 101, and its gate is connected to the gate of transistor 102. The first terminal of the transistor 105 is connected to the wiring 114, and the second terminal of the transistor 105 is connected to the wiring 114. The gate of the transistor 101 is connected to the wiring 115. 06 has a first terminal connected to the wiring 115 and a second terminal connected to the gate of the transistor 102. The first terminal of the transistor 107 is connected to the wiring 115, and the gate of the transistor 107 is connected to the wiring 115. The second terminal is connected to the line 113, and the second terminal is connected to the gate of the transistor 102. The gate of the transistor 101 is connected to the gate of the transistor 102. In this manner, a novel circuit configuration can be provided. can.

[0034] The gate of the transistor 101 is indicated as a node N1, and the gate of the transistor 102 is indicated as a node N2. This is denoted as node N2.

[0035] An example of a signal or voltage input to each wiring will be described. A voltage VSS is input to the wiring 113, a signal SP is input to the wiring 114, A signal CK2 is input to the wiring 115. The signals CK1, CK2, and SP Based on this, the signal OUT is output to the wiring 112. There is a lock signal. Signals CK1 and CK2 are out of phase with each other. Signal SP is There is a start pulse (also called a set signal). The voltage VSS can be the power supply voltage or the ground voltage. The signal OUT is the output signal of the sequential circuit.

[0036] For convenience, the high-level potential of the signals CK1, CK2, and SP is VD D(VDD>VSS) and the low-level potential is VSS.

[0037] Note that one embodiment of the present invention also includes a case where no signal or voltage is input to each wiring. For example, each wiring may be any wiring that can receive the above-mentioned signals or voltages.

[0038] The function of each transistor will be described.

[0039] The transistor 101 turns on or off the wiring 111 and the wiring 112 based on the potential of the node N1. The transistor 101 controls the non-conduction of the signal CK By supplying a signal 1 to the wiring 112, the signal OUT becomes high level.

[0040] The transistor 102 turns on or off the wiring 113 and the wiring 112 based on the potential of the node N2. The transistor 102 controls the voltage VS based on the potential of the node N2. By supplying S to the wiring 112, the signal OUT is set to a low level.

[0041] The transistor 103 is connected to the wiring 113 and the first terminal of the transistor 104 based on the signal CK1. The transistor 104 controls conduction or non-conduction between the node N1 and the transistor 104 based on the potential of the node N2. Based on this, the conduction or non-conduction between the second terminal of the transistor 103 and the node N1 is controlled. That is, the circuit having the transistor 103 and the transistor 104 outputs the signals CK1 and NO The conduction or non-conduction between the wiring 113 and the node N1 is controlled based on the potential of the node N2. The circuit including the transistors 103 and 104 controls the signal CK1 and the node N 2, the voltage VSS is supplied to the node N1, thereby Set the value so that transistor 101 is turned off.

[0042] The transistor 105 turns on or off the wiring 114 and the node N1 based on a signal CK2. The transistor 105 controls the signal SP based on the signal CK2 to the node N1. , the potential of the node N1 is set to a value at which the transistor 101 is turned on. Thereafter, transistor 105 is turned off by removing the signal SP from node N1. Put N1 in a floating state.

[0043] The transistor 106 turns on or off the wiring 115 and the node N2 based on a signal CK2. Then, the transistor 106 controls the signal CK2 to the node N 2, the potential of the node N2 is supplied to the transistors 102 and 10 Set the value so that 4 is on.

[0044] The transistor 107 turns on or off the wiring 113 and the node N2 based on the potential of the node N1. The transistor 107 controls the voltage VS based on the potential of the node N1. By supplying S to node N2, the potential of node N2 is set to transistor 102 and transistor The value is set so that the transistor 104 turns off.

[0045] An example of the operation of the sequential circuit of FIG. 1 will be described with reference to FIG. 2 to FIG. 4. FIG. 2 shows a signal C K1, signal CK2, signal SP, and the potential of node N1 (V N1), the potential of node N2 (V N2 3A is a timing chart showing an example of a signal OUT from time t1 to time t 3(B) is a schematic diagram of the operation during the period from time t2 to t3 (also referred to as period T1). FIG. 4(A) is a schematic diagram of the operation during the period T2 from time t3 to t4 (period FIG. 4B is a schematic diagram of the operation from time t4 to t5 (period T4 1 is a schematic diagram of the operation in a conventional synchronous transfer system.

[0046] In addition, the signals CK1 and CK2 illustrated in FIG. 2 are at a high level during one period. The periods when the signal CK1 is at a low level are equal to each other, and the phase difference is 180°. The signal SP shown in FIG. 2 has a pulse width of 100 s. This is a half cycle of signal CK1 or signal CK2.

[0047] First, at time t1, the signal SP goes high and the signal CK1 goes low. , signal CK2 becomes high level.

[0048] The potential of the node N1 is as follows: Since the signal CK2 is at a high level, the transistor 105 is turned on. Also, since the signal CK1 is at a low level, the transistor 103 is turned on. As will be described later, the potential of node N2 becomes high, so the transistor Therefore, the high level signal SP is applied to the node N1 through the transistor 104. Since the potential of the node N1 is supplied via the potential 05, the potential of the node N1 rises. is the gate potential of the transistor 105 minus the threshold voltage of the transistor 105, i.e. That is, the value obtained by subtracting the threshold voltage of the transistor 105 from the high-level potential of the signal CK2 (VDD When the voltage Vth rises to −Vth105, the transistor 105 turns off. The node N1 is in a floating state and the potential of the node N1 is maintained at VDD-Vth105. do.

[0049] The potential of the node N2 is as follows: Since the signal CK2 is at a high level, the transistor 106 is turned on. In addition, the potential of the node N1 becomes high, so that the transistor 107 Therefore, a high-level signal CK2 is applied to the node N1 to turn on the transistor 106. The voltage VSS is supplied through transistor 107. Therefore, the potential of the node N2 is determined by the resistance ratio of the transistor 106 and the transistor 107. Here, the transistor 106 has a larger source and drain than the transistor 107. The resistance between the node N1 and the node N2 is sufficiently small. Specifically, the potential of the node N2 is set to a value slightly higher than that of the transistor 102. The potential of the first terminal is higher than the sum of the potential of the first terminal and the threshold voltage of the transistor 102, and the potential of the transistor A value higher than the sum of the potential of the first terminal of transistor 104 and the threshold voltage of transistor 104, i.e. is higher than the sum of the voltage VSS and the threshold voltage of the transistor 102 (VSS+Vth102), And the sum of the voltage VSS and the threshold voltage of the transistor 104 (VSS+Vth104) It will be a high value.

[0050] The potential of the wiring 112 is as follows: Since the potential of the node N1 is high, the transistor The transistor 101 is turned on. Also, the potential of the node N2 becomes high, so that the transistor 10 Therefore, the low-level signal CK1 is applied to the wiring 112. Since the voltage VSS is supplied through transistor 102, The potential of the wiring 112 becomes VSS. That is, the signal OUT becomes low.

[0051] Next, at time t2, the signal SP goes low and the signal CK1 goes high. , signal CK2 goes low.

[0052] The potential of the node N1 is as follows: Since the signal CK2 is at a low level, the transistor 105 remains off. Signal CK1 goes high, so transistor 103 As described later, the potential of the node N2 becomes VSS, so that the transistor 10 4 is turned off. Therefore, the node N1 remains in a floating state, and the potential of the node N1 is VD However, as described later, as the potential of the wiring 112 increases, This causes the potential of the node N1 to further increase.

[0053] The potential of the node N2 is as follows: Since the signal CK2 is at a low level, the transistor 106 is turned off. In addition, the potential of the node N1 becomes high, so that the transistor 107 Therefore, the voltage VSS is applied to the node N2 through the transistor 107. As a result, the potential of the node N2 becomes VSS.

[0054] The potential of the wiring 112 is as follows: Since the potential of the node N1 remains high, The transistor 101 remains on. Also, the potential of the node N2 becomes VSS. Therefore, the wiring 112 is connected to the high-level transistor 101 via the transistor 101. Since the signal CK1 of the high level is supplied, the potential of the wiring 112 rises. Due to the parasitic capacitance between the gate and the second terminal of the transistor 101, The potential difference between the wiring 1 and the node N1 is maintained. As the potential of node N1 rises, the potential of node N2 also rises. is the sum of the potential of the first terminal of the transistor 101 and the threshold voltage of the transistor 101, i.e. The sum of the high-level potential of the signal CK1 and the threshold voltage of the transistor 101 (VDD+Vth 101) will be higher than the potential of the wiring 112 until the potential of the wiring 112 reaches VDD. That is, the signal OUT becomes high level.

[0055] Next, at time t3, the signal SP remains at a low level, and the signal CK1 becomes a low level. and the signal CK2 goes high.

[0056] The potential of the node N1 is as follows: Since the signal CK2 is at a high level, the transistor 105 is turned on. The signal CK1 is at a low level, so the transistor 103 is turned off. In addition, as described later, the potential of the node N2 becomes high, so that the transistor 10 Therefore, a low level signal SP is input to node N1, so that node The potential of the node N1 becomes VSS.

[0057] The potential of the node N2 is as follows: Since the signal CK2 is at a high level, the transistor In addition, the potential of the node N1 becomes VSS, so that the transistor 107 Therefore, a high-level signal CK2 is applied to the node N2 to turn on the transistor 106. Since the potential of the node N2 is supplied through the transistor, the potential of the node N2 rises. The potential of the gate of transistor 106 minus the threshold voltage of transistor 106, i.e., the signal The value obtained by subtracting the threshold voltage of the transistor 106 from the high-level potential of CK2 (VDD-Vt When the potential at node N2 rises to h106, transistor 106 turns off. goes into a floating state, and the potential of the node N2 is maintained at VDD-Vth106.

[0058] The potential of the wiring 112 is as follows: Since the potential of the node N1 becomes VSS, The transistor 101 is turned off. Also, the potential of the node N2 becomes high, so that the transistor 10 2 is turned on. Therefore, the voltage VSS is supplied to the wiring 112 through the transistor 102. Therefore, the potential of the wiring 112 becomes VSS. That is, the signal OUT becomes low.

[0059] Next, at time t4, the signal SP remains at a low level, and the signal CK1 becomes a high level. and the signal CK2 goes to low level.

[0060] The potential of the node N1 is as follows: Since the signal CK2 is at a low level, the transistor 105 is turned off. Also, since the signal CK1 is at a high level, the transistor 103 is turned As will be described later, the potential of the node N2 remains high, so that the transistor Therefore, the voltage VSS is applied to the node N1 through the transistor 103. and is supplied through the transistor 104, the potential of the node N1 remains at VSS. do.

[0061] The potential of the node N2 is as follows: Since the signal CK2 is at a low level, the transistor In addition, the potential of the node N1 becomes VSS, so that the transistor 107 Therefore, the node N2 is in a floating state, and the potential of the node N2 is VDD- Maintained at Vth106.

[0062] The potential of the wiring 112 is as follows: Since the potential of the node N1 remains at VSS, The transistor 101 remains off. Also, the potential of the node N2 remains high. Therefore, the voltage VSS is applied to the wiring 112. Since the potential of the wiring 112 remains VSS, the potential of the wiring 112 remains VSS. That is, the signal OUT remains at a low level.

[0063] After time t5, the signals CK1 and CK2 are held at high level until the signal SP becomes high again. Each time the signal is inverted, the operation from time t3 to t4 and the operation from time t4 to t5 are repeated. vinegar.

[0064] An example of the effect achieved by the sequential circuit of FIG. 1 will be described.

[0065] A novel circuit configuration can be provided.

[0066] In the period T1, the transistor 103 is turned off, and the gate of the transistor 102 is turned off. The gate of the transistor 104 can be connected to the gate of the transistor 105, and the period T1, the period T In the period T3 and the period T4, the transistor 102 can be turned on. The period during which the transistor 102 is on can be extended, and the voltage VSS can be supplied to the line 112. In addition, the period during which the transistor 102 is turned on can be increased. Since there is no need to provide a transistor, the number of transistors can be reduced. The on / off of the stator 102 and the transistor 104 is controlled by a common signal or a common circuit. Since the control can be performed, the number of signals can be reduced and the circuit scale can be reduced.

[0067] A transistor 104 is connected between the transistor 103 and the node N1. Fluctuations in the potential of the gate of the transistor 103 can be prevented from being transmitted to the node N1. Therefore, the potential of the node N1 can be stabilized, and malfunction can be suppressed.

[0068] It is possible to provide a circuit configuration capable of achieving the above-mentioned effects.

[0069] W (channel width) and L (channel length) of the transistors 101 to 107 An example will be described.

[0070] The load of the wiring 112 is often larger than the load of the node N1 and the load of the node N2. Therefore, the W / L of transistor 101 is greater than the W / L of transistor 103. It is preferable that the W / L of the transistor 101 is greater than the W / L of the transistor 104. It is preferable that the W / L of transistor 101 is greater than the W / L of transistor 105. It is preferable that the W / L of the transistor 101 is greater than the W / L of the transistor 106. It is preferable that the W / L of transistor 101 is larger than the W / L of transistor 107. It is preferable that the W / L of the transistor 102 is larger than the W / L of the transistor 103. It is preferable that the W / L of transistor 102 is greater than the W / L of transistor 104. It is preferable that the W / L of transistor 102 is greater than the W / It is preferable that the W / L of transistor 102 is greater than the W / L of transistor 106. It is preferable that W / L of transistor 102 is greater than W / L of transistor 107. It is preferable that the width W / L is larger than the width W / L. Thus, the width W / L of the transistor 101 and the transistor 1 Since the current supply capacity of 02 can be increased, the change in the signal OUT can be made steeper. In addition, the load of the wiring 112 can be increased. Since the size of the transistor 107 can be reduced, the layout of the sequential circuit can be improved. The area required for the mounting can be reduced.

[0071] The load on node N1 is often larger than the load on node N2. The W / L of transistor 05 is preferably greater than the W / L of transistor 106. The W / L of 105 is preferably greater than the W / L of transistor 107. Thus, Since the current supply capability of the transistor 105 can be increased, the potential of the node N1 can be increased This allows the sequential circuit to operate at a faster speed. Since the size of the transistor 106 and the transistor 107 can be reduced, the sequential circuit The layout area of ​​the road can be reduced.

[0072] Transistor 105 is turned on to change the potential of node N1, while transistor Transistor 103 and transistor 104 are turned on to maintain the potential of node N1. Therefore, the W / L of transistor 105 is greater than the W / L of transistor 103. It is preferable that the W / L of the transistor 105 is larger than the W / L of the transistor 104. In this way, the current supply capability of the transistor 105 can be increased. Therefore, the potential of the node N1 can be changed quickly, and the operation speed of the sequential circuit can be increased. On the other hand, the sizes of the transistors 103 and 104 can be reduced. This makes it possible to reduce the layout area of ​​the sequential circuit.

[0073] A transistor 103 and a transistor 104 are connected in series between the wiring 113 and the node N1. 1, whereas the transistor 107 is connected between the wiring 113 and the node N2. In addition, the load on node N1 is often larger than the load on node N2. Therefore, it is preferable that the W / L of transistor 103 is larger than the W / L of transistor 107. In addition, the W / L of the transistor 104 is greater than the W / L of the transistor 107. In this way, the current supplying power of the transistor 103 and the transistor 104 is preferably Since the potential of the node N1 can be quickly lowered, The operating speed of the circuit can be improved. In addition, the potential of the node N1 can be reliably maintained at VSS. Therefore, it is possible to maintain the transistor 107 and prevent malfunction. Since the size can be reduced, the layout area of ​​the sequential circuit can be reduced. Cut.

[0074] The smaller the overlapping area between the semiconductor layer and the gate electrode of the transistor 103, the The potential of the gate of the transistor 103 is not easily transmitted to the node N1. When the overlapping area between the semiconductor layer and the gate electrode is reduced, the current supply capability of the transistor 103 is reduced. Therefore, it is preferable to increase the current supply capability of the transistor 104. Therefore, the area where the semiconductor layer of the transistor 104 overlaps with the gate electrode is preferably It is preferable that the area is larger than the area where the semiconductor layer of the transistor 103 and the gate electrode overlap. In particular, the W / L of the transistor 104 is preferably greater than the W / L of the transistor 103. Alternatively, the W×L of the transistor 104 is preferably larger than the W×L of the transistor 103. It is preferable that the thickness is large.

[0075] The resistance between the source and drain of transistor 106 is higher than that of transistor 107. To be small enough, the W / L of transistor 106 is smaller than the W / L of transistor 107. It is preferable that the thickness is larger than the thickness of the slab.

[0076] A modified example of the sequential circuit of FIG. 1 will be described. Note that the parts common to FIG. 1 are denoted by the same reference numerals. are not shown and their explanation is omitted.

[0077] As shown in FIG. 5A, the gate of the transistor 105 may be connected to a wiring 114. The transistor 105 shown in FIG. 5A supplies the signal SP to a node N1 based on the signal SP. Therefore, it is possible to prevent malfunctions caused by a timing difference between the signal SP and the signal CK2. can be done.

[0078] As shown in FIG. 5B, the first terminal of the transistor 105 is connected to a wiring 115. The gate of the transistor 105 may be connected to the wiring 114. 105 supplies a signal CK2 to the node N1 based on the signal SP. Since the change in potential can be made steep, the operating speed of sequential circuits can be improved. do.

[0079] As shown in FIG. 5C, the first terminal of the transistor 105 is connected to a wiring 117. The gate of the transistor 105 may be connected to the wiring 114. A voltage VDD is supplied to the wiring 117. The transistor 105 shown in FIG. 5C outputs the voltage VDD to the node based on the signal SP. Therefore, the change in the potential of the node N1 can be made steep, The operating speed of the circuit can be improved.

[0080] Note that two of the transistors 105 shown in FIGS. 1, 5A, 5B, and 5C For example, as shown in FIG. 5(D), the sequential circuit shown in FIG. A transistor 105A corresponding to the transistor 105 and a transistor 105B corresponding to the transistor 105A shown in FIG. A transistor 105B corresponding to .05 may be provided.

[0081] As shown in FIG. 6A, the first terminal of the transistor 107 may be connected to a wiring 115. The transistor 107 shown in FIG. 6A outputs a signal CK2 based on the potential of the node N1. The signal CK2 is at a high level during the period T1. Therefore, it is possible to prevent a shoot-through current from occurring in the transistors 106 and 107 in the Therefore, the power consumption can be reduced. Since it is not necessary to increase the size of the sequential circuit, the layout area of ​​the sequential circuit can be reduced.

[0082] As shown in FIG. 6B, the first terminal of the transistor 107 may be connected to a wiring 114. The transistor 107 shown in FIG. 6B outputs the signal SP to the node N1 based on the potential of the node N1. Since the signal SP is at a high level during the period T1, Therefore, a shoot-through current can be prevented from occurring in the transistors 106 and 107. Therefore, the power consumption can be reduced. Since there is no need to increase the size of the sequential circuit, the layout area of ​​the sequential circuit can be reduced.

[0083] As shown in FIG. 6C, the gate of the transistor 107 may be connected to a wiring 112. A transistor 107 shown in FIG. 6C supplies a voltage VSS to a node N2 based on a signal OUT. Since the signal OUT is at a low level during the period T1, Therefore, the transistor 107 can be turned off during the period T1. 6 and the transistor 107 can be prevented from passing through, thereby reducing power consumption. In addition, since there is no need to increase the W / L of the transistor 106, The layout area of ​​the sequential circuit can be reduced.

[0084] As shown in FIG. 6D, the first terminal of the transistor 107 is connected to the wiring 115. The gate of the transistor 107 may be connected to the wiring 112. 107 supplies a signal CK2 to the node N2 based on the signal OUT. The signal OUT is applied during a period T Since the signal becomes low level during period T1, the transistor 107 is turned off during period T2. Therefore, the transistors 106 and 107 in the period T1 This prevents the through current from flowing through the transistors, which reduces power consumption. Since there is no need to increase the W / L of the transistor 106, the layout area of ​​the sequential circuit is reduced. It is possible to make small plans.

[0085] As shown in FIG. 6E, the first terminal of the transistor 107 is connected to the wiring 114. The gate of the transistor 107 may be connected to the wiring 112. 107 supplies a signal SP to a node N2 based on the signal OUT. The signal OUT is applied during a period T1 Since the signal goes to a low level during the period T1, the transistor 107 is turned off during the period T2. Therefore, the current generated in the transistors 106 and 107 during the period T1 can be This can prevent through current from flowing through the transistors, thereby reducing power consumption. Since there is no need to increase the W / L of the transistor 106, the layout area of ​​the sequential circuit is reduced. It is possible to achieve this.

[0086] As shown in FIG. 7A, the first terminal of the transistor 106 may be connected to a wiring 117. The transistor 106 shown in FIG. 7A supplies the voltage VDD to the node N This allows a low-level signal to be supplied to node N2 due to a timing error or the like. Therefore, it is possible to prevent the supply of the electric power from being interrupted.

[0087] As shown in FIG. 7B, the first terminal of the transistor 106 is connected to a wiring 118. The gate of the transistor 106 may be connected to a wiring 118. A signal CK3 is input to the wiring 118. Signal CK3 is a clock signal. However, signal CK3 is the same as signal CK1 and The transistor 106 shown in FIG. 7B is driven based on the signal CK3. The signal CK3 is then supplied to the node N2.

[0088] As shown in FIG. 7C, the first terminal of the transistor 106 is connected to a wiring 117. The gate of the transistor 107 may be connected to the wiring 118. 106 supplies the voltage VDD to the node N2 based on the signal CK3. This prevents a low-level signal from being supplied to node N2 due to timing misalignment or the like. This can be done.

[0089] As shown in FIG. 8A, a first terminal of the transistor 104 is connected to a wiring 113. A first terminal of the transistor 103 is connected to a second terminal of the transistor 104. The second terminal of 103 may be connected to node N1.

[0090] As shown in FIG. 8B, the gate of the transistor 103 may be connected to a wiring 119. A signal CK4 is input to the wiring 119, and the signal CK4 is applied to the transistor 1 The signal CK4 is a clock signal. 4 is out of phase with signals CK1 and CK2.

[0091] Although not shown, the gate of the transistor 103 may be connected to the wiring 118.

[0092] Although not shown, a first terminal is connected to the node N1, and a second terminal is connected to the wiring 112. A capacitive element may be provided.

[0093] Although not shown in the figure, the first terminal of the transistor 102 is connected to a wiring different from the wiring 113. For example, a voltage higher than the voltage VSS may be supplied to the line. Therefore, the current generated in the transistor 101 and the transistor 102 can be reduced.

[0094] Although not shown in the figure, the gate of the transistor 102 is connected to the wiring 115, the wiring 118, or the wiring 11. May be connected to 9.

[0095] The above-described sequential circuits shown in FIG. 1, FIG. 5 to FIG. 8, etc. may be freely combined. For example, when the first terminal of the transistor 106 is connected to the wiring 117 as shown in FIG. In both cases, the first terminal of the transistor 107 is connected to the wiring 115 as shown in FIG. As another example, a transistor 10 as shown in FIG. The first terminal of the transistor 6 is connected to the wiring 117, and as shown in FIG. The gate of the transistor 103 may be connected to a wiring 119 (see FIG. 9B).

[0096] One embodiment of the present invention includes the following configuration within its category.

[0097] One embodiment of the present invention is a transistor 101, a transistor 102, a transistor 103, and The first terminal of the transistor 101 is connected to a wiring 111. The second terminal of the transistor 101 is connected to the wiring 112. The first terminal of the transistor 101 is connected to a wiring 113, and the second terminal of the transistor 102 is connected to a wiring 112. The first terminal of the transistor 103 is connected to the wiring 113. The gate of the transistor 104 is connected to the wiring 111. A second terminal of the transistor 104 is connected to a second terminal of the transistor 101. The gate of transistor 104 is connected to the gate of transistor 102. (See FIG. 10(A)).

[0098] One embodiment of the present invention is a transistor 101, a transistor 102, a transistor 103, and The first terminal of the transistor 101 is connected to a wiring 111. The second terminal of the transistor 101 is connected to the wiring 112. The first terminal of the transistor 101 is connected to a wiring 113, and the second terminal of the transistor 102 is connected to a wiring 112. The first terminal of the transistor 103 is connected to the wiring 113. The gate of the transistor 104 is connected to the wiring 119. A second terminal of the transistor 104 is connected to a second terminal of the transistor 101. The gate of transistor 104 is connected to the gate of transistor 102. (See FIG. 10(B)).

[0099] This embodiment may be appropriately combined with configurations disclosed in the present specification and the like, such as other embodiments. This can be implemented.

[0100] (Embodiment 2) In this embodiment, a shift register (also called a semiconductor device) using the sequential circuit of the first embodiment is This section explains the above.

[0101] An example of the configuration of a shift register will be described with reference to FIG. 1 is an example of a circuit diagram of a starter.

[0102] The shift register in FIG. 11 includes sequential circuits 100[1] to 100[N] (N is 2 or more). 11, sequential circuits 100[1] to 100[2] are shown. As sequential circuits 100[1] to 100[N], the sequential circuits shown in FIG. The sequential circuits 100[1] to 100[N] are used. The sequential circuit is not limited to the sequential circuit of FIG. 11, and may be any other sequential circuit disclosed in the present specification such as the first embodiment. The route may be adopted.

[0103] The shift register in FIG. 11 includes wirings 121[1] to 121[N], a wiring 122, and a wiring 123, wiring 124, and wiring 125. In any one of the above, the wiring 111 is connected to one of the wiring 123 and the wiring 124, The line 112 is connected to the line 121[i], the line 113 is connected to the line 125, and the line 11 4 is connected to the wiring 121[i-1], and the wiring 115 is connected to the other of the wiring 123 and the wiring 124. The sequential circuit 100[1] is sequential at the point where the wiring 114 is connected to the wiring 122. The circuit 100[i] is different from the circuit 100[i]. Also, in the odd-numbered sequential circuits and the even-numbered sequential circuits, In the odd-numbered stages, the wiring 111 and the wiring 115 are connected to opposite locations. When 11 is connected to the wiring 123 and 115 is connected to the wiring 124, in the even-numbered stages, , the wiring 111 is connected to the wiring 124 , and the wiring 115 is connected to the wiring 123 .

[0104] Signals SOUT[1] to SOUT[N] are output from wirings 121[1] to 121[N]. Each of the wirings 121[1] to 121[N] is connected to the wiring 112. Each of the signals SOUT[1] to SOUT[N] corresponds to the signal OUT. A signal SSP is input to the line 122. The line 122 corresponds to the line 114, and the signal SSP is In particular, in the sequential circuit 100[i], the wiring 121[i-1] corresponds to the wiring 1 14, and the signal SOUT[i-1] corresponds to the signal SP. A signal SCK2 is input to the wiring 123. corresponds to one of the wirings 115, and the signal SCK1 corresponds to one of the signals CK1 and CK2. The wiring 124 corresponds to the other of the wiring 111 and the wiring 115, and the signal SCK2 corresponds to the signal This corresponds to the other of the signal CK1 and the signal CK2. A voltage VSS is supplied to the wiring 125. 125 corresponds to the wiring 113 .

[0105] An example of the operation of the shift register of FIG. 11 will be described with reference to FIG. 12. Signal SCK1, signal SCK2, signal SSP, the potential of node N1 of the sequential circuit 100[1] (V N1 ), the potential of the node N2 of the sequential circuit 100[1] (V N2 ), signal SOUT[1], signal 11 is a timing chart showing an example of a signal SOUT[2] and a signal SOUT[3].

[0106] First, at time t1, the signal SCK1 goes low and the signal SCK2 goes high. The sequential circuit 100[1] in the first embodiment is In order to perform the operation during the period T1 described above, the signal SOUT[1] becomes low level. The circuit 100[2] performs the operation during the period T4 described in the first embodiment. The signal SOUT[2] goes low. In order to perform the operation during the period T3 described above, the signal SOUT[3] becomes low level.

[0107] Next, at time t2, the signal SCK1 goes high and the signal SCK2 goes low. The sequential circuit 100[1] in the first embodiment is In order to perform the operation during the period T2 described above, the signal SOUT[1] becomes high level. The circuit 100[2] performs the operation during the period T1 described in the first embodiment. The signal SOUT[2] goes low. In order to perform the operation during the period T4 described above, the signal SOUT[3] becomes low level.

[0108] Next, at time t3, the signal SCK1 goes low and the signal SCK2 goes high. The sequential circuit 100[1] in the first embodiment is In order to perform the operation during the period T3 described above, the signal SOUT[1] becomes low level. The circuit 100[2] performs the operation during the period T2 described in the first embodiment. The signal SOUT[2] becomes high level. In order to perform the operation during the period T1 described above, the signal SOUT[3] becomes low level.

[0109] Next, at time t4, the signal SCK1 goes high and the signal SCK2 goes low. The sequential circuit 100[1] in the first embodiment is In order to perform the operation during the period T4 described above, the signal SOUT[1] becomes low level. The circuit 100[2] performs the operation during the period T3 described in the first embodiment. The signal SOUT[2] goes low. In order to perform the operation during the period T2 described above, the signal SOUT[3] becomes high level.

[0110] This embodiment may be appropriately combined with configurations disclosed in the present specification and the like, such as other embodiments. This can be implemented.

[0111] (Embodiment 3) <Configuration Example of Semiconductor Display Device> Next, a structural example of a semiconductor display device according to one embodiment of the present invention will be described.

[0112] In the semiconductor display device 70 shown in FIG. 13A, a pixel section 71 includes a plurality of pixels 55 and a pixel 5 for each row, corresponding to the bus lines GL1 to GLy (y is a natural number). A wiring GL indicated by a number (number) and a wiring SL for supplying an image signal to a selected pixel 55 1 to SLx (x is a natural number) are provided. The input of the signal is controlled by the driving circuit 72. The input of the image signal to the wiring SL is The pixel 55 is controlled by a driving circuit 73. Each of the wirings SL is connected to at least one of the wirings SL.

[0113] Specifically, the driving circuit 72 generates signals for sequentially selecting the wirings GL1 to GLy. Specifically, the driver circuit 73 has a shift register 75 which sequentially outputs a pulse. A shift register 76 generates a signal corresponding to the shift register 76. and a switch circuit 77 for controlling the supply of image signals to the wirings SL1 to SLx. .

[0114] A sequential circuit or a shift register according to one embodiment of the present invention includes a shift register 75 or a shift In this case, for example, the wirings GL1 to GLy can be used as the resistor 76. Each of these corresponds to the wiring 112.

[0115] The type and number of wirings provided in the pixel section 71 depend on the configuration, number and arrangement of the pixels 55. Specifically, in the case of the pixel section 71 shown in FIG. The pixels 55 in the row are arranged in a matrix, and the wirings SL1 to SLx and the wiring GL1 10 shows an example in which the wirings GLy are arranged inside the pixel portion 71.

[0116] In FIG. 13A, the driver circuit 72 and the driver circuit 73 are formed on a single substrate together with the pixel portion 71. The driving circuit 72 and the driving circuit 73 are formed on a substrate. It may be formed on a substrate different from that of 71 .

[0117] 13B shows an example of the configuration of a pixel 55. Each pixel 55 includes a liquid crystal element 60 a transistor 56 for controlling the supply of an image signal to the liquid crystal element 60; The liquid crystal element 60 has a capacitance element 57 for holding a voltage between the pixel electrode and the common electrode. The liquid crystal display includes a pixel electrode, a common electrode, and a liquid crystal material to which a voltage is applied between the pixel electrode and the common electrode. and a liquid crystal layer.

[0118] The transistor 56 controls whether or not the potential of the wiring SL is applied to the pixel electrode of the liquid crystal element 60. A predetermined potential is applied to the common electrode of the liquid crystal element 60.

[0119] The specific connection configuration between the transistor 56 and the liquid crystal element 60 will be described below. In B), the gate of the transistor 56 is connected to one of the wirings GL1 to GLy. One of the source and drain of the transistor 56 is connected to the wiring SL1. Lx, and the other of the source and drain of the transistor 56 is connected to the liquid crystal It is connected to the pixel electrode of the element 60 .

[0120] In the liquid crystal element 60, the voltage applied between the pixel electrode and the common electrode changes depending on the voltage contained in the liquid crystal layer. The orientation of the liquid crystal molecules contained in the liquid crystal element 60 changes, and the transmittance changes. The transmittance of the pixel is controlled by the potential of the image signal applied to the pixel, thereby displaying gray scales. In each of the pixels 55 in the pixel section 71, a liquid crystal element The gray scale of the pixel 60 is adjusted in accordance with an image signal having image information, so that an image is displayed on the pixel section 71. is displayed.

[0121] In FIG. 13B, a pixel 55 includes a switch that controls the input of an image signal to the pixel 55. However, the case where one transistor 56 is used as a switch is illustrated. A number of transistors functioning in the same manner may be used in pixel 55.

[0122] In one embodiment of the present invention, a transistor 56 having an extremely low off-state current is used as a It is preferable to use the transistor 56 as a switch to control the input to the A small value prevents charge from leaking through transistor 56. The potential of the image signal applied to the liquid crystal element 60 and the capacitance element 57 can be more reliably held. Therefore, the transmittance of the liquid crystal element 60 changes due to leakage of electric charges within one frame period. This prevents the display of images from being blurred, thereby improving the quality of the images displayed. When the off-current of the transistor 56 is small, the charge leakage through the transistor 56 is prevented. Therefore, during the period when a still image is displayed, the driving circuits 72 and 73 With the above configuration, the supply of the image signal to the pixel section 71 may be stopped. This reduces the number of times the signal is written, thereby reducing the power consumption of the semiconductor display device.

[0123] For example, a transistor including an oxide semiconductor in a semiconductor film has an extremely small off-state current. This is suitable for use as transistor 56.

[0124] In FIG. 13B, the transistor 56 is a single layer in which a semiconductor film is sandwiched between the transistors. The semiconductor device may have a pair of gate electrodes, the pair of gate electrodes being electrically connected to each other. In one embodiment of the present invention, the above structure increases the on-state current of the transistor 56. In addition, the reliability of the transistor 56 can be improved.

[0125] Next, FIG. 13C shows another example of the pixel 55. The pixel 55 has an image signal a transistor 95 for controlling the input of a signal; a light-emitting element 98; A transistor 96 controls the current value supplied to the image sensor 8, and a capacitor 97 holds the potential of the image signal. and a capacitance element 97.

[0126] The light emitting element 98 is a light emitting diode (LED) or an organic light emitting diode (OLED). current or voltage, such as a photovoltaic (Pb) or photovoltaic (Pb) light emitting diode (Pb) The category includes devices whose luminance is controlled by the light emitting diode (ELD) layer. For example, an OLED includes an EL layer and The device has at least an anode and a cathode. The EL layer is provided between the anode and the cathode. The layer is made up of a single layer or multiple layers, each of which contains a luminescent material. It includes at least a light emitting layer.

[0127] In addition, the EL layer is turned on when the potential difference between the cathode and the anode becomes equal to or exceeds the threshold voltage of the light emitting element 98. When the current is applied, electroluminescence is obtained. There are two types of emission: fluorescence when returning from the singlet excited state to the ground state and fluorescence when returning from the triplet excited state. This includes light emission (phosphorescence) when the compound returns to the ground state.

[0128] Either the anode or the cathode of the light emitting element 98 is connected to an image signal input to the pixel 55. Therefore, the potential is controlled. The potential of the anode and the cathode is controlled according to the image signal. The electrode to be controlled is a pixel electrode, and the other electrode is a common electrode. A predetermined potential is applied to the electrode, and the brightness of the light-emitting element 98 is determined by the potential between the pixel electrode and the common electrode. Therefore, the luminance of the light emitting element 98 is determined by the potential difference between the pixel electrodes. By controlling the pixel area, it is possible to display gradations. In each of the above-mentioned embodiments, the gradation of the light-emitting element 98 is adjusted according to an image signal having image information. As a result, an image is displayed on the pixel section 71 .

[0129] Next, the transistor 95, the transistor 96, the capacitor element 97, the light emitting element 98, and the like included in the pixel 55 are The connection configuration of the element 98 will now be described.

[0130] The transistor 95 has one of a source and a drain connected to the wiring SL. The other input is connected to the gate of transistor 96. The gate of transistor 95 is , and is connected to the wiring GL. VL, and the other of the source and drain is connected to the light emitting element 98. The other of the source and drain of the transistor 96 is connected to the anode and cathode of the light emitting element 98. The light emitting element 98 is connected to either the anode or the cathode. A predetermined potential is applied to the

[0131] In FIG. 13C, a transistor 96 is a pair of gates overlapping each other with a semiconductor film sandwiched therebetween. The pair of gate electrodes may be electrically connected to each other. In one embodiment, the above-described structure increases the on-state current of the transistor 96. This can improve the reliability of Transistor 96.

[0132] For example, in this specification, a display element, a display device which is a device having a display element, a light-emitting A light-emitting device, which is a device having an element and a light-emitting element, can be used in various forms or can be used in various forms. The display element, the display device, the light-emitting element, or the light-emitting device can have, for example, EL (electroluminescence) elements (EL elements containing organic and inorganic materials, organic EL elements LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.) , transistors (transistors that emit light according to electric current), electron-emitting devices, liquid crystal devices, electron Ink, electrophoretic element, grating light valve (GLV), plasma display (PDP), a display element using MEMS (microelectromechanical systems) Digital Micromirror Device (DMD), Digital MicroShutter ch.), IMOD (Interference Modulation) element, shutter type MEMS display element, optical interference type MEMS display element, electrowetting element, pressure At least one of electroceramic displays, display elements using carbon nanotubes, etc. In addition, the contrast, brightness, and other properties can be improved by electrical or magnetic effects. The display device may have a display medium whose reflectance, transmittance, etc. change. An example of a display device using electron emission elements is an EL display. The display is a field emission display (FED) or SED type flat panel display. Play (SED: Surface-conduction Electron-emit An example of a display device using liquid crystal elements is the liquid crystal Displays (transmissive LCDs, semi-transmissive LCDs, reflective LCDs) LCD, direct-view LCD, projection LCD, etc. An example of a display device using electronic liquid powder (registered trademark) or electrophoretic elements is an electronic page. In addition, there are also other LCDs that can realize semi-transmissive and reflective LCD displays. In this case, a part or the whole of the pixel electrode may be made to function as a reflective electrode. For example, a part or the whole of the pixel electrode may be made of aluminum, silver, etc. In this case, a memory circuit such as an SRAM should be provided under the reflective electrode. This makes it possible to further reduce power consumption.

[0133] For example, in this specification, it is possible to form transistors using various substrates. The type of substrate is not limited to a specific one. Conductor substrates (e.g., single crystal substrates or silicon substrates), SOI substrates, glass substrates, quartz substrates, Plastic substrate, metal substrate, stainless steel substrate, stainless steel foil Substrate with tungsten foil, Tungsten substrate, Substrate with tungsten foil, Flexible substrate, Adhesive There are laminated films, papers containing fibrous materials, and base films. Examples include barium borosilicate glass, aluminoborosilicate glass, or soda lime glass. Examples of flexible substrates, laminated films, and base films include glass. Examples of such materials include polyethylene terephthalate (PET), polyethylene Plastics such as polyolefin naphthalate (PEN) and polyethersulfone (PES) One example is synthetic resin such as acrylic. Another example is Examples of the material include polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride. Examples of the material include polyamide, polyimide, aramid, epoxy, and inorganic vapor deposition. Films, papers, etc. In particular, semiconductor substrates, single crystal substrates, and SOI substrates, etc. By manufacturing transistors using this method, there is little variation in characteristics, size, shape, etc. This allows the manufacture of transistors with fewer gates, higher current capability, and smaller size. When a circuit is constructed using such transistors, the power consumption of the circuit can be reduced or the circuit can be highly integrated. It is possible to achieve this.

[0134] In addition, a flexible substrate is used as the substrate, and a transistor is formed directly on the flexible substrate. Alternatively, a release layer may be provided between the substrate and the transistor. After a semiconductor device is partially or completely completed, it is separated from the substrate and transferred to another substrate. In this case, the transistor can be transferred to a substrate with poor heat resistance or a flexible substrate. The above-mentioned peeling layer may be formed of an inorganic material such as a tungsten film and a silicon oxide film. The structure may be a laminated structure of films or a structure in which an organic resin film such as polyimide is formed on a substrate. It is possible.

[0135] That is, a transistor is formed using one substrate, and then the transistor is transferred to another substrate. The transistor may be placed on one substrate and the transistor may be placed on another substrate. Examples include substrates on which the above-mentioned transistors can be formed, as well as paper substrates, ceramic substrates, etc. Fan board, aramid film board, polyimide film board, stone board, wood board, cloth board Board (natural fibers (silk, cotton, linen), synthetic fibers (nylon, polyurethane, polyester) or Mostly recycled fibers (including acetate, cupra, rayon, recycled polyester, etc.), leather The substrates used are leather and rubber. By using these substrates, Formation of transistors with low power consumption, fabrication of durable devices, heat resistance It is possible to provide a lighter or thinner device.

[0136] This embodiment may be appropriately combined with configurations disclosed in the present specification and the like, such as other embodiments. This can be implemented.

[0137] (Embodiment 4) Pixel Structure Next, a liquid crystal display device, which is one of the semiconductor display devices 70 shown in FIG. 13(A), will be taken as an example. Next, a configuration example of the pixel 55 will be described. FIG. 14 shows a top view of the pixel 55 as an example. In FIG. 14, various insulating films are omitted in order to clarify the layout of the pixel 55. A liquid crystal display device formed using an element substrate having pixels 55 shown in FIG. A cross-sectional view of the liquid crystal display device shown in FIG. corresponds to a cross-sectional view taken along dashed line B1-B2 in FIG.

[0138] A pixel 55 shown in FIGS. 14 and 15 includes a transistor 56 and a capacitor 57. Furthermore, the pixel 55 shown in FIG.

[0139] The transistor 56 is provided on the substrate 31 having an insulating surface, and has a function as a gate electrode. A conductive film 40 and an insulating film located on the conductive film 40, which has a function as a gate insulating film. a conductive film 40 formed on the insulating film 22; an oxide semiconductor film 41 overlapping the conductive film 40 on the insulating film 22; A conductive electrode electrically connected to the body membrane 41 and functioning as a source electrode or a drain electrode. The conductive film 40 includes a film 43 and a conductive film 44. The conductive film 40 serves as the wiring GL shown in FIG. The conductive film 43 also functions as the wiring SL shown in FIG. .

[0140] The pixel 55 also has a metal oxide film 42 on the insulating film 22. The metal oxide film 42 is The metal oxide film 42 is a conductive film that is transparent to visible light. A conductive film 61 is provided which is electrically connected to the metal oxide film 42. The conductive film 61 is The wiring 14 functions as a wiring for supplying a predetermined potential to the

[0141] The insulating film 22 may be made of aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, Silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, dioxide One or more of: lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide The insulating film containing the acid may be used as a single layer or a laminated layer. A nitride is a material whose composition contains more oxygen than nitrogen, while a nitride oxide is a material whose composition contains more oxygen than nitrogen. It refers to a material whose composition contains more nitrogen than oxygen.

[0142] 15, the oxide semiconductor film 41, the conductive film 43, and the conductive film 44, and the metal oxide film An insulating film 26 and an insulating film 27 are provided on the insulating film 42 and the conductive film 61 in this order. The transistor 56 may include the insulating film 26 and the insulating film 27 as components. In addition, in FIG. 15, the insulating film 26 and the insulating film 27 are stacked in this order. Instead of the insulating film 26 and the insulating film 27, a single-layer insulating film may be used. Insulating films having three or more layers may be used.

[0143] The insulating film 26 and the insulating film 27 have an opening 58 at a position where they overlap with the metal oxide film 42. The opening 58 is formed in a region different from the oxide semiconductor film 41, the conductive film 43, and the conductive film 44. and is provided in a region overlapping with the metal oxide film 42.

[0144] 15, the metal oxide film 4 on the insulating film 26 and the insulating film 27 and in the opening 58 On the upper surface of the insulating film 2, a nitride insulating film 28 and an insulating film 29 are provided in this order.

[0145] Note that an oxide semiconductor film is formed on the insulating film 22, and a nitride By forming the insulating film 28, the electrical conductivity of the oxide semiconductor film can be increased. As a result, the oxide semiconductor film with increased conductivity can be used as the metal oxide film 42. The conductivity of the oxide semiconductor film increases when the opening 58 is formed or when the nitride insulating film 2 During the formation of the nitride insulating film 28, oxygen vacancies are formed in the oxide semiconductor film, and the oxygen diffuses from the nitride insulating film 28. This is thought to be because the hydrogen atom that is released binds to the oxygen vacancy to generate a donor. The resistivity of the metal oxide film 42 is typically 1×10 -3 Ωcm or more 1×10 4 Ωcm More preferably, the resistivity is less than 1×10 -3 Ωcm or more 1×10 -1 Less than Ωcm It would be good to do so.

[0146] The metal oxide film 42 preferably has a higher hydrogen concentration than the oxide semiconductor film 41. In the film 42, secondary ion mass spectrometry (SIMS) was used. The hydrogen concentration obtained by assemblage spectrometry was 8×10 19 atom s / cm 3 More than 1×10 20 atoms / cm 3 More preferably, 5x 10 20 atoms / cm 3 The above is the case. In the oxide semiconductor film 41, the secondary ion mass The hydrogen concentration obtained by the analytical method is 5×10 19 atoms / cm 3 Less than 5, preferably ×10 18 atoms / cm 3 Less than 1 x 10 18 atoms / cm 3 below, More preferably, 5×10 17 atoms / cm 3 Less than 1×10, more preferably 16 a toms / cm 3 The following is the result.

[0147] The nitride insulating film 28 may be, for example, silicon nitride, silicon oxynitride, or aluminum nitride. The nitride insulating film using the above-mentioned material may be aluminum oxide nitride. 28 is less susceptible to external impurities than oxide insulating films such as silicon oxide and aluminum oxide. Substances such as water, alkali metals, and alkaline earth metals diffuse into the oxide semiconductor film 41. This can prevent the following:

[0148] In addition, an opening 62 is provided in the nitride insulating film 28 and the insulating film 29 at a position where the conductive film 44 overlaps. A transparent insulating film that is transparent to visible light is formed on the nitride insulating film 28 and the insulating film 29. The conductive film 45 has an opening and functions as a pixel electrode. At the opening 62, the conductive film 45 is electrically connected to the conductive film 44. At 58, the conductive film 45 overlaps with the metal oxide film 42. The overlapping portion sandwiching the oxide insulating film 28 and the insulating film 29 functions as a capacitance element 57. .

[0149] The capacitor 57 includes a metal oxide film 42 and a conductive film 45 which function as a pair of electrodes, and a dielectric The nitride insulating film 28 and the insulating film 29 functioning as a film are transparent to visible light. Therefore, the capacitor 57 is transparent to visible light, and the capacitance of the capacitor The aperture ratio of the pixel 55 can be increased compared to pixels having low translucency to visible light. This allows the capacitance required to obtain high image quality to be secured while minimizing light loss within the panel. Therefore, the power consumption of the semiconductor device can be reduced.

[0150] As described above, the insulating film 29 is not necessarily provided, but it is preferable to provide the insulating film 29 more than the nitride insulating film 28. The insulating film 29 using an insulating material having a lower relative dielectric constant than the nitride insulating film 28 is used as a dielectric film together with the nitride insulating film 28. By using the nitride insulating film 28, the dielectric constant of the dielectric film of the capacitance element 57 is increased. It is possible to adjust the value to a desired value without any need for adjustment.

[0151] On the conductive film 45, an alignment film 52 is provided.

[0152] A substrate 46 is provided so as to face the substrate 31. and a colored layer 48 that transmits visible light in a specific wavelength range. A resin film 50 is provided on the shielding film 47 and the colored layer 48. A conductive film 59 having a function as a common electrode is provided on the film 50. An alignment film 51 is provided on 59 .

[0153] Between the substrate 31 and the substrate 46, a liquid crystal layer is disposed so as to be sandwiched between the alignment film 52 and the alignment film 51. The liquid crystal element 60 includes a conductive film 45, a conductive film 59, and a liquid crystal layer 53 including a conductive film 59. and a liquid crystal layer 53 .

[0154] In addition, in FIG. 14 and FIG. 15, a TN (Twisted Nemat) liquid crystal driving method is used. The liquid crystal driving method is also called FFS (Fringe flip-flop) mode. e Field Switching) mode, STN (Super Twisted Nematic mode, VA (Vertical Alignment) mode, MV A (Multi-domain Vertical Alignment) mode, IP S (In-Plane Switching) mode, OCB (Optically C ompensated birefringence mode, blue phase mode, TBA (Transverse Bend Alignment) mode, VA-IPS mode ,ECB(Electrically Controlled Birefringen) ce) mode, FLC (Ferroelectric Liquid Crystal) Mode, AFLC (AntiFerroelectric Liquid Crysta) l) mode, PDLC (Polymer Dispersed Liquid Crystal tal) mode, PNLC (Polymer Network Liquid Crys tal) mode, guest host mode, ASV (Advanced Super Vie It is also possible to apply modes such as w).

[0155] In the liquid crystal display device according to one embodiment of the present invention, the liquid crystal layer may include, for example, a thermotropic Liquid crystal materials classified as lyotropic or lyotropic liquid crystals can be used. The liquid crystal layer may be, for example, a nematic liquid crystal, a smectic liquid crystal, a cholesteric liquid crystal, or A liquid crystal material classified as a discotic liquid crystal can be used for the liquid crystal layer. For example, liquid crystal materials classified as ferroelectric liquid crystal or antiferroelectric liquid crystal can be used. Alternatively, the liquid crystal layer may be made of, for example, a main chain type polymer liquid crystal, a side chain type polymer liquid crystal, or By using liquid crystal materials classified as polymer liquid crystals such as composite polymer liquid crystals or low molecular weight liquid crystals, Alternatively, the liquid crystal layer may be, for example, a polymer dispersed liquid crystal (PDLC). A liquid crystal material may be used.

[0156] In addition, a liquid crystal exhibiting a blue phase without using an alignment film may be used in the liquid crystal layer. When the temperature of a cholesteric liquid crystal is increased, the cholesteric phase changes to the isotropic phase. The blue phase appears only in a narrow temperature range, so The temperature range is improved by adding chiral agents and UV-curable resins. The liquid crystal composition containing the above has a short response time of 1 msec or less and is optically isotropic, so that alignment is possible. This is preferable because no processing is required and the viewing angle dependency is small.

[0157] FIG. 15 shows a liquid crystal display device that uses color filters to display color images. However, the liquid crystal display device according to one embodiment of the present invention has multiple display devices that emit light of different hues. The light sources may be sequentially turned on to display a color image.

[0158] Note that the oxide semiconductor film 41 of the transistor 56 is formed of a single oxide semiconductor film. The insulating film 16 may be formed of a plurality of stacked oxide semiconductor films. Now, let us consider a case where the oxide semiconductor film 41 is composed of three stacked oxide semiconductor films. Specifically, in a transistor 56 illustrated in FIG. 41, oxide semiconductor films 41a to 41c are arranged in this order from the insulating film 22 side. It is layered.

[0159] The oxide semiconductor film 41a and the oxide semiconductor film 41c constitute the oxide semiconductor film 41b. The element contains at least one metal element that forms an oxide. The energy of the conduction band minimum is The difference is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.05 eV or more, more preferably 0.07 eV or more, more preferably 0.1 eV or more, more preferably ... .15 eV or more and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less, true The oxide semiconductor film 41b is an oxide film close to a vacant level. It is preferable for the compound to contain the compound to have a high carrier mobility.

[0160] Note that the oxide semiconductor film 41c is formed by arranging the conductive film 43 and the conductive film 44 as shown in FIG. It may be configured so as to overlap the insulating film 22 at the upper layer.

[0161] This embodiment may be appropriately combined with configurations disclosed in the present specification and the like, such as other embodiments. This can be implemented.

[0162] (Embodiment 5) <Top view and cross-sectional view of semiconductor display device> Next, the appearance of a semiconductor display device according to one embodiment of the present invention will be described using a liquid crystal display device as an example. This will be described with reference to FIG. 17. FIG. 17 shows a substrate 4001 and a substrate 4006 sealed with a sealing material 40. 17. Also, FIG. 18 shows the top view of the liquid crystal display device bonded by the broken line C in FIG. This corresponds to the cross-sectional view taken along line 1-C2.

[0163] A pixel portion 4002 and a pair of driver circuits 4004 are provided on a substrate 4001. A sealing material 4005 is provided on the pixel portion 4002 and the driver circuit 4004. Therefore, the pixel portion 4002 and the driver circuit 4004 are connected to a substrate 4006. It is sealed by 4001 , a sealing material 4005 and a substrate 4006 .

[0164] In addition, the driving force is applied to an area other than the area surrounded by the sealing material 4005 on the substrate 4001. An operating circuit 4003 is implemented.

[0165] In addition, a pixel portion 4002 and a driver circuit 4004 provided on a substrate 4001 are made of transistors. In FIG. 18, a transistor 4010 included in a pixel portion 4002 is illustrated. On the transistor 4010, an insulating layer made of various insulating films including a nitride insulating film is formed. An insulating film 4020 is provided, and the transistor 4010 is In the opening, it is connected to a pixel electrode 4021 on the insulating film 4020 .

[0166] In addition, a resin film 4059 is provided on the substrate 4006, and a common An electrode 4060 is provided. A pixel electrode is provided between the substrate 4001 and the substrate 4006. A liquid crystal layer 4028 is provided so as to be sandwiched between the electrode 4021 and the common electrode 4060. The liquid crystal element 4023 includes a pixel electrode 4021, a common electrode 4060, and a liquid crystal layer 4028. do.

[0167] In the liquid crystal element 4023, the value of the voltage applied between the pixel electrode 4021 and the common electrode 4060 Accordingly, the orientation of the liquid crystal molecules contained in the liquid crystal layer 4028 changes, and the transmittance changes. The liquid crystal element 4023 changes its pixel voltage in response to the potential of the image signal applied to the pixel electrode 4021. By controlling the transmittance, it is possible to display gradations.

[0168] As shown in FIG. 18, in one embodiment of the present invention, the insulating film 4020 is In the region where the insulating film 4020 has been removed, the conductive film 4 The conductive film 4050 and the source or drain of the transistor 4010 are formed. The conductive film that functions as an insulating film can be formed by etching a conductive film. do.

[0169] Conductive particles 4061 having conductivity are dispersed between the substrate 4001 and the substrate 4006. The conductive film 4050 is provided with a resin film 4062 dispersed therein. That is, the common electrode 4060 and the conductive particles 4061 are electrically connected to each other. The film 4050 is electrically connected to the panel at the edge via conductive particles 4061. The resin film 4062 is made of a thermosetting resin or an ultraviolet-curing resin. The conductive particles 4061 can be made of, for example, spherical organic resin with Au, Ni, Co, etc. Particles coated with a thin film of metal such as those mentioned above can be used.

[0170] Although the alignment film is not shown in FIG. 18, the alignment film is formed on the pixel electrode 4021 and the common electrode 4 When the conductive film 4050 is provided on the common electrode 4060, the conductive particles 4061, and the conductive film 4050 are In order to electrically connect the common electrode 4060 and the alignment film, a part of the alignment film is removed from the area where the alignment film overlaps the common electrode 4060. In this case, the alignment film may be partially removed from a portion overlapping with the conductive film 4050 .

[0171] In the liquid crystal display device according to one embodiment of the present invention, a color filter is used to display a color image. An image may be displayed, or multiple light sources emitting light of different hues may be sequentially turned on. A color image may be displayed.

[0172] In addition, image signals from the driver circuit 4003 and various control signals and potentials from the FPC 4018 are 4004 or the pixel section 400 2 is given.

[0173] This embodiment may be appropriately combined with configurations disclosed in the present specification and the like, such as other embodiments. This can be implemented.

[0174] (Embodiment 6) In this embodiment mode, the semiconductor layer of the transistor described in the above embodiment mode can be formed by using An oxide semiconductor layer that can be formed using the oxide semiconductor layer will be described.

[0175] The oxide semiconductor used for the channel formation region in the semiconductor layer of the transistor is at least It is preferable that the alloy contains indium (In) or zinc (Zn). In particular, the alloy contains In and Zn. In addition, it is preferable to have a stabilizer that strongly binds oxygen. The stabilizer is preferably gallium (Ga), tin (Sn), zirconium (Zr), or the like. Contains at least one of Zr, Hafnium, and Aluminum. Just do that.

[0176] Other stabilizers include the lanthanides lanthanum (La) and cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Ho, Erbium, Thulium, Ytterbium, Ru The element may contain one or more of tetraethynyl ions (Te).

[0177] Examples of oxide semiconductors used for the semiconductor layer of a transistor include indium oxide. Tin oxide, zinc oxide, In-Zn oxide, Sn-Zn oxide, Al-Zn oxide Zn-Mg oxide, Sn-Mg oxide, In-Mg oxide, In-Ga oxide In-Ga-Zn oxide (also written as IGZO), In-Al-Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, S n-Al-Zn oxide, In-Hf-Zn oxide, In-Zr-Zn oxide, In -Ti-Zn oxide, In-Sc-Zn oxide, In-Y-Zn oxide, In-L a-Zn oxide, In-Ce-Zn oxide, In-Pr-Zn oxide, In-Nd -Zn oxide, In-Sm-Zn oxide, In-Eu-Zn oxide, In-Gd- Zn-based oxide, In-Tb-Zn-based oxide, In-Dy-Zn-based oxide, In-Ho-Z n-based oxides, In-Er-Zn-based oxides, In-Tm-Zn-based oxides, In-Yb-Zn In-Lu-Zn ​​oxide, In-Sn-Ga-Zn oxide, In-Hf- Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al-Zn oxide oxides, In-Sn-Hf-Zn oxides, In-Hf-Al-Zn oxides, etc.

[0178] For example, In:Ga:Zn=1:1:1, In:Ga:Zn=3:1:2, or I In-Ga-Zn oxide with an atomic ratio of n:Ga:Zn=2:1:3 and its neighboring compositions It is preferable to use an oxide.

[0179] When a large amount of hydrogen is contained in the oxide semiconductor film constituting the semiconductor layer, hydrogen is bonded to the oxide semiconductor. By doing so, some of the hydrogen atoms become donors, generating electrons that act as carriers. This causes the threshold voltage of the transistor to shift in the negative direction. After the semiconductor film is formed, a dehydration treatment (dehydrogenation treatment) is performed to remove water from the oxide semiconductor film. It is preferable to highly purify the material by removing hydrogen or moisture to minimize the amount of impurities contained therein.

[0180] Note that the oxide semiconductor film is dehydrated (dehydrogenated) to Therefore, the oxygen content increases during dehydration (dehydrogenation) treatment. In order to fill the oxygen vacancies, a treatment for adding oxygen to the oxide semiconductor film is preferably performed. In the specification and the like, supplying oxygen to an oxide semiconductor film may be referred to as oxygen supplying treatment. or when the amount of oxygen contained in the oxide semiconductor film is higher than that in the stoichiometric composition, This may be referred to as "synthesis treatment."

[0181] In this manner, hydrogen or moisture is removed from the oxide semiconductor film by the dehydration treatment (dehydrogenation treatment). By adding oxygen to the material, the oxygen deficiency is compensated for, resulting in an i-type (intrinsic) or i-type In this case, the oxide semiconductor film can be an oxide semiconductor film that is substantially i-type (intrinsic). The term "substantially intrinsic" means that the oxide semiconductor film contains very few carriers derived from donors (zero (close to B), and the carrier density is 1×10 17 / cm 3 Below, 1×10 16 / cm 3 Below, 1 ×10 15 / cm 3 Below, 1×10 14 / cm 3 Below, 1×10 13 / cm 3 Is less than or equal to This means.

[0182] In addition, a transistor including an i-type or substantially i-type oxide semiconductor film as described above can be For example, a transistor using an oxide semiconductor film can achieve excellent off-state current characteristics. The drain current when the transistor is off is 1×10 at room temperature (approximately 25°C). -18 Below A , preferably 1 x 10 -21 A or less, more preferably 1×10-24 A or below, or 85℃ 1×10 -15 A or less, preferably 1×10 -18 A or less, more preferably 1×10 -21 A or less. Note that the off state of a transistor is an n-channel In the case of a transistor, this refers to a state in which the gate voltage is sufficiently smaller than the threshold voltage. If the gate voltage is more than 1 V, more than 2 V, or more than 3 V less than the threshold voltage, the transistor is in the off state.

[0183] The structure of the oxide semiconductor film will be described below.

[0184] Oxide semiconductor films are classified into non-single-crystal oxide semiconductor films and single-crystal oxide semiconductor films. Alternatively, oxide semiconductors are divided into, for example, crystalline oxide semiconductors and amorphous oxide semiconductors. do.

[0185] As the non-single-crystal oxide semiconductor, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor, polycrystalline oxide Semiconductors made of crystalline oxides include semiconductors made of microcrystalline oxides and amorphous oxides. The materials include single-crystal oxide semiconductors, CAAC-OS, polycrystalline oxide semiconductors, and microcrystalline oxides. Semiconductors, etc.

[0186] First, we will explain the CAAC-OS film.

[0187] The CAAC-OS film is one of oxide semiconductor films having a plurality of crystal parts aligned along the c-axis.

[0188] Transmission Electron Microscope (TEM) A bright-field image and a combined diffraction pattern of the CAAC-OS film were obtained by using a microscope. By observing the TEM image, multiple crystalline regions can be confirmed. On the other hand, the high-resolution TEM image also shows clear boundaries between crystals, i.e., grain boundaries. Therefore, the CAAC-OS film is It can be said that the decrease in electron mobility caused by grain boundaries is unlikely to occur.

[0189] When a high-resolution TEM image of the cross section of the CAAC-OS film was observed from a direction approximately parallel to the sample surface, It can be seen that the metal atoms are arranged in layers in the crystal part. Each layer of metal atoms is The CAAC-OS film is formed on the surface (also called the surface on which the film is formed) or on the upper surface. The CAAC-OS film has a shape similar to that of the crystalline silicon film, and is aligned parallel to the surface on which the CAAC-OS film is formed or the upper surface.

[0190] On the other hand, a high-resolution TEM image of the plane of the CAAC-OS film was observed from a direction approximately perpendicular to the sample surface. It was confirmed that the metal atoms in the crystals were arranged in triangular or hexagonal shapes. However, there is no regularity in the arrangement of metal atoms between different crystal parts.

[0191] X-ray diffraction (XRD) was performed on the CAAC-OS film. For example, InGaZnO 4 CAAC-OS film with crystals In the out-of-plane analysis, a peak was observed at a diffraction angle (2θ) of approximately 31°. This peak may appear in InGaZnO 4 It is assigned to the (009) plane of the crystal of From this, it can be seen that the crystals of the CAAC-OS film have a c-axis orientation, and the c-axis is approximately aligned on the surface on which the film is formed or on the upper surface. You can see that it is oriented vertically.

[0192] In addition, InGaZnO 4 Out-of-plane synthesis of CAAC-OS films with crystallites In the analysis by , in addition to the peak at 2θ near 31°, a peak also appeared at 2θ near 36°. The peak at 2θ of around 36° may be due to the c-axis orientation in some parts of the CAAC-OS film. The CAAC-OS film contains crystals that do not have a 2θ of around 31°. It is preferred that the spectrum exhibits a peak and does not exhibit a peak at 2θ of around 36°.

[0193] The CAAC-OS film is an oxide semiconductor film with a low concentration of impurities. The impurities include hydrogen, carbon, and The elements are other than the main components of the oxide semiconductor film, such as silicon and transition metal elements. The elements that bond to oxygen more strongly than the metal elements that form the oxide semiconductor film, such as arsenic, are oxidized. By removing oxygen from the oxide semiconductor film, the atomic arrangement of the oxide semiconductor film is disrupted, reducing its crystallinity. In addition, heavy metals such as iron and nickel, argon, and carbon dioxide have an atomic radius of Since the molecular radius is large, when the cation is contained in the oxide semiconductor film, the The impurities in the oxide semiconductor film may cause the atomic arrangement to be disturbed, which may result in a decrease in crystallinity. Objects can act as carrier traps or carrier generation sources.

[0194] The CAAC-OS film is an oxide semiconductor film having a low density of defect states. Oxygen vacancies in the semiconductor film can become carrier traps or trap hydrogen, It can be a carrier source.

[0195] A material with a low impurity concentration and a low defect level density (few oxygen vacancies) is called a high-purity intrinsic or The term "substantially high-purity intrinsic" refers to a highly-purified intrinsic oxide semiconductor film. Since there are fewer carrier generation sources, the carrier density can be reduced. The transistor including the oxide semiconductor film has electrical characteristics in which the threshold voltage is negative ( Also called normally-on.) In addition, high purity intrinsic or substantially high purity The highly intrinsic oxide semiconductor film has few carrier traps. The transistors using the thin film have small fluctuations in electrical characteristics and are highly reliable. Note that it takes a certain time for charges trapped in the carrier traps in the oxide semiconductor film to be released. The time when the charge is released is long, and it may behave as if it is a fixed charge. A transistor using an oxide semiconductor film having a high density of defect states has unstable electrical characteristics. This may be the case.

[0196] In addition, the electrical characteristics of transistors using CAAC-OS films were improved by irradiation with visible light or ultraviolet light. The fluctuation is small.

[0197] Next, a microcrystalline oxide semiconductor film will be described.

[0198] The microcrystalline oxide semiconductor film has a region where crystals can be confirmed in a high-resolution TEM image. The microcrystalline oxide semiconductor film has a crystal structure including a region where a crystal part is not clearly observed and a region where a crystal part is not clearly observed. The crystal part contained in the crystal has a size of 1 nm to 100 nm or 1 nm to 10 nm. In particular, the fineness is often between 1 nm and 10 nm, or between 1 nm and 3 nm. The oxide semiconductor film having nanocrystals (nc) is called nc -OS(nanocrystalline oxide semiconductor) In the nc-OS film, for example, the grain boundaries are clearly identified in high-resolution TEM images. It may not be possible to recognize

[0199] The nc-OS film is a microscopic region (e.g., a region of 1 nm to 10 nm, especially a region of 1 nm or more). The atomic arrangement has periodicity in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystal parts. Therefore, no orientation is observed throughout the film. Therefore, the nc-OS film cannot be distinguished from an amorphous oxide semiconductor film depending on the analysis method. For example, X-ray diffraction (XR) is used to measure the nc-OS film using X-rays with a diameter larger than that of the crystals. When structural analysis was performed using the D instrument, the crystal plane In addition, the peaks indicating the probe size were not detected in the nc-OS film. Electron diffraction (also called selected area electron diffraction) using an electron beam with a diameter (for example, 50 nm or more) When the diffraction pattern is changed to 0.05μm, a halo-like diffraction pattern is observed. Nano-beam electrons are used, which use an electron beam with a probe diameter close to or smaller than the size of the crystal part. When diffraction is performed, spots are observed. When this is done, a circular (ring-shaped) area of ​​high brightness may be observed. Nanobeam electron diffraction of the nc-OS film revealed multiple spots within the ring-shaped region. It may be observed.

[0200] The nc-OS film is an oxide semiconductor film that has higher order than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film. In the nc-OS film, there is no regularity in the crystal orientation between different crystal parts. The S film has a higher density of defect states than the CAAC-OS film.

[0201] Next, the amorphous oxide semiconductor film will be described.

[0202] The amorphous oxide semiconductor film is an oxide semiconductor film in which the atomic arrangement in the film is irregular and does not have a crystal part. An example is an oxide semiconductor film that has an amorphous state, such as quartz.

[0203] In the amorphous oxide semiconductor film, no crystalline parts can be confirmed in a high-resolution TEM image.

[0204] When the structure of the amorphous oxide semiconductor film is analyzed using an XRD device, out-of-p In the lane analysis, no peaks indicating crystal planes were detected. When electron diffraction is performed on a conductive film, a halo pattern is observed. When nanobeam electron diffraction is performed on a conductive film, no spots are observed, and a halo pattern is observed. Observed.

[0205] Note that the oxide semiconductor film has a structure that exhibits physical properties between the nc-OS film and the amorphous oxide semiconductor film. An oxide semiconductor film having such a structure may have a structure such as the following. Amorphous-like Oxide Semiconductor (a-like OS) The conductor membrane is called the endothelium.

[0206] In the a-like OS film, voids are observed in the high-resolution TEM image. In addition, crystals may be clearly visible in high-resolution TEM images. The a-like OS film has a region in which a crystal part is not observed and a region in which a crystal part is not observed. Crystallization occurs due to the small amount of electron irradiation, which is the level observed in TEM observations, and the growth of the crystals can be seen. On the other hand, if the nc-OS film is of good quality, the small amount of charge observed by TEM can be observed. Almost no crystallization due to electron irradiation was observed.

[0207] The size of the crystals in the a-like OS film and the nc-OS film was measured using a high-resolution T This can be done using EM images. For example, InGaZnO 4 The crystals have a layered structure, There are two Ga-Zn-O layers between the In-O layers. 4 Crystal unit cell of The layer has three In-O layers and six Ga-Zn-O layers, for a total of nine layers aligned in the c-axis direction. The spacing between adjacent layers is therefore the (009) plane. This is approximately the same as the lattice spacing (also called the d value), and crystal structure analysis has determined that this value is 0.29 nm Therefore, we focused on the lattice fringes in high-resolution TEM images and In the region where the distance is between 0.28 nm and 0.30 nm, the lattice fringes are InG aZnO 4 This corresponds to the ab plane of the crystal.

[0208] In addition, the density of an oxide semiconductor film may differ depending on the structure. If the composition of the membrane is known, the density can be determined by comparing it with that of a single crystal of the same composition. The structure of the oxide semiconductor film can be estimated. The density of the OS-like film is 78.6% or more and less than 92.3%. The density of the nc-OS film and the CAAC-OS film was 92.3% or more. Note that an oxide semiconductor film having a density of less than 78% of the density of a single crystal is The film formation itself is difficult.

[0209] The above will be explained using a specific example. For example, In:Ga:Zn=1:1:1 [atomic In the oxide semiconductor film that satisfies the [number ratio], single crystal InGaZnO having a rhombohedral crystal structure 4 The density of is 6.357g / cm 3 Therefore, for example, In:Ga:Zn=1:1:1 In the oxide semiconductor film that satisfies the atomic ratio, the density of the a-like OS film is 5.0 g / cm 3 More than 5.9g / cm 3 For example, In:Ga:Zn=1:1: In the oxide semiconductor film that satisfies the atomic ratio of 1, the density of the nc-OS film and the CAAC- The density of the OS film is 5.9 g / cm 3 More than 6.3g / cm 3 It will be less than.

[0210] In addition, there are cases where single crystals with the same composition do not exist. In such cases, the composition may differ in any ratio. By combining single crystals, it is possible to calculate the density equivalent to a single crystal of the desired composition. The density of a single crystal of a desired composition can be determined by the ratio of the single crystals of different compositions. However, the density should be calculated using as few types of single crystals as possible. It is preferable to perform the calculation in combination.

[0211] Note that the oxide semiconductor film may be, for example, an amorphous oxide semiconductor film, an a-like OS film, or a microcrystalline oxide semiconductor film. The semiconductor layer may be a stacked film including two or more of a crystalline oxide semiconductor film and a CAAC-OS film.

[0212] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Line" refers to the state in which two straight lines are arranged at an angle between -30° and 30°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the angle may be between 85° and 95°. This refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0213] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. .

[0214] This embodiment may be appropriately combined with configurations disclosed in the present specification and the like, such as other embodiments. This can be implemented.

[0215] (Embodiment 7) <Configuration Example of Electronic Device Using Semiconductor Device> A semiconductor device according to one aspect of the present invention includes a display device, a personal computer, and a recording medium. Image playback devices with advanced functions (typically DVD: Digital Versatile Disc (Devices having a display capable of playing back recording media such as 3D models and displaying the images) In addition, an electronic device in which the semiconductor device according to one embodiment of the present invention can be used Mobile phones, handheld game consoles, personal digital assistants, e-books, video cameras, digital cameras, etc. Cameras such as TasStill cameras, goggle-type displays (head-mounted displays) ), navigation systems, audio playback devices (car audio, digital audio players) Years, etc.), copiers, facsimiles, printers, printer-combination machines, automated teller machines Examples of such electronic devices include ATMs and vending machines. vinegar.

[0216] FIG. 19A shows a portable game machine, which includes a housing 5001, a housing 5002, a display unit 5003, Display unit 5004, microphone 5005, speaker 5006, operation keys 5007, The display unit 5003 or the display unit 5004 and other integrated circuits The semiconductor device according to one embodiment of the present invention can be used for the semiconductor device shown in FIG. The portable game machine has two display units 5003 and 5004. The number of display units that the game machine has is not limited to this.

[0217] FIG. 19B shows a portable information terminal, which includes a first housing 5601, a second housing 5602, a first display unit, and a 5603, a second display unit 5604, a connection unit 5605, and operation keys 5606. The display unit 5603 is provided in the first housing 5601, and the second display unit 5604 is provided in the second housing 5602. The first housing 5601 and the second housing 5602 are connected to each other via a connection portion 5602. 5605, and the angle between the first housing 5601 and the second housing 5602 is The image on the first display unit 5603 can be changed by the connection unit 5 The structure is such that the switch is performed according to the angle between the first housing 5601 and the second housing 5602 at 605. The first display portion 5603 or the second display portion 5604 or other integrated circuits may be formed. In this case, the semiconductor device according to one embodiment of the present invention can be used.

[0218] FIG. 19C shows a notebook personal computer, which includes a housing 5401 and a display unit 5402. The display unit 5402 and the like include a keyboard 5403 and a pointing device 5404. The semiconductor device according to one embodiment of the present invention can be used for these and other integrated circuits.

[0219] FIG. 19D shows a wristwatch, which includes a housing 5201, a display unit 5202, an operation button 5203, and a button. The display portion 5202 and other integrated circuits according to one embodiment of the present invention may include a display unit 5202 and other integrated circuits. A semiconductor device having such a structure can be used.

[0220] FIG. 19E shows a video camera, which includes a first housing 5801, a second housing 5802, and a display unit 58. 03, operation keys 5804, a lens 5805, a connection part 5806, etc. 4 and a lens 5805 are provided in a first housing 5801, and a display unit 5803 is provided in a second housing. The first housing 5801 and the second housing 5802 are connected to each other via a connection portion. The first housing 5801 and the second housing 5802 are connected by a joint 5806. The video on the display unit 5803 can be changed by the video input unit 5806. , according to the angle between the first housing 5801 and the second housing 5802 at the connection portion 5806. The semiconductor device according to one embodiment of the present invention may be provided in the display portion 5803 or other integrated circuits. A body device can be used.

[0221] FIG. 19F shows a mobile phone. A housing 5901 includes a display unit 5902, a microphone 5907, and a speaker. Speaker 5904, camera 5903, external connection part 5906, and operation button 5905 are provided. The semiconductor device according to one embodiment of the present invention is used for the display portion 5902 and other integrated circuits. In addition, the semiconductor device according to one embodiment of the present invention can be formed on a flexible substrate. In the case where the semiconductor device is formed in the display portion 5902 having a curved surface as shown in FIG. It is possible to apply the position.

[0222] In addition, the contents (or even a part of the contents) described in one embodiment may be used in the embodiment. Another content (or a part of the content) described in the embodiment, and / or one or more other embodiments The application, combination, or replacement of the contents (or part of the contents) described in the form It is possible to do the following:

[0223] The contents described in the embodiments are explained in detail with reference to various figures in each embodiment. This refers to the content that is stated or stated using the text in the specification.

[0224] In addition, a figure (or a part thereof) described in one embodiment may be different from another part of the figure, Another figure (or a part thereof) described in the embodiment, and / or one or more By combining with the figure (or a part of it) described in another embodiment of the present invention , and many more diagrams can be constructed.

[0225] In addition, regarding the contents not specified in the drawings or text in the specification, Alternatively, the upper limit of a certain value may be set. If a numerical range is listed, such as a lower limit, you can narrow the range arbitrarily. Or, by excluding one point within the scope, a mode of the invention that excludes a part of the scope is specified. As a result, for example, the prior art can be considered to be within the technical scope of one aspect of the present invention. It may be stipulated that no entry will be allowed.

[0226] As a specific example, a circuit diagram in which first to fifth transistors are used in a circuit is shown below. In that case, the circuit does not have a sixth transistor. Alternatively, the circuit does not have a capacitance element. Furthermore, it is possible to specify that the circuit has a specific connection structure. The invention can be configured by specifying that the semiconductor device does not have a sixth transistor. Alternatively, it is specified that the circuit does not have a capacitive element having a specific connection structure. For example, the gate of the third transistor may be connected to the gate of the third transistor. It is possible to specify the invention as not having a sixth transistor. Alternatively, for example, a capacitor element having a first electrode connected to the gate of the third transistor may be provided. It is possible to define the invention as not having

[0227] As another specific example, for a certain value, for example, "a certain voltage is 3 V or more and 10 V or less. In that case, for example, if a certain voltage is -2V It is possible to specify one aspect of the invention as "excluding cases where the voltage is greater than or equal to 1 V and less than or equal to 1 V." Or, For example, it is possible to define one aspect of the invention as excluding cases where a certain voltage is 13 V or higher. For example, the invention may be stipulated that the voltage is between 5V and 8V. It is possible. For example, it is also possible to specify the invention as having a voltage of approximately 9V. For example, the voltage is between 3V and 10V, but does not include the case where the voltage is 9V. It is also possible to define the invention as follows: Even if it is described that "it is preferable that these conditions are satisfied" or "it is preferable that these conditions are satisfied," Certain values ​​are not limited to those listed. However, even if the following description is given, the present invention is not necessarily limited to the above description.

[0228] As another specific example, for a certain value, for example, "It is preferable that a certain voltage is 10 V" In that case, for example, if a certain voltage is between -2V and 1V, It is possible to define an aspect of the invention as "except when, for example, It is possible to provide an aspect of the invention that excludes cases where the voltage is 13V or greater.

[0229] As another specific example, when describing the properties of a certain substance, for example, "a certain film is an insulating film," In that case, the insulating film is, for example, an organic insulating film. Alternatively, the insulating film may be an inorganic insulating film. It is possible to define an embodiment of the invention as excluding the case of a velum. Or, for example, It is possible to specify one embodiment of the invention so that the film does not include a conductive film. For example, one embodiment of the invention may be stipulated as excluding the case where the film is a semiconductor film. It is Noh.

[0230] As another specific example, regarding a certain laminated structure, for example, "between film A and film B, a certain film is In that case, for example, if the film is a laminate of four or more layers, Or, for example, the invention can be defined as "excluding the case where the film is a multi-layer film." It is possible to define the invention as excluding the case where a conductive film is provided between the film and the .

[0231] In this specification, the terms "active elements" and "passive elements" are used interchangeably. For all terminals of devices (capacitive elements, resistive elements, etc.), the connection destination is not specified. However, a person skilled in the art may be able to configure one aspect of the invention. Even if the destination is not specified, one aspect of the invention is clear. When the contents are described in this specification, etc., one aspect of the invention that does not specify a connection destination is the same as the embodiment of the present specification. In particular, when the terminals are connected to multiple If such a case is considered, there is no need to limit the connection destination of the terminal to a specific location. Therefore, there are active elements (transistors, diodes, etc.) and passive elements (capacitive elements, resistive elements, etc.) By specifying the connection destinations of only some of the terminals of a device (e.g., It may be possible to configure one embodiment.

[0232] In this specification and the like, if at least the connection destination of a certain circuit is specified, it is understood by those skilled in the art that If you are a person who has experience in the field of electronics, you may be able to identify the invention. In some cases, a person skilled in the art can identify an invention by at least specifying the function. In other words, if a function is specified, it can be said that one aspect of the invention is clear. It may be possible to determine that one aspect of the invention is described in the present specification. Therefore, even if the function of a circuit is not specified, if the connection destination is specified, it can be considered as an embodiment of the invention. and can constitute one embodiment of the invention. For a certain circuit, even if the connection destination is not specified, if the function is specified, it can be considered as one aspect of the invention. What is disclosed can constitute an embodiment of the invention.

[0233] In addition, in this specification and the like, in the drawings or text described in a certain embodiment, it is possible to extract a part thereof to constitute an aspect of the invention. Therefore, when a drawing or text describing a certain part is described, the content obtained by extracting a part of the drawing or text thereof is also disclosed as an aspect of the invention and is assumed to be able to constitute an aspect of the invention. And it can be said that one aspect of the invention is clear. Therefore, for example, in drawings or text in which one or more active elements (such as transistors and diodes), wirings, passive elements (such as capacitor elements and resistor elements), conductive layers, insulating layers, semiconductor layers, organic materials, inorganic materials, components, devices, operation methods, manufacturing methods, etc. are described, it is assumed that a part thereof can be extracted to constitute an aspect of the invention. For example, from a circuit diagram composed of N (N is an integer) circuit elements (such as transistors and capacitor elements), M (M is an integer and M < N) circuit elements (such as transistors and capacitor elements) can be extracted to constitute an aspect of the invention. As another example, from a cross-sectional view composed of N (N is an integer) layers, M (M is an integer and M < N) layers can be extracted to constitute an aspect of the invention. As yet another example, from a flowchart composed of N (N is an integer) elements, M (M is an integer and M < N) elements can be extracted to constitute an aspect of the invention. As yet another example, from a text described as "A has B, C, D, E, or F", by arbitrarily extracting some elements, "A has B and E", "A has E and F", "A has C, E, and F", etc. can be obtained. Furthermore, from the text described as "A has B, C, D, E, or F", by arbitrarily extracting some elements, "A has Or, it is possible to construct an aspect of the invention such as "A has B, C, D, and E." It is.

[0234] In this specification, etc., in a drawing or text described in a certain embodiment, When at least one specific example is described, it is not possible to derive a generic concept of that specific example. It will be easily understood by those skilled in the art. When at least one specific example is described in a figure or text, the general outline of that specific example is The invention is also disclosed as an embodiment of the invention and may constitute an embodiment of the invention. And one aspect of the invention can be said to be clear.

[0235] In this specification, at least the contents shown in the drawings (or even a part of the drawings) This is disclosed as one aspect of the invention and can constitute one aspect of the invention. Therefore, if something is shown in a diagram, it does not need to be explained in words. However, the contents are disclosed as one aspect of the invention and constitute one aspect of the invention. Similarly, a part of the drawings may be regarded as an embodiment of the invention. This is disclosed as one embodiment of the present invention. It can be said that one aspect of the invention is clear. [Explanation of symbols]

[0236] 22 Insulating film 26 Insulating Film 27 Insulating Film 28 Nitride insulating film 29 Insulating Film 31 Substrate 40 Conductive Film 41 Oxide Semiconductor Film 41a Oxide semiconductor film 41b Oxide semiconductor film 41c Oxide semiconductor film 42 Metal oxide film 43 Conductive Film 44 Conductive Film 45 Conductive Film 46 Substrate 47 Shielding membrane 48 Colored layer 50 Resin Film 51 Orientation film 52 Orientation film 53 Liquid crystal layer 55 pixels 56 Transistor 57 Capacitive element 58 Opening 59 Conductive Film 60 Liquid crystal element 61 Conductive Film 62 Opening 70 Semiconductor display device 71 Pixel section 72 Drive circuit 73 Drive circuit 75 Shift Register 76 Shift Register 77 Switch Circuit 95 Transistors 96 Transistors 97 Capacitive element 98 Light emitting element 100 sequential circuits 101 Transistor 102 Transistor 103 Transistor 104 Transistor 105 Transistor 105A Transistor 105B Transistor 106 Transistor 107 Transistor 111 Wiring 112 Wiring 113 Wiring 114 Wiring 115 Wiring 117 Wiring 118 Wiring 119 Wiring 121 Wiring 122 Wiring 123 Wiring 124 Wiring 125 Wiring 4001 Substrate 4002 Pixel section 4003 Drive circuit 4004 Drive circuit 4005 Encapsulating material 4006 Substrate 4010 Transistor 4018 FPC 4020 Insulating film 4021 Pixel electrode 4023 Liquid crystal element 4028 Liquid crystal layer 4030 Wiring 4050 Conductive film 4059 Resin film 4060 Common electrode 4061 Conductive particles 4062 Resin film 5001 Case 5002 Case 5003 Display section 5004 Display section 5005 Microphone 5006 Speaker 5007 Operation key 5008 Stylus 5201 Case 5202 Display section 5203 Operation button 5204 Band 5401 Case 5402 Display section 5403 Keyboard 5404 Pointing Device 5601 Case 5602 Case 5603 Display section 5604 Display section 5605 Connection 5606 Operation key 5801 Case 5802 Case 5803 Display section 5804 Operation key 5805 Lens 5806 Connection 5901 Case 5902 Display section 5903 Camera 5904 Speaker 5905 Button 5906 External connection part 5907 Mike

Claims

Claim 1: having a first transistor to a seventh transistor, and a first wiring to a sixth wiring, One of the source or drain of the first transistor is always in conduction with the first wiring, The other of the source or drain of the first transistor is always in conduction with the second wiring, One of the source or drain of the second transistor is always in conduction with the third wiring, The other of the source or drain of the second transistor is always in conduction with the first wiring, One of the source or drain of the third transistor is always in conduction with the third wiring, The other of the source or drain of the third transistor is always in conduction with one of the source or drain of the fourth transistor, The gate of the third transistor is always in conduction with the second wiring, The other of the source or drain of the fourth transistor is always in conduction with the gate of the seventh transistor, The gate of the fourth transistor is always in conduction with the gate of the second transistor, One of the source or drain of the fifth transistor is always in conduction with the gate of the seventh transistor, The other of the source or drain of the fifth transistor is always in conduction with the fourth wiring, The gate of the fifth transistor is always in conduction with the fifth wiring, One of the source or drain of the sixth transistor is always in conduction with the sixth wiring, The gate of the sixth transistor is always in conduction with the fifth wiring, One of the source or drain of the seventh transistor is always in conduction with the gate of the second transistor, The other of the source or drain of the seventh transistor is always in conduction with the fifth wiring, When the fourth wiring and the gate of the first transistor are in conduction through at least the channel formation region of the fifth transistor, the potential of the fourth wiring is input to the gate of the first transistor through at least the channel formation region of the fifth transistor, When the sixth wiring and the gate of the second transistor are in conduction through at least the channel formation region of the sixth transistor, the potential of the sixth wiring is input to the gate of the second transistor through at least the channel formation region of the sixth transistor. Semiconductor device.

2. It has the first transistor to the seventh transistor, and the first wiring to the sixth wiring, One of the source or drain of the first transistor is always in conduction with the first wiring, The other of the source or drain of the first transistor is always in conduction with the second wiring, One of the source or drain of the second transistor is always in conduction with the third wiring, The other of the source or drain of the second transistor is always in conduction with the first wiring, One of the source or drain of the third transistor is always in conduction with the third wiring, The other of the source or drain of the third transistor is always in conduction with one of the source or drain of the fourth transistor, The gate of the third transistor is always in conduction with the second wiring, The other of the source or drain of the fourth transistor is always in conduction with the gate of the seventh transistor, The gate of the fourth transistor is always in conduction with the gate of the second transistor, One of the source or drain of the fifth transistor is always in conduction with the gate of the seventh transistor, The other of the source or drain of the fifth transistor is always in conduction with the fourth wiring, The gate of the fifth transistor is always in conduction with the fifth wiring, One of the source or drain of the sixth transistor is always in conduction with the sixth wiring, The gate of the sixth transistor is always in conduction with the fifth wiring, One of the source or drain of the seventh transistor is always in conduction with the gate of the second transistor, The other of the source or drain of the seventh transistor is always in conduction with the fifth wiring, When the fourth wiring and the gate of the first transistor are in conduction at least through the channel formation region of the fifth transistor, the potential of the fourth wiring is input to the gate of the first transistor at least through the channel formation region of the fifth transistor, When the sixth wiring and the gate of the second transistor are electrically connected through at least the channel formation region of the sixth transistor, the potential of the sixth wiring is input to the gate of the second transistor through at least the channel formation region of the sixth transistor. The first wiring is always electrically connected to the gate of the transistor included in the first pixel. A first clock signal is input to the second wiring. A first power supply voltage is input to the third wiring. The fourth wiring is always electrically connected to the gate of the transistor included in the second pixel. A second clock signal is input to the fifth wiring. A second power supply voltage is input to the sixth wiring. A semiconductor device. According to claim 3, a semiconductor device comprising first to seventh transistors, and first to sixth wirings, One of the source and drain of the first transistor is always electrically connected to the first wiring. The other of the source and drain of the first transistor is always electrically connected to the second wiring. One of the source and drain of the second transistor is always electrically connected to the third wiring. The other of the source and drain of the second transistor is always electrically connected to the first wiring. One of the source and drain of the third transistor is always electrically connected to the third wiring. The other of the source and drain of the third transistor is always electrically connected to one of the source and drain of the fourth transistor. The gate of the third transistor is always electrically connected to the second wiring. The other of the source and drain of the fourth transistor is always electrically connected to the gate of the seventh transistor. The gate of the fourth transistor is always electrically connected to the gate of the second transistor. One of the source and drain of the fifth transistor is always electrically connected to the gate of the seventh transistor. The other of the source and drain of the fifth transistor is always electrically connected to the fourth wiring. The gate of the fifth transistor is always electrically connected to the fifth wiring. One of the source and drain of the sixth transistor is always electrically connected to the sixth wiring. The gate of the sixth transistor is always electrically connected to the fifth wiring. One of the source or drain of the seventh transistor is always in conduction with the gate of the second transistor, The other of the source or drain of the seventh transistor is always in conduction with the fifth wiring, When the fourth wiring and the gate of the first transistor are in conduction through at least the channel formation region of the fifth transistor, the potential of the fourth wiring is input to the gate of the first transistor through at least the channel formation region of the fifth transistor, When the sixth wiring and the gate of the second transistor are in conduction through at least the channel formation region of the sixth transistor, the potential of the sixth wiring is input to the gate of the second transistor through at least the channel formation region of the sixth transistor, The fifth transistor has a larger ratio of channel width to channel length than the sixth transistor. Semiconductor device.

4. Having the first transistor to the seventh transistor, and the first wiring to the sixth wiring, One of the source or drain of the first transistor is always in conduction with the first wiring, The other of the source or drain of the first transistor is always in conduction with the second wiring, One of the source or drain of the second transistor is always in conduction with the third wiring, The other of the source or drain of the second transistor is always in conduction with the first wiring, One of the source or drain of the third transistor is always in conduction with the third wiring, The other of the source or drain of the third transistor is always in conduction with one of the source or drain of the fourth transistor, The gate of the third transistor is always in conduction with the second wiring, The other of the source or drain of the fourth transistor is always in conduction with the gate of the seventh transistor, The gate of the fourth transistor is always in conduction with the gate of the second transistor, One of the source or drain of the fifth transistor is always in conduction with the gate of the seventh transistor, The other of the source or drain of the fifth transistor is always in conduction with the fourth wiring, The gate of the fifth transistor is always in conduction with the fifth wiring. One of the source or drain of the sixth transistor is always in conduction with the sixth wiring. The gate of the sixth transistor is always in conduction with the fifth wiring. One of the source or drain of the seventh transistor is always in conduction with the gate of the second transistor. The other of the source or drain of the seventh transistor is always in conduction with the fifth wiring. When the fourth wiring and the gate of the first transistor are in conduction through at least the channel formation region of the fifth transistor, the potential of the fourth wiring is input to the gate of the first transistor through at least the channel formation region of the fifth transistor. When the sixth wiring and the gate of the second transistor are in conduction through at least the channel formation region of the sixth transistor, the potential of the sixth wiring is input to the gate of the second transistor through at least the channel formation region of the sixth transistor. The first wiring is always in conduction with the gate of the transistor included in the first pixel. A first clock signal is input to the second wiring. A first power supply voltage is input to the third wiring. The fourth wiring is always in conduction with the gate of the transistor included in the second pixel. A second clock signal is input to the fifth wiring. A second power supply voltage is input to the sixth wiring. The fifth transistor has a larger ratio of channel width to channel length than the sixth transistor. Semiconductor device.

5. Having first to seventh transistors and first to sixth wirings, One of the source or drain of the first transistor is electrically connected to the first wiring. The other of the source or drain of the first transistor is electrically connected to the second wiring. One of the source or drain of the second transistor is electrically connected to the third wiring. The other of the source or drain of the second transistor is electrically connected to the first wiring. One of the source or drain of the third transistor is electrically connected to the third wiring. The other of the source or drain of the third transistor is electrically connected to one of the source or drain of the fourth transistor. The gate of the third transistor is electrically connected to the second wiring. The other of the source or drain of the fourth transistor is electrically connected to the gate of the seventh transistor. The gate of the fourth transistor is electrically connected to the gate of the second transistor. One of the source or drain of the fifth transistor is electrically connected to the gate of the seventh transistor. The other of the source or drain of the fifth transistor is electrically connected to the fourth wiring. The gate of the fifth transistor is electrically connected to the fifth wiring. One of the source or drain of the sixth transistor is electrically connected to the sixth wiring. The other of the source or drain of the sixth transistor is electrically connected to the gate of the second transistor. The gate of the sixth transistor is electrically connected to the fifth wiring. One of the source or drain of the seventh transistor is electrically connected to the gate of the second transistor. The other of the source or drain of the seventh transistor is electrically connected to the fifth wiring. The gate of the seventh transistor is electrically connected to the gate of the first transistor. Semiconductor device. **Claim 6**: A semiconductor device having first to seventh transistors and first to sixth wirings, One of the source or drain of the first transistor is electrically connected to the first wiring. The other of the source or drain of the first transistor is electrically connected to the second wiring. One of the source or drain of the second transistor is electrically connected to the third wiring. The other of the source or drain of the second transistor is electrically connected to the first wiring. One of the source or drain of the third transistor is electrically connected to the third wiring. The other of the source or drain of the third transistor is electrically connected to one of the source or drain of the fourth transistor. The gate of the third transistor is electrically connected to the second wiring. The other of the source or drain of the fourth transistor is electrically connected to the gate of the seventh transistor. The gate of the fourth transistor is electrically connected to the gate of the second transistor, One of the source or drain of the fifth transistor is electrically connected to the gate of the seventh transistor, The other of the source or drain of the fifth transistor is electrically connected to the fourth wiring, The gate of the fifth transistor is electrically connected to the fifth wiring, One of the source or drain of the sixth transistor is electrically connected to the sixth wiring, The other of the source or drain of the sixth transistor is electrically connected to the gate of the second transistor, The gate of the sixth transistor is electrically connected to the fifth wiring, One of the source or drain of the seventh transistor is electrically connected to the gate of the second transistor, The other of the source or drain of the seventh transistor is electrically connected to the fifth wiring, The gate of the seventh transistor is electrically connected to the gate of the first transistor, The first wiring is electrically connected to the gate of the transistor included in the first pixel, A first clock signal is input to the second wiring, A first power supply voltage is input to the third wiring, The fourth wiring is electrically connected to the gate of the transistor included in the second pixel, A second clock signal is input to the fifth wiring, A second power supply voltage is input to the sixth wiring, A semiconductor device.

7. A semiconductor device having first to seventh transistors and first to sixth wirings, One of the source or drain of the first transistor is electrically connected to the first wiring, The other of the source or drain of the first transistor is electrically connected to the second wiring, One of the source or drain of the second transistor is electrically connected to the third wiring, The other of the source or drain of the second transistor is electrically connected to the first wiring, One of the source or drain of the third transistor is electrically connected to the third wiring, The other of the source or drain of the third transistor is electrically connected to one of the source or drain of the fourth transistor, The gate of the third transistor is electrically connected to the second wiring, The other of the source or drain of the fourth transistor is electrically connected to the gate of the seventh transistor, The gate of the fourth transistor is electrically connected to the gate of the second transistor, One of the source or drain of the fifth transistor is electrically connected to the gate of the seventh transistor, The other of the source or drain of the fifth transistor is electrically connected to the fourth wiring, The gate of the fifth transistor is electrically connected to the fifth wiring, One of the source or drain of the sixth transistor is electrically connected to the sixth wiring, The other of the source or drain of the sixth transistor is electrically connected to the gate of the second transistor, The gate of the sixth transistor is electrically connected to the fifth wiring, One of the source or drain of the seventh transistor is electrically connected to the gate of the second transistor, The other of the source or drain of the seventh transistor is electrically connected to the fifth wiring, The gate of the seventh transistor is electrically connected to the gate of the first transistor, The fifth transistor has a larger ratio of channel width to channel length than the sixth transistor, Semiconductor device.

8. Having a first transistor to a seventh transistor and first wiring to sixth wiring, One of the source or drain of the first transistor is electrically connected to the first wiring, The other of the source or drain of the first transistor is electrically connected to the second wiring, One of the source or drain of the second transistor is electrically connected to the third wiring, The other of the source or drain of the second transistor is electrically connected to the first wiring, One of the source or drain of the third transistor is electrically connected to the third wiring, The other of the source or drain of the third transistor is electrically connected to one of the source or drain of the fourth transistor, The gate of the third transistor is electrically connected to the second wiring, The other of the source or drain of the fourth transistor is electrically connected to the gate of the seventh transistor, the gate of the fourth transistor is electrically connected to the gate of the second transistor, one of the source or drain of the fifth transistor is electrically connected to the gate of the seventh transistor, the other of the source or drain of the fifth transistor is electrically connected to the fourth wiring, the gate of the fifth transistor is electrically connected to the fifth wiring, one of the source or drain of the sixth transistor is electrically connected to the sixth wiring, the other of the source or drain of the sixth transistor is electrically connected to the gate of the second transistor, the gate of the sixth transistor is electrically connected to the fifth wiring, one of the source or drain of the seventh transistor is electrically connected to the gate of the second transistor, the other of the source or drain of the seventh transistor is electrically connected to the fifth wiring, the gate of the seventh transistor is electrically connected to the gate of the first transistor, the first wiring is electrically connected to the gate of the transistor included in the first pixel, a first clock signal is input to the second wiring, a first power supply voltage is input to the third wiring, the fourth wiring is electrically connected to the gate of the transistor included in the second pixel, a second clock signal is input to the fifth wiring, a second power supply voltage is input to the sixth wiring, the fifth transistor has a larger ratio of channel width to channel length than the sixth transistor, a semiconductor device.

9. In any one of Claims 1 to 8, all of the first transistor to the seventh transistor have the same polarity, a semiconductor device.

Images