Semiconductor device

Abstract

To provide a semiconductor device which can reduce power consumption and which has less number of transistors.SOLUTION: A semiconductor device has: a first transistor in which one of a source and drain is electrically connected with first wiring and the other of the source and the drain is electrically connected with second wiring; a second transistor in which one of a source and a drain is electrically connected with the first wiring and a gate is electrically connected with a gate of the first transistor; and a capacitive element in which one electrode is electrically connected with third wiring and the other electrode is electrically connected with the other of the source and the drain of the second transistor.SELECTED DRAWING: Figure 16

Description

[Technical field]

[0001] One embodiment of the present invention relates to a semiconductor device and a display device. [Background technology]

[0002] As display devices such as liquid crystal display devices and EL display devices become larger, more value-added display devices are required. In particular, the development of display device driver circuits that use only one conductivity type transistor is being Technical development for constructing such a system is being actively promoted (see Patent Document 1 and Non-Patent Document 1).

[0003] FIG. 17(A) shows a driving circuit disclosed in Patent Document 1. is generated by transistors M1, M2, M3 and M4. When the signal IN is at a high level, the transistor M1 is turned off. This causes the transistors M2, M3, and M4 to turn on. On the other hand, when the signal IN is at a low level, the Transistor M1 is turned on, transistor M2 and transistor M4 are turned off, and transistor M1 is turned on. Transistor M3 turns on once and then turns off. Then, the signal OUT becomes low level. .

[0004] FIG. 17(B) shows the driving circuit disclosed in Non-Patent Document 1. The circuit is composed of transistors M11 to M19, a capacitance element C11, etc. When the signal IN is at a high level, the transistors M12 and M 14, transistor M16 and transistor M17 are turned on, and transistor M11, Transistor M13 and transistor M15 are turned off, and transistor M18 and transistor Transistor M19 turns on once and then turns off. Then, the signal OUT goes low. On the other hand, when the signal IN is at a low level, the transistor M12 and the transistor M14, transistor M16, transistor M17 and transistor M18 are turned off. , transistor M11, transistor M15 and transistor M19 are turned on, and transistor M1 3 turns on once and then turns off. Then, the signal OUT becomes high level. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2002-328643 A [Non-patent literature]

[0006] [Non-Patent Document 1] Eri Fukumoto, Toshiaki Arai, Narihiro Morosawa, Kazuhiko Tokunaga, Yasuhiro Terai,Takashige Fujimori and Tatsuya Sasaoka, "High Mobility Oxide Semiconductor TFT for Circuit Integration of AM-OLED", IDW'10, pp.631-634 Summary of the Invention [Problem to be solved by the invention]

[0007] In the driving circuit of Patent Document 1, when the signal IN becomes high level, the transistor M3 and the transistor Therefore, during the period when the signal IN is at a high level, In this case, the transistors M3 and M4 are connected to the wiring to which the potential VDD is supplied. In turn, current continues to flow through the wiring to which the potential VSS is supplied, resulting in increased power consumption. was.

[0008] In addition, in the driving circuit of Patent Document 1, during the period when the signal IN is at a high level, It was necessary to lower the potential of the gate of transistor M1 to a level that would turn transistor M1 off. To this end, W (W: channel width) / L (L: channel length) of transistor M4 is It was necessary to make the W / L of the resistor M3 sufficiently larger, but this was not necessarily easy. This is because if the W / L of transistor M3 is increased, the W / L of transistor M4 also This is because the layout area increases because the signal I During the period when N is at a high level, the transistor M3 turns on and transistor M2 turns on the potential VDD. When a voltage is supplied to the gate of the transistor M1, the potential of the gate of the transistor M1 is set to a predetermined potential. This resulted in a longer time for the transistor M1 to turn on. The transition time becomes slower and the Vgs of the transistor M1 becomes smaller, so the rising edge of the signal OUT This caused delays or distortions in the signal OUT.

[0009] In addition, in the drive circuit of Non-Patent Document 1, as is clear from a comparison with the drive circuit of Patent Document 1, , a large number of elements such as transistors and capacitors are required.

[0010] In view of this, in one embodiment of the present invention, a current flowing between wirings of a circuit through a transistor is suppressed, One of the objectives is to reduce the power consumption of the circuit. One of the objectives is to shorten the delay time and suppress the delay or distortion of the output signal. One of the objectives is to reduce the number of elements such as transistors and capacitors in the circuit. One of the objectives is to provide a circuit configuration. Note that the objective is inextricably linked to the effect, When describing an effect in this specification, etc., it is self-evident that there is a problem corresponding to that effect. Conversely, when a problem is described in this specification, etc., it is assumed that an effect corresponding to the problem is achieved. This is self-evident. [Means for solving the problem]

[0011] In one embodiment of the present invention, one of a source and a drain is electrically connected to a first wiring. a first transistor, the other of which is electrically connected to a second wiring; One of the drain and the gate is electrically connected to the first wiring, and the gate is the gate of the first transistor. a second transistor electrically connected to the first wiring and a third wiring having one electrode electrically connected to the second wiring; and the other electrode is electrically connected to the other of the source and drain of the second transistor. and a capacitive element.

[0012] In the above embodiment of the present invention, the W / L (W is the channel width, L is the channel length) may be greater than W / L of the second transistor.

[0013] In the above embodiment of the present invention, the first transistor and the second transistor are the same. The conductivity types may be the same. Effect of the Invention

[0014] One aspect of the present invention is to suppress a current flowing between wirings of a circuit through a transistor, thereby reducing the power consumption of the circuit. It is possible to reduce power consumption and shorten the rise time of the output signal from the circuit. This makes it possible to suppress delay or distortion of the output signal. The number of elements such as capacitors and capacitance elements can be reduced. [Brief description of the drawings]

[0015] [Figure 1] FIG. 1 illustrates an inverter circuit according to one embodiment of the present invention. [Diagram 2] FIG. 1 illustrates an inverter circuit according to one embodiment of the present invention. [Diagram 3] FIG. 1 illustrates an inverter circuit according to one embodiment of the present invention. [Figure 4] FIG. 1 illustrates a circuit used in an inverter circuit according to one embodiment of the present invention. [Diagram 5] FIG. 1 illustrates an inverter circuit according to one embodiment of the present invention. [Figure 6] FIG. 1 illustrates an inverter circuit according to one embodiment of the present invention. [Figure 7] FIG. 1 illustrates a shift register circuit according to one embodiment of the present invention. [Figure 8] FIG. 1 illustrates a shift register circuit according to one embodiment of the present invention. [Figure 9] FIG. 1 illustrates a shift register circuit according to one embodiment of the present invention. [Figure 10] FIG. 1 illustrates a shift register circuit according to one embodiment of the present invention. [Figure 11] FIG. 1 illustrates a shift register circuit according to one embodiment of the present invention. [Figure 12] 1A and 1B are diagrams illustrating a display device according to one embodiment of the present invention. [Figure 13] 1A to 1C are diagrams illustrating a transistor according to one embodiment of the present invention. [Figure 14] 1A and 1B are diagrams illustrating a display device according to one embodiment of the present invention. [Figure 15] 1A to 1C are diagrams illustrating electronic devices according to one embodiment of the present invention. [Figure 16] 1A to 1C are diagrams illustrating a semiconductor device according to one embodiment of the present invention. [Figure 17] FIG. 1 is a diagram for explaining a conventional driving circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] An embodiment of the present invention will be described below with reference to the accompanying drawings. The contents of the embodiments may be modified without departing from the spirit and scope of the present invention. It would be easy for a person skilled in the art to understand. Therefore, the present invention is not limited to the description of the following embodiments. It won't be done.

[0017] (Embodiment 1) In this embodiment, an inverter circuit (also referred to as a semiconductor device or a driver circuit) according to one embodiment of the present invention will be described. This section explains what is meant by "

[0018] The configuration of an inverter circuit of this embodiment will be described with reference to FIG.

[0019] The inverter circuit in FIG. 1A includes a circuit 100 and a circuit 200. The circuit 100 includes , the wiring 11, the wiring 12, the wiring 13, the wiring 14, and the circuit 200. The wiring 200 is connected to the wiring 11 , the wiring 13 , the wiring 14 , and the circuit 100 .

[0020] The circuit 100 includes a transistor 101 and a transistor 102. A first terminal (also referred to as one of the source and drain) of 101 is connected to a wiring 11. A second terminal (also referred to as the other of the source and drain) of the transistor 101 is connected to the wiring 12. A first terminal of the transistor 102 is connected to the wiring 13. The second terminal is connected to a wiring 12 , and the gate of the transistor 102 is connected to a wiring 14 .

[0021] The circuit 200 includes a transistor 201, a transistor 202, a transistor 203, A first terminal of the transistor 201 is connected to the wiring 11. The gate of the transistor 201 is connected to the gate of the transistor 101. A first terminal of the transistor 202 is connected to the wiring 13, and a second terminal of the transistor 202 is connected to the wiring 13. The gate of the transistor 202 is connected to the second terminal of the transistor 201, and the gate of the transistor 202 is connected to the wiring 14. A first terminal of the transistor 203 is connected to the wiring 13, and a second terminal of the transistor 203 is connected to the wiring 13. The terminal of the transistor 201 is connected to the gate of the transistor 203. The gate of the transistor 203 is connected to the wiring 1. A first electrode (also referred to as one electrode) of the capacitor 204 is connected to the wiring 14. The second electrode (also referred to as the other electrode) of the capacitor 204 is connected to the second This is connected to the terminal.

[0022] The gate of the transistor 101, the gate of the transistor 201, and the gate of the transistor 203 A connection point between the second terminal of the transistor 201 and the second terminal of the transistor 202 is indicated as a node N1. The connection point between the second terminal of the transistor 202 and the second electrode of the capacitor 204 is a node Denoted as N2.

[0023] Note that the transistors included in the inverter circuit of this embodiment mode are of the same conductivity type. For example, in the inverter circuit of FIG. The transistors 102, 201, 202 and 203 are of the same conductor. In this embodiment, the transistor 101 and the transistor 10 2. The transistor 201, the transistor 202, and the transistor 203 are N-channel types. One case will now be described.

[0024] In this specification, the term "connection" means electrical connection, and does not include current, voltage, potential, signal, etc. Therefore, "connected" means that In addition to the direct connection, for example, wiring, conductive film, resistors, diodes, transistors This also includes indirect connections via elements such as inverters and switching elements. .

[0025] A potential VDD is supplied to the wiring 11 (also called a power supply line), and the wiring 11 transmits the potential VDD. The potential VDD is a constant potential.

[0026] A potential VSS is supplied to the wiring 13 (also referred to as a power supply line). The potential VSS is a constant potential and is less than the potential VDD.

[0027] A signal IN is input to the wiring 14 (also called a signal line), and the wiring 14 has a function of transmitting the signal IN. The signal IN is an input signal to the inverter circuit in FIG. 1(A). indicates whether the transistors 102, 202, and 203 are conductive or non-conductive. This is a signal for controlling the

[0028] A signal OUT is output from the wiring 12 (also called a signal line), and the wiring 12 transmits the signal OUT. The signal OUT is the output signal of the inverter circuit in FIG.

[0029] Note that the signals or potentials applied to the wirings 11, 13, and 14 are not limited to those described above. Various signals, potentials, etc. can also be input.

[0030] The circuit 100 (also referred to as a buffer circuit) changes the potential of the wiring 11 in response to an output signal from the circuit 200. The circuit 100 has a function of supplying a voltage VDD to the wiring 12. The circuit 100 has a function of supplying the potential VSS of the line 13 to the wiring 12. In response to the output signal of 0 and the signal IN, the potential VDD of the wiring 11 and the potential VSS of the wiring 13 are One of them is supplied to the wiring 12 .

[0031] The circuit 200 (also referred to as a control circuit) controls the potential V A function for generating a signal (potential of node N1) for controlling the timing of supplying DD to wiring 12 Possesses the ability.

[0032] The transistor 101 has a function of controlling electrical continuity or non-conduction between the wiring 11 and the wiring 12 . The transistor 101 has a function of supplying the potential VDD of the wiring 11 to the wiring 12 . The transistor 101 has a function of holding the potential difference between the wiring 12 and the node N1.

[0033] The transistor 102 has a function of controlling electrical continuity or non-conduction between the wiring 13 and the wiring 12 . The transistor 102 has a function of supplying the potential VSS of the wiring 13 to the wiring 12 .

[0034] The transistor 201 has a function of controlling conduction or non-conduction between the wiring 11 and the node N2. The transistor 201 has a function of supplying the potential VDD of the wiring 11 to the node N2. The transistor 201 has a function of holding the potential difference between the node N1 and the node N2. do.

[0035] The transistor 202 has a function of controlling conduction or non-conduction between the wiring 13 and the node N2. The transistor 202 has a function of supplying the potential VSS of the wiring 13 to the node N2. do.

[0036] The transistor 203 has a function of controlling conduction or non-conduction between the wiring 13 and the node N1. The transistor 203 has a function of supplying the potential VSS of the wiring 13 to the node N1. do.

[0037] The capacitor 204 has a function of holding the potential difference between the wiring 14 and the node N2.

[0038] Next, an example of a method for driving the inverter circuit of FIG. 1(A) will be described with reference to FIG. 1(B). FIG. 1B is a timing chart for explaining a method of driving the inverter circuit of FIG. 1A. An example of a mapping chart is shown below.

[0039] The high-level potential of the signal IN is equal to the potential VDD, and the low-level potential is equal to the potential VS The explanation will be given assuming that the signal IN is a digital signal equal to S. Also, the signal IN is at a high level. The case where the signal IN is at a low level will be described separately.

[0040] First, when the signal IN goes high, the transistor 102 and the transistor 202 And transistor 203 turns on.

[0041] When the transistor 203 is turned on, the potential VSS of the wiring 13 is supplied to the node N1. Therefore, the potential of the node N1 falls to the potential VSS. When it drops, transistor 101 and transistor 201 turn off.

[0042] When the transistor 202 is turned on, the potential VSS of the wiring 13 is supplied to the node N2. As a result, the potential of the node N2 drops to the potential VSS.

[0043] When the transistor 102 is turned on, the potential VSS of the wiring 13 is supplied to the wiring 12. Therefore, the potential of the wiring 12 drops to the potential VSS. become.

[0044] Next, when the signal IN goes low, the transistor 102 and the transistor 202 And transistor 203 is turned off.

[0045] When the transistor 203 is turned off, the node N1 is in a floating state. Since the potential of the transistor 101 remains at the potential VSS, the transistor 201 is turned on. It will remain as is.

[0046] When the transistor 202 is turned off, the node N2 is in a floating state. The capacitance element 204 is connected to the wiring 14, the node N2, and the line 14 during the period when the signal IN is at a high level. Therefore, when the signal IN goes low, the potential difference between the nodes The potential of the node N2 also drops. When the potential drops below the threshold voltage of the transistor 201, the transistor 201 turns on. become.

[0047] When the transistor 201 is turned on, the potential VDD of the wiring 11 is supplied to the node N2. As a result, the potential of the node N2 rises. When the transistor 202 is turned off, the voltage between the node N1 and the node N2 is Therefore, as the potential of the node N2 rises, the potential of the node N1 also The potential of the node N2 rises to the potential VDD, and the potential of the node N1 rises to a potential lower than the potential VDD. This is the so-called bootstrap operation. The rising potential turns on transistor 101.

[0048] When the transistor 101 is turned on, the potential VDD of the wiring 11 is supplied to the wiring 12. As described above, the potential of the node N1 is higher than the potential VDD. The potential of the signal OUT rises to the potential VDD. That is, the signal OUT becomes high level.

[0049] As described above, the inverter circuit in FIG. There is no period during which both transistors 201 and 02 are on at the same time. There is no period during which both 202 and 203 are on at the same time. This eliminates the need for a continuous current path. Also, fewer transistors are used than in conventional drive circuits. With this number of inputs, the high-level potential of the signal OUT can be raised to the potential VDD of the wiring 11. Cut.

[0050] When the signal IN is at a low level, the voltage of the second terminal of the transistor 201 is As the potential of the second terminal of the transistor 101 increases, the potential of the second terminal of the transistor 101 increases. Accordingly, the potential of the node N1 rises. This shortens the time it takes for transistor 101 to turn on. In addition, the potential of the node N1 can be increased. Therefore, the Vgs of the transistor 101 can be increased. In the circuit, the timing at which the transistor 101 turns on can be advanced. The fact that the Vgs of the transistor 101 can be increased synergistically acts to increase the The rise time of T can be significantly reduced.

[0051] Next, an inverter circuit different from that shown in FIG. 1A will be described with reference to FIGS. 2 to 6. .

[0052] First, the inverter circuit of FIG. 2A is obtained by adding a circuit 300A to the inverter circuit of FIG. It is a structure of.

[0053] A first terminal (also referred to as an input terminal) of the circuit 300A is connected to the wiring 14. The second terminal (also referred to as an output terminal) is connected to the gate of the transistor 203 .

[0054] The circuit 300A outputs a signal corresponding to a signal (for example, a signal IN) input to a first terminal to a second terminal. The circuit 300A has a function of outputting a signal from the first terminal. It has a function of outputting a delayed and / or corrupted signal from a second terminal.

[0055] For example, the second signal is delayed more than the first signal when the first signal is The timing when the second signal rises is more important than the timing when the first signal rises or falls. For example, the timing of the first signal is slower than that of the second signal. The second signal is said to be dull if the rise time or fall time of the first signal is This means that the rise time or fall time of the first signal is longer than the rise time or fall time of the second signal.

[0056] In the inverter circuit of FIG. 2(A), even if the signal IN goes from high to low, For a certain period of time, the signal output from the second terminal of the circuit 300A remains at a high level. In other words, even if the signal IN goes from high to low, the transistor remains in the ON state for a certain period of time. The transistor 203 remains on, and the potential VSS remains supplied to the node N1.

[0057] Therefore, in the inverter circuit of FIG. 2A, the potential of the node N2 is equal to the capacitance of the capacitor 204. When the potential VSS of the wiring 13 is lowered by the capacitance coupling, the potential VSS of the wiring 13 can be supplied to the node N1. Therefore, the potential of the node N1 is prevented from decreasing as the potential of the node N2 decreases. That is, the potential difference between the node N1 and the node N2 can be increased. If the potential difference between the nodes N1 and N2 can be increased, the potential of the node N2 can be increased. When the potential of the transistor reaches the potential VDD, the potential of the node N1 can be made higher. Therefore, the rise time of the signal OUT can be increased. can be shortened.

[0058] In the inverter circuit of FIG. 2A, the first electrode of the capacitor 204 is connected to the A may be connected to the second terminal of A.

[0059] Next, the inverter circuit of FIG. 2B is obtained by adding a circuit 300B to the inverter circuit of FIG. 2A. It is a structure of.

[0060] A first terminal of the circuit 300B is connected to the wiring 14, and a second terminal of the circuit 300B is connected to a capacitance element 204 is connected to the first electrode of the sensor 204 .

[0061] The circuit 300B has the same function as the circuit 300A. However, the second terminal of the circuit 300B The signal output from the first terminal of the circuit 300A is delayed with respect to the signal output from the second terminal of the circuit 300A. It is preferable that the material is not aged and / or not stale.

[0062] In the inverter circuit of FIG. 2(B), even if the signal IN goes from high to low, A signal output from the second terminal of the circuit 300A and the second terminal of the circuit 300B for a certain period of time. In other words, when the signal IN goes from high to low, However, the transistor 203 remains on for a predetermined period, and the potential VSS is applied to the node N1. In addition, the signal input to the first electrode of the capacitor 204 is kept supplied for a predetermined period. The number will remain at a high level.

[0063] After that, the signal output from the second terminal of the circuit 300B changes from high level to low level. However, the signal output from the circuit 300A remains at a high level for a predetermined period of time. In other words, when the signal output from the second terminal of the circuit 300B changes from a high level to a low level, Even if the potential Vs is increased, the transistor 203 remains on for a predetermined period of time, and the node N1 is supplied with the potential Vs S remains supplied.

[0064] Therefore, in the inverter circuit of FIG. 2B, after the transistor 202 is turned off, In other words, the potential of the first electrode of the capacitor 204 can be reduced. After the node N2 is put into a floating state, the potential of the node N2 is lowered by the capacitive coupling of the capacitor 204. Therefore, the potential of the node N2 can be further lowered. As in the inverter circuit, the potential of the node N2 is lowered by the capacitive coupling of the capacitor 204. At this time, the potential VSS of the wiring 13 can be supplied to the node N1. As the potential at node N2 drops, the potential at node N1 can be prevented from dropping.

[0065] In addition, in the inverter circuit of FIG. 2B, the potential of the node N2 can be made lower. This synergistic effect is achieved by suppressing the potential at the node N1 from decreasing. Therefore, the potential difference between the node N1 and the node N2 can be increased. If the potential difference between node N2 and node N1 can be increased, the potential of node N2 will be equal to the potential VDD. The potential of the node N1 at the time of switching ON can be made higher, and the Vgs of the transistor 101 can be made higher. Therefore, the rise time of the signal OUT can be made shorter. can be done.

[0066] Next, the inverter circuit of FIG. 3A is obtained by adding a circuit 300C to the inverter circuit of FIG. 2A. It is a structure of.

[0067] A first terminal of the circuit 300C is connected to the wiring 14, and a second terminal of the circuit 300C is connected to the wiring 14. The first terminal of the capacitor 204 is connected to the first terminal of the capacitor 204 .

[0068] The circuit 300C has the same function as the circuit 300A.

[0069] In the inverter circuit of FIG. 3(A), even if the signal IN goes from high to low, A signal output from the second terminal of the circuit 300A and the second terminal of the circuit 300C for a certain period of time. In other words, when the signal IN goes from high to low, However, the transistor 203 remains on for a predetermined period, and the potential VSS is applied to the node N1. In addition, the signal input to the first electrode of the capacitor 204 is kept supplied for a predetermined period. The number will remain at a high level.

[0070] After that, the signal output from the second terminal of the circuit 300C changes from a high level to a low level. However, the signal output from the circuit 300A remains at a high level for a predetermined period of time. In other words, the signal output from the second terminal of the circuit 300C changes from a high level to a low level. Even if the potential Vs is increased, the transistor 203 remains on for a predetermined period of time, and the node N1 is supplied with the potential Vs S remains supplied.

[0071] Therefore, the inverter circuit in FIG. 3(A) operates in the same manner as the inverter circuit in FIG. 2(B). Therefore, the same effect as that of the inverter circuit of FIG. It can be played.

[0072] Furthermore, in the inverter circuit of FIG. 3A, the circuit 300A and the circuit 300C are connected in series. As a result, the signal output from the second terminal of the circuit 300A is The signal output from the second terminal is delayed and / or corrupted. As a result, it is possible to reduce the circuit scale of the circuit 300A or the size of the elements.

[0073] Next, the inverter circuit of FIG. 3B is a transistor 10 of the inverter circuit of FIG. The gate of transistor 202 is connected to the gate of transistor 203.

[0074] In the inverter circuit of FIG. 3B, the gate of the transistor 102 is connected directly to the The timing at which the transistor 102 is turned on is delayed compared to when the transistor 102 is connected to the wiring 14. Therefore, both the transistor 101 and the transistor 102 can be simultaneously In other words, the conduction current between the wiring 11 and the wiring 13 can be reduced. The current flow can be suppressed, and therefore power consumption can be reduced.

[0075] As in the inverter circuit of FIG. 3B, the inverter circuit of FIG. 2B or FIG. 3A may be In the inverter circuit, the gate of the transistor 102 is connected to the gate of the transistor 203. May be connected.

[0076] Here, a specific configuration example of the circuit 300A, the circuit 300B, and the circuit 300C will be described with reference to FIG. The following description will be given with reference to FIG. 4(A) to FIG. 4(F). FIG. 4(A) to FIG. 4(F) show a circuit 300A, a circuit 3 shows a circuit 300 that can be used for circuit 300B and circuit 300C.

[0077] A circuit 300 in FIG.

[0078] One terminal of the resistor element 301 is connected to a first terminal of the circuit 300, and the other terminal of the resistor element 301 is connected to a first terminal of the circuit 300. One terminal is connected to the second terminal of the circuit 300 .

[0079] The circuit 300 in FIG. 4B has a configuration in which a capacitor 302 is provided in addition to the circuit 300 in FIG. 4A. do.

[0080] A first electrode of the capacitor 302 is connected to the wiring 13, and a second electrode of the capacitor 302 is connected to the circuit 300 and the second terminal thereof.

[0081] Note that the first electrode of the capacitor 302 may be connected to the wiring 11, the wiring 14, or the like.

[0082] Note that the second electrode of the capacitor 302 may be connected to the first terminal of the circuit 300.

[0083] The circuit 300 in FIG.

[0084] A first terminal of the transistor 303 is connected to a first terminal of the circuit 300. The second terminal of the transistor 303 is connected to the second terminal of the circuit 300, and the gate of the transistor 303 is It is connected to wiring 11.

[0085] The circuit 300 in FIG. 4D has a configuration in which a transistor 304 is provided in the circuit 300 in FIG. 4C. It is.

[0086] The first terminal of the transistor 304 is connected to the first terminal of the circuit 300. The second terminal of the transistor 304 is connected to the second terminal of the circuit 300, and the gate of the transistor 304 is It is connected to a first terminal of the circuit 300.

[0087] In the circuit 300 of FIG. 4D, when the signal input to the first terminal is at a low level, When the first terminal When the signal input to the transistor 303 is at a high level, the transistor 304 and the transistor Both 304s are turned on.

[0088] Therefore, in the circuit 300 of FIG. 4D, the signal input to the first terminal is at a low level. In some cases, the signal can be delayed and output from the second terminal. When the signal input to the terminal is at high level, the signal is sent to the second It can be output from the terminal.

[0089] In addition, in the circuit 300 shown in FIG. 4A and FIG. 4B, the transistor 30 4 may be provided.

[0090] The circuit 300 in FIG. 4E is the same as the circuit 300 in FIG. 4C except that a transistor 305 is provided. It is.

[0091] A first terminal of the transistor 305 is connected to the wiring 11, and a second terminal of the transistor 305 is connected to the wiring 11. The gate of the transistor 305 is connected to the second terminal of the circuit 300. It is connected to terminal 1.

[0092] In the circuit 300 of FIG. 4E, when the signal input to the first terminal is at a low level, When the first terminal When the signal input to the transistor 303 is at a high level, the transistor 304 and the transistor Both 305s are on.

[0093] Therefore, the same effect as that of the circuit 300 in FIG. 4(D) can be achieved.

[0094] In addition, in the circuit 300 shown in FIG. 4A and FIG. 4B, the transistor 30 5 may be provided.

[0095] The circuit 300 of FIG. 4F is the circuit 300 of FIG. 4C, except that a transistor 306 and a transistor This configuration includes a star 307.

[0096] A first terminal of the transistor 306 is connected to the wiring 11, and a second terminal of the transistor 306 is connected to the wiring 11. The first terminal of the transistor 307 is connected to the second terminal of the circuit 300. 0, and the second terminal of transistor 307 is connected to the gate of transistor 306. The gate of the transistor 307 is connected to the wiring 11.

[0097] In the circuit 300 of FIG. 4F, when the signal input to the first terminal is at a low level, When the first terminal When the signal input to the transistor 303 is at a high level, the transistor 304 and the transistor In particular, when the signal input to the first terminal is at a high level, both of the first and second terminals 306 and 307 are turned on. In the first place, the potential of the gate of the transistor 306 is made higher than the potential VDD by the bootstrap operation. The potential is higher than that of the

[0098] Therefore, in addition to the same effect as the circuit 300 in FIG. 4D, The high-level potential of the signal can be set to the potential VDD. 00, the signal delay when the signal input to the first terminal is at a high level is smaller. It is possible.

[0099] When the circuit 300 in FIG. 4F is used in the inverter circuit in FIG. 2A, the capacitance element 2 The first electrode of transistor 304 may be connected to the gate of transistor 306. Since the difference between the minimum and maximum potentials of the gate of is greater than the amplitude voltage of the signal IN, The potential of N2 can be further reduced.

[0100] In addition, in the circuit 300 shown in FIG. 4A and FIG. 4B, the transistor 30 6 and transistor 307 may be provided.

[0101] Note that the transistors included in the circuit 300 (for example, the transistor 304 and the transistor 30 5, transistor 306 and transistor 307) have the same conductivity type as transistor 101 It is preferable that:

[0102] It should be noted that the circuit 300A, the circuit 300B, and the circuit 300C do not need to have the same configuration. Any one of Figs. 4(A) to 4(F) may be applied as appropriate.

[0103] The inverter circuit of FIG. 5A is the same as the inverter circuit of FIG. 2A except that the circuit 30 4(D) is applied to the .DELTA..times ...

[0104] The inverter circuit of FIG. 5B is the same as the inverter circuit of FIG. 2A except that the circuit 30 4F is applied to the .DELTA..times ...

[0105] Next, the inverter circuit of FIG. 6A is the inverter circuit of FIG. 1A with a transistor 20 This is a configuration with 5.

[0106] A first terminal of the transistor 205 is connected to a second terminal of the transistor 203. The second terminal of the transistor 205 is connected to the gate of the transistor 101 and the gate of the transistor 201. The gate of the transistor 205 is connected to a wiring 11.

[0107] The transistor 205 is connected to the gate of the transistor 101 and the gate of the transistor 201. The gate has a function of controlling conduction or non-conduction between the second terminal of the transistor 203 and the second terminal of the transistor 203 .

[0108] In the inverter circuit of FIG. 6(A), during the period when the signal IN is at a low level, The potential of the second terminal of the transistor 203 is changed from the potential of the gate of the transistor 205 (potential VDD) to When the potential rises to a potential lower than the threshold voltage of the transistor 205, the transistor 205 Therefore, the potential of the second terminal of the transistor 203 can be reduced. Therefore, deterioration and / or destruction of the transistor 203 can be suppressed.

[0109] As in the inverter circuit of FIG. 6(A), FIG. 2(A), FIG. 2(B), FIG. In the inverter circuits shown in Figs. 3(B), 5(A) and 5(B), the transistor A star 205 may be provided.

[0110] Next, the inverter circuit of FIG. 6B is the inverter circuit of FIG. Also, the wiring 13 is divided into a plurality of wirings.

[0111] The wiring 11 is divided into a wiring 11A and a wiring 11B. A first terminal of the transistor 201 is connected to the wiring 11B. The wiring 13 is divided into wirings 13A, 13B, and 13C, and the transistor 102 A first terminal of the transistor 201 is connected to the wiring 13A, and a first terminal of the transistor 202 is connected to the wiring 13B. A first terminal of the transistor 203 is connected to the wiring 13C.

[0112] In the inverter circuit of FIG. 6B, a potential VDD is supplied to the wiring 11A and the wiring 11B. If the potential VSS is supplied to the wirings 13A, 13B, and 13C, the same as in FIG. However, when different potentials are supplied to the wiring 11A and the wiring 11B, Alternatively, different potentials may be supplied to the wiring 13A, the wiring 13B, and the wiring 13C.

[0113] It is to be noted that only one of the wiring 11 and the wiring 13 may be divided into a plurality of wirings.

[0114] In addition, when the wiring 13 is divided into a plurality of wirings, the wiring 13C is omitted and the transistor The first terminal of the capacitor 203 may be connected to the wiring 13A or the wiring 13B. Even if A is omitted and the first terminal of the transistor 102 is connected to the wiring 13B or the wiring 13C, good.

[0115] As in the inverter circuit of FIG. 6(B), FIG. 2(A), FIG. 2(B), FIG. In the above-mentioned inverter circuits such as those shown in Figs. 3(B), 5(A), 5(B) and 6(A), Alternatively, the wiring 11 and / or the wiring 13 may be divided into a plurality of wirings.

[0116] Although not shown, FIGS. 1(A), 2(A), 2(B), 3(A), and 3(B) In the above-mentioned inverter circuits shown in Figs. 5(A), 5(B), 6(A) and 6(B), The first electrode is connected to the second terminal of the transistor 101, and the second electrode is connected to the A capacitive element connected to the gate of the transistor 101 may be provided.

[0117] Although not shown, FIGS. 1(A), 2(A), 2(B), 3(A), and 3(B) In the above-mentioned inverter circuits shown in Figs. 5(A), 5(B), 6(A) and 6(B), The first electrode is connected to the second terminal of the transistor 201, and the second electrode is connected to the A capacitive element connected to the gate of the transistor 201 may be provided.

[0118] The load driven by the transistor 101 (for example, the load connected to the wiring 12) is A load (e.g., a resistor 201, a transistor 202, and a transistor 203) is driven by the transistor 201. The load connected to the node N1 or the node N2 is larger than the load connected to the node N1 or the node N2. The larger the W / L, the shorter the rise time of the signal OUT. The W / L of transistor 101 is the W / L of transistor 201, the W / L of transistor 202 It is preferable that L is larger than W / L of transistor 203 .

[0119] Similarly, the load driven by the transistor 102 (for example, the load connected to the line 12) is The loads driven by the transistors 201, 202, and 203 are larger than the loads driven by the transistors 201, 202, and 203. In addition, the larger the W / L of the transistor 102, the shorter the fall time of the signal OUT. Therefore, the W / L of the transistor 102 can be shortened by W / L, which is greater than the W / L of transistor 202 and the W / L of transistor 203 is preferred.

[0120] Also, the Vgs when the transistor 101 turns on is Therefore, the W / L of the transistor 101 is It is preferable that the W / L of the transistor 101 is larger than that of the transistor 102. It is preferable that the W / L ratio be the largest among the transistors included in the inverter circuit of the embodiment. It is nice.

[0121] The low-level potential of the signal IN is supplied to the transistors 102, 202, and If the potential is such that the transistor 203 is turned off, the inverter circuit of this embodiment is Therefore, the low level potential of the signal IN is set to a potential lower than the potential VSS. In this way, the transistors 201, 202, and 203 Vgs when the transistor 201 is turned off can be a negative voltage. When the transistor 202 and the transistor 203 are normally on, or The voltages between the gates and sources of the transistors 201, 202, and 203 are Even if the drain current is large when the potential difference is 0 [V], it operates normally. can be done.

[0122] Note that the high-level potential of the signal IN is If the potential is such that the transistor 203 is turned on, the inverter circuit of this embodiment is normal. Therefore, even if the high-level potential of the signal IN is set to a potential lower than the potential VDD, This makes it possible to reduce the drive voltage of the circuit that outputs a signal to the wiring 14. In the inverter circuit of this embodiment, the high-level potential of the signal IN is equal to the potential VDD Even if the potential is lower, the high-level potential of the signal OUT can be set to the potential VDD. do.

[0123] The signal IN is supplied to the transistors 102, 202, and 203. When the transistor 102, the transistor 202, and the transistor 203 are turned off, As long as the signal has a potential to be turned on, it is not limited to a digital signal. For example, the signal IN is , it may have three or more potentials, or may be an analog signal.

[0124] If a signal such as a clock signal is input to the wiring 11, when the signal IN is at a low level, In particular, the signal from the wiring 11 can be output to the wiring 12. When the wiring 11 is divided into wiring 11A and wiring 11B as in the case of the wiring 11, It is preferable to input a signal such as a lock signal and supply a potential VDD to the wiring 11B. Then, the potential of the node N1 can be made high, so that the transistor 101 is easily turned on. Therefore, the signal on the wiring 11A can be output to the wiring 12 in a stable manner.

[0125] Note that the transistor 102, the transistor 202, and the transistor 203 are connected to the wiring 13. A signal that is low level during the ON period (for example, the period when the signal IN is high level) If the signal is input, the inverter circuit of this embodiment operates normally. During the period when the transistor 102, the transistor 202, and the transistor 203 are turned off (e.g. For example, a signal that is at a high level during all or part of the period during which the signal IN is at a low level. When this input is input, the transistors 102, 202, and 203 are reverse biased. Therefore, the transistor 102, the transistor 202, and the transistor The deterioration of the transistor 203 can be reduced.

[0126] Here, one aspect of the present invention includes the following configuration.

[0127] One embodiment of the present invention is a semiconductor device including a transistor 101, a transistor 201, a capacitor 204, and A first terminal of the transistor 101 is connected to a wiring 11. The second terminal of the transistor 101 is connected to the wiring 12. The terminal of the transistor 201 is connected to the wiring 11, and the gate of the transistor 201 is connected to the gate of the transistor 101. A first electrode of the capacitor 204 is connected to the wiring 14, and a second electrode of the capacitor 204 is connected to the wiring 14. The electrode of this gate is connected to the second terminal of the transistor 201 (see FIG. 16A).

[0128] In the above embodiment of the present invention, as the potential of the wiring 14 decreases, The potential of the second terminal of transistor 201 drops. As a result, the transistor 201 is turned on, and the potential of the wiring 11 is changed to the transistor The potential at the second terminal of the transistor 201 is increased ( As the potential of the second terminal of the transistor 201 increases, The potential of the gate of the transistor 201 rises. As a result, the transistor 101 is turned on and the potential of the wiring 11 is The potential is supplied to the wiring 12, and the potential of the wiring 12 increases (see FIG. 16C).

[0129] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0130] (Embodiment 2) In this embodiment, a shift register circuit (semiconductor device or driver circuit) according to one embodiment of the present invention will be described. This article explains the "system of thought" (also known as the "system of thought").

[0131] The shift register circuit of this embodiment is a multiple flip-flop circuit (semiconductor device or driver Therefore, we will first explain the flip-flop circuit, and then A shift register circuit having a flip-flop circuit will be described.

[0132] Regarding the flip-flop circuit included in the shift register circuit of this embodiment, FIG. This will be described with reference to the following.

[0133] The flip-flop circuit of FIG. 7A includes a transistor 401, a transistor 402, The semiconductor memory device includes a transistor 403 , a transistor 404 , a transistor 405 , and a circuit 500 . A first terminal of the transistor 401 is connected to the wiring 21, and a second terminal of the transistor 401 is connected to the wiring 21. The first terminal of the transistor 402 is connected to the wiring 13. The second terminal of the transistor 402 is connected to the wiring 22. The second terminal of the transistor 403 is connected to the wiring 13, and the second terminal of the transistor 401 is connected to the gate A first terminal of the transistor 404 is connected to the wiring 23. The second terminal of 404 is connected to the gate of the transistor 401. The first terminal of the transistor 405 is connected to the wiring 13. The second terminal of the transistor 405 is connected to the gate of the transistor 401. The gate of the capacitor 405 is connected to the wiring 24. The first terminal (also called the input terminal) of the circuit 500 ) is connected to the gate of the transistor 401, and the second terminal (also called the output terminal) of the circuit 500 The transistor 402 and the transistor 403 are connected to each other.

[0134] Note that the inverter circuit in Embodiment 1 can be used as the circuit 500. The first terminal of the circuit 500 corresponds to the wiring 14 of the inverter circuit of the first embodiment. The second terminal corresponds to the wiring 12 of the inverter circuit of the first embodiment.

[0135] The gate of the transistor 401, the second terminal of the transistor 403, and the A connection between the second terminal of the transistor 405 and the first terminal of the circuit 500. The gate of the transistor 402 and the gate of the transistor 403 are shown as node N3. The connection point between the port and the second terminal of the circuit 500 is indicated as node N4.

[0136] Note that the transistors included in the flip-flop circuit of this embodiment mode have the same conductivity type. For example, in the flip-flop circuit of FIG. , transistor 402, transistor 403, transistor 404, and transistor 40 5 and the transistors included in the circuit 500 preferably have the same conductivity type.

[0137] A signal CK is input to the wiring 21 (also called a signal line), and the wiring 21 has a function of transmitting the signal CK. The signal CK is a clock signal that alternates between high and low levels.

[0138] A signal SOUT is output from the wiring 22 (also called a signal line). The signal SOUT is the output signal of the flip-flop circuit shown in FIG. It is.

[0139] A signal SP is input to the wiring 23 (also called a signal line), and the wiring 23 has a function of transmitting the signal SP. The signal SP is an input signal to the flip-flop circuit of FIG.

[0140] A signal RE is input to the wiring 24 (also called a signal line), and the wiring 24 has a function of transmitting the signal RE. The signal RE is an input signal to the flip-flop circuit of FIG.

[0141] Note that the signals or potentials applied to the wirings 21, 23, and 24 are not limited to those described above. Various signals, potentials, etc. can also be input.

[0142] The transistor 401 has a function of controlling electrical continuity or non-conduction between the wiring 21 and the wiring 22 . The transistor 401 also has a function of supplying a signal CK from the wiring 21 to the wiring 22. In addition, the transistor 401 has a function of holding the potential difference between the wiring 22 and the node N3.

[0143] The transistor 402 has a function of controlling electrical continuity or non-conduction between the wiring 13 and the wiring 22 . The transistor 402 has a function of supplying the potential VSS of the wiring 13 to the wiring 22 .

[0144] The transistor 403 has a function of controlling conduction or non-conduction between the wiring 13 and the node N3. The transistor 403 has a function of supplying the potential VSS of the wiring 13 to the node N3. do.

[0145] The transistor 404 has a function of controlling conduction or non-conduction between the wiring 23 and the node N3. The transistor 404 has a function of supplying the signal SP of the wiring 23 to the node N3. .

[0146] The transistor 405 has a function of controlling conduction or non-conduction between the wiring 13 and the node N3. In addition, the transistor 405 has a function of supplying the potential VSS to the node N3.

[0147] Next, an example of a method for driving the flip-flop circuit of FIG. 7(A) will be described with reference to FIG. 7(B). FIG. 7B illustrates a method for driving the flip-flop circuit of FIG. 1 shows an example of a timing chart for

[0148] The high-level potentials of the signals CK, SP, and RE are equal to the potential VDD. The description will be given assuming that the potential of the level is equal to the potential VSS. The explanation will be given separately for period Ta, period Tb, period Tc, and period Td.

[0149] During the period Ta, the signal SP goes high, the signal RE goes low, and the signal C K goes low, so that transistor 404 turns on and transistor 405 will be turned off.

[0150] When the transistor 404 is turned on, the signal SP of the wiring 23 is supplied to the node N3. Since the signal SP is at a high level, the potential of the node N3 rises. As a result, the output signal of the circuit 500 becomes low level. When the potential of the node N3 rises, the transistor 403 is turned off. 01 turns on.

[0151] When the transistor 401 is turned on, the signal CK on the wiring 21 is supplied to the wiring 22. Since the signal CK is at a low level, the potential of the wiring 22 is the potential VSS. UT goes to low level.

[0152] Note that the potential of the node N3 is changed from the potential of the gate of the transistor 404 (potential VDD) to the potential of the transistor When the potential rises to a potential lower than the threshold voltage of the transistor 404, the transistor 404 is turned off. Therefore, node N3 is in a floating state.

[0153] Next, during a period Tb, the signal SP goes to a low level and the signal RE remains at a low level. Therefore, the signal CK becomes high level. 5 remains off. Also, the output signal of the circuit 500 remains at a low level. , transistor 402 and transistor 403 remain off.

[0154] Since transistor 403, transistor 404 and transistor 405 remain off, Therefore, the node N3 remains in a floating state. Therefore, the potential of the node N3 remains high. Therefore, transistor 401 remains on.

[0155] Since the transistor 401 remains on, the signal CK on the wiring 21 is supplied to the wiring 22. Since the signal CK is at a high level, the potential of the wiring 22 starts to rise. At this time, a node N3 is connected between the gate and the second terminal of the transistor 401 during the period Ta. The potential difference between the wiring 22 and the node 21 is maintained. As a result, the potential of the wiring 22 becomes equal to the potential of the signal CK. That is, the signal SOUT goes to a high level.

[0156] Next, during a period Tc, the signal SP remains at a low level, and the signal RE goes to a high level. Therefore, the signal CK becomes low level, and the transistor 404 remains off. Transistor 405 turns on.

[0157] When the transistor 405 is turned on, the potential VSS of the wiring 13 is supplied to the node N3. Therefore, the potential of the node N3 falls to the potential VSS. In addition, the output signal of the circuit 500 becomes high level, and the transistor 402 and the transistor Transistor 403 turns on.

[0158] When the transistor 402 is turned on, the potential VSS of the wiring 13 is supplied to the wiring 22. As a result, the potential of the wiring 22 drops to the potential VSS. In other words, the signal SOUT becomes low level. do.

[0159] Next, during a period Td, the signal SP remains at a low level, and the signal RE goes low. The signal CK alternates between low and high levels. The output signal of the circuit 500 is high. Therefore, the transistor 402 and the transistor 403 remain on. It becomes.

[0160] When the transistor 403 remains on, the potential VSS of the wiring 13 is supplied to the node N3. Therefore, the potential of the node N3 is maintained at the potential VSS, and the transistor The controller 401 remains off.

[0161] In addition, when the transistor 402 remains on, the potential VSS of the wiring 13 is supplied to the wiring 22. Therefore, the potential of the wiring 22 remains at the potential VSS. SOUT remains at low level.

[0162] As described above, the flip-flop circuit of FIG. 7A is the inverter circuit of the first embodiment. By having this, the same effects as those of the inverter circuit of the first embodiment can be achieved.

[0163] Next, a flip-flop circuit different from that shown in FIG. 7(A) will be described with reference to FIGS. 8 and 9. The following will explain the differences from FIG.

[0164] First, the flip-flop circuit in FIG. 8(A) is a flip-flop circuit in FIG. 7(A). The configuration includes a transistor 406.

[0165] A first terminal of the transistor 406 is connected to the wiring 13, and a second terminal of the transistor 406 is connected to the wiring 13. The terminal of the transistor 406 is connected to a wiring 22 , and the gate of the transistor 406 is connected to a wiring 25 .

[0166] A signal CKB is input to the wiring 25 (also called a signal line), and the wiring 25 transmits the signal CKB. The signal CKB is an inverted signal of the signal CK or a signal that is out of phase with the signal CK. be.

[0167] The transistor 406 has a function of controlling electrical continuity or non-conduction between the wiring 13 and the wiring 22. The transistor 406 has a function of supplying the potential VSS of the wiring 13 to the wiring 22. do.

[0168] In the flip-flop circuit of FIG. 8(A), the signal CKB goes high during the period Td. Therefore, during the period Td, the signal CKB becomes Every time the potential VSS of the wiring 13 becomes high, the potential VSS of the wiring 13 is supplied to the wiring 22.

[0169] In particular, when the signal CKB is an inverted signal of the signal CK, during the periods Ta and Tc, During the period Tc In this case, the potential VSS of the wiring 13 is applied through both the transistor 402 and the transistor 406. Since the signal SOUT is supplied to the wiring 22, the fall time of the signal SOUT can be shortened. .

[0170] If the flip-flop circuit includes the transistor 406, during the period Td, The potential of the wiring 22 can be maintained at the potential VSS. If the transistor 402 is omitted, the number of transistors can be reduced and the layout can be simplified. It is possible to reduce the area required for installation.

[0171] Next, the flip-flop circuit of FIG. 8(B) transmits a signal to the flip-flop circuit of FIG. 7(A). The configuration is provided with a transistor 407.

[0172] A first terminal of the transistor 407 is connected to the wiring 13, and a second terminal of the transistor 407 is connected to the wiring 13. The terminal of the transistor 407 is connected to a wiring 22 , and the gate of the transistor 407 is connected to a wiring 24 .

[0173] The transistor 407 has a function of controlling electrical continuity or non-conduction between the wiring 13 and the wiring 22 . The transistor 407 has a function of supplying the potential VSS of the wiring 13 to the wiring 22. .

[0174] In the flip-flop circuit of FIG. 8B, the transistors are turned on during the periods Ta, Tb, and Td. During the period Tc, the transistor 407 is turned on. In the period Tc, when the transistor 407 is turned on, the potential VSS of the wiring 13 is It is supplied to the wiring 22.

[0175] Therefore, in the period Tc, the potential VSS of the wiring 13 is Since the signal SOUT is supplied to the wiring 22 via both the resistor 407 and the can be shortened.

[0176] In addition, similarly to the flip-flop circuit of FIG. 8B, the above-mentioned flip-flop circuit of FIG. The drop circuit may also include a transistor 407.

[0177] Next, the flip-flop circuit of FIG. 9(A) is a transistor of the flip-flop circuit of FIG. 7(A). The configuration is provided with a transistor 408.

[0178] A first terminal of the transistor 408 is connected to the wiring 11, and a second terminal of the transistor 408 is connected to the wiring 12. The transistor 408 has a gate connected to a node N4 and a gate connected to the wiring 24.

[0179] The transistor 408 has a function of controlling conduction or non-conduction between the wiring 11 and the node N4. The transistor 408 has a function of supplying the potential VDD of the wiring 11 to the node N4. Yes.

[0180] In the flip-flop circuit of FIG. 9A, the transistors are turned on during periods Ta, Tb, and Td. During the period Tc, the transistor 408 is turned on. In the period Tc, when the transistor 408 is turned on, the potential VDD of the wiring 11 is It is supplied to node N4.

[0181] Therefore, the time required for the potential of the node N4 to reach a predetermined value can be shortened. Therefore, the timing at which the transistors 402 and 403 are turned on is made earlier. As a result, the timing at which the potential VSS of the wiring 13 is supplied to the wiring 22 can be accelerated. Therefore, the fall time of the signal SOUT can be shortened.

[0182] As in the flip-flop circuit of FIG. 9(A), the above-mentioned The flip-flop circuit may also include a transistor 408.

[0183] If the flip-flop circuit includes the transistor 408, during the period Tc, The transistor 402 and the transistor 403 are turned on. Therefore, the transistor 405 By omitting the transistor 405, the number of transistors can be reduced and the layout can be improved. It is possible to reduce the out area, etc.

[0184] In addition, the transistor 408 is used in the flip-flop circuit of FIG. The first terminal of the transistor 408 may be connected to the wiring 25. Even if the line 25 is connected, the signal CKB of the line 25 is at a high level during the period Tc. This turns on transistor 408 and allows it to operate as described above.

[0185] Next, the flip-flop circuit of FIG. 9(B) transmits a signal to the flip-flop circuit of FIG. 7(A). The configuration is provided with a transistor 409.

[0186] A first terminal of the transistor 409 is connected to the wiring 21, and a second terminal of the transistor 409 is connected to the wiring 21. The gate of the transistor 409 is connected to the wiring 26, and the gate of the transistor 409 is connected to a node N3.

[0187] In the flip-flop circuit of FIG. 9B, the signal output from the wiring 22 is the signal SO The signal output from the wiring 26 is indicated as a signal SOUTb. The output signal of the flip-flop circuit is the signal SO It has the function of transmitting UTb.

[0188] The transistor 409 has the same function as the transistor 401, and is, for example, The reference numeral 9 has a function of controlling electrical continuity or non-conduction between the wiring 21 and the wiring 26 .

[0189] In the flip-flop circuit of FIG. 9B, a signal SOUTa, which is the same as the signal SOUTa, is Therefore, for example, when the signal SOUTa is connected to the wiring 22, The signal SOUTb is used as a signal for driving a load, and another stage connected to the wiring 26 The signal can be used as a signal for driving the flip-flop circuit.

[0190] As in the flip-flop circuit of FIG. 9(B), the flip-flop circuit of FIG. The flip-flop circuits such as A) may also be provided with a transistor 409. .

[0191] Although not shown, FIGS. 7(A), 8(A), 8(B), 9(A) and 9(B) In the flip-flop circuit described above, the first terminal of the transistor 404 is connected to a In this case, during the period Ta, the node N3 may be connected to the wiring 11 or the wiring 25. Since the potential or signal of the wiring 11 or the wiring 25 is supplied, the circuit for supplying the signal SP to the wiring 23 The load on the road can be reduced.

[0192] Although not shown, FIGS. 7(A), 8(A), 8(B), 9(A) and 9(B) In the above-mentioned flip-flop circuits, one electrode is connected to the wiring 22 and the other A capacitor element may be provided whose electrode is connected to the node N3. If the transistor 401 is provided in the amplifier circuit, the capacitance between the gate and the second terminal of the transistor 401 can be increased. This makes it easier to perform bootstrap operations.

[0193] Although not shown, FIGS. 7(A), 8(A), 8(B), 9(A) and 9(B) In the above-mentioned flip-flop circuit, the first terminal is connected to the wiring 22, and the second terminal is connected to the wiring 23. A transistor having a terminal connected to the node N3 and a gate connected to the wiring 21 may be provided. In this way, during the period Td when the signal CK is at a high level, the node N 3 to the wiring 22, or the potential of the wiring 22 to the node N3. Therefore, one of the transistor 402 and the transistor 403 may be omitted. When one of the transistors 402 and 403 is omitted, the load of the circuit 500 is Since the load is reduced, the W / L of the transistors in the circuit 500 can be reduced. do.

[0194] Although not shown, FIGS. 7(A), 8(A), 8(B), 9(A) and 9(B) In the above-mentioned flip-flop circuit, the first terminal is connected to the wiring 23, and the second terminal is connected to the wiring 24. A transistor having a terminal connected to the node N3 and a gate connected to the wiring 25 may be provided. In this case, the potential of the node N3 can be increased quickly during the period Ta.

[0195] Although not shown, FIGS. 7(A), 8(A), 8(B), 9(A) and 9(B) In the above-mentioned flip-flop circuit, the second terminal of the transistor 404 and the The first terminal of the transistor 401 is not connected to the gate of the transistor 402, and the second terminal of the transistor 404 is not connected to the gate of the transistor 401. The second terminal is connected to the gate of the transistor 401, and the gate is connected to the wiring 11 or Alternatively, a transistor connected to the wiring 25 may be provided. 404, and a voltage applied to a transistor connected to the second terminal of the transistor 404. Since the voltage can be reduced, deterioration or destruction of the transistor can be prevented. Note that the first terminal of the circuit 500 is the second terminal of the transistor 404 or the The second terminal of the transistor 405 may be connected to the gate of the transistor 401. The second terminal of the transistor 404 or the gate of the transistor 401 may be connected to the second terminal of the transistor 404 or the gate of the transistor 401 .

[0196] Although not shown, in the above-mentioned flip-flop circuit of FIG. 9B etc., The first terminal is connected to the wiring 13, the second terminal is connected to the wiring 26, the gate is connected to the node N4, A transistor connected to the line 24 or the wiring 25 may be provided. Since the potential VSS can be supplied to the wiring 26, the potential of the wiring 26 is maintained at the potential VSS. It becomes easier.

[0197] Next, a specific example in which the inverter circuit of the first embodiment is used as the circuit 500 will be described. .

[0198] The flip-flop circuit of FIG. 10A is the flip-flop circuit of FIG. The circuit 500 is configured using the inverter circuit of FIG.

[0199] The flip-flop circuit of FIG. 10B is the flip-flop circuit of FIG. The first terminal of the transistor 101 and the first terminal of the transistor 201 are connected to the wiring 21. It is a continuous structure.

[0200] In the flip-flop circuit in FIG. 10B, the wiring 13 The potential VSS is supplied to the node N4, and the signal C During a period Td, a signal CK on the wiring 21 is supplied to the node N4. If the potential of the node N4 is supplied with the voltage, the potential of the node N4 will alternate between the potential VDD and the potential VSS. The transistor 402 and the transistor 403 are repeatedly turned on and off. In this case, the potential VSS of the wiring 13 is periodically supplied to the wiring 22, and the potential VSS of the transistor 402 is Therefore, the potential of the wiring 22 is set to the potential V SS and suppress deterioration of the transistors 402 and 403. can be done.

[0201] As in the flip-flop circuit of FIG. 10(B), the flip-flop circuits of FIG. In the flip-flop circuit described above in FIG. 9(A) and FIG. 9(B), the circuit 500 is implemented as In either case of using the inverter circuit of the first embodiment, the first terminal of the transistor 101 The first terminal of the transistor 201 and the second terminal of the transistor 202 may be connected to the wiring 21.

[0202] Next, the shift register circuit of this embodiment will be described with reference to FIG.

[0203] The shift register circuit of FIG. 11 has N flip-flop circuits 600 (N is a natural number). However, in FIG. 11, the first to third stages of flip-flop circuits 600 (flip-flops Flip-flop circuit 600_1, flip-flop circuit 600_2, flip-flop circuit 60 Only 0_3) are shown.

[0204] In the shift register circuit of FIG. 11, the flip-flop circuit 600 is the flip-flop circuit shown in FIG. A flip-flop circuit is used. However, as the flip-flop circuit 600, The flip-flop circuit is not limited to that shown in FIG.

[0205] The shift register circuit of FIG. 11 is connected to N wirings 31, 32, 33, and 34. The flip-flop circuit 600 in the i-th stage (i is any one from 2 to N-1) is Wire 31 in the i-th row, wire 31 in the i-1th row, wire 31 in the i+1th row, wire 33 and wire 34 In addition, the wiring 22 is connected to the wiring 31 of the i-th stage, and the wiring 23 is connected to the i-th stage. The wiring 24 is connected to the wiring 31 in the (i+1)th stage, and the wiring 21 is connected to the wiring 31 in the (i+1)th stage. It is connected to the wiring 33 or the wiring 34 .

[0206] In addition, when the wiring 21 is connected to the wiring 33 in the flip-flop circuit 600 in the i-th stage, In this case, the wiring 21 and the wiring 34 are connected in the (i-1)th and (i+1)th flip-flop circuits 600. Connected.

[0207] The flip-flop circuit 600 in the first stage is the same as the flip-flop circuit 600 in the i-th stage. Although the connection is the same as that of the flip-flop circuit 600 in the first stage, the flip-flop circuit 600 in the i-1 stage There is no wiring 31. Therefore, in the first stage flip-flop circuit, the wiring 23 is connected to the wiring 3. It is connected to 2.

[0208] The flip-flop circuit 600 in the Nth stage has the same structure as the flip-flop circuit 600 in the ith stage. Although the connection is the same, the flip-flop circuit 600 in the Nth stage has the wiring 3 in the i+1th stage. Therefore, in the Nth stage flip-flop circuit 600, the wiring 24 is connected to the wiring 3. 2. However, in the Nth stage flip-flop circuit 600, the wiring 24 is Alternatively, the signal RE may be connected to the line 33 or the wiring 34. It may be connected to a line.

[0209] Signals SOUT_1 to SOUT_ N is output, and N wirings 31 have the function of transmitting signals SOUT_1 to SOUT_N. For example, a signal SOUT_i is output from the wiring 31 in the i-th stage, 31 has the function of transmitting the signal SOUT_i.

[0210] A signal SSP is input to the wiring 32 (also called a signal line), and the wiring 32 transmits the signal SSP. The signal SSP is a start pulse for the shift register circuit of FIG.

[0211] A signal CK is input to the wiring 33 (also called a signal line), and the wiring 33 has a function of transmitting the signal CK. Possesses the ability.

[0212] A signal CKB is input to the wiring 34 (also called a signal line), and the wiring 34 transmits the signal CKB. It has the function of

[0213] The wiring 32, the wiring 33, and the wiring 34 are not limited to the above-mentioned signals or potentials, and may be other signals or potentials. Various signals, potentials, etc. may also be input to the input terminals 111, 112.

[0214] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0215] (Embodiment 3) Taking an EL display device as an example, the cross-sectional structure of a pixel and a driving circuit of a display device according to one embodiment of the present invention will be described. The structure will be described with reference to FIG. 12. FIG. 12 shows a cross-sectional view of a pixel 840 and a driving circuit 841. is shown as an example.

[0216] The pixel 840 includes a light emitting element 832 and a transistor having a function of supplying a current to the light emitting element 832. The pixel 840 includes a light-emitting element 832 and a transistor 831. In addition, a transistor for controlling the input of an image signal to the pixel 840 and a transistor for controlling the potential of the image signal It may also have various semiconductor elements such as a capacitor element for holding the signal.

[0217] The driving circuit 841 is a transistor 830 and holds the gate voltage of the transistor 830. The driver circuit 841 includes the inverter circuit of the first embodiment, This corresponds to the flip-flop circuit or the shift register circuit of the second embodiment. The transistor 830 is the transistor 101 of the first embodiment or the transistor 102 of the second embodiment. The driver circuit 841 corresponds to the transistor 830 and the capacitor 401. In addition to the element 833, various semiconductor elements such as transistors and capacitors may be included. .

[0218] The transistor 831 is formed by forming a conductive film serving as a gate on a substrate 800 having an insulating surface. 816, the gate insulating film 802 on the conductive film 816, and the conductive film 816 at a position overlapping the gate insulating film 802. A semiconductor film 817 located on the gate insulating film 802 and a source terminal or a drain terminal The conductive film 815 and the conductive film 818 are located over the semiconductor film 817. The film 816 also functions as a scan line.

[0219] The transistor 830 is formed by forming a conductive film serving as a gate on a substrate 800 having an insulating surface. 812, the gate insulating film 802 on the conductive film 812, and the conductive film 812 at a position overlapping the gate insulating film 802 A semiconductor film 813 located on the gate insulating film 802 and a source terminal or a drain terminal The semiconductor film 813 includes a conductive film 814 and a conductive film 819 located over the semiconductor film 813 .

[0220] The capacitor 833 is formed by forming a conductive film 812 over a substrate 800 having an insulating surface. The gate insulating film 802 and the conductive film 812 are overlapped with each other. and a conductive film 819 disposed therebetween.

[0221] In addition, an insulating film 820 is formed over the conductive film 814, the conductive film 815, the conductive film 818, and the conductive film 819. and an insulating film 821 are provided in this order. A conductive film 822 that functions as an anode is provided on the insulating film 820. and is connected to the conductive film 818 via a contact hole 823 formed in the insulating film 821. It is being done.

[0222] In addition, an insulating film 824 having an opening through which a part of the conductive film 822 is exposed is formed on the insulating film 82 An EL layer 825 and an insulating film 824 are provided on a part of the conductive film 822 and the insulating film 824. A conductive film 826 serving as a cathode is provided in this order. The region where the light emitting element 832 is formed is an area where the EL layer 825 and the conductive film 826 overlap each other. do.

[0223] Note that in one embodiment of the present invention, the transistors 830 and 831 are amorphous and Semiconductors such as silicon or germanium, which may be crystalline, polycrystalline or single crystalline, are used for the semiconductor film. Alternatively, a wide-gap semiconductor such as an oxide semiconductor may be used for the semiconductor film. It's fine if it is.

[0224] The semiconductor films of the transistors 830 and 831 may be amorphous, microcrystalline, polycrystalline, or When a semiconductor such as silicon or germanium, which is a single crystal, is used, it is necessary to give one conductivity. The semiconductor film is doped with an impurity element that functions as a source terminal or a drain terminal. For example, by adding phosphorus or arsenic to the semiconductor film, It is possible to form an impurity region having n-type conductivity. By adding this to a semiconductor film, an impurity region having p-type conductivity can be formed.

[0225] When an oxide semiconductor is used for the semiconductor films of the transistors 830 and 831, In this case, a dopant is added to the semiconductor film to function as a source terminal or a drain terminal. The dopant can be added by ion implantation. Dopants include rare gases such as helium, argon, and xenon, as well as nitrogen, phosphorus, Group 15 elements such as arsenic and antimony can be used. For example, nitrogen can be used as a dopant. When used as a sintered body, the concentration of nitrogen atoms in the impurity region is 5×10 19 / cm 3 1x or more 10 22 / cm 3 It is desirable that the following:

[0226] Silicon semiconductors are grown by vapor phase growth methods such as plasma CVD or sputtering. Amorphous silicon produced by the laser annealing method, amorphous silicon After hydrogen ions are implanted into polycrystalline silicon and single crystal silicon wafers that have been crystallized, Single crystal silicon from which the surface layer has been peeled off can be used.

[0227] The oxide semiconductor film is made of at least one material selected from the group consisting of In, Ga, Sn, and Zn. For example, the oxide of the quaternary metal, In-Sn-Ga-Zn-O system In-Ga-Zn-O oxide semiconductors, which are oxides of ternary metals, and In-S n-Zn-O oxide semiconductor, In-Al-Zn-O oxide semiconductor, Sn-Ga-Zn -O-based oxide semiconductors, Al-Ga-Zn-O-based oxide semiconductors, Sn-Al-Zn-O-based oxide semiconductors Semiconductors made of Zn-Zn oxides, In-Zn-O oxide semiconductors, which are binary metal oxides, and Sn-Zn- O-based oxide semiconductors, Al-Zn-O-based oxide semiconductors, Zn-Mg-O-based oxide semiconductors, S n-Mg-O oxide semiconductor, In-Mg-O oxide semiconductor, In-Ga-O oxide Semiconductors, In-O oxide semiconductors and Sn-O oxide semiconductors, which are oxides of single-component metals In addition, a Zn-O-based oxide semiconductor can be used. Elements other than Ga, Sn, and Zn, such as SiO 2 may be included.

[0228] For example, an In-Ga-Zn-O oxide semiconductor is a semiconductor that contains indium (In), gallium (G a) means an oxide semiconductor containing zinc (Zn), and the composition is not important.

[0229] The oxide semiconductor film is made of InMO 3 (ZnO) m A thin film expressed as (m>0) Here, M is one selected from Zn, Ga, Al, Mn, and Co. For example, M may be Ga, Ga and Al, Ga and Mn, or Examples of the elements include Ga and Co.

[0230] In addition, when an In-Zn-O-based material is used as the oxide semiconductor, The atomic ratio of metal elements is In:Zn=50:1 to 1:2 (converted to molar ratio, In 2 O 3 ZnO=25:1 to 1:4), preferably In:Zn=20:1 to 1:1 (molar ratio Converted to In 2 O 3 In:ZnO=10:1 to 1:2), more preferably In:Zn= 15:1 to 1.5:1 (converted to molar ratio: In 2 O 3 :ZnO=15:2~3:4) For example, the target used for forming an In-Zn-O-based oxide semiconductor has an atomic ratio of When In:Zn:O=X:Y:Z, Z>1.5X+Y. The ratio of Zn is within the above range. By keeping the above range, it is possible to improve the mobility.

[0231] In addition, impurities such as moisture and hydrogen, which act as electron donors, are reduced, and the acid The reduced electron vacancies result in a highly purified oxide semiconductor. A de semiconductor is an i-type (intrinsic semiconductor) or is very close to an i-type. Therefore, the off-state current of a transistor including the oxide semiconductor is extremely low. The band gap of the oxide semiconductor is 2 eV or more, preferably 2.5 eV or more. More preferably, the concentration of impurities such as moisture or hydrogen is sufficiently reduced. In addition, an oxide semiconductor film that has been highly purified by reducing oxygen vacancies is used. This allows the off-state current of the transistor to be reduced.

[0232] Specifically, the off-state current of a transistor using a highly purified oxide semiconductor for a semiconductor film is low. For example, when the channel width is 1×10 6 μm Even with a device with a channel length of 10 μm, the voltage between the source and drain terminals (drain voltage When the applied voltage is in the range of 1V to 10V, the off-state current is measured by a semiconductor parameter analyzer. Below the limit, i.e. 1×10 -13 In this case, the characteristic of A or less can be obtained. The off-state current density, which corresponds to the off-state current divided by the transistor channel width, is 100zA. In addition, the capacitance element is connected to a transistor, and the capacitance element A circuit that controls the charge flowing into or out of a capacitance element using the transistor is used. The current density of the purified transistor can be measured. The oxide semiconductor film is used for the channel formation region, and the change in the amount of charge per unit time of the capacitor is The off-state current density of the transistor is measured from the source of the transistor. When the voltage between the drain and terminals is 3V, the off-state current is extremely low, at several tens of yA / μm. Therefore, it is known that the current density can be obtained by using a highly purified oxide semiconductor film as a channel. The off-state current of the transistor used in the gate formation region is a crystalline silicon transistor. It can be seen that the IR-value is significantly lower than that of the transistor.

[0233] Unless otherwise specified, in this specification, the off-state current is In this case, the drain terminal is set to a higher potential than the source terminal and gate. When the potential of the gate is 0 or less with respect to the potential of the transistor, the source terminal and the drain terminal The off-state current in this specification refers to the current that flows between the p-channel In a transistor with a drain terminal at a lower potential than the source terminal and gate, In this state, when the potential of the gate is equal to or greater than 0 with respect to the potential of the source terminal, It refers to the current that flows between the source terminal and the drain terminal.

[0234] The oxide semiconductor film is formed by, for example, forming a semiconductor layer using In (indium), Ga (gallium), and Zn (zinc). It can be formed by a sputtering method using a target containing In-Ga-Zn-based oxide. When the compound semiconductor film is formed by sputtering, the atomic ratio of In:Ga: Zn=1:1:1, 4:2:3, 3:1:2, 1:1:2, 2:1:3, or 3:1: A target of In-Ga-Zn oxide shown in FIG. 4 is used. By forming an oxide semiconductor film using an In-Ga-Zn oxide target, multi-crystal This makes it easier for crystals or CAAC, which will be described later, to form.

[0235] The filling rate of the target containing In, Ga, and Zn is preferably 90% or more and 100% or less. The filling rate is 95% or more and less than 100%. By using a target with a high filling rate, The deposited oxide semiconductor film becomes a dense film.

[0236] Specifically, the oxide semiconductor film is formed by holding the substrate in a treatment chamber that is kept in a reduced pressure state. The residual moisture in the treatment chamber is removed while introducing a sputtering gas from which hydrogen and moisture have been removed. During the film formation, the substrate temperature is preferably set to 100° C. or higher and 600° C. or lower. Preferably, the temperature may be 200° C. or higher and 400° C. or lower. In this way, the impurity concentration in the formed oxide semiconductor film can be reduced. Damage caused by tarring is reduced. To remove residual moisture in the processing chamber, an adsorption type It is preferable to use a vacuum pump. For example, a cryopump, an ion pump, a titanium sa It is preferable to use a blimpation pump. Also, as the exhaust means, a turbo pump is used. A cold trap may be added to the vacuum chamber. The deposition chamber is evacuated using a cryopump. Then, for example, hydrogen atom, water (H 2 Compounds containing hydrogen atoms such as 1,2-dihydrogen (preferably carbon-1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, Since the exhaust gas contains fluorine atoms, the oxide semiconductor film formed in the treatment chamber is This can reduce the concentration of impurities contained in the material.

[0237] Note that moisture or hydrogen ( Water or hydrogen can form donor levels and Therefore, in one embodiment of the present invention, To reduce impurities such as moisture or hydrogen in semiconductor films (dehydration or dehydrogenation) For the oxide semiconductor film, a reduced pressure atmosphere, an inert gas atmosphere such as nitrogen or a rare gas, or an oxygen atmosphere is used. Under nitrogen gas atmosphere or ultra-dry air (CRDS (cavity ring-down laser spectroscopy) When measured using a dew point meter, the moisture content is 20 ppm (-55°C in dew point equivalent) or less. The heat treatment is performed in an atmosphere of air, preferably 1 ppm or less, preferably 10 ppb or less. Carry out.

[0238] By performing heat treatment on the oxide semiconductor film, moisture or hydrogen is released from the oxide semiconductor film. Specifically, the substrate temperature is 250° C. or higher and 750° C. or lower, preferably 400° C. or higher. For example, the heat treatment may be performed at 500° C. for 3 to 6 minutes. If the RTA method is used for the heat treatment, dehydration or dehydrogenation can be carried out in a short time. Therefore, processing can be performed at temperatures exceeding the distortion point of the glass substrate.

[0239] Note that the heat treatment causes oxygen to be released from the oxide semiconductor film and the oxygen to be left in the oxide semiconductor film. Therefore, in one embodiment of the present invention, a vacancy may be formed in the gate electrode in contact with the oxide semiconductor film. An insulating film containing oxygen is used as an insulating film such as a gate insulating film. After the insulating film is formed, heat treatment is performed, whereby oxygen is supplied from the insulating film to the oxide semiconductor film. With the above structure, oxygen vacancies serving as donors are reduced, and oxygen atoms contained in the oxide semiconductor film are The oxide semiconductor film can have a stoichiometric composition. It is preferable that the oxide semiconductor film contains oxygen in an amount exceeding the stoichiometric composition. This makes it possible to approach the i-type, and reduces the variation in the electrical characteristics of transistors due to oxygen vacancies. It is possible to reduce the capacitance and improve the electrical characteristics.

[0240] Note that the heat treatment for supplying oxygen to the oxide semiconductor film is performed using nitrogen, ultra-dry air, or rare earth metal. In a gas (argon, helium, etc.) atmosphere, preferably at 200°C to 400°C The temperature is, for example, 250°C to 350°C. The gas has a water content of 20 ppm or less. It is desirable that the concentration is below 1 ppm, preferably below 10 ppb.

[0241] The oxide semiconductor film may be in a single crystal, polycrystalline (also referred to as polycrystalline), amorphous, or other state. Take a stance.

[0242] Preferably, the oxide semiconductor film is a CAAC-OS (C Axis Aligned Cr The film is a crystalline oxide semiconductor.

[0243] The CAAC-OS film is neither completely single crystalline nor completely amorphous. is an oxide semiconductor film with a crystalline-amorphous mixed phase structure having crystalline and amorphous parts in the amorphous phase. The crystal part must be small enough to fit within a cube with one side less than 100 nm. In addition, transmission electron microscopes (TEM) In the observation image by a microscope, the amorphous part and the The boundary between the crystal and the crystalline part is not clear. Therefore, the CAAC-OS film does not have any in-boundary defects. The resulting decrease in electron mobility is suppressed.

[0244] The crystal parts in the CAAC-OS film have c-axes that are normal vectors to the surface on which the CAAC-OS film is formed. The triangle is aligned parallel to the normal vector of the ab plane and perpendicular to the ab plane. The metal atoms are arranged in a layered or hexagonal shape when viewed perpendicular to the c-axis. Metal atoms and oxygen atoms are arranged in layers. The orientation of the a and b axes may be different. In this specification, when it is simply described as vertical, it means that The range of 5° to 95° is also included. This also includes the range from 1° to 5°.

[0245] In the CAAC-OS film, the distribution of the crystal parts may not be uniform. In the process of forming the C-OS film, when crystal growth is performed from the surface side of the oxide semiconductor film, The proportion of crystalline parts may be higher near the surface than near the growth surface. By adding impurities to the AC-OS film, the crystalline part becomes amorphous in the impurity-added region. It may also be pawned.

[0246] The c-axis of the crystal part in the CAAC-OS film is the normal vector of the surface on which the CAAC-OS film is formed. The CAAC-OS film shape (the shape of the film on which the film is formed) is Depending on the cross-sectional shape of the surface or the cross-sectional shape of the surface, the directions may differ from each other. The crystal parts are formed during film formation or by carrying out a crystallization process such as a heat treatment after film formation. will be done.

[0247] The electrical characteristics of transistors using CAAC-OS films change when exposed to visible or ultraviolet light. Therefore, the transistor has high reliability.

[0248] Note that part of oxygen contained in the oxide semiconductor film may be replaced with nitrogen.

[0249] The CAAC-OS film can be formed, for example, by sputtering a polycrystalline oxide semiconductor target. The sputtering target is used to form a film by sputtering. Upon impact, the crystalline regions in the sputtering target cleave from the ab plane, forming a -b: The particles peel off as plate-like or pellet-like sputtered particles with surfaces parallel to the surface. In this case, the plate-like sputtered particles maintain their crystalline state. It is believed that the CAAC-OS film is formed by the nanoparticles reaching the substrate as they are.

[0250] In addition, the following conditions are preferably applied to form the CAAC-OS film.

[0251] By reducing the amount of impurities mixed in during film formation, it is possible to prevent the crystal from collapsing due to impurities. For example, it is sufficient to reduce the concentration of impurities (hydrogen, water, carbon dioxide, etc.) present in the film formation chamber. In addition, the impurity concentration in the deposition gas should be reduced. Specifically, the dew point should be -80°C or less. Preferably, a deposition gas having a temperature of -100°C or lower is used.

[0252] In addition, by increasing the substrate heating temperature during film formation, the migration of sputtered particles after they reach the substrate is reduced. Therefore, the substrate heating temperature is set to 100°C or higher and It is preferable to form the film at a temperature of 200° C. or lower and preferably 500° C. or higher. By increasing the substrate heating temperature, the plate-shaped sputtering particles that reach the substrate are transformed into microspheres on the substrate. The oxide semiconductor is then deposited so that the flat surfaces of the sputtered particles are parallel to the substrate. It is believed that a membrane is formed.

[0253] In addition, by increasing the oxygen ratio in the deposition gas and optimizing the power, plasma damage during deposition is reduced. The oxygen ratio in the deposition gas is preferably 30% by volume or more, and more preferably 100% by volume or more. The product is %.

[0254] As an example of a sputtering target, an In-Ga-Zn-O compound target is The details are shown below.

[0255] InO X powder, GaO Y Powder and ZnO Z The powders are mixed in a specified molar ratio and pressurized. Then, it is heated at a temperature between 1000℃ and 1500℃ to produce polycrystalline In-G The target is a-Zn-O compound. X, Y, and Z are any positive numbers. The specified mole ratio is, for example, InO X powder, GaO Y Powder and ZnO Z The powder, 2:2:1, 8:4:3, 3:1:1, 1:1:1, 4:2:3 or 3:1:2 The type of powder and the molar ratio of the powder to be mixed depend on the sputtering turbine to be prepared. The setting can be changed as appropriate depending on the get.

[0256] Next, an example of a specific structure of a transistor included in the semiconductor device of the present invention will be described. do.

[0257] The transistor shown in FIG. 13A is a bottom-gate type transistor with a channel-etched structure.

[0258] The transistor shown in FIG. 13A has a gate electrode (Gate 1602, a gate insulating film 1603 on the gate electrode 1602, and a gate insulating film 160 3, a semiconductor film 1604 overlapping the gate electrode 1602, and a semiconductor film 1604 The transistor further includes a conductive film 1605 and a conductive film 1606 formed thereon. An insulating film 1607 formed on the semiconductor film 1604, the conductive film 1605, and the conductive film 1606 is , may be included in its components.

[0259] Note that the transistor shown in FIG. 13A has an insulating layer at a position overlapping with the semiconductor film 1604. A back gate electrode formed on the insulating film 1607 may also be included.

[0260] The transistor shown in FIG. 13B is a bottom-gate transistor with a channel protection structure.

[0261] The transistor shown in FIG. 13B has a gate electrode 161 formed on an insulating surface. 2, a gate insulating film 1613 on the gate electrode 1612, and A semiconductor film 1614 overlapping the gate electrode 1612 and a gate electrode 1613 formed on the semiconductor film 1614. A channel protective film 1618 formed on the semiconductor film 1614, a conductive film 1615 formed on the semiconductor film 1614, and a conductive The transistor further includes a channel protection film 1618 and a conductive film 1616. 15 and an insulating film 1617 formed on the conductive film 1616 may be included as a component. .

[0262] Note that the transistor shown in FIG. 13B has an insulating layer at a position overlapping with the semiconductor film 1614. A back gate electrode formed on the insulating film 1617 may also be included.

[0263] By providing a channel protective film 1618, the channel forming region of the semiconductor film 1614 and In the later process, the film is formed by plasma or etching agent during etching on the part that will be This prevents damage such as wear and tear, thus improving the reliability of the transistor. can be done.

[0264] The transistor shown in FIG. 13C is a bottom-gate type transistor having a bottom-contact structure.

[0265] The transistor shown in FIG. 13C has a gate electrode 162 formed on an insulating surface. 2, a gate insulating film 1623 on the gate electrode 1622, and a conductive film on the gate insulating film 1623. A gate electrode 1622 is formed on the gate insulating film 1623. The semiconductor film 162 overlaps the conductive film 1625 and the conductive film 1626. The transistor further includes a conductive film 1625, a conductive film 1626, and a semiconductor An insulating film 1627 formed on the film 1624 may be included as a component thereof.

[0266] Note that the transistor shown in FIG. 13C has an insulating layer at a position overlapping with the semiconductor film 1624. A back gate electrode formed on the insulating film 1627 may also be included.

[0267] The transistor shown in FIG. 13D is a top-gate type with a bottom-contact structure.

[0268] The transistor shown in FIG. 13D includes a conductive film 1645 formed on an insulating surface, A conductive film 1646, a semiconductor formed on the insulating surface, the conductive film 1645, and the conductive film 1646 A conductive film 1645, a conductive film 1646, and a semiconductor film 1644 are formed on the conductive film 1645, the conductive film 1646, and the semiconductor film 1644. A gate insulating film 1643 and a semiconductor film 1644 overlapping the gate insulating film 1643. The transistor further has a gate electrode 1642 on which the The formed insulating film 1647 may be included as a component thereof.

[0269] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0270] (Embodiment 4) An example of a panel, which is one form of a display device, will be described with reference to FIG. The panel includes a substrate 700, a pixel section 701 on the substrate 700, a signal line driving circuit 702, a scanning line It includes a drive circuit 703 and a terminal 704 .

[0271] The pixel portion 701 has a plurality of pixels, and each pixel has a display element and a control circuit for controlling the operation of the display element. The scanning line driver circuit 703 is provided with one or more transistors for each pixel. The pixel portion 701 is provided with a pixel selector 702, and a pixel selector 703 is provided to select the pixel by controlling the supply of a potential to a scanning line connected to the pixel. The signal line driver circuit 702 outputs an image to the pixel selected by the scanning line driver circuit 703. Controls the signal supply.

[0272] One or both of the signal line driver circuit 702 and the scanning line driver circuit 703 may be the same as that of the first embodiment. the flip-flop circuit of the second embodiment or the shift register circuit of the second embodiment In this way, the effects described in the first and second embodiments can be achieved. In addition, the pixel portion 701 can be enlarged. A material can be provided.

[0273] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0274] (Embodiment 5) A semiconductor device according to one aspect of the present invention includes a display device, a personal computer, and a recording medium. Image playback devices with advanced functions (typically DVD: Digital Versatile Disc (a device having a display that can play back recording media such as a DVD player and display the images) In addition, the semiconductor device according to one embodiment of the present invention can be used as a device. Examples of electronic devices that can be used include mobile phones, handheld game consoles, personal digital assistants, e-books, video Cameras such as digital still cameras, goggle-type displays (head-mounted displays), navigation systems, audio playback devices (car audio, digital Audio players, copiers, fax machines, printers, multifunction printers, These electronic devices include automated teller machines (ATMs) and vending machines. An example is shown in Figure 15.

[0275] FIG. 15A shows a portable game machine, which includes a housing 5001, a housing 5002, a display unit 5003, Display unit 5004, microphone 5005, speaker 5006, operation keys 5007, The semiconductor according to one embodiment of the present invention is used in a driver circuit of a portable game machine. By using this device, it is possible to provide a portable game machine with low power consumption and stable operation. The semiconductor device according to one embodiment of the present invention is used for the display portion 5003 or the display portion 5004. By doing so, it is possible to provide a portable game machine with high image quality. The portable game machine has two display units 5003 and 5004. The number of display units that the game machine has is not limited to this.

[0276] FIG. 15B shows a display device, which includes a housing 5201, a display portion 5202, a support stand 5203, and the like. By using a semiconductor device according to one embodiment of the present invention for a driver circuit of a display device, power consumption can be reduced. It is possible to provide a display device with low resistance and stable operation. By using the semiconductor device according to one embodiment, a display device with high image quality can be provided. Display devices include all devices for personal computers, TV broadcast reception, advertising displays, etc. This includes display devices for displaying information.

[0277] FIG. 15C shows a notebook personal computer, which includes a housing 5401 and a display unit 5402. 5403, a pointing device 5404, etc. By using a semiconductor device according to one embodiment of the present invention for a driver circuit of a mobile computer, power consumption can be reduced. It is possible to provide a notebook type personal computer that requires less force and operates stably. By using the semiconductor device according to one embodiment of the present invention for the display portion 5402, a high-quality notebook PC can be displayed. A personal computer can be provided.

[0278] FIG. 15D shows a portable information terminal, which includes a first housing 5601, a second housing 5602, a first display unit, and a 5603, a second display unit 5604, a connection unit 5605, and operation keys 5606. The display unit 5603 is provided in the first housing 5601, and the second display unit 5604 is provided in the second housing 5602. The first housing 5601 and the second housing 5602 are connected to each other via a connection portion 56 5605, and the angle between the first housing 5601 and the second housing 5602 is The first display unit 5603 is movable by a first housing 5605. The switch may be configured to switch according to the angle between the first and second housings 5602. At least one of the display unit 5603 and the second display unit 5604 has a function as a position input device. A semiconductor display device having a function as a position input device may be used. The function can be added by providing a touch panel to the semiconductor display device. The function of the input device is to use a photoelectric conversion element, also called a photosensor, as a semiconductor display device. It can also be added by providing it in a pixel portion. A portable information terminal which consumes less power and operates stably by using a semiconductor device according to one embodiment. The first display portion 5603 or the second display portion 5604 may be provided with one of the display devices of the present invention. By using the semiconductor device according to the embodiment, a portable information terminal with high image quality can be provided.

[0279] FIG. 15E shows a mobile phone. The mobile phone includes a housing 5801, a display unit 5802, an audio input unit 5803, The device has a voice output unit 5804, an operation key 5805, a light receiving unit 5806, etc. By converting the light received in the mobile phone into an electrical signal, it is possible to capture an image from the outside. By using a semiconductor device according to one embodiment of the present invention for a driver circuit of a mobile phone, power consumption can be reduced. In this way, a mobile phone with stable operation can be provided. By using such a semiconductor device, a mobile phone with high image quality can be provided.

[0280] This embodiment mode can be implemented in appropriate combination with other embodiment modes. [Explanation of symbols]

[0281] 11 Wiring 11A Wiring 11B Wiring 12 Wiring 13 Wiring 13A Wiring 13B Wiring 13C Wiring 14 Wiring 21 Wiring 22 Wiring 23 Wiring 24 Wiring 25 Wiring 26 Wiring 31 Wiring 32 Wiring 33 Wiring 34 Wiring 100 circuits 101 Transistor 102 Transistor 200 circuits 201 Transistor 202 Transistor 203 Transistor 204 Capacitive element 205 Transistor 300 circuits 300A circuit 300B circuit 300C circuit 301 Resistance element 302 Capacitive element 303 Transistor 304 Transistor 305 Transistor 306 Transistor 307 Transistor 401 Transistor 402 Transistor 403 Transistor 404 Transistor 405 Transistor 406 Transistor 407 Transistor 408 Transistor 409 Transistor 500 circuits 600 Flip-Flop Circuit 600_1 Flip-flop circuit 600_2 Flip-flop circuit 600_3 Flip-flop circuit 700 Substrates 701 Pixel section 702 Signal line driver circuit 703 Scanning line driver circuit 704 Terminal 800 boards 802 Gate insulating film 812 Conductive film 813 Semiconductor Film 814 Conductive film 815 Conductive Film 816 Conductive Film 817 Semiconductor Film 818 Conductive film 819 Conductive film 820 Insulating film 821 Insulating film 822 Conductive film 823 Contact Hole 824 Insulating film 825 EL layer 826 Conductive Film 830 Transistor 831 Transistor 832 Light emitting element 833 Capacitive element 840 pixels 841 Drive circuit 1602 Gate electrode 1603 Gate insulating film 1604 Semiconductor film 1605 Conductive film 1606 Conductive film 1607 Insulating film 1612 Gate electrode 1613 Gate insulating film 1614 Semiconductor film 1615 Conductive film 1616 Conductive film 1617 Insulating film 1618 Channel protection film 1622 Gate electrode 1623 Gate insulating film 1624 Semiconductor film 1625 Conductive film 1626 Conductive film 1627 Insulating film 1642 Gate electrode 1643 Gate insulating film 1644 Semiconductor film 1645 Conductive film 1646 Conductive film 1647 Insulating film 5001 Case 5002 Case 5003 Display section 5004 Display section 5005 Microphone 5006 Speaker 5007 Operation key 5008 Stylus 5201 Case 5202 Display section 5203 Support stand 5401 Case 5402 Display section 5403 Keyboard 5404 Pointing Device 5601 Case 5602 Case 5603 Display section 5604 Display section 5605 Connection 5606 Operation key 5801 Case 5802 Display section 5803 Audio input unit 5804 Audio output unit 5805 Operation key 5806 Light receiving section M1 Transistor M2 Transistor M3 Transistor M4 Transistor M11 Transistor M12 Transistor M13 Transistor M14 Transistor M15 Transistor M16 Transistor M17 Transistor M18 Transistor M19 Transistor C11 Capacitor element VDD potential VSS potential N1 Node N2 Node N3 Node N4 Node SP signal RE signal CK signal CKB signal IN signal SSP signal OUT signal SOUT signal SOUTa signal SOUTb signal SOUT_1 signal SOUT_i signal SOUT_N signal

Claims

1. The semiconductor device includes first to fifth transistors and a capacitor. one of a source and a drain of the first transistor is electrically connected to an output signal line; the other of the source and the drain of the first transistor is electrically connected to a first wiring; one of a source and a drain of the second transistor is electrically connected to the output signal line; the other of the source and the drain of the second transistor is electrically connected to a power supply line; one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor; a gate of the third transistor is electrically connected to a first signal line; one of a source and a drain of the fourth transistor is electrically connected to a gate of the first transistor; the other of the source and the drain of the fourth transistor is electrically connected to the power supply line; a gate of the fourth transistor is electrically connected to a second signal line; one electrode of the capacitance element is electrically connected to the gate of the first transistor; the other electrode of the capacitance element is electrically connected to one of the source and the drain of the fifth transistor; the other of the source and the drain of the fifth transistor is electrically connected to the power supply line; a gate of the fifth transistor is electrically connected to a gate of the first transistor; the third transistor is turned on, and a potential supplied to the other of the source or the drain of the third transistor is supplied to the gate of the first transistor via a channel formation region of the third transistor, thereby turning on the first transistor, and the potential of the first wiring is output to the output signal line by turning on the first transistor, When the second transistor is turned on, the potential of the power supply line is output to the output signal line.

2. The semiconductor device includes first to fifth transistors and a capacitor. one of a source and a drain of the first transistor is electrically connected to an output signal line; the other of the source and the drain of the first transistor is electrically connected to a first wiring; one of a source and a drain of the second transistor is electrically connected to the output signal line; the other of the source and the drain of the second transistor is electrically connected to a power supply line; one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor; a gate of the third transistor is electrically connected to a first signal line; one of a source and a drain of the fourth transistor is electrically connected to a gate of the first transistor; the other of the source and the drain of the fourth transistor is electrically connected to the power supply line; a gate of the fourth transistor is electrically connected to a second signal line; one electrode of the capacitance element is electrically connected to the gate of the first transistor; the other electrode of the capacitance element is electrically connected to one of the source and the drain of the fifth transistor; the other of the source and the drain of the fifth transistor is electrically connected to the power supply line; a gate of the fifth transistor is electrically connected to a gate of the first transistor; the third transistor is turned on, and a potential supplied to the other of the source or the drain of the third transistor is supplied to the gate of the first transistor via a channel formation region of the third transistor, thereby turning on the first transistor, and the potential of the first wiring is output to the output signal line by turning on the first transistor, When the second transistor is turned on, the potential of the power supply line is output to the output signal line, The first to seventh transistors are of the same conductivity type.

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