Crystal oscillation circuit

Abstract

To provide a crystal oscillation circuit capable of suppressing current consumption when a power supply voltage is in a high state while ensuring an inverter gain when the power supply voltage drops.SOLUTION: An oscillation circuit connected to a crystal oscillator and oscillating on the basis of an oscillation of the crystal oscillator, includes: a voltage comparator circuit configured to output a comparison result signal having a first voltage level when a voltage value of a power supply voltage is lower than a predetermined reference value and having a second voltage level when the voltage value of the power supply voltage is higher than the predetermined reference value; a current regulator circuit including a bias current source configured to transmit a constant current; and an oscillation inverter composed of a first transistor of a first conductivity type and a second transistor of a second conductivity type connected in tandem, and configured to oscillate by receiving the supply of a current that varies in accordance with fluctuations in the power supply voltage when the comparison result signal is at a first voltage level and to oscillate by receiving the supply of a current that corresponds to the constant current when the comparison result signal is at a second voltage level.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a crystal oscillator circuit. [Background technology]

[0002] A crystal oscillator circuit is used as a clock source for a processing device such as an MCU (Micro Controller Unit). In order to reduce the current consumption during oscillation of the crystal oscillator circuit, an oscillator device is adopted that is provided with a regulator that outputs a constant voltage and drives the crystal oscillator circuit to oscillate with the constant voltage supplied from the regulator (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2008-236629 A Summary of the Invention [Problem to be solved by the invention]

[0004] In a circuit configured as in the above-mentioned conventional technology, a regulator for the oscillator circuit and a terminal for connecting a stabilizing capacitance for the regulator are separately required. This poses the problem that it may be difficult to secure the terminals for MCUs with a small number of pins.

[0005] Alternatively, instead of using a regulator, a current source may be inserted between the power supply voltage and the oscillation inverter to reduce current consumption, but such a circuit inevitably has a narrow operating voltage range, which can lead to a problem that the gain of the inverter in the oscillation stage may be insufficient and oscillation may stop when the power supply voltage drops.

[0006] The present invention has been made in consideration of the above problems, and has an object to provide a crystal oscillator circuit that can suppress an increase in the number of terminals, ensure inverter gain when the power supply voltage drops, and suppress current consumption when the power supply voltage is high. [Means for solving the problem]

[0007] The crystal oscillator circuit according to the present invention is an oscillator circuit connected to a crystal oscillator and oscillates based on the oscillation of the crystal oscillator, comprising: a voltage comparator circuit that outputs a comparison result signal having a first voltage level when a voltage value of a power supply voltage is lower than a predetermined reference value, and a second voltage level when a voltage value of the power supply voltage is higher than the predetermined reference value; a current regulator circuit including a bias current source that outputs a constant current; and an oscillation inverter that is composed of a first transistor of a first conductivity type and a second transistor of a second conductivity type connected in cascade, and that oscillates by receiving a supply of a current that changes in accordance with fluctuations in the power supply voltage when the comparison result signal is at the first voltage level, and that oscillates by receiving a supply of a current that corresponds to the constant current when the comparison result signal is at the second voltage level. [Brief description of the drawings]

[0008]

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[0009] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will now be described in detail. In the following description of each embodiment and in the accompanying drawings, the same reference numerals are used to designate substantially the same or equivalent parts. EXAMPLES

[0010] 1 is a circuit diagram showing a configuration of a crystal oscillator circuit 100 according to a first embodiment of the present invention. The crystal oscillator circuit 100 is a circuit that constitutes a crystal oscillator together with a crystal resonator XTAL. The crystal oscillator circuit 100 has connection terminals XT0 and XT1, and is connected to one end and the other end of the crystal resonator XTAL via each connection terminal.

[0011] The crystal oscillator circuit 100 includes a power drop detection circuit 11, a current regulator circuit 12, a slope adjustment circuit 13, an oscillation stage 14, and a clock output stage 15.

[0012] The power supply drop detection circuit 11 is composed of a resistor R1, a resistor R2, a hysteresis comparator CP1, and a reference voltage VR1.

[0013] The resistors R1 and R2 are connected in series between the power supply voltage VDD and the ground potential VSS to form a resistor ladder. One end of the resistor R1 is connected to a voltage supply line L1 of the power supply voltage VDD. One end of the resistor R2 is connected to a voltage supply line L2 of the ground potential VSS. The other ends of the resistors R1 and R2 are connected to each other.

[0014] An inverting input terminal of the hysteresis comparator CP1 is connected to a connection node that connects the other ends of the resistors R1 and R2, and a non-inverting input terminal of the hysteresis comparator CP1 is connected to a reference voltage VR1.

[0015] The reference voltage VR1 is provided between the non-inverting input terminal of the hysteresis comparator CP1 and a voltage supply line L2 of the ground potential VSS. From the output terminal of the hysteresis comparator CP1, a comparison result signal CMP_0 having a voltage level according to a comparison result obtained by comparing VDD×R2 / (R1+R2), which is the voltage of the connection node between the resistors R1 and R2, with a voltage value VREF of the reference voltage VR1 (hereinafter also referred to as the reference voltage VREF), is output.

[0016] The current regulator circuit 12 is composed of a transistor PM1, an amplifier AP1, and a bias current source BC1.

[0017] The transistor PM1 is composed of a P-channel MOSFET of a first conductivity type. The gate and drain of the transistor PM1 are connected to each other (i.e., diode-connected). The source and back gate of the transistor PM1 are connected to a voltage supply line L1 of a power supply voltage VDD. The drain of the transistor PM1 is connected to one end of a bias current source BC1.

[0018] The bias current source BC1 is a current source that outputs a constant current. The other end of the bias current source BC1 is connected to a voltage supply line L2 of the ground potential VSS.

[0019] The non-inverting input terminal of the amplifier AP1 is connected to the gate and drain of the transistor PM1. The output terminal of the amplifier AP1 is connected to the inverting input terminal of the amplifier AP1 (i.e., negative feedback connection). From the output terminal of the amplifier AP1, a voltage obtained by amplifying the voltages at the gate and drain of the transistor PM1 is output as an output voltage PG_PRE.

[0020] The slope adjustment circuit 13 is supplied with the output voltage PG_PRE of the current regulator circuit 12. The slope adjustment circuit 13 includes an inverter made up of a transistor PM2 and a transistor NM2, and a capacitive element C1 connected thereto.

[0021] The transistor PM2 is composed of a P-channel MOSFET which is a first conductivity type. The transistor NM2 is composed of an N-channel MOSFET which is a second conductivity type opposite to the first conductivity type. The gates of the transistor PM2 and the transistor NM2 are connected to each other and the drains of the transistor PM2 and the transistor NM2 are connected to each other to form an inverter.

[0022] The source of the transistor PM2 is connected to the output terminal of the amplifier AP1. The back gate of the transistor PM2 is connected to the voltage supply line L1 of the power supply voltage VDD. The source and back gate of the transistor NM2 are connected to the ground potential VSS. A connection node connecting the gates of the transistor PM2 and the transistor NM2 is connected to the output terminal of the hysteresis comparator CP1.

[0023] One end of the capacitance element C1 is connected to the output end of the hysteresis comparator CP1 and to the input of an inverter formed by the transistors PM2 and NM2 (i.e., a connection node connecting the gates of the transistors). The other end of the capacitance element C1 is connected to the output of the inverter formed by the transistors PM2 and NM2 (i.e., a connection node connecting the drains of the transistors). In other words, the input and output of the inverter formed by the transistors PM2 and NM2 are shorted via the capacitance element C1.

[0024] The output voltage PG of the slope adjustment circuit 13 is output from a connection node that connects the drains of the transistor PM2 and the transistor NM2 to each other, which serves as an output terminal. The output voltage PG is supplied to an oscillation stage .

[0025] Since the slope adjustment circuit 13 has the capacitance element C1, it has a function of making the voltage change of the output voltage PG gentle and suppressing the disturbance of the oscillation waveform of the clock signal CLK (i.e., a slope adjustment function). Details of this function will be described later.

[0026] The oscillation stage 14 is made up of a transistor PM3, a transistor PM4, a transistor NM4, a resistor R3, a capacitance element C2, and a capacitance element C3. The transistor PM4 and the transistor NM4 make up an oscillation inverter 16.

[0027] The transistor PM3 is composed of a P-channel MOSFET. The source and back gate of the transistor PM3 are connected to the voltage supply line L1 of the power supply voltage VDD. The gate of the transistor PM3 is connected to the output terminal of the slope adjustment circuit 13. That is, the output voltage PG of the slope adjustment circuit 13 is supplied to the gate (i.e., the control terminal) of the transistor PM3.

[0028] When the output voltage PG is sufficiently higher than the ground potential VSS, the current sent from the bias current source BC1 of the current regulator circuit 12 is current-mirrored and supplied to the oscillation inverter 16 of the oscillation stage 14. On the other hand, when the output voltage PG is the ground potential VSS (=GND), the transistor PM3 is in a fully-on state, and a current flowing from the voltage supply line L1 of the power supply voltage VDD, that is, a current whose value changes according to fluctuations in the voltage value of the power supply voltage VDD, is supplied to the oscillation inverter 16.

[0029] The transistor PM4 is composed of a P-channel MOSFET. The transistor NM4 is composed of an N-channel MOSFET. The transistors PM4 and NM4 configure an oscillation inverter 16 by connecting their gates to each other and their drains to each other. The input of the oscillation inverter 16 (i.e., the gates of the transistors PM4 and NM4) is connected to a connection terminal XT0. The output of the oscillation inverter 16 (i.e., the drains of the transistors PM4 and NM4) is connected to a connection terminal XT1.

[0030] The source of the transistor PM4 is connected to the drain of the transistor PM3. The back gate of the transistor PM4 is connected to the back gate of the transistor PM3 and to the voltage supply line L1 of the power supply voltage VDD. The source and back gate of the transistor NM4 are each connected to the voltage supply line L2 of the ground potential VSS.

[0031] One end of the resistor R3 is connected to the input of the oscillation inverter 16, and the other end is connected to the output of the oscillation inverter 16. In other words, the resistor R3 is a feedback resistor inserted between the output and input of the oscillation inverter 16.

[0032] The capacitive element C2 has one end connected to the input of the oscillation inverter 16 and the other end connected to the voltage supply line L2 of the ground potential VSS. The capacitive element C3 has one end connected to the output of the oscillation inverter 16 and the other end connected to the voltage supply line L2 of the ground potential VSS.

[0033] The clock output stage 15 is composed of a transistor PM5 and a Schmitt buffer SB1.

[0034] The transistor PM5 is composed of a P-channel MOSFET. The source and back gate of the transistor PM5 are connected to the voltage supply line L1 of the power supply voltage VDD. The gate of the transistor PM5 is connected to the output of the slope adjustment circuit 13 together with the gate of the transistor PM3. The drain of the transistor PM5 is connected to the positive power supply input terminal of the Schmitt buffer SB1.

[0035] The input terminal of the Schmitt buffer SB1 is connected to the output of the oscillation inverter 16. The output terminal of the Schmitt buffer SB1 is connected to the clock output terminal CK1. The Schmitt buffer SB1 receives the output signal of the oscillation inverter 16 at its input terminal, shapes the signal, and outputs it as the clock signal CLK. The Schmitt buffer SB1 has a hysteresis characteristic, cuts out noise on the connection terminal XT1, and outputs the clock signal CLK shaped so as not to generate so-called whiskers.

[0036] Next, the operation of the crystal oscillation circuit 100 of this embodiment will be described. The crystal oscillation circuit 100 switches between two operating states (operation modes) depending on the voltage level of the power supply voltage VDD. In the following, the operation of the crystal oscillation circuit 100 will be described with the two operating states being a first operating state and a second operating state.

[0037] [First operating state] When the power supply voltage VDD is higher than a predetermined reference value, specifically, when it is represented by the following mathematical formula (Equation 1), the crystal oscillation circuit 100 enters the first operating state.

[0038] [Equation]

[0039] In other words, when VDD > VREF × (R1 + R2) / R2, the crystal oscillation circuit 100 enters the first operating state.

[0040] At this time, since the comparison result signal CMP_0 output from the hysteresis comparator CP1 is at a low level, the transistor PM2 of the slope adjustment circuit 13 is turned on (NM2 is turned off). As a result, the output voltage PG of the slope adjustment circuit 13 becomes the voltage level of the output voltage PG_PRE of the current regulator circuit 12.

[0041] The output voltage PG_PRE of the current regulator circuit 12 is the output obtained by buffering the output of the diode connection of the transistor PM1 of the current regulator circuit 12 with the amplifier AP1. Therefore, the current of the bias current source BC1 is mirrored and supplied to the oscillation inverter 16, and the oscillation inverter 16 oscillates with a constant current.

[0042] [Second operating state] When the power supply voltage VDD is lower than a predetermined reference value, specifically, when it is represented by the following mathematical formula (Equation 2), the crystal oscillation circuit 100 enters the second operating state.

[0043] [Equation]

[0044] In other words, when VDD < VREF × (R1 + R2) / R2, the crystal oscillation circuit 100 enters the second operating state.

[0045] At this time, the comparison result signal CMP_0 output from the hysteresis comparator CP1 goes to a high level, so that the transistor NM2 of the slope adjustment circuit 13 goes to an on state (and the transistor PM2 goes to an off state). As a result, the output voltage PG of the slope adjustment circuit 13 is fixed to the ground potential VSS.

[0046] When the output voltage PG of the slope adjustment circuit 13 is fixed to the level of the ground potential VSS, i.e., the GND (ground) level, the transistor PM3 of the oscillation stage 14 is in a fully on state, and the drain voltage PD of the transistor PM3 is at the voltage level of the power supply voltage VDD. Therefore, the oscillation inverter 16 is in a state where it oscillates with a current according to the voltage value of the power supply voltage VDD.

[0047] By switching the operating state in this way, the crystal oscillation circuit 100 of this embodiment operates to suppress current consumption when the voltage level of the power supply voltage VDD is high, and when the voltage level of the power supply voltage VDD is low, the gain of the oscillation inverter 16 is secured and oscillation can be maintained even at a low voltage. This will be described below.

[0048] FIG. 2 is a circuit diagram showing a crystal oscillation circuit 200 of a first comparative example that does not have a configuration for oscillating an oscillation inverter with a constant current.

[0049] In the crystal oscillation circuit 200 of the first comparative example, the source of the transistor PM4 of the oscillation inverter 16 is directly connected to the voltage supply line L1 of the power supply voltage VDD. Therefore, the oscillation inverter 16 always operates with a current according to the voltage level of the power supply voltage VDD, and when the voltage level of the power supply voltage VDD rises, the current consumption increases.

[0050] FIG. 3 is a circuit diagram showing a crystal oscillation circuit 300 of a second comparative example, which is configured so that the oscillation inverter oscillates at a constant current value regardless of the voltage level of the power supply voltage VDD in order to reduce power consumption.

[0051] In the crystal oscillation circuit 300 of the second comparative example, the gate of the transistor PM1 connected to the bias current source BC1 is connected to the gate of the transistor PM3 to form a current mirror, so that a constant current according to the current of the bias current source BC1 is supplied to the oscillation inverter 16.

[0052] FIG. 4 is a circuit diagram showing a crystal oscillation circuit 400 of a third comparative example, which is another configuration for reducing power consumption.

[0053] The crystal oscillation circuit 400 of the third comparative example is provided with a constant voltage regulator CVR that steps down the power supply voltage VDD to generate a constant voltage VDDX. A stabilizing capacitance CX is connected to the constant voltage regulator CVR via a voltage supply line L3 of the constant voltage VDDX and a connection terminal DX. The source of the transistor PM4 of the oscillation inverter 16 is connected to the voltage supply line L3 of the constant voltage VDDX. As a result, a constant current is supplied to the oscillation inverter 16, similar to the crystal oscillation circuit 300 of the second comparative example.

[0054] In the crystal oscillation circuit 300 of the second comparative example, the transistor PM3 is inserted between the oscillation inverter 16 and the voltage supply line L1 of the power supply voltage VDD, which inevitably narrows the operating voltage range. Therefore, if the voltage level of the power supply voltage VDD drops, there is a risk that the gain of the oscillation stage will be insufficient and oscillation will stop.

[0055] Furthermore, in the crystal oscillation circuit 400 of the third comparative example, a connection terminal DX is required for connecting the stabilizing capacitance CX to the constant voltage regulator CVR, and there is a risk that the number of terminals cannot be secured in an MCU or the like with fewer pins.

[0056] In contrast, in the crystal oscillation circuit 100 of this embodiment, the operating state is switched according to the voltage level of the power supply voltage VDD as described above. Specifically, when the voltage level of the power supply voltage VDD is higher than a predetermined reference value (Equation 1), the crystal oscillation circuit 100 is in the same circuit state as the second comparative example, and the oscillation inverter 16 is in a state of oscillating at a constant current.

[0057] 2 is a diagram showing the relationship between the power supply voltage VDD and the current consumption of the crystal oscillation circuit 100. When the power supply voltage VDD is higher than a predetermined reference value, the oscillation inverter 16 oscillates at a constant current, so that the current consumption can be suppressed to a constant value.

[0058] On the other hand, when the power supply voltage VDD is lower than a predetermined reference value, that is, when it is expressed by the above (Equation 2), the crystal oscillation circuit 100 is in a circuit state similar to that of the first comparative example. Therefore, unlike the second comparative example, the crystal oscillation circuit 100 of this embodiment can ensure the gain of the oscillation inverter 16 up to a low voltage, and can maintain oscillation even at a low voltage.

[0059] Moreover, unlike the third comparative example, there is no need to provide a constant voltage regulator CVR, and therefore no need for a connection terminal DX for connecting a stabilizing capacitance CX.

[0060] As described above, the crystal oscillation circuit 100 of this embodiment operates in accordance with the voltage level of the power supply voltage VDD to suppress current consumption when the voltage level is high, and operates to ensure the gain of the oscillation stage when the voltage level is low. This makes it possible to suppress current consumption when the voltage level of the power supply voltage VDD is high while ensuring the gain of the oscillation inverter 16 when the voltage level of the power supply voltage VDD drops.

[0061] Next, the operation of the slope adjustment circuit 13, particularly the effect of the slope adjustment circuit 13 having the capacitive element C1, will be described with reference to Figures 6A, 6B, 7A, 7B, 8A, and 8B. In the following description, the case where the slope adjustment circuit 13 does not have the capacitive element C1 (i.e., the case where it is composed only of an inverter made up of transistors PM2 and NM2) will be referred to as "having no slope adjustment function."

[0062] 6A and 6B are diagrams showing voltage changes in the output voltage PG of the slope adjustment circuit 13 when the voltage value of the power supply voltage VDD monotonically decreases over time.

[0063] 6A, when the voltage value of the power supply voltage VDD decreases monotonically over time, the power supply voltage divided by the resistor ladder consisting of resistors R1 and R2 (i.e., the voltage input to the inverting input terminal of the hysteresis comparator CP1), {R2 / (R1+R2)}×VDD, also decreases. When this voltage falls below the reference voltage VREF, the output voltage PG changes from a high level (=VDD) to a low level (=GND) in response to a change in the comparison result signal CMP_0 output from the hysteresis comparator CP1.

[0064] 6B, if there is no slope adjustment function, the output voltage PG becomes the GND level as soon as the divided voltage of the resistor ladder falls below the reference voltage VREF. In contrast, if a slope adjustment circuit 13 having a slope adjustment function is provided as in this embodiment, the output voltage PG of the slope adjustment circuit 13 has a waveform whose voltage value changes gradually over time and reaches the ground potential (GND).

[0065] FIG. 7A is a graph showing the oscillation waveforms of the drain voltage PD of the transistor PM3 and the output of the oscillation inverter 16 (i.e., the output from the connection terminal XT1) when it is assumed that the slope adjustment circuit 13 does not have a slope adjustment function (i.e., there is no capacitive element C1).

[0066] If the slope adjustment circuit 13 does not have a slope adjustment function, the drain voltage PD of the transistor PM3 changes abruptly when the divided voltage of the resistor ladder falls below the reference voltage VREF (i.e., the output voltage PG changes to the GND level), which causes the oscillation waveform of the output of the oscillation inverter 16 to become distorted.

[0067] In addition, since the output voltage PG is also supplied to the gate of the transistor PM5 provided for adjusting the current of the Schmitt buffer SB1, the threshold of the Schmitt buffer SB1 also changes according to the change in the output voltage PG. At this time, a mismatch may occur between the time change in the drain voltage PD of the transistor PM3 and the time change in the threshold of the Schmitt buffer SB1.

[0068] 7B is a diagram showing the signal waveform of the clock signal CLK that is the output of the Schmitt buffer SB1, assuming that there is no slope adjustment function in the slope adjustment circuit 13. As described above, a mismatch occurs between the time change in the drain voltage PD of the transistor PM3 and the time change in the threshold of the Schmitt buffer SB1, which may cause so-called "whiskers" in the CLK signal or partial period extension.

[0069] FIG. 8A is a graph showing the oscillation waveforms of the drain voltage PD of the transistor PM3 and the output (output from the connection terminal XT1) of the oscillation inverter 16 when the slope adjustment circuit 13 has a slope adjustment function (that is, when the capacitive element C1 is present).

[0070] As described above, the output voltage PG of the slope adjustment circuit 13 changes gradually over time after the divided voltage of the resistor ladder falls below the reference voltage VREF. Therefore, the drain voltage PD of the transistor PM3 also changes gradually compared to a case without the slope adjustment function. In addition, the threshold of the Schmitt buffer SB1 also changes gradually, so there is no mismatch in the timing of each change over time.

[0071] 8B is a diagram showing the signal waveform of the clock signal CLK when the slope adjustment circuit 13 has a slope adjustment function. When the slope adjustment function is provided, there is no mismatch between the time change in the drain voltage PD of the transistor PM3 and the time change in the threshold of the Schmitt buffer SB1, so that it is possible to suppress the occurrence of spikes and period extension in the oscillation waveform of the clock signal CLK.

[0072] As described above, in the crystal oscillator circuit 100 of this embodiment, the slope adjustment circuit 13 can make the change in the output voltage PG supplied to the gates of the transistors PM3 and PM5 more gradual, thereby making it possible to suppress the occurrence of spikes and lengthening of the period of the clock signal CLK.

[0073] In addition, the slope adjustment circuit 13 can be expected to have an effect as an output filter for the current regulator circuit 12. The current regulator circuit 12 of this embodiment is composed of a transistor PM1, an amplifier AP1, and a bias current source BC1.

[0074] The amplifier AP1 constituting the current regulator circuit 12 has a function of buffering the drain gate voltage VIP of the transistor PM1 and converting impedance from high impedance to low impedance.

[0075] Unlike the configuration of this embodiment, in a configuration in which the gate of the transistor PM1 is directly connected to the slope adjustment circuit 13 without the amplifier AP1, if the impedance of the transistor PM1 is high, the drain gate voltage VIP of the transistor PM1 may fluctuate during the switching operation of the slope adjustment circuit 13. Furthermore, noise generated in the oscillation stage 14 may fluctuate the drain gate voltage VIP of the transistor PM1 via parasitic coupling capacitance of elements, wiring, etc. Fluctuations in the voltage VIP cause fluctuations in the threshold of the Schmitt buffer SB1 and degradation of the oscillation characteristics due to current fluctuations in the oscillation inverter 16.

[0076] In contrast, in the crystal oscillation circuit 100 of this embodiment, the drain gate voltage VIP of the transistor PM1 is impedance converted and buffered via the amplifier AP1, so that fluctuations in the voltage VIP can be suppressed.

[0077] As described above, according to the crystal oscillation circuit 100 of this embodiment, the power drop detection circuit 11 switches the operating state of the oscillation stage 14 in accordance with the voltage level of the power supply voltage VDD, thereby making it possible to suppress current consumption when the power supply voltage VDD is high and to ensure the gain of the oscillation inverter 16 so that oscillation does not stop when the power supply voltage drops.

[0078] In addition, the slope adjustment function of the slope adjustment circuit 13 makes the voltage change of the output voltage PG supplied to the oscillation stage 14 gentler, thereby making it possible to suppress the occurrence of spikes and lengthening of the period in the oscillation waveform of the clock signal CLK output from the crystal oscillation circuit 100.

[0079] Furthermore, according to the configuration of the current regulator circuit 12 of this embodiment, fluctuations in the drain gate voltage VIP of the transistor PM1 can be suppressed, and the deterioration of the oscillation characteristics due to fluctuations in the threshold of the Schmitt buffer SB1 and current fluctuations in the oscillation inverter 16 can be suppressed. EXAMPLES

[0080] Next, a description will be given of a second embodiment of the present invention. The crystal oscillation circuit of this embodiment differs from the crystal oscillation circuit 100 of the first embodiment in the configuration of the current regulator circuit.

[0081] 9 is a circuit diagram showing the configuration of the current regulator circuit 12A of this embodiment. The current regulator circuit 12A is made up of a bias current source BC1, an amplifier AP2, and a reference voltage generating circuit VR2.

[0082] One end of the reference voltage generating circuit VR2 is connected to a voltage supply line L1 of a power supply voltage VDD, and the other end of the reference voltage generating circuit VR2 is connected to one end of a bias current source BC1 and to the non-inverting input terminal of an amplifier AP2.

[0083] 10 is a circuit diagram showing an example of the circuit configuration of the reference voltage generating circuit VR2. The reference voltage generating circuit VR2 is composed of (n+1) transistors PM1-0 to PM1-n connected in series. Each of the transistors PM1-0 to PM1-n is composed of a P-channel MOSFET.

[0084] The drain of the transistor P1-0 is connected to one end of a bias current source BC1. The source of the transistor P1-n is connected to a voltage supply line L1 of a power supply voltage VDD. The gates of the transistors PM1-0 to PM1-n are connected to each other and to a non-inverting input terminal of an amplifier AP2 (not shown in FIG. 10).

[0085] 11 is a circuit diagram showing another example of the circuit configuration of the reference voltage generating circuit VR2. The transistors PM1-0 to PM1-n are connected in series between a voltage supply line L1 of a power supply voltage VDD and one end of a bias current source BC1, with each gate and drain being in a so-called diode-connected state.

[0086] 12 is a circuit diagram showing an example of the circuit configuration of the amplifier AP2. The amplifier AP2 is composed of a constant current source CS1, a transistor NM5, and a differential stage including a transistor NM6, a transistor NM7, a transistor NM8, a transistor PM7, and a transistor PM8.

[0087] One end of the constant current source CS1 is connected to a voltage supply line L1 of the power supply voltage VDD. The transistor NM5 is an N-channel MOSFET, and its drain and gate are connected to the other end of the constant current source CS1. The source of the transistor NM5 is connected to a voltage supply line L2 of the ground potential VSS.

[0088] The differential pair of transistors NM7 and NM8 are composed of N-channel MOSFETs. A reference voltage VIP2, which is the output voltage of a reference voltage generating circuit VR2, is supplied to the gate of the transistor NM7. An output voltage PG_PRE is output from the gate of the transistor NM8.

[0089] The drain of the transistor NM7 is connected to the drain of the transistor PM7. The drain of the transistor NM8 is connected to the drain of the transistor PM8. The sources of the transistors NM7 and NM8 are connected to the drain of the transistor NM6.

[0090] The transistor NM6 is composed of an N-channel MOSFET. The source of the transistor NM6 is connected to the voltage supply line L2 of the ground potential VSS. The gate of the transistor NM6 is connected to the gate of the transistor NM5.

[0091] The transistors PM7 and PM8 are each configured by a P-channel MOSFET. The sources and back gates of the transistors PM7 and PM8 are connected to a voltage supply line L1 of a power supply voltage VDD. The gates of the transistors PM7 and PM8 are connected to each other.

[0092] The amplifier AP2 is preferably a high-speed amplifier because noise generated in the oscillation stage 14 (not shown in FIG. 12) of the crystal oscillation circuit may cause the reference voltage VIP2 to fluctuate. For this reason, in this embodiment, a single amplifier as shown in FIG. 12 is adopted as the configuration of the amplifier AP2.

[0093] The crystal oscillator circuit of this embodiment has the current regulator circuit 12A including the reference voltage generating circuit VR2 and the amplifier AP2 configured as described above, so that it is possible to increase the negative resistance without degrading the frequency characteristics when oscillating in a high frequency band. This will be described below.

[0094] In general, the crystal unit XTAL can be replaced with an equivalent circuit using inductance Le and effective resistance Re, and the crystal oscillation circuit can be replaced with a load capacitance CL and negative resistance -RL. In this case, the negative resistance -RL is expressed by the following equation (3) using the conductance gm of the oscillation inverter, the oscillation frequency f, and the oscillation capacitances Cg and Cd.

[0095] -RL = -gm / (2πf) 2 *Cg*Cd (3) The conductance gm of the oscillation inverter is expressed by the following equation (4) using the input voltage Vin and the output current Iout.

[0096] gm = ΔIout / ΔVin (4) Moreover, the oscillation condition is expressed by the following equation (5).

[0097] -RL≧Re (5) In other words, when the above condition is met, the effective resistance Re of the crystal resonator XTAL is cancelled out by the negative resistance -RL, the impedance loss of the crystal oscillation circuit 100 is eliminated, and the LC oscillation of the inductance Le and the load capacitance CL occurs, enabling oscillation.

[0098] For stable oscillation, the negative resistance -RL must be smaller than 0Ω, and its absolute value must be a constant equal to or greater than 1 time the effective resistance Re. If the oscillation margin, which indicates the margin from the oscillating state to the oscillation stopping state, is n, the oscillation margin n is expressed by the following equation (6).

[0099] n=|-RL| / Re (6) In general, it is considered that the oscillation margin n should be at least three times the effective resistance Re in consumer crystal oscillators, and at least five times the effective resistance Re in automotive crystal oscillators.

[0100] In addition, in order to increase the negative resistance -RL in the high frequency band, it is necessary to increase the current of the oscillation inverter according to formula (4). The characteristics of the current consumption and negative resistance when the current of the oscillation inverter is increased to oscillate in the high frequency band are explained below.

[0101] Fig. 13 is a diagram showing the current consumption characteristics of the crystal oscillation circuit 200 (Fig. 2) of the first comparative example in high frequency band oscillation. The middle part of Fig. 16 is a diagram showing the negative resistance characteristics of the crystal oscillation circuit 200 of the first comparative example in high frequency band oscillation.

[0102] As shown in Fig. 13, the crystal oscillation circuit 200 of the first comparative example oscillates when the power supply voltage VDD has a voltage value in the range of A to E, but the higher the power supply voltage VDD, the greater the current consumption. As shown in the middle of Fig. 16, at frequency f0, the higher the power supply voltage VDD is from C to D to E, the higher the negative resistance shifts to a higher band. Since the amount of fluctuation in the negative resistance is large, when the power supply voltage VDD reaches E, oscillation may stop depending on various conditions. Furthermore, at frequency f1, the negative resistance is relatively stable, but there is some variation, so there is a possibility that a frequency deviation may appear depending on the power supply voltage VDD.

[0103] Fig. 14 is a diagram showing the current consumption characteristics of the crystal oscillation circuit 400 (Fig. 4) of the third comparative example in high frequency band oscillation. The lower part of Fig. 16 is a diagram showing the negative resistance characteristics of the crystal oscillation circuit 400 of the third comparative example in high frequency band oscillation.

[0104] The voltage supplied by the constant voltage regulator CVR is constant (constant voltage VDDX), and the current consumption does not increase depending on the power supply voltage VDD, so the negative resistance is stable at frequencies above f0. However, the constant voltage regulator CVR does not operate at power supply voltages VDD below B in Figure 14, and oscillation also stops.

[0105] 1 in the high frequency band, it is possible to adjust the mirror ratio of the transistor PM3 with respect to the transistor PM1 and increase the current of the oscillation inverter 16. For example, when the transistor PM1 is one unit, the current can be increased by increasing the size of the transistor PM3 as "1 unit x n".

[0106] However, increasing the number of units of transistor PM3 increases the parasitic capacitance of the MOS transistor, the number of wirings, and the wiring capacitance, which in turn degrades the frequency characteristics and also reduces the negative characteristics.

[0107] In contrast to this, the crystal oscillation circuit of this embodiment has a configuration in which the current regulator circuit 12 of the crystal oscillation circuit 100 shown in Fig. 1 is replaced with a current regulator circuit 12A shown in Fig. 9. Also, the reference voltage generating circuit VR2 has a configuration as shown in Fig. 10 or 11.

[0108] The reference voltage generating circuit VR2 generates a reference voltage VIP2 based on the power supply voltage VDD. The reference voltage VIP2 is supplied to the gate of the transistor PM3.

[0109] The reference voltage VIP2 generated by the reference voltage generating circuit VR2 has a voltage value lower than the drain gate voltage VIP of the transistor PM1 in the first embodiment. Therefore, the gate voltage of the transistor PM3 can be lowered and the amount of current of the transistor PM3 can be increased. Therefore, it is not necessary to increase the size of the transistor PM3, so that the parasitic capacitance and wiring capacitance of the MOS transistor do not increase, and it is possible to increase the negative resistance without degrading the frequency characteristics.

[0110] Fig. 15 is a diagram showing the current consumption characteristics of the crystal oscillation circuit of this embodiment during high frequency band oscillation. The upper part of Fig. 16 is a diagram showing the negative resistance characteristics of the crystal oscillation circuit of this embodiment during high frequency band oscillation.

[0111] When the voltage value of the power supply voltage VDD is in the range of A to D, the current is increased, and the negative resistance is increased. On the other hand, when the voltage value of the power supply voltage VDD is in the range of D to E, the current consumption is suppressed by performing the current adjustment required for the negative resistance of the current of the oscillation inverter 16. Therefore, according to the configuration of the crystal oscillation circuit of this embodiment, a stable negative resistance is realized at frequencies equal to or higher than f0 and in a wide range of the power supply voltage VDD from A to E, making it possible to perform stable oscillation.

[0112] As described above, according to the crystal oscillator circuit of this embodiment, by using the reference voltage generation circuit VR2 that generates the reference voltage VIP2 based on the power supply voltage VDD, and the current regulator circuit 12A that is configured using the amplifier AP2, which is a high-speed amplifier, it is possible to oscillate in the high-frequency band with low current consumption when the voltage value of the power supply voltage VDD is in the low range.

[0113] It should be noted that the present invention is not limited to the above-described embodiments. For example, the configuration of the current regulator circuit is not limited to the above-described embodiments.

[0114] 17 is a circuit diagram showing a modified current regulator circuit. The modified current regulator circuit 12B is composed of a bias current source BC1, an amplifier AP2, a reference voltage generating circuit VR2, and resistors R4 and R5. One end of the resistor R4 is connected to a voltage supply line L1 of a power supply voltage VDD, and the other end is connected to one end of the resistor R5 and the inverting input terminal of the amplifier AP2. One end of the resistor R5 is connected to the other end of the resistor R4 and the inverting input terminal of the amplifier AP2, and the other end is connected to the output terminal of the amplifier AP2.

[0115] In the current regulator circuit 12B of the modified example, unlike the current regulator circuit 12A of the second embodiment, the output voltage PG_PRE of the amplifier AP2, i.e., the gate voltage supplied to the transistor PM3 via the slope adjustment circuit 13, is adjusted based on the resistance ratio of the resistors R1 and R2. In other words, the user can adjust the gate voltage of the transistor PM3 by changing the setting of the resistance ratio of the resistors R1 and R2.

[0116] In the above embodiment, the current supplied to the oscillation inverter 16 is adjusted by the transistor PM3 made of a P-channel MOSFET, but it may be configured to be adjusted using an N-channel MOSFET instead. Also, the circuit may be configured to adjust the current using both a P-channel MOSFET and an N-channel MOSFET.

[0117] In addition, in the above-described Second Embodiment, as circuit examples of the reference voltage generation circuit VR2, the circuit configurations of FIGS. 10 and 11 were shown. However, the configuration of the reference voltage generation circuit VR2 is not limited to this, and for example, a combination of the configuration of FIG. 10 and the configuration of FIG. 11 may be used. Also, in each of the configurations of FIGS. 10 and 11, the reference voltage VIP2 may be taken from any drain terminal (i.e., the connection node with an adjacent transistor) of the transistors PM1-0 to PM1-n connected in series. The reference voltage generation circuit VR2 may be any circuit capable of generating a voltage based on the power supply voltage VDD, and circuits with various configurations can be used.

[0118] In addition, in the above-described Second Embodiment, the case where the amplifier AP2 is configured by a single amplifier as shown in FIG. 12 was described as an example. However, the configuration of the amplifier AP2 is not limited to this, and any amplifier capable of obtaining desired frequency characteristics can use circuits with various configurations.

Description of Reference Numerals

[0119] 100 Crystal Oscillation Circuit 11 Power Supply Drop Detection Circuit 12 Current Regulator Circuit 13 Slope Adjustment Circuit 14 Oscillation Stage 15 Clock Output Stage 16 Oscillation Inverter

Claims

1. An oscillation circuit that is connected to a crystal oscillator and oscillates based on the oscillation of the crystal oscillator, a voltage comparator circuit that outputs a comparison result signal having a first voltage level when a voltage value of a power supply voltage is lower than a predetermined reference value, and a second voltage level when the voltage value of the power supply voltage is higher than the predetermined reference value; a current regulator circuit including a bias current source that delivers a constant current; an oscillation inverter comprising a first transistor of a first conductivity type and a second transistor of a second conductivity type connected in series, the oscillation inverter receiving a current that varies in accordance with fluctuations in the power supply voltage when the comparison result signal is at the first voltage level, and receiving a current that corresponds to the constant current when the comparison result signal is at the second voltage level; A crystal oscillator circuit comprising:

2. a third transistor of the first conductivity type connected between a supply line of the power supply voltage and one end of the first transistor and having a control end receiving a voltage corresponding to the comparison result signal; 2. The crystal oscillator circuit according to claim 1, wherein the oscillation inverter is supplied with a current having an amount corresponding to a voltage value of the power supply voltage or a current obtained by current mirroring the constant current based on a voltage applied to a control terminal of the third transistor.

3. 2. The crystal oscillation circuit according to claim 1, further comprising an inverter formed of a pair of transistors that are turned on and off complementarily in response to the input of the comparison result signal, and a voltage adjustment circuit that converts the voltage level of the comparison result signal into a voltage level corresponding to the output of the current regulator circuit and outputs the voltage level.

4. 4. The crystal oscillation circuit according to claim 3, wherein the voltage adjustment circuit has a capacitance element connected in parallel to the inverter between the input and the output.

5. The current regulator circuit is a fourth transistor of the first conductivity type, the fourth transistor having a first end connected to a voltage supply line of the power supply voltage and a second end connected to one end of the bias current source; a first amplifier having a non-inverting input terminal connected to the second terminal and a control terminal of the fourth transistor, and an output terminal and an inverting input terminal connected in feedback; 2. The crystal oscillator circuit according to claim 1, further comprising:

6. The current regulator circuit comprises: a reference voltage generating circuit including a plurality of cascade-connected transistors, one end of which is connected to a voltage supply line of the power supply voltage and the other end of which is connected to one end of the bias current source; an amplifier having a non-inverting input terminal connected to the other terminal of the reference voltage generating circuit and an output terminal and an inverting input terminal connected to each other; 2. The crystal oscillator circuit according to claim 1, further comprising:

7. The current regulator circuit comprises: a reference voltage generating circuit including a plurality of cascade-connected transistors, one end of which is connected to a voltage supply line of the power supply voltage and the other end of which is connected to one end of the bias current source; an amplifier having a non-inverting input terminal connected to the other terminal of the reference voltage generating circuit; a first resistor element having one end connected to a voltage supply line of the power supply voltage and the other end connected to an inverting input terminal of the amplifier; a second resistive element having one end connected to the other end of the first resistive element and the inverting input end of the amplifier and having the other end connected to the output end of the amplifier; 2. The crystal oscillator circuit according to claim 1, further comprising:

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