Silicon thin film transistor and display having silicon thin film transistor

Abstract

To provide a display having a silicon thin film transistor and a semiconductor oxide thin film transistor.SOLUTION: An electronic device may include a display having an array of display pixels on a substrate. These display pixels may be an organic light-emitting diode display pixel, or a display pixel in a liquid crystal display. In the organic light-emitting diode display, a hybrid thin film transistor structure, including a semiconductor oxide thin film transistor, a silicon thin film transistor and a capacitor structure, may be formed. The capacitor structure may be superposed on the semiconductor oxide thin film transistor. The organic light-emitting diode display pixel may have a combination of the oxide transistor and the silicon transistor.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] This application generally relates to electronic devices, and more particularly to electronic devices including a display having thin film transistors.

Background Art

[0002] Electronic devices often include a display. For example, cellular phones and portable computers include a display for presenting information to a user.

[0003] Displays, such as liquid crystal displays, are formed from multiple layers. A liquid crystal display may include, for example, an upper polarizer layer and a lower polarizer layer, a color filter layer including an array of color filter elements, a thin film transistor layer including thin film transistors and display pixel electrodes, and a layer of liquid crystal material interposed between the color filter layer and the thin film transistor layer. Each display pixel typically includes a thin film transistor for controlling the application of a signal to a display pixel electrode structure within that display pixel.

[0004] Displays, such as organic light emitting diode displays, have an array of display pixels based on light emitting diodes. In this type of display, each display pixel includes a light emitting diode and a thin film transistor for controlling the application of a signal to that light emitting diode.

[0005] Displays often include a thin film display drive circuit mechanism. For example, a gate drive circuit mechanism and a demultiplexer circuit mechanism on the display can be formed from thin film transistors.

Summary of the Invention

Problems to be Solved by the Invention

[0006] Failure to pay attention may cause the display pixels of the display and the thin-film transistor circuit mechanism within the display driving circuit mechanism to exhibit non-uniformity, excessive leakage current, insufficient driving strength, poor area efficiency, hysteresis, and other problems. Therefore, it would be desirable to be able to provide an improved display for an electronic device.

Means for Solving the Problem

[0007] An electronic device can provide a display. This display can have an array of display pixels on a substrate. Those display pixels can be organic light-emitting diode display pixels or display pixels within a liquid crystal display.

[0008] Within an organic light-emitting diode display, a hybrid thin-film transistor structure including a semiconductor oxide thin-film transistor, a silicon thin-film transistor, and a capacitor structure can be formed. The capacitor structure can be superimposed on the semiconductor oxide thin-film transistor. The capacitor structure can also be formed from a plurality of overlapping electrode layers formed from a source-drain metal layer, a polysilicon layer, and a gate metal layer and can be used.

[0009] The organic light-emitting diode display pixels can have a combination of an oxide transistor and a silicon transistor. Transistors such as driving transistors coupled to the light-emitting diodes can be formed from an oxide transistor structure, and switching transistors can be formed from a silicon transistor structure.

[0010] Within a liquid crystal display, the display driving circuit mechanism may include a silicon thin film transistor circuit mechanism, and the display pixels may be based on oxide thin film transistors. When forming the silicon transistor gate and the oxide transistor gate, a single layer or two different layers of gate metal can be used. The silicon transistor may have a gate that overlaps a floating gate structure. The oxide transistor can be incorporated into the display driving circuit mechanism.

[0011] The display driving circuit mechanism can be configured to expose the silicon transistor circuit mechanism to a lower voltage amplitude than the oxide transistor circuit mechanism within the array of display pixels.

Brief Description of the Drawings

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DETAILED DESCRIPTION OF THE INVENTION

[0013] A display within an electronic device can provide a drive circuit mechanism for displaying an image on an array of display pixels. An exemplary display is shown in FIG. 1. As shown in FIG. 1, the display 14 can have one or more layers such as a substrate 24. A layer such as the substrate 24 can be formed from a layer of a flat rectangular material such as a flat glass layer. The display 14 can have an array of display pixels 22 for displaying an image to a user. The array of display pixels 22 can be formed from rows and columns of display pixel structures on the substrate 24. There can be any suitable number (e.g., 10 or more, 100 or more, or 1000 or more) of rows and columns within the array of display pixels 22.

[0014] A display driving circuit mechanism such as the display driving integrated circuit 16 can be coupled to a conductive path such as a metal wiring on the substrate 24 using solder or a conductive adhesive. The display driving integrated circuit 16 (which may also be referred to as a timing controller chip) may include a communication circuit mechanism for communicating with the system control circuit mechanism via the path 25. The path 25 can be formed from wiring on a flexible printed circuit or other cables. The control circuit mechanism can be disposed on a main logic board within an electronic device such as a cellular phone, a computer, a set-top box, a media player, a portable electronic device, or other electronic devices in which the display 14 is used. During operation, the control circuit mechanism can supply information about the image to be displayed on the display 14 to the display driving integrated circuit 16. To display an image on the display pixels 22, the display driving integrated circuit 16 supplies corresponding image data to the data line D while issuing clock signals and other control signals to assist thin-film transistor display driving circuit mechanisms such as the gate driving circuit mechanism 18 and the demultiplexing circuit mechanism 20.

[0015] The gate driving circuit mechanism 18 can be formed on the substrate 24 (e.g., on the right and left edges of the display 14, on only a single edge of the display 14, or at other locations within the display 14). By using the demultiplexer circuit mechanism 20, the data signals from the display driving integrated circuit 16 can be distributed onto a plurality of corresponding data lines D. In the exemplary arrangement of FIG. 1, the data lines D extend vertically through the display 14. Each data line D is associated with a corresponding column of the display pixels 22. The gate lines G extend horizontally through the display 14. Each gate line G is associated with a corresponding row of the display pixels 22. The gate driving circuit mechanism 18 can be disposed on the left side of the display 14, on the right side of the display 14, or on both the right and left sides of the display 14 as shown in FIG. 1.

[0016] The gate drive circuit mechanism 18 can assert a gate signal (which may also be referred to as a scanning signal) on the gate line G within the display 14. For example, the gate drive circuit mechanism 18 can receive a clock signal and other control signals from the display driver integrated circuit 16, and in response to those received signals, starting from the gate line signal G in the first row of the display pixels 22, can assert the gate signals on the gate line G in sequence. When each gate line is asserted, the corresponding display pixels in the row where that gate line is asserted display the display data that appears on the data line D.

[0017] Display drive circuit mechanisms such as the demultiplexer circuit mechanism 20 and the gate line drive circuit mechanism 18 can be formed from thin film transistors on the substrate 24. The thin film transistors can also be used when forming the circuit mechanisms within the display pixels 22. To improve display performance, thin film transistor structures within the display 14 that meet desired criteria such as leakage current, switching speed, drive strength, uniformity, etc. can be used. The thin film transistors within this display 14 can generally be formed using any suitable type of thin film transistor technology (e.g., silicon-based, semiconductor oxide-based, etc.).

[0018] In one suitable arrangement configuration, which may be described as an example in this specification, the channel regions (active regions) within some of the thin film transistors on the display 14 are formed from silicon (such as polysilicon deposited using a low temperature process, which may also be referred to as LTPS or low temperature polysilicon), and the channel regions within other thin film transistors on the display 14 are formed from a semiconductor oxide material (such as amorphous indium gallium zinc oxide, which may also be referred to as IGZO). Optionally, other types of semiconductors, such as amorphous silicon, semiconductor oxides other than IGZO, etc., can be used when forming these thin film transistors. In this type of hybrid display configuration, silicon transistors (such as LTPS transistors) can be used when attributes such as switching speed and good drive current are desired (such as for the gate driver within a liquid crystal diode display, or within a portion of an organic light emitting diode display pixel where switching speed is a consideration), while oxide transistors (such as IGZO transistors) can be used when low leakage current is desired (such as within liquid crystal diode display pixels and display drive circuit mechanisms), or when high uniformity between pixels is desired (such as within an array of organic light emitting diode display pixels). Other considerations (such as considerations related to power consumption, resource consumption, hysteresis, etc.) can also be taken into account.

[0019] Oxide transistors, such as IGZO thin film transistors, are generally n-channel devices (i.e., NMOS transistors). Silicon transistors can be fabricated using a p-channel design or an n-channel design (i.e., LTPS devices can be either PMOS or NMOS). The combination of these thin film transistor structures can provide optimal performance.

[0020] In an organic light emitting diode display, each display pixel includes a corresponding organic light emitting diode. A schematic diagram of an exemplary organic light emitting diode display pixel 22-1 is shown in FIG. 2. As shown in FIG. 2, the display pixel 22-1 may include a light emitting diode 26. A positive power supply voltage ELVDD can be supplied to the positive power supply terminal 34, and a ground power supply voltage ELVSS can be supplied to the ground power supply terminal 36. The amount of current flowing through the diode 26, and thus the amount of emitted light 40 from the display pixel 22-1, is controlled by the state of the driving transistor 28.

[0021] To ensure that the transistor 28 is held in the desired state between consecutive frames of data, the display pixel 22-1 may include a storage capacitor such as the storage capacitor Cst. The voltage on the storage capacitor Cst controls the transistor 28 by being applied to the gate of the transistor 28 at node A. One or more switching transistors, such as the switching transistor 30, can be used to load data into the storage capacitor Cst. When the switching transistor 30 is off, the data line D is insulated from the storage capacitor Cst, and the gate voltage on terminal A is equal to the data value stored in the storage capacitor Cst (i.e., the data value from the previous frame of display data is displayed on the display 14). When the gate line G (which may also be referred to as a scan line) associated with the display pixel 22-1 is asserted, the switching transistor 30 turns on, and a new data signal on the data line D is loaded into the storage capacitor Cst. This new signal on the capacitor Cst controls the state of the transistor 28 by being applied to the gate of the transistor 28 at node A, thereby adjusting the amount of corresponding light 40 emitted by the light emitting diode 26.

[0022] Organic light-emitting diode display pixels such as pixel 22-1 in FIG. 2 can use a thin-film transistor structure of the type shown in FIG. 3. In this type of structure, two different types of semiconductors are used. As shown in FIG. 3, circuit mechanism 72 can include a display pixel structure such as light-emitting diode cathode terminal 42 and light-emitting diode anode terminal 44. Organic light-emitting diode emissive material 47 can be inserted between cathode 42 and anode 44. Dielectric layer 46 can serve to define the layout of the display pixel and may be referred to as a pixel defining layer. A planarization layer 50 can be formed on top of thin-film transistor structure 52. Thin-film transistor structure 52 can be formed on buffer layer 54 on substrate 24.

[0023] Thin-film transistor structure 52 can include silicon transistor 58. Transistor 58 can be an LTPS transistor formed using a “top gate” design and can function as a switching transistor within the organic light-emitting diode display pixel (see, for example, transistor 30 in pixel 22-1 of FIG. 2). Transistor 58 can have polysilicon channel 62 covered by a gate insulating layer 64 (e.g., a layer of silicon oxide). Gate 66 can be formed from a patterned metal (e.g., as an example, molybdenum). Gate 66 can be covered by an interlayer dielectric layer (e.g., silicon nitride layer 68 and silicon oxide layer 70). Source-drain contacts 74 and 76 can contact opposite side portions of polysilicon layer 62 to form silicon thin-film transistor 58.

[0024] The thin film transistor structure 52 may also include a thin film transistor and a capacitor structure 60. The structure 60 may include a storage capacitor (i.e., the storage capacitor Cst in FIG. 2) and an oxide thin film transistor structure. This storage capacitor may have a first terminal (sometimes referred to as a plate, electrode, or electrode layer) formed from a polysilicon layer 62’ (patterned as part of the same layer as layer 62). The terminal 62’ can be covered by a gate insulating layer 64’, which can be an extension of the gate insulating layer 64. This capacitor may have a second terminal formed from a metal layer 66’. The metal layer 66’ can be patterned from the same metal layer used when forming the gate 66 of the transistor 58. The metal layer 66’ can be covered by a dielectric layer 68 and a dielectric layer 70. The thin film transistor within the structure 60 can be a “bottom gate” oxide transistor. The layer 66’, which functions as the second terminal of the capacitor Cst (i.e., node A in FIG. 2), can also function as the gate of this oxide transistor. This oxide transistor can function as the driving transistor 28 in FIG. 2. The “gate insulator” of this oxide transistor can be formed from an interlayer dielectric layer (i.e., layers 68 and 70). The channel semiconductor of this oxide transistor can be formed from an oxide layer 80 (e.g., IGZO). By overlaying the oxide layer 80 on the polysilicon capacitor electrode layer 62’ (i.e., overlaying the oxide transistor on the capacitor), space can be saved. The source-drain terminals 82 and 84 can be formed from a metal that contacts the opposing ends of the semiconductor oxide layer 80.

[0025] Transistors such as LTPS transistors and oxide transistors can be formed in various layouts. For example, LTPS transistors tend to have high carrier mobility. As a result, LTPS transistors may have a relatively long gate length L and a relatively short gate width in order to ensure an appropriate low W / L ratio, and the relatively high mobility of these transistors may be offset. This may make LTPS transistors relatively inefficient with respect to pixel layout. Oxide transistors can be constructed with a W / L ratio having a smaller aspect ratio (for example, 4 / 4 for oxide compared to 3 / 30 for LTPS). Due to these layout efficiency considerations, it may be preferable to use oxide transistors as the driving transistors within display pixel 22-1. Regarding switching transistors such as transistor 30 in FIG. 2, it may be preferable to use LTPS transistors due to the relatively fast switching speed provided by LTPS transistors.

[0026] Within a display pixel having more (e.g., three or more, four or more, five or more, six or more, seven or more, or eight or more) transistors, the choice of which transistors to implement using LTPS technology and which transistors to implement using oxide technology can be made to balance transistor performance considerations between these two types of transistors.

[0027] When implementing a driving transistor, an LTPS transistor tends to have a larger size (longer channel length) than an oxide transistor, tends to have a larger dark current than an oxide transistor, and may exhibit worse uniformity than an oxide transistor. The LTPS driving transistor may also have a larger hysteresis than an oxide driving transistor. As a result of these factors, in many cases, the driving transistor in an organic light-emitting diode display pixel may advantageously be formed from an oxide transistor. The oxide driving transistor may exhibit low leakage current and minimal hysteresis.

[0028] When implementing a switching transistor, an LTPS transistor can be made smaller than an oxide transistor, can exhibit less parasitic capacitance than an oxide transistor, and can exhibit lower power consumption than an oxide transistor. As a result of such factors, in many cases, the switching transistor in an organic light-emitting diode display pixel may advantageously be formed from an LTPS transistor. The LTPS switching transistor may exhibit a high switching speed and low parasitic capacitance.

[0029] An exemplary hybrid thin film transistor structure that can be used when implementing both an LTPS transistor and an oxide transistor within a single organic light emitting diode display pixel (e.g., for implementing a circuit such as display pixel circuit 22-1 in FIG. 2) is shown in FIG. 4. The hybrid thin film transistor structure 114 of FIG. 4 includes a silicon thin film transistor 108, a capacitor (Cst) 110, and an oxide transistor 112. The silicon transistor 108 is formed from a polysilicon layer 90. A gate insulating layer 92 covers the polysilicon layer 90. A layer of gate metal is patterned on top of the gate insulating layer 92 to form a gate 94, a capacitor electrode 96, and a gate electrode 98. Layers of interlayer dielectric material such as a silicon nitride layer 116 and a silicon oxide layer 118 can cover those patterned gate metal structures. Source-drain contacts 100 and 94 for the silicon transistor 108 can contact (i.e., short) the polysilicon layer 90 in the vicinity of the channel region 106. The gate 94 of the transistor 108 can function as an implantation mask to enable a low density drain implant to be formed in the polysilicon layer 90 within region 104 adjacent to the polysilicon channel region 106 of the transistor 108.

[0030] The source-drains 100 and 102 of the silicon transistor 108 and the source-drains 122 and 124 of the oxide transistor 112 can be formed from patterned portions of a common metal layer on the interlayer dielectrics 116 and 118.

[0031] The capacitor 110 can have a first terminal formed from a metal electrode 120 and a portion 126 of the polysilicon layer 90. The capacitor 110 can have a second terminal formed from the metal electrode 96.

[0032] The oxide transistor 112 may have a semiconductor oxide layer such as an IGZO layer 128, source-drain contacts 122 and 124, and a gate 98. The gate 98 is separated from the semiconductor oxide 128 that functions as a channel region for the transistor 112 by a dielectric 116 and a dielectric 118. The dielectric 116 and the dielectric 118 thus function as a gate insulator for the oxide transistor 112.

[0033] FIG. 5 is a circuit diagram of another exemplary organic light-emitting diode pixel circuit that can be used within the display 14. The pixel 22-2 includes a driving transistor 28 for driving a current within the light-emitting diode 26. An accumulation capacitor Cst is used to store a signal on the gate of the transistor 28 between frames. A sensing line SENSING is used to implement a compensation scheme for adjusting variations in transistor performance between pixels. Gate lines SCAN and SCAN2 are used when applying control signals to the switching transistors 30-1 and 30-2.

[0034] To optimize the performance within the display pixel 22-2, it may be desirable to use a hybrid structure of the type shown in FIGS. 3 and 4, or other configurations for forming silicon thin-film transistors and / or oxide thin-film transistors and capacitors. For example, it may be desirable to form the driving transistor 28 from an oxide transistor (e.g., an NMOS oxide transistor), while forming switching transistors such as the transistors 30-1 and 30-2 from silicon transistors, or from a mixture of silicon (NMOS and / or PMOS) transistors and oxide (NMOS) transistors.

[0035] In the first exemplary configuration, transistor 30-1 is an oxide transistor, transistor 30-2 is an oxide transistor, and transistor 28 is an oxide transistor. In the second exemplary configuration, transistor 30-1 is a silicon transistor, transistor 30-2 is a silicon transistor, and transistor 28 is an oxide transistor. A hybrid transistor structure, such as the structure of FIG. 3 or the structure of FIG. 4, can be used in this scenario (e.g., to implement transistors 30-1 and 28 and capacitor Cst). In an exemplary third configuration, transistor 30-1 is a silicon transistor, transistor 30-2 is an oxide transistor, and transistor 28 is an oxide transistor. Similar to the second exemplary configuration, a hybrid transistor structure, such as the structure of FIG. 3 or the structure of FIG. 4, can be used to implement transistors 30-1 and 28 and capacitor Cst.

[0036] Optionally, display 14 can be a liquid crystal display. In this type of scenario, each pixel of display 14 can include an electrode structure for applying an electric field to a relevant portion of the liquid crystal layer within the display, a capacitor for storing charge on the electrode between frames of image data, and a thin film transistor for controlling the application of the electric field to the electrode. In one preferred arrangement, the gate drive circuit mechanism 18 and the demultiplexer circuit mechanism 20 (FIG. 1) within the liquid crystal display can be formed from silicon transistors, and the thin film transistors within the display pixels 22 can be formed from oxide transistors. The silicon transistors have a high-mobility channel region, are suitable for fast switching speeds and high drive currents, and operate at low voltage and low power. The oxide thin film transistors within the display pixels 22 exhibit low leakage current.

[0037] A type of thin film transistor structure that can be used when forming a liquid crystal display having both silicon transistors and oxide transistors is shown in FIG. 6. As shown in FIG. 6, the thin film transistor structure 242 may include a silicon thin film transistor structure 216 (for example, for forming various parts of peripheral circuits such as the display driving circuit mechanism 18 and the demultiplexer circuit mechanism 20), and an oxide thin film transistor structure 240 (for example, for forming display pixels 22 in a liquid crystal display having a layout of the type shown by the display 14 in FIG. 1).

[0038] The structure 216 and the structure 240 can be formed on the buffer layer 202 on the substrate 24. The polysilicon layer 204 can be deposited on the buffer 202. The gate insulating layer 206 can be formed on the polysilicon layer 204. By patterning a common layer of metal, the metal structures 218, 220, and the metal structure 228 can be formed. The structure 218 can serve as a gate for a silicon transistor including the source-drain contacts 212 and 214 and a channel formed from the polysilicon 204. The metal structure 228 can serve as a gate for an oxide transistor formed from a semiconductor oxide layer 224 (for example, IGZO) and the source-drain terminals 222 and 226. The metal structure 228 can also serve as a light-shielding body useful for preventing the backlight in the display 14 from reaching the oxide layer 224, so that there is no need to incorporate a separate light-shielding structure in the structure 240. Interlayer dielectrics such as the silicon nitride layer 208 and the silicon nitride layer 210 can cover the gate 218 in the structure 216 and can serve as a gate insulator for the gate 228 in the oxide transistor of the structure 240.

[0039] Metal 230 contacts the source-drain 226 of the display pixel thin-film oxide transistor formed from the oxide layer 224. Metal 230 can be supported by the organic layer 232. On the surface of the organic layer 232, metal 230 can form an electrode having a plurality of finger portions. The dielectric layer 236 can insulate the electrode 230 from the common electrode (Vcom) 234. During operation, an electric field is generated between the electrode 230 and the electrode 234. These electric fields pass through the liquid crystal material within the display. Optionally, the display 14 can incorporate a capacitive touch sensor formed from portions of the Vcom electrode 234. In this type of configuration, an optional metal line such as line 238 can be used to help reduce the resistance of the material used to form the electrode 234 (e.g., a slightly resistive conductive material such as indium tin oxide).

[0040] The thicknesses of layer 208 and layer 210 can be about 6000 angstroms. This relatively large thickness can help minimize the capacitance between the gate 218 and nearby metal structures such as the source-drain 214, but may limit the switching speed within the oxide transistor. To address this concern, a design of the type used by the structure 242' in FIG. 7 can be used. In the arrangement of FIG. 7, an additional semiconductor manufacturing mask can be used to create a gate for the oxide transistor that is formed from a metal layer separate from the metal layer used to form the gate 218. In this approach, by using only a single 3000 angstrom dielectric layer 210' (e.g., formed from a sublayer of silicon nitride and silicon oxide), the oxide layer 224 can be separated from the oxide transistor gate 228', thereby improving the switching speed of the oxide transistor. Due to the arrangement of the structure 242' in FIG. 7, the gate 218 and the gate 228' can be formed from different metals. For example, the gate 218 can be formed from a heat-resistant metal such as Mo to correspond to the elevated temperature associated with the activation of the silicon transistor, while on the other hand, the gate 228' can be formed from a metal with a lower resistance, such as copper.

[0041] In some applications, it may be necessary to consider the handling of high drive voltages (between the gate and the source and drain). The transistor structure 242” of FIG. 8 can be used in scenarios where it is desired to handle relatively large (e.g., 20 volts) amplitudes on a silicon transistor gate. In this situation, the gate insulating layer 206 may be too thin to withstand damage from a 20 volt signal. For example, the gate insulator 206 can be about 800 angstroms thick, which may not be thick enough to reliably handle a 20 volt drive voltage. To ensure that the gate insulating layer 206 is not overly stressed, the gate structure 218 can be converted to a floating (electrically insulating) metal structure, and an additional metal layer (i.e., part of the same metal layer that is patterned to form the gate 228’ of the oxide transistor 240) can be used when forming the silicon transistor gate 218’. The floating gate 218 can be maintained to function as a mask for the low density drain (LDD) implant within the source and drain contact portions of the polysilicon layer 204 even when the floating gate 218 is not driven by a control signal during the operation of the silicon transistor 216.

[0042] In a hybrid silicon / oxide liquid crystal display, display drive circuit mechanisms such as the gate drive circuit mechanism 18 and the demultiplexer circuit mechanism 20 need not be formed from silicon transistors. Optionally, some of these display drive circuit mechanisms can be formed from oxide transistors. For example, a low drive current CMOS type circuit within the peripheral circuit mechanism of the display 14, such as the exemplary CMOS inverter 300 of FIG. 9, can include oxide transistors. Since forming a PMOS oxide transistor may be difficult, a circuit such as the inverter 300 can be formed using (as an example) NMOS oxide transistors and PMOS silicon transistors as needed.

[0043] Hybrid oxide-silicon thin film transistor structures, such as the exemplary thin film transistor structure 302 of FIG. 10, can be used in forming CMOS type circuit mechanisms within display driving circuit mechanisms such as the gate driving circuit mechanism 18 and the demultiplexer circuit mechanism 20. As shown in FIG. 10, the structure 302 can have a polysilicon layer 308 formed on a substrate 24. A P-channel active region 310 can be formed under a gate 312. A gate insulating layer 306 (e.g., silicon oxide) can separate the gate 312 from a silicon channel region 310 within the silicon layer 308. A dielectric layer 302 (e.g., a sublayer of silicon oxide and silicon nitride) can cover the gate 312. The dielectric layer 306 can separate the gate 312 from an overlapping oxide layer 312. The oxide layer 312 can be a semiconductor oxide such as an IGZO material. The gate 312 can be formed from a first patterned metal layer. A second patterned metal layer can be used in forming an output terminal 322, a source terminal 316, and a drain terminal 318. An inactivation layer 320 can cover the terminals 316 and 312. The gate 312 can be formed from a material such as molybdenum, molybdenum tungsten, tungsten, or other metals. The metals for forming structures such as the metal structures 322, 316, and the metal structure 318 can be formed from metals such as aluminum, molybdenum, etc.

[0044] In the layout configuration of FIG. 10, the gate 314 functions as a common (shared) gate for two transistors. Specifically, the gate 314 (e.g., referring to the terminal Vin of FIG. 9) functions as both a gate for a PMOS silicon transistor (transistor TP of FIG. 9) formed from the silicon layer 308 and a gate for an NMOS oxide transistor (transistor TN of FIG. 9) formed from the oxide layer 312. The oxide layer 312 is disposed above the gate 314, and the silicon layer 310 is disposed below the gate 314. The shared gate layout configuration of FIG. 10 enables a CMOS inverter of the type shown in FIG. 9 to be implemented compactly.

[0045] FIG. 11 shows an exemplary gate drive circuit mechanism 18 that can be used on a liquid crystal display. The circuit mechanism 18 uses signals having a relatively small voltage amplitude (e.g., an amplitude of 15 volts or 16 volts) with respect to silicon transistors, while generating a gate signal G having a larger voltage amplitude (e.g., an amplitude of 20 volts or more), thereby ensuring good operation of the oxide thin film transistors within the display pixels 22 driven by those gate signals.

[0046] As shown in FIG. 11, the circuit mechanism 18 can have a shift register formed from SR latches 400 or other register circuits connected in series. Each row of the circuit mechanism in FIG. 11 is associated with a separate row of display pixels 22 within the liquid crystal display, and provides a corresponding gate signal G to that row of display pixels. During operation, a trigger signal TRIGGER can be applied to the latch within the first row of the shift register within the circuit mechanism 18 while a clock signal LOAD CLOCK is applied to the shift register. This trigger signal causes a cascade signal that propagates and drops through the shift register. In response, each latch 400 asserts its output OUT in turn. Each row of the gate drive circuit mechanism 18 has a corresponding level shifter 404 and buffer 404 that receive the output signal OUT.

[0047] The output signal OUT ranges from a high voltage of 15V (or other suitable voltage) to 0 volts (or other suitable voltage). The 15V amplitude associated with this type of configuration is acceptable by the silicon thin film transistors within the latch 400. On the other hand, a larger voltage amplitude such as 20V may overly stress the silicon thin film transistors. The level shifter 402 shifts the 15V to 0V signal OUT from the latch 400 so that the output on path 406 from the level shifter 402 ranges from 5V to -11V (i.e., a 16V amplitude acceptable by the silicon transistors within the level shifter 402). The buffer 404 receives the 15V to 0V signal OUT from the latch 400 as the input signal IN_H and receives a 5V to -11V signal as the input signal IN_L. The buffer 404 preferably includes silicon thin film transistors. The design of this buffer 404 enables the buffer 404 to generate an output signal (gate line signal G) having a large voltage amplitude (e.g., 15V to -11V), which is of a type suitable for controlling oxide transistors within the array of display pixels 22 on the liquid crystal display.

[0048] FIG. 12 is a circuit diagram of an exemplary circuit of a type that can be used to implement the level shifter 402. The signal from the output OUT of the latch 400 can be received at the input 410 of the level shifter 402, and the corresponding level-shifted output signal (signal IN_L) for the buffer 404 can be provided at the output 412 of the level shifter 402. Other level shifter designs can be used for the level shifter 402 as needed. The configuration of FIG. 12 is merely exemplary. Silicon thin film transistors can be used when forming the level shifter 402.

[0049] The circuit mechanism 404 of FIG. 13 is an example of a design that can be used when implementing the buffer 404 of FIG. 11. In this design, the signal IN_H and the signal IN_L are the same rectangular wave pulses with different corresponding voltage amplitudes. The signal IN_H ranges from 15 to 0 volts. The signal IN_L ranges from 5 to -11 volts. The corresponding output signal (gate line signal) G in this embodiment is a rectangular wave pulse ranging from 15 volts to -11 volts, and thus has an amplitude exceeding 20 volts.

[0050] The ground voltage GND is applied to the gates of the transistors T2 and T3. This ensures that even when the output amplitude of the circuit 414 exceeds 20 volts, the maximum voltage experienced by the transistors of the circuit 414 is limited to less than about 16 volts. The ground voltage GND on the gates of the transistors T2 and T3 always turns off these transistors and protects the transistors T1 and T4 when an excessive source terminal voltage amplitude is detected. As an example, consider the transistors T1 and T2. The transistor T2 can be characterized by a threshold voltage Vth. When the source S of the transistor T1 begins to fall below the voltage GND - Vth, the transistor T2 turns off and insulates the transistor T1. The transistors T3 and T4 operate in the same manner. By using this configuration, none of the transistors in the buffer 414 are exposed to excessive voltage amplitudes, and it becomes possible to form the transistors T1, T2, T3, and T4 from thin-film silicon transistors.

[0051] If necessary, other circuit configurations can be used to enable the gate drive circuit mechanism 18 to operate in an environment where the gate line signal G has a large voltage amplitude to correspond to the oxide transistors in the display pixel 22. As an example, in addition to using a thin-film silicon transistor structure, a thin-film oxide transistor structure can be used to implement a subset of the level shifter transistors and a subset of the output buffer transistors.

[0052] FIG. 14 is a cross-sectional view of a further thin film transistor circuit mechanism of a type that can be used within a liquid crystal display. As shown in FIG. 14, the thin film transistor structure 242 can include a silicon thin film transistor structure 216 (for example, for forming portions of peripheral circuits such as the display drive circuit mechanism 18 and the demultiplexer circuit mechanism 20), and an oxide thin film transistor structure 240 (for example, for forming the display pixels 22 within a liquid crystal display having a layout of the type shown by the display 14 of FIG. 1).

[0053] Structures 216 and 240 can be formed on the buffer layer 202 on the substrate 24. A polysilicon layer 204 can be deposited on the buffer 202. A gate insulating layer 206 can be formed on the polysilicon layer 204. By patterning a common layer of metal, metal structures 218, 220, and metal structure 228 can be formed. Structure 218 can serve as a gate for a silicon transistor including source-drain contacts 212 and 214 and a channel formed from polysilicon 204. Metal structure 228 can serve as a gate for an oxide transistor formed from a semiconductor oxide layer 224 (for example, IGZO) and source-drain terminals 222 and 226. Metal structure 228 can also serve as a light shield useful for preventing the backlight within the display 14 from reaching the oxide layer 224, so that there is no need to incorporate a separate light shielding structure within structure 240. Interlayer dielectrics such as silicon nitride layer 208 and silicon nitride layer 210 can cover the gate 218 within structure 216 and can serve as a gate insulator for the gate 228 within the oxide transistor of structure 240.

[0054] The metal structures 218, 220, and the metal structure 228, as well as routing lines such as the interconnecting line 502, can be formed from a first metal layer (which may also be referred to as the M1 layer). The metal 222 and the metal 226 that form source-drain contacts for the oxide transistors of the structure 240, as well as routing lines such as the interconnecting line 500, can be formed from a second metal layer (which may also be referred to as the SD1 layer). The metal structures 212, 214, and routing lines such as the interconnecting line 506 can be formed from a third metal layer (which may also be referred to as the SD2 layer). The second metal layer can be separated from the third metal layer by the dielectric layer 232B. The third metal layer can be separated from metal structures such as the metal layer 234 by the dielectric layer 232A.

[0055] The metal 230 is coupled to the source-drain 226 of the display pixel thin-film oxide transistor formed from the oxide layer 224 by contacting the metal layer 504. The metal 230 can be supported by the organic layer 232B. On the surface of the organic layer 232B, the metal 230 can form an electrode having a plurality of finger portions. The electrode 230 can be insulated from the common electrode (Vcom) 234 by the dielectric layer 236. During operation, an electric field is generated between the electrode 230 and the electrode 234. These electric fields pass through the liquid crystal material within the display. Optionally, the display 14 can incorporate a capacitive touch sensor formed from portions of the Vcom electrode 234. In this type of configuration, an optional metal line such as the line 238 can be used to help reduce the resistance of the material (e.g., a slightly resistive conductive material such as indium tin oxide) used to form the electrode 234.

[0056] Capacitance coupling between routing lines within the display 14 can result in switching losses. As an example, the source-drain structure 222 can be coupled to a data line within the display 14. The voltage on this line switches with respect to Vcom (electrode 234), which can result in power losses. The presence of the dielectric layer 232A and the dielectric layer 232B can help reduce the capacitance coupling between this data line and the Vcom electrode, thereby reducing power losses. The presence of these dielectric layers can also reduce capacitance coupling between the routing lines within the display 14 (e.g., capacitance coupling between the routing lines and other structures such as the first metal layer and the second metal layer, the first metal layer and the third metal layer, etc.). The layers 232A and 232B can be formed from a low dielectric constant organic dielectric or other dielectric materials. As an example, the layers 232A and 232B can be an acrylic polymer, other polymers, a type of dielectric sometimes referred to as spin-on glass (e.g., a spin-on glass polymer deposited via a slit coating tool), a siloxane-based material, etc.

[0057] FIG. 15 is a cross-sectional view of an exemplary thin-film transistor circuit mechanism related to a liquid crystal display including a top-gate semiconductor oxide transistor. As shown in FIG. 15, the thin-film transistor structure 242 may include a silicon thin-film transistor structure 216 and a semiconductor oxide thin-film transistor structure 240. The silicon thin-film transistor structure 216 can be used in peripheral circuits such as the display driving circuit mechanism 18 and the demultiplexer circuit mechanism 20, and / or can be used when forming a circuit related to the display pixel 22 in the liquid crystal display. The semiconductor oxide thin-film transistor structure 240 can be used in peripheral circuits such as the display driving circuit mechanism 18 and the demultiplexer circuit mechanism 20, and / or can be used when forming a circuit related to the display pixel 22 in the liquid crystal display. Transistors such as the silicon (polysilicon) transistor 216 can be n-channel devices or p-channel devices. Transistors such as the semiconductor oxide transistor 240 can be n-channel devices or p-channel devices.

[0058] The structure 216 and the structure 240 can be formed on the buffer layer 202 on the substrate 24. The buffer layer 202 can be formed of a dielectric such as an inorganic dielectric. The buffer layer 202 can help prevent ions in the substrate 24 from moving into the structure 216 and the structure 240.

[0059] The polysilicon layer 204 can be deposited on the buffer 202. The gate insulating layer 206 can be formed on the polysilicon layer 204. The gate insulating layer 206 can be formed from a dielectric such as silicon oxide (e.g., a 100 nm silicon oxide layer). By patterning a common layer of metal, the metal structures 218, 220, and the metal structure 228 can be formed. The structure 218 can function as a gate for a silicon transistor including the source-drain contacts 212 and 214 and a channel formed from the polysilicon 204. The metal structure 228 can function as a gate for a top-gate oxide transistor (i.e., a semiconductor oxide transistor) formed from the semiconductor oxide layer 224 (e.g., IGZO) and the source-drain terminals 222 and 226. The metal structures 218, 220, and the metal structure 228 can be covered by one or more interlayer dielectric (ILD) layers. For example, the metal structures 218, 220, and the metal structure 228 can be covered by a first dielectric layer such as the layer 208 and a second dielectric layer such as the layer 210. (By way of example) the layer 208 can be a silicon nitride layer and the layer 210 can be a silicon oxide layer. Since there is no lateral overlap between the gate 228 and the source-drain electrodes 222 and 226, the parasitic capacitance between the gate 228 and the source-drain structures 222 and 226 can be minimized. Furthermore, the layers 208 and 210 of the oxide transistor in FIG. 15 can be made thicker than the layers 208 and 210 in the bottom-gate oxide transistor of FIG. 14, thereby further reducing the parasitic capacitance.

[0060] The metal structures 218, 220, and 228 can be formed from a first metal layer (which may also be referred to as the M1 layer). The metals 222 and 226 that form source-drain contacts for the oxide transistors of the structure 240, and the metals 212 and 214 that form source-drain contacts for the silicon transistors of the structure 216 can be formed from a second metal layer (which may also be referred to as the SD1 layer or the M2 layer). Metal structures such as the metal line 238 can be formed from a third metal layer (which may also be referred to as the M3 layer). The second metal layer can be separated from the third metal layer by a dielectric 232 (e.g., an organic dielectric layer such as a polymer layer).

[0061] The metal 230 contacts the source-drain 226 of a display pixel thin-film oxide transistor formed from the oxide layer 224. The metal 230 can be supported by an organic layer 232. On the surface of the organic layer 232, the metal 230 can form an electrode (e.g., a pixel electrode for a display pixel within a display) having a plurality of finger portions. The electrode 230 can be insulated from the common electrode (Vcom) 234 by a dielectric layer 236. During operation, an electric field is generated between the electrode 230 and the electrode 234. These electric fields pass through a liquid crystal material within the display that is formed on top of the structure of FIG. 15. Optionally, the display 14 can incorporate a capacitive touch sensor formed from portions of the Vcom electrode 234. In this type of configuration, an optional metal line such as the line 238 can be used to help reduce the resistance of the material (e.g., a somewhat resistive conductive material such as indium tin oxide) used to form the electrode 234.

[0062] As shown in FIG. 16, an optional light-shielding structure such as a light-shielding body 520 can be formed under the semiconductor oxide transistor 240 or at other locations within the display. The light-shielding body 520 can be formed from an opaque material such as a metal, a metal oxide, a dark polymer, or other light-shielding materials. The presence of the light-shielding body 520 can help prevent stray light from interfering with the operation of the semiconductor oxide transistor structure 240 or other overlapping structures.

[0063] In the embodiment of FIG. 17, the dielectric layer 232 of FIG. 15 is divided into two dielectric layers 232A and dielectric layer 232B. Layer 232A can be overlapped with the source-drain electrodes of transistors 216 and 240. Layer 232B can be inserted between the source-drain electrodes and other metal structures formed from the source-drain metal layer, and layers 208 and 210. As described in connection with FIG. 14, this type of two-layer approach can reduce the capacitive coupling between the metal structures of devices 216 and 240. A side cross-sectional view of an exemplary thin-film transistor circuit mechanism including a top-gate semiconductor oxide transistor within an organic light-emitting diode display is shown in FIG. 18. As shown in FIG. 18, the circuit mechanism 72 can include display pixel structures such as a light-emitting diode cathode terminal 42 and a light-emitting diode anode terminal 44. An organic light-emitting diode emissive material 47 can be inserted between the cathode 42 and the anode 44. The pixel defining layer 46 can be a dielectric layer 46 that helps define the layout of the display pixel. Layer 46 can be formed from a polymer such as a black polymer so as to help block stray light.

[0064] A planarization layer 50 can be formed on top of the thin film transistor structure 52. The thin film transistor structure 52 can be formed on a buffer layer 54 on the substrate 24. The substrate 24 can be formed from metal, glass, polymer, other materials, or combinations of these materials. The buffer layer 54 can be formed from an inorganic dielectric layer that helps prevent ions in the substrate 24 from interfering with the operation of the structure 52. An optional functional layer 522 can be interposed between the buffer layer 54 and the substrate 24. The functional layer 522 can be a layer used when forming components such as a stress relaxation layer, a light-shielding layer, a capacitor (e.g., a capacitor electrode related to a pixel circuit and / or a peripheral circuit).

[0065] The thin film transistor structure 52 can include a silicon transistor 58. The transistor 58 can be an LTPS transistor formed using a top gate design and can function as a switching transistor within an organic light emitting diode display pixel (e.g., refer to the transistor 30 in pixel 22-1 of FIG. 2). The transistor 58 can also be used within a peripheral circuit (e.g., a drive circuit mechanism 18 and a demultiplexer circuit mechanism 20).

[0066] The transistor 58 can have a polysilicon channel 62 covered by a gate insulating layer 64 (e.g., a layer of silicon oxide having a thickness of 100 nm or other suitable thickness). The gate 66 can be formed from a patterned metal (e.g., as an example, molybdenum). The gate 66 can be covered by a layer of interlayer dielectric (e.g., a silicon nitride layer 68 and a silicon oxide layer 70). Source-drain contacts 74 and 76 can contact opposite side portions of the polysilicon layer 62 to form the silicon thin film transistor 58.

[0067] The dielectric layer 526 can cover the source-drain structures 74 and 76. An optional metal layer 524 can be formed on layer 526 and, if necessary, can be contacted to the underlying metal structure through a via (e.g., see via 528). The structure 66 can be formed within the first (“M1”) metal layer. The source-drain electrodes 74 and 76 can be formed within the second metal layer. The metal layer 524 can be formed as part of the third (“M3”) metal layer. Layer 524 can be overlapped with portions of the transistor 58 and / or the transistor 60 and can be used to form a capacitor or a signal interconnecting line (i.e., routing). A radiation material layer 47 can be overlapped with layer 524, and layer 524 can form a light-shielding structure that prevents, for example, the stray light from the radiation material 47 from reaching the underlying transistor structure.

[0068] Thin film transistor structures, such as the semiconductor oxide thin film transistor structure 60 and the silicon thin film transistor structure 58, can be used when forming a part of the pixel circuit in the organic light emitting diode display and / or can be used when forming a part of the peripheral circuit mechanisms 18 and 20. The thin film transistor 60 in FIG. 18 can be a top gate semiconductor oxide transistor. The gate insulating layer 64, which functions as a gate insulator for the silicon transistor 58, also functions as a gate insulator for the oxide transistor 60.

[0069] The metal gate 532 forms the gate of the oxide transistor 60. The channel semiconductor of this oxide transistor can be formed from the semiconductor oxide layer 128 (e.g., IGZO). The source-drain terminals 534 and 536 can be formed of a metal that contacts the opposing ends of the semiconductor oxide layer 128. The metal structures 530 and 538 can be used for routing and can be formed from the same metal layer that is patterned to form the gates 66 and 532. The source-drain structures 534 and 536 can be formed from the same metal layer that is used when forming the source-drain structures 74 and 76.

[0070] According to one embodiment, there is provided a liquid crystal display including a substrate, an array of display pixels on the substrate, and a display driving circuit mechanism formed from thin film transistors on the substrate, the display driving circuit mechanism including silicon thin film transistors, the array of display pixels including semiconductor oxide thin film transistors, and a layer of gate metal patterned to form a common gate that functions as a gate for the silicon thin film transistors and as a gate for the semiconductor oxide thin film transistors.

[0071] According to another embodiment, the semiconductor oxide thin film transistor has a semiconductor oxide layer, and the common gate is present below the semiconductor oxide layer.

[0072] According to another embodiment, a layer of polysilicon on the substrate forms the silicon channel for the silicon thin film transistors, and the common gate is present above the layer of polysilicon.

[0073] According to another embodiment, the liquid crystal display includes a layer of silicon nitride and a layer of silicon oxide inserted between the gate of the semiconductor oxide thin film transistor and the semiconductor oxide layer.

[0074] According to one embodiment, a liquid crystal display is provided that includes a substrate, an array of display pixels on the substrate, and a display driving circuit mechanism formed from thin film transistors on the substrate. The display driving circuit mechanism includes silicon thin film transistors, and the array of display pixels includes semiconductor oxide thin film transistors. The liquid crystal display further includes a layer of polysilicon on the substrate that forms a silicon channel for the silicon thin film transistors, a first gate metal layer that forms a gate for the silicon thin film transistors, and a second gate metal layer that is different from the first gate metal layer and forms a gate for the semiconductor oxide thin film transistors.

[0075] According to one embodiment, a liquid crystal display is provided that includes a substrate, an array of display pixels on the substrate, and a display driving circuit mechanism formed from thin film transistors on the substrate. The display driving circuit mechanism includes silicon thin film transistors, and the array of display pixels includes semiconductor oxide thin film transistors. The liquid crystal display further includes a layer of polysilicon on the substrate that forms a silicon channel for the silicon thin film transistors, a first gate metal layer that forms a floating gate for the silicon thin film transistors, and a second gate metal layer that overlaps the floating gate and is separated from the floating gate by a dielectric layer and forms a gate for the silicon thin film transistors. A portion of the second gate metal layer forms a gate for the semiconductor oxide thin film transistors.

[0076] According to one embodiment, a liquid crystal display is provided that includes a substrate, an array of display pixel circuits on the substrate, and a display driving circuit mechanism that drives signals within the array of display pixel circuits. The display driving circuit mechanism is formed from thin film transistors on the substrate, includes silicon thin film transistors, and includes semiconductor oxide thin film transistors.

[0077] According to another embodiment, this liquid crystal display includes a metal layer that forms a common gate for both the silicon thin film transistor and the semiconductor oxide thin film transistor.

[0078] According to another embodiment, the semiconductor oxide thin film transistor has a semiconductor oxide layer above its common gate.

[0079] According to another embodiment, the silicon thin film transistor has a polysilicon layer below its common gate.

[0080] According to another embodiment, the silicon thin film transistor and the semiconductor oxide thin film transistor form an inverter.

[0081] According to one embodiment, a liquid crystal display is provided, which includes a substrate, an array of display pixels on the substrate, and a display driving circuit mechanism formed from thin film transistors on the substrate. This display driving circuit mechanism includes a silicon thin film transistor, the array of display pixels includes a semiconductor oxide thin film transistor, a first patterned metal layer including a gate for the silicon thin film transistor and a gate for the semiconductor oxide thin film transistor, a second patterned metal layer including a source-drain contact for the semiconductor oxide thin film transistor, a third patterned metal layer including a structure coupled to at least one of the source-drain contacts, and a dielectric layer between the second patterned metal layer and the third patterned metal layer.

[0082] According to another embodiment, this liquid crystal display includes a fourth patterned metal layer including a display pixel electrode.

[0083] According to another embodiment, this liquid crystal display includes an additional dielectric layer between the third patterned metal layer and the fourth patterned metal layer.

[0084] According to another embodiment, the dielectric layer between the second patterned metal layer and the third patterned metal layer is an organic dielectric layer.

[0085] According to another embodiment, the dielectric layer between the third patterned metal layer and the fourth patterned metal layer is an organic dielectric layer.

[0086] According to another embodiment, this liquid crystal display includes an inorganic dielectric layer between the first patterned metal layer and the second patterned metal layer.

[0087] According to another embodiment, the first patterned metal layer includes routing lines.

[0088] According to another embodiment, the second patterned metal layer includes routing lines.

[0089] According to another embodiment, the third patterned metal layer includes routing lines.

[0090] According to one embodiment, a display pixel circuit within a display pixel in an organic light-emitting diode display is provided, including a light-emitting diode, a semiconductor oxide thin-film transistor coupled to the light-emitting diode, and a silicon thin-film transistor.

[0091] According to another embodiment, the semiconductor oxide thin-film transistor includes a driving transistor having a gate, and the display pixel includes a capacitor coupled between the gate and the light-emitting diode.

[0092] According to another embodiment, the silicon thin-film transistor has a polysilicon channel and is coupled to the capacitor.

[0093] According to another embodiment, the display pixel circuit includes a metal layer, the capacitor has a first electrode and a second electrode, the first electrode and the gate are formed from a part of the metal layer, and the silicon thin film transistor has a gate formed from another part of the metal layer.

[0094] According to another embodiment, the silicon thin film transistor has a channel formed from a part of a polysilicon layer, the second electrode is formed from a further part of the polysilicon layer, the oxide transistor has a channel formed from a semiconductor oxide layer, and the channel formed from the semiconductor oxide layer overlaps a further part of the polysilicon layer.

[0095] According to one embodiment, there is provided a hybrid thin film transistor structure including a silicon layer for a silicon thin film transistor, a semiconductor oxide layer for an oxide transistor, and a metal layer patterned to form a first gate for the silicon thin film transistor and patterned to form a second gate for the oxide transistor.

[0096] According to another embodiment, this hybrid thin film transistor structure includes a capacitor having an electrode layer formed from a part of the metal layer.

[0097] According to another embodiment, this hybrid thin film transistor structure includes a further metal layer having a portion for forming a source-drain contact for the silicon thin film transistor, a portion for forming a source-drain contact for the oxide transistor, and a portion for forming an electrode layer in the capacitor.

[0098] According to another embodiment, this capacitor has a further electrode layer formed from a part of the metal layer patterned to form the first gate.

[0099] According to another embodiment, the silicon layer includes a polysilicon layer, and a portion of this polysilicon layer forms an electrode layer of a capacitor related to that capacitor, where the portion is short-circuited to portions of a further metal layer that forms the electrode layer within the capacitor.

[0100] According to one embodiment, an organic light emitting diode display is provided that includes a light emitting diode and a thin film transistor coupled to the light emitting diode, where the thin film transistor includes at least one semiconductor oxide channel region and at least one silicon channel region.

[0101] According to another embodiment, the thin film transistor includes a semiconductor oxide thin film transistor formed from a semiconductor oxide channel region and coupled to the light emitting diode.

[0102] According to another embodiment, the thin film transistor includes a silicon thin film transistor formed from a silicon channel region.

[0103] According to another embodiment, the thin film transistor includes a semiconductor oxide thin film transistor formed from a semiconductor oxide channel region and coupled to the light emitting diode, and a silicon thin film transistor formed from a silicon channel region.

[0104] According to another embodiment, the semiconductor oxide thin film transistor includes a driving transistor having a gate.

[0105] According to another embodiment, the organic light emitting diode display includes a capacitor coupled between its gate and the light emitting diode.

[0106] According to another embodiment, the silicon channel region includes a polysilicon channel region coupled to the capacitor.

[0107] According to another embodiment, this organic light emitting diode display includes a metal layer, the capacitor has a first electrode and a second electrode, the first electrode and the gate are formed from a part of the metal layer, and the silicon thin film transistor has a gate formed from another part of the metal layer.

[0108] According to another embodiment, the thin film transistor includes a silicon thin film transistor and a semiconductor oxide thin film transistor, the silicon channel region is formed from a part of the polysilicon layer to form a part of the silicon thin film transistor, and the second electrode is formed from a further part of the polysilicon layer.

[0109] According to another embodiment, the semiconductor oxide channel region forms a part of the semiconductor oxide thin film transistor, and the semiconductor oxide channel region overlaps with a further part of the polysilicon layer.

[0110] According to one embodiment, a liquid crystal display is provided that includes a substrate, an array of display pixel circuits on the substrate, and a display drive circuit mechanism that drives a gate line signal within the array of display pixel circuits, and this display drive circuit mechanism includes a level shifter circuit mechanism.

[0111] According to another embodiment, the array of display pixel circuits includes a semiconductor oxide thin film transistor circuit mechanism.

[0112] According to another embodiment, the display drive circuit mechanism includes a silicon thin film transistor formed on the substrate.

[0113] According to another embodiment, the display drive circuit mechanism includes a gate drive circuit mechanism, and the level shifter circuit mechanism forms a part of this gate drive circuit mechanism.

[0114] According to another embodiment, the gate drive circuit mechanism further includes a shift register.

[0115] According to another embodiment, the level shifter circuit mechanism is coupled to the shift register.

[0116] According to another embodiment, the gate driving circuit mechanism includes a buffer circuit mechanism.

[0117] According to another embodiment, the buffer circuit mechanism is coupled to the level shifter circuit mechanism and generates a gate line signal.

[0118] According to another embodiment, the shift register supplies a signal having a first voltage amplitude, the level shifter adjusts the first voltage amplitude to a second voltage amplitude, and the buffer circuit mechanism receives a signal from the shift register having the first voltage amplitude and receives a signal from the level shifter having the second voltage amplitude.

[0119] According to another embodiment, the shift register supplies a signal having a first voltage amplitude, and the level shifter adjusts the first voltage amplitude to a second voltage amplitude.

[0120] According to another embodiment, the gate driving circuit mechanism includes a buffer circuit mechanism that receives a signal from the shift register having a first voltage amplitude.

[0121] According to one embodiment, a liquid crystal display is provided that includes a substrate, an array of display pixel circuits on the substrate, wherein the display pixel circuits include semiconductor oxide thin film transistors, and a display driving circuit mechanism formed from silicon thin film transistors on the substrate, the display driving circuit mechanism including a gate driving circuit mechanism, the gate driving circuit mechanism including a level shifter circuit mechanism that receives a signal having a first voltage amplitude and adjusts the first voltage amplitude to a second voltage amplitude.

[0122] According to another embodiment, the gate driving circuit mechanism drives a gate line signal within the array of display pixel circuits.

[0123] According to another embodiment, the semiconductor oxide thin film transistors each have a semiconductor oxide channel region, and the silicon thin film transistors each have a polysilicon channel region.

[0124] According to another embodiment, the gate driving circuit mechanism further includes a shift register, and the level shifter circuit mechanism is coupled to this shift register.

[0125] According to another embodiment, the gate driving circuit mechanism includes a buffer circuit mechanism that receives a signal from a shift register having a first voltage amplitude and receives a signal from a level shifter having a second voltage amplitude.

[0126] According to one embodiment, there is provided a liquid crystal display including an array of semiconductor oxide thin film transistor display pixel circuits on a substrate and a level shifter that receives a signal having a first voltage amplitude and adjusts the first voltage amplitude to a second voltage amplitude, and a silicon thin film transistor gate driving circuit mechanism on the substrate, and this silicon thin film transistor gate driving circuit mechanism controls the array of semiconductor oxide thin film transistor display pixel circuits.

[0127] According to another embodiment, the silicon thin film transistor circuit mechanism includes silicon thin film transistors each having a polysilicon channel region, and the silicon thin film transistor gate driving circuit mechanism includes a shift register.

[0128] According to another embodiment, the silicon thin film transistor gate driving circuit mechanism includes a buffer circuit mechanism.

[0129] According to another embodiment, this liquid crystal display includes a shift register circuit mechanism coupled to a level shifter, and the buffer circuit mechanism receives a signal from the level shifter and a signal from the shift register and provides a gate line signal to the array of semiconductor oxide thin film transistor display pixel circuits.

[0130] According to one embodiment, a liquid crystal display is provided that includes a substrate, an array of display pixel circuits on the substrate, and a display driving circuit mechanism on the substrate, wherein the display driving circuit mechanism and the display pixels include thin film transistors, and the thin film transistors include at least one top-gate semiconductor oxide transistor and at least one silicon transistor.

[0131] According to another embodiment, the liquid crystal display includes a layer of gate metal that is patterned to form a first gate for the silicon transistor and a second gate for the top-gate semiconductor oxide transistor.

[0132] According to another embodiment, the liquid crystal display includes a layer of polysilicon on the substrate that forms a silicon channel for the silicon transistor, and the first gate is located above the layer of polysilicon.

[0133] According to another embodiment, the liquid crystal display includes a semiconductor oxide layer on the substrate that forms a semiconductor oxide channel for the top-gate semiconductor oxide transistor, and the second gate is located above the semiconductor oxide layer.

[0134] According to another embodiment, the liquid crystal display includes a gate insulating layer.

[0135] According to another embodiment, a first portion of the gate insulating layer is inserted between the first gate and the polysilicon layer.

[0136] According to another embodiment, a second portion of the gate insulating layer is inserted between the second gate and the semiconductor oxide layer.

[0137] According to another embodiment, the liquid crystal display includes source-drain electrodes for the thin film transistors, and the source-drain electrodes are formed from a patterned layer of metal.

[0138] According to another embodiment, this liquid crystal display includes a metal layer on which source-drain electrodes are formed and a silicon oxide layer inserted between a first gate and a second gate.

[0139] According to another embodiment, this liquid crystal display includes a metal layer on which source-drain electrodes are formed and a silicon nitride layer inserted between a first gate and a second gate.

[0140] According to another embodiment, this liquid crystal display includes a display pixel electrode and an organic layer inserted between the display pixel electrode and the source-drain electrodes.

[0141] According to another embodiment, this liquid crystal display includes a display pixel electrode, a first organic layer inserted between the display pixel electrode and the source-drain electrodes, and a second organic layer inserted between the source-drain electrodes and the silicon oxide layer.

[0142] According to one embodiment, this liquid crystal display includes a light shield under the semiconductor oxide layer.

[0143] According to one embodiment, an organic light emitting diode display including a light emitting diode, a top gate semiconductor oxide thin film transistor coupled to the light emitting diode, and a silicon thin film transistor is provided.

[0144] According to one embodiment, this organic light emitting diode display includes a gate metal layer patterned to form a first gate for the silicon thin film transistor and a second gate for the top gate semiconductor oxide transistor.

[0145] According to another embodiment, this organic light-emitting diode display includes a polysilicon layer that forms a silicon channel for a silicon transistor, and a semiconductor oxide layer that forms a semiconductor oxide channel for a top-gate semiconductor oxide transistor. The first gate is present above the polysilicon layer, and the second gate is present above the semiconductor oxide layer.

[0146] According to another embodiment, the light-emitting diode includes a cathode, an anode, and an organic emission layer between the anode and the cathode. This organic light-emitting diode display includes a gate insulator having a first portion inserted between the first gate and the polysilicon layer and a second portion inserted between the second gate and the semiconductor oxide layer, and a source-drain electrode in a semiconductor oxide thin-film transistor coupled to the anode.

[0147] According to one embodiment, there is provided an organic light-emitting diode display including a light-emitting diode, a silicon thin-film transistor, a semiconductor oxide thin-film transistor having a source-drain electrode and a gate, and a semiconductor oxide layer coupled to the source-drain electrode, and a light-shielding layer overlapping at least a part of the silicon thin-film transistor and at least a part of the semiconductor oxide thin-film transistor.

[0148] According to another embodiment, the light-emitting diode includes a cathode, an anode, and an organic emission layer between the anode and the cathode. The organic emission layer overlaps the light-shielding layer. This organic light-emitting diode display includes a gate insulating layer having a first portion that functions as a gate insulator for the silicon thin-film transistor and a second portion that functions as a gate insulator for the semiconductor oxide thin-film transistor.

[0149] According to another embodiment, this organic light-emitting diode display includes a source-drain electrode in a semiconductor oxide thin-film transistor coupled to the anode.

[0150] The above are merely examples, and various modifications can be made by those skilled in the art without departing from the scope and spirit of the described embodiments. The above embodiments can be implemented individually or in any combination.

Claims

1. A first power supply terminal; A second power supply terminal; a light emitting diode connected between the first power terminal and the second power terminal; a drive transistor connected between the first power supply terminal and the light emitting diode; a first switching transistor connected to the gate of the drive transistor, the first switching transistor being an oxide transistor; a capacitor connected to a first node located between the first switching transistor and the drive transistor; a second switching transistor connected between a signal line and the anode of said light emitting diode, said second switching transistor being a silicon transistor.

2. 10. The display pixel of claim 1, wherein the drive transistor is a silicon transistor.

3. 3. The display pixel of claim 2, wherein the drive transistor is a P-type metal oxide semiconductor silicon transistor.

4. 2. The display pixel of claim 1, wherein the second switching transistor is a P-type metal oxide semiconductor silicon transistor.

5. The display pixel of claim 1 , wherein the capacitor is configured to store a data signal from a data line.

6. 2. The display pixel of claim 1, wherein the first power supply terminal is a positive power supply terminal and the second power supply terminal is a ground power supply terminal.

7. 1. A display comprising an array of display pixels arranged in rows and columns, each display pixel comprising: A first power supply terminal; A second power supply terminal; a light emitting diode connected between the first power terminal and the second power terminal; a drive transistor connected between the first power supply terminal and the light emitting diode; an oxide switching transistor connected to the gate of the drive transistor; a capacitor connected to a first node located between the oxide switching transistor and the gate of the drive transistor; a second node interposed between said drive transistor and said light emitting diode; and an additional switching transistor connected between a signal line of a column of display pixels and a second node interposed between said drive transistor and said light emitting diode.

8. the oxide switching transistor having a channel formed of a layer of a semiconductor oxide; 8. The display of claim 7, wherein the additional switching transistor has a channel formed in a layer of silicon.

9. 8. A display as claimed in claim 7, wherein the additional switching transistor is a silicon switching transistor.

10. the first switching transistor having a channel formed of a layer of semiconductor oxide; 8. The display of claim 7, wherein the drive transistor has a channel formed in a layer of silicon.

11. 8. A display as claimed in claim 7, wherein the capacitor is arranged to store the signal on the gate of the drive transistor between frames.

12. 8. The display of claim 7, wherein said additional switching transistor is a P-type metal oxide semiconductor silicon transistor.

13. 8. A display as claimed in claim 7, wherein the first power supply terminal is a positive power supply terminal and the second power supply terminal is a ground power supply terminal.

14. A first power supply terminal; A second power supply terminal; a driving transistor and a light emitting diode connected in series between the first power supply terminal and the second power supply terminal; a first switching transistor connected to the gate of the drive transistor, the first switching transistor being an oxide transistor; A signal line; a second switching transistor connected between the signal line and a first node interposed between the drive transistor and the light emitting diode, the second switching transistor being a silicon transistor.

15. 15. The display pixel of claim 14, wherein the drive transistor is a silicon transistor.

16. The display pixel of claim 14 , wherein the signal line is used to implement a compensation scheme to adjust for variations in transistor performance between pixels.

17. 15. The display pixel of claim 14, further comprising a capacitor connected to a second node interposed between the first switching transistor and the gate of the drive transistor.

18. 15. The display pixel of claim 14, wherein the first power supply terminal is a positive power supply terminal and the second power supply terminal is a ground power supply terminal.

19. 15. The display pixel of claim 14, wherein the drive transistor is a P-type metal oxide semiconductor silicon transistor.

20. 15. The display pixel of claim 14, wherein the second switching transistor is a P-type metal oxide semiconductor silicon transistor.

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