Semiconductor device and display device

Abstract

To improve an operation speed of a circuit.SOLUTION: There are provided: a first transistor; a second transistor in which a first terminal is connected to a gate of the first transistor, and has a function for setting a value of a potential of the gate of the first transistor to a value where the first transistor is ON; a third transistor that sets a value of the potential of the gate of the second transistor to a value where the second transistor is ON, and has a function for setting the gate of the second transistor to be in a floating state; and a fourth transistor that has a function for setting a value of the potential of the gate of the second transistor to a value where the second transistor is OFF. By such a construction, a potential difference between the gate and a source of the second transistor can be maintained so as to be a value that is larger than a threshold value voltage of the second transistor, and can improve an operation speed.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device, a display module, and an electronic device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The technical field of one aspect of the invention disclosed in this specification etc. relates to an article, a method, or a manufacturing method. Or, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter). Or, one aspect of the present invention relates to a semiconductor device, a display device a light-emitting device, a power storage device, a storage device, a driving method thereof, or a manufacturing method thereof.

Background Art

[0003] Development of a circuit applicable to a driving circuit such as a storage device, an image sensor, or a display device is in progress. In particular, development of a circuit composed of transistors of the same polarity is actively under way. Techniques related to such a circuit are disclosed in Patent Document 1.

[0004] In Patent Document 1, the potential difference between the gate and the source of a transistor gradually decreases. Then when the potential difference between the gate and the source of the transistor becomes equal to the threshold voltage of the transistor the transistor turns off and the node inside the circuit becomes a floating state.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] In a conventional circuit, since the potential difference between the gate and the source of a transistor gradually decreases, the drain current of the transistor also gradually decreases. Therefore, the time required for the potential change at the node inside the circuit is long, and it is difficult to operate at high speed. Also, it is necessary to increase the W / L of the transistor, and it is difficult to reduce the layout area. Also, it is difficult to shorten the rise time or fall time of a signal.

[0007] One aspect of the present invention is to provide a novel semiconductor device. Or, one aspect of the present invention is to provide a configuration that operates at high speed or enables it. Or, one aspect of the present invention is to provide a configuration that reduces or enables reduction of the layout area. Or, one aspect of the present invention is to provide a configuration that reduces or enables reduction of the drive voltage. Or, one aspect of the present invention is to provide a configuration that shortens or enables shortening of the rise time or fall time of a signal.

[0008] Note that one aspect of the present invention does not necessarily need to solve all of the above problems, and it suffices if it can solve at least one problem. Also, the description of the above problems does not prevent the existence of other problems. These other problems will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other problems from the description in the specification, drawings, claims, etc.

Means for Solving the Problems

[0009] One aspect of the present invention is a semiconductor device having first to fourth transistors. One of the source or drain of the first transistor is electrically connected to the first wiring, and the other of the source or drain of the first transistor is electrically connected to the second wiring. One of the source or drain of the second transistor is electrically connected to the third wiring, and the other of the source or drain of the second transistor is electrically connected to the gate of the first transistor. One of the source or drain of the third transistor is electrically connected to the fourth wiring, and the other of the source or drain of the third transistor is electrically connected to the gate of the second transistor. One of the source or drain of the fourth transistor is electrically connected to the fifth wiring, and the other of the source or drain of the fourth transistor is electrically connected to the gate of the second transistor. One of the source or drain of the first transistor is electrically connected to the first wiring, and the other of the source or drain of the first transistor is electrically connected to the second wiring. One of the source or drain of the second transistor is electrically connected to the third wiring, and the other of the source or drain of the second transistor is electrically connected to the gate of the first transistor. One of the source or drain of the second transistor is electrically connected to the third wiring, and the other of the source or drain of the second transistor is electrically connected to the gate of the first transistor. One of the source or drain of the second transistor is electrically connected to the third wiring, and the other of the source or drain of the second transistor is electrically connected to the gate of the first transistor. One of the source or drain of the third transistor is electrically connected to the fourth wiring, and the other of the source or drain of the third transistor is electrically connected to the gate of the second transistor. One of the source or drain of the third transistor is electrically connected to the fourth wiring, and the other of the source or drain of the third transistor is electrically connected to the gate of the second transistor. One of the source or drain of the fourth transistor is electrically connected to the fifth wiring, and the other of the source or drain of the fourth transistor is electrically connected to the gate of the second transistor. One of the source or drain of the fourth transistor is electrically connected to the fifth wiring, and the other of the source or drain of the fourth transistor is electrically connected to the gate of the second transistor. One of the source or drain of the fourth transistor is electrically connected to the fifth wiring, and the other of the source or drain of the fourth transistor is electrically connected to the gate of the second transistor.

[0010] One aspect of the present invention is a semiconductor device having first to fourth transistors. One of the source or drain of the first transistor is electrically connected to the first wiring, and the other of the source or drain of the first transistor is electrically connected to the second wiring. One of the source or drain of the first transistor is electrically connected to the first wiring, and the other of the source or drain of the first transistor is electrically connected to the second wiring. One of the source or drain of the second transistor is electrically connected to the third wiring, and the other of the source or drain of the second transistor is electrically connected to the gate of the first transistor. One of the source or drain of the second transistor is electrically connected to the third wiring, and the other of the source or drain of the second transistor is electrically connected to the gate of the first transistor. One of the source or drain of the second transistor is electrically connected to the third wiring, and the other of the source or drain of the second transistor is electrically connected to the gate of the first transistor. One of the source or drain of the third transistor is electrically connected to the third wiring, and the other of the source or drain of the third transistor is electrically connected to the gate of the second transistor. One of the source or drain of the third transistor is electrically connected to the third wiring, and the other of the source or drain of the third transistor is electrically connected to the gate of the second transistor. One of the source or drain of the third transistor is electrically connected to the third wiring, and the other of the source or drain of the third transistor is electrically connected to the gate of the second transistor. Continuing, the other of the source or drain of the fourth transistor is electrically connected to the gate of the second transistor.

[0011] One aspect of the present invention is a semiconductor device having first to fourth transistors. One of the source or drain of the first transistor is electrically connected to the first wiring, and the other of the source or drain of the first transistor is electrically connected to the second wiring. One of the source or drain of the second transistor is electrically connected to the third wiring, and the other of the source or drain of the second transistor is electrically connected to the gate of the first transistor. One of the source or drain of the third transistor is electrically connected to the fourth wiring, and the other of the source or drain of the third transistor is electrically connected to the gate of the second transistor. One of the source or drain of the fourth transistor is electrically connected to the third wiring or the fourth wiring, and the other of the source or drain of the fourth transistor is electrically connected to the gate of the second transistor.

[0012] In addition, in one aspect of the present invention, the gate of the fourth transistor may be connected to the first wiring or the second wiring.

[0013] One aspect of the present invention is a display module having the semiconductor device and an FPC.

[0014] One aspect of the present invention is an electronic device having the display module, an antenna, an operation button, or a speaker.

Advantages of the Invention

[0015] One aspect of the present invention can provide a novel semiconductor device. Or, one aspect of the present invention​​​​​​​​​​​​ can provide a configuration that operates at high speed or enables it. Or, the present aspect of the invention can provide a configuration that reduces or enables reduction of the layout area. Or, an aspect of the present invention can provide a configuration that reduces or enables reduction of the drive voltage. Or, an aspect of the present invention can provide a configuration that reduces or enables reduction of the rise time or fall time of a signal.

[0016] Note that the description of these effects does not preclude the existence of other effects. Note that an aspect of the present invention does not necessarily have to have all of these effects. Note that other effects will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other effects from the description in the specification, drawings, claims, etc.

Brief Description of the Drawings

[0017]

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Embodiments for Carrying Out the Invention

[0018] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the description in the following embodiments, and it will be easily understood by those skilled in the art that the form and details thereof can be variously changed without departing from the spirit and scope of the present invention. Therefore the present invention should not be construed as being limited to the description of the following embodiments. Moreover, one aspect of the present invention includes, in addition to an imaging device, any

[0019] RF tag, display device, integrated circuit, etc. The device is included in its scope. In addition, display devices include liquid crystal display devices, light-emitting devices having light-emitting elements typified by organic light-emitting elements in each pixel, electronic paper, DMD (Digital Micromirror Device), PDP (Plasma Display Pa nel), FED (Field Emission Display), etc., and display devices having integrated circuits are included in its scope. When explaining the configuration of the invention with reference to the drawings, the same reference numerals may be commonly used among different drawings. In addition, in this specification, etc., in the figures or text described in a certain embodiment, it is possible to extract a part thereof to constitute an aspect of the invention. Therefore,

[0020] when a figure or text describing a certain part is described, the content obtained by extracting a part of the figure or text is also disclosed as an aspect of the invention and can be configured as an aspect of the invention. And it can be said that that aspect of the invention is clear. Therefore, for example, in the figures or text in which active elements (such as transistors), wirings, passive elements (such as capacitive elements), conductive layers,

[0021] insulating layers, semiconductor layers, components, devices, operation methods, manufacturing methods, etc. are described singly or plurally, it is possible to extract a part thereof to constitute an aspect of the invention. For example, from a circuit diagram configured with N (N is an integer) circuit elements (such as transistors and capacitive elements), it is possible to extract M (M is an integer and M < N) circuit elements (such as transistors and capacitive elements) to constitute an aspect of the invention. As another example, it is possible to extract a part thereof to constitute an aspect of the invention. For example, from a circuit diagram configured with N (N is an integer) circuit elements (such as transistors and capacitive elements), it is possible to extract M (M is an integer and M < N) circuit elements (such as transistors and capacitive elements) to constitute an aspect of the invention. As another example, when a figure or text describing a certain part is described, the content obtained by extracting a part of the figure or text is also disclosed as an aspect of the invention and can be configured as an aspect of the invention. And it can be said that that aspect of the invention is clear. Therefore, for example, in the figures or text in which active elements (such as transistors), wirings, passive elements (such as capacitive elements), conductive layers, insulating layers, semiconductor layers, components, devices, operation methods, manufacturing methods, etc. are described singly or plurally, it is possible to extract a part thereof to constitute an aspect of the invention. For example, from a circuit diagram configured with N (N is an integer) circuit elements (such as transistors and capacitive elements), it is possible to extract M (M is an integer and M < N) circuit elements (such as transistors and capacitive elements) to constitute an aspect of the invention. As another example, insulating layers, semiconductor layers, components, devices, operation methods, manufacturing methods, etc. are described singly or plurally, it is possible to extract a part thereof to constitute an aspect of the invention. For example, from a circuit diagram configured with N (N is an integer) circuit elements (such as transistors and capacitive elements), it is possible to extract M (M is an integer and M < N) circuit elements (such as transistors and capacitive elements) to constitute an aspect of the invention. As another example, when a figure or text describing a certain part is described, the content obtained by extracting a part of the figure or text is also disclosed as an aspect of the invention and can be configured as an aspect of the invention. And it can be said that that aspect of the invention is clear. Therefore, for example, in the figures or text in which active elements (such as transistors), wirings, passive elements (such as capacitive elements), conductive layers, insulating layers, semiconductor layers, components, devices, operation methods, manufacturing methods, etc. are described singly or plurally, it is possible to extract a part thereof to constitute an aspect of the invention. For example, from a circuit diagram configured with N (N is an integer) circuit elements (such as transistors and capacitive elements), it is possible to extract M (M is an integer and M < N) circuit elements (such as transistors and capacitive elements) to constitute an aspect of the invention. As another example, when a figure or text describing a certain part is described, the content obtained by extracting a part of the figure or text is also disclosed as an aspect of the invention and can be configured as an aspect of the invention. And it can be said that that aspect of the invention is clear. Therefore, for example, in the figures or text in which active elements (such as transistors), wirings, passive elements (such as capacitive elements), conductive layers, Then, from the sentence "A has B, C, D, E, or F", some of the elements can be arbitrarily extracted to form "A has B and E", "A has E and F" ,"A has C, E, and F", or "A has B, C, D, and E", etc. It is possible to constitute one aspect of the invention.

[0022] Also, in this specification, etc., in the figures or sentences described in a certain embodiment when at least one specific example is described, it is easily understood by those skilled in the art to derive the upper concept of that specific example. Therefore, in a certain embodiment when at least one specific example is described in the figures or sentences described, the upper concept of that specific example is also disclosed as one aspect of the invention and can constitute one aspect of the invention. And it can be said that one aspect of that invention is clear.

[0023] Also, in this specification, etc., at least the content described in the figures (even a part of the figures) is disclosed as one aspect of the invention and can constitute one aspect of the invention. Therefore, for a certain content, if it is described in the figures, even if it is not described using sentences, that content is disclosed as one aspect of the invention and can constitute one aspect of the invention. Similarly, for a figure obtained by extracting a part of the figure, it is also disclosed as one aspect of the invention and can constitute one aspect of the invention. And it can be said that one aspect of that invention is clear.

[0024] Also, for the content not defined in the sentences or drawings in the specification, excluding that content can constitute one aspect of the invention defined thereby. Or, for a certain value, if a numerical range indicated by an upper limit value and a lower limit value etc. is described, by arbitrarily narrowing that range , or by excluding one point within that range, one aspect of the invention excluding a part of that range can be defined . By these, for example, it can be defined that the prior art does not fall within the technical scope of one aspect of the present invention .

[0025] Also, in this specification etc., for all terminals of an active element (such as a transistor), a passive element (such as a capacitor element ), etc., even if the connection destination thereof is not specified, a person skilled in the art may be able to constitute one aspect of the invention. That is, even if the connection destination is not specified, it can be said that one aspect of the invention is clear. And, when the content where the connection destination is specified is described in this specification etc., it may be possible to determine that one aspect of the invention without specifying the connection destination is described in this specification etc . In particular, when there are a plurality of candidates for the connection destination of a terminal, it is not necessary to limit the connection destination of that terminal to a specific location. Therefore, for some terminals of an active element (such as a transistor ), a passive element (such as a capacitor element), etc., it may be possible to constitute one aspect of the invention by specifying the connection destination thereof . Also, in this specification etc., for a certain circuit, if at least the connection destination is specified, a person skilled in the art

[0026] may be able to specify the invention. Or, for a certain circuit, if at least the function is specified, a person skilled in the art may be able to specify the invention. That is, if the function is specified, it can be said that one aspect of the invention is clear. And, when the function is specified and described in this specification etc., it can be said that one aspect of the invention is clear. And, when the function is specified It may be possible to determine that one aspect of the invention is described in the present specification. Therefore, even if the function of a circuit is not specified, if the connection destination is specified, it can be considered as an embodiment of the invention. and can constitute one embodiment of the invention. For a certain circuit, even if the connection destination is not specified, if the function is specified, it can be considered as one aspect of the invention. What is disclosed can constitute an embodiment of the invention.

[0027] In addition, when it is explicitly stated in this specification that X and Y are connected, is when X and Y are electrically connected and when X and Y are functionally connected. and the case where X and Y are directly connected are considered to be disclosed in this specification and the like. Therefore, the present invention is not limited to a specific connection relationship, for example, a connection relationship shown in a drawing or a sentence. Any connections other than those shown in the drawings or text shall be deemed to be described in the drawings or text. do.

[0028] Here, X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.). , etc.).

[0029] An example of a direct connection between X and Y is a circuit that allows electrical connection between X and Y. The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, When a resistor (such as an electrode, display element, light-emitting element, or load) is not connected between X and Y, The elements that allow electrical connection between X and Y (e.g., switches, transistors, capacitors, etc.) elements, inductors, resistors, diodes, display elements, light-emitting elements, loads, etc.) , X and Y are connected.

[0030] An example of a case where X and Y are electrically connected is The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, One or more elements (such as an electrode, a display element, a light-emitting element, or a load) can be connected between X and Y. It is possible. The switch has a function that allows it to be turned on and off. A switch can be in a conductive state (on state) or a non-conductive state (off state) and can either pass current or not. The switch has the function of controlling whether or not current flows. When X and Y are electrically connected, This includes the case where Y is directly connected.

[0031] An example of a case where X and Y are functionally connected is a case where a functional connection between X and Y is possible. Circuits that perform the above functions (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits ( power supply circuits (voltage boost circuits, voltage drop circuits, etc.), level shifter circuits that change the potential level of signals, etc.) , voltage sources, current sources, switching circuits, amplifier circuits (which can increase the signal amplitude or current amount, etc.) circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation One or more external circuits (e.g., a memory circuit, a control circuit, etc.) can be connected between X and Y. For example, even if another circuit is inserted between X and Y, the signal output from X If X is transmitted to Y, then X and Y are considered to be functionally connected. When X and Y are functionally connected, there is a direct connection between X and Y and a direct connection between X and Y. including the case where they are electrically connected.

[0032] In addition, when it is explicitly described that X and Y are electrically connected, X and Y are in the case of being electrically connected (that is, connected with another element or another circuit sandwiched between X and Y ), the case where X and Y are functionally connected (that is, functionally connected with another circuit sandwiched between X and Y ), and the case where X and Y are directly connected (that is, connected without another element or another circuit sandwiched between X and Y ) shall be regarded as those disclosed in this specification and the like. That is, when it is explicitly described that they are electrically connected, it shall be regarded that the same content as when it is only explicitly described that they are connected is disclosed in this specification and the like.

[0033] In addition, for example, when the source (or the first terminal, etc.) of a transistor is electrically connected to X via (or without) Z1, and the drain (or the second terminal, etc.) of the transistor is electrically connected to Y via (or without) Z 2, or when the source (or the first terminal, etc.) of the transistor is directly connected to a part of Z1, another part of Z1 is directly connected to X, the drain (or the second terminal, etc.) of the transistor is directly connected to a part of Z2, and another part of Z2 is directly connected to Y, it can be expressed as follows.

[0034] For example, "X, Y, the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor are electrically connected to each other, and X, the source (or the first The source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are electrically connected in this order. It can be expressed as: "The source of the transistor (or the first terminal, etc.) is electrically connected to X, and the drain of the transistor (or the second terminal, etc.) is electrically connected to Y, and X, the source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are electrically connected in this order." Or, "The source of the transistor (or the first terminal, etc.) is electrically connected to X, the drain of the transistor (or the second terminal, etc.) is electrically connected to Y, and X, the source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are electrically connected in this order." Or, "X is electrically connected to Y via the source of the transistor (or the first terminal, etc.) and the drain of the transistor (or the second terminal, etc.), and X, the source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are provided in this connection order." Using the same expression method as these examples, by defining the order of connections in the circuit configuration, the source of the transistor (or the first terminal, etc.) and the drain of the transistor (or the second terminal, etc.) can be distinguished to determine the technical scope. Or, as another expression method, for example, "The source of the transistor (or the first terminal, etc.) is electrically connected to X via at least the first connection path, and the first connection path does not have a second connection path. The second connection path is the path between the source of the transistor (or the first terminal, etc.) and the drain of the transistor (or the second terminal, etc.) through the transistor. The first connection path is the path through Z1. The drain of the transistor (or the second terminal, etc.) is electrically connected to Y via at least the third connection path, and the third connection path does not have the second connection path. The third connection path is the path through Z2." It can be expressed as: "The source of the transistor (or the first terminal, etc.) is electrically connected to X via at least the first connection path, and the first connection path does not have a second connection path. The second connection path is the path between the source of the transistor (or the first terminal, etc.) and the drain of the transistor (or the second terminal, etc.) through the transistor. The first connection path is the path through Z1. The drain of the transistor (or the second terminal, etc.) is electrically connected to Y via at least the third connection path, and the third connection path does not have the second connection path. The third connection path is the path through Z2." Using the same expression method as these examples, by defining the order of connections in the circuit configuration, the source of the transistor (or the first terminal, etc.) and the drain of the transistor (or the second terminal, etc.) can be distinguished to determine the technical scope. Or, as another expression method, for example, "The source of the transistor (or the first terminal, etc.) is electrically connected to X via at least the first connection path, and the first connection path does not have a second connection path. The second connection path is the path between the source of the transistor (or the first terminal, etc.) and the drain of the transistor (or the second terminal, etc.) through the transistor. The first connection path is the path through Z1. The drain of the transistor (or the second terminal, etc.) is electrically connected to Y via at least the third connection path, and the third connection path does not have the second connection path. The third connection path is the path through Z2." Using the same expression method as these examples, by defining the order of connections in the circuit configuration, the source of the transistor (or the first terminal, etc.) and the drain of the transistor (or the second terminal, etc.) can be distinguished to determine the technical scope. Or, as another expression method, for example, "The source of the transistor (or the first terminal, etc.) is electrically connected to X via at least the first connection path, and the first connection path does not have a second connection path. The second connection path is the path between the source of the transistor (or the first terminal, etc.) and the drain of the transistor (or the second terminal, etc.) through the transistor. The first connection path is the path through Z1. The drain of the transistor (or the second terminal, etc.) is electrically connected to Y via at least the third connection path, and the third connection path does not have the second connection path. The third connection path is the path through Z2." Using the same expression method as these examples, by defining the order of connections in the circuit configuration, the source of the transistor (or the first terminal, etc.) and the drain of the transistor (or the second terminal, etc.) can be distinguished to determine the technical scope.

[0035] Or, as another expression method, for example, "The source of the transistor (or the first terminal, etc.) is electrically connected to X via at least the first connection path, and the first connection path does not have a second connection path. The second connection path is the path between the source of the transistor (or the first terminal, etc.) and the drain of the transistor (or the second terminal, etc.) through the transistor. The first connection path is the path through Z1. The drain of the transistor (or the second terminal, etc.) is electrically connected to Y via at least the third connection path, and the third connection path does not have the second connection path. The third connection path is the path through Z2." is electrically connected to X via at least the first connection path, and the first connection path does not have a second connection path. The second connection path is the path between the source of the transistor (or the first terminal, etc.) and the drain of the transistor (or the second terminal, etc.) through the transistor. The first connection path is the path through Z1. The drain of the transistor (or the second terminal, etc.) is electrically connected to Y via at least the third connection path, and the third connection path does not have the second connection path. The third connection path is the path through Z2. is electrically connected to X via at least the first connection path, and the first connection path does not have a second connection path. The second connection path is the path between the source of the transistor (or the first terminal, etc.) and the drain of the transistor (or the second terminal, etc.) through the transistor. The first connection path is the path through Z1. The drain of the transistor (or the second terminal, etc.) is electrically connected to Y via at least the third connection path, and the third connection path does not have the second connection path. The third connection path is the path through Z2. is electrically connected to X via at least the first connection path, and the first connection path does not have a second connection path. The second connection path is the path between the source of the transistor (or the first terminal, etc.) and the drain of the transistor (or the second terminal, etc.) through the transistor. The first connection path is the path through Z1. The drain of the transistor (or the second terminal, etc.) is electrically connected to Y via at least the third connection path, and the third connection path does not have the second connection path. The third connection path is the path through Z2. is electrically connected to X via at least the first connection path, and the first connection path does not have a second connection path. The second connection path is the path between the source of the transistor (or the first terminal, etc.) and the drain of the transistor (or the second terminal, etc.) through the transistor. The first connection path is the path through Z1. The drain of the transistor (or the second terminal, etc.) is electrically connected to Y via at least the third connection path, and the third connection path does not have the second connection path. The third connection path is the path through Z2. is electrically connected to Y via at least the third connection path, and the third connection path does not have the second connection path. The third connection path is the path through Z2. is electrically connected to Y via at least the third connection path, and the third connection path does not have the second connection path. The third connection path is the path through Z2. The connection path can be expressed as "the path via Z2." Or, " The source of the transistor (or the first terminal, etc.) is electrically connected to X via Z1 by at least the first connection path, and the first connection path does not have a second connection path. The second connection path has a connection path via a transistor, and the drain of the transistor (or the second terminal, etc.) is electrically connected to Y via Z2 by at least the third connection path, and the third connection path does not have the second connection path." It can be expressed as such. Or, "The source of the transistor (or the first terminal, etc.) is electrically connected to X via Z1 by at least the first electrical path, and the first electrical path does not have a second electrical path. The second electrical path is an electrical path from the source of the transistor (or the first terminal, etc.) to the drain of the transistor (or the second terminal, etc.). The drain of the transistor (or the second terminal, etc.) is electrically connected to Y via Z2 by at least the third electrical path, and the third electrical path does not have a fourth electrical path. The fourth electrical path is an electrical path from the drain of the transistor (or the second terminal, etc.) to the source of the transistor (or the first terminal, etc.)." By using an expression method similar to these examples to define the connection paths in the circuit configuration, the source of the transistor (or the first terminal, etc.) and the drain (or the second terminal, etc.) can be distinguished to determine the technical scope. Note that these expression methods are just examples and are not limited to these expression methods. Here, X

[0036] ​​​​​​​​​​​​​ , Y, Z1, and Z2 are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layer, etc.).

[0037] In addition, the circuit diagram shows independent components as if they are electrically connected to each other. Even if the components are the same, one component may have the functions of multiple components. For example, when a part of the wiring also functions as an electrode, one conductive film has the function of the wiring and The electrode functions as both components. The term "electrochemically connected" refers to a case where one conductive film has the functions of multiple components. This also falls within the scope of the above.

[0038] (Embodiment 1) In this embodiment, a semiconductor device according to one embodiment of the present invention will be described.

[0039] The structure of a semiconductor device according to one embodiment of the present invention will be described with reference to FIG. One embodiment of the invention is not limited to the configuration described below.

[0040] The semiconductor device illustrated in FIG. 1 includes a circuit 100. The circuit 100 includes a wiring 111, a wiring 113, and a The potential of the wiring 112 is controlled based on the potentials of the wiring 114 and the wiring 115. The circuit 100 is configured to change the voltage based on the potentials of the wirings 111, 113, 114, and 115. The signal thus obtained is output to the wiring 112. The potential of the wiring 112 is controlled by the signal. In this manner, the circuit 100 has a function as a logic circuit or a sequential circuit.

[0041] The circuit 100 includes a transistor 101, a transistor 102, a transistor 103, and a transistor It has a resistor 104, a capacitor element 105, and a capacitor element 106. Transistor 101 has its first terminal (either one of the source or the drain) connected to wiring 111, and its second terminal (the other of the source or the drain) connected to wiring 112. Transistor 102 has its first terminal connected to wiring 113, and its second terminal connected to the gate of transistor 101 . Transistor 103 has its first terminal connected to wiring 114, and its second terminal connected to the gate of transistor 102, and its gate connected to wiring 114. Transistor 104 has its first terminal connected to wiring 115, and its second terminal connected to the gate of transistor 102. Capacitor element 105 has its first terminal connected to wiring 112, and its second terminal connected to the gate of transistor 101. Capacitor element 106 has its first terminal connected to the gate of transistor 101, and its second terminal connected to the gate of transistor 102.

[0042] By having the above connection relationship, the semiconductor device of this embodiment can provide a novel configuration .

[0043] Note that the gate of transistor 101, the second terminal of transistor 102, the second terminal of capacitor element 105 , or the first terminal of capacitor element 106 is denoted as node ND1. Also, the gate of transistor 102, the second terminal of transistor 103, the second terminal of transistor 104, or the second terminal of capacitor element 106 is denoted as node ND2.

[0044] Note that the potentials of wiring 111, wiring 113, wiring 114, and wiring 115 are controlled by inputting signals or voltages, etc. to each wiring. For the sake of convenience, wiring 111, wiring 113, and wiring The potential of 114 shall have a high level and a low level. In other words, wiring 1 11, wiring 113, and wiring 114 each receive a signal having a high level and a low level. Let the high-level potential be VH and the low-level potential be VL (VH > VL). Also, let the potential of wiring 115 be VL. However, the potential of wiring 115 may have a high level and a low level. In other words, a signal having a high level and a low level may be input to wiring 115.

[0045] Note that wiring 111, wiring 113, and wiring 114 may be referred to as input terminals. Also, wiring 1 12 may be referred to as an output terminal. Also, wiring 111, wiring 112, wiring 113, and wiring 114 may be referred to as signal lines. Or, wiring 115 may be referred to as a power line.

[0046] Transistors 101, 102, 103, and 104 will be described. However, one aspect of the present invention is not limited to the transistors described below.

[0047] Transistors 101, 102, 103, and 104 can be transistors having amorphous silicon in the channel formation region, transistors having polycrystalline silicon in the channel formation region, transistors having single-crystalline silicon in the channel formation region, transistors having an oxide semiconductor in the channel formation region, transistors having a compound semiconductor in the channel formation region, etc. In particular, a transistor having an oxide semiconductor in the channel formation region (also referred to as an OS transistor) has a channel formation region, and can be used for various applications such as transistors having a compound semiconductor in the channel formation region. In particular, a transistor having an oxide semiconductor in the channel formation region (also referred to as an OS transistor) has a channel formation region, and can be used for various applications such as transistors having a compound semiconductor in the channel formation region. In particular, a transistor having an oxide semiconductor in the channel formation region (also referred to as an OS transistor) has a channel ​​​​​It has a higher mobility than a transistor having amorphous silicon in a channel formation region, and has a feature that the off-current is extremely small. Therefore, since the channel width of the transistor can be made small, the layout area can be reduced.

[0048] The conductivity type or polarity of transistors 101, 102, 103, and 104 will be described. However, one aspect of the present invention is not limited to the conductivity type or polarity described below.

[0049] Transistors 101, 102, 103, and 104 are preferably of the same conductivity type. Alternatively, all of the transistors included in circuit 100 are preferably of the same conductivity type. Alternatively, all of the transistors provided on the same substrate as circuit 100 are preferably of the same conductivity type. Thereby, simplification of the manufacturing process, improvement in yield, reduction in manufacturing cost, etc. can be achieved.

[0050] In particular, transistors 101, 102, 103, and transistor 104 are preferably N-channel type. Alternatively, all of the transistors included in circuit 100 are preferably all N-channel type. Alternatively, all of the transistors provided on the same substrate as circuit 100 are preferably all N-channel type. Thereby, it becomes possible to employ a transistor having an oxide semiconductor in a channel formation region (also referred to as an OS transistor). FIG. 1 illustrates the case where transistors 101, 102, 103, and transistor 104 are N-channel type. However, the transistor is not limited to this. The resistor 101, the transistors 102, 103, and 104 may be P-channel type. Alternatively, all the transistors included in the circuit 100 may be P-channel type. Or, all the transistors provided on the same substrate as the circuit 100 may be P-channel type. FIG. 26 shows the configuration when the transistors 101, 102, 103, and 104 in FIG. 1 are replaced with transistors 101p, 102p, 103p, and 104p. The transistors 101p, 102p, 103p, and 104p are P-channel type. Also, in configurations other than FIG. 1, N-channel transistors may be replaced with P-channel transistors in the same manner as in FIG. 26. For the sake of convenience, the transistors 101, 102, and 103 will be described as being N-channel type. The resistor 101, the transistors 102, 103, and 104 may be P-channel type. Alternatively, all the transistors included in the circuit 100 may be P-channel type. Or, all the transistors provided on the same substrate as the circuit 100 may be P-channel type. FIG. 26 shows the configuration when the transistors 101, 102, 103, and 104 in FIG. 1 are replaced with transistors 101p, 102p, 103p, and 104p. The transistors 101p, 102p, 103p, and 104p are P-channel type. Also, in configurations other than FIG. 1, N-channel transistors may be replaced with P-channel transistors in the same manner as in FIG. 26. For the sake of convenience, the transistors 101, 102, and 103 will be described as being N-channel type. The resistor 101, the transistors 102, 103, and 104 may be P-channel type. Alternatively, all the transistors included in the circuit 100 may be P-channel type. Or, all the transistors provided on the same substrate as the circuit 100 may be P-channel type. FIG. 26 shows the configuration when the transistors 101, 102, 103, and 104 in FIG. 1 are replaced with transistors 101p, 102p, 103p, and 104p. The transistors 101p, 102p, 103p, and 104p are P-channel type. Also, in configurations other than FIG. 1, N-channel transistors may be replaced with P-channel transistors in the same manner as in FIG. 26. For the sake of convenience, the transistors 101, 102, and 103 will be described as being N-channel type. The resistor 101, the transistors 102, 103, and 104 may be P-channel type. Alternatively, all the transistors included in the circuit 100 may be P-channel type. Or, all the transistors provided on the same substrate as the circuit 100 may be P-channel type. FIG. 26 shows the configuration when the transistors 101, 102, 103, and 104 in FIG. 1 are replaced with transistors 101p, 102p, 103p, and 104p. The transistors 101p, 102p, 103p, and 104p are P-channel type. Also, in configurations other than FIG. 1, N-channel transistors may be replaced with P-channel transistors in the same manner as in FIG. 26. For the sake of convenience, the transistors 101, 102, and 103 will be described as being N-channel type. The resistor 101, the transistors 102, 103, and 104 may be P-channel type. Alternatively, all the transistors included in the circuit 100 may be P-channel type. Or, all the transistors provided on the same substrate as the circuit 100 may be P-channel type. FIG. 26 shows the configuration when the transistors 101, 102, 103, and 104 in FIG. 1 are replaced with transistors 101p, 102p, 103p, and 104p. The transistors 101p, 102p, 103p, and 104p are P-channel type. Also, in configurations other than FIG. 1, N-channel transistors may be replaced with P-channel transistors in the same manner as in FIG. 26. For the sake of convenience, the transistors 101, 102, and 103 will be described as being N-channel type. The resistor 101, the transistors 102, 103, and 104 may be P-channel type. Alternatively, all the transistors included in the circuit 100 may be P-channel type. Or, all the transistors provided on the same substrate as the circuit 100 may be P-channel type. FIG. 26 shows the configuration when the transistors 101, 102, 103, and 104 in FIG. 1 are replaced with transistors 101p, 102p, 103p, and 104p. The transistors 101p, 102p, 103p, and 104p are P-channel type. Also, in configurations other than FIG. 1, N-channel transistors may be replaced with P-channel transistors in the same manner as in FIG. 26. For the sake of convenience, the transistors 101, 102, and 103 will be described as being N-channel type. The resistor 101, the transistors 102, 103, and 104 may be P-channel type. Alternatively, all the transistors included in the circuit 100 may be P-channel type. Or, all the transistors provided on the same substrate as the circuit 100 may be P-channel type. FIG. 26 shows the configuration when the transistors 101, 102, 103, and 104 in FIG. 1 are replaced with transistors 101p, 102p, 103p, and 104p. The transistors 101p, 102p, 103p, and 104p are P-channel type. Also, in configurations other than FIG. 1, N-channel transistors may be replaced with P-channel transistors in the same manner as in FIG. 26. For the sake of convenience, the transistors 101, 102, and 103 will be described as being N-channel type. The resistor 101, the transistors 102, 103, and 104 may be P-channel type. Alternatively, all the transistors included in the circuit 100 may be P-channel type. Or, all the transistors provided on the same substrate as the circuit 100 may be P-channel type. FIG. 26 shows the configuration when the transistors 101, 102, 103, and 104 in FIG. 1 are replaced with transistors 101p, 102p, 103p, and 104p. The transistors 101p, 102p, 103p, and 104p are P-channel type. Also, in configurations other than FIG. 1, N-channel transistors may be replaced with P-channel transistors in the same manner as in FIG. 26. For the sake of convenience, the transistors 101, 102, and 103 will be described as being N-channel type. The resistor 101, the transistors 102, 103, and 104 may be P-channel type. Alternatively, all the transistors included in the circuit 100 may be P-channel type. Or, all the transistors provided on the same substrate as the circuit 100 may be P-channel type. FIG. 26 shows the configuration when the transistors 101, 102, 103, and 104 in FIG. 1 are replaced with transistors 101p, 102p, 103p, and 104p. The transistors 101p, 102p, 103p, and 104p are P-channel type. Also, in configurations other than FIG. 1, N-channel transistors may be replaced with P-channel transistors in the same manner as in FIG. 26. For the sake of convenience, the transistors 101, 102, and 103 will be described as being N-channel type.

[0051] For the sake of convenience, the transistors 101, 102, and 103 will be described as being N-channel type. For the sake of convenience, the transistors 101, 102, and 103 will be described as being N-channel type.

[0052] The functions of the transistors 101, 102, 103, 104, the capacitor elements 105 and 106 will be described. However, one aspect of the present invention is not limited to the functions described below. The functions of the transistors 101, 102, 103, 104, the capacitor elements 105 and 106 will be described. However, one aspect of the present invention is not limited to the functions described below. The functions of the transistors 101, 102, 103, 104, the capacitor elements 105 and 106 will be described. However, one aspect of the present invention is not limited to the functions described below.

[0053] The transistor 101 controls the conduction or non-conduction between the wiring 111 and the wiring 112. When the wiring 111 and the wiring 112 are conductive, the potential of the wiring 111 is supplied to the wiring 112, and the potential of the wiring 112 is controlled based on the potential of the wiring 111. If the potential of the wiring 111 is at a high level, the potential of the wiring 112 rises. In particular, when the potential of the node ND1 is at the high level of the wiring 111, The transistor 101 controls the conduction or non-conduction between the wiring 111 and the wiring 112. When the wiring 111 and the wiring 112 are conductive, the potential of the wiring 111 is supplied to the wiring 112, and the potential of the wiring 112 is controlled based on the potential of the wiring 111. If the potential of the wiring 111 is at a high level, the potential of the wiring 112 rises. In particular, when the potential of the node ND1 is at the high level of the wiring 111, The transistor 101 controls the conduction or non-conduction between the wiring 111 and the wiring 112. When the wiring 111 and the wiring 112 are conductive, the potential of the wiring 111 is supplied to the wiring 112, and the potential of the wiring 112 is controlled based on the potential of the wiring 111. If the potential of the wiring 111 is at a high level, the potential of the wiring 112 rises. In particular, when the potential of the node ND1 is at the high level of the wiring 111, The transistor 101 controls the conduction or non-conduction between the wiring 111 and the wiring 112. When the wiring 111 and the wiring 112 are conductive, the potential of the wiring 111 is supplied to the wiring 112, and the potential of the wiring 112 is controlled based on the potential of the wiring 111. If the potential of the wiring 111 is at a high level, the potential of the wiring 112 rises. In particular, when the potential of the node ND1 is at the high level of the wiring 111, If it is a value higher than the sum of the potential of the loop and the threshold voltage of transistor 101, the potential of wiring 112 rises. If the potential of wiring 111 is at a low level, the potential of wiring 112 drops to VL. When the potential of wiring 111 is at a low level, the potential of wiring 112 drops to VL. L drops.

[0054] Transistor 102 controls the conduction or non - conduction between wiring 113 and node ND1. When wiring 113 and node ND1 are conducting, the potential of wiring 113 is supplied to node ND1, and the potential of node ND1 is controlled based on the potential of wiring 113. If the potential of wiring 113 is at a high level, the potential of node ND1 rises. In particular, if the potential of node ND2 is higher than the sum of the high - level potential of wiring 113 and the threshold voltage of transistor 102, the potential of node ND1 rises to VH. Thus, the potential of node ND1 is set to a value at which transistor 101 turns on. If the potential of wiring 113 is at a low level, the potential of node ND1 drops to VL. Thus, the potential of node ND1 is set to a value at which transistor 101 turns off. When wiring 113 and node ND1 are conducting, the potential of wiring 113 is supplied to node ND1, and the potential of node ND1 is controlled based on the potential of wiring 113. Node ND1's potential is controlled based on the potential of wiring 113. If the potential of wiring 113 is high level, the potential of node ND1 rises. If the potential of wiring 113 is at a high level, the potential of node ND1 rises. In particular, if the potential of node ND2 is higher than the sum of the high - level potential of wiring 113 and the threshold voltage of transistor 102, the potential of node ND1 rises to VH. If the potential of node ND2 is higher than the sum of the high - level potential of wiring 113 and the threshold voltage of transistor 102, the potential of node ND1 rises to VH. Thus, the potential of node ND1 is set to a value at which transistor 101 turns on. If the potential of wiring 113 is at a low level, the potential of node ND1 drops to VL. If the potential of wiring 113 is at a low level, the potential of node ND1 drops to VL. Thus, the potential of node ND1 is set to a value at which transistor 101 turns off. Thus, the potential of node ND1 is set to a value at which transistor 101 turns off.

[0055] Transistor 103 controls the conduction or non - conduction between wiring 114 and node ND2. When wiring 114 and node ND2 are conducting, the potential of wiring 114 is supplied to node ND2, and the potential of node ND2 is controlled based on the potential of wiring 114. If the potential of wiring 114 is at a high level, the potential of node ND2 rises. However, since the gate of transistor 103 is connected to wiring 114, when the potential of node ND2 rises to a value obtained by subtracting the threshold voltage of transistor 103 from the high - level potential of wiring 114, transistor 103 turns off. And node ND2 becomes a floating state. Thus, the potential of node ND2 is When wiring 114 and node ND2 are conducting, the potential of wiring 114 is supplied to node ND2, and the potential of node ND2 is controlled based on the potential of wiring 114. Node ND2's potential is controlled based on the potential of wiring 114. If the potential of wiring 114 is high level, the potential of node ND2 rises. If the potential of wiring 114 is at a high level, the potential of node ND2 rises. However, since the gate of transistor 103 is connected to wiring 114, since the gate of transistor 103 is connected to wiring 114, when the potential of node ND2 rises to a value obtained by subtracting the threshold voltage of transistor 103 from the high - level potential of wiring 114, transistor 103 turns off. when the potential of node ND2 rises to a value obtained by subtracting the threshold voltage of transistor 103 from the high - level potential of wiring 114, transistor 103 turns off. And node ND2 becomes a floating state. Thus, the potential of node ND2 is ​When the value at which transistor 102 turns on is set and node ND2 becomes floating Also, if the potential of wiring 114 is at a low level, transistor 103 turns off , and wiring 114 and node ND2 become non-conductive.

[0056] Note that, as shown in Fig. 2(A), the first terminal of transistor 103 may be connected to wiring 116 , and the gate of transistor 103 may be connected to wiring 114. The potential of wiring 116 is preferably VH. However, the potential of wiring 116 can also have a high level and a low level . In Fig. 2(A), transistor 103 controls the conduction or non-conduction between wiring 116 and node N D2. When wiring 116 and node ND2 conduct, the potential of wiring 1 16 is supplied to node ND2, and the potential of node ND2 is controlled based on the potential of wiring 116 . If the potential of wiring 116 is VH or at a high level, the potential of node ND2 rises. However, since the gate of transistor 103 is connected to wiring 114, when the potential of node ND2 rises from the high-level potential of wiring 114 by a value obtained by subtracting the threshold voltage of transistor 103 , transistor 103 turns off. Then, node ND2 becomes floating . Thus, the potential of node ND2 is set to the value at which transistor 102 turns on and node ND2 becomes floating .

[0057] Note that, as shown in Fig. 2(B), the first terminal of transistor 103 may be connected to wiring 114 , and the gate of transistor 103 may be connected to wiring 116. In Fig. 2(B), transistor 103 controls the conduction or non-conduction between wiring 114 and node ND2. Wiring 1 When 14 is conductive with node ND2, the potential of wiring 114 is supplied to node ND2, and the potential of node ND2 is controlled based on the potential of wiring 114. If the potential of wiring 114 is at a high level, the potential of node ND2 rises. However, since the gate of transistor 103 is connected to wiring 116, when the potential of node ND2 rises to a value obtained by subtracting the threshold voltage of transistor 103 from the potential of wiring 116, transistor 103 turns off. Then, node ND2 becomes a floating state. Thus, the potential of node ND2 is set to a value at which transistor 102 turns on and node ND2 becomes a floating state. Also, if the potential of wiring 114 is at a low level, the potential of node ND2 drops to VL. Thus, the potential of node ND2 is set to a value at which transistor 102 turns off. Note that, as shown in FIG. 3(A), the first terminal and the gate of transistor 103 may be connected to wiring 113. In FIG. 3(A), transistor 103 controls the conduction or non - conduction between wiring 113 and node ND2. When wiring 113 and node ND2 are conductive, the potential of wiring 113 is supplied to node ND2, and the potential of node ND2 is controlled based on the potential of wiring 113. If the potential of wiring 113 is at a high level, the potential of node ND2 rises. However, since the gate of transistor 103 is connected to wiring 113, when the potential of node ND2 rises to a value obtained by subtracting the threshold voltage of transistor 103 from the high - level potential of wiring 113, transistor 103 turns off. Then, node ND2 becomes a floating state. Thus, the potential of node ND2 is set to a value at which transistor 102 turns on.

[0058] At the same time, node ND2 becomes a floating state. Also, if the potential of wiring 113 is at a low level then, since transistor 104 turns off, wiring 113 and node ND2 become non-conductive .

[0059] Note that, as shown in FIG. 3(B), the first terminal of transistor 103 may be connected to wiring 116 and the gate of transistor 103 may be connected to wiring 113. In FIG. 3(B), transistor 103 controls the conduction or non-conduction between wiring 116 and node ND2. When wiring 1 16 and node ND2 conduct, the potential of wiring 116 is supplied to node ND2, and the potential of node ND2 is controlled based on the potential of wiring 116. If the potential of wiring 116 is VH or at a high level, the potential of node ND2 rises. However, since the gate of transistor 103 is connected to wiring 113 , when the potential of node ND2 rises to a value obtained by subtracting the threshold voltage of transistor 103 from the high-level potential of wiring 113 , transistor 10 3 turns off. Then, node ND2 becomes a floating state. In this way, the potential of node ND2 is set to a value at which transistor 102 turns on and node ND2 becomes a floating state .

[0060] Note that although not shown, the first terminal of transistor 103 may be connected to wiring 114 and the gate of transistor 103 may be connected to wiring 113.

[0061] Note that although not shown, the first terminal of transistor 103 may be connected to wiring 113 and the gate of transistor 103 may be connected to wiring 116.

[0062] Transistor 104 controls the conduction or non-conduction between wiring 115 and node ND2. Wiring When 115 is electrically connected to node ND2, the potential of wiring 115 is supplied to node ND2, and the potential of node ND2 is controlled based on the potential of wiring 115. If the potential of wiring 115 is VL or at a low level, the potential of node ND2 drops to VL. Thus, the potential of node ND2 is set to a value at which transistor 102 turns off. - - -

[0063] Note that, as shown in FIG. 4(A), the first terminal of transistor 104 may be connected to wiring 113. In FIG. 4(A), transistor 104 controls the conduction or non-conduction between wiring 113 and node ND2. When wiring 113 and node ND2 are conducting, the potential of wiring 113 is supplied to node ND2, and the potential of node ND2 is controlled based on the potential of wiring 113. If the potential of wiring 113 is VL or at a low level, the potential of node ND2 drops to VL. Thus, the potential of node ND2 is set to a value at which transistor 102 turns off. - - - - - -

[0064] Note that, as shown in FIG. 4(B), the first terminal of transistor 104 may be connected to wiring 114. In FIG. 4(B), transistor 104 controls the conduction or non-conduction between wiring 114 and node ND2. When wiring 114 and node ND2 are conducting, the potential of wiring 114 is supplied to node ND2, and the potential of node ND2 is controlled based on the potential of wiring 114. If the potential of wiring 114 is VL or at a low level, the potential of node ND2 drops to VL. Thus, the potential of node ND2 is set to a value at which transistor 102 turns off. - - - - - -

[0065] Note that, as shown in FIG. 5(A), the gate of transistor 104 may be connected to wiring 111. is also acceptable.

[0066] Note that, as shown in FIG. 5(B), the gate of transistor 104 is connected to wiring 112 is also acceptable.

[0067] The capacitive element 105 holds the potential difference between the wiring 112 and the node ND1. If the node ND1 is in a floating state, the potential of the node ND1 changes based on the change in the potential of the wiring 112. Therefore, if the potential of the node ND1 rises as the potential of the wiring 112 rises, the potential of the node ND1 becomes higher than the sum of the high-level potential of the wiring 111 and the threshold voltage of the transistor 101. When in a floating state, the potential of node ND1 changes based on the change in the potential of wiring 112. Therefore, if the potential of node ND1 rises as the potential of wiring 112 rises, the potential of node ND1 becomes higher than the sum of the high-level potential of wiring 111 and the threshold voltage of transistor 101. For this reason, if the potential of node ND1 rises as the potential of wiring 112 rises, the potential of node ND1 becomes higher than the sum of the high-level potential of wiring 111 and the threshold voltage of transistor 101. 1 is higher than the sum of the high-level potential of wiring 111 and the threshold voltage of transistor 101. becomes higher.

[0068] Note that, as shown in FIG. 6(A), the capacitive element 105 may be omitted. The parasitic capacitance between the second terminal and the gate of the transistor 101 holds the potential difference between the wiring 112 and the node ND1. The potential difference between the wiring 112 and the node ND1 is held by the parasitic capacitance between the second terminal and the gate of the transistor 101. is held.

[0069] The capacitive element 106 holds the potential difference between the node ND1 and the node ND2. If the node ND2 is in a floating state, the potential of the node ND2 changes based on the change in the potential of the node ND1. Therefore, if the potential of the node ND2 rises as the potential of the node ND1 rises, the potential of the node ND2 becomes higher than the sum of the high-level potential of the wiring 113 and the threshold voltage of the transistor 102. When in a floating state, the potential of node ND2 changes based on the change in the potential of node ND1. Therefore, if the potential of node ND2 rises as the potential of node ND1 rises, the potential of node ND2 becomes higher than the sum of the high-level potential of wiring 113 and the threshold voltage of transistor 102. For this reason, if the potential of node ND2 rises as the potential of node ND1 rises, the potential of node ND2 becomes higher than the sum of the high-level potential of wiring 113 and the threshold voltage of transistor 102. 2 is higher than the sum of the high-level potential of wiring 113 and the threshold voltage of transistor 102. becomes higher.

[0070] Note that, as shown in FIG. 6(B), the capacitive element 106 may be omitted. The parasitic capacitance between the second terminal and the gate of the transistor 102 holds the potential difference between the node ND1 and the node ND2. The potential difference between the node ND1 and the node ND2 is held by the parasitic capacitance between the second terminal and the gate of the transistor 102. is held.

[0071] Note that the transistor 101, transistor 102, transistor 103, transistor 1 04, the capacitive element 105, and the capacitive element 106 do not necessarily have all of the functions described above.

[0072] Note that the circuit 100 illustrated and described with reference to FIGS. 1, 2, 3, 4, 5, and 6, etc., and the circuit 100 described without illustration can be appropriately combined.

[0073] The operation of the semiconductor device according to the present embodiment will be described by taking the configuration of FIG. 1 as an example. However, one aspect of the present invention is not limited to the operation described below.

[0074] The timing chart shown in FIG. 7 shows an example of the potential of the wiring 111, the potential of the wiring 113, the potential of the wiring 114, the on or off state of the transistor 104, the potential of the node ND1, the potential of the node ND2, and the potential of the wiring 112.

[0075] For convenience, the description will be divided into four periods: period T1, period T2, period T3, and period T4. For example, one frame period includes periods T1 to T4.

[0076] For convenience, in the period T0 immediately before the period T1, the potential of the wiring 111 is at a low level, the potential of the wiring 113 is at a low level, the potential of the wiring 114 is at a low level, and the node ND1 has a potential of VL, the node ND2 has a potential of VL, and the potential of the wiring 112 is VL It is assumed that. Also, since the potential of the node ND1 is VL, the transistor 101 is off. Also, since the potential of the node ND2 is VL, the transistor 102 is off is.

[0077] The operation during period T1 will be described with reference to FIG. 8(A). The potential of wiring 111 remains at the low level, the potential of wiring 113 remains at the low level, the potential of wiring 114 changes from the low level to the high level, and transistor 104 remains off. Since the potential of wiring 114 becomes the high level, transistor 103 turns on. Therefore, since the high-level potential of wiring 114 is supplied to node ND2, the potential of node ND2

[0078] rises from VL. After that, when the potential of node ND2 becomes higher than the sum (VL + Vth102) of the potential (VL) of the first terminal of transistor 102 and the threshold voltage (Vth102) of transistor 102, transistor 102 turns on. Therefore, since the low-level potential of wiring 113 is supplied to node

[0079] ND1, the potential of node ND1 remains at VL. Also, since the potential of node ND1 remains at VL, transistor 101 remains off. Therefore, the potential of wiring 112 remains at VL.

[0080] After that, when the potential of node ND2 rises to a value (VH - Vth103) obtained by subtracting the threshold voltage (Vth103) of transistor 103 from the potential (VH) of the gate of transistor 103, transistor 103 turns off. Therefore, node ND2 becomes floating, and the potential of node

[0081] ND2 is maintained at VH - Vth103.

[0082] Note that in FIG. 2(A), since the first terminal of transistor 103 is connected to wiring 116, the potential (for example, VH) of wiring 116 is supplied to node ND2.

[0082] The operation during period T2 will be described with reference to FIG. 8(B). The potential of wiring 111 remains at the low level, the potential of wiring 113 changes from the low level to the high level, the potential of wiring 1 14 changes from the high level to the low level, and transistor 104 remains off.

[0083] Since the potential of wiring 114 becomes the low level, transistor 103 remains off. Thus, node ND2 remains in a floating state, and the potential of node ND2 becomes VH - Vth103. Also, since the potential of node ND2 remains at VH - Vth103, transistor 102 remains on. Thus, the high-level potential of wiring 113 is supplied to node N D1, so the potential of node ND1 rises from VL. At this time, capacitor element 1 06 holds the potential difference between node ND1 and node ND2, and node ND2 is in a floating state. Therefore, as the potential of node ND1 rises, the potential of node ND2 rises from VH - Vth103.

[0084] After that, when the potential of node ND1 becomes higher than the sum (VL + Vth101) of the potential (VL) of the first terminal of transistor 101 and the threshold voltage (Vth101) of transistor 101 transistor 101 turns on. Thus, the low-level potential of wiring 111 is supplied to wiring 1 12, so the potential of wiring 112 remains at VL.

[0085] After that, as the potential of node ND1 rises, when the potential of node ND2 rises to a value (VH + Vth102 + α (α is a positive number)) higher than the sum of the potential (VH) of the first terminal of transistor 102 and the threshold voltage (Vth102) of transistor 102 node ND1's ​​​​ The potential rises to VH.

[0086] In addition, in FIG. 2(B), in order to keep the transistor 103 off, it is preferable that the potential of the wiring 114 remains at a high level during the period T2. during which the potential of the wiring 114 remains at a high level.

[0087] In addition, in FIGS. 3(A) and 3(B), during the period T2, the transistor 103 turns on for the first time after the period T0. Specifically, when the potential of the wiring 113 becomes high level, the transistor 103 turns on. Therefore, in FIG. 3(A), the high-level potential of the wiring 113 is supplied to the node ND2, and the potential of the node ND2 rises from VL. On the other hand, in FIG. 3(B), the potential of the wiring 116 (for example, VH) is supplied to the node ND2, and the potential of the node ND2 rises from VL. Then, when the potential of the node ND2 becomes higher than VL + Vth102, the transistor 102 turns on. Therefore, the high-level potential of the wiring 113 is supplied to the node ND1, and the potential of the node ND1 rises from VL. After that, when the potential of the node ND2 becomes VH - Vth103, the transistor 103 turns off, and the node ND2 becomes a floating state. At this time, the potential of the node ND1 is rising. And the capacitive element 106 holds the potential difference between the node ND1 and the node ND2. Therefore, as the potential of the node ND1 rises, the potential of the node ND2 rises from VH - Vht103. After that, when the potential of the node ND1 becomes higher than VL + Vth101, the transistor 101 turns on. Therefore, since the low-level potential of the wiring 111 is supplied to the wiring 112, the potential of the wiring 112 remains at VL. After that, as the potential of the node ND1 rises, the node 0 after which it first turns on. Specifically, when the potential of the wiring 113 becomes high level, the transistor 103 turns on. Thus, in FIG. 3(A), the high level potential of the wiring 113 is supplied to the node ND2, and the potential of the node ND2 rises from VL. On the other hand, in FIG. 3(B), the potential of the wiring 116 (e.g., VH) is supplied to the node ND2, and the potential of the node ND2 rises from VL. Subsequently, when the potential of the node ND2 becomes higher than VL + Vth102, the transistor 102 turns on. Thus, the high level potential of the wiring 113 is supplied to the node ND1, and the potential of the node ND1 rises from VL. After that, when the potential of the node ND2 becomes VH - Vth103, the transistor 103 turns off, and the node ND2 becomes a floating state. At this time, the potential of the node ND1 is rising. And the capacitive element 106 holds the potential difference between the node ND1 and the node ND2. Therefore, as the potential of the node ND1 rises, the potential of the node ND2 rises from VH - Vht103. After that, when the potential of the node ND1 becomes higher than VL + Vth101, the transistor 101 turns on. Therefore, since the low level potential of the wiring 111 is supplied to the wiring 112, the potential of the wiring 112 remains at VL. After that, as the potential of the node ND1 rises, the node becomes high, the transistor 103 turns on. Thus, in FIG. 3(A), the high-level potential of the wiring 113 is supplied to the node ND2, and the potential of the node ND2 rises from VL. is supplied to the node ND2, and the potential of the node ND2 rises from VL. (B), the potential of the wiring 116 (e.g., VH) is supplied to the node ND2, and the potential of the node ND2 rises from VL. Then, when the potential of the node ND2 becomes higher than VL + Vth102, the transistor 102 turns on. Thus, the high-level potential of the wiring 113 is supplied to the node ND1, and the potential of the node ND1 rises from VL. rises from VL. After that, when the potential of the node ND2 becomes VH - Vth103, the transistor 103 turns off, and the node ND 2 becomes a floating state. At this time, the potential of the node ND1 is rising. And the capacitive element 106 holds the potential difference between the node ND1 and the node ND2. Therefore, as the potential of the node ND1 rises, the potential of the node ND2 rises from VH - Vht103. 2 becomes a floating state. At this time, the potential of the node ND1 is rising. And the capacitive element 106 holds the potential difference between the node ND1 and the node ND2. Therefore, as the potential of the node ND1 rises, the potential of the node ND2 rises from VH - Vht103. After that, when the potential of the node ND1 becomes higher than VL + Vth101, the transistor 101 turns on. Therefore, since the low-level potential of the wiring 111 is supplied to the wiring 112, the potential of the wiring 112 remains at VL. After that, as the potential of the node ND1 rises, the node 106 holds the potential difference between the node ND1 and the node ND2. Therefore, as the potential of the node ND1 rises, the potential of the node ND2 rises from VH - Vht103. rises from VH - Vht103 as the potential of the node ND1 rises. After that when the potential of the node ND1 becomes higher than VL + Vth101, the transistor 101 turns on. on. Therefore, since the low-level potential of the wiring 111 is supplied to the wiring 112, the potential of the wiring 112 remains at VL. After that, as the potential of the node ND1 rises, the node When the potential of ND2 rises to VH + Vth102 + α, the potential of node ND1 rises to VH. Thus, in FIGS. 3(A) and 3(B), the operations in periods T1 and T2 of FIG. 1 can be performed collectively in period T2. Therefore, the operating speed can be improved. Regarding the operation in period T3, it will be described with reference to FIG. 9(A). The potential of wiring 111 changes from the low level to the high level, the potential of wiring 113 changes from the high level to the low level, the potential of wiring 114 remains at the low level, and transistor 104 changes from off to on. Since the potential of wiring 114 remains at the low level, transistor 103 remains off. Also, transistor 104 turns on. Therefore, since the potential of wiring 115 is supplied to node ND2, the potential of node ND2 drops from VH + Vth102 + α to VL.

[0088] Since the potential of node ND2 becomes VL, transistor 102 turns off. Therefore, node ND1 becomes a floating state and the potential of node ND1 remains at VH. Since the potential of node ND1 remains at VH, transistor 101 remains on. Therefore, since the high-level potential of wiring 111 is supplied to wiring 112, the potential of wiring 112 rises from VL. At this time, capacitor element 105 holds the potential difference between wiring 112 and node ND1, and node ND1 is in a floating state. Therefore, as the potential of wiring 112 rises, the potential of node ND1 rises from VH. Subsequently, as the potential of wiring 112 rises, the potential of node ND1 becomes the threshold voltage of transistor 101.

[0089]

[0090] ​​​​​​​​​​​​​When it rises above the sum of the potential of terminal (VH) of 1 and the threshold voltage (Vth101) of transistor 101 to a value higher than (VH + Vth101 + β, where β is a positive number), the potential of wiring 112 rises to VH.

[0091] Note that in FIG. 4(A), since the first terminal of transistor 104 is connected to wiring 113, the low-level potential of wiring 113 is supplied to node ND2. Also, in FIG. 4(B), since the first terminal of transistor 104 is connected to wiring 114, the low-level potential of wiring 114 is supplied to node ND2.

[0092] The operation in period T4 will be described with reference to FIG. 9(B). The potential of wiring 111 changes from high level to low level, the potential of wiring 113 remains at low level, the potential of wiring 1 14 changes from low level to high level, and transistor 104 changes from on to off.

[0093] Since the potential of wiring 114 becomes high level, transistor 103 turns on. Thus, the high-level potential of wiring 114 is supplied to node ND2, and the potential of node ND2 rises. At this time, since the potential of node ND1 is VH + Vth101 + β, transistor 101 remains on. Therefore, since the low-level potential of wiring 111 is supplied to wiring 112, the potential of wiring 112 drops from VH to VL.

[0094] After that, when the potential of node ND2 becomes higher than the sum of the potential (VL) of the first terminal of transistor 102 and the threshold voltage (Vth102) of transistor 102, transistor 102 turns on. Thus, since the low-level potential of wiring 113 is supplied to node ND1, ​​​​ , the potential of node ND1 drops from VH + Vth101 + β to VL. Also, since the potential of node ND 1 becomes VL, transistor 101 turns off.

[0095] After that, when the potential of node ND2 rises from the potential of the gate of transistor 103 (VH) to a value obtained by subtracting the threshold voltage (Vth103) of transistor 103, transistor 103 turns off. Thus, node ND2 becomes floating, and the potential of node ND2 is maintained at VH - V ht103.

[0096] Note that in Fig. 2(A), since the first terminal of transistor 103 is connected to wiring 116 , the potential of wiring 116 (for example, VH) is supplied to node ND2.

[0097] The semiconductor device of the present embodiment has a connection relationship capable of performing the above operation, and thus the potential of node ND2 can be set to VH + Vth102 + α.

[0098] The semiconductor device of the present embodiment sets the potential of node ND2 to VH + Vth102 + α, so that the potential difference between the gate and the source of transistor 102 can be maintained at a value greater than the threshold voltage of transistor 102.

[0099] The semiconductor device of the present embodiment maintains the potential difference between the gate and the source of transistor 102 at a value greater than the threshold voltage of transistor 102, thereby raising the potential of node ND1 to VH.

[0100] The semiconductor device of the present embodiment maintains the potential difference between the gate and the source of transistor 102 at a value greater than the threshold By maintaining a value greater than the threshold voltage of the transistor 102, the time required for the potential change at the node ND1 can be shortened.

[0101] The semiconductor device of the present embodiment can increase the potential difference between the gate and the source of the transistor 101 by raising the potential of the node ND1 to VH.

[0102] The semiconductor device of the present embodiment can shorten the time required for the potential change in the wiring 112 by increasing the potential difference between the gate and the source of the transistor 101. That is, a signal with short rise time and fall time can be output to the wiring 112.

[0103] The semiconductor device of the present embodiment can reduce the drive voltage by increasing the potential difference between the gate and the source of the transistors 101 and 102. As a result, the power consumption can be reduced.

[0104] The semiconductor device of the present embodiment can reduce the channel widths of the transistors 101 and 102 by increasing the potential difference between the gate and the source of the transistors 101 and 102. As a result, the layout area can be reduced.

[0105] Since the semiconductor device of the present embodiment can shorten the time required for the potential change at the node ND1 and the time required for the potential change in the wiring 112, the operating speed can be improved.

[0106] ​​​​​​​​​Transistors 101, 102, 103, and 104 The W (channel width) / L (channel length) of will be described. However, one aspect of the present invention is not limited to the W / L described below.

[0107] Transistor 101 drives wiring 112, transistor 102 drives node ND1 , and transistors 103 and 104 drive node ND2. And, the load of wiring 112 is often larger than the loads of node ND1 and node ND2. Therefore, the W / L of transistor 101 is preferably larger than the W / L of transistors 102, 103, and 104. Alternatively, it is preferable that the W / L of transistor 101 is the largest among the transistors included in circuit 100. Alternatively, it is preferable that the W / L of transistor 101 is the largest among the transistors provided on the same substrate as circuit 100. However, transistors having the same or substantially the same W / L as transistor 101 may be provided. In this way, since the driving ability of transistor 101 can be increased, the load of wiring 112 can be increased. Furthermore, since the sizes of transistors 102, 103, and 104 can be reduced, the layout area can be reduced.

[0108] Even when the potential of node ND1 rises, the potential difference between the gate and source of transistor 102 can be maintained at a value equal to or higher than the threshold voltage of transistor 102. Therefore, it is possible Since the potential difference between the gate and the source of the transistor 103 gradually decreases, it is preferable that the W / L of the transistor 103 is large. Therefore, the W / L of the transistor 103 is preferably larger than the W / L of the transistor 102. Thus, since the driving ability of the transistor 103 can be increased, the time required for the potential change at the node ND2 can be shortened. Furthermore, since the size of the transistor 102 can be reduced, the layout area can be reduced. However, the W / L of the transistor 102 may be larger than the W / L of the transistor 103. The circuits 100 illustrated and described with reference to FIGS. 1, 2, 3, 4, 5, and 6, etc., the circuits 100 described without illustration, and the configurations combining these will be described with respect to transistors that can be added. However, one aspect of the present invention is not limited to the configurations described below. The transistor 107 may be added to the circuit 100 described above. FIG. 10(A) shows a configuration in the case where the transistor 107 is added to the circuit 100 shown in FIG. 1. The transistor 107 has a first terminal connected to the wiring 115B and a second terminal connected to the wiring 112. The potential of the wiring 115B is preferably VL. However, the potential of the wiring 115B may have a high level and a low level. The transistor 107 controls the conduction or non-conduction between the wiring 115B and the wiring 112. When the transistor 107 is turned on, the wiring 115B and the wiring 112 are conducted, and the potential of the wiring 112 is controlled based on the potential of the wiring 115B. If the potential of the wiring 115B is VL or a low level, the potential of the wiring 112 becomes VL. Since the potential difference between the gate and the source of the transistor 103 gradually decreases, it is preferable that the W / L of the transistor 103 is large. Therefore, the W / L of the transistor 103 is preferably larger than the W / L of the transistor 102. Thus, since the driving ability of the transistor 103 can be increased, the time required for the potential change at the node ND2 can be shortened. Furthermore, since the size of the transistor 102 can be reduced, the layout area can be reduced. However, the W / L of the transistor 102 may be larger than the W / L of the transistor 103. Since the potential difference between the gate and the source of the transistor 103 gradually decreases, it is preferable that the W / L of the transistor 103 is large. Therefore, the W / L of the transistor 103 is preferably larger than the W / L of the transistor 102. Thus, since the driving ability of the transistor 103 can be increased, the time required for the potential change at the node ND2 can be shortened. Furthermore, since the size of the transistor 102 can be reduced, the layout area can be reduced. However, the W / L of the transistor 102 may be larger than the W / L of the transistor 103. Since the potential difference between the gate and the source of the transistor 103 gradually decreases, it is preferable that the W / L of the transistor 103 is large. Therefore, the W / L of the transistor 103 is preferably larger than the W / L of the transistor 102. Thus, since the driving ability of the transistor 103 can be increased, the time required for the potential change at the node ND2 can be shortened. Furthermore, since the size of the transistor 102 can be reduced, the layout area can be reduced. However, the W / L of the transistor 102 may be larger than the W / L of the transistor 103. Since the potential difference between the gate and the source of the transistor 103 gradually decreases, it is preferable that the W / L of the transistor 103 is large. Therefore, the W / L of the transistor 103 is preferably larger than the W / L of the transistor 102. Thus, since the driving ability of the transistor 103 can be increased, the time required for the potential change at the node ND2 can be shortened. Furthermore, since the size of the transistor 102 can be reduced, the layout area can be reduced. However, the W / L of the transistor 102 may be larger than the W / L of the transistor 103.

[0109] The circuits 100 illustrated and described with reference to FIGS. 1, 2, 3, 4, 5, and 6, etc., the circuits 100 described without illustration, and the configurations combining these will be described with respect to transistors that can be added. However, one aspect of the present invention is not limited to the configurations described below. The circuits 100 illustrated and described with reference to FIGS. 1, 2, 3, 4, 5, and 6, etc., the circuits 100 described without illustration, and the configurations combining these will be described with respect to transistors that can be added. However, one aspect of the present invention is not limited to the configurations described below. The circuits 100 illustrated and described with reference to FIGS. 1, 2, 3, 4, 5, and 6, etc., the circuits 100 described without illustration, and the configurations combining these will be described with respect to transistors that can be added. However, one aspect of the present invention is not limited to the configurations described below. .

[0110] The transistor 107 may be added to the circuit 100 described above. FIG. 10(A) shows a configuration in the case where the transistor 107 is added to the circuit 100 shown in FIG. 1. The transistor 107 has a first terminal connected to the wiring 115B and a second terminal connected to the wiring 112. The potential of the wiring 115B is preferably VL. However, the potential of the wiring 115B may have a high level and a low level. The transistor 107 controls the conduction or non-conduction between the wiring 115B and the wiring 112. When the transistor 107 is turned on, the wiring 115B and the wiring 112 are conducted, and the potential of the wiring 112 is controlled based on the potential of the wiring 115B. If the potential of the wiring 115B is VL or a low level, the potential of the wiring 112 becomes VL. The transistor 107 may be added to the circuit 100 described above. FIG. 10(A) shows a configuration in the case where the transistor 107 is added to the circuit 100 shown in FIG. 1. The transistor 107 has a first terminal connected to the wiring 115B and a second terminal connected to the wiring 112. The potential of the wiring 115B is preferably VL. However, the potential of the wiring 115B may have a high level and a low level. The transistor 107 controls the conduction or non-conduction between the wiring 115B and the wiring 112. When the transistor 107 is turned on, the wiring 115B and the wiring 112 are conducted, and the potential of the wiring 112 is controlled based on the potential of the wiring 115B. If the potential of the wiring 115B is VL or a low level, the potential of the wiring 112 becomes VL. The transistor 107 has a first terminal connected to the wiring 115B and a second terminal connected to the wiring 112. The potential of the wiring 115B is preferably VL. However, the potential of the wiring 115B may have a high level and a low level. The transistor 107 controls the conduction or non-conduction between the wiring 115B and the wiring 112. When the transistor 107 is turned on, the wiring 115B and the wiring 112 are conducted, and the potential of the wiring 112 is controlled based on the potential of the wiring 115B. If the potential of the wiring 115B is VL or a low level, the potential of the wiring 112 becomes VL. The potential of the wiring 115B is preferably VL. However, the potential of the wiring 115B may have a high level and a low level. The transistor 107 controls the conduction or non-conduction between the wiring 115B and the wiring 112. When the transistor 107 is turned on, the wiring 115B and the wiring 112 are conducted, and the potential of the wiring 112 is controlled based on the potential of the wiring 115B. If the potential of the wiring 115B is VL or a low level, the potential of the wiring 112 becomes VL. The potential of the wiring 115B is preferably VL. However, the potential of the wiring 115B may have a high level and a low level. The transistor 107 controls the conduction or non-conduction between the wiring 115B and the wiring 112. When the transistor 107 is turned on, the wiring 115B and the wiring 112 are conducted, and the potential of the wiring 112 is controlled based on the potential of the wiring 115B. If the potential of the wiring 115B is VL or a low level, the potential of the wiring 112 becomes VL. The transistor 107 controls the conduction or non-conduction between the wiring 115B and the wiring 112. When the transistor 107 is turned on, the wiring 115B and the wiring 112 are conducted, and the potential of the wiring 112 is controlled based on the potential of the wiring 115B. If the potential of the wiring 115B is VL or a low level, the potential of the wiring 112 becomes VL. When the transistor 107 is turned on, the wiring 115B and the wiring 112 are conducted, and the potential of the wiring 112 is controlled based on the potential of the wiring 115B. If the potential of the wiring 115B is VL or a low level, the potential of the wiring 112 becomes VL. If the potential of the wiring 115B is VL or a low level, the potential of the wiring 112 becomes VL. Transistor 107 preferably has the same polarity as transistors 101 to 104. .

[0111] During period T1, transistor 107 turns on. Thus, since the potential of wiring 115B is supplied to wiring 112, the potential of wiring 112 becomes VL. However, during period T1, transistor 107 may also be off.

[0112] During period T2, transistor 107 turns on. Thus, since the potential of wiring 115B is supplied to wiring 112, the potential of wiring 112 becomes VL. However, during period T2, transistor 107 may also be off.

[0113] During period T3, transistor 107 turns off.

[0114] During period T4, transistor 107 turns on. Thus, since the potential of wiring 115B is supplied to wiring 112, the potential of wiring 112 becomes VL. However, during period T4, transistor 107 may also be off.

[0115] In FIG. 10(A), since circuit 100 has transistor 107, it is possible to prevent wiring 112 from becoming a floating state and stabilize the potential of wiring 112. Thus, it is possible to prevent malfunction.

[0116] Note that the first terminal of transistor 107 may be connected to wiring 111, wiring 113, wiring 114, or wiring 115. Also, the gate of transistor 107 may be connected to wiring 113 or wiring 114.

[0117] A transistor 108 may be added to the circuit 100 described above. The circuit 100 is configured to include a transistor 108. , a first terminal is connected to the wiring 115C, and a second terminal is connected to the node ND1. The potential of the wiring 115C is preferably VL. However, the potential of the wiring 115C is high level. and a low level. When the transistor 108 is turned on, the transistor 108 controls the conduction or non-conduction between the wiring 115C and the The node ND1 is electrically connected, and the potential of the node ND1 is controlled based on the potential of the wiring 115C. If the potential of the wiring 115C is VL or a low level, the potential of the node ND1 becomes VL. In this way, the potential of the node ND1 is set to a value at which the transistor 101 is turned off. In addition, the transistor 108 has the same polarity as the transistors 101 to 104. preferable.

[0118] In the period T1, the transistor 108 is turned on. The potential of the node ND1 becomes VL. However, during the period T1, Transistor 108 may be off.

[0119] In period T2, transistor 108 is turned off.

[0120] During period T3, transistor 108 is turned off.

[0121] In the period T4, the transistor 108 is turned on. The potential of the node ND1 becomes VL. However, during the period T4, Transistor 108 may be off.

[0122] In FIG. 10(B), since circuit 100 has transistor 108, node ND1 can be prevented from becoming a floating state and the potential of node ND1 can be stabilized. Thus, malfunctions can be prevented.

[0123] Note that the first terminal of transistor 108 may be connected to wiring 111, wiring 113, wiring 114, or wiring 115. Also, the gate of transistor 108 may be connected to wiring 114.

[0124] Note that when both transistor 107 and transistor 108 are added to circuit 100, the gate of transistor 107 and the gate of transistor 108 may be connected. Or, the first terminal of transistor 107 and the first terminal of transistor 108 may be connected.

[0125] One or both of transistor 107 or transistor 108 may be added to the above-described circuit 100, and transistor 109 and transistor 110 may be added. FIG. 11(A) shows a configuration when transistor 107 and transistor 108 are added to circuit 100 shown in FIG. 1, and transistor 109 and transistor 110 are added. Transistor 109 has its first terminal connected to wiring 116, its second terminal connected to the gates of transistor 107 and transistor 108, and its gate connected to wiring 114. Transistor 110 has its first terminal connected to wiring 114, its second terminal connected to the gates of transistor 107 and transistor 108, and its gate connected to node It is connected to ND1. The gate of transistor 107, the gate of transistor 108, the second terminal of transistor 109 or the second terminal of transistor 110 is denoted as node ND3. Transistor 109 controls the conduction or non - conduction between wiring 116 and node ND3. When transistor 109 is turned on, wiring 116 and node ND3 are conducted, and the potential of node ND3 is controlled based on the potential of wiring 116. If the potential of wiring 116 is VH or high level, the potential of node ND3 rises. However, since the gate of transistor 109 is connected to wiring 114, when the potential of node ND3 rises to the value obtained by subtracting the threshold voltage of transistor 109 from the high - level potential of wiring 114, transistor 109 turns off. Then, node ND3 becomes a floating state. In this way, the potential of node ND3 is set to the value at which transistor 107 or transistor 108 turns on, and node ND3 becomes a floating state. Also, transistor 110 controls the conduction or non - conduction between wiring 114 and node ND3. When transistor 110 is turned on, wiring 114 and node ND3 are conducted, and the potential of node ND3 is controlled based on the potential of wiring 114. If the potential of wiring 114 is low level, the potential of node ND3 drops to VL. In this way, the potential of node ND3 is set to the value at which transistor 107 or transistor 108 turns off. Also, transistors 109 and 110 preferably have the same polarity as transistors 101 to 104. During period T1, since wiring 114 becomes high level, transistor 109 turns on. Also, since the potential of node ND1 becomes VL, transistor 110 turns off. When transistor 109 is turned on, wiring 116 and node ND3 are conducted, and the potential of node ND3 is controlled based on the potential of wiring 116. If the potential of wiring 116 is VH or high level, the potential of node ND3 rises. However, since the gate of transistor 109 is connected to wiring 114, when the potential of node ND3 rises to the value obtained by subtracting the threshold voltage of transistor 109 from the high - level potential of wiring 114, transistor 109 turns off. Then, node ND3 becomes a floating state. In this way, the potential of node ND3 is set to the value at which transistor 107 or transistor 108 turns on, and node ND3 becomes a floating state. Also, transistor 110 controls the conduction or non - conduction between wiring 114 and node ND3. When transistor 110 is turned on, wiring 114 and node ND3 are conducted, and the potential of node ND3 is controlled based on the potential of wiring 114. If the potential of wiring 114 is low level, the potential of node ND3 drops to VL. In this way, the potential of node ND3 is set to the value at which transistor 107 or transistor 108 turns off. Also, transistors 109 and 110 preferably have the same polarity as transistors 101 to 104. During period T1, since wiring 114 becomes high level, transistor 109 turns on. Also, since the potential of node ND1 becomes VL, transistor 110 turns off. Transistor 109 controls the conduction or non - conduction between wiring 116 and node ND3. When transistor 109 is turned on, wiring 116 and node ND3 are conducted, and the potential of node ND3 is controlled based on the potential of wiring 116.

[0126] If the potential of wiring 116 is VH or high level, the potential of node ND3 rises. However, since the gate of transistor 109 is connected to wiring 114, when the potential of node ND3 rises to the value obtained by subtracting the threshold voltage of transistor 109 from the high - level potential of wiring 114, transistor 109 turns off. The potential of the wiring 116 is supplied to the node ND3, and the potential of the node ND3 rises from VL to. Thereafter, when the potential of the node ND3 becomes higher than the sum of the potential (VL) of the first terminal of the transistor 107 and the threshold voltage (Vth107) of the transistor 107, the transistor 107 turns on. Also, when the potential of the node ND3 becomes higher than the sum of the potential (VL) of the first terminal of the transistor 108 and the threshold voltage (Vth108) of the transistor 108, the transistor 108 turns on. Thereafter, when the potential of the node ND3 becomes a value obtained by subtracting the threshold voltage (Vth109) of the transistor 109 from the potential (VH) of the gate of the transistor 109, the transistor 109 turns off. Thus, the node ND3 becomes a floating state, and the potential of the node ND3 is maintained at VH - Vth109. In the period T2, since the potential of the wiring 114 becomes a low level, the transistor 109 turns off. Also, when the potential of the node ND1 becomes higher than the sum of the potential (VL) of the first terminal of the transistor 110 and the threshold voltage (Vth110) of the transistor 110, the transistor 110 turns on. Thus, the low-level potential of the wiring 114 is supplied to the node ND3, and the potential of the node ND3 drops from VH - Vth109 to VL. Thus, the transistors 107 and the transistor 108 turn off. In the period T3, since the potential of the wiring 114 remains at a low level, the transistor 10

[0127] 9 remains off. Also, since the potential of the node ND1 becomes VH + Vth110 + β, the transistor 110 remains on. Thus, the low-level potential of the wiring 114 is supplied to the node ND3, and the potential of the node ND3 drops from VH - Vth109 to VL. Thus, the transistors 107 and the transistor 108 turn off. In the period T3, since the potential of the wiring 114 remains at a low level, the transistor 10 9 remains off. Also, since the potential of the node ND1 becomes VH + Vth110 + β,

[0128] 9 remains off. Also, since the potential of the node ND1 becomes VH + Vth110 + β, the transistor 110 remains on. Thus, the low-level potential of the wiring 114 is supplied to the node ND3, and the potential of the node ND3 drops from VH - Vth109 to VL. Thus, the transistors - It is supplied to node ND3, and the potential of node ND3 remains at VL. Therefore, the transistors 107 and transistor 108 remain off.

[0129] During period T4, since the potential of wiring 114 becomes high level, transistor 109 turns on. Also, since the potential of node ND1 becomes VL, transistor 110 turns off. Therefore, the potential of wiring 116 is supplied to node ND3, and the potential of node ND3 rises from VL. After that, when the potential of node ND3 becomes higher than the sum of the potential (V L) of the first terminal of transistor 107 and the threshold voltage (Vth107) of transistor 107, transistor 107 turns on. Also, when the potential of node ND3 becomes higher than the sum of the potential (VL) of the first terminal of transistor 108 and the threshold voltage (Vth108) of transistor 108, transistor 108 turns on.

[0130] FIG. 11(A) shows that since circuit 100 has transistor 109 and transistor 110, a signal for controlling transistor 107 or transistor 108 can be generated within circuit 100. Therefore, the number of signals can be reduced.

[0131] Note that, as shown in FIG. 11(B), the gate of transistor 109 and the first terminal of transistor 110 may be connected to wiring 117. The potential of wiring 117 has a high level (for example, VH) and a low level (for example, VL).

[0132] Note that the gate of transistor 109 may be connected to wiring 117, and the first terminal of transistor 110 may be connected to wiring 114. Alternatively, the gate of transistor 109 may be connected to wiring 1 ​14, and the first terminal of the transistor 110 may be connected to the wiring 117.

[0133] The second terminal of the transistor 109 and the second terminal of the transistor 110 are connected to a transistor The gate of the transistor 107 and the gate of the transistor 108 are Alternatively, the second terminal of the transistor 109 and the The second terminal of 110 is connected to the gate of transistor 107 and the gate of transistor 108. Of these, only the gate of the transistor 108 may be connected.

[0134] The first terminal of the transistor 110 is connected to the wiring 115, the wiring 115B, the wiring 115C, or It may be connected to wiring 117.

[0135] A transistor 121 may be added to the circuit 100 described above. The circuit 100 shown in FIG. 1 includes a transistor 121. 1 has a first terminal connected to the wiring 112, a second terminal connected to the node ND1, and a gate The transistor 121 is connected to the wiring 112 and the node ND1. When the transistor 121 is turned on, the wiring 112 and the node ND For example, in a period T3, the potential of the wiring 112 rises from VL and When the potential of the node ND1 rises from VH, the rise in the potential of the node ND1 is suppressed. In both cases, the time required for the potential of the wiring 112 to change is shortened. Since the gate of the line 112 is connected to the line 111, the potential of the line 112 is the high level of the line 111. When the potential of the transistor 121 becomes equal to the potential of the It turns off. Also, transistor 121 preferably has the same polarity as transistors 101 to 104. Preferably.

[0136] During period T1, since wiring 111 becomes low level, transistor 121 turns off. Turns off.

[0137] During period T2, since wiring 111 becomes low level, transistor 121 turns off. Turns off.

[0138] During period T3, since wiring 111 becomes high level, transistor 121 turns on. However, when the potential of wiring 112 rises to the value obtained by subtracting the threshold voltage (Vth121) of transistor 121 from the potential (VH) of the gate of transistor 121, transistor 121 turns off. However, when the potential of wiring 112 rises to the value obtained by subtracting the threshold voltage (Vth121) of transistor 121 from the potential (VH) of the gate of transistor 121, transistor 121 turns off. 1 turns off. 1 turns off.

[0139] During period T4, since wiring 111 becomes low level, transistor 121 turns off. Turns off.

[0140] FIG. 12(A) shows that by having transistor 121 in circuit 100, it is possible to prevent the potential of node ND1 from becoming too high. Therefore, it is possible to suppress deterioration or prevent destruction of the transistor connected to node ND1. Therefore, it is possible to suppress deterioration or prevent destruction of the transistor connected to node ND1. FIG. 12(A) shows that by having transistor 121 in circuit 100, it is possible to prevent the potential of node ND1 from becoming too high. Therefore, it is possible to suppress deterioration or prevent destruction of the transistor connected to node ND1.

[0141] Transistor 122 may be added to the above-described circuit 100. FIG. 12(B) shows the configuration when transistor 122 is added to the circuit 100 shown in FIG. 1. Transistor 122 has its first terminal connected to node ND1, its second terminal connected to node ND2, and its gate connected to wiring 113. Transistor 122 connects node ND1 and node ND2. FIG. 12(B) shows the configuration when transistor 122 is added to the circuit 100 shown in FIG. 1. Transistor 122 has its first terminal connected to node ND1, its second terminal connected to node ND2, and its gate connected to wiring 113. Transistor 122 connects node ND1 and node ND2. 2 has its first terminal connected to node ND1, its second terminal connected to node ND2, and its gate connected to wiring 113. 2 has its first terminal connected to node ND1, its second terminal connected to node ND2, and its gate connected to wiring 113. Controls conduction or non - conduction. When transistor 122 turns on, node ND1 and node ND2 conduct. For example, when the potential of node ND1 rises from VL and the potential of node ND2 rises from VH - Vth103 during period T2, the rise of the potential of node ND2 is suppressed and the time required for the change in the potential of node ND1 is shortened. However, since the gate of transistor 122 is connected to wiring 113, when the potential of node ND1 reaches a value obtained by subtracting the threshold voltage of transistor 122 from the high - level potential of wiring 113, transistor 122 turns off. Also, transistor 122 preferably has the same polarity as transistors 101 to 104. In period T1, since wiring 113 becomes low - level, transistor 122 turns off. In period T2, since wiring 113 becomes high - level, transistor 122 turns on. However, when the potential of node ND1 rises to a value obtained by subtracting the threshold voltage (Vth122) of transistor 122 from the potential (VH) of the gate of transistor 122, transistor 1 22 turns off. In period T3, since wiring 113 becomes low - level, transistor 122 turns off.

[0142] In period T4, since wiring 113 becomes low - level, transistor 122 turns off.

[0143] In period T2, since wiring 113 becomes high - level, transistor 122 turns on. However, when the potential of node ND1 rises to a value obtained by subtracting the threshold voltage of transistor 122 from the potential of the gate of transistor 122, transistor 1 22 turns off. In period T3, since wiring 113 becomes low - level, transistor 122 turns off.

[0144] In period T4, since wiring 113 becomes low - level, transistor 122 turns off.

[0145] In period T4, since wiring 113 becomes low - level, transistor 122 turns off.

[0146] FIG. 12(B) shows that due to circuit 100 having transistor 122, the It is possible to prevent the potential from becoming too high. Therefore, connected to node ND2 It is possible to suppress the deterioration of the transistor or prevent its breakdown, etc.

[0147] A transistor 123 may be added to the circuit 100 described above. FIG. 13(A) shows the configuration when the transistor 123 is added to the circuit 100 shown in FIG. 1. The transistor 12 3 has its first terminal connected to the wiring 111 and its second terminal connected to the node ND1. The transistor 12 3 controls the conduction or non - conduction between the wiring 111 and the node ND1. When the transistor 123 is turned on, the wiring 111 and the node ND1 are conducted, and the potential of the wiring 111 is supplied to the node ND1. If the potential of the wiring 111 is at a low level, the potential of the node ND1 becomes VL. In this way, the potential of the node ND1 is set to a value at which the transistor 101 turns off. Also, the transistor 123 is preferably of the same polarity as the transistors 101 to 104. polarity as the transistors 101 to 104. polarity as the transistors 101 to 104.

[0148] During the period T0, the transistor 123 is turned on. Therefore, the low - level potential of the wiring 111 is supplied to the node ND1, and the potential of the node ND1 becomes VL. During the period T0, the transistor 123 is turned on. Therefore, the low - level potential of the wiring 111 is supplied to the node ND1, and the potential of the node ND1 becomes VL.

[0149] During the periods T1, T2, T3, and T4, the transistor 123 is turned off. During the periods T1, T2, T3, and T4, the transistor 123 is turned off.

[0150] As shown in FIG. 13(A), since the circuit 100 has the transistor 123, the potential of the node ND1 can be set to VL. Therefore, malfunction can be prevented.

[0151] A transistor 124 may be added to the circuit 100 described above. FIG. 13(B) shows the circuit 100 shown in FIG. 1 with the transistor 124 added. The configuration when transistor 124 is added to the circuit 100 shown is shown. Transistor 12 4 has its first terminal connected to wiring 113 and its second terminal connected to node ND2. The trans istor 124 controls the conduction or non-conduction between wiring 113 and node ND2. When the trans istor 124 is turned on, wiring 113 and node ND2 are conducted, and the potential of wiring 113 is supplied to node ND2. If the potential of wiring 113 is at a low level, the potential of node ND2 becomes VL. In this way, the potential of node ND2 is set to a value at which transistor 102 is turned off. Also, transistor 124 is preferably of the same polarity as transistors 101 to 104.

[0152] During period T0, transistor 124 is turned on. Therefore, the low-level potential of wiring 113 is supplied to node ND2, and the potential of node ND2 becomes VL.

[0153] During periods T1, T2, T3, and T4, transistor 124 is turned off.

[0154] FIG. 13(B) shows that the potential of node ND2 can be set to VL by the circuit 100 having transistor 124. Therefore, malfunction can be prevented.

[0155] Note that when both transistor 123 and transistor 124 are added to circuit 100, the gates of transistor 123 and transistor 124 may be connected.

[0156] The circuit 100 illustrated and described in FIGS. 1, 2, 3, 4, 5, 6, 10, 11, 12, and 13, etc., and the circuit 100 described without being illustrated can be freely combined. ​​​​​​ It is possible.

[0157] FIG. 14(A) shows a configuration in which the first terminal and the gate of the transistor 103 are connected to the wiring 113 (see FIG. 3(A)) and a configuration in which the gate of the transistor 104 is connected to the wiring 111 (see FIG. 5(A)), and is a combined configuration.

[0158] FIG. 14(B) shows a configuration in which the gate of the transistor 104 is connected to the wiring 111 (see FIG. 5(A ), a configuration in which the transistor 108 is added (see FIG. 10(B)), and a configuration in which the transistors 109 and 110 are added (see FIG. 11(B)), and is a combined configuration in this case.

[0159] Note that the present embodiment can be appropriately combined with the descriptions of other embodiments. Therefore, the content described in the present embodiment (even a part of the content) can be applied to, combined with, or replaced with the content described in that other embodiment (even a part of the content), and / or the content described in one or more other embodiments (even a part of the content). Note that the content described in the embodiments refers to the content described using various figures in each embodiment, or the content described using the text described in the specification. Also, the figure (even a part of it) described in a certain embodiment can be combined with another part of that figure, with another figure (even a part of it) described in that embodiment, and / or with one or more figures (even a part of them) described in one or more other embodiments to form even more figures. This is the same in the following embodiments.

[0160] ​​ (Embodiment 2) In this embodiment, a semiconductor device according to one embodiment of the present invention will be described.

[0161] The structure of a semiconductor device according to one embodiment of the present invention will be described with reference to FIG. One embodiment of the present invention is not limited to the configuration described below.

[0162] The semiconductor device illustrated in FIG. 15 includes a circuit 200. The circuit 200 includes a wiring 212 and a wiring 21 3. Based on the potentials of the wiring 214 and the wiring 215, N (N is a natural number equal to or greater than 3) wirings 2 The circuit 20 has a function of controlling the potential of the wirings 211[1] to 211[N]. 0 is a signal based on the potentials of the wiring 212, the wiring 213, the wiring 214, and the wiring 215. 211[1] to [N]. The potential of each of the electrodes [1] to [N] is controlled.

[0163] Specifically, the circuit 200 is configured such that the potentials of the wirings 212, 213, 214, and 215 are The function of sequentially activating the potentials of the wirings 211[1] to [N] based on The potential of the transistors 211[1] to 211[N] is sequentially set to a high level or a low level. In FIG. 16, the circuit 200 is connected to the potentials of the wiring 212, the wiring 213, the wiring 214, and the wiring 215. Based on this, the timing when the potentials of the wirings 211[1] to 211[N] are sequentially set to a high level is A chart is shown below. In this manner, the circuit 200 has a function as a shift register.

[0164] The potentials of the wirings 212, 213, 214, and 215 are connected to the respective wirings by signals or It is controlled by inputting a voltage or the like. For example, a signal CK1 is input to the wiring 212. and a signal CK2 is input to the wiring 213, a signal CK3 is input to the wiring 214, and a signal SP is input to the wiring 215. Signals OUT[1] to [N] are output to each of the wirings 211[1] to [N]. That is, the signals OUT[1] to [N] have values based on the signal CK1, the signal CK2, the signal CK3, and the signal SP. As the signal CK1, the signal CK2, and the signal CK3, there are clock signals having different phases from each other. Also, as the signal SP, there is a start pulse.

[0165] The circuit 200 has N circuits 201 (also denoted as circuits 201[1] to [N]). Each of the circuits 201[1] to [N] corresponds to the circuit 100 described in the first embodiment. In FIG. 15, the circuit 100 shown in FIG. 5(A) is used for each of the circuits 201[1] to [N].

[0166] In the circuit 201[2m + 1] (where m is 0 or a positive integer), the first terminal of the transistor 101 and the gate of the transistor 104 are connected to the wiring 214. Therefore, the wiring 214 corresponds to the wiring 111. Also, the second terminal of the transistor 101 is connected to the wiring 211[2m + 1]. Therefore, the wiring 211[2m + 1] corresponds to the wiring 112. Also, the first terminal of the transistor 102 is connected to the wiring 215 or the wiring 211[2m]. Therefore, the wiring 215 or the wiring 211[2m] corresponds to the wiring 113. Also, the first terminal and the gate of the transistor 103 are connected to the wiring 212. Therefore, the wiring 212 corresponds to the wiring 114. Also, the first terminal of the transistor 104 is connected to the wiring 213. Therefore, the wiring 213 corresponds to the wiring 115.

[0167] ​​​​​​​​​​​ In circuit 201[2m + 2], the first terminal of transistor 101 and the gate of transistor 1 04 are connected to wiring 212. Thus, wiring 212 corresponds to wiring 111. Also, the second terminal of transistor 101 is connected to wiring 211[2m + 2]. Thus , wiring 211[2m + 2] corresponds to wiring 112. Also, the first terminal of transistor 102 is connected to wiring 211[2m + 1]. Thus, wiring 211[2m + 1] is the wiring corresponding to 113. Also, the first terminal and the gate of transistor 103 are connected to wiring 213 and thus, wiring 213 corresponds to wiring 114. Also, the first terminal of transistor 104 is connected to wiring 214. Thus, wiring 214 corresponds to wiring 115.

[0168] In circuit 201[2m + 3], the first terminal of transistor 101 and the gate of transistor 1 04 are connected to wiring 213. Thus, wiring 213 corresponds to wiring 111. Also, the second terminal of transistor 101 is connected to wiring 211[2m + 3]. Thus , wiring 211[2m + 3] corresponds to wiring 112. Also, the first terminal of transistor 102 is connected to wiring 211[2m + 2]. Thus, wiring 211[2m + 2] is the wiring corresponding to 113. Also, the first terminal and the gate of transistor 103 are connected to wiring 214 and thus, wiring 214 corresponds to wiring 114. Also, the first terminal of transistor 104 is connected to wiring 212. Thus, wiring 212 corresponds to wiring 115.

[0169] Note that as shown in FIG. 17, in each of circuits 201[1] to [N], the transistor The first terminal of the switch 104 may be connected to the wiring 216. The wiring 216 corresponds to the wiring 115. Also, the voltage VSS may be supplied to the wiring 216. The voltage VSS has a value (equal or approximately equal value) corresponding to the low levels of the signals CK1, CK2, CK3, and SP, for example. In addition, as shown in FIG. 18, in the circuit 201[2m + 1], the first terminal and the gate of the transistor 103 may be connected to the wiring 213. Also, in the circuit 201[2m + 2], the first terminal and the gate of the transistor 103 may be connected to the wiring 214. Further, in the circuit 201[2m + 3], the first terminal and the gate of the transistor 103 may be connected to the wiring 212. That is, in the circuit 201[i] (where i is any one of 2 to N), the first terminal and the gate of the transistor 103 may be connected to the wiring among the wirings 212, 213, and 214 to which the first terminal of the transistor 101 of the circuit 201[i - 1] is connected. Moreover, when adopting a circuit 100 (see, for example, FIGS. 2(A), 2(B), and 3(B)) in which the first terminal or the gate of the transistor 103 in each of the circuits 201[1] to [N] is connected to the wiring 116, a new wiring to which the first terminal or the gate of the transistor 103 in each of the circuits 201[1] to [N] is connected may be provided. Note that this embodiment can be appropriately combined with the descriptions of other embodiments. Therefore, the content described in this embodiment (even some of the content) may be combined with the other content described in that embodiment.

[0170] In addition, as shown in FIG. 18, in the circuit 201[2m + 1], the first terminal and the gate of the transistor 103 may be connected to the wiring 213. Also, in the circuit 201[2m + 2], the first terminal and the gate of the transistor 103 may be connected to the wiring 214. Further, in the circuit 201[2m + 3], the first terminal and the gate of the transistor 103 may be connected to the wiring 212. That is, in the circuit 201[i] (where i is any one of 2 to N), the first terminal and the gate of the transistor 103 may be connected to the wiring among the wirings 212, 213, and 214 to which the first terminal of the transistor 101 of the circuit 201[i - 1] is connected. That is, in the circuit 201[i] (where i is any one of 2 to N), the first terminal and the gate of the transistor 103 may be connected to the wiring among the wirings 212, 213, and 214 to which the first terminal of the transistor 101 of the circuit 201[i - 1] is connected. That is, in the circuit 201[i] (where i is any one of 2 to N), the first terminal and the gate of the transistor 103 may be connected to the wiring among the wirings 212, 213, and 214 to which the first terminal of the transistor 101 of the circuit 201[i - 1] is connected. That is, in the circuit 201[i] (where i is any one of 2 to N), the first terminal and the gate of the transistor 103 may be connected to the wiring among the wirings 212, 213, and 214 to which the first terminal of the transistor 101 of the circuit 201[i - 1] is connected. That is, in the circuit 201[i] (where i is any one of 2 to N), the first terminal and the gate of the transistor 103 may be connected to the wiring among the wirings 212, 213, and 214 to which the first terminal of the transistor 101 of the circuit 201[i - 1] is connected.

[0171] In addition, when adopting a circuit 100 (see, for example, FIGS. 2(A), 2(B), and 3(B)) in which the first terminal or the gate of the transistor 103 in each of the circuits 201[1] to [N] is connected to the wiring 116, a new wiring to which the first terminal or the gate of the transistor 103 in each of the circuits 201[1] to [N] is connected may be provided. In addition, when adopting a circuit 100 (see, for example, FIGS. 2(A), 2(B), and 3(B)) in which the first terminal or the gate of the transistor 103 in each of the circuits 201[1] to [N] is connected to the wiring 116, a new wiring to which the first terminal or the gate of the transistor 103 in each of the circuits 201[1] to [N] is connected may be provided. In addition, when adopting a circuit 100 (see, for example, FIGS. 2(A), 2(B), and 3(B)) in which the first terminal or the gate of the transistor 103 in each of the circuits 201[1] to [N] is connected to the wiring 116, a new wiring to which the first terminal or the gate of the transistor 103 in each of the circuits 201[1] to [N] is connected may be provided. In addition, when adopting a circuit 100 (see, for example, FIGS. 2(A), 2(B), and 3(B)) in which the first terminal or the gate of the transistor 103 in each of the circuits 201[1] to [N] is connected to the wiring 116, a new wiring to which the first terminal or the gate of the transistor 103 in each of the circuits 201[1] to [N] is connected may be provided.

[0172] Note that this embodiment can be appropriately combined with the descriptions of other embodiments. Therefore, the content described in this embodiment (even some of the content) may be combined with the other content described in that embodiment. Note that this embodiment can be appropriately combined with the descriptions of other embodiments. Therefore, the content described in this embodiment (even some of the content) may be combined with the other content described in that embodiment. Content (which may be part of the content), and / or, apply, combine, or replace, etc. to the content (which may be part of the content) described in one or more other embodiments. It is possible to perform operations such as application, combination, or replacement on the content (which may be part of the content). Note that the content described in the embodiments refers to the content described using various figures or the content described using the text described in the specification in each embodiment. In addition, the figure (which may be part of it) described in a certain embodiment can be combined with another part of the figure, another figure (which may be part of it) described in that embodiment, and / or, one or more figures (which may be part of it) described in one or more other embodiments to form even more figures. This is the same in the following embodiments.

[0173] (Embodiment 3) In this embodiment, a display device according to an aspect of the present invention will be described.

[0174] The configuration of the display device according to an aspect of the present invention will be described with reference to FIG. 19. However, one aspect of the present invention is not limited to the configuration described below.

[0175] The display device shown in FIG. 19 has a pixel portion 301, a scanning line driving circuit 302, and a signal line driving circuit 30 3.

[0176] In the pixel portion 301, N scanning lines GL (also shown as scanning lines GL[1] to [N]) and M ( M is a natural number of 2 or more) signal lines SL (also shown as signal lines SL[1] to [M]) are arranged so as to intersect each other. In addition, pixels 310 are arranged at each intersection portion.

[0177] The pixel 310 has at least a display element and a transistor. As the display element, a light-emitting There are elements and liquid crystal elements. As the light-emitting element, there is an EL element.

[0178] For example, in this specification and the like, a display element, a display device having the display element, a light-emitting element, and a light-emitting device having the light-emitting element can use various forms or have various elements. The display element, the display device, the light-emitting element, or the light-emitting device can be, for example, an EL (electroluminescence) element (including an EL element containing organic and inorganic substances, an organic EL element, an inorganic EL element), an LED (such as a white LED, a red LED, a green LED, a blue LED), a transistor (a transistor that emits light according to current), an electron-emitting element, a liquid crystal element, an electron ink, an electrophoretic element, a grating light valve (GLV), a plasma display (PDP), a display element using MEMS (micro-electro-mechanical system), a digital micromirror device (DMD), a DMS (digital micro-shutter), an IMOD (interference modulation) element, a shutter-type MEMS display element, an optical interference-type MEMS display element, an electro-wetting element, a piezoelectric ceramic display, a display element using carbon nanotubes, etc., and has at least one of these. In addition to these, it may have a display medium in which contrast, brightness, reflectance, transmittance, etc. change due to an electric or magnetic action. As an example of a display device using an EL element, there is an EL display, etc. As an example of a display device using an electron-emitting element, there is a field emission display (FED) or an SED type flat panel display (SED: Surface-conduction Electron-emi ssion Display) ​There are, for example, (tter Display). As an example of a display device using a liquid crystal element, there is a liquid crystal display (transmissive liquid crystal display, transflective liquid crystal display, reflective liquid crystal display, direct-view liquid crystal display, projection liquid crystal display), etc. As an example of a display device using electronic ink or an electrophoretic element, there is electronic paper, etc. Note that when realizing a transflective liquid crystal display or a reflective liquid crystal display, part or all of the pixel electrodes may have the function of a reflective electrode. For example, part or all of the pixel electrodes may have aluminum, silver, etc. Further more, in that case, it is also possible to provide a memory circuit such as SRAM under the reflective electrode. By this, further, power consumption can be reduced. Note that when using an LED, graphene or graphite may be disposed under the electrode of the LED or the nitride semiconductor. Graphene or graphite may be stacked in multiple layers to form a multilayer film. In this way, by providing graphene or graphite, an n-type GaN semiconductor layer having crystals, for example, can be easily formed thereon. Further, a p-type GaN semiconductor layer having crystals, etc. can be provided thereon to form an LED. Note that an AlN layer may be provided between graphene or graphite and the n-type GaN semiconductor layer having crystals. Note also that the GaN semiconductor layer of the LED may be formed by MOCVD. However, by providing graphene, the GaN semiconductor layer of the LED can also be formed by sputtering.

[0179] The scan line drive circuit 302 has a function of controlling the potentials of the scan lines GL[1] to [[ID=N]].The scanning line driving circuit 302 outputs a scanning signal to each of the scanning lines GL[1] to GL[N]. The potential of each of the scanning lines GL[1] to GL[N] is controlled by a scanning signal. The scanning line driver circuit 302 may be the same as the circuit 100 described in the first embodiment or the circuit It is possible to have the circuit 200 described in form 2. In such a case, for example, Each of the scanning lines GL[1] to GL[N] corresponds to the wiring 112. 1] to [N] correspond to the wirings 211[1] to [N], respectively. A signal for controlling the circuit 302 (such as a clock signal and a start pulse, or a signal CK1, Signals CK2, CK3, and SP, etc., are provided from circuit 304.

[0180] The signal line driver circuit 303 has a function of controlling the potential or current of the signal lines SL[1] to SL[M]. The signal line driver circuit 303 supplies video signals to each of the signal lines SL[1] to SL[M]. Then, the potentials of the signal lines SL[1] to SL[M] are changed by the video signal. The signal line driver circuit 303 is controlled in accordance with the circuit 10 described in the first embodiment. 0 or the circuit 200 described in the second embodiment. Signals for controlling the line driving circuit 303 (e.g., a clock signal, a start pulse, a video The input signal, such as a digital signal, is provided by circuit 304.

[0181] The circuit 304 supplies signals to the scanning line driver circuit 302 and the signal line driver circuit 303. Therefore, the circuit 304 functions as a timing controller. A voltage may be supplied to the circuit 302 and the signal line driver circuit 303. In such a case, the circuit 3 04 functions as a power supply circuit.

[0182] Note that the scanning line driving circuit 302 has a slower operation speed than the signal line driving circuit 303. Therefore , it is preferable that the transistors included in the scanning line driving circuit 302 have oxide semiconductor, polycrystalline silicon, or non crystalline silicon in the channel formation region. On the other hand, it is preferable that the transistors included in the signal line driving circuit 30 3 have single crystal silicon in the channel formation region . Therefore, it is preferable to provide the pixel portion 301 and the scanning line driving circuit 302 on the same substrate, and provide the signal line driving circuit 3 03 on a different substrate. However, the pixel portion 301, the scanning line driving circuit 302 and the signal line driving circuit 303 may be provided on the same substrate.

[0183] Note that by adopting the circuit 100 described in the first embodiment or the circuit 200 described in the second embodiment in the scanning line driving circuit 302, all the transistors included in the scanning line driving circuit 302 can be made the same polarity. Therefore, when the pixel portion 301 and the scanning line driving circuit 302 are provided on the same substrate, it is preferable that all the transistors provided on the substrate have the same polarity.

[0184] Note that by adopting the circuit 100 described in the first embodiment or the circuit 200 described in the second embodiment in the scanning line driving circuit 302, the layout area of the scanning line driving circuit 302 can be reduced. Therefore, the resolution of the pixel 310 can be increased . In addition, the frame can be made smaller.

[0185] Note that this embodiment can be appropriately combined with the descriptions of other embodiments. Therefore, the content described in this embodiment (even some of the content) is another described in that embodiment Content (which may be part of the content), and / or apply, combine, or replace, etc. to the content (which may be part of the content) described in one or more other embodiments It is possible to do so. Note that the content described in the embodiments refers to the content described using various figures in each embodiment, or the content described using the text described in the specification. Also, the figure (which may be part of it) described in a certain embodiment can be combined with another part of that figure, another figure (which may be part of it) described in that embodiment, and / or the figure (which may be part of it) described in one or more other embodiments to form more figures. This is the same in the following embodiments.

[0186] (Embodiment 4) In this embodiment, the structure of the semiconductor device described in Embodiment 1 will be described.

[0187] Figure 20 is a top view of the semiconductor device shown in Figure 5(A). Also, Figure 23 is a cross-section taken along line A - B of the top view shown in Figure 20. However, one aspect of the present invention is not limited to the configuration described below.

[0188] The semiconductor device shown in Figure 20 has conductive layers 401A to 401D, semiconductor layers 402A to 402 D, conductive layers 403A to 403I, and insulating layer 404. Figure 21 shows only the conductive layers 40 1A to 401D. Figure 22 shows only the conductive layers 403A to 403I. Also, the X direction is a direction substantially perpendicular to the Y direction. Alternatively, the X direction is a direction that intersects the Y direction.

[0189] ​​​​​​​The insulating layer 404 includes a region that becomes the gate insulating layer of the transistor 101, the transistor 102 a region that becomes the gate insulating layer of, the transistor 103, and the transistor 104 a region that becomes the gate insulating layer of. Further, the insulating layer 404 includes a region sandwiched between the conductive layer 4 01A and the semiconductor layer 402A, a region sandwiched between the conductive layer 401B and the semiconductor layer 402B a region sandwiched between the conductive layer 401C and the semiconductor layer 402C, and a region sandwiched between the conductive layer 401D and the semiconductor layer 402D. Note that the black circles in the figure indicate contact holes included in the insulating layer 404.

[0190] As the insulating layer 404, an insulating layer containing one or more of a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, a hafnium oxide film, a yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film can be used respectively by a plasma enhanced chemical vapor deposition (PECVD) method, a sputtering method, or the like. ning film, etc. film, an aluminum oxide film, a hafnium oxide film, a yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film can be used respectively.

[0191] The conductive layers 401A to 401D are of the same layer. Alternatively, the conductive layers 401A to 401D have the same material. Alternatively, the conductive layers 401A to 401D are formed through a process of processing the same conductive film.

[0192] As the conductive layers 401A to 401D, chromium (Cr), copper (Cu), aluminum (A l), gold (Au), silver (Ag), zinc (Zn), molybdenum (Mo), tantalum (Ta) , titanium (Ti), tungsten (W), manganese (Mn), nickel (Ni), iron (F e), a metal element selected from cobalt (Co), or an alloy containing the above-described metal element as a component, or an alloy formed by combining the above-described metal elements can be formed respectively.

[0193] Also, the conductive layers 401A to 401D may have a single-layer structure or a laminated structure of two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is laminated on an aluminum film, a two-layer structure in which a titanium film is laminated on a titanium nitride film, a two-layer structure in which a tungsten film is laminated on a titanium nitride film, a two-layer structure in which a tungsten film is laminated on a tantalum nitride film or a tungsten nitride film, a three-layer structure in which a titanium film and an aluminum film are laminated on the titanium film, and a titanium film is further formed thereon, etc. Also, an alloy film or a nitride film in which one or a plurality of elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium are combined with aluminum may be used. or a plurality of them may be combined. Alternatively, a nitride film may be used.

[0194] Also, as the conductive layers 401A to 401D, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, acid A conductive material having translucency such as indium tin oxide added with silicon oxide can be applied. It is also possible.

[0195] Also, a Cu-X alloy film (X is Mn, Ni, Cr, F e, Co, Mo, Ta, or Ti) may be applied to the conductive layers 401A to 401D. By using a Cu-X alloy film, , Since it can be processed by a wet etching process, it is possible to suppress the manufacturing cost. It can be.

[0196] The conductive layer 401A has a region that becomes the gate electrode of the transistor 101 and a region that becomes the second electrode of the capacitor element 105. Further, the conductive layer 401A has an opening 401A1 and an opening 401A2. The openings 401A1 and 401A2 have a length along the substantially Y direction. It has a length.

[0197] The conductive layer 401B has a region that becomes the gate electrode of the transistor 102 and a region that becomes the second electrode of the capacitor element 106. Further, the conductive layer 401B has an opening 401B1. The opening 401B1 has a length along the substantially Y direction.

[0198] The conductive layer 401C has a region that becomes the gate electrode of the transistor 103.

[0199] The conductive layer 401D has a region that becomes the gate electrode of the transistor 104.

[0200] Note that the area of the conductive layer 401A is larger than the areas of the conductive layers 401B, 401C, and 401D. Also, the area of the conductive layer 401B is larger than the areas of the conductive layers 401C and 401D. It is larger.

[0201] Note that the areas of the openings 401A1 and 401A2 are larger than the area of the opening 401B1. Also, the widths of the openings 401A1 and 401A2 are larger than the width of the opening 401B1. Further, the length in the longitudinal direction of the openings 401A1 and 401A2 is longer than the length in the longitudinal direction of the opening 401B1. It is longer.

[0202] Note that the conductive layer 401A may be provided with three or more openings, and the conductive layer 401B may be provided with two or more openings. However, the number of openings in the conductive layer 401A is preferably larger than the number of openings in the conductive layer 401B.

[0203] The semiconductor layers 402A to 402D are of the same layer. Alternatively, the semiconductor layers 402A to 402D have the same material. Alternatively, the semiconductor layers 402A to 402D are formed through a process of processing the same semiconductor film.

[0204] Examples of the semiconductor layers 402A to 402D include single-crystalline semiconductors or non-single-crystalline semiconductors. Examples of the non-single-crystalline semiconductors include non-single-crystalline silicon or non-single-crystalline germanium. Examples of the non-single-crystalline silicon include amorphous silicon, microcrystalline silicon, or polycrystalline silicon, and examples of the non-single-crystalline germanium include amorphous germanium, microcrystalline germanium, or polycrystalline germanium.

[0205] In particular, it is preferable to use an oxide semiconductor film as the semiconductor layers 402A to 402D. Examples of the oxide semiconductor film include In-M (where M represents Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf) oxide and In-M-Zn oxide. In particular, it is preferable to use In-M-Zn oxide as the oxide semiconductor film. When the oxide semiconductor film is In-M-Zn oxide, the atomic ratio of the metal elements of the sputtering target used to form the In-M-Zn oxide preferably satisfies In≧M and Zn≧M. Examples of such an atomic ratio of the metal elements of the sputtering target include In:M:Zn =1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:3, In: =1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:3, In: An atomic ratio of M:Zn = 3:1:2 and In:M:Zn = 4:2:4.1 is preferable. Also, when the oxide semiconductor film is an In-M-Zn oxide, as the sputtering target, it is preferable to use a target containing polycrystalline In-M-Zn oxide. By using a target containing polycrystalline In-M-Zn oxide, it becomes easier to form a crystalline oxide semiconductor film. Note that the atomic ratio of the oxide semiconductor film to be formed includes, as an error, a fluctuation of plus or minus 40% of the atomic ratio of the metal elements contained in the above sputtering target. For example, when using a sputtering target with an atomic ratio of In:Ga:Zn = 4:2:4.1, the atomic ratio of the oxide semiconductor film to be formed may be around In:Ga:Zn = 4:2:3.

[0206] The oxide semiconductor film has an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more. By using an oxide semiconductor with a wide energy gap in this way, the off-current of the transistor can be reduced.

[0207] The thickness of the oxide semiconductor film is 3 nm or more and 200 nm or less, preferably 3 nm or more and 100 nm or less, more preferably 3 nm or more and 50 nm or less.

[0208] As the oxide semiconductor film, an oxide semiconductor film with a low carrier density is used. For example, the carrier density of the oxide semiconductor film is 1×10 17 per cm 3 or less, preferably 1×10 15 per cm 3 or less, more preferably 1×10 13 per cm 3 or less, even more preferably 1×101 1 pieces / cm 3 shall be as follows. Further, the carrier density of the oxide semiconductor film is 1×10 5 pieces / cm 3 or more, more preferably 1×10 7 pieces / cm 3 or more may be sufficient.

[0209] Note that the present invention is not limited to these, and those having an appropriate composition may be used according to the semiconductor characteristics and electrical characteristics (field effect mobility, threshold voltage, etc.) of the required transistor. Further, in order to obtain the semiconductor characteristics of the required transistor, it is preferable to make the carrier density, impurity concentration, defect density, atomic number ratio of metal element and oxygen, interatomic distance, density, etc. of the oxide semiconductor film appropriate is preferable.

[0210] Note that as the oxide semiconductor film, an oxide semiconductor film having a low impurity concentration and a low defect level density is used respectively, so that a transistor having more excellent electrical characteristics can be manufactured preferably. Here, a low impurity concentration and a low defect level density (less oxygen deficiency) is called high-purity intrinsic or substantially high-purity intrinsic. The oxide semiconductor film having high-purity intrinsic or substantially high-purity intrinsic has few carrier generation sources, so that the carrier density can be lowered Therefore, a transistor having a channel region formed in the oxide semiconductor film has a low threshold voltage and is less likely to have electrical characteristics (also called normally-on). Further, the oxide semiconductor film having high-purity intrinsic or substantially high-purity intrinsic has a low defect level density Therefore, the trap level density may also be low. Further, the oxide semiconductor film having high-purity intrinsic or substantially high-purity intrinsic has a significantly small off-current, and the channel width is 1×10 or more, and the oxide semiconductor film has a significantly small off-current, and the channel width is 1×10 6μm Even in an element with a channel length L of 10 μm, when the voltage between the source electrode and the drain electrode (drain voltage) is in the range of 1 V to 10 V, the off-current can be below the measurement limit of the semiconductor parameter analyzer, that is, 1×10 -13 A or less.

[0211] Therefore, a transistor in which a channel region is formed in the above high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film has small fluctuations in electrical characteristics and can be a highly reliable transistor. Note that the charges trapped in the trap levels of the oxide semiconductor film may take a long time to disappear and may behave like fixed charges. Therefore, a transistor in which a channel region is formed in an oxide semiconductor film with a high trap level density may have unstable electrical characteristics. Impurities include hydrogen, nitrogen, alkali metals, or alkaline earth metals, etc. characteristics. Impurities include hydrogen, nitrogen, alkali metals, or alkaline earth metals, etc. characteristics. Impurities include hydrogen, nitrogen, alkali metals, or alkaline earth metals, etc. characteristics. Impurities include hydrogen, nitrogen, alkali metals, or alkaline earth metals, etc.

[0212] Hydrogen contained in the oxide semiconductor film reacts with oxygen bonded to metal atoms to form water, and at the same time, oxygen vacancies are formed in the lattice from which oxygen has desorbed (or the part from which oxygen has desorbed). When hydrogen enters the oxygen vacancies, electrons, which are carriers, may be generated. In addition, part of the hydrogen may combine with oxygen bonded to metal atoms to generate electrons, which are carriers. Therefore, a transistor using an oxide semiconductor film containing hydrogen tends to have normally-on characteristics. For this reason, it is preferable that the oxide semiconductor film has hydrogen reduced as much as possible. Specifically, in the oxide semiconductor film, the hydrogen concentration obtained by SIMS analysis is 2×10 a transistor using an oxide semiconductor film containing hydrogen tends to have normally-on characteristics. For this reason, it is preferable that the oxide semiconductor film has hydrogen reduced as much as possible. Specifically, in the oxide semiconductor film, the hydrogen concentration obtained by SIMS analysis is 2×10 a transistor using an oxide semiconductor film containing hydrogen tends to have normally-on characteristics. For this reason, it is preferable that the oxide semiconductor film has hydrogen reduced as much as possible. Specifically, in the oxide semiconductor film, the hydrogen concentration obtained by SIMS analysis is 2×10 atoms / cm 20 atoms / cm 3 or less, preferably 5×1019 atoms / cm 3 Hereinafter, more preferably it is preferably 1×10 19 atoms / cm 3 or less, and more preferably 5×10 18 atoms / cm 3 or less. It is preferably 1×10 18 atoms / cm 3 or less, and more preferably 5×10 17 atom s / cm 3 may be the following. Also, in the oxide semiconductor film, the hydrogen concentration obtained by SIMS analysis is 1×10 or more, and more preferably 1×10 16 atoms / cm 3 or more. 17 a toms / cm 3 may be the following.

[0213] When silicon or carbon, which is one of the Group 14 elements, is contained in the oxide semiconductor film, oxygen deficiency increases in the oxide semiconductor film and it becomes n-type. For this reason, the concentration of silicon or carbon in the oxide semiconductor film and the concentration of silicon or carbon near the interface with the oxide semiconductor film ( the concentration obtained by SIMS analysis) is 2×10 or less. Also, the concentration of silicon or carbon in the oxide semiconductor film and the concentration of silicon or carbon near the interface with the oxide semiconductor film ( 18 the concentration obtained by SIMS analysis) is 1×10 3 or more, and more preferably 3×10 or more, and more preferably 1× 10 17 atoms / cm 3 or more. 17 atoms / cm 3 or more, and more preferably 1× 10 18 atoms / cm 3 may be the following.

[0214] In the oxide semiconductor film, the concentration of alkali metal or alkaline earth metal obtained by SIMS analysis is 1 × 10 18 atoms / cm 3 or less, preferably 2 × 10 16 atom s / cm 3 or less. Alkali metals and alkaline earth metals may combine with the oxide semiconductor and generate carriers, which may increase the off-current of the transistor. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the oxide semiconductor film. Also, in the oxide semiconductor film, the concentration of alkali metal or alkaline earth metal obtained by SIMS analysis is 5 × 10 15 atoms / cm 3 or more, preferably 1 × 10 16 atoms / cm 3 or more.

[0215] When nitrogen is contained in the oxide semiconductor film, carriers, i.e., electrons, are generated, increasing the carrier density and making it easier to form an n-type. As a result, a transistor using an oxide semiconductor film containing nitrogen tends to have normal-on characteristics. Therefore, in the oxide semiconductor film, it is preferable that nitrogen is reduced as much as possible. For example, the nitrogen concentration obtained by SIMS analysis is 5 × 10 18 atoms / cm 3 or less. Also, the nitrogen concentration obtained by SIMS analysis is 1 × 10 16 atoms / cm 3 or more, more preferably 5 × 10 16 atoms / cm 3 or more, more preferably 1 × 10 17 atoms / cm 3 or more, even more preferably 5 × 10 ​17 atoms / cm 3 This may be the case above.

[0216] The oxide semiconductor films may each have a non-single crystal structure. The non-single crystal structure includes, for example, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor), polycrystalline structure, microcrystalline structure, or amorphous structure. In the non-single crystal structure, the amorphous structure has the highest density of defect levels, and CAAC-OS has the lowest density of defect levels.

[0217] Hereinafter, the structure of the oxide semiconductor film will be described.

[0218] The oxide semiconductor film can be divided into a non-single crystal oxide semiconductor film and a single crystal oxide semiconductor film. Or, the oxide semiconductor can be divided into, for example, a crystalline oxide semiconductor and an amorphous oxide semiconductor and the like.

[0219] Note that examples of the non-single crystal oxide semiconductor include CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor), polycrystalline oxide semiconductor, microcrystalline oxide semiconductor, amorphous oxide semiconductor, and the like. Examples of the crystalline oxide semiconductor include single crystal oxide semiconductor, CAAC-OS, polycrystalline oxide semiconductor, microcrystalline oxide semiconductor, and the like.

[0220] First, the CAAC-OS film will be described.

[0221] The CAAC-OS film is one of the oxide semiconductor films having a plurality of crystal parts oriented in the c-axis direction.

[0222] Transmission Electron Microscope (TEM: Transmission Electron Micro ​​By the (scope), a composite analysis image of the bright-field image and diffraction pattern of the CAAC-OS film ( Also referred to as a high-resolution TEM image.) can be observed to confirm a plurality of crystal parts. On the other hand, even with a high-resolution TEM image, the boundary between distinct crystal parts, that is, the grain boundary (grain Boundary is also referred to as boundary.) cannot be confirmed. Therefore, it can be said that in the CAAC-OS film, A decrease in electron mobility due to grain boundaries is unlikely to occur.

[0223] When observing a high-resolution TEM image of the cross-section of the CAAC-OS film from a direction substantially parallel to the sample surface, In the crystal part, it can be confirmed that the metal atoms are arranged in layers. Each layer of metal atoms Reflects the unevenness of the surface (also referred to as the formed surface) or the upper surface of the CAAC-OS film And is arranged parallel to the formed surface or the upper surface of the CAAC-OS film.

[0224] On the other hand, when observing a high-resolution TEM image of the plane of the CAAC-OS film from a direction substantially perpendicular to the sample surface, In the crystal part, it can be confirmed that the metal atoms are arranged in a triangular or hexagonal shape. However, There is no regularity in the arrangement of metal atoms between different crystal parts.

[0225] When performing a structural analysis on the CAAC-OS film using an X-ray diffraction (XRD: X-Ray Diffraction) Apparatus, for example, in the out-of-plane method analysis of a CAAC-OS film 4 Having crystals of InGaZnO A peak may appear near a diffraction angle (2θ) of 31°. This peak is attributed to the (009) plane of the InGaZnO Crystal. 4 Therefore, it can be confirmed that the crystal of the CAAC-OS film has c-axis orientation, and the c-axis is substantially Perpendicular to the formed surface or the upper surface. ​

[0226] Note that, for the out-of-plane method of the CAAC-OS film having InGaZnO 4 crystals, in the analysis by the method, in addition to the peak at around 2θ = 31°, a peak may appear at around 2θ = 36° . The peak at around 2θ = 36° indicates that a part of the CAAC-OS film contains crystals without c-axis orientation . The CAAC-OS film preferably shows a peak at around 2θ = 31° and does not show a peak at around 2θ = 36° .

[0227] The CAAC-OS film is an oxide semiconductor film with a low impurity concentration. Impurities are elements other than the main components of the oxide semiconductor film, such as hydrogen, carbon, silicon, and transition metal elements. In particular, elements such as silicon, which have a stronger binding force with oxygen than the metal elements constituting the oxide semiconductor film, deprive the oxide semiconductor film of oxygen, disrupt the atomic arrangement of the oxide semiconductor film, and reduce the crystallinity . Also, heavy metals such as iron and nickel, argon, carbon dioxide, etc., have a large atomic radius (or molecular radius), so when contained inside the oxide semiconductor film, they disrupt the atomic arrangement of the oxide semiconductor film and reduce the crystallinity. Note that impurities contained in the oxide semiconductor film may become carrier traps or carrier generation sources .

[0228] Also, the CAAC-OS film is an oxide semiconductor film with a low defect level density. For example, oxygen deficiencies in the oxide semiconductor film may become carrier traps or carrier generation sources by capturing hydrogen .

[0229] Having a low impurity concentration and a low defect level density (few oxygen deficiencies) is referred to as high-purity intrinsic or ​It is substantially called high-purity genuineness. An oxide semiconductor film having high-purity genuineness or substantially high-purity genuineness has few carrier generation sources, so the carrier density can be lowered. Therefore, a transistor using the oxide semiconductor film rarely has electrical characteristics in which the threshold voltage becomes negative ( also referred to as normally-on).) An oxide semiconductor film having high-purity genuineness or substantially high purity genuineness has few carrier traps. Therefore, a transistor using the oxide semiconductor film has small fluctuations in electrical characteristics and becomes a highly reliable transistor. Note that the charge trapped in the carrier trap of the oxide semiconductor film takes a long time to be released and may behave like a fixed charge. Therefore, a transistor using an oxide semiconductor film with a high impurity concentration and a high defect level density may have unstable electrical characteristics.

[0230] Also, a transistor using a CAAC-OS film has small fluctuations in electrical characteristics due to irradiation with visible light or ultraviolet light.

[0231] Next, the microcrystalline oxide semiconductor film will be described.

[0232] The microcrystalline oxide semiconductor film has a region where a crystal part can be confirmed and a region where a clear crystal part cannot be confirmed in a high-resolution TEM image. The crystal part contained in the microcrystalline oxide semiconductor film is often 1 nm or more and 100 nm or less, or 1 nm or more and 10 nm or less in size. In particular, an oxide semiconductor film having nanocrystals (nc: nanocrystal) that are microcrystals of 1 nm or more and 10 nm or less, or 1 nm or more and 3 nm or less is referred to as nc -OS (nanocrystalline Oxide Semiconductor) ​​​​​​​​is called a film. Also, in a high-resolution TEM image, for example, the grain boundaries of the nc-OS film may not be clearly identified.

[0233] The nc-OS film has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). Also, the nc-OS film has no regularity in the crystal orientation between different crystal parts. Therefore, no orientation is observed in the whole film. Thus, depending on the analysis method, the nc-OS film may not be distinguishable from an amorphous oxide semiconductor film. For example, when performing structural analysis on the nc-OS film using an XRD apparatus that uses X-rays with a diameter larger than that of the crystal part, no peak indicating a crystal plane is detected in the analysis by the out-of-plane method. Also, when performing electron diffraction (also called limited-field electron diffraction) on the nc-OS film using an electron beam with a probe diameter larger than that of the crystal part (for example, 50 nm or more), a diffraction pattern such as a halo pattern is observed. On the other hand, when performing nano-beam electron diffraction on the nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the crystal part, spots are observed. Also, when performing nano-beam electron diffraction on the nc-OS film, a region with high luminance may be observed as if drawing a circle (in a ring shape). Also, when performing nano-beam electron diffraction on the nc-OS film, a plurality of spots may be observed within the ring-shaped region.

[0234] The nc-OS film is an oxide semiconductor film with higher regularity than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect levels than an amorphous oxide semiconductor film. However, the nc-OS film has no regularity in the crystal orientation between different crystal parts. Therefore, nc-O ​​​​​​​​​​​​​​​The S film has a higher density of defect levels compared to the CAAC-OS film.

[0235] Next, the amorphous oxide semiconductor film will be described.

[0236] The amorphous oxide semiconductor film is an oxide semiconductor film in which the atomic arrangement in the film is irregular and has no crystalline part. An oxide semiconductor film having an amorphous state like quartz is an example. An oxide semiconductor film having an amorphous state like quartz is an example.

[0237] In the high-resolution TEM image, no crystalline part can be confirmed in the amorphous oxide semiconductor film.

[0238] When performing structural analysis on the amorphous oxide semiconductor film using an XRD apparatus, no peak indicating a crystal plane is detected in the out-of-plane method analysis. Also, when performing electron diffraction on the amorphous oxide semiconductor film, a halo pattern is observed. Further, when performing nano-beam electron diffraction on the amorphous oxide semiconductor film, no spot is observed and a halo pattern is observed. When performing structural analysis on the amorphous oxide semiconductor film using an XRD apparatus, no peak indicating a crystal plane is detected in the out-of-plane method analysis. Also, when performing electron diffraction on the amorphous oxide semiconductor film, a halo pattern is observed. Further, when performing nano-beam electron diffraction on the amorphous oxide semiconductor film, no spot is observed and a halo pattern is observed.

[0239] Note that the oxide semiconductor film may have a structure showing physical properties between the nc-OS film and the amorphous oxide semiconductor film. An oxide semiconductor film having such a structure is particularly called an amorphous-like oxide semiconductor (a-like OS: amorphous-like Oxide Semiconductor) film. Note that the oxide semiconductor film may have a structure showing physical properties between the nc-OS film and the amorphous oxide semiconductor film. An oxide semiconductor film having such a structure is particularly called an amorphous-like oxide semiconductor (a-like OS: amorphous-like Oxide Semiconductor) film. conductor) film.

[0240] In the high-resolution TEM image of the a-like OS film, voids (also called voids) may be observed. Also, in the high-resolution TEM image, there are regions where a crystalline part can be clearly confirmed and regions where a crystalline part cannot be confirmed. The a-like OS film In the high-resolution TEM image of the a-like OS film, voids (also called voids) may be observed. Also, in the high-resolution TEM image, there are regions where a crystalline part can be clearly confirmed and regions where a crystalline part cannot be confirmed. ​Crystallization may occur and growth of the crystalline portion may be observed by a minute amount of electron irradiation for observation by TEM. On the other hand, in the case of a high-quality nc-OS film, crystallization due to a minute amount of electron irradiation for observation by TEM is hardly observed. In addition, the size of the crystalline portion of the a-like OS film and the nc-OS film can be measured using a high-resolution TEM image. For example, the crystal of InGaZnO has a layered structure and has two Ga-Zn-O layers between In-O layers. The unit cell

[0241] of the InGaZnO crystal has three In-O layers and six Ga-Zn-O layers, and a total of nine layers are stacked in the c-axis direction in a layered structure. Therefore, the distance between these adjacent layers is approximately the same as the lattice plane spacing of the (009) plane (also referred to as the d value), and the value is determined to be 0.29 nm 4 from crystal structure analysis. Therefore, paying attention to the lattice fringes in the high-resolution TEM image, where the distance between the lattice fringes is 0.28 nm or more and 0.30 nm or less, each lattice fringe corresponds to the a-b plane of the InGaZnO 4 crystal. In addition, the density of the oxide semiconductor film may vary depending on the structure. For example, if the composition of a certain oxide semiconductor film is known, the structure of the oxide semiconductor film can be estimated by comparing it with the density of a single crystal having the same composition. For example, the density of the a-like OS film is 78.6% or more and less than 92.3% with respect to the density of the single crystal. Also, for example, the density of the nc-OS film and the density of the CAAC-OS film are 92.3% or more and less than 100% with respect to the density of the single crystal. Note that an oxide semiconductor film having a density of less than 78% with respect to the density of the single crystal has a density of less than 78% with respect to the density of the single crystal. Therefore, by focusing on the lattice fringes in the high-resolution TEM image and where the distance between the lattice fringes is 0.28 nm or more and 0.30 nm or less, each lattice fringe corresponds to the a-b plane of the InGaZnO crystal. 4 corresponds to the a-b plane of the crystal of InGaZnO.

[0242] Also, the density of the oxide semiconductor film may vary depending on the structure. For example, if the composition of a certain oxide semiconductor film is known, the structure of the oxide semiconductor film can be estimated by comparing it with the density of a single crystal having the same composition. For example, by comparing with the density of a single crystal, the density of the a-like OS film is 78.6% or more and less than 92.3%. Also, for example, by comparing with the density of a single crystal, the density of the nc-OS film and the density of the CAAC-OS film are 92.3% or more and less than 100% with respect to the density of the single crystal. Note that an oxide semiconductor film having a density of less than 78% with respect to the density of the single crystal has a density of less than 78% with respect to the density of the single crystal. For example, the density of the a-like OS film is 78.6% or more and less than 92.3% with respect to the density of the single crystal. Also, for example, the density of the nc-OS film and the density of the CAAC-OS film are 92.3% or more and less than 100% with respect to the density of the single crystal. In addition, an oxide semiconductor film having a density of less than 78% with respect to the density of the single crystal has a density of less than 78% with respect to the density of the single crystal. Film formation itself is difficult.

[0243] Regarding the above, it will be described using specific examples. For example, in an oxide semiconductor film satisfying In:Ga:Zn = 1:1:1 [atomic number ratio], the density of a single crystal InGaZnO having a rhombohedral crystal structure 4 is 6.357 g / cm 3 . Therefore, for example, in an oxide semiconductor film satisfying In:Ga:Zn = 1:1:1 [atomic number ratio], the density of the a-like OS film is 5.0 g / cm 3 or more and less than 5.9 g / cm 3 . Further, for example, in an oxide semiconductor film satisfying In:Ga:Zn = 1:1: 1 [atomic number ratio], the density of the nc-OS film and the density of the CAAC- OS film are 5.9 g / cm 3 or more and less than 6.3 g / cm 3 .

[0244] Note that there may be cases where single crystals of the same composition do not exist. In that case, by combining single crystals with different compositions at arbitrary ratios, the density corresponding to a single crystal of the desired composition can be calculated. The density of a single crystal of the desired composition may be calculated using a weighted average with respect to the ratio of combining single crystals with different compositions. However, it is preferable to calculate the density by combining as few types of single crystals as possible.

[0245] Note that the oxide semiconductor film may be, for example, a laminated film having two or more of an amorphous oxide semiconductor film, an a-like OS film, a microcrystalline oxide semiconductor film, and a CAAC-OS film.

[0246] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. It refers to the state. Therefore, it also includes the case of -5° or more and 5° or less. Also, "substantially parallel" refers to the state where two straight lines are arranged at an angle of -30° or more and 30° or less. Also "perpendicular" refers to the state where two straight lines are arranged at an angle of 80° or more and 100° or less . Therefore, it also includes the case of 85° or more and 95° or less. Also, "substantially perpendicular" refers to two straight lines arranged at an angle of 60° or more and 120° or less

[0247] In addition, in this specification, when the crystal is trigonal or rhombohedral, it is expressed as a hexagonal system .

[0248] The semiconductor layer 402A has a channel formation region of the transistor 101

[0249] The semiconductor layer 402B has a channel formation region of the transistor 102

[0250] The semiconductor layer 402C has a channel formation region of the transistor 103

[0251] The semiconductor layer 402D has a channel formation region of the transistor 104

[0252] Note that the area of the semiconductor layer 402A is larger than the areas of the semiconductor layer 402B, the semiconductor layer 402C, and the semiconductor layer 4 02D. Also, the area of the semiconductor layer 402B is larger than the areas of the semiconductor layer 402C and the semiconductor layer 402D

[0253] Note that the semiconductor layer 402A is provided inside the end of the conductive layer 401A. The semiconductor layer 402 B is provided inside the end of the conductive layer 401B. The semiconductor layer 402C is provided inside the end of the conductive layer 401C . The semiconductor layer 402D is provided inside the end of the conductive layer 401D This can eliminate the step difference in the semiconductor layers 402A to 402D and suppress the occurrence of defects. This can be achieved.

[0254] The conductive layers 403A to 403I are of the same layer. Alternatively, the conductive layers 403A to 403I have the same material. Alternatively, the conductive layers 403A to 403I are formed through a process of processing the same conductive film. That is, they are formed in this way.

[0255] As the conductive layers 403A to 403I, materials or structures applicable to the conductive layers 401A to 401D can be appropriately selected from among them.

[0256] The conductive layer 403A has a region that becomes one of the source electrode or drain electrode of the transistor 101. Also, the conductive layer 403A is connected to the semiconductor layer 402A. Alternatively, the conductive layer 403A has a region in contact with the semiconductor layer 402A. Also, the conductive layer 403A is connected to the conductive layer 401D through the contact hole of the insulating layer 404. Alternatively, the conductive layer 40 3A has a region in contact with the conductive layer 401D. Also, the conductive layer 403A has a plurality of regions 4 03A1. Each of the plurality of regions 403A1 has a length along the substantially Y direction and overlaps with the conductive layer 401A through the semi conductor layer 402A. Also, the conductive layer 403A has a region 403 A2. The region 403A2 has a length along the substantially X direction and does not overlap with the semiconductor layer 402A and the conductive layer 401A.

[0257] The conductive layer 403B has a region that becomes the other of the source electrode or drain electrode of the transistor 101, a region that becomes the first electrode of the capacitor element 105, and a region that becomes the wiring 113. Also, the conductive layer 403B is connected to the semiconductor layer 402A. Alternatively, the conductive layer 403B and has a region in contact with the semiconductor layer 402A. Further, the conductive layer 403B has a plurality of regions 403 B1. The plurality of regions 403B1 have a long dimension along the substantially Y direction and overlap with the conductive layer 401A via the semiconductor layer 402A . Further, the conductive layer 403B has a region 403B2. The region 403B2 has a long dimension along the substantially X direction and overlaps with the conductive layer 40 1A without passing through the semiconductor layer 402A. Further, the conductive layer 403B has an opening 403B3 and an opening 403B4 . The opening 403B3 and the opening 403B4 have a long dimension along the substantially Y direction.

[0258] The conductive layer 403C has a region that becomes one of the source electrode or the drain electrode of the transistor 102 and a region that becomes the wiring 113. Further, the conductive layer 403C is connected to the semiconductor layer 402B . Alternatively, the conductive layer 403C has a region in contact with the semiconductor layer 402B. Further, the conductive layer 403C has a plurality of regions 403C1. The plurality of regions 403C1 have a long dimension along the substantially Y direction and overlap with the conductive layer 401B via the semiconductor layer 402B. Further, the conductive layer 403C has a region 403C2. The region 403C2 has a long dimension along the substantially X direction and does not overlap with the semiconductor layer 402B and the conductive layer 401B.

[0259] The conductive layer 403D has a region that becomes the other of the source electrode or the drain electrode of the transistor 102 and a region that becomes the first electrode of the capacitor element 106. Further, the conductive layer 403D is connected to the semi conductor layer 402B. Alternatively, the conductive layer 403D has a region in contact with the semiconductor layer 402B . Further, the conductive layer 403D is connected to the conductive layer 401A via a contact hole of the insulating layer 404 . Alternatively, the conductive layer 403D has a region in contact with the conductive layer 401A It has. Also, the conductive layer 403D has a plurality of regions 403D1. The plurality of regions 403D 1 has a long dimension along the substantially Y direction and overlaps with the conductive layer 401B via the semiconductor layer 402B. Also, the conductive layer 403D has a region 403D2. The region 403D2 has a long dimension along the substantially X direction and overlaps with the conductive layer 401B without passing through the semiconductor layer 402B. Also, the conductive layer 403 D has an opening 403D3. The opening 403D3 has a long dimension along the substantially Y direction.

[0260] The conductive layer 403E has a region that becomes one of the source electrode or the drain electrode of the transistor 103 and is connected to the semiconductor layer 402C. Alternatively, the conductive layer 4 03E has a region in contact with the semiconductor layer 402C. Also, the conductive layer 403E is connected to the conductive layer 4 01C through the contact hole of the insulating layer 404. Alternatively, the conductive layer 403E has a region in contact with the conductive layer 401C.

[0261] The conductive layer 403F has a region that becomes the other of the source electrode or the drain electrode of the transistor 103 and a region that becomes the other of the source electrode or the drain electrode of the transistor 104. Also, the conductive layer 403F is connected to the semiconductor layer 402C and is connected to the semiconductor layer 402D . Alternatively, the conductive layer 403F has a region in contact with the semiconductor layer 402C and a region in contact with the semiconductor layer 402D and is connected to the conductive layer 401B through the contact hole of the insulating layer 404. Alternatively, the conductive layer 403F has a region in contact with the conductive layer 401B . region.

[0262] The conductive layer 403G has a region that becomes the wiring 111. Also, the conductive layer 403G is the insulating layer 4 04 via a contact hole. has a region in contact with conductive layer 401D.

[0263] The conductive layer 403H has a region that becomes the wiring 114. The conductive layer 403H is also formed on the insulating layer 4. 04 via the contact hole. has a region in contact with conductive layer 401C.

[0264] The conductive layer 403I is a region that will become the wiring 115 and a region that will become the source electrode or drain electrode of the transistor 104. The conductive layer 403I has a region that is to become one of the in-electrodes. Alternatively, the conductive layer 403I has a region in contact with the semiconductor layer 402D.

[0265] The area of ​​the opening 403B3 is larger than the area of ​​the opening 401A1. The area of ​​opening 401A1 is larger than the area of ​​opening 401A2. 3B3, and opening 401A2 is provided inside opening 403B4. This eliminates the step of the conductive layer 403B caused by the conductive layer 401A, and prevents the occurrence of defects. It can be suppressed.

[0266] The area of ​​the opening 403D3 is larger than the area of ​​the opening 401B1. The conductive layer 404A1 is provided inside the opening 403D3. This can eliminate steps in the conductive layer 403D caused by the above, thereby suppressing the occurrence of defects.

[0267] Note that the region 403A2 of the conductive layer 403A does not overlap the conductive layer 401A and the semiconductor layer 402A. On the other hand, the region 403B2 of the conductive layer 403B is connected to the conductive layer 4 without the intermediation of the semiconductor layer 402A. It overlaps with 01A. However, the region 403B2 of the conductive layer 403B may overlap with the conductive layer 401A via the semiconductor layer 402A. Also, the overlapping area of the conductive layer 403A and the conductive layer 401A is smaller than the overlapping area of the conductive layer 403B and the conductive layer 401A. Thereby, the parasitic capacitance between the conductive layer 403A and the conductive layer 401A can be reduced, and the parasitic capacitance between the conductive layer 403B and the conductive layer 401A can be increased. Therefore, the influence on the gate of the potential transistor 101 of the wiring 111 can be reduced, and the layout area can be reduced by making it possible to reduce the capacitance value of the capacitor element 105. The parasitic capacitance between the conductive layer 403A and the conductive layer 401A can be reduced, and the parasitic capacitance between the conductive layer 403B and the conductive layer 401A can be increased. Thus, the influence on the gate of the potential transistor 101 of the wiring 111 can be reduced, and the layout area can be reduced by making it possible to reduce the capacitance value of the capacitor element 105. Note that the region 403C2 of the conductive layer 403C does not overlap with the conductive layer 401B and the semiconductor layer 402B, while the region 403D2 of the conductive layer 403D overlaps with the conductive layer 401B without passing through the semiconductor layer 402B. However, the region 403D2 of the conductive layer 403D may overlap with the conductive layer 401B via the semiconductor layer 402B. Also, the overlapping area of the conductive layer 403C and the conductive layer 401B is smaller than the overlapping area of the conductive layer 403D and the conductive layer 401B. Thereby, the parasitic capacitance between the conductive layer 403C and the conductive layer 401B can be reduced, and the parasitic capacitance between the conductive layer 403D and the conductive layer 401B can be increased. Therefore, the influence on the gate of the potential transistor 102 of the wiring 113 can be reduced, and the layout area can be reduced by making it possible to reduce the capacitance value of the capacitor element 106. Note that the region 403C2 of the conductive layer 403C does not overlap with the conductive layer 401B and the semiconductor layer 402B, while the region 403D2 of the conductive layer 403D overlaps with the conductive layer 401B without passing through the semiconductor layer 402B. However, the region 403D2 of the conductive layer 403D may overlap with the conductive layer 401B via the semiconductor layer 402B. Also, the overlapping area of the conductive layer 403C and the conductive layer 401B

[0268] Note that the region 403C2 of the conductive layer 403C does not overlap with the conductive layer 401B and the semiconductor layer 402B, while the region 403D2 of the conductive layer 403D overlaps with the conductive layer 401B without passing through the semiconductor layer 402B. However, the region 403D2 of the conductive layer 403D may overlap with the conductive layer 401B via the semiconductor layer 402B. Also, the overlapping area of the conductive layer 403C and the conductive layer 401B Note that the region 403C2 of the conductive layer 403C does not overlap with the conductive layer 401B and the semiconductor layer 402B, while the region 403D2 of the conductive layer 403D overlaps with the conductive layer 401B without passing through the semiconductor layer 402B. However, the region 403D2 of the conductive layer 403D may overlap with the conductive layer 401B via the semiconductor layer 402B. Also, the overlapping area of the conductive layer 403C and the conductive layer 401B It overlaps with 01A. However, the region 403B2 of the conductive layer 403B may overlap with the conductive layer 401A via the semiconductor layer 402A. Also, the overlapping area of the conductive layer 403A and the conductive layer 401A is smaller than the overlapping area of the conductive layer 403B and the conductive layer 401A. Thereby, the parasitic capacitance between the conductive layer 403A and the conductive layer 401A can be reduced, and the parasitic capacitance between the conductive layer 403B and the conductive layer 401A can be increased. Therefore, the influence on the gate of the potential transistor 101 of the wiring 111 can be reduced, and the layout area can be reduced by making it possible to reduce the capacitance value of the capacitor element 105. The parasitic capacitance between the conductive layer 403A and the conductive layer 401A can be reduced, and the parasitic capacitance between the conductive layer 403B and the conductive layer 401A can be increased. Thus, the influence on the gate of the potential transistor 101 of the wiring 111 can be reduced, and the layout area can be reduced by making it possible to reduce the capacitance value of the capacitor element 105. Note that the region 403C2 of the conductive layer 403C does not overlap with the conductive layer 401B and the semiconductor layer 402B, while the region 403D2 of the conductive layer 403D overlaps with the conductive layer 401B without passing through the semiconductor layer 402B. However, the region 403D2 of the conductive layer 403D may overlap with the conductive layer 401B via the semiconductor layer 402B. Also, the overlapping area of the conductive layer 403C and the conductive layer 401B is smaller than the overlapping area of the conductive layer 403D and the conductive layer 401B. Thereby, the parasitic capacitance between the conductive layer 403C and the conductive layer 401B can be reduced, and the parasitic capacitance between the conductive layer 403D and the conductive layer 401B can be increased. Therefore, the influence on the gate of the potential transistor 102 of the wiring 113 can be reduced, and the layout area can be reduced by making it possible to reduce the capacitance value of the capacitor element 106. Note that the region 403C2 of the conductive layer 403C does not overlap with the conductive layer 401B and the semiconductor layer 402B, while the region 403D2 of the conductive layer 403D overlaps with the conductive layer 401B without passing through the semiconductor layer 402B. However, the region 403D2 of the conductive layer 403D may overlap with the conductive layer 401B via the semiconductor layer 402B. Also, the overlapping area of the conductive layer 403C and the conductive layer 401B

[0269] There are no major restrictions on the materials of the substrates on which the conductive layers 401A to 401D, the semiconductor layers 402A to 402D, the conductive layers 403A to 403I, and the insulating layer 404 are formed, but at least There are no major restrictions on the materials of the substrates on which the conductive layers 401A to 401D, the semiconductor layers 402A to 402D, the conductive layers 403A to 403I, and the insulating layer 404 are formed, but at least At least, it is necessary to have heat resistance enough to withstand subsequent heat treatment. For example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. may be used as the substrate. Also, a single crystal semiconductor substrate, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, etc. made of silicon or silicon carbide can also be applied, and those with semiconductor elements provided on these substrates may be used as the substrate. When using a glass substrate as the substrate, large area substrates such as the 6th generation (1500mm×1850mm), 7th generation (1 870mm×2200mm), 8th generation (2200mm×2400mm), 9th generation (2 400mm×2800mm), 10th generation (2950mm×3400mm) can be used to fabricate a large display device. In addition, a flexible substrate may be used as the substrate, and transistors may be formed directly on the flexible substrate. Or, a release layer may be provided between the substrate and the transistor. The release layer is used to separate from the substrate after partially or completely completing a semiconductor device thereon and transfer it to another substrate. At that time, the transistor can also be transferred to a substrate with poor heat resistance or a flexible substrate. For example, in this specification, etc., it has been common to form transistors using various substrates. The type of the substrate is not limited to a specific one. As an example of the substrate, a semiconductor substrate (for example, a single crystal substrate or a silicon substrate), an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a metal substrate, a stainless steel substrate, a stainless steel foil can be used. Moreover, a flexible substrate may be used as the substrate, and transistors may be formed directly on the flexible substrate. Or, a release layer may be provided between the substrate and the transistor. The release layer is used to separate from the substrate after partially or completely completing a semiconductor device thereon and transfer it to another substrate. At that time, the transistor can also be transferred to a substrate with poor heat resistance or a flexible substrate.

[0270] For example, in this specification and the like, it has been common to form transistors using various substrates. The type of the substrate is not limited to a specific one. As an example of the substrate, a semiconductor substrate (for example, a single crystal substrate or a silicon substrate), an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a metal substrate, a stainless steel substrate, a stainless steel foil can be used. Moreover, a flexible substrate may be used as the substrate, and transistors may be formed directly on the flexible substrate. Or, a release layer may be provided between the substrate and the transistor. The release layer is used to separate from the substrate after partially or completely completing a semiconductor device thereon and transfer it to another substrate. At that time, the transistor can also be transferred to a substrate with poor heat resistance or a flexible substrate. For example, in this specification and the like, it has been common to form transistors using various substrates. The type of the substrate is not limited to a specific one. As an example of the substrate, a semiconductor substrate (for example, a single crystal substrate or a silicon substrate), an SOI substrate, a glass substrate, a quartz substrate,

[0271] For example, in this specification and the like, it has been common to form transistors using various substrates. The type of the substrate is not limited to a specific one. As an example of the substrate, a semiconductor substrate (for example, a single crystal substrate or a silicon substrate), an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a metal substrate, a stainless steel substrate, a stainless steel foil can be used. a plastic substrate, a metal substrate, a stainless steel substrate, a stainless steel foil can be Substrates include those having a substrate, a tungsten substrate, a substrate having a tungsten foil, a flexible substrate, a bonded film, paper containing a fibrous material, or a base film. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, or soda lime glass. Examples of flexible substrates, bonded films, base films, etc. include the following. For example, plastics represented by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), polytetrafluoro ethylene (PTFE). Or, as an example, there are synthetic resins such as acrylic resins. Or, as an example, there are polypropylene, polyester, poly vinyl fluoride, or polyvinyl chloride. Or, as an example, there are polyester films, polyamides, polyimides, aramids, epoxies, inorganic vapor deposition films, or papers. In particular, by manufacturing transistors using semiconductor substrates, single-crystal substrates, or SOI substrates, etc., transistors with less variation in characteristics, size, or shape, high current capacity, and small size can be manufactured. By configuring a circuit with such transistors, low power consumption of the circuit or high integration of the circuit can be achieved. Moreover, a flexible substrate may be used as the substrate, and transistors may be formed directly on the flexible substrate. Or, a release layer may be provided between the substrate and the transistor. The release layer can be separated from the substrate after partially or fully completing a semiconductor device thereon and used for

[0272] transferring to another substrate. At that time, the transistors can also be transferred to substrates with poor heat resistance or flexible substrates. Or, a release layer may be provided between the substrate and the transistor. The release layer can be separated from the substrate after partially or fully completing a semiconductor device thereon and used for transferring to another substrate. After partially or fully completing a semiconductor device thereon, it can be separated from the substrate and used for transferring to another substrate. At that time, the transistors can be transferred to substrates with poor heat resistance or flexible substrates. It can be carried. Note that for the above-described release layer, for example, a laminated structure composed of a tungsten film and a silicon oxide film, a structure in which an organic resin film such as polyimide is formed on a substrate, etc. can be used. That is, a transistor may be formed using a certain substrate, and then the transistor may be transferred to another substrate and arranged on the other substrate. As an example of the substrate to which the transistor is transferred, in addition to the substrate on which the above-described transistor can be formed, a paper substrate, a cellophane substrate, an aramid film substrate, a polyimide film substrate, a stone substrate, a wood substrate, a cloth substrate (including natural fibers (silk, cotton, linen), synthetic fibers (nylon, polyurethane, polyester), or regenerated fibers (acetate, cupra, rayon, recycled polyester), etc.), a leather substrate, or a rubber substrate, etc. By using these substrates, it is possible to form a transistor with good characteristics, form a transistor with low power consumption, manufacture a device that is not easily broken, impart heat resistance, reduce weight, or make it thinner. It can be done.

[0273] That is, a transistor may be formed using a certain substrate, and then the transistor may be transferred to another substrate and arranged on the other substrate. As an example of the substrate to which the transistor is transferred, in addition to the substrate on which the above-described transistor can be formed, a paper substrate, a cellophane substrate, an aramid film substrate, a polyimide film substrate, a stone substrate, a wood substrate, a cloth substrate (including natural fibers (silk, cotton, linen), synthetic fibers (nylon, polyurethane, polyester), or regenerated fibers (acetate, cupra, rayon, recycled polyester), etc.), a leather substrate, or a rubber substrate, etc. By using these substrates, it is possible to form a transistor with good characteristics, form a transistor with low power consumption, manufacture a device that is not easily broken, impart heat resistance, reduce weight, or make it thinner. A leather substrate, or a rubber substrate, etc. (Including natural fibers (silk, cotton, linen), synthetic fibers (nylon, polyurethane, polyester), or regenerated fibers (acetate, cupra, rayon, recycled polyester), etc.), a leather substrate, or a rubber substrate, etc. A leather substrate, or a rubber substrate, etc. By using these substrates, it is possible to form a transistor with good characteristics, form a transistor with low power consumption, manufacture a device that is not easily broken, impart heat resistance, reduce weight, or make it thinner. It can be achieved.

[0274] Note that this embodiment can be appropriately combined with the descriptions of other embodiments. Therefore, the content described in this embodiment (even part of the content) can be applied, combined, or replaced, etc. with the content described in that embodiment (even part of the content), and / or the content described in one or more other embodiments (even part of the content). Note that the content described in the embodiments refers to the content described using various figures in each embodiment or the content described using the text described in the specification. That is, the content described in this embodiment (even part of the content) can be applied, combined, or replaced, etc. with the content described in that embodiment (even part of the content), and / or the content described in one or more other embodiments (even part of the content). Note that the content described in the embodiments refers to the content described using various figures in each embodiment or the content described using the text described in the specification. Also, the figure (even part of it) described in a certain embodiment can be applied, combined, or replaced, etc. with another part of that figure, Note that the content described in the embodiments refers to the content described using various figures in each embodiment or the content described using the text described in the specification. That is, the content described in this embodiment (even part of the content) can be applied, combined, or replaced, etc. with the content described in that embodiment (even part of the content), and / or the content described in one or more other embodiments (even part of the content). or another embodiment. Another figure (which may be a part) described in the embodiment, and / or one or more figures (which may be a part) described in another embodiment can be combined to constitute more figures. This also applies to the following embodiments. It is the same.

[0275] (Embodiment 5) In this embodiment, a display module and an electronic device having a semiconductor device according to one aspect of the present invention will be described with reference to FIGS. 24 and 25.

[0276] The display module 8000 shown in FIG. 24 includes a touch panel 8004 connected to an FPC 8003, a display panel 8006 connected to an FPC 8005, a backlight 8007, a frame 8009, a printed circuit board 8010 , and a battery 8011 between an upper cover 8001 and a lower cover 8002.

[0277] A semiconductor device or a display device according to one aspect of the present invention can be used, for example, for the display panel 8006.

[0278] The upper cover 8001 and the lower cover 8002 can be appropriately changed in shape and dimensions according to the sizes of the touch panel 8004 and the display panel 8 006.

[0279] The touch panel 8004 can be used by superimposing a resistive film type or a capacitive type touch panel on the display panel 8 006. Also, it is possible to provide a touch panel function on the counter substrate (sealing substrate ) of the display panel 8006. Further, it is possible to provide an optical sensor in each pixel of the display panel 80 06 to form an optical touch panel.

[0280] The backlight 8007 has a light source 8008. In FIG. Although the configuration in which the light source 8008 is disposed on the 8007 has been illustrated, the present invention is not limited to this. For example, a light source 8008 is arranged at the end of a backlight 8007, and a light diffusion plate is further used. In addition, when a self-luminous light-emitting element such as an organic EL element is used, or when a reflective In the case of a panel or the like, the backlight 8007 need not be provided.

[0281] The frame 8009 protects the display panel 8006 and also prevents the operation of the printed circuit board 8010. It also functions as an electromagnetic shield to block electromagnetic waves generated by the frame. The plate 8009 may function as a heat sink.

[0282] The printed circuit board 8010 includes a power supply circuit, a signal circuit for outputting a video signal, and a clock signal. The power supply circuit is supplied with power from an external commercial power source. Alternatively, the power source may be a battery 8011 provided separately. This can be omitted if a commercial power source is used.

[0283] In addition, the display module 8000 includes additional components such as a polarizing plate, a retardation plate, and a prism sheet. It may also be provided as such.

[0284] 25(A) to 25(G) are diagrams showing electronic devices. These electronic devices are 9000, display unit 9001, speaker 9003, operation keys 9005 (power switch, or Including operation switches), connection terminal 9006, sensor 9007 (force, displacement, position, speed, acceleration Speed, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field , current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays (including those having a function of measuring them), and can have a microphone 9008, etc.

[0285] The electronic devices shown in FIGS. 25(A) to 25(G) can have various functions. For example, a function of displaying various information (such as still images, moving images, text images, etc.) on a display unit, a touch panel function, a function of displaying a calendar, date or time, etc., a function of controlling processing by various software (programs), a wireless communication function, a function of connecting to various computer networks using the wireless communication function, a function of transmitting or receiving various data using the wireless communication function, a function of reading a program or data recorded on a recording medium and displaying it on the display unit, etc. can be provided. Note that the functions that the electronic devices shown in FIGS. 25(A) to 25(G) can have are not limited to these, and they can have various functions. Also, although not shown in FIGS. 25(A) to 25(G), the electronic device may have a configuration having a plurality of display units. Further, a camera or the like may be provided in the electronic device, and it may have a function of taking a still image, a function of taking a moving image, a function of storing the taken image in a recording medium (external or built-in to the camera), a function of displaying the taken image on the display unit, etc.

[0286] The details of the electronic devices shown in FIGS. 25(A) to 25(G) will be described below.

[0287] FIG. 25(A) is a perspective view showing a portable information terminal 9100. The portable information terminal 9100 has The display unit 9001 is flexible. Therefore, the display unit 9001 can be moved along the curved surface of the curved housing 9000. The display unit 9001 can be incorporated in the display unit 9001. The device can be operated by touching the screen with a finger or a stylus. For example, You can start an application by touching the icon displayed on the screen 9001. Cut.

[0288] FIG. 25B is a perspective view showing a portable information terminal 9101. The portable information terminal 9101 is For example, the device has one or more functions selected from a telephone, a notebook, an information viewing device, etc. In practice, the mobile information terminal 9101 can be used as a smartphone. Although the peaker 9003, the connection terminal 9006, the sensor 9007, etc. are omitted in the figure, The portable information terminal 9100 shown in FIG. 5(A) can be installed in the same position. The information terminal 9101 can display text and image information on multiple sides. The four operation buttons 9050 (also called operation icons or simply icons) are provided on the display unit 9001. In addition, information 9051 indicated by a dashed rectangle can be displayed on one surface of the display unit 900. 1. An example of the information 9051 is an e-mail or Displays to notify you of incoming calls and SNS (social networking services), Subject of email or SNS, sender name of email or SNS, date and time, time, The remaining battery level, antenna reception strength, etc. Or, the information 9051 is displayed. In place of the information 9051, operation buttons 9050 or the like may be displayed.

[0289] FIG. 25(C) is a perspective view showing a portable information terminal 9102. The portable information terminal 9102 has a function of displaying information on three or more sides of a display unit 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are respectively displayed on different sides. For example, a user of the portable information terminal 9102 can check the display (here, information 9053) in a state where the portable information terminal 9102 is stored in the breast pocket of a suit. Specifically, the phone number or name of the caller of an incoming call is displayed at a position where it can be observed from above the portable information terminal 9102. The user can check the display without taking the portable information terminal 9102 out of the pocket and determine whether to answer the call. It has a function of displaying information on three or more sides of the display unit 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are respectively displayed on different sides. For example, a user of the portable information terminal 9102 can check the display (here, information 9053) in a state where the portable information terminal 9102 is stored in the breast pocket of a suit. Specifically, the phone number or name of the caller of an incoming call is displayed at a position where it can be observed from above the portable information terminal 9102. The user can check the display without taking the portable information terminal 9102 out of the pocket and determine whether to answer the call. It has a function of displaying information on three or more sides of the display unit 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are respectively displayed on different sides. For example, a user of the portable information terminal 9102 can check the display (here, information 9053) in a state where the portable information terminal 9102 is stored in the breast pocket of a suit. Specifically, the phone number or name of the caller of an incoming call is displayed at a position where it can be observed from above the portable information terminal 9102. The user can check the display without taking the portable information terminal 9102 out of the pocket and determine whether to answer the call. Specifically, the phone number or name of the caller of an incoming call is displayed at a position where it can be observed from above the portable information terminal 9102. The user can check the display without taking the portable information terminal 9102 out of the pocket and determine whether to answer the call. Specifically, the phone number or name of the caller of an incoming call is displayed at a position where it can be observed from above the portable information terminal 9102. The user can check the display without taking the portable information terminal 9102 out of the pocket and determine whether to answer the call. Specifically, the phone number or name of the caller of an incoming call is displayed at a position where it can be observed from above the portable information terminal 9102. The user can check the display without taking the portable information terminal 9102 out of the pocket and determine whether to answer the call.

[0290] FIG. 25(D) is a perspective view showing a wristwatch-type portable information terminal 9200. The portable information terminal 9200 can execute various applications such as a mobile phone, e-mail, text viewing and creation, music playback, Internet communication, and computer games. Also, the display unit 9001 is provided with a curved display surface, and display can be performed along the curved display surface. Also, the portable information terminal 9200 can execute communication-standard short-range wireless communication. For example, by communicating with a wireless headset, hands-free calling can also be performed. Also, the portable information terminal 9200 has a connection terminal 9006 and can directly exchange data with other information terminals via a connector. Also, charging can be performed via the connection terminal 9006. Note that the charging operation may be performed by wireless power supply without passing through the connection terminal 9006. The portable information terminal 9200 can execute various applications such as a mobile phone, e-mail, text viewing and creation, music playback, Internet communication, and computer games. Also, the display unit 9001 is provided with a curved display surface, and display can be performed along the curved display surface. Also, the portable information terminal 9200 can execute communication-standard short-range wireless communication. For example, by communicating with a wireless headset, hands-free calling can also be performed. Also, the portable information terminal 9200 has a connection terminal 9006 and can directly exchange data with other information terminals via a connector. Also, charging can be performed via the connection terminal 9006. Note that the charging operation may be performed by wireless power supply without passing through the connection terminal 9006. The portable information terminal 9200 can execute various applications such as a mobile phone, e-mail, text viewing and creation, music playback, Internet communication, and computer games. Also, the display unit 9001 is provided with a curved display surface, and display can be performed along the curved display surface. Also, the portable information terminal 9200 can execute communication-standard short-range wireless communication. For example, by communicating with a wireless headset, hands-free calling can also be performed. Also, the portable information terminal 9200 has a connection terminal 9006 and can directly exchange data with other information terminals via a connector. Also, charging can be performed via the connection terminal 9006. Note that the charging operation may be performed by wireless power supply without passing through the connection terminal 9006. The portable information terminal 9200 can execute various applications such as a mobile phone, e-mail, text viewing and creation, music playback, Internet communication, and computer games. Also, the display unit 9001 is provided with a curved display surface, and display can be performed along the curved display surface. Also, the portable information terminal 9200 can execute communication-standard short-range wireless communication. For example, by communicating with a wireless headset, hands-free calling can also be performed. Also, the portable information terminal 9200 has a connection terminal 9006 and can directly exchange data with other information terminals via a connector. Also, charging can be performed via the connection terminal 9006. Note that the charging operation may be performed by wireless power supply without passing through the connection terminal 9006. Also, charging can be performed via the connection terminal 9006. Note that the charging operation may be performed by wireless power supply without passing through the connection terminal 9006. Also, charging can be performed via the connection terminal 9006. Note that the charging operation may be performed by wireless power supply without passing through the connection terminal 9006.

[0291] FIG. 25(E)(F)(G) is a perspective view showing the foldable mobile information terminal 9201. . Further, FIG. 25(E) is a perspective view of the mobile information terminal 9201 in an unfolded state, and FIG. 25( F) is a perspective view of the mobile information terminal 9201 in a state of changing from one of the unfolded state or the folded state to the other, and FIG. 25(G) is a perspective view of the mobile information terminal 9201 in a folded state. The mobile information terminal 9201 has excellent portability in the folded state and excellent display listability due to a seamless wide display area in the unfolded state. The display unit 9001 of the mobile information terminal 920 1 is supported by three housings 9000 connected by a hinge 9055. By bending between the two housings 9000 via the hinge 9055, the mobile information terminal 9201 can be reversibly deformed from the unfolded state to the folded state. For example, the mobile information terminal 9201 can be bent with a radius of curvature of 1 mm or more and 150 mm or less.

[0292] The electronic device described in this embodiment has a display unit for displaying some information. However, the semiconductor device according to one aspect of the present invention can also be applied to an electronic device having no display unit. In addition, in the display unit of the electronic device described in this embodiment, a configuration having flexibility and capable of performing display along a curved display surface, or a configuration of a foldable display unit has been exemplified, but the present invention is not limited to this, and a configuration without flexibility and performing display on a flat surface may also be used.

[0293] The configuration shown in this embodiment can be appropriately combined with the configuration shown in other embodiments and used.

Description of Reference Numerals

[0294] CK1 signal CK2 signal CK3 signal ND1 node ND2 node ND3 node OUT signal SP signal T0 period T1 period T2 period T3 period T4 period 100 circuit 101 transistor 102 transistor 103 transistor 104 transistor 105 capacitor 106 capacitor 107 transistor 108 transistor 109 transistor 110 transistor 101p transistor 102p transistor 103p transistor 104p transistor 111 wiring 112 wiring 113 wiring 114 wiring 115 wiring 115B wiring 115C wiring 116 wiring 117 wiring 121 transistor 122 transistor 123 transistor 124 transistor 200 circuit 201 circuit 211 wiring 212 wiring 213 wiring 214 wiring 215 wiring 216 Wiring 301 Pixel Section 302 Scanning Line Driving Circuit 303 Signal Line Driving Circuit 304 Circuit 310 Pixel 401A Conductive Layer 401A1 Opening 401A2 Opening 401B Conductive Layer 401B1 Opening 401C Conductive Layer 401D Conductive Layer 402A Semiconductor Layer 402B Semiconductor Layer 402C Semiconductor Layer 402D Semiconductor Layer 403A Conductive Layer 403A1 Region 403A2 Region 403B Conductive Layer 403B1 Region 403B2 Region 403B3 Opening 403B4 Opening 403C Conductive Layer 403C1 Region 403C2 Region 403D Conductive Layer 403D1 Region 403D2 Region 403D3 Opening 403E Conductive Layer 403F Conductive Layer 403G Conductive Layer 403H Conductive Layer 403I Conductive Layer 404 Insulating Layer 404A1 Opening 8000 Display Module 8001 Upper Cover 8002 Lower Cover 8003 FPC 8004 Touch Panel 8005 FPC 8006 Display Panel 8007 Backlight 8008 Light source 8009 Frame 8010 Printed circuit board 8011 Battery 9000 Housing 9001 Display unit 9003 Speaker 9005 Operation key 9006 Connection terminal 9007 Sensor 9008 Microphone 9050 Operation button 9051 Information 9052 Information 9053 Information 9054 Information 9055 Hinge 9100 Portable information terminal 9101 Portable information terminal 9102 Portable information terminal 9200 Portable information terminal 9201 Portable information terminal

Claims

1. Having the first to third transistors, One of the source electrode or the drain electrode of the first transistor is electrically connected to a first wiring from which a signal is output, One of the source electrode or the drain electrode of the second transistor is electrically connected to a scanning line, The other of the source electrode or the drain electrode of the second transistor is electrically connected to the gate of the first transistor, One of the source electrode or the drain electrode of the third transistor is electrically connected to a clock signal line, The other of the source electrode or the drain electrode of the third transistor is electrically connected to the gate of the second transistor, The gate of the third transistor is electrically connected to a second wiring to which a high-level potential is input, In a plan view, a semiconductor device having a region where a first conductive layer having a function as the other of the source electrode or the drain electrode of the second transistor overlaps with a second conductive layer having a function as the gate electrode of the second transistor in a region that does not overlap with a semiconductor layer having a function as the channel formation region of the second transistor.

2. Having the first to third transistors, One of the source electrode or the drain electrode of the first transistor is electrically connected to a first wiring from which a signal is output, One of the source electrode or the drain electrode of the second transistor is electrically connected to a scanning line, The other of the source electrode or the drain electrode of the second transistor is electrically connected to the gate of the first transistor, One of the source electrode or the drain electrode of the third transistor is electrically connected to a clock signal line, The other of the source electrode or the drain electrode of the third transistor is electrically connected to the gate of the second transistor, The gate of the third transistor is electrically connected to a second wiring to which a high-level potential is input, In a plan view, a first conductive layer having a function as the other of the source electrode or the drain electrode of the second transistor has a region that overlaps with a second conductive layer having a function as the gate electrode of the second transistor in a region that does not overlap with a semiconductor layer having a function as the channel formation region of the second transistor, A semiconductor device in which the area of a third conductive layer having a function as a gate electrode of the first transistor is larger than the area of the second conductive layer.

3. Having first to third transistors, One of the source electrode or the drain electrode of the first transistor is electrically connected to a first wiring to which a signal is output, One of the source electrode or the drain electrode of the second transistor is electrically connected to a scanning line, The other of the source electrode or the drain electrode of the second transistor is electrically connected to the gate of the first transistor, One of the source electrode or the drain electrode of the third transistor is electrically connected to a clock signal line, The other of the source electrode or the drain electrode of the third transistor is electrically connected to the gate of the second transistor, The gate of the third transistor is electrically connected to a second wiring to which a high-level potential is input, In a plan view, a first conductive layer having a function as the other of the source electrode or the drain electrode of the second transistor has a region overlapping with a second conductive layer having a function as a gate electrode of the second transistor in a region not overlapping with a semiconductor layer having a function as a channel formation region of the second transistor. A semiconductor device in which the first conductive layer has a region in contact with a third conductive layer having a function as a gate electrode of the first transistor.

4. Having first to third transistors, One of the source electrode or the drain electrode of the first transistor is electrically connected to a first wiring to which a signal is output, One of the source electrode or the drain electrode of the second transistor is electrically connected to a scanning line, The other of the source electrode or the drain electrode of the second transistor is electrically connected to the gate of the first transistor, One of the source electrode or the drain electrode of the third transistor is electrically connected to a clock signal line, The other of the source electrode or the drain electrode of the third transistor is electrically connected to the gate of the second transistor, The gate of the third transistor is electrically connected to a second wiring to which a high-level potential is input, In a plan view, a first conductive layer having a function as the other of the source electrode or the drain electrode of the second transistor has a region overlapping with a second conductive layer having a function as a gate electrode of the second transistor in a region not overlapping with a semiconductor layer having a function as a channel formation region of the second transistor. A semiconductor device in which, in a plan view, a channel length direction of the first transistor and a channel length direction of the third transistor intersect each other. **Claim 5**: Having first to third transistors, One of the source electrode or the drain electrode of the first transistor is electrically connected to a first wiring to which a signal is output. One of the source electrode or the drain electrode of the second transistor is electrically connected to a scanning line. The other of the source electrode or the drain electrode of the second transistor is electrically connected to the gate of the first transistor. One of the source electrode or the drain electrode of the third transistor is electrically connected to a clock signal line. The other of the source electrode or the drain electrode of the third transistor is electrically connected to the gate of the second transistor. The gate of the third transistor is electrically connected to a second wiring to which a high-level potential is input. In a plan view, a first conductive layer having a function as the other of the source electrode or the drain electrode of the second transistor has a region overlapping with a second conductive layer having a function as a gate electrode of the second transistor in a region not overlapping with a semiconductor layer having a function as a channel formation region of the second transistor. The area of a third conductive layer having a function as a gate electrode of the first transistor is larger than the area of the second conductive layer. The semiconductor device in which the first conductive layer has a region in contact with the third conductive layer. **Claim 6**: Having first to third transistors, One of the source electrode or the drain electrode of the first transistor is electrically connected to a first wiring to which a signal is output. One of the source electrode or the drain electrode of the second transistor is electrically connected to a scanning line. The other of the source electrode or the drain electrode of the second transistor is electrically connected to the gate of the first transistor. One of the source electrode or the drain electrode of the third transistor is electrically connected to a clock signal line. The other of the source electrode or the drain electrode of the third transistor is electrically connected to the gate of the second transistor. The gate of the third transistor is electrically connected to a second wiring to which a high-level potential is input. In a plan view, a first conductive layer having a function as the other of the source electrode or the drain electrode of the second transistor has a region overlapping with a second conductive layer having a function as the gate electrode of the second transistor in a region not overlapping with a semiconductor layer having a function as the channel formation region of the second transistor. The area of the third conductive layer having a function as the gate electrode of the first transistor is larger than the area of the second conductive layer. A semiconductor device in which, in a plan view, the channel length direction of the first transistor and the channel length direction of the third transistor intersect each other.

7. Having first to third transistors. One of the source electrode or the drain electrode of the first transistor is electrically connected to a first wiring from which a signal is output. One of the source electrode or the drain electrode of the second transistor is electrically connected to a scanning line. The other of the source electrode or the drain electrode of the second transistor is electrically connected to the gate of the first transistor. One of the source electrode or the drain electrode of the third transistor is electrically connected to a clock signal line. The other of the source electrode or the drain electrode of the third transistor is electrically connected to the gate of the second transistor. The gate of the third transistor is electrically connected to a second wiring to which a high-level potential is input. In a plan view, a first conductive layer having a function as the other of the source electrode or the drain electrode of the second transistor has a region overlapping with a second conductive layer having a function as the gate electrode of the second transistor in a region not overlapping with a semiconductor layer having a function as the channel formation region of the second transistor. The first conductive layer has a region in contact with a third conductive layer having a function as the gate electrode of the first transistor. A semiconductor device in which, in a plan view, the channel length direction of the first transistor and the channel length direction of the third transistor intersect each other.

8. Having first to third transistors. One of the source electrode or the drain electrode of the first transistor is electrically connected to a first wiring from which a signal is output. One of the source electrode or the drain electrode of the second transistor is electrically connected to a scanning line. The other of the source electrode or the drain electrode of the second transistor is electrically connected to the gate of the first transistor. One of the source electrode or the drain electrode of the third transistor is electrically connected to a clock signal line. The other of the source electrode or the drain electrode of the third transistor is electrically connected to the gate of the second transistor. The gate of the third transistor is electrically connected to a second wiring to which a high-level potential is input. In a plan view, a first conductive layer having a function as the other of the source electrode or the drain electrode of the second transistor has a region overlapping with a second conductive layer having a function as the gate electrode of the second transistor in a region not overlapping with a semiconductor layer having a function as the channel formation region of the second transistor. The area of a third conductive layer having a function as the gate electrode of the first transistor is larger than the area of the second conductive layer. The first conductive layer has a region in contact with the third conductive layer. A semiconductor device in which, in a plan view, the channel length direction of the first transistor and the channel length direction of the third transistor are in directions intersecting with each other. **Claim 9**: A scanning line driving circuit and a pixel formed on the same substrate as the scanning line driving circuit. The scanning line driving circuit includes first to third transistors. One of the source electrode or the drain electrode of the first transistor is electrically connected to a first wiring from which a signal is output. One of the source electrode or the drain electrode of the second transistor is electrically connected to a scanning line. The other of the source electrode or the drain electrode of the second transistor is electrically connected to the gate of the first transistor. One of the source electrode or the drain electrode of the third transistor is electrically connected to a clock signal line. The other of the source electrode or the drain electrode of the third transistor is electrically connected to the gate of the second transistor. The gate of the third transistor is electrically connected to a second wiring to which a high-level potential is input. In a plan view, a first conductive layer having a function as the other of the source electrode or the drain electrode of the second transistor has a region overlapping with a second conductive layer having a function as the gate electrode of the second transistor in a region not overlapping with a semiconductor layer having a function as the channel formation region of the second transistor. The pixel has a fourth transistor. The fourth transistor has an oxide semiconductor in a channel formation region in a display device. **Claim 10**: A scanning line driving circuit and a pixel formed on the same substrate as the scanning line driving circuit. The scanning line driving circuit has first to third transistors. One of the source electrode or the drain electrode of the first transistor is electrically connected to a first wiring from which a signal is output. One of the source electrode or the drain electrode of the second transistor is electrically connected to a scanning line. The other of the source electrode or the drain electrode of the second transistor is electrically connected to the gate of the first transistor. One of the source electrode or the drain electrode of the third transistor is electrically connected to a clock signal line. The other of the source electrode or the drain electrode of the third transistor is electrically connected to the gate of the second transistor. The gate of the third transistor is electrically connected to a second wiring to which a high-level potential is input. In a plan view, a first conductive layer having a function as the other of the source electrode or the drain electrode of the second transistor has a region overlapping with a second conductive layer having a function as the gate electrode of the second transistor in a region not overlapping with a semiconductor layer having a function as the channel formation region of the second transistor. The area of a third conductive layer having a function as the gate electrode of the first transistor is larger than the area of the second conductive layer. The pixel has a fourth transistor. The fourth transistor has an oxide semiconductor in a channel formation region in a display device. **Claim 11**: A scanning line driving circuit and a pixel formed on the same substrate as the scanning line driving circuit. The scanning line driving circuit has first to third transistors. One of the source electrode or the drain electrode of the first transistor is electrically connected to a first wiring from which a signal is output. One of the source electrode or the drain electrode of the second transistor is electrically connected to the scanning line. The other of the source electrode or the drain electrode of the second transistor is electrically connected to the gate of the first transistor. One of the source electrode or the drain electrode of the third transistor is electrically connected to the clock signal line. The other of the source electrode or the drain electrode of the third transistor is electrically connected to the gate of the second transistor. The gate of the third transistor is electrically connected to a second wiring to which a high-level potential is input. In a plan view, the first conductive layer having a function as the other of the source electrode or the drain electrode of the second transistor has a region overlapping with the second conductive layer having a function as the gate electrode of the second transistor in a region not overlapping with the semiconductor layer having a function as the channel formation region of the second transistor. The first conductive layer has a region in contact with the third conductive layer having a function as the gate electrode of the first transistor. The pixel has a fourth transistor. The fourth transistor has an oxide semiconductor in a channel formation region.

12. A scanning line driving circuit and a pixel formed on the same substrate as the scanning line driving circuit. The scanning line driving circuit has first to third transistors. One of the source electrode or the drain electrode of the first transistor is electrically connected to a first wiring from which a signal is output. One of the source electrode or the drain electrode of the second transistor is electrically connected to the scanning line. The other of the source electrode or the drain electrode of the second transistor is electrically connected to the gate of the first transistor. One of the source electrode or the drain electrode of the third transistor is electrically connected to the clock signal line. The other of the source electrode or the drain electrode of the third transistor is electrically connected to the gate of the second transistor. The gate of the third transistor is electrically connected to a second wiring to which a high-level potential is input. In plan view, the first conductive layer having a function as the other of the source electrode or the drain electrode of the second transistor has a region overlapping with the second conductive layer having a function as the gate electrode of the second transistor in a region not overlapping with the semiconductor layer having a function as the channel formation region of the second transistor. In plan view, the channel length direction of the first transistor and the channel length direction of the third transistor are directions intersecting with each other. The pixel has a fourth transistor. The fourth transistor is a display device having an oxide semiconductor in a channel formation region. **Claim 13**: A scanning line driving circuit and a pixel formed on the same substrate as the scanning line driving circuit. The scanning line driving circuit has first to third transistors. One of the source electrode or the drain electrode of the first transistor is electrically connected to a first wiring to which a signal is output. One of the source electrode or the drain electrode of the second transistor is electrically connected to a scanning line. The other of the source electrode or the drain electrode of the second transistor is electrically connected to the gate of the first transistor. One of the source electrode or the drain electrode of the third transistor is electrically connected to a clock signal line. The other of the source electrode or the drain electrode of the third transistor is electrically connected to the gate of the second transistor. The gate of the third transistor is electrically connected to a second wiring to which a high-level potential is input. In plan view, the first conductive layer having a function as the other of the source electrode or the drain electrode of the second transistor has a region overlapping with the second conductive layer having a function as the gate electrode of the second transistor in a region not overlapping with the semiconductor layer having a function as the channel formation region of the second transistor. The area of the third conductive layer having a function as the gate electrode of the first transistor is larger than the area of the second conductive layer. The first conductive layer has a region in contact with the third conductive layer. The pixel has a fourth transistor. The fourth transistor is a display device having an oxide semiconductor in a channel formation region. **Claim 14**: A scanning line driving circuit and a pixel formed on the same substrate as the scanning line driving circuit. The scanning line driving circuit has first to third transistors. One of the source electrode or the drain electrode of the first transistor is electrically connected to a first wiring through which a signal is output. One of the source electrode or the drain electrode of the second transistor is electrically connected to a scanning line. The other of the source electrode or the drain electrode of the second transistor is electrically connected to the gate of the first transistor. One of the source electrode or the drain electrode of the third transistor is electrically connected to a clock signal line. The other of the source electrode or the drain electrode of the third transistor is electrically connected to the gate of the second transistor. The gate of the third transistor is electrically connected to a second wiring to which a high-level potential is input. In a plan view, a first conductive layer having a function as the other of the source electrode or the drain electrode of the second transistor has a region overlapping with a second conductive layer having a function as the gate electrode of the second transistor in a region not overlapping with a semiconductor layer having a function as the channel formation region of the second transistor. The area of the third conductive layer having a function as the gate electrode of the first transistor is larger than the area of the second conductive layer. In a plan view, the channel length direction of the first transistor and the channel length direction of the third transistor are in directions intersecting with each other. The pixel includes a fourth transistor. The fourth transistor has an oxide semiconductor in a channel formation region. A display device.

15. A scanning line driving circuit and a pixel formed on the same substrate as the scanning line driving circuit. The scanning line driving circuit includes first to third transistors. One of the source electrode or the drain electrode of the first transistor is electrically connected to a first wiring through which a signal is output. One of the source electrode or the drain electrode of the second transistor is electrically connected to a scanning line. The other of the source electrode or the drain electrode of the second transistor is electrically connected to the gate of the first transistor. One of the source electrode or the drain electrode of the third transistor is electrically connected to a clock signal line. The other of the source electrode or the drain electrode of the third transistor is electrically connected to the gate of the second transistor. The gate of the third transistor is electrically connected to a second wiring to which a high-level potential is input. In plan view, the first conductive layer having a function as the other of the source electrode or the drain electrode of the second transistor has a region overlapping with the second conductive layer having a function as the gate electrode of the second transistor in a region not overlapping with the semiconductor layer having a function as the channel formation region of the second transistor. The first conductive layer has a region in contact with a third conductive layer having a function as the gate electrode of the first transistor. In plan view, the channel length direction of the first transistor and the channel length direction of the third transistor are directions intersecting with each other. The pixel has a fourth transistor. The fourth transistor has an oxide semiconductor in a channel formation region, and is a display device. **Claim 16**: A scanning line driving circuit and a pixel formed on the same substrate as the scanning line driving circuit. The scanning line driving circuit has first to third transistors. One of the source electrode or the drain electrode of the first transistor is electrically connected to a first wiring to which a signal is output. One of the source electrode or the drain electrode of the second transistor is electrically connected to a scanning line. The other of the source electrode or the drain electrode of the second transistor is electrically connected to the gate of the first transistor. One of the source electrode or the drain electrode of the third transistor is electrically connected to a clock signal line. The other of the source electrode or the drain electrode of the third transistor is electrically connected to the gate of the second transistor. The gate of the third transistor is electrically connected to a second wiring to which a high-level potential is input. In plan view, the first conductive layer having a function as the other of the source electrode or the drain electrode of the second transistor has a region overlapping with the second conductive layer having a function as the gate electrode of the second transistor in a region not overlapping with the semiconductor layer having a function as the channel formation region of the second transistor. The area of the third conductive layer having a function as the gate electrode of the first transistor is larger than the area of the second conductive layer. The first conductive layer has a region in contact with the third conductive layer. In plan view, the channel length direction of the first transistor and the channel length direction of the third transistor are directions intersecting with each other. The pixel has a fourth transistor, and the fourth transistor is a display device having an oxide semiconductor in a channel formation region.

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