Light emitting device, display device, photoelectric conversion device, electronic apparatus, illumination device, wearable device, and image forming apparatus

Abstract

To provide a technique advantageous for preventing a luminous element from unintentionally entering a light emission state due to leakage current flowing from a drive transistor to the luminous element.SOLUTION: A light emitting device has a plurality of pixels arranged on a substrate. Each pixel includes a luminous element, a drive transistor supplying current to the luminous element, and a writing transistor supplying signal voltage to a gate of the drive transistor. The drive transistor has an offset structure having an insulator between the gate and a semiconductor region forming a source or a drain, on an orthogonal projection on a principal surface of the substrate.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present invention relates to a light-emitting device, a display device, a photoelectric conversion device, an electronic device, a lighting device, a wearable device, and an image forming device.

Background Art

[0002] Patent Document 1 describes a light-emitting device in which each pixel includes a light-emitting element, a driving transistor for supplying a current corresponding to a luminance signal to the light-emitting element, and a light-emitting control transistor for controlling light emission or non-light emission of the light-emitting element. The light-emitting control transistor is disposed between the light-emitting element and the driving transistor and has a drain offset structure.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] When the electric field in the semiconductor region constituting the source or drain of the driving transistor is large, for example, the leakage current flowing between the source and the drain is accelerated and increased by the electric field, so that the current flowing into the light-emitting element may increase. This can cause the light-emitting element to emit light unintentionally.

[0005] An object of the present invention is to provide an advantageous technique for suppressing the light-emitting element from being unintentionally brought into a light-emitting state due to a leakage current flowing from the driving transistor into the light-emitting element.

Means for Solving the Problems

[0006] One aspect of the present invention relates to a light-emitting device having a plurality of pixels disposed on a substrate. Each pixel includes a light-emitting element, a driving transistor that supplies current to the light-emitting element, and a writing transistor that supplies a signal voltage to the gate of the driving transistor. The driving transistor has an offset structure having an insulator between a semiconductor region constituting a source or a drain and the gate in a front projection onto the main surface of the substrate.

Advantages of the Invention

[0007] According to the present invention, a technique advantageous for suppressing the unintentional emission of a light-emitting element due to a leakage current flowing from a driving transistor into the light-emitting element is provided.

Brief Description of the Drawings

[0008]

Figure 1

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Figure 16

Mode for Carrying Out the Invention

[0009] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the invention according to the claims. Although a plurality of features are described in the embodiments, not all of these plurality of features are essential to the invention, and the plurality of features may be arbitrarily combined. Further, in the accompanying drawings, the same or similar configurations are denoted by the same reference numerals, and redundant descriptions are omitted.

[0010] In this specification, the terms "first conductivity type" and "second conductivity type" may be used to distinguish between P-type and N-type. When the first conductivity type is P-type, the second conductivity type is N-type. On the other hand, when the first conductivity type is N-type, the second conductivity type is P-type.

[0011] The light-emitting device of this embodiment has a plurality of pixels arranged on a substrate, and each pixel may include a light-emitting element, a driving transistor that supplies current to the light-emitting element, and a writing transistor that supplies a signal voltage to the gate electrode of the driving transistor. The driving transistor and the writing transistor may be P-type transistors or N-type transistors. Hereinafter, for the purpose of presenting a more specific example, for convenience, an example in which the driving transistor and the writing transistor are composed of P-type transistors will be described. However, the driving transistor may be composed of a P-type transistor and the writing transistor may be composed of an N-type transistor, or the driving transistor may be composed of an N-type transistor and the writing transistor may be composed of a P-type transistor. Each pixel of the light-emitting device may further include other transistors such as a reset transistor, and the reset transistor may be a P-type transistor or an N-type transistor. The circuit configuration of the pixel can be appropriately changed according to the conductivity type of the transistors constituting it. The light-emitting element may be an organic light-emitting element, but may be, for example, a light-emitting element having a light-emitting layer made of an inorganic material.

[0012] Hereinafter, the light-emitting device 101 of the first embodiment will be described with reference to FIGS. 1, 2, 3, and 4. FIG. 1 shows the configuration of the light-emitting device 101 of the first embodiment. The light-emitting device 101 can be configured as, for example, an organic light-emitting device. The light-emitting device 101 may include a pixel array 103. The pixel array 103 may include a plurality of pixels 102. The plurality of pixels 102 can be arranged on the substrate. The plurality of pixels 102 can be arranged, for example, to form a plurality of rows and a plurality of columns. Each light-emitting element 201 may include an anode, an organic layer including a light-emitting layer, and a cathode. The organic layer may include a hole injection layer, a hole transport layer, an electron injection layer, and an electron transport layer in addition to the light-emitting layer. The pixel array 103 may include a plurality of scanning lines 106 extending along the rows and a plurality of signal lines 107 extending along the columns.

[0013] The light-emitting device 101 may include a driving circuit 110 that drives the pixel array 103. The driving circuit 110 may include a vertical scanning circuit 104 that drives a plurality of scanning lines 106 so as to control writing of a signal voltage (luminance signal) to the pixels 102 in each row, and a signal output circuit 105 that drives a plurality of signal lines 107 so as to supply a luminance signal to the pixels 102 in each column.

[0014] FIG. 2 illustrates an equivalent circuit showing the configuration of one pixel 102. The pixel 102 may include a light-emitting element 201, a driving transistor 202 that drives the light-emitting element 201, and a writing transistor 203 that supplies a signal voltage to the gate electrode of the driving transistor 202. One of the source and drain of the driving transistor 202 (the drain in this example) may be connected to the first electrode (the anode in this example) of the two electrodes of the light-emitting element 201. Also, the other of the source and drain of the driving transistor 202 (the source in this example) may be connected to the first power supply terminal 204 (hereinafter, Vdd). The second electrode (the cathode in this example) of the light-emitting element 201 may be connected to the second power supply terminal 205 (hereinafter, Vss). One of the source and drain of the writing transistor 203 is connected to the gate of the driving transistor 202, and the other of the source and drain of the writing transistor 203 is connected to the signal line 107. The gate of the writing transistor 203 is connected to the scanning line 106.

[0015] FIGS. 3 and 4 are a plan view and a cross-sectional view, respectively, schematically showing the configurations of the driving transistor 202 and the writing transistor 203 among the pixels 102 shown in FIG. 2. FIG. 4 shows a cross-section taken along A-A' in FIG. 3. The pixel 102 is disposed on a substrate SUB. The surface of the substrate SUB on which the driving transistor 202 is disposed (the surface in contact with the gate insulating film of the driving transistor 202) among the two widest surfaces of the substrate SUB is referred to as the main surface PS.

[0016] The driving transistor 202 is a MOS transistor having a gate 301, a source 302, and a drain 303. The gate 301 can be disposed on the main surface PS via a gate insulating film. The driving transistor 202 can have an offset structure having an insulator INSD between a semiconductor region constituting the source 302 or the drain 303 and the gate 301 in a front projection (plan view) with respect to the main surface PS of the substrate SUB. In the examples of FIGS. 3 and 4, the driving transistor 202 has an offset structure having an insulator INSD between the semiconductor region constituting the drain 303 and the gate 301 in a front projection with respect to the main surface PS of the substrate SUB. Such an offset structure can also be called a drain offset structure. The insulator INSD can be, for example, STI (Shallow Trench Isolation) or LOCOS (Local Oxidation Of Silicon). The writing transistor 203 is a MOS transistor having a gate 304, a source 305, and a drain 306. Via plugs 307 can be connected to the sources 302, 305 and the drains 303, 306. The light-emitting element 201 is disposed above the via plug 307, but in FIG. 4, the light-emitting element 201 is omitted.

[0017] In one example, the source 302 of the driving transistor 202 can be composed of a first semiconductor region of a first conductivity type (P-type in this example), and the drain 303 of the driving transistor 202 can be composed of a second semiconductor region of the first conductivity type. Further, in the current path from the first semiconductor region of the first conductivity type constituting the source 302 to the second semiconductor region of the first conductivity type constituting the drain 303, a third semiconductor region 401 of a second conductivity type (N-type in this example) and a fourth semiconductor region 402 of the first conductivity type can be sequentially disposed. The net impurity concentration of the first conductivity type in the fourth semiconductor region 402 is lower than the net impurity concentration of the first conductivity type in the second semiconductor region constituting the drain 303.

[0018] The fourth semiconductor region 402 of the first conductivity type is arranged to bypass the insulator INSD, and the insulator INSD functions as an offset portion 403 that offsets the drain 303. In one example, the depth of the bottom surface of the insulator INSD with respect to the main surface PS (the distance from the main surface PS to the bottom surface of the insulator INSD) is greater than the depth of the bottom surface of the drain 303 (the semiconductor region constituting the drain 303) with respect to the main surface PS.

[0019] The source 305 of the write transistor 203 is composed of a semiconductor region of the first conductivity type, and the drain 306 of the write transistor 203 may be composed of a semiconductor region of the first conductivity type. The substrate SUB may include, for example, a semiconductor layer 405 of the first conductivity type and a semiconductor layer 404 (well) of the second conductivity type disposed on the semiconductor layer 405. The sources 302, 305, drains 303, 306, and semiconductor regions 401, 402 of the drive transistor 202 and the write transistor 203 can be formed by implanting impurities into the semiconductor layer 404. The substrate SUB has a separation portion 406 for separating transistors such as the drive transistor 202 and the write transistor 203 from each other. The separation portion 406 can be, for example, STI separation, LOCOS separation, or separation by a diffusion layer of the second conductivity type.

[0020] According to the first embodiment, the electric field in the vicinity of the gate end on the drain side of the drive transistor 202 (the right end of the gate 301 in FIG. 4) can be reduced. Therefore, it is possible to suppress the leakage current flowing between the source and the drain or between the well and the drain from being accelerated and increased by the electric field in the vicinity of the gate end. This helps to prevent the light-emitting element 201 from being inadvertently turned on due to the leakage current flowing from the drive transistor 202 to the light-emitting element 201. Such an effect enables high-quality black display, for example, when the light-emitting device 101 is configured as a display device.

[0021] Next, the light-emitting device 101 of the second embodiment will be described with reference to FIGS. 5, 6, 7, and 8. Matters not mentioned as the second embodiment may follow the first embodiment. In the light-emitting device 101 of the second embodiment, each pixel 102 has a reset transistor 601 for resetting the light-emitting element 201. FIG. 5 shows the configuration of the light-emitting device 101 of the second embodiment. In the second embodiment, the pixel array 103 may include a plurality of first scanning lines 106 extending along rows, a plurality of second scanning lines 501 extending along rows, and a plurality of signal lines 107 extending along columns. The vertical scanning circuit 104 drives the plurality of first scanning lines 106 so as to control writing of a signal voltage (luminance signal) to the pixels 102 in each row, and drives the plurality of second scanning lines 501 so as to reset the light-emitting elements 201 of the pixels 102 in each row.

[0022] FIG. 6 illustrates an equivalent circuit showing the configuration of one pixel 102 in the second embodiment. The pixel 102 may include a reset transistor 601 that resets the light-emitting element 201, in addition to the light-emitting element 201, the driving transistor 202, and the writing transistor 203. One of the source and drain of the reset transistor 601 (the source in this example) may be connected to one of the source and drain of the driving transistor 202 (the drain in this example). The other of the source and drain of the reset transistor 601 may be connected to a third power supply terminal 602 (hereinafter, Vres). The gate of the reset transistor 601 is connected to the second scanning line 501. By activating the second scanning line 501, the reset transistor 601 is turned on, whereby the anode of the light-emitting element 201 is connected to Vres 602, and the luminance of the light-emitting element 201 is reset to the black level. This is advantageous, for example, for realizing a light-emitting device 101 with high contrast. On the other hand, when causing the light-emitting element 201 to emit light according to the luminance signal, the reset transistor 601 is turned off by deactivating the second scanning line 501. At this time, the gate of the reset transistor 601 has a high-level potential (for example, Vdd). On the other hand, since the potential of the anode of the light-emitting element 201 can be a potential lower than Vdd, an electric field is generated between the anode of the light-emitting element 201 and the gate of the reset transistor 601. If this electric field is large, the leakage current between the well and the source of the reset transistor 601 can be accelerated and increased. In the second embodiment, such an electric field is reduced.

[0023] Figs. 7 and 8 are a plan view and a cross-sectional view schematically showing the configurations of the driving transistor 202, the writing transistor 203, and the reset transistor 601 among the pixels 102 shown in Fig. 6, respectively. Fig. 8 shows a cross-section taken along B-B' in Fig. 7. The reset transistor 601 is a MOS transistor having a gate 701, a source 303, and a drain 702. In this example, the source 303 of the reset transistor 601 is common with the drain 303 of the driving transistor 202, but the source of the reset transistor 601 may be provided separately from the drain of the driving transistor 202. The reset transistor 601 may have an offset structure having an insulator INSR between the source 303 of the reset transistor 601 and the gate 701 of the reset transistor 601 in the orthographic projection onto the main surface PS of the substrate SUB. Such an offset structure may also be called a source offset structure. The insulator INSR may be, for example, STI or LOCOS.

[0024] In one example, the source 302 of the driving transistor 202 may be composed of a first semiconductor region of a first conductivity type, and the drain 303 (the source 303 of the reset transistor 601) of the driving transistor 202 may be composed of a second semiconductor region of the first conductivity type. In the current path from the first semiconductor region constituting the source 302 of the driving transistor 202 to the second semiconductor region constituting the drain 303 of the driving transistor 202, a third semiconductor region 401 of a second conductivity type and a fourth semiconductor region 402 of the first conductivity type may be arranged in this order. The net impurity concentration of the first conductivity type in the fourth semiconductor region 402 is lower than the net impurity concentration of the first conductivity type in the second semiconductor region constituting the drain 303 of the driving transistor 202. The fourth semiconductor region 402 of the first conductivity type is arranged so as to bypass the insulator INSD, and the insulator INSD functions as an offset portion 403 that offsets the drain 303 of the driving transistor 202. In one example, the depth of the bottom surface of the insulator INSD with respect to the main surface PS (the distance from the main surface PS to the bottom surface of the insulator INSD) is larger than the depth of the bottom surface of the drain 303 (the semiconductor region constituting it) with respect to the main surface PS.

[0025] In one example, the drain 702 of the reset transistor 601 may be formed of a fifth semiconductor region of a first conductivity type. In the current path from the second semiconductor region forming the source 303 of the reset transistor 601 to the fifth semiconductor region forming the drain 702 of the reset transistor 601, a fourth semiconductor region 402 of the first conductivity type and a sixth semiconductor region 801 of the second conductivity type may be arranged in this order. The net impurity concentration of the first conductivity type in the fourth semiconductor region 402 is lower than the net impurity concentration of the first conductivity type in the second semiconductor region forming the drain 303 (source 303 of the reset transistor 601) of the drive transistor 202. The fourth semiconductor region 402 of the first conductivity type is arranged so as to bypass the insulator INSR, and the insulator INSR functions as an offset portion 802 that offsets the source 303 of the reset transistor 601. In one example, the depth of the bottom surface of the insulator INSR with respect to the main surface PS (the distance from the main surface PS to the bottom surface of the insulator INSR) is greater than the depth of the bottom surface of the source 303 (the semiconductor region forming the same) with respect to the main surface PS.

[0026] According to the second embodiment, the electric field in the vicinity of the gate end on the source side of the reset transistor 601 (the left end of the gate 701 in FIG. 8) can be reduced, and the leakage current flowing between the well and the source can be suppressed. This helps to prevent the light-emitting element 201 from entering an unintended light-emitting state due to the leakage current flowing from the reset transistor 601 to the light-emitting element 201. Such an effect enables high-quality black display, for example, when the light-emitting device 101 is configured as a display device.

[0027] The leakage currents flowing from the drive transistor 202 and the reset transistor 601 to the light-emitting element 201 may depend on the lengths of the offset portions 403 and 802, respectively. Therefore, the lengths of the offset portion 403 and the offset portion 802 may be adjusted individually. From another perspective, the length of the offset portion 403 may be different from the length of the offset portion 802. Here, the length of the offset portion 403 is the length of the insulator INSD of the drive transistor 202 in the channel length direction of the drive transistor 202. The length of the offset portion 802 is the length of the insulator INSR of the reset transistor 601 in the channel length direction of the reset transistor 601.

[0028] Hereinafter, the light-emitting device 101 of the third embodiment will be described with reference to FIGS. 9, 10, 11, and 12. Matters not mentioned as the third embodiment may follow the first and second embodiments. In the light-emitting device 101 of the third embodiment, each pixel 102 includes a light-emitting control transistor 911 that controls the current supply from Vdd204 to the drive transistor 202. FIG. 9 shows the configuration of the light-emitting device 101 of the third embodiment. In the third embodiment, the pixel array 103 may include a plurality of first scanning lines 106 extending along rows, a plurality of second scanning lines 501 extending along rows, a plurality of third scanning lines 901 extending along rows, and a plurality of signal lines 107 extending along columns. The vertical scanning circuit 104 drives the plurality of first scanning lines 106 so as to control the writing of a signal voltage (luminance signal) to the pixels 102 in each row, and drives the plurality of second scanning lines 501 so as to reset the light-emitting elements 201 of the pixels 102 in the row. The vertical scanning circuit 104 drives the plurality of third scanning lines 901 so as to control the period (in another perspective, light emission and non-light emission) during which the light-emitting elements 201 of the pixels 102 in each row emit light.

[0029] FIG. 10 illustrates an equivalent circuit showing the configuration of one pixel 102 in the third embodiment. Similar to the second embodiment, the pixel 102 may include a light-emitting element 201, a driving transistor 202, a writing transistor 203, and a reset transistor 601. Further, the pixel 102 may further include a light-emitting control transistor 911 that controls the period during which the light-emitting element 201 emits light. One of the source and drain of the light-emitting control transistor 911 (the drain in this example) may be connected to one of the source and drain of the driving transistor 202 (the source in this example). The other of the source and drain of the light-emitting control transistor 911 (the source in this example) may be connected to Vdd204. Also, the gate of the light-emitting control transistor 911 is connected to the third scanning line 901.

[0030] The pixel 102 may include a first capacitor element 1002 connected between the gate of the driving transistor 202 and the source of the driving transistor 202, and a second capacitor element 1003 connected between the source of the driving transistor 202 and Vdd204. The first capacitor element 1002 and the second capacitor element 1003 may be, for example, parasitic capacitances or may have a MIM (Metal-Insulator-Metal) structure.

[0031] The light emission control transistor 911 is a MOS transistor having a gate, a source, and a drain. The light emission control transistor 911 turns on in response to a light emission control signal applied to the gate via the third scan line 901 from the vertical scan circuit 104, thereby enabling current supply from Vdd204 to the drive transistor 202. As a result, the light emitting element 201 is driven by the drive transistor 202 and the light emitting element 201 emits light. That is, the light emission control transistor 911 functions to control the period during which the light emitting element 201 emits light. From another perspective, the light emission control transistor 911 functions to control the light emission and non-light emission of the light emitting element 201. From still another perspective, the light emission control transistor 911 has a function of controlling the ratio of the light emission period to the non-light emission period of the light emitting element 201, that is, the duty ratio. By controlling the duty ratio, it is possible to reduce the afterimage blur associated with the pixel 102 emitting light over one frame period, and in particular, it is possible to improve the image quality during video.

[0032] Also, due to variations during manufacturing, the threshold value of the drive transistor 202 may differ for each pixel. In this case, when the same signal voltage is written to a plurality of pixels having the same emission color, the amount of current flowing through the drive transistor 202 differs for each pixel, and the amount of light emission may vary. Therefore, it is advisable to perform a so-called threshold correction operation that holds the threshold value between the gate and the source of the drive transistor 202 before writing the signal voltage. By this threshold correction operation, it is possible to reduce the variation in the amount of current of the drive transistor 202 in each pixel and realize more uniform light emission. In the threshold correction operation, after flowing a current through the light emitting element 201 via the light emission control transistor 911 and the drive transistor 202, the light emission control transistor 911 is turned off. As a result, current flows through the light emitting element 201 until the voltage between the gate and the source of the drive transistor 202 stabilizes, and threshold correction is performed.

[0033] FIG. 11 and FIG. 12 are a plan view and a cross-sectional view schematically showing the configurations of the driving transistor 202, the writing transistor 203, the reset transistor 601, and the light emission control transistor 911 among the pixels 102 shown in FIG. 10, respectively. FIG. 12 shows a cross-section taken along C-C' in FIG. 11. The light emission control transistor 911 may include a semiconductor region of a first conductivity type that forms the source 923, a semiconductor region of a first conductivity type that forms the drain 302, and a gate 921. In this example, the semiconductor region of the first conductivity type that forms the drain 302 of the light emission control transistor 911 is common with the semiconductor region of the first conductivity type that forms the source 302 of the driving transistor 202. However, the semiconductor region of the first conductivity type that forms the drain of the light emission control transistor 911 may be provided separately from the semiconductor region of the first conductivity type that forms the source of the driving transistor 202.

[0034] Hereinafter, application examples of the above light emitting device 101 will be described. FIG. 13 is a schematic diagram showing an example of a display device 1000 according to an embodiment. The display device 1000 may include a touch panel 1003, a display panel 1005, a frame 1006, a circuit board 1007, and a battery 1008 between an upper cover 1001 and a lower cover 1009. The display panel 1005 is an application example of the light emitting device 101. The touch panel 1003 and the display panel 1005 are connected to flexible printed circuits FPC1002 and 1004. Transistors are printed on the circuit board 1007. The battery 1008 may not be provided if the display device is not a portable device, or may be provided at another position even if it is a portable device. The display device 1000 may include color filters having red, green, and blue. The color filters may have the red, green, and blue arranged in a delta array.

[0035] The display device 1000 may be used for a display unit of a portable terminal. In that case, it may have both a display function and an operation function. Examples of the portable terminal include mobile phones such as smartphones, tablets, head-mounted displays, and the like.

[0036] The display device 1000 may be used in a display unit of an imaging device having an optical unit with a plurality of lenses and an imaging element that receives light that has passed through the optical unit. The imaging device may have a display unit that displays information acquired by the imaging element. Also, the display unit may be a display unit exposed to the outside of the imaging device or a display unit disposed within the viewfinder. The imaging device may be a digital camera or a digital video camera.

[0037] FIG. 14(a) is a schematic diagram showing an example of an imaging device 1100. The imaging device 1100 may have a viewfinder 1101, a rear display 1102, an operation unit 1103, and a housing 1104. The viewfinder 1101 may have the display device 1000. In that case, the display device 1000 may display not only the image to be captured but also environmental information, imaging instructions, etc. The environmental information may include the intensity of external light, the direction of external light, the speed at which the subject moves, the possibility that the subject is shielded by an obstacle, etc.

[0038] The imaging device 1100 has an optical unit (not shown). The optical unit has a plurality of lenses and forms an image on an imaging element housed within the housing 1104. The plurality of lenses can adjust the focus by adjusting their relative positions. This operation can also be performed automatically. The imaging device may be called an optoelectronic conversion device. The optoelectronic conversion device may include, as imaging methods, a method of detecting the difference from a previous image instead of sequentially imaging, a method of cutting out from an image that is always recorded, etc.

[0039] FIG. 14(b) is a schematic diagram showing an example of an electronic device according to an embodiment. The electronic device 1200 includes a display unit 1201, an operation unit 1202, and a housing 1203. The housing 1203 may include a circuit, a printed circuit board having the circuit, a battery, and a communication unit. The operation unit 1202 may be a button or a reaction unit of a touch panel type. The operation unit may be a biometric recognition unit that recognizes a fingerprint and performs unlocking or the like. An electronic device having a communication unit can also be called a communication device. The electronic device may further have a camera function by including a lens and an imaging device. An image captured by the camera function is displayed on the display unit. Examples of the electronic device include a smartphone and a notebook computer.

[0040] FIG. 15(a) is a schematic diagram showing an example of a display device 1300 according to an embodiment. The display device 1300 can be applied to a TV monitor, a PC monitor, or the like. The display device 1300 has a frame 1301 and a display unit 1302. The display unit 1302 is an application example of the light-emitting device 101.

[0041] It has a frame 1301 and a base 1303 that supports the display unit 1302. The base 1303 is not limited to the form of FIG. 4(a). The lower side of the frame 1301 may also serve as the base. Further, the frame 1301 and the display unit 1302 may be bent. The radius of curvature may be 5000 mm or more and 6000 mm or less.

[0042] FIG. 15(b) is a schematic diagram showing another example of the display device 1310 according to an embodiment. The display device 1310 in FIG. 15(b) is configured to be foldable and is a so-called foldable display device. The display device 1310 includes a first display unit 1311, a second display unit 1312, a housing 1313, and a bending point 1314. The first display unit 1311 and the second display unit 1312 are application examples of the light-emitting device 101. The first display unit 1311 and the second display unit 1312 may be a single seamless display device. The first display unit 1311 and the second display unit 1312 can be separated at the bending point. The first display unit 1311 and the second display unit 1312 may display different images respectively, or may display one image together with the first and second display units.

[0043] Referring to FIG. 16, an application example of the above display device will be described. The display device can be applied to a wearable system such as smart glasses, HMDs, or smart contacts. The imaging display device used in such an application example includes an imaging device capable of photoelectrically converting visible light and a display device capable of emitting visible light.

[0044] FIG. 16(a) shows the configuration of glasses 1600 (smart glasses) according to one application example. An imaging device 1602 such as a CMOS sensor or a SPAD is provided on the front surface side of the lens 1601 of the glasses 1600. Also, a display device of each of the above-described embodiments is provided on the back surface side of the lens 1601.

[0045] The glasses 1600 further include a control device 1603. The control device 1603 functions as a power source that supplies power to the imaging device 1602 and the display device according to each embodiment. Also, the control device 1603 controls the operations of the imaging device 1602 and the display device. An optical system for condensing light onto the imaging device 1602 is formed in the lens 1601.

[0046] FIG. 16(b) shows the configuration of glasses 1610 (smart glasses) according to another application example. The glasses 1610 have a control device 1612. An imaging device corresponding to the imaging device 1602 and a display device are mounted on the control device 1612. An optical system for projecting the light emitted by the display device in the control device 1612 is formed in the lens 1611, and an image is projected onto the lens 1611. The control device 1612 functions as a power source for supplying power to the imaging device and the display device, and controls the operations of the imaging device and the display device. The control device may have a gaze detection unit for detecting the wearer's gaze. Infrared rays may be used for gaze detection. The infrared light emitting unit emits infrared light to the eyeball of the user who is gazing at the display image. The imaging unit having a light receiving element detects the reflected light of the emitted infrared light from the eyeball, and thus an imaging image of the eyeball is obtained. By having a reducing means for reducing the light from the infrared light emitting unit to the display unit in a plan view, a decrease in image quality is reduced.

[0047] The user's gaze with respect to the display image is detected from the imaging image of the eyeball obtained by imaging infrared light. Any known method can be applied to gaze detection using the imaging image of the eyeball. As an example, a gaze detection method based on the Purkinje image by reflection of irradiation light on the cornea can be used.

[0048] More specifically, a gaze detection process based on the pupil corneal reflex method is performed. Using the pupil corneal reflex method, a gaze vector representing the orientation (rotation angle) of the eyeball is calculated based on the image of the pupil and the Purkinje image included in the imaging image of the eyeball, whereby the user's gaze is detected.

[0049] The display device according to an embodiment of the present invention may have an imaging device having a light receiving element, and control the display image of the display device based on the user's gaze information from the imaging device.

[0050] Specifically, the display device determines, based on the line-of-sight information, a first display area that the user gazes at and a second display area other than the first display area. The first display area and the second display area may be determined by the control device of the display device, or the display device may receive those determined by an external control device. In the display area of the display device, the display resolution of the first display area may be controlled to be higher than that of the second display area. That is, the resolution of the second display area may be made lower than that of the first viewing area.

[0051] Also, the display area has a first display area and a second display area different from the first display area, and based on the line-of-sight information, an area with a higher priority is determined from the first display area and the second display area. The first viewing area and the second viewing area may be determined by the control device of the display device, or the display device may receive those determined by an external control device. The resolution of the area with a higher priority may be controlled to be higher than that of the area other than the area with a higher priority. That is, the resolution of the area with a relatively lower priority may be made lower.

[0052] Note that AI may be used to determine the first display area or the area with a higher priority. AI may be a model configured to estimate the angle of the line of sight and the distance to the target at the tip of the line of sight from the eye image, using the eye image and the direction in which the eye in the image is actually looking as teacher data. The AI program may be possessed by the display device, the imaging device, or an external device. When an external device possesses it, it is transmitted to the display device via communication.

[0053] When performing display control based on visual recognition detection, it is preferably applicable to smart glasses further having an imaging device that images the outside. The smart glasses can display the imaged external information in real time.

[0054] This specification and the drawings include the following disclosures. (Item 1) A light-emitting device having a plurality of pixels arranged on a substrate, Each pixel includes a light-emitting element, a driving transistor that supplies current to the light-emitting element, and a writing transistor that supplies a signal voltage to the gate of the driving transistor. The driving transistor has an offset structure having an insulator between a semiconductor region constituting a source or a drain and the gate in a orthographic projection onto the main surface of the substrate. A light-emitting device characterized by the above. (Item 2) The gate is disposed via a gate insulating film on the main surface, and a depth of a bottom surface of the insulator with respect to the main surface is larger than a depth of a bottom surface of the semiconductor region with respect to the main surface. The light-emitting device according to Item 1, characterized by the above. (Item 3) The insulator includes STI (Shallow Trench Isolation). The light-emitting device according to Item 2, characterized by the above. (Item 4) The offset structure is a drain offset structure having the insulator between the drain and the gate in a orthographic projection onto the main surface of the substrate. The light-emitting device according to any one of Items 1 to 3, characterized by the above. (Item 5) The source is a first semiconductor region of a first conductivity type, and the drain is a second semiconductor region of the first conductivity type. In a current path from the first semiconductor region to the second semiconductor region, a third semiconductor region of a second conductivity type and a fourth semiconductor region of the first conductivity type are arranged in order. An effective impurity concentration of the first conductivity type in the fourth semiconductor region is lower than an effective impurity concentration of the first conductivity type in the second semiconductor region. The light-emitting device according to any one of Items 1 to 4, characterized by the above. (Item 6) The offset structure is a drain offset structure having the insulator between the drain and the gate in a orthographic projection onto the main surface of the substrate. Each pixel further includes a reset transistor for resetting the light-emitting element. In the orthographic projection, the reset transistor has a source offset structure having an insulator between the source of the reset transistor and the gate of the reset transistor. The light-emitting device according to any one of Items 1 to 3, characterized in that. (Item 7) The source of the reset transistor is common to the drain of the drive transistor. The light-emitting device according to Item 6, characterized in that. (Item 8) The depth of the bottom surface of the insulator in the source offset structure with respect to the main surface is greater than the depth of the bottom surface of the source of the reset transistor with respect to the main surface. The light-emitting device according to Item 6 or 7, characterized in that. (Item 9) The insulator in the source offset structure includes STI (Shallow Trench Isolation). The light-emitting device according to Item 8, characterized in that. (Item 10) The source of the drive transistor is a first semiconductor region of a first conductivity type, the drain of the drive transistor is a second semiconductor region of the first conductivity type, The drain of the reset transistor is a fifth semiconductor region of the first conductivity type, In the current path from the first semiconductor region to the second semiconductor region, a third semiconductor region of a second conductivity type and a fourth semiconductor region of the first conductivity type are arranged in order. The net impurity concentration of the first conductivity type in the fourth semiconductor region is lower than the net impurity concentration of the first conductivity type in the second semiconductor region. In the current path from the second semiconductor region to the fifth semiconductor region, the fourth semiconductor region of the first conductivity type and a sixth semiconductor region of the second conductivity type are arranged in order. The light-emitting device according to any one of Items 6 to 9, characterized in that. (Item 11) The length of the insulator of the drive transistor in the channel length direction of the drive transistor is different from the length of the insulator of the reset transistor in the channel length direction of the reset transistor. The light-emitting device according to any one of Items 6 to 10, characterized in that. (Item 12) Each pixel further includes a light-emitting control transistor that controls a period during which the light-emitting element emits light. The light-emitting device according to any one of Items 1 to 11, characterized in that. (Item 13) The plurality of pixels are arranged so as to form a plurality of rows and a plurality of columns. The light-emitting device according to any one of Items 1 to 12, characterized in that. (Item 14) A display device including the light-emitting device according to any one of Items 1 to 13. (Item 15) An optoelectronic conversion device having an optical unit having a plurality of lenses, an image pickup element that receives light that has passed through the optical unit, and a display unit that displays an image, The display unit has the light-emitting device according to any one of Items 1 to 13, and is characterized in that. (Item 16) An electronic device having a housing provided with a display unit and a communication unit provided in the housing and communicating with the outside, The display unit has the light-emitting device according to any one of Items 1 to 13, and is characterized in that. (Item 17) A wearable device having a display device for displaying an image, The display device has the light-emitting device according to any one of Items 1 to 13, and is characterized in that.

[0055] The invention is not limited to the above embodiments, and various changes and modifications are possible without departing from the spirit and scope of the invention. Therefore, the claims are attached to disclose the scope of the invention.

Description of Symbols

[0056] 101: Light-emitting device, 102: Pixel, 201: Light-emitting element, 202: Driving transistor, 203: Writing transistor, INSD: Insulator, 403: Offset portion, PS: Main surface, SUB: Substrate

Claims

1. A light-emitting device having a plurality of pixels disposed on a substrate, each pixel including a light-emitting element, a driving transistor that supplies current to the light-emitting element, and a writing transistor that supplies a signal voltage to the gate of the driving transistor, the driving transistor having an offset structure having an insulator between a semiconductor region constituting a source or a drain and the gate in a front projection onto a main surface of the substrate, the light-emitting device being characterized by this.

2. The gate is disposed via a gate insulating film on the main surface, and a depth of a bottom surface of the insulator with respect to the main surface is greater than a depth of a bottom surface of the semiconductor region with respect to the main surface, the light-emitting device according to Claim 1 being characterized by this.

3. The insulator includes STI (Shallow Trench Isolation), the light-emitting device according to Claim 2 being characterized by this.

4. The offset structure is a drain offset structure having the insulator between the drain and the gate in a front projection onto a main surface of the substrate, the light-emitting device according to Claim 1 being characterized by this.

5. The source is a first semiconductor region of a first conductivity type, and the drain is a second semiconductor region of the first conductivity type, in a current path from the first semiconductor region to the second semiconductor region, a third semiconductor region of a second conductivity type and a fourth semiconductor region of the first conductivity type are sequentially disposed, a net impurity concentration of the first conductivity type in the fourth semiconductor region is lower than a net impurity concentration of the first conductivity type in the second semiconductor region, the light-emitting device according to Claim 1 being characterized by this.

6. The offset structure is a drain offset structure having the insulator between the drain and the gate in a front projection onto a main surface of the substrate, each pixel further including a reset transistor for resetting the light-emitting element, the reset transistor having a source offset structure having an insulator between a source of the reset transistor and a gate of the reset transistor in the front projection, the light-emitting device according to Claim 1 being characterized by this.

7. The source of the reset transistor is common with the drain of the driving transistor, the light-emitting device according to Claim 6 being characterized by this.

8. The depth of the bottom surface of the insulator in the source offset structure with respect to the main surface is greater than the depth of the bottom surface of the source of the reset transistor with respect to the main surface. The light-emitting device according to claim 6, characterized in that.

9. The insulator in the source offset structure includes STI (Shallow Trench Isolation). The light-emitting device according to claim 8, characterized in that.

10. The source of the driving transistor is a first semiconductor region of a first conductivity type, and the drain of the driving transistor is a second semiconductor region of the first conductivity type. The drain of the reset transistor is a fifth semiconductor region of the first conductivity type. In the current path from the first semiconductor region to the second semiconductor region, a third semiconductor region of a second conductivity type and a fourth semiconductor region of the first conductivity type are arranged in order. The net impurity concentration of the first conductivity type in the fourth semiconductor region is lower than the net impurity concentration of the first conductivity type in the second semiconductor region. In the current path from the second semiconductor region to the fifth semiconductor region, the fourth semiconductor region of the first conductivity type and a sixth semiconductor region of the second conductivity type are arranged in order. The light-emitting device according to claim 6, characterized in that.

11. The length of the insulator of the driving transistor in the channel length direction of the driving transistor is different from the length of the insulator of the reset transistor in the channel length direction of the reset transistor. The light-emitting device according to claim 6, characterized in that.

12. Each pixel further includes a light-emitting control transistor that controls a period during which the light-emitting element emits light. The light-emitting device according to claim 1, characterized in that.

13. The plurality of pixels are arranged so as to form a plurality of rows and a plurality of columns. The light-emitting device according to any one of claims 1 to 12, characterized in that.

14. A display device including the light-emitting device according to any one of claims 1 to 12.

15. An optical unit having a plurality of lenses, an imaging element that receives light that has passed through the optical unit, and a display unit that displays an image. The photoelectric conversion device, characterized in that the display unit includes the light-emitting device according to any one of claims 1 to 12.

16. A housing provided with a display unit, and a communication unit provided in the housing and communicating with the outside. The display unit is an electronic device characterized by having the light-emitting device according to any one of claims 1 to 12. **Claim 17** A wearable device having a display device for displaying an image, wherein the display device has the light-emitting device according to any one of claims 1 to 12.

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