Method, device and system for serial bus transaction with selectable data transaction size

Abstract

To provide a method, device and system for specifying the size of data transfer before the data transfer begins.SOLUTION: A method includes the steps of: receiving, at a serial input / output (IO) of a memory device, metadata that includes at least command values, address values and encoded length values in synchronism with a serial clock; from at least the command values, address values and encoded length values, determining a memory access operation, a memory array location, and one of a plurality of different data length values (LEN) corresponding to the memory access operation; and transferring at least data having a length corresponding to the one of the plurality of different LEN at the serial IO in synchronism with the serial clock during execution of the memory access operation.SELECTED DRAWING: Figure 8

Description

Technical Field

[0001] Cross - reference to Related Applications This application claims the benefit and priority of U.S. Patent Application No. 63 / 602,186, filed on November 22, 2023, the entire content of which is incorporated herein by reference.

[0002] This disclosure generally relates to the authentication of memory device transactions, and more particularly to enabling memory device transactions with selectable extended data sizes, where the extended data is write data, program data, or erase data in addition to read data.

Background Art

[0003] Currently, many electronic platforms using memory storage devices are concerned with the security of data access operations. Many specifications, including some automotive specifications, require that the code and data stored by a memory device be authenticated before execution.

[0004] Conventionally, a system may use "shadow" memory for security improvements. In this type of configuration, code for execution can be transferred from non - volatile memory (NVM) to volatile memory. A host (e.g., the device executing the code) can authenticate the code transferred to volatile memory. The shadow memory approach is not compatible with an execution - in - place (XiP) design where code is preferably executed directly from NVM because only the code present on volatile memory is authenticated.

[0005] In a conventional Serial Peripheral Interface Bus (SPI) transaction, the number of bytes transferred can be determined by the host assertion stop of the chip select signal (CS). Alternatively, this type of transaction, such as a read operation, operates with a fixed data length, such as the amount of read data. Some conventional memory devices can include a configuration register that can use a "wrap length" to specify a fixed transaction length outside of the SPI protocol.

[0006] Prior to the start of data transfer, it is desirable to have a protocol for specifying the size of the data transfer. This can enable an efficient implementation of security features such as authentication tags. SUMMARY OF THE INVENTION MEANS FOR SOLVING THE PROBLEM

[0007] A method can include receiving, at a serial input / output (IO) of a memory device and synchronized with a serial clock, metadata including at least a command value, an address value, and an encoded length value. From at least the command value, the address value, and the encoded length value, a memory access operation, a memory array location, and one of a plurality of different data length values (LEN) corresponding to the memory access operation can be determined. At least data having a length corresponding to one of the plurality of different LENs can be transferred at the serial IO synchronized with the serial clock during execution of the memory access operation. Corresponding devices and systems are also disclosed. BRIEF DESCRIPTION OF THE DRAWINGS

[0008]

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Best Mode for Carrying Out the Invention

[0009] According to an embodiment, a memory device can receive an encoded data length value (LEN) along with commands and address values received in a transaction. The encoded LEN value can indicate one of many possible lengths for the data included within the transaction. In a read operation, the LEN value can indicate the size of the corresponding read data. In a write or program operation, the LEN value can indicate the size of the corresponding write or program data. In this way, the amount of data transferred in a memory device transaction can be controllable by the bit values transferred along with the commands and address values. The LEN value can correspond to the number of serial clock cycles required to transfer the data and can thus vary according to the serial bus size.

[0010] In some embodiments, a memory device transaction can include additional data that extends beyond the LEN value, such as "tag" data for authenticating the transaction.

[0011] In some embodiments, in addition to the data length, the LEN value can include metadata for the transaction. This type of metadata can include, but is not limited to, indicating the encryption of the data or the inclusion of authentication data.

[0012] According to an embodiment, in a read transaction, the memory device can provide any of a number of possible read data sizes determined by the LEN value received along with the command and address data. Similarly, in a write or program operation, the memory device can determine the amount of data received according to the LEN value received along with the command and address data.

[0013] In some embodiments, the encoded LEN value can be received after the command value and address value.

[0014] In some embodiments, the LEN value can be received together with the command value, and then the address value can be received.

[0015] In some embodiments, the LEN value can be received together with the address value, and then the command value can be received.

[0016] In some embodiments, the LEN value can include additional metadata that can indicate the characteristics of the corresponding transaction.

[0017] In some embodiments, a transaction having a selectable data length value can occur between a non-volatile memory device and a host device. The host device can read and execute code directly (i.e., execute in place (XiP)) from the non-volatile memory device by means of a command-address (CMD / ADD) sequence that includes an encoded LEN value.

[0018] FIG. 1 is a block diagram of a memory device 100 according to one embodiment. The memory device 100 can include a memory array 102, input / output (IO) circuitry 104, control logic 106, array decoder circuitry 108-0 / 1, program and erase circuitry 110, data latches 112, and a data path 114. The memory array 102 can include any suitable type of memory cell, including non-volatile memory cells, volatile memory cells, and combinations thereof. The IO circuitry 104 can be connectable to a serial bus 118, and the serial bus 118 can carry a control signal CS#, a serial clock SCK, and one or more serial inputs and / or outputs SIO0 through SIOn. It should be understood that a sequence of command and address values can be received as serial data on one serial IO (e.g., SIO0) in synchronization with the SCK. Additionally, the encoded LEN value can be received as part of the command address sequence.

[0019] The control logic 106 can receive the command value, address value, and LEN value received by the IO circuit 104. In response to this type of value, the control logic 106 can generate a control signal 116 that can control access to the memory array 102. Different from conventional memory devices, the control logic 106 can include a LEN decoding circuit 106-0, and the LEN decoding circuit 106-0 can generate a LEN value and determine the size (e.g., length) of the data that is the target of the memory access transaction. It should be understood that the LEN decoding circuit 106-0 can determine one of many possible different LEN values from the received command / address (CMD / ADD) sequence. This is in contrast to conventional devices that may require programming of configuration registers to establish a data length size for transactions that exceed the default or initially configured size.

[0020] The array decoder can include an X decoder 108-0 and a Y decoder 108-1. The X decoder 108-0 can select a row of memory cells, and in some embodiments, can select a higher organization (e.g., block) of memory cells. The Y decoder 108-1 can select a column of memory cells. In some embodiments, data can be stored in the memory array 102 along with corresponding extended data. As a result, in response to the decoded LEN value, the decoder circuits (108-0 and / or 108-1) can access an appropriate amount of memory locations at the address provided in the CMD / ADD sequence. Further, as noted herein, the LEN value can include metadata related to the operation.

[0021] In the illustrated embodiment, the memory device 100 can include a program and erase circuit 110 for programming and erasing data from non-volatile memory cells within the memory array 102. In some embodiments, this kind of programming of data can vary according to the LEN value. In some embodiments, the metadata of the LEN value can similarly control the characteristics of the erase operation. In some embodiments, the control logic 106 can process authenticated transactions. In such cases, additional data (referred to herein as "tag" data) can be received after transmission of data having a length indicated by the LEN value. The tag data can authenticate the data for the transaction and / or can authenticate the transaction itself (e.g., can authenticate command / address data). FIG. 1 shows a program and erase circuit 110 compatible with non-volatile memory cells, but alternative embodiments can include volatile memory cells, in which case the program / erase circuit 110 can be a write circuit suitable for the memory cell type (e.g., a write amplifier, a refresh circuit section, etc.) (or can include a write circuit).

[0022] The data latch 112 circuit can latch data for programming / writing into the memory array 102. The data path 114 can transfer data between the control logic 106 and the data latch 112 and / or the memory array 102.

[0023] In this way, the memory device can decode the values received in the command address sequence on the serial input and determine the variable data length size. The operations of transmitting and / or receiving data can be adjusted to meet the data length size.

[0024] Figures 2-0 and 2-1 are timing diagrams showing memory device transactions 225-0 and 225-1 according to an embodiment. Memory device transactions 225-0 / 1 can occur on serial bus 218. Figures 2-0 and 2-1 show waveforms for serial clock signal SCK and serial IO (SIO). SIO can be a single IO or a combination of SIOs including multiple other IOs for receiving / sending data for a transaction (e.g., Quad SPI (QSPI), Octal SPI (OSPI)). Furthermore, in some embodiments, SIO can be split into one or more dedicated serial inputs for receiving serial data and one or more dedicated serial outputs for transmitting serial data.

[0025] Figure 2-0 shows a transaction in which the CMD / ADD sequence includes one LEN value. Figure 2-1 shows another transaction in which the CMD / ADD sequence includes another different LEN value.

[0026] Referring to Figure 2-0, at time t0, the device can start receiving command / address sequence 220-0. CMD / ADD sequence 220 can include command data (C), address data (A), and data indicating an n+1 LEN value, which is different from conventional transactions. In some embodiments, this type of value can be an encoded LEN value. The LEN data can be included separately from the command and address data (shown as 221), can be included in the command data, can be included in the address data, or can be a combination thereof.

[0027] Command data can be received (e.g., latched) at the rising and falling edges of SCK. In some embodiments, the command data received at the rising and falling edges can be the same data (i.e., the command is repeated). However, in other embodiments, the command data can be received at the rising edge, while the command data at the falling edge can include LEN data. FIG. 2-0 shows the command data received through a single cycle of SCK. In other embodiments, the command data can be received through more cycles, and this type of command data may include LEN data.

[0028] At time t1, after the command data, the address data can be received at the rising and falling edges of SCK. In some embodiments, the address data can include LEN data. In some embodiments, the LEN data can occupy the least significant address bit. In some embodiments, LEN (and possibly other data) can be received in the extended command data 221 that can follow the command and address data.

[0029] At time t2, the transaction data 220-0 having a length LEN can be transmitted or received according to the transaction 225-0. In the illustrated embodiment, the LEN value indicates n+1. Accordingly, the transaction data 220-0 can have a length of n+1. This type of data can be transmitted after a CMD / ADD sequence (e.g., a read operation) or received together with a CMD / ADD sequence (e.g., a write / program operation).

[0030] Referring next to FIG. 2-1, similar to the case of FIG. 2-0, at time t0, the device can start receiving the command / address sequence 220-1. However, this type of CMD / ADD sequence 220 can include m+1 different LEN values. As a result, the corresponding transaction data 220-1 can have a length of m+1.

[0031] FIG. 2-1 also shows extended data 223 that can be included within several transactions. The extended data 223 can be received after the transaction data of length m+1. The extended data 223 can represent any suitable data in addition to the transaction data, including but not limited to authentication data, error detection data (e.g., CRC), and / or error correction data (ECC code).

[0032] According to an embodiment, the command and address data for the two transactions 225-0 / 1 of FIGS. 2-0 and 2-1 can be the same, but it should be recognized that the difference in the LEN values results in a change in the size of the data transmitted for the transaction.

[0033] In this way, the memory device transaction can include selectable data length values in the CMD / ADD sequence, and the transaction data can be transmitted through the number of clock cycles corresponding to the selected data length.

[0034] FIG. 3 is a block diagram of a system 330 according to an embodiment. The system 330 can include a memory device 300 and a memory controller 340 that communicate on a serial bus 318. In some embodiments, the memory device 300 can be one embodiment of those shown in FIG. 1.

[0035] The memory device 300 can include one or more memory cell arrays 302, an IO circuit 304, a CMD / ADD decoder circuit 306-0, an access control circuit 306-1, a data output circuit 324-0, a data input circuit 324-1, and optionally, an extended data operation circuit 306-2. The memory cell array 302 can include one or more memory cell arrays or equivalents described herein. The IO circuit 304 can be connected to the serial bus 318, can receive a control signal 342-0, can receive commands, addresses, and LEN values, and can further receive or transmit data values on one or more SIOS.

[0036] In the illustrated embodiment, the CMD / ADD decoder circuit 306-0 can receive command and address data 334-0 along with encoded LEN data. From this type of data, the CMD / ADD decoder circuit 306-0 can determine the type of transaction, the address corresponding to the transaction, and the LEN value for the transaction. This type of value can be provided to the access control circuit 306-1. The access control circuit 306-1 can control access to the memory cell array 302 according to the determined transaction type and LEN size. The access control circuit 306-1 can include an extended transaction control circuit 332 for constructing extended data included in a transaction. For example, the extended control circuit 332 can operate on data received after data of length LEN (i.e., after transaction data), and the received data is understood to be extended data rather than transaction data.

[0037] The optional extended data operation circuit 306-2 can execute the extended data operation indicated by the CMD / ADD sequence. The extended data operation can include any suitable operation that utilizes extended data, along with commands, addresses, and / or other data associated with the transaction. In some embodiments, the extended operation can include, but is not limited to, authentication, error detection, or error correction. The authentication operation can include any one of an authentication read operation, an authentication write or program operation, and an authentication erase operation. In the authentication read operation, the extended data can be used to authenticate the read data transmitted together with the extended data. In the authentication program or write operation, the extended data can be transmitted together with the CMD / ADD sequence and can be used to authenticate the program / write data and / or the CMD / ADD data. Additionally or alternatively, the authentication program or write operation can write the extended data into the memory device together with the corresponding write / program data. When the programmed / written data is read out as read data, this type of extended data can be output together with the read data. In the authentication erase operation, the extended data can be transmitted together with the CMD / ADD sequence and can be used to authenticate the CMD / ADD data. The error detection operation can use the extended data to detect errors in the data (e.g., write or program data), using the extended data received together with this type of data.

[0038] In the illustrated embodiment, the extended operation circuit 306-2 can include an extended function circuit 328-0 and an extended value generation circuit 328-1. The extended function circuit 328-0 can execute the extended operations described in the present specification, which can include, but are not limited to, authenticating write / program data using corresponding extended data and / or authenticating write / program or erase commands (and possibly addresses) using corresponding extended data. The host can generate extended values, but in some embodiments, the memory device 300 can include the extended value generation circuit 328-1. In some embodiments, this type of circuit can include generating extended values, such as authentication values, EDC, or ECC, from the read data.

[0039] The data output circuit 324-0 can provide a path from the memory cell array 302 to the extended operation circuit 306-2. The data input circuit 324-1 can provide a path from the extended operation circuit 306-2 to the memory cell array 302.

[0040] The memory controller 340 can execute transactions with the memory device 300 and, in some embodiments, can be part of a host device. The memory controller 340 can include a controller IO circuit 340-0, a controller CMD / ADD generator circuit 340-1, and optionally, a controller extension function circuit 340-2. The controller CMD / ADD generator 340-1 can receive request data 348 and LEN data 350. The request data can indicate the type of operation (memory read, memory write, memory erase). The LEN data can indicate the LEN value for the transaction. In response to this type of input, the controller CMD / ADD generator 340-1 can generate a CMD / ADD value with an encoded LEN value for the controller IO circuit 340-0. Unlike conventional controllers, the CMD / ADD generator circuit 340-1 can include an LEN encoder circuit 344, and the LEN encoder circuit 344 can encode the LEN value and generate a combination of bits for inclusion in the CMD / ADD sequence. As understood from the embodiments herein, different combinations of encoded LEN bits can correspond to different LEN sizes.

[0041] The optional controller extension function circuit 340-2 can execute functions related to extended data transactions. The extended check circuit 346-0 can receive data from the memory device 300 and execute one or more functions associated with the received extended data. The functions can include, but are not limited to, authentication of read data by corresponding extended data, error detection and / or correction of read data by corresponding extended data. The authenticated read data can be output from the extended check circuit 346-0 as data output 352-0. Unauthenticable read data can be discarded. The error-corrected read data can be output from the extended check circuit 346-0 as data output 352-0. Read data having errors that are only detected and not corrected can be discarded, and the read operation can be repeated.

[0042] The extended data generation circuit 346-1 can generate extended data values for transmission to the memory device 300. In the illustrated embodiment, a data input 352-1 is received, from which extended data (e.g., any of authentication data, EDC, ECC) can be generated. The received data input 352-1 and the corresponding generated extended data can then be provided to the controller IO circuit 340-0 for output on the serial bus 318. In some embodiments, commands and / or address data can also be included in the generation of extended data (e.g., for authentication of CMD / ADD values).

[0043] The controller IO circuit 340-0 can drive signals 342-0 on the control lines and control transmission on the serial bus 318. This type of control signal 342-0 can include, but is not limited to, SCK and CS signals. The controller circuit 340-0 can also transmit a CMD / ADD sequence with extended data and receive read data 342-1 with extended data on one or more SIO lines.

[0044] In this way, the controller device can encode the length size for the transaction data, and this kind of value can be included within the CMD / ADD sequence for the memory device. The memory device can decode the encoded length value and determine the size of the data for the transaction indicated by the CMD / ADD sequence.

[0045] Figures 4-0, 4-1, and 4-2 are state diagrams of the CMD / ADD decoder of a memory device according to an embodiment. Figures 4-0 through 4-2 can include similar items referenced by the same reference numerals.

[0046] Figure 4-0 shows a CMD / ADD decoder 406-0 that can derive an encoded LEN value after receiving command and address data. When the CS signal is activated, the CMD / ADD decoder 406-0 can transition from the idle state 454 to a decoding operation that changes according to the serial bus cycle 456-0. From bus cycle "i" to "j-1", the received value can be decoded as a command value (458). From cycle "j" to "k-1", the received value can be decoded as an address value (460). From cycle "k" to "l", the received value can be decoded as an LEN value (462). It should be understood that the clock cycles "i", "j", "k", and "l" can be portions of a cycle (e.g., a half-cycle). Further, the values of this kind of clock cycle (i~l) can vary according to the device configuration (e.g., the number of SIOS, the memory device address space, the memory device IO size, etc.). In some embodiments, cycle i to j-1 can be dedicated to command data, and cycle j to k-1 can be dedicated to address data according to the standard (e.g., SPI standard) in which the memory device 300 operates.

[0047] FIG. 4-1 shows a CMD / ADD decoder 406-1 that can derive the encoded LEN value included by the address value. In some embodiments, this type of configuration can result from the LSB (least significant bit) of the address replaced by the LEN bits. FIG. 4-1 differs from FIG. 4-0 in that after receiving the command value, the values received from cycle j to k-1 can be decoded as address and LEN values (464). In some embodiments, cycles i through j-1 can be dedicated to address data according to the standard in which memory device 300 operates.

[0048] FIG. 4-2 shows a CMD / ADD decoder 406-2 that can derive the encoded LEN value included by the command value. This type of configuration can utilize a combination of a period (e.g., a falling clock edge) and / or unassigned bit values as the encoded LEN value in the command value space. FIG. 4-2 differs from FIG. 4-0 in that the values received from cycle i to j-1 can be decoded as command and LEN values (466). In some embodiments, cycles i through j-1 can be dedicated to command data according to the standard in which memory device 300 operates.

[0049] Note that embodiments can include the LEN decoding combinations presented in FIGS. 4-0 through 4-2.

[0050] In this way, the CMD / ADD decoder of the memory device can decode the bit indicating the transaction data length size included in any of the following, where the following are bits after the clock cycles assigned to the command and address values, bits included in the clock cycles assigned to the address value, and / or bits included in the clock cycles assigned to the command value.

[0051] Figures 5-0 to 5-2, 6-0 to 6-2, and 7-0 to 7-2 are timing diagrams showing memory device transactions according to embodiments. Each timing diagram includes a CS# waveform, an SCK waveform, and an SIO waveform. The SIO waveform can include eight SIO[7:0] (e.g., OSPI).

[0052] Figures 5-0 to 5-2 show data transactions that can include LEN and / or metadata as data at the end of the CMD / ADD sequence in addition to the command and address values.

[0053] Referring to Figure 5-0, a data read operation according to an embodiment is shown in the timing diagram. Before time t0, CS# can transition to active (i.e., go low). At time t0, command data (C) can be latched at least at the rising edge of SCK. In the illustrated embodiment, the command data (C) can indicate an extended read operation. The extended read operation can return the read data to the indicated address and also return the corresponding extended data to the requesting device. Unlike conventional read operations, the amount of read data (i.e., LEN) can be determined by the encoded LEN values in L1 and L0 included in the CMD / ADD sequence. After the command data (C), at time t1, address data (A) can be latched at the last rising edge of SCK. Unlike conventional serial memory read operations, after the address data (A), at time t2, the encoded LEN data extended data (shown as L0, L1) can be latched at least at the rising edge of SCK. In some embodiments, a second set of command data (C) (i.e., at the falling edge of SCK in Figure 5-0) can indicate the presence of the LEN data (L1, L0) after the address data (A).

[0054] Referring further to FIG. 5-0, at around time t3, after many dummy cycles, the read data corresponding to the extended data read operation (shown as cD0 to cD31) can be output in synchronization with the rising and falling edges of SCK (i.e., at double data rate). In the illustrated embodiment, the read data can have a length indicated by the encoded LEN value, and in the illustrated embodiment, it can be a 32-byte output over 16 SCK cycles (i.e., double data rate).

[0055] Note that after transmission of the read data, at time t4, CS# can remain active. However, since the LEN is known to the controller device that issues the read command, the controller device can distinguish where the read data ends and where the extended data starts.

[0056] At around time t4, after the read data (cD0 to cD31), the extended data (shown as eT0 to eT15) can be output on the rising and falling edges of SCK. In the illustrated embodiment, the extended data can be an output with a burst length of 128 bits over 8 SCK cycles. At around time t5, CS# can be made inactive to end the extended data read transaction.

[0057] Figure 5-1 shows an extended data write / program operation according to an embodiment. From time t0 to t2, the extended data write / program operation can follow the actions described for Figure 5-0, but the command value (C) indicates the extended data write / program operation. Around time t3, after the encoded LEN data (L0, L1), the write / program data corresponding to the extended data write / program operation can be output at the rising and falling edges of SCK. Different from the conventional write / program operation, the amount of write data can be determined by the encoded LEN values in L1 and L0 included in the CMD / ADD sequence. In the illustrated embodiment, the write / program data can be output with a burst length of 256 bits over 16 SCK cycles. Around time t4, after the write / program data (from cD0 to cD31), the extended data (shown as eT0 to eT15) can be output at the rising and falling edges of SCK. In the illustrated embodiment, the extended data can be output with a burst length of 128 bits over 8 SCK cycles. Around time t5, CS# can end the extended data write / program transaction. Due to the LEN values received by L1 and L0, the memory device receiving the data can determine where the write / program ends and where the extended data starts.

[0058] Figure 5-2 shows an extended data erasure operation according to an embodiment. From time t0 to t2, the extended data erasure operation can follow the actions described for Figure 5-0, but the command value (C) indicates the extended data erasure operation. Around time t3, after the encoded LEN data (L0, L1), the extended data (from eT0 to eT15) can be output at the rising and falling edges of SCK. In the illustrated embodiment, the extended data can be output with a burst length of 128 bits over 8 SCK cycles. Around time t4, CS# can terminate the extended data erasure transaction. In some embodiments, the LEN data can include metadata related to the erasure operation.

[0059] Figure 5-3 is a table showing command values according to an embodiment. In some embodiments, the command value can be a hexadecimal value and, thus, can be transmitted at the rising and falling edges of SCK as shown in Figures 5-0 to 5-2. In some embodiments, this type of command value can be latched at the first falling edge of SCK.

[0060] Figure 5-4 is a table showing the encoded LEN values (L1, L0) according to an embodiment. In the illustrated embodiment, the encoded LEN values can be 16 bits, and bits [0:12] can indicate the length of the transaction data in bytes. Bits [13:15] can include other data related to the corresponding extended data operation (e.g., indicating authentication without encryption), but can provide any other suitable data not limited thereto.

[0061] It should be understood that alternative embodiments can include operations without extended data that can provide transaction data (e.g., read data, write / program data) having a length indicated by L0, L1.

[0062] In this way, the memory device can decode the length data received after the command and address values on the serial bus and determine the transaction data length value. For extended data transactions, the memory device can determine where the transaction data ends and where the extended data starts. The decoded length data can also indicate additional information (e.g., metadata) for the indicated operation.

[0063] Figures 6-0 through 6-2 illustrate an extended data transaction in which LEN and other data can be included in the command value of a CMD / ADD sequence. Figure 6-0 shows an extended data read operation according to one embodiment. Prior to time t0, CS# can transition to active (i.e., low). At time t0, command data (C) 620 can be latched on the rising edge of SCK. Unlike some conventional serial read operations, rather than repeating the command data (C) on the falling edge, the encoded LEN data 621 can be latched on the falling edge of SCK. In some embodiments, the command data (C) 620 and / or the encoded data 621 can indicate an extended read operation. In the illustrated embodiment, the encoded LEN data 621 can include data on all eight SIO lines, with the three LSBs L[2:0] indicating the LEN value and the remaining bits C[7:3] indicating additional features of the extended data operation. After the extended data 621, at time t2, address data (A) can be latched on at least the rising edge of SCK. Around time t3, after many dummy cycles, the extended data read operation can follow the operation shown in Figure 5-0.

[0064] FIG. 6-1 shows an extended data write / program operation according to an embodiment. From time t0 to t2, the extended data write / program operation can follow the actions described for FIG. 6-0, but the command value (C) 620 and / or the encoded value 621 indicate the extended data write / program operation. Around time t3, the extended data write / program operation can follow the actions shown in FIG. 5-1.

[0065] FIG. 6-2 shows an extended data erase operation according to an embodiment. From time t0 to t2, the extended data erase operation can follow the actions described for FIG. 6-0, but the command value (C) 620 and / or the encoded value 621 indicate the extended data erase operation. Around time t3, the extended data write / program operation can follow the actions shown in FIG. 5-2.

[0066] FIG. 6-3 is a table showing the encoded LEN value received together with command data according to an embodiment. In the illustrated embodiment, the encoded LEN value can be 8 bits, and bits [2:0] can indicate the length of the extended data in bytes. Bits [7:3] can provide other data related to the corresponding transaction (e.g., authentication without encryption).

[0067] In this way, the memory device can decode the length data received together with the command value before the address value on the serial bus. From the data length value, the memory device can determine the size of the transaction data. The decoded extended length data can also indicate additional information for extended operations that utilize the extended data.

[0068] Figures 7-0 through 7-2 illustrate an extended data transaction that can include LEN and other data in the address value of a CMD / ADD sequence. Figure 7-0 shows an extended data read operation according to one embodiment. Prior to time t0, CS# can transition to active. At time t0, command data (C) 720 can be latched at least on the rising edge of SCK. After the command data (C), at time t1, address data (A) can be latched on the edge of SCK. Unlike some conventional serial read operations, rather than considering the data received after the command data to be only address data, at time t2, a mix of the address value and the encoded LEN data 721 can be latched. In some embodiments, the command data (C) can indicate an extended data read operation. In the illustrated embodiment, the data latched at time t2 can include the three MSBs A[7:5] of the address data, and the remaining five LSBs L[4:0] are the encoded LEN data. In some embodiments, in addition to the transaction data length LEN, the LSBs L[4:0] can indicate additional features of the extended data operation. In some embodiments, the number of bits dedicated to the encoded LEN data can be based on the data size of the transaction and the granularity of the address value. For example, if the memory device access for an application is aligned along 32-byte boundaries and the smallest data size is 1 byte, the five LSBs of the address are not needed and can be dedicated to encoding the LEN data. Around time t3, after many dummy cycles, the extended data read operation can follow the operation described for Figure 5-0.

[0069] FIG. 7-1 shows an extended data write / program operation according to an embodiment. From time t0 to t2, the extended data write / program operation can follow the actions described for FIG. 7-0, but the command value (C) indicates the extended data write / program operation. Around time t3, the extended data write / program operation can follow the operations described for FIG. 5-1.

[0070] FIG. 7-2 shows an extended data erase operation according to an embodiment. From time t0 to t2, the extended data write / program operation can follow the actions described for FIG. 7-0, but the command value (C) indicates the extended data erase operation. Around time t3, the extended data write / program operation can follow the operations described for FIG. 5-2.

[0071] FIG. 7-3 is a table showing the encoded LEN values according to an embodiment. In the illustrated embodiment, the encoded LEN value can be 4 bits, and bits [1:0] can indicate the length of the transaction data in bytes. Bits [5:2] can provide other data related to the corresponding operation (e.g., authentication without encryption).

[0072] In this way, the memory device can decode the data length value included in the address data and determine the transaction data length. From the data length value, the memory device can determine the number of clock cycles during which the transaction data is transmitted or received. In the extended data operation, LEN can also indicate the boundary between the transaction data and the extended data.

[0073] The systems and devices described in this specification show various methods, and additional methods are described below with reference to flowcharts. This type of method is executable by the circuits of the devices and / or systems described in this specification.

[0074] FIG. 8 is a flowchart of a method 870 according to an embodiment. The method is executable by a memory device. Method 870 can include, at 870-0, receiving, via serial IO in synchronization with a serial clock, a command, an address, and an encoded data length value. This kind of action can include receiving a CMD / ADD sequence according to any of the embodiments or equivalents described herein.

[0075] At 870-1, the received values can be decoded to determine one of many possible data length values. This kind of action can include decoding to determine a LEN value according to any of the embodiments or equivalents described herein. In some embodiments, this kind of action can also determine information indicating other features of an extended data operation (e.g., metadata) in addition to the LEN value.

[0076] At 870-2, at least a transaction data value having a length LEN can be transferable via serial IO in synchronization with a serial clock. This kind of action can include transmitting transaction data from a memory device or receiving transaction data at a memory device. In some embodiments, extended data exceeding the length LEN can be transmitted by the transaction data.

[0077] In this way, one of many transaction data length values can be encoded and included within a command address sequence, and transaction data of the indicated length can be included within a memory transaction.

[0078] FIG. 9 is a flowchart of another method 970 according to an embodiment. Method 970 is executed by a memory device, performs either a read, write / program, or erase operation, and this type of operation includes a version that includes extended data. At 970-0, in response to the CS signal becoming active, at 970-1, command data can be received in synchronization with the serial IO clock signal. This type of action can include receiving command data on one or more serial IO lines. At 970-2, address data can be received serially IO, in synchronization with the clock signal, after the command data. At 970-3, the LEN value and possibly other data can be received serially IO, in synchronization with the clock signal, after the address data. In some embodiments, the LEN value can be encoded as described herein or equivalently. Actions 970-0 through 970-3 can form a received CMD / ADD sequence. The LEN value can include data in addition to the transaction data length value, as described herein or equivalently. In some embodiments, portions of the CMD data and / or ADD data can indicate the addition of LEN data after the address data.

[0079] Referring further to FIG. 9, after the receipt of CMD / ADD and LEN data (970-1, -2, -3), at 970-4, a command can be executed. The CMD data is decodable. If the CMD data indicates a read transaction (from 970-5 to Y), at 970-6, data of length LEN stored at the address indicated by ADD can be output as read data in synchronization with the clock signal. If the read operation is an extended data read operation (from 970-7 to Y), at 970-8, extended data corresponding to the read data can be output in synchronization with the clock signal. In some embodiments, the extended data can follow (e.g., be appended to) the read data.

[0080] When the CMD data indicates a write or program transaction (from 970-9 to Y), in 970-10, the write or program data and the extended data of length LEN can be received in synchronization with the clock signal. When the write or program transaction includes extended data (from 970-7 to Y), in 970-11, the extended data can be output together with the write or program data.

[0081] In 970-12, optionally, the write or program transaction can be evaluated by the extended data. This type of action can include any extended evaluation or equivalents described in this specification, and the extended data can be used to authenticate the received write or program data, authenticate the received write or program command, and perform error detection and / or correction of the write or program data, or perhaps the corresponding command and address data, but is not limited thereto. If the write or program transaction fails the extended evaluation (from 970-12 to N), the received data shall not be written or programmed to the address indicated by ADD. If the write or program transaction passes the extended evaluation (from 970-12 to Y), or if the write or program transaction does not include extended data, in 970-13, the received data may be written or programmed to the address indicated by ADD.

[0082] When the CMD data indicates an erase transaction (from 970-14 to Y), and the erase transaction includes extended data (from 970-7 to Y), in 970-15, the erase transaction is evaluable by the extended data. This kind of action can include, but is not limited to, steps of performing authentication, error detection, or error correction on the erase transaction command and / or address data. If the erase transaction fails the extended evaluation (from 970-14 to N), the data at the address indicated by ADD shall not be erased. If the erase transaction passes the extended evaluation (from 970-14 to Y), or if the erase transaction does not include extended data (from 970-7 to N), in 970-16, the data at the address indicated by ADD may be erased.

[0083] In this way, the method can include the step of receiving LEN data after the CMD and ADD data, and the step of performing a read or write or program operation with the data of length LEN.

[0084] FIG. 10 is a flowchart of another method 1070 according to another embodiment. The method 1070 is executed by a memory device and can perform any of read, write / program, or erase operations. At 1070-0, in response to the CS signal becoming active, at 1070-1, CMD data including a LEN value can be received in serial IO synchronized with a clock signal. In some embodiments, this kind of action can include receiving the CMD at one edge of the serial clock (e.g., rising or falling), and receiving the LEN data at the opposite edge of the same clock (e.g., falling or rising). In some embodiments, the LEN value can be encodable and can include additional data regarding the extended operations or equivalents described herein. At 1070-2, ADD data can be received in serial IO, synchronized with the clock signal, after the command data. Actions 1070-0 through 1070-2 can be a CMD / ADD sequence. After receiving the CMD / LEN / ADD data (1070-1, -2), at 1070-4, an extended command can be executed. This kind of action 1070-4 can occur in the same way as that described for 970-4 in FIG. 9.

[0085] In this way, the method can include receiving LEN data along with CMD data followed by ADD data, and performing a read, write, or program operation on data of size LEN.

[0086] FIG. 11 is a flow diagram of another method 1170 according to a further embodiment. The method 1170 is executed by a memory device and can perform any of read, write / program, or erase operations. At 1170-0, in response to the CS signal becoming active, at 1170-1, the CMD data can be received in serial IO synchronized with the clock. This kind of action can occur as described for 970-1 of FIG. 9 or equivalently.

[0087] At 1170-2, after the CMD data, the ADD data including the LEN value can be received in serial IO synchronized with the clock signal. In some embodiments, this kind of action can include receiving the ADD data at one edge of the serial clock and receiving the LEN data at the opposite edge (e.g., falling or rising) of the same clock. In some embodiments, the data latched at the clock edge can include both ADD and LEN data. After receiving the CMD / ADD / LEN data (1170-1, -2), at 1170-4, the command can be executed. This kind of action 1170-4 can occur in the same way as described for 970-4 of FIG. 9.

[0088] In this way, the method can include receiving CMD data followed by ADD data having LEN data, and performing a read, write, or program operation with the data of size LEN.

[0089] FIG. 12 is a flow diagram of another method 1270 according to an embodiment. The method 1270 is executed by a memory controller device and can perform any of read, write, program, or erase operations. The method 1270 can generally follow FIG. 9, but can represent the memory controller side.

[0090] Method 1270 can include, at 1270-0, the step of activating the CS signal. At 1270-1, the CMD data can be transmitted on the serial IO in synchronization with the clock signal. At 1270-2, the ADD data can be transmitted on the serial IO in synchronization with the clock signal after the command data. At 1270-3, the LEN value and possibly other data can be transmitted on the serial IO in synchronization with the clock signal after the address data. The LEN value can be encoded as described herein or equivalently. Actions 1270-1 through 1270-3 can transmit the CMD / ADD sequence to the memory device. The LEN value can include data in addition to the extended data length value, as described herein or equivalently. In some embodiments, portions of the CMD data and / or ADD data can indicate the addition of LEN data after the address data.

[0091] Referring further to FIG. 12, after the transmission of CMD / ADD and LEN data (1270-1, -2, -3), at 1270-4, the command can be executed. If the transmitted CMD data indicates a read operation (from 1270-5 to Y), at 1270-6, the read data of length LEN can be received via serial IO in synchronization with the clock signal. In some embodiments, the read data can be received after some delay (e.g., a dummy cycle or other latency). If the read operation is an extended read operation (from 1270-7 to Y), at 1270-8, the extended data of length can be received via serial IO in synchronization with the clock signal. In some embodiments, the extended data can follow (e.g., be appended to) the read data. If the CMD data indicates a write or program transaction (from 1270-9 to Y), at 1270-10, the write or program data of length LEN can be transmitted via serial IO in synchronization with the clock signal. If the write or program operation is an extended data operation (from 1270-11 to Y), at 1270-12, the extended data can be transmitted via serial IO in synchronization with the clock signal. If the erase operation is an extended data operation (from 1270-7 to Y), at 1270-12, the extended data can be transmitted via serial IO in synchronization with the clock signal.

[0092] At 1270-4, after the execution of any command, at 1270-14, the CS signal can be deactivated.

[0093] In this way, the method can include the steps of transmitting LEN data after CMD and ADD data, and executing a read, write, program, or erase operation including transmitting transaction data having length LEN.

[0094] FIG. 13 and FIG. 14 are flowcharts of additional methods 1370 and 1470 according to the embodiment. FIG. 13 can include actions of the controller corresponding to FIG. 10. FIG. 14 can include actions of the controller corresponding to FIG. 11.

[0095] Referring to FIG. 13, method 1370 can include, at 1370-0, a step in which the CS signal becomes active. At 1370-1, CMD data including the LEN value can be transmitted in serial IO in synchronization with the clock signal. This type of data can take the form described for FIG. 10 or an equivalent form. At 1370-2, ADD data can be transmitted in serial IO in synchronization with the clock signal after the CMD data. Actions 1370-0 to 1370-2 can be a CMD / ADD sequence. After the transmission of the CMD / LEN / ADD data (1370-1, -2), at 1370-4, an extended command can be executed. This type of action 1370-4 can occur in the same manner as that described for 1270-4 of FIG. 12. At 1370-12, after any extended data command has been executed at 1370-4, the CS signal can be made inactive.

[0096] In this way, the method can include a step of transmitting LEN data together with CMD data followed by ADD data, and a step of performing a read, write, program, or erase operation of the extended data, including the transmission of the extended data of length LEN.

[0097] Figure 14 can include steps in which the CS signal becomes active at 1470-0. At 1470-1, the CMD data can be transmitted serially via the serial IO in synchronization with the clock. At 1470-2, after the CMD data, the ADD data including the LEN value can be transmitted serially via the serial IO in synchronization with the clock signal. This kind of combination of ADD and LEN values can occur as described for Figure 11 or equivalently. After the transmission of the CMD / ADD / LEN data (1470-1, -2), at 1470-4, an extended command can be executed. This kind of action 1470-4 can occur in the same way as described for 1270-4 in Figure 12. At 1470-4, after any extended data command has been executed, at 1470-12, the CS signal can be deactivated.

[0098] In this way, the method can include the step of transmitting CMD data followed by ADD data having LEN data, and the step of performing a read, write, program, or erase operation of extended data, including the transmission of extended data of length LEN.

[0099] FIG. 15 is a table showing commands received at the serial interface of a memory device according to one embodiment. The received commands can include standard commands including, but not limited to, a read command (READ), a fast read command (FAST_READ), a page program command (PP), and a sector erase command (SE). However, unlike conventional memory devices, this type of standard command can have a corresponding variable-length command, in which the amount of the transaction can be established by the encoded LEN value or equivalent included in the CMD / ADD sequence described herein. In the illustrated embodiment, the variable-length read command 1572-0 can establish the amount of read data having a LEN value. The variable-length program command 1572-1 can establish the amount of program data having a LEN value. FIG. 15 also shows an advanced sector erase command 1572-2. This type of command can utilize the metadata of the LEN value to control the manner of the sector erase operation.

[0100] In this way, in response to a particular received command, the memory device can execute a memory access transaction that can select the amount of data transmitted in the transaction. Additionally or alternatively, a particular received command can include metadata. The metadata can include, but is not limited to, data for indicating the characteristics of the transaction or data for controlling the characteristics of the transaction.

[0101] Embodiments can include any suitable type of memory array, although some embodiments can include a 1-transistor (1T) NOR type array. FIG. 16-0 is a schematic diagram of a 1T NOR array 1602-0 that can be included in an embodiment. The array 1602-0 can include many memory cells (one shown as 1674) arranged in rows and columns, where the memory cells in the same row are connected to the same word line (one shown as 1676), and the memory cells in the same column are connected to the same bit line (one shown as 1678). In some embodiments, the memory cell (1674) can be formed by a single transistor structure having a charge storage structure 1674-0 between a control gate and a channel. The charge storage structure 1674-0 can store one or more bits of data as charge (including the absence of charge) without requiring power to maintain the data. The charge storage structure 1674-0 can take any suitable form including, but not limited to, a floating gate, a charge storage dielectric (e.g., replacement gate), or combinations thereof. However, embodiments can include any other suitable non-volatile memory cell type.

[0102] In some embodiments, commands and equivalents having the embedded LEN values described herein are used to access non-volatile memory cells and enable reading data from a NOR type memory device having a selectable data transaction size (e.g., length), including an execution-in-place (XiP) code read operation.

[0103] Embodiments can also include any suitable volatile array structure or volatile memory cell type. FIG. 16-1 is a schematic diagram of a possible volatile memory cell array that can be included in an embodiment. FIG. 16-1 shows an array 1602-1 that can include many volatile memory cells (one shown as 1680) arranged in rows and columns and connected to one or more bit lines (e.g., 1678) and word lines (e.g., 1676). The volatile memory cells (1680) can take any suitable form including, but not limited to, DRAM cells 1680-0 and / or SRAM cells 1680-1. The SRAM cells 1680-1 can include, but are not limited to, 4-transistor (4T), 6T, and / or 8T variations.

[0104] Embodiments can include devices and systems having various interconnected components, but embodiments can also include a single device capable of performing the extended data memory device transactions and equivalents described herein. In some embodiments, this type of single device can advantageously be a compact single integrated circuit (i.e., chip). FIG. 17 shows a packaged memory IC device 1700 capable of performing extended data transactions according to embodiments described herein. A CMD / ADD sequence with embedded LEN data can be received, and a selected amount of transaction data can be input or output on one or more external connections (one shown as 1782). However, memory devices according to embodiments can include any other suitable integrated circuit packaging type, such as directly bonding the device chip to a circuit board or substrate.

[0105] In this way, the IC memory device can perform extended data memory transactions.

[0106] Embodiments can include a memory device that executes a memory access transaction having a selectable transaction data size. Embodiments can also include a memory controller circuit that can execute this type of transaction on an interface that is compatible with the memory device. This type of memory controller can be part of a host device. FIG. 18-0 shows a memory controller 1840 according to one embodiment. The memory controller 1840 can include a processing circuit 1842, an IF circuit 1844, a command queue 1846-0, a write queue 1846-1, and a read queue 1846-2. The processing circuit 1842 can include a LEN data command generation circuit 1842-0 and a LEN data operation circuit 1842-1.

[0107] The command queue 1846-0, the write queue 1846-1, and the read queue 1846-2 can be connectable to a controller IF 1848 that can be part of a larger host device, or can be connectable to the host device via a communication path. The command queue 1846-0 can receive a memory request via the controller IF 1848 and access a memory device connected to the bus 1818. The write data queue 1846-1 can receive write or program data (e.g., data to be stored in the memory device) associated with the memory request. The read data queue 1846-2 can provide read data (e.g., data read from the memory device) resulting from the memory request.

[0108] In some embodiments, the LEN data command generation circuit 1842-0 can distinguish memory access requests received through the command queue 1846-0 into some requests that result in a CMD / ADD sequence with an encoded LEN data value and other requests that result in a standard CMD / ADD sequence (i.e., a sequence without encoded LEN bits). However, in other embodiments, this kind of distinction cannot be made, and all memory access requests may result in generating a CMD / ADD sequence with an encoded LEN value. The transaction can take any form described herein or an equivalent. The LEN data operation circuit 1842-1 can execute operations according to any of the embodiments or equivalents described herein, and the operations include, but are not limited to, distinguishing transaction data and extended data according to the LEN value. The interface 1844 and the corresponding bus 1818 can be any suitable bus including, but not limited to, a bidirectional serial bus.

[0109] In this way, the memory controller can generate a CMD / ADD sequence with a transaction data length value for processing by the memory device in response to a memory access request.

[0110] Embodiments can include a system having a memory device that operates in conjunction with a host device. Embodiments can also include a stand-alone host device having a LEN command generation and operation circuit and one or more memory device IFs formed within a single IC package. This type of embodiment is shown in FIG. 18-1. FIG. 18-1 shows a packaged host device in perspective top view 1840-0 and bottom view 1840-1. The host device 1840-0 / 1 can include a number of physical connections (e.g., 1850), all or some of which can be connectable to the memory device IFs described herein. This type of IF can perform data transactions and equivalents for processing as described herein. In some embodiments, the host device can be a system-on-chip (SoC) type device. It should be understood that the host device can include any other suitable package type.

[0111] In this way, the IC host device can generate a data transaction having a selectable transaction data size in response to a request received through the controller IF.

[0112] FIG. 19 is a table showing the memory address space 1984 of a system according to an embodiment. The memory address space 1984 can include physical addresses (ADDRESS) having various data stored therein (including firmware 1984-0). In some embodiments, some or all accesses to addresses assigned to firmware (e.g., from 0x4000000 to 0x4005000) are accessible by a selectable transaction data size as described herein or equivalently (1985).

[0113] In this way, the system can allocate memory device access transactions of selectable data sizes to one or more regions of the system memory space.

[0114] FIG. 20 is a flowchart of a method 2090 according to another embodiment. The method 2090 is executable by a host device. The method 2090 can include, at 2090-0, storing firmware in non-volatile memory. In some embodiments, this kind of action can include, as described herein or equivalently, transmitting a program CMD / ADD sequence having a selected program data size, but is not limited thereto. Thereafter, when a firmware access occurs (from 2090-1 to Y), at 2090-2, this kind of memory access can be a data transaction that directly accesses non-volatile memory having a selectable data transaction size (e.g., size by LEN). In some embodiments, this kind of access can be an XiP type of access, and thus, does not include the time or extra components associated with copying firmware to volatile memory, like some conventional approaches.

[0115] In this way, in response to a firmware access, the host device can execute a data transaction having a selectable data transaction size.

[0116] Embodiments can include any suitable system that can benefit from fast, secure, and flexible access to a memory such as a non-volatile memory. Embodiments can advantageously be used in systems that access code from a secure memory device with high reliability, such as an automotive system. FIG. 21 shows an automotive system 2130-0 according to one embodiment. The system 2130-0 can include a first NVM device 2100-0, a second NVM device 2100-1, a SoC (2140-0), an automotive microcontroller (MCU) 2140-1, sensors 2192, an automatic control 2194-0, an automatic communication system 2194-1, an automatic power system 2194-2, and optionally, a dynamic random access memory (DRAM) device 2186. The NVM devices 2100-0 / 1 can execute transactions of variable data sizes (LEN Ops) 2106-20 / 21. The SoC (2140-0) and the MCU (2140-1) can generate a CMD / ADD sequence having LEN values (LEN Ops) 2140-20 / 21.

[0117] The SoC (2140-0) and the first NVM device 2100-0 can be a host device and a corresponding NVM device according to any of the embodiments shown in the present specification. Thus, the SoC (2140-0) can securely execute the code stored in place in the NVM device 2100-0 using data transactions with variable data lengths, eliminating the need to copy this type of code to "shadow" volatile memory for authentication before execution. The transaction can include a read operation with extended data for authenticating the code, and the LEN value is used to define the boundary where the read data ends and the corresponding authentication data begins. Similarly, the MCU (2140-1) and the second NVM device 2100-1 can be a host device and a corresponding NVM device according to any of the embodiments or equivalents shown in the present specification. Thus, the MCU (2140-1) can include XiP operations and any other appropriate operations using data transactions with the LEN value 2140-21 for accessing the code.

[0118] Although it can include the DRAM device 2186, since the SoC / MCU (2140-0 / 1) can execute the code instead of the NVM device 2100-0 / 1, this type of device can serve purposes other than shadowing code.

[0119] In this way, an automotive control system can include one or more non-volatile memory devices that execute data transactions with a variable data transaction size by a controller device.

[0120] Referring to FIG. 22, an automotive system 2296 according to one embodiment is shown in the drawing. The automotive system 2296 can have a number of subsystems (one shown as 2300-0 and 2300-1) that are operated by firmware accessed from an NVM device. This type of subsystem (2230-0, 2230-1) can include an electronic control unit (ECU) and / or an advanced driver assistance system (ADAS). However, in other embodiments, this type of subsystem can include, as just two of a number of possible examples, a dashboard display / control subsystem and / or an infotainment subsystem. Each subsystem (2230-0, 2230-1) can include at least one host device and one or more NVM devices that can execute extended data transactions as described herein or equivalently. This type of transaction can include, but is not limited to, a selectable data transaction size, authentication, error correction, or error detection.

[0121] In this way, the vehicle can benefit from variable data size transactions with the NVM device.

[0122] Embodiments can include methods, devices, and systems, the method including receiving at a serial IO of a memory device, synchronized with a serial clock, at least a command value, an address value, and an encoded length value; and determining from the at least the command value, the address value, and the encoded length value, a memory access operation, a memory array location, and one LEN of a plurality of different LEN values corresponding to the memory access operation. At least data of one length LEN can be transmitted at the serial IO, synchronized with the serial clock, during execution of the memory access operation.

[0123] Embodiments can include a method, a device, and a system. The device has a memory cell array and a decoder circuit. The decoder circuit is configured to determine a memory access operation from a command value, determine a memory cell array location from an address value, and determine one of a plurality of different data length values (LEN) from an encoded data length value. The control circuit can be configured to access the memory cell array location according to the memory access operation. The IO circuit can include a serial clock input configured to receive a serial clock, and at least one serial IO. The at least one serial IO is configured to receive a command value, an address value, and an encoded extended data length value in synchronization with the serial clock, and transfer at least data of length LEN.

[0124] Embodiments can include a method, a device, and a system. The system has a memory device including a memory cell array and a control circuit. The control circuit is configured to determine a memory access operation and location from a command and an address value, determine one of a plurality of data length values (LEN) from an encoded data length value, and access the memory cell array location according to the memory access operation. The IO circuit can be configured to receive a command value, an address value, and an encoded extended data length value at the serial IO in synchronization with the serial clock, and transfer at least data of length LEN. The serial bus can be coupled to at least the IO circuit.

[0125] Methods, devices, and systems according to embodiments can include receiving command bits in synchronization with a serial clock, receiving address bits after the command bits in synchronization with the serial clock, and receiving LEN bits after the address bits in synchronization with the serial clock.

[0126] A method, device, and system according to an embodiment can include receiving a first set of command bits in synchronization with a serial clock, receiving a second set of command bits and LEN bits after the first set in synchronization with the serial clock, and receiving address bits after the second set in synchronization with the serial clock.

[0127] A method, device, and system according to an embodiment can include receiving command bits in synchronization with a serial clock, receiving a first set of address bits after the command bits in synchronization with the serial clock, and receiving a second set of address bits and LEN bits after the first set in synchronization with the serial clock.

[0128] A method, device, and system according to an embodiment can include a selectable transaction data size that is a multiple of X, where X is an integer.

[0129] A method, device, and system according to an embodiment can include determining that a memory access operation is a read operation, and at least the step of transferring data of at least one length LEN includes transferring read data of length LEN stored at an address via serial IO.

[0130] A method, device, and system according to an embodiment can include determining that a memory access operation is an authenticated read operation, and at least the step of transferring data of at least one length LEN includes transferring read data of length LEN stored at an address via serial IO, followed by authentication data for authenticating the read data, from a memory device.

[0131] The method, device, and system according to the embodiment can include a step of determining that a memory access is a program or write operation, and at least the step of transferring data of at least one length LEN includes receiving program or write data of length LEN at the serial IO of the memory device.

[0132] The method, device, and system according to the embodiment can include a step of determining that a memory access is an authenticated program or write operation, and at least the step of transferring data of at least one length LEN includes receiving program or write data of length LEN followed by authentication data at the serial IO of the memory device, where the authentication data is for authenticating at least the write or program data.

[0133] The method, device, and system according to the embodiment can include a step of determining LEN for a memory access operation by the operation of a host device, and in response to a request to access a memory space corresponding to the memory device, synchronizing with a serial clock and transmitting at least a command, an address, and an LEN value to the serial IO.

[0134] The method, device, and system according to the embodiment can include a memory cell array including non-volatile memory cells.

[0135] The method, device, and system according to the embodiment can include a serial clock input and at least one serial IO that are compatible with at least one Serial Peripheral Interface (SPI) standard.

[0136] In the method, device, and system according to the embodiment, the IO circuit is configured to receive command data bits in synchronization with a serial clock, receive address data bits after the command bits in synchronization with the serial clock, and receive encoded LEN bits after the address bits in synchronization with the serial clock.

[0137] In the method, device, and system according to the embodiment, the IO circuit is configured to receive a first set of command data bits in synchronization with a serial clock, receive a second set of command data bits and encoded LEN bits after the first set in synchronization with the serial clock, and receive address data bits after the second set in synchronization with the serial clock.

[0138] In the method, device, and system according to the embodiment, the IO circuit is configured to receive command data bits in synchronization with a serial clock, receive a first set of address data bits after the command bits in synchronization with the serial clock, and receive a second set of address bits and encoded LEN bits after the first set in synchronization with the serial clock.

[0139] In the method, device, and system according to the embodiment, the IO circuit is configured to receive a command value, an address value, and an encoded extended length value in a format selected from the following groups: receiving command bits followed by address bits followed by encoded extended length bits; and receiving command bits followed by encoded extended length bits followed by address bits.

[0140] The method, device, and system according to the embodiment can include a host device, where the host device is configured to generate a first command value, a first address value, and an encoded extended length value in an authenticated read operation, a command address generator circuit, an authentication circuit configured to authenticate at least read data with corresponding extended data, and a host IO circuit. The host IO circuit can be coupled to a serial bus and is configured to transmit the first command value, the first address value, and the first encoded extended data length value in host serial IO synchronously with a serial clock, and to receive read data of length LEN and corresponding extended data.

[0141] The method, device, and system according to the embodiment can include a memory device having a memory cell array including non-volatile memory cells configured to store code, and a host device including a processor circuit configured to directly execute the code from the memory device in an authenticated read operation.

[0142] Throughout this specification, references to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Therefore, it should be emphasized and recognized that two or more references to "an embodiment" or "one embodiment" or "alternative embodiments" in various parts of this specification do not necessarily all refer to the same embodiment. Further, the particular features, structures, or characteristics may be suitably combined in one or more embodiments of the present invention.

[0143] Similarly, in the exemplary embodiments of the present invention described above, in order to rationalize the disclosure that aids in understanding one or more of the various aspects of the present invention, it should be understood that sometimes they are grouped together in a single embodiment, drawing, or description thereof. However, this manner of disclosure should not be construed as representing an intention that the claims require more features than those explicitly recited in each claim. Rather, an aspect of the invention has less than all the features of a single described embodiment of the disclosure above. Accordingly, the claims following the detailed description are expressly incorporated into this detailed description, and each claim stands on its own as a separate embodiment of the present invention.

[0144] The present invention has been described with reference to the illustrated embodiments, but the description of this specification is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrated embodiments as well as other embodiments of the present invention will become apparent to those skilled in the art upon reference to the description of this specification. Therefore, it is intended that the appended claims cover any such modifications or embodiments.

Claims

1. receiving metadata at a serial input / output (IO) of a memory device synchronous to a serial clock, the metadata including at least a command value, an address value, and an encoded length value; from said at least a command value, an address value, and an encoded length value; A memory access operation; a memory array location; a data length value (LEN) of a plurality of different data length values ​​corresponding to the memory access operation; determining transferring, during execution of the memory access operation, at least data having a length corresponding to the one LEN of the plurality of different LENs, over the serial IO in synchronization with the serial clock; The method includes:

2. The step of receiving at least a command value, an address value, and metadata includes: receiving command bits synchronously with the serial clock; receiving address bits after the command bits synchronously with the serial clock; receiving a LEN bit after the address bits synchronously with the serial clock; Including, The method of claim 1.

3. The step of receiving at least a command value, an address value, and metadata includes: receiving a first set of command bits synchronously with the serial clock; receiving a second set of command bits and a LEN bit after the first set synchronously with the serial clock; receiving address bits after the second set synchronously with the serial clock; Including, The method of claim 1.

4. The step of receiving at least a command value, an address value, and metadata includes: receiving command bits synchronously with the serial clock; receiving a first set of address bits after the command bits synchronously with the serial clock; receiving a second set of address bits and a LEN bit after the first set synchronously with the serial clock; Including, The method of claim 1.

5. the plurality of distinct data length values ​​being a multiple of X, where X is an integer; The method of claim 1.

6. The method further includes determining that the memory access operation is a read operation; The step of transferring at least the data having the length corresponding to the one LEN among the plurality of LENs includes a step of transferring, from the memory device, read data of the length LEN stored at an address corresponding to an address value, by the serial IO; The method of claim 1.

7. The method further includes determining that the memory access operation is an authenticated read operation; the step of transferring at least the data having the length corresponding to the one LEN of the plurality of LENs includes transferring, on the serial IO, read data of length LEN from the memory device at an address corresponding to the address value, followed by authentication data for authenticating the read data; The method of claim 1.

8. The method further includes determining that the memory access operation is a program or write operation; transferring at least the data having the length corresponding to the one LEN of the plurality of LENs includes receiving program or write data of length LEN at the serial IO of the memory device; The method of claim 1.

9. The method further includes determining that the memory access operation is an authorized program or write operation; transferring at least the data having the length corresponding to the one LEN of the plurality of LENs includes receiving, at the serial IO of the memory device, program or write data of length LEN followed by authentication data, the authentication data for authenticating at least the write or program data; The method of claim 1.

10. The method comprises: determining a LEN for a memory access operation by operation of a host device; transmitting metadata, including at least a command value, an address value, and the encoded length value, to the serial IO synchronously with the serial clock in response to a request to access a memory space corresponding to the memory device; Further comprising: The method of claim 1.

11. 1. A device comprising a memory cell array, a decoder circuit, a control circuit, and an input / output (IO) circuit, The decoder circuit includes: Determine the memory access operation from the command value; determining a memory cell array position from the address value; determining a data length value (LEN) of a plurality of different data length values ​​from an encoded data length value included in the metadata; the control circuitry is configured to access the memory cell array locations in accordance with the memory access operations; The input / output (IO) circuit includes: a serial clock input configured to receive a serial clock; At least one serial IO; Equipped with The at least one serial IO is receiving a command value, an address value and the metadata synchronously with the serial clock; configured to transfer at least data of said length LEN; device.

12. the memory cell array comprises non-volatile memory cells; The device of claim 11.

13. the serial clock input and at least one serial IO are compatible with at least one Serial Peripheral Interface (SPI) standard; The device of claim 11.

14. The IO circuit includes: receiving command data bits synchronously with said serial clock; receiving address data bits after the command data bits in synchronization with the serial clock; receiving an encoded LEN bit after the address data bits in synchronization with the serial clock; The device of claim 11.

15. The IO circuit includes: receiving a first set of command data bits synchronously with the serial clock; receiving a second set of command data bits and an encoded LEN bit after the first set synchronously with the serial clock; receiving address data bits after the second set synchronously with the serial clock; The device of claim 11.

16. The IO circuit includes: receiving command data bits synchronously with said serial clock; receiving a first set of address data bits after the command data bits synchronously with the serial clock; receiving a second set of address bits and an encoded LEN bit after the first set in synchronization with the serial clock; The device of claim 11.

17. 1. A system comprising a memory device and a serial bus, the memory device includes a memory cell array, a control circuit, and an input / output (IO) circuit; The control circuit includes: determining a memory access operation and location from the command and address value; determining a data length value (LEN) of a plurality of data length values ​​from an encoded data length value included in the metadata; configured to access memory cell array locations in accordance with the memory access operations; The input / output (IO) circuit includes: receiving a command value, an address value and said metadata on a serial IO in synchronization with a serial clock; configured to transfer at least data of said length LEN; the serial bus is coupled to at least the IO circuit; system.

18. The IO circuits are of the following group: receiving command bits followed by address bits followed by encoded extension length bits; receiving command bits, followed by encoded length bits, followed by address bits; configured to receive a command value, an address value, and an encoded extension length value in a format selected from 20. The system of claim 17.

19. The system further includes a host device. The host device includes: a command address generator circuit configured to generate metadata for an authenticated read operation, the metadata including a first command value, a first address value, and an encoded length value; an authentication circuit configured to authenticate at least the read data with corresponding authentication data; a host IO circuit coupled to the serial bus; Including, The host IO circuit includes: transmitting the first command value, a first address value and the metadata over a host serial IO synchronously with the serial clock; configured to receive read data of length LEN and corresponding authentication data; 20. The system of claim 17.

20. the memory device includes a memory cell array comprising non-volatile memory cells configured to store code; the host device includes a processor circuit configured to execute the code directly from the memory device upon an authenticated read operation; 20. The system of claim 19.

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