Imaging device

Abstract

To provide an imaging device that outputs development data in a predetermined transmission format.SOLUTION: An imaging device includes a development processing unit for generating development data based on an imaging signal, and a plurality of channels and fields. For a predetermined transmission format including a plurality of fields in which at least one field is allocated to each different channel among a plurality of channels, when an imaging signal is output, first pixel data is arranged in at least one field, second pixel data corresponding to a position of the first pixel data in the development data is divided into a plurality of fields and arranged, and development data is output in a predetermined transmission format to an external device via a connection member connected to the external device.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to an imaging device.

Background Art

[0002] When using the imaging device described in Non-Patent Document 1, a moving image developed by the imaging device can be transmitted to an external recording device connected to the imaging device via an SDI (Serial Digital Interface) cable or an HDMI (High Definition Multimedia Interface) (registered trademark) cable. In the image transmission recording system according to the prior art, there has been a problem that the transmission is limited to the image after development.

Prior Art Documents

Non-Patent Documents

[0003]

Non-Patent Document 1

Summary of the Invention

[0004] According to a first aspect of the present invention, an imaging device includes an image sensor that captures a subject and outputs an imaging signal, a development processing unit that generates development data based on the imaging signal, and a plurality of fields and channels, and at least one field includes a plurality of fields respectively assigned to different channels among the plurality of channels. When outputting the imaging signal for a predetermined transmission format, first pixel data is arranged in the at least one field, and second pixel data corresponding to the position of the first pixel data in the development data is divided and arranged in the plurality of fields, and the development data is output to an external device in the predetermined transmission format via a connection member connected to the external device. And an output control unit.

Brief Description of the Drawings

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DETAILED DESCRIPTION OF THE INVENTION

[0006] An image transmission and recording system according to the prior art will be described below with reference to FIGS. 1 to 4. FIG. 1 is an example of a block diagram of an image transmission and recording system 10 according to the prior art. The conventional image transmission and recording system 10 includes an imaging device 20, an image recording device 40 which is an external device of the imaging device 20, and an HDMI cable 30 which is a connection member connecting the imaging device 20 and the image recording device 40.

[0007] The imaging device 20 includes an imaging device control unit 21, an image sensor 22, a sensor data input circuit 23, a data memory 24, a development processing unit 25, an output control unit 26, and a display unit 27. The imaging device control unit 21 is composed of, for example, a microprocessor and a memory, and controls the entire imaging device 20, that is, the imaging device control unit 21, the image sensor 22, the sensor data input circuit 23, the data memory 24, the development processing unit 25, the output control unit 26, and the display unit 27 by running a computer program.

[0008] The image sensor 22 has a plurality of photoelectric conversion elements, and images an object's image through an optical system (not shown) to output an imaging signal. The sensor data input circuit 23 performs detection processing on the imaging signal output from the image sensor 22, and performs synchronization processing between the imaging signal and the audio signal, and calculation processing of white balance data and gamma data, for example, in frame units. The RAW data 241 of the imaging signal, the audio signal data, the white balance data, and the gamma data are stored in the register area or the data memory 24 of the sensor data input circuit unit 23 in frame units. Here, the RAW data 241 is data based on the imaging signal output from the image sensor 22. The color information recognizable by the data of one pixel of the RAW data 241 is the color information per pixel in a color filter (not shown) provided in the image sensor 22. The color filter transmits only light of a predetermined color, for example, only the red component R. The image sensor 22 is provided with color filters that transmit the red component R, the green component G, and the blue component B, respectively. For example, the color filters that transmit the red component R, the green component G, and the blue component B are arranged in a Bayer array. The RAW data 241 is data based on the imaging signal before debayering.

[0009] The development processing unit 25 generates development data 242 such as YUV data and / or RGB data based on the RAW data 241 stored in the data memory 24. The RGB data is generated by representing the color information of a pixel by a combination of the red component R, the green component G, and the blue component B, which are the three primary colors of light. The YUV data is generated by representing the color information of a pixel by a combination of the luminance component Y, the color difference component U between the luminance component and the blue component, and the color difference component V between the luminance component and the red component. Also, display output adjustment processing based on the white balance data and the gamma data is performed. In the following, the YUV data will be described as the development data, but the RGB data can be handled in the same way. The development data 242 generated by the development processing unit 25 is stored in the data memory 24. The development data 242 is data that can be displayed on the display unit 27.

[0010] The output control unit 26 includes a display output control unit 261 and an external output control unit 262, and reads out the development data 242 stored in the data memory 24. The display output control unit 261 synchronizes the development data 242 with an audio signal in frame units under the control of the imaging device control unit 21, and thereby displays an image on the display unit 27 in frame units. At this time, the display output control unit 261 outputs audio to a speaker or earphone (not shown) based on the audio signal associated with the frame. Note that the output control unit 26 may perform display output adjustment processing A1 based on white balance data and gamma data.

[0011] The external output control unit 262 performs a read process A2 of reading out the development data 242 while associating an audio signal with the development data 242 in frame units under the control of the imaging device control unit 21. The external output control unit 262 can transmit the development data 242 and the audio signal to the image recording device 40 via the HDMI cable 30 by arranging them in a predetermined field in the HDMI transmission format.

[0012] The image recording device 40 includes an image recording device control unit 41, an external input control unit 42, an image processing unit 43, a storage device 44, a display output control unit 45, and a display unit 46. The image recording device control unit 41 is composed of, for example, a microprocessor and a memory, and controls the entire image recording device 40, that is, the image recording device control unit 41, the external input control unit 42, the image processing unit 43, the storage device 44, the display output control unit 45, and the display unit 46 by running a computer program.

[0013] The external input control unit 42 receives the development data 242 and the audio signal from the imaging device 20 via the HDMI cable 30, that is, acquires the development data 242 and the audio signal arranged in a predetermined field in the HDMI transmission format and transfers them to the image processing unit 43. The image processing unit 43 stores the development data 242 and the audio signal in the storage device 44 in frame units and delivers them to the display output control unit 45.

[0014] The display output control unit 45, under the control of the image recording device control unit 41, performs synchronization processing with an audio signal and display output adjustment processing based on white balance data and gamma data on a frame-by-frame basis for the developed data 242 received from the image processing unit 43, thereby displaying an image on a frame-by-frame basis on the display unit 46. At that time, the display output control unit 261 outputs sound to a speaker or earphone (not shown) based on the audio signal associated with that frame.

[0015] 2A and 2B are diagrams illustrating developed data 242 stored in the data memory 24 in the imaging device 20 according to the prior art, and an image displayed on the display unit 27 based on the developed data 242. FIG. 2A shows a pixel sequential method (pixel sequential method) for Y pixel data 1, U pixel data 2, and V pixel data 3 in the data memory 24 when YUV data as the developed data 242 is configured in, for example, a YUV444 format. 2(a) shows an example of arrangement using a pixel arrangement technique (interleaving). Y pixel data 1, U pixel data 2, and V pixel data 3 are repeatedly arranged in order in the horizontal direction Ma of the data memory 24, and the YUV pixel data string thus formed is juxtaposed in the vertical direction Mb of the data memory 24. In particular, the first row L1 and the next row L2 are illustrated as an example in FIG. 2(a).

[0016] Fig. 2(b) shows an example of dot sequential arrangement of Y pixel data 1, U pixel data 2, and V pixel data 3 in the data memory 24 when the YUV data as the developed data 242 is configured in, for example, a YUV422 format. Y pixel data 1, U pixel data 2, Y pixel data 1, and V pixel data 3 are arranged in order in the horizontal direction Ma of the data memory 24, and the arrangement of these four pixels is repeated. The YUV pixel data string thus formed is juxtaposed in the vertical direction Mb of the data memory 24. Fig. 2(b) particularly illustrates the first row L1 and the next row L2.

[0017] Figure 2(c) shows an example of the arrangement in a planar format within the data memory 24 of the Y pixel data 1, U pixel data 2, and V pixel data 3 when the YUV data is configured in, for example, the YUV444 format or the YUV422 format as the developed data 242. In each row from the first row L1 to the row Li-1 at the beginning of the data memory 24, only the Y pixel data 1 is repeatedly arranged in the horizontal direction Ma. In each row from the row Li to the row Lj-1, only the U pixel data 2 is repeatedly arranged in the horizontal direction Ma. In each row after the row Lj, only the V pixel data 3 is repeatedly arranged in the horizontal direction Ma, and these rows are juxtaposed in the vertical direction Mb of the data memory 24. In Figure 2(c) in particular, the first row L1 where only the Y pixel data 1 is repeatedly arranged, the first row Li where only the U pixel data 2 is repeatedly arranged, and the first row Lj where only the V pixel data 3 is repeatedly arranged are illustrated.

[0018] Figure 2(d) shows an example of the arrangement in a semi-planar format within the data memory 24 of the Y pixel data 1, U pixel data 2, and V pixel data 3 when the YUV data is configured in, for example, the YUV422 format as the developed data 242. In each row from the first row L1 to the row Lk-1 at the beginning of the data memory 24, only the Y pixel data 1 is repeatedly arranged in the horizontal direction Ma. In each row after the row Lk, the U pixel data 2 and the V pixel data 3 are repeatedly arranged in order in the horizontal direction Ma, and these rows are juxtaposed in the vertical direction Mb of the data memory 24. In Figure 2(d) in particular, the first row L1 where only the Y pixel data 1 is repeatedly arranged and the first row Lk where the U pixel data 2 and the V pixel data 3 are repeatedly arranged in order are illustrated.

[0019] Figure 2(e) is a diagram illustrating an image developed in the YUV444 format input to the display unit 27 of the imaging device 20. This image is composed of a plurality of pixels arranged in the horizontal direction Ia and the vertical direction Ib, and the data of each pixel includes the Y pixel data 1, the U pixel data 2, and the V pixel data 3, each for one pixel.

[0020] FIG. 2(f) is a diagram illustrating an image developed in the YUV422 format and input to the display unit 27 of the imaging device 20. This image is composed of a plurality of pixels arranged in the horizontal direction Ia and the vertical direction Ib. As pixel data for each row, pixel data including one pixel each of Y pixel data 1, U pixel data 2, and V pixel data 3, and pixel data including only Y pixel data 1 are repeatedly arranged in order.

[0021] FIG. 3 is a diagram for explaining an example of a transmission format when development data 242 is output from the imaging device 20 according to the prior art via the HDMI cable 30. FIG. 3(a) shows an arrangement example in the dot sequential method in the data memory 24 of each 16-bit Y pixel data 1, U pixel data 2, and V pixel data 3 when the YUV data is configured in the YUV444 format 48-bit mode as the development data 242. In row L1, the state where the pixel data of each 16-bit pixel Y00, U00, V00, Y01, U01, V01, Y02, U02, and V02 is arranged in order in the horizontal direction Ma is shown. Further, in row L2 following row L1, the state where the pixel data of each 16-bit pixel Y10, U10, V10, Y11, U11, V11, Y12, U12, and V12 is arranged in order in the horizontal direction Ma is shown.

[0022] Figs. 3(b) and (c) are diagrams showing an example of a transmission format. Figs. 3(b) and (c) show the transmission format used by the external output control unit 262 of the imaging device 20 to transmit the pixel data arranged in the rows L1 and L2 shown in Fig. 3(a) via an HDMI cable. Horizontally, the clock intervals from 0 to 5 are exemplified, and time elapses as it progresses from interval 0 to 5. In each clock interval, three channels from channel 0 to 2 are provided, and data of 8 bits each can be accommodated in the fields assigned to each channel. That is, in Figs. 3(b) and (c), a total of 24 bits of data can be accommodated in each clock interval. However, since the YUV data is in the YUV444 format 48-bit mode, by using two intervals of clocks, a total of 48 bits of data for one pixel each of the Y pixel data 1, U pixel data 2, and V pixel data 3 are accommodated in a total of six fields of 8 bits each.

[0023] Therefore, in the example shown in Fig. 3(b), in channel 0 at clock interval 0, 0 to 7 bits of the 16-bit pixel data of pixel Y00 arranged in row L1 are accommodated, and in channel 0 at clock interval 1, 8 to 15 bits of the 16-bit pixel data of pixel Y00 are accommodated. In channel 1 at clock interval 0, 0 to 7 bits of the 16-bit pixel data of pixel U00 arranged in row L1 are accommodated, and in channel 1 at clock interval 1, 8 to 15 bits of the 16-bit pixel data of pixel U00 are accommodated. In channel 2 at clock interval 0, 0 to 7 bits of the 16-bit pixel data of pixel V00 arranged in row L1 are accommodated, and in channel 2 at clock interval 1, 8 to 15 bits of the 16-bit pixel data of pixel V00 are accommodated. The same mapping process is performed for the pixel data of pixels Y01, U01, V01, Y02, U02, and V02 arranged in row L1.

[0024] In the example shown in FIG. 3(c), for channel 0 at the time of clock interval 0, among the 16-bit pixel data of pixel Y10 arranged in row L2, data from bit 0 to bit 7 is accommodated, and for channel 0 at the time of clock interval 1, among the 16-bit pixel data of pixel Y10, data from bit 8 to bit 15 is accommodated. For channel 1 at the time of clock interval 0, among the 16-bit pixel data of pixel U10 arranged in row L2, data from bit 0 to bit 7 is accommodated, and for channel 1 at the time of clock interval 1, among the 16-bit pixel data of pixel U10, data from bit 8 to bit 15 is accommodated. For channel 2 at the time of clock interval 0, among the 16-bit pixel data of pixel V10 arranged in row L2, data from bit 0 to bit 7 is accommodated, and for channel 2 at the time of clock interval 1, among the 16-bit pixel data of pixel V10, data from bit 8 to bit 15 is accommodated. The same mapping process is performed for the pixel data of pixels Y11, U11, V11, Y12, U12, and V12 arranged in row L2.

[0025] Next, the case of transmitting YUV422 data composed of 12 bits for each component in the conventional transmission format in order to transmit in the YUV422 format 24-bit mode as shown in FIG. 2(b) will be described below.

[0026] For channel 0 at the time of clock interval 0, data from bit 0 to bit 3 among the 12-bit pixel data of pixel Y00 arranged in row L1 and data from bit 0 to bit 3 among the 12-bit image data of pixel Y01 arranged in row L1 are accommodated. Also, for channel 0 at the time of clock interval 1, data from bit 0 to bit 3 among the 12-bit pixel data of pixel U00 arranged in row L1 and data from bit 0 to bit 3 among the 12-bit pixel data of pixel V00 arranged in row L1 are accommodated.

[0027] For channel 1 at the time of clock interval 0, data from bit 4 to bit 11 among the 12-bit pixel data of pixel Y00 arranged in row L1 is accommodated, and for channel 1 at the time of clock interval 1, data from bit 4 to bit 11 among the 12-bit pixel data of pixel U00 is accommodated.

[0028] For channel 2 during the clock interval 0, among the 12-bit pixel data of pixel Y01 arranged in row L1, the data from bit 4 to bit 11 is accommodated. For channel 2 during the clock interval 1, among the 12-bit pixel data of pixel V00 arranged in row L1, the data from bit 4 to bit 11 is accommodated. The same mapping process is performed for the pixel data of pixels Y10, U10, Y11, and V10 arranged in row L2.

[0029] FIG. 4 is a diagram for explaining an example of a transmission format when development data 242 is output via an HDMI cable 30 from an imaging device 20 according to the prior art. FIG. 4(a) shows an arrangement example in a dot sequential manner in a data memory 24 of each 12-bit Y pixel data 1, U pixel data 2, and V pixel data 3 when the YUV data is configured in, for example, a YUV422 format 24-bit mode as the development data 242. In row L1, it shows a state where the pixel data of each 12-bit pixel Y00, Y01, Y02, Y03, Y04, and Y05 are sequentially arranged in the horizontal direction Ma. Further, in row L2 following row L1, it shows a state where the pixel data of each 12-bit pixel Y10, Y11, Y12, Y13, Y14, and Y15 are sequentially arranged in the horizontal direction Ma. Also, in row Lk after all the Y pixel data 1 is arranged, it shows a state where the pixel data of each 12-bit pixel U00, V00, U02, V02, U04, and V04 are sequentially arranged in the horizontal direction Ma. Further, in row Lk + 1 following row Lk, it shows a state where the pixel data of each 12-bit pixel U10, V10, U12, V12, U14, and V14 are sequentially arranged in the horizontal direction Ma.

[0030] Figs. 4(b) and (c) are diagrams showing an example of a transmission format. Figs. 4(b) and (c) show the transmission format used by the external output control unit 262 of the imaging device 20 to transmit the pixel data arranged in the rows L1, L2, Lk, and Lk+1 shown in Fig. 4(a) via an HDMI cable. Horizontally, the clock intervals from 0 to 5 are exemplified, and time elapses as it progresses from interval 0 to 5. In each clock interval, three channels from channel 0 to 2 are provided, and each field assigned to each channel can accommodate 8 bits of data each. That is, in Figs. 4(b) and (c), a total of 24 bits of data can be accommodated in each clock interval. However, since the YUV data is in the YUV422 format 24-bit mode, in each 8-bit of one clock interval, a total of three fields accommodate 1 pixel of Y pixel data 1, as well as 1 pixel each of U pixel data 2 and V pixel data 3 alternately, for a total of 24 bits of data.

[0031] Therefore, in the example shown in FIG. 4(b), for channel 0 at clock interval 0, among the 12-bit pixel data of pixel Y00 arranged in row L1, data from bit 0 to bit 3 is accommodated, and for channel 1 at the same clock interval 0, among the 12-bit pixel data of pixel Y00, data from bit 4 to bit 11 is accommodated. For channel 0 at clock interval 0, among the 12-bit pixel data of pixel U00 arranged in row Lk, data from bit 0 to bit 3 is accommodated, and for channel 2 at the same clock interval 0, among the 12-bit pixel data of pixel U00, data from bit 4 to bit 11 is accommodated. For channel 0 at clock interval 1, among the 12-bit pixel data of pixel Y01 arranged in row L1, data from bit 0 to bit 3 is accommodated, and for channel 1 at the same clock interval 1, among the 12-bit pixel data of pixel Y01, data from bit 4 to bit 11 is accommodated. For channel 0 at clock interval 1, among the 12-bit pixel data of pixel V00 arranged in row Lk, data from bit 0 to bit 3 is accommodated, and for channel 2 at the same clock interval 1, among the 12-bit pixel data of pixel V00, data from bit 4 to bit 11 is accommodated. Similar mapping processing is also performed on the pixel data of pixels Y02, Y03, Y04, and Y05 arranged in row L1, and the pixel data of pixels U02, V02, U04, and V04 arranged in row Lk.

[0032] In the example shown in FIG. 4(c), for channel 0 at clock interval 0, among the 12-bit pixel data of pixel Y10 arranged in row L2, data from bit 0 to bit 3 is accommodated, and for channel 1 at the same clock interval 0, among the 12-bit pixel data of pixel Y10, data from bit 4 to bit 11 is accommodated. For channel 0 at clock interval 0, among the 12-bit pixel data of pixel U10 arranged in row Lk+1, data from bit 0 to bit 3 is accommodated, and for channel 2 at the same clock interval 0, among the 12-bit pixel data of pixel U10, data from bit 4 to bit 11 is accommodated. For channel 0 at clock interval 1, among the 12-bit pixel data of pixel Y11 arranged in row L2, data from bit 0 to bit 3 is accommodated, and for channel 1 at the same clock interval 1, among the 12-bit pixel data of pixel Y11, data from bit 4 to bit 11 is accommodated. For channel 0 at clock interval 1, among the 12-bit pixel data of pixel V10 arranged in row Lk+1, data from bit 0 to bit 3 is accommodated, and for channel 2 at the same clock interval 1, among the 12-bit pixel data of pixel V10, data from bit 4 to bit 11 is accommodated. The same mapping process is performed for the pixel data of pixels Y12, Y13, Y14, and Y15 arranged in row L2, and for the pixel data of pixels U12, V12, U14, and V14 arranged in row Lk+1.

[0033] Next, each embodiment and modification of the present invention will be described with reference to the drawings from FIG. 5 onwards. FIG. 5 is an example of a block diagram of an image transmission and recording system 11 in each embodiment and modification of the present invention. The image transmission and recording system 11 includes an imaging device 20, an image recording device 40 that is an external device of the imaging device 20, and an HDMI cable 30 that connects the imaging device 20 and the image recording device 40.

[0034] The imaging device 20 includes an imaging device control unit 21, an image sensor 22, a sensor data input circuit 23, a data memory 24, a development processing unit 25, an output control unit 26, and a display unit 27. The imaging device control unit 21 is composed of, for example, a microprocessor and a memory, and controls the entire imaging device 20, that is, the imaging device control unit 21, the image sensor 22, the sensor data input circuit 23, the data memory 24, the development processing unit 25, the output control unit 26, and the display unit 27 by running a computer program.

[0035] The image sensor 22 has a plurality of photoelectric conversion elements, and captures a subject image through an optical system (not shown) and outputs a captured image signal. The sensor data input circuit 23 performs detection processing on the captured image signal output from the image sensor 22, and performs synchronization processing of the captured image signal and the audio signal, and calculation processing of white balance data and gamma data, for example, in units of frames. The RAW data 241 of the captured image signal, the audio signal data, the white balance data, and the gamma data are stored in the register area of the sensor data input circuit unit 23 or the data memory 24 in units of frames.

[0036] The development processing unit 25 generates development data 242 such as YUV data and / or RGB data based on the RAW data 241 stored in the data memory 24. RGB data is generated by representing the color information of a pixel as a combination of the red component R, the green component G, and the blue component B, which are the three primary colors of light. YUV data is generated by representing the color information of a pixel as a combination of the luminance component Y, the color difference component U between the luminance component and the blue component, and the color difference component V between the luminance component and the red component. In addition, a display output adjustment process A1 based on the white balance data and the gamma data is performed. In the following, the YUV data will be described as the development data, but the RGB data can be handled in the same manner. The development data 242 generated by the development processing unit 25 is stored in the data memory 24.

[0037] The output control unit 26 includes a display output control unit 261 and an external output control unit 262, and reads out the development data 242 stored in the data memory 24. The display output control unit 261 performs, under the control of the imaging device control unit 21, on the development data 242, in frame units, a display output adjustment process A1 based on synchronization processing with an audio signal, white balance data, and gamma data, thereby displaying an image in frame units on the display unit 27. At this time, the display output control unit 261 outputs audio to a speaker or earphone (not shown) based on the audio signal associated with the frame. Note that the output control unit 26 may perform the display output adjustment process A1 based on the white balance data and the gamma data.

[0038] The external output control unit 262 performs, under the control of the imaging device control unit 21, on the development data 242, in frame units, a reading process A2 of reading out the development data 242 while associating an audio signal therewith. The external output control unit 262 can transmit the development data 242 and the audio signal to the image recording device 40 via the HDMI cable 30 by arranging them in a predetermined field in the HDMI transmission format.

[0039] Furthermore, the external output control unit 262 performs, under the control of the imaging device control unit 21, on the RAW data 241, in frame units, a reading process A3 of reading out the RAW data 241 while associating an audio signal, white balance data, and gamma data therewith. The external output control unit 262 arranges the RAW data 241, the white balance data, and the gamma data in a specific field in the HDMI transmission format, and arranges the audio signal in a predetermined field in the HDMI transmission format. By doing so, the external output control unit 262 can transmit the RAW data 241, the audio signal, the white balance data, and the gamma data to the image recording device 40 via the HDMI cable 30.

[0040] The image recording apparatus 40 includes an image recording apparatus control unit 41, an external input control unit 42, an image processing unit 43, a storage device 44, a display output control unit 45, and a display unit 46. The image recording apparatus control unit 41 is composed of, for example, a microprocessor and a memory, and controls the entire image recording apparatus 40, that is, the image recording apparatus control unit 41, the external input control unit 42, the image processing unit 43, the storage device 44, the display output control unit 45, and the display unit 46 by running a computer program.

[0041] The external input control unit 42 receives the development data 242 and the audio signal from the imaging apparatus 20 via the HDMI cable 30, that is, acquires the development data 242 and the audio signal arranged in a predetermined field on the HDMI transmission format and transfers them to the image processing unit 43. The image processing unit 43 stores the development data 242 and the audio signal in the storage device 44 in units of frames and delivers them to the display output control unit 45.

[0042] The display output control unit 45, under the control of the image recording apparatus control unit 41, performs synchronization processing with the audio signal and display output adjustment processing based on white balance data and gamma data on a frame-by-frame basis for the development data 242 received from the image processing unit 43, thereby displaying an image on the display unit 46 in units of frames. At this time, the display output control unit 261 outputs audio to a speaker or earphone (not shown) based on the audio signal associated with the frame.

[0043] In addition, the external input control unit 42 receives RAW data 241, white balance data, gamma data, and an audio signal from the imaging device 20 via the HDMI cable 30, that is, acquires the RAW data 241, white balance data, gamma data, and audio signal arranged in a specific / predetermined field on the HDMI transmission format and transfers them to the image processing unit 43. The image processing unit 43 generates developed data such as YUV data and / or RGB data based on the RAW data 241. The image processing unit 43 stores the RAW data 241, the white balance data, gamma data, and audio signal acquired from the imaging device 20 via the external input control unit 42 in the storage device 44 in frame units. Further, the generated developed data is delivered to the display output control unit 45. Note that the image processing unit 43 may perform compression processing (encoding processing) on the RAW data 241 and then deliver it to the storage device.

[0044] The display output control unit 45, under the control of the image recording device control unit 41, performs, for the developed data generated by the image processing unit 43, synchronization processing with the audio signal and display output adjustment processing based on the white balance data and gamma data in frame units based on the white balance data, gamma data, and audio signal obtained from the imaging device 20, thereby displaying an image on the display unit 46 in frame units. At this time, the display output control unit 261 outputs audio to a speaker or earphone (not shown) based on the audio signal associated with the frame.

[0045] FIG. 6 is a diagram illustrating RAW data 241 stored in data memory 24 in imaging device 20 in each embodiment and modification of the present invention. FIG. 6(a) shows an arrangement example of R pixel data 4, G pixel data 5, and B pixel data 6 that constitute RAW data 241 when RAW data 241 is stored instead of the YUV data configured in the YUV444 format illustrated in FIG. 2(a), in a dot sequential manner within data memory 24. In the odd rows of data memory 24, R pixel data 4 and G pixel data 5 are repeatedly arranged in order in the horizontal direction Ma, and in the even rows, G pixel data 5 and B pixel data 6 are repeatedly arranged in order in the horizontal direction Ma. The RAW pixel data columns of the odd rows and even rows thus formed are juxtaposed in the vertical direction Mb of data memory 24. In FIG. 6(a) in particular, the top row L1 (an example of an odd row) and the next row L2 (an example of an even row) are illustrated.

[0046] FIG. 6(b) shows an arrangement example of R pixel data 4, G pixel data 5, and B pixel data 6 that constitute RAW data 241 when RAW data 241 is stored instead of the YUV data configured in the YUV422 format illustrated in FIG. 2(b), in a dot sequential manner within data memory 24. In the odd rows of data memory 24, R pixel data 4 and G pixel data 5 are repeatedly arranged in order in the horizontal direction Ma, and in the even rows, G pixel data 5 and B pixel data 6 are repeatedly arranged in order in the horizontal direction Ma, and the RAW pixel data columns of the odd rows and even rows thus formed are juxtaposed in the vertical direction Mb of data memory 24. The RAW pixel data columns of the odd rows and even rows thus formed are juxtaposed in the vertical direction Mb of data memory 24. In FIG. 6(b) in particular, the top row L1 (an example of an odd row) and the next row L2 (an example of an even row) are illustrated.

[0047] FIG. 6(c) shows an arrangement example in a plane sequential format in a data memory 24 of R pixel data 4, G pixel data 5, and B pixel data 6 that constitute RAW data 241 and D pixel data 7 which is dummy data different from the RAW data 241, when the RAW data 241 is stored instead of YUV data configured in the YUV444 format or the YUV422 format exemplified in FIG. 2(c). In each row from the first row L1 to the row Li-1 at the head of the data memory 24, the RAW data 241 is arranged at a position where only the Y pixel data 1 is repeatedly arranged in the horizontal direction Ma in the case of YUV data. In the odd-numbered rows among these, the R pixel data 4 and the G pixel data 5 are repeatedly arranged in order in the horizontal direction Ma, and in the even-numbered rows, the G pixel data 5 and the B pixel data 6 are repeatedly arranged in order in the horizontal direction Ma. The RAW pixel data columns of the odd-numbered rows and the even-numbered rows thus formed are juxtaposed in the vertical direction Mb of the data memory 24. In each row from the row Li to the row Lj-1, the D pixel data 7 which is dummy data is repeatedly arranged at a position where only the U pixel data 2 is repeatedly arranged in the horizontal direction Ma in the case of YUV data. In each row after the row Lj, the D pixel data 7 which is dummy data is repeatedly arranged at a position where only the V pixel data 3 is repeatedly arranged in the horizontal direction Ma in the case of YUV data. Each of these rows is juxtaposed in the vertical direction Mb of the data memory 24. In FIG. 6(c) in particular, the first row L1 (an example of an odd-numbered row) where the RAW data 241 is arranged and the next row L2 (an example of an even-numbered row), the first row Li where only the D pixel data 7 is repeatedly arranged and the row Lj where only the D pixel data 7 is repeatedly arranged are exemplified. Note that the D pixel data 7 which is dummy data does not necessarily have to be stored in the data memory 24 in particular.

[0048] FIG. 6(d) shows an example of the arrangement in the plane sequential method in the data memory 24 of the R pixel data 4, G pixel data 5, and B pixel data 6 that constitute the RAW data 241 and the D pixel data 7 which is dummy data different from the RAW data 241, when the RAW data 241 is stored instead of the YUV data configured in the YUV422 format illustrated in FIG. 2(d). In each row from the first row L1 to the row Lk-1 at the head of the data memory 24, the RAW data 241 is arranged at a position where only the Y pixel data 1 is repeatedly arranged in the horizontal direction Ma in the case of YUV data. In the odd-numbered rows among these, the R pixel data 4 and the G pixel data 5 are repeatedly arranged in order in the horizontal direction Ma, and in the even-numbered rows, the G pixel data 5 and the B pixel data 6 are repeatedly arranged in order in the horizontal direction Ma. The RAW pixel data columns of the odd-numbered rows and even-numbered rows thus formed are juxtaposed in the vertical direction Mb of the data memory 24. In each row after the row Lk, the D pixel data 7 which is dummy data is repeatedly arranged at a position where the U pixel data 2 and the V pixel data 3 are repeatedly arranged in order in the horizontal direction Ma in the case of YUV data. Each of these rows is juxtaposed in the vertical direction Mb of the data memory 24. In FIG. 6(d) in particular, the first row L1 (an example of an odd-numbered row) where the RAW data 241 is arranged and the next row L2 (an example of an even-numbered row), and the first row Lk where only the D pixel data 7 is repeatedly arranged are illustrated. Note that the D pixel data 7 which is dummy data does not necessarily have to be stored in the data memory 24 in particular.

[0049] -First Embodiment- The transmission format of RAW data 241 in the first embodiment of the present invention will be described with reference to FIG. 7. FIG. 7 is a diagram for explaining an example of the output of RAW data using the transmission format for YUV data in the first embodiment of the present invention. FIG. 7(a) shows an arrangement example of each 16-bit R pixel data 4, G pixel data 5, and B pixel data 6 of RAW data 241 in the data memory 24 in a dot sequential manner when RAW data 241 is stored instead of the YUV data configured in the YUV444 format 48-bit mode illustrated in FIG. 3(a). In row L1, it shows how the pixel data of each 16-bit pixel R00, G00, R01, G01, R02, G02, R03, G03, and R04 are sequentially arranged in the horizontal direction Ma. Further, in row L2 following row L1, it shows how the pixel data of each 16-bit pixel G10, B10, G11, B11, G12, B12, G13, B13, and G14 are sequentially arranged in the horizontal direction Ma.

[0050] FIGS. 7(b) and (c) are diagrams showing how the external output control unit 262 of the imaging device 20 maps each pixel data of the RAW data 241 arranged in rows L1 and L2 shown in FIG. 7(a) to the transmission format for YUV data in order to transmit it via the HDMI cable 30. The intervals of the clock from 0 to 5 are illustrated in the horizontal direction, and time elapses as it progresses from interval 0 to 5. In each interval of the clock, three channels from channel 0 to 2 are provided, and each channel can accommodate 8 bits of data in each assigned field. That is, in FIGS. 7(b) and (c), a total of 24 bits of data can be accommodated in each interval of the clock. However, following the example of the YUV444 format 48-bit mode shown in FIGS. 3(b) and (c), by using two intervals of the clock, a total of 48 bits of data for a total of three pixels, which is two pixels of one of the R pixel data 4 and G pixel data 5 and one pixel of the other, or two pixels of one of the G pixel data 5 and B pixel data 6 and one pixel of the other, can be accommodated in a total of six fields, each of 8 bits.

[0051] Therefore, in the example shown in FIG. 7(b), for channel 0 at clock interval 0, among the 16-bit pixel data of pixel R00 arranged in row L1, the data from bit 0 to bit 7 is accommodated, and for channel 0 at clock interval 1, among the 16-bit pixel data of pixel R00, the data from bit 8 to bit 15 is accommodated. For channel 1 at clock interval 0, among the 16-bit pixel data of pixel G00 arranged in row L1, the data from bit 0 to bit 7 is accommodated, and for channel 1 at clock interval 1, among the 16-bit pixel data of pixel G00, the data from bit 8 to bit 15 is accommodated. For channel 2 at clock interval 0, among the 16-bit pixel data of pixel R01 arranged in row L1, the data from bit 0 to bit 7 is accommodated, and for channel 2 at clock interval 1, among the 16-bit pixel data of pixel R01, the data from bit 8 to bit 15 is accommodated. Comparing FIG. 7(b) and FIG. 3(b), the positions of the accommodation boundaries of the pixel data of pixel R00, pixel G00, and pixel R01 in RAW data 241 are included in the positions of the accommodation boundaries of the pixel data of pixel Y00, pixel U00, and pixel V00 in the developed data 242 in the YUV444 format 48-bit mode. For the pixel data of pixels G01, R02, G02, R03, G03, and R04 arranged in row L1, the same mapping process as the pixel data of pixel R00, pixel G00, and pixel R01 is performed.

[0052] In the example shown in FIG. 7(c), for channel 0 at the clock interval 0, among the 16-bit pixel data of pixel G10 arranged in row L2, data from bit 0 to bit 7 is accommodated, and for channel 0 at the clock interval 1, among the 16-bit pixel data of pixel G10, data from bit 8 to bit 15 is accommodated. For channel 1 at the clock interval 0, among the 16-bit pixel data of pixel B10 arranged in row L2, data from bit 0 to bit 7 is accommodated, and for channel 1 at the clock interval 1, among the 16-bit pixel data of pixel B10, data from bit 8 to bit 15 is accommodated. For channel 2 at the clock interval 0, among the 16-bit pixel data of pixel G11 arranged in row L2, data from bit 0 to bit 7 is accommodated, and for channel 2 at the clock interval 1, among the 16-bit pixel data of pixel G11, data from bit 8 to bit 15 is accommodated. Comparing FIG. 7(c) and FIG. 3(c), the positions of the accommodation boundaries of the pixel data of pixel G10, pixel B10, and pixel G11 in the RAW data 241 are included in the positions of the accommodation boundaries of the pixel data of pixel Y10, pixel U10, and pixel V10 in the developed data 242 in the YUV444 format 48-bit mode. For the pixel data of pixels B11, G12, B12, G13, B13, and G14 arranged in row L2, the same mapping process as the pixel data of pixel G10, pixel B10, and pixel G11 is performed.

[0053] According to the first embodiment described above, the following operational effects can be obtained.

[0054] (1) The imaging device 20 of the image transmission recording system 10 includes an image sensor 22 that captures an image of a subject and outputs an imaging signal, a developing processing unit 25 that generates developed image data 242 based on the RAW data 241 of the imaging signal, and an output control unit 26 that outputs the developed image data 242 to the image recording device 40 via an HDMI cable 30 in a predetermined transmission format. The output control unit 26 outputs the RAW data 241 to the image recording device 40 via the HDMI cable 30 by accommodating it in a transmission channel according to a predetermined transmission format. Thereby, the imaging device 20 can efficiently output the RAW data 241 externally using the existing HDMI cable 30.

[0055] (2) In the imaging device 20, the position of the accommodation boundary of pixel data when the RAW data 241 is accommodated in the transmission channel according to a predetermined transmission format is included in the position of the accommodation boundary of pixel data when the developed image data 242 is accommodated in the transmission channel according to a predetermined transmission format. Thereby, if the imaging device 20 corresponds to the transmission format for the developed image data 242, it is not necessary to correspond to the transmission specification specific to the RAW data 241. Also, in the image recording device 40, it becomes possible to divert the process of specifying the developed image data 242 on the transmission format to the process of specifying the RAW data 241 on the transmission format.

[0056] -Second Embodiment- The transmission format of the RAW data 241 in the second embodiment of the present invention will be described with reference to FIG. 8. FIG. 8 is a diagram for explaining an example of the output of RAW data using the transmission format for YUV data in the second embodiment of the present invention. FIG. 8(a) shows the case where RAW data 241 is stored instead of YUV422 data composed of 12 bits for each component for transmission in the YUV422 format 24-bit mode illustrated in FIG. 4(a). An arrangement example in the dot sequential method in the data memory 24 of each 12-bit R pixel data 4, G pixel data 5, B pixel data 6, and D pixel data 7 which is dummy data is shown. In row L1, the state where pixel data of each 12-bit pixel R00, G00, R01, G01, R02, and G02 are sequentially arranged in the horizontal direction Ma is shown. Further, in row L2 following row L1, the state where pixel data of each 12-bit pixel G10, B10, G11, B11, G12, and B12 are sequentially arranged in the horizontal direction Ma is shown. Also, in row Lk after all the RAW data 241 is arranged, the state where a plurality of D pixel data 7 which are each 12-bit dummy data are sequentially arranged in the horizontal direction Ma is shown. Further, in row Lk + 1 following row Lk, the state where a plurality of D pixel data 7 which are each 12-bit dummy data are sequentially arranged in the horizontal direction Ma is shown.

[0057] Figures 8(b) and 8(c) are diagrams showing how the external output control unit 262 of the imaging device 20 maps the pixel data arranged in the lines L1, L2, Lk, and Lk+1 shown in Figure 8(a) in the transmission format for YUV data via the HDMI cable 30. Horizontally, the clock intervals from 0 to 5 are illustrated, and time elapses as it progresses from interval 0 to 5. In each clock interval, three channels from channel 0 to 2 are provided, and each channel can accommodate 8 bits of data in each field assigned to it. That is, in Figures 8(b) and 8(c), a total of 24 bits of data can be accommodated in each clock interval. However, following the example of the YUV422 format 24-bit mode shown in Figures 4(b) and 4(c), by using one interval of the clock, a total of 24 bits of data, which is one pixel of the R pixel data 4, the G pixel data, or the B pixel data 6, and one pixel of the D pixel data 7, which is dummy data, can be accommodated in a total of three fields of 8 bits each.

[0058] Therefore, in the example shown in Figure 8(b), in channel 0 at the clock interval 0, 0 to 3 bits of the 12-bit pixel data of the pixel R00 arranged in line L1 are accommodated, and in channel 1 at the same clock interval 0, 4 to 11 bits of the 12-bit pixel data of the pixel R00 are accommodated. In channel 0 at the clock interval 0, 0 to 3 bits of the 12-bit pixel data of the D pixel data 7, which is dummy data, arranged in line Lk are accommodated, and in channel 2 at the same clock interval 0, 4 to 11 bits of the 12-bit pixel data of the D pixel data 7, which is dummy data, are accommodated. Comparing Figure 8(b) with Figure 4(b), the positions of the accommodation boundaries of the pixel data of the pixel R00 of the RAW data 241 and the D pixel data 7, which is dummy data, are included in the positions of the accommodation boundaries of the pixel data of the pixel Y00 and the pixel U00 of the developed data 242 in the YUV422 format 24-bit mode.

[0059] For channel 0 during clock interval 1, among the 12-bit pixel data of pixel gG00 arranged in row L1, data from bit 0 to bit 3 is accommodated. For channel 1 during the same clock interval 1, among the 12-bit pixel data of pixel G00, data from bit 4 to bit 11 is accommodated. For channel 0 during clock interval 1, among the 12-bit pixel data of D pixel data 7 which is dummy data arranged in row Lk, data from bit 0 to bit 3 is accommodated. For channel 2 during the same clock interval 1, among the 12-bit pixel data of D pixel data 7 which is dummy data, data from bit 4 to bit 11 is accommodated. Comparing Figure 8(b) and Figure 4(b), the positions of the accommodation boundaries of the pixel data of pixel G00 in RAW data 241 and D pixel data 7 which is dummy data are included in the positions of the accommodation boundaries of the pixel data of pixel Y01 and pixel V00 in the developed data 242 in the YUV422 format 24-bit mode. The same mapping process is also performed for the pixel data of pixels R01, G01, R02, and G02 arranged in row L1, and for a plurality of D pixel data 7 which is dummy data arranged in row Lk.

[0060] In the example shown in Figure 8(c), for channel 0 during clock interval 0, among the 12-bit pixel data of pixel G10 arranged in row L2, data from bit 0 to bit 3 is accommodated. For channel 1 during the same clock interval 0, among the 12-bit pixel data of pixel G10, data from bit 4 to bit 11 is accommodated. For channel 0 during clock interval 0, among the 12-bit pixel data of D pixel data 7 which is dummy data arranged in row Lk + 1, data from bit 0 to bit 3 is accommodated. For channel 2 during the same clock interval 0, among the 12-bit pixel data of D pixel data 7 which is dummy data, data from bit 4 to bit 11 is accommodated. Comparing Figure 8(c) and Figure 4(c), the positions of the accommodation boundaries of the pixel data of pixel G10 in RAW data 241 and D pixel data 7 which is dummy data are included in the positions of the accommodation boundaries of the pixel data of pixel Y10 and pixel U10 in the developed data 242 in the YUV422 format 24-bit mode.

[0061] For channel 0 during clock interval 1, among the 12-bit pixel data of pixel B10 arranged in row L2, data from bit 0 to bit 3 is accommodated. For channel 1 during the same clock interval 1, among the 12-bit pixel data of pixel B10, data from bit 4 to bit 11 is accommodated. For channel 0 during clock interval 1, among the 12-bit pixel data of D pixel data 7 which is dummy data arranged in row Lk + 1, data from bit 0 to bit 3 is accommodated. For channel 2 during the same clock interval 1, among the 12-bit pixel data of D pixel data 7 which is dummy data, data from bit 4 to bit 11 is accommodated. Comparing FIG. 8(c) and FIG. 4(c), the positions of the accommodation boundaries of the pixel data of pixel B10 of RAW data 241 and D pixel data 7 which is dummy data are included in the positions of the accommodation boundaries of the respective pixel data of pixel Y11 and pixel V10 of developed data 242 in the YUV422 format 24-bit mode. The same mapping process is also performed for the pixel data of pixels G11, B11, G12, and B12 arranged in row L2, and for a plurality of D pixel data 7 which is dummy data arranged in row Lk + 1.

[0062] According to the second embodiment described above, the following operational effects can be obtained. In imaging device 20, when RAW data 241 is accommodated in a transmission channel according to a predetermined transmission format, the position of the accommodation boundary of the pixel data is included in the position of the accommodation boundary of the pixel data when developed data 242 is accommodated in the transmission channel according to the predetermined transmission format. Thereby, if imaging device 20 corresponds to the transmission format for developed data 242, it is not necessary to correspond to the transmission specification specific to RAW data 241. Also, in image recording device 40, it becomes possible to divert the process of specifying developed data 242 on the transmission format to the process of specifying RAW data 241 on the transmission format.

[0063] -Modification Example- The following modifications are also within the scope of the present invention.

[0064] (1) FIG. 9 is a diagram for explaining an example of a transmission format when RAW data 241 is output from the imaging device 20 in the modification example (1) via the HDMI cable 30. FIG. 9(a) shows an arrangement example in a dot sequential manner in the data memory 24 of each 12-bit R pixel data 4, G pixel data 5, and B pixel data 6 of the RAW data 241 when the RAW data 241 is stored instead of YUV444 data composed of 16 bits for each component for transmission in the YUV444 format 48-bit mode. In row L1, it shows how pixel data of each 12-bit pixel R00, G00, R01, G01, R02, G02, R03, G03, R04, G04, R05, and G05 are sequentially arranged in the horizontal direction Ma. Further, in row L2 following row L1, it shows how pixel data of each 16-bit pixel G10, B10, G11, B11, G12, B12, G13, B13, G14, B14, G15, and B15 are sequentially arranged in the horizontal direction Ma.

[0065] In FIGS. 9(b) and 9(c), although a total of 24 bits of data can be accommodated in each clock interval, following the example of the YUV444 format 48-bit mode, by using two intervals of clocks, 48 bits of data for a total of 4 pixels, each 12 bits that make up the RAW data 241, are accommodated in a total of 6 fields, 8 bits for each transmission channel.

[0066] In the example shown in FIG. 9(b), for channel 0 at the time of clock interval 0, among the 12-bit pixel data of pixel R00 arranged in row L1, data from bit 0 to bit 7 is accommodated, and for channel 0 at the time of clock interval 1, among the 12-bit pixel data of pixel R00, data from bit 8 to bit 11 is accommodated. For channel 0 at the time of clock interval 1, among the 12-bit pixel data of pixel G00 arranged in row L1, data from bit 0 to bit 3 is accommodated, and for channel 1 at the time of clock interval 0, among the 12-bit pixel data of pixel G00, data from bit 4 to bit 11 is accommodated. For channel 2 at the time of clock interval 1, among the 12-bit pixel data of pixel R01 arranged in row L1, data from bit 0 to bit 7 is accommodated, and for channel 2 at the time of clock interval 0, among the 12-bit pixel data of pixel R01, data from bit 8 to bit 11 is accommodated. For channel 2 at the time of clock interval 0, among the 12-bit pixel data of pixel G01 arranged in row L1, data from bit 0 to bit 3 is accommodated, and for channel 2 at the time of clock interval 1, among the 12-bit pixel data of pixel G01, data from bit 8 to bit 11 is accommodated. For the pixel data of pixels R02, G02, R03, G03, R04, G04, R05, and G05 arranged in row L1, the same mapping process as the pixel data of pixel R00, pixel G00, pixel R01, and pixel G01 is performed.

[0067] In the example shown in FIG. 9(c), for channel 0 at the time of clock interval 0, among the 12-bit pixel data of pixel G10 arranged in row L2, data from bit 0 to bit 7 is accommodated, and for channel 0 at the time of clock interval 1, among the 12-bit pixel data of pixel G10, data from bit 8 to bit 11 is accommodated. For channel 0 at the time of clock interval 1, among the 12-bit pixel data of pixel B10 arranged in row L2, data from bit 0 to bit 3 is accommodated, and for channel 1 at the time of clock interval 0, among the 12-bit pixel data of pixel B10, data from bit 4 to bit 11 is accommodated. For channel 2 at the time of clock interval 1, among the 12-bit pixel data of pixel G11 arranged in row L2, data from bit 0 to bit 7 is accommodated, and for channel 2 at the time of clock interval 0, among the 12-bit pixel data of pixel G11, data from bit 8 to bit 11 is accommodated. For channel 2 at the time of clock interval 0, among the 12-bit pixel data of pixel B11 arranged in row L2, data from bit 0 to bit 3 is accommodated, and for channel 2 at the time of clock interval 1, among the 12-bit pixel data of pixel B11, data from bit 8 to bit 11 is accommodated. For the pixel data of pixels G12, B12, G13, B13, G14, B14, G15, and B15 arranged in row L2, the same mapping process as the pixel data of pixel G10, pixel B10, pixel G11, and pixel B11 is performed. According to the modification example (1), the imaging device 20 can efficiently output the RAW data 241 using the existing HDMI cable 30 to the outside.

[0068] (2) FIG. 10 is a diagram for explaining an example of a transmission format when RAW data 241 is output from the imaging device 20 in the modification example (2) via the HDMI cable 30. FIG. 10(a) shows an arrangement example in a dot sequential system in the data memory 24 of each 12-bit R pixel data 4, G pixel data 5, and B pixel data 6 of the RAW data 241 when the RAW data 241 is stored instead of the YUV444 data composed of 12 bits for each component for transmission in the YUV444 format 36-bit mode. In row L1, it shows how the pixel data of each 12-bit pixel R00, G00, R01, G01, R02, G02, R03, G03, R04, G04, R05, and G05 are sequentially arranged in the horizontal direction Ma. Further, in row L2 following row L1, it shows how the pixel data of each 12-bit pixel G10, B10, G11, B11, G12, B12, G13, B13, G14, B14, G15, and B15 are sequentially arranged in the horizontal direction Ma.

[0069] In FIGS. 10(b) and (c), a total of 24 bits of data can be accommodated in each clock interval. Following the example of the YUV444 format 36-bit mode, the 36-bit data of a total of 3 pixels of each 12 bits constituting the RAW data 241 is accommodated in a field of 8 bits for each transmission channel in one of the two clock intervals and a field of 4 bits for each transmission channel in the other interval.

[0070] In the example shown in FIG. 10(b), for channel 0 at clock interval 0, among the 12-bit pixel data of pixel R00 arranged in row L1, data from bit 0 to bit 7 is accommodated, and for channel 0 at clock interval 1, among the 12-bit pixel data of pixel R00, data from bit 8 to bit 11 is accommodated. For channel 1 at clock interval 0, among the 12-bit pixel data of pixel G00 arranged in row L1, data from bit 0 to bit 7 is accommodated, and for channel 1 at clock interval 1, among the 12-bit pixel data of pixel G00, data from bit 8 to bit 11 is accommodated. For channel 2 at clock interval 0, among the 12-bit pixel data of pixel R01 arranged in row L1, data from bit 0 to bit 7 is accommodated, and for channel 2 at clock interval 1, among the 12-bit pixel data of pixel R01, data from bit 8 to bit 11 is accommodated.

[0071] For channel 0 at clock interval 1, among the 12-bit pixel data of pixel G01 arranged in row L1, data from bit 0 to bit 3 is accommodated, and for channel 0 at clock interval 2, among the 12-bit pixel data of pixel G01, data from bit 4 to bit 11 is accommodated. For channel 1 at clock interval 1, among the 12-bit pixel data of pixel R02 arranged in row L1, data from bit 8 to bit 11 is accommodated, and for channel 1 at clock interval 2, among the 12-bit pixel data of pixel R02, data from bit 0 to bit 7 is accommodated. For channel 2 at clock interval 1, among the 12-bit pixel data of pixel G02 arranged in row L1, data from bit 0 to bit 3 is accommodated, and for channel 2 at clock interval 2, among the 12-bit pixel data of pixel G02, data from bit 4 to bit 11 is accommodated. The same mapping process as that of the pixel data of pixel R00, pixel G00, pixel R01, pixel G01, pixel R02, and pixel G02 is also performed on the pixel data of pixels R03, G03, R04, G04, R05, and G05 arranged in row L1.

[0072] In the example shown in FIG. 10(c), for channel 0 at clock interval 0, among the 12-bit pixel data of pixel G10 arranged in row L2, data from bit 0 to bit 7 is accommodated, and for channel 0 at clock interval 1, among the 12-bit pixel data of pixel G10, data from bit 8 to bit 11 is accommodated. For channel 1 at clock interval 0, among the 12-bit pixel data of pixel B10 arranged in row L2, data from bit 0 to bit 7 is accommodated, and for channel 1 at clock interval 1, among the 12-bit pixel data of pixel B10, data from bit 8 to bit 11 is accommodated. For channel 2 at clock interval 0, among the 12-bit pixel data of pixel G11 arranged in row L2, data from bit 0 to bit 7 is accommodated, and for channel 2 at clock interval 1, among the 12-bit pixel data of pixel G11, data from bit 8 to bit 11 is accommodated.

[0073] For channel 0 at clock interval 1, among the 12-bit pixel data of pixel B11 arranged in row L2, data from bit 0 to bit 3 is accommodated, and for channel 0 at clock interval 2, among the 12-bit pixel data of pixel B11, data from bit 4 to bit 11 is accommodated. For channel 1 at clock interval 1, among the 12-bit pixel data of pixel G12 arranged in row L2, data from bit 8 to bit 11 is accommodated, and for channel 1 at clock interval 2, among the 12-bit pixel data of pixel G12, data from bit 0 to bit 7 is accommodated. For channel 2 at clock interval 1, among the 12-bit pixel data of pixel B12 arranged in row L2, data from bit 0 to bit 3 is accommodated, and for channel 2 at clock interval 2, among the 12-bit pixel data of pixel B12, data from bit 4 to bit 11 is accommodated. For the pixel data of pixels G13, B13, G14, B14, G15, and B15 arranged in row L2, the same mapping process as the pixel data of pixels G10, pixel B10, pixel G11, pixel B11, pixel G12, and pixel B12 is performed.

[0074] According to the modification example (2), the imaging device 20 can efficiently output the RAW data 241 using an existing HDMI cable 30. Further, the position of the accommodation boundary of each pixel data of the RAW data 241 is included in the position of the accommodation boundary of each pixel data of the developed data 242 in the YUV444 format 36-bit mode. If the imaging device 20 and the image recording device 40 support the transmission format for the developed data 242, they can support the transmission process of the RAW data 241.

[0075] (3) FIG. 11 is a diagram for explaining an example of the transmission format when the RAW data 241 is output from the imaging device 20 in the modification example (3) via the HDMI cable 30. FIG. 11(a) shows an arrangement example in a dot sequential manner in the data memory 24 of each 16-bit R pixel data 4, G pixel data 5, and B pixel data 6 of the RAW data 241 when the RAW data 241 is stored instead of the YUV444 data composed of 8 bits for each component for transmission in the YUV444 format 24-bit mode. In row L1, it shows how the pixel data of each 16-bit pixel R00, G00, R01, G01, R02, G02, R03, G03, and R04 are sequentially arranged in the horizontal direction Ma. Further, in row L2 following row L1, it shows how the pixel data of each 16-bit pixel G10, B10, G11, B11, G12, B12, G13, B13, and G14 are sequentially arranged in the horizontal direction Ma.

[0076] In FIGS. 11(b) and (c), a total of 24 bits of data can be accommodated in each clock interval. However, following the example of the YUV444 format 24-bit mode, 24 bits of data corresponding to a total of 1.5 pixels of each 16-bit data constituting the RAW data 241 are accommodated in a total of three fields with 8 bits for each transmission channel in one clock interval.

[0077] In the example shown in FIG. 11(b), for channel 0 at clock interval 0, among the 16-bit pixel data of pixel R00 arranged in row L1, data from bit 0 to bit 7 is accommodated, and for channel 1 at clock interval 0, among the 16-bit pixel data of pixel R00, data from bit 8 to bit 15 is accommodated. For channel 2 at clock interval 0, among the 16-bit pixel data of pixel G00 arranged in row L1, data from bit 0 to bit 7 is accommodated, and for channel 0 at clock interval 1, among the 16-bit pixel data of pixel G00, data from bit 8 to bit 15 is accommodated. For channel 1 at clock interval 1, among the 16-bit pixel data of pixel R01 arranged in row L1, data from bit 0 to bit 7 is accommodated, and for channel 2 at clock interval 1, among the 16-bit pixel data of pixel R01, data from bit 8 to bit 15 is accommodated. For the pixel data of pixels G01, R02, G02, R03, G03, and R04 arranged in row L1, the same mapping process as the pixel data of pixel R00, pixel G00, pixel R01, and pixel G01 is performed.

[0078] In the example shown in FIG. 11(c), for channel 0 at clock interval 0, among the 16-bit pixel data of pixel G10 arranged in row L2, data from bit 0 to bit 7 is accommodated, and for channel 1 at clock interval 0, among the 16-bit pixel data of pixel G10, data from bit 8 to bit 15 is accommodated. For channel 2 at clock interval 0, among the 16-bit pixel data of pixel B10 arranged in row L2, data from bit 0 to bit 7 is accommodated, and for channel 0 at clock interval 1, among the 16-bit pixel data of pixel B10, data from bit 8 to bit 15 is accommodated. For channel 1 at clock interval 1, among the 16-bit pixel data of pixel G11 arranged in row L2, data from bit 0 to bit 7 is accommodated, and for channel 2 at clock interval 1, among the 16-bit pixel data of pixel G11, data from bit 8 to bit 15 is accommodated. For the pixel data of pixels B11, G12, B12, G13, B13, and G14 arranged in row L2, the same mapping process as the pixel data of pixel G10, pixel B10, and pixel G11 is performed. According to the modification example (3), the imaging device 20 can efficiently output the RAW data 241 to the outside using the existing HDMI cable 30.

[0079] (4) Fig. 12 is a diagram for explaining an example of a transmission format when RAW data 241 is output from the imaging device 20 in the modification example (4) via the HDMI cable 30. Fig. 12(a) shows an arrangement example in a dot sequential manner in the data memory 24 of each 12-bit R pixel data 4, G pixel data 5, and B pixel data 6 of the RAW data 241 when the RAW data 241 is stored instead of YUV444 data composed of 8 bits for each component for transmission in the YUV444 format 24-bit mode. In row L1, it shows how pixel data of each 12-bit pixel R00, G00, R01, G01, R02, G02, R03, G03, R04, G04, R05, and G05 are sequentially arranged in the horizontal direction Ma. Further, in row L2 following row L1, it shows how pixel data of each 12-bit pixel G10, B10, G11, B11, G12, B12, G13, B13, G14, B14, G15, and B15 are sequentially arranged in the horizontal direction Ma.

[0080] In Figs. 12(b) and (c), a total of 24 bits of data can be accommodated in each clock interval. Following the example of the YUV444 format 24-bit mode, 24 bits of data for a total of two pixels, each 12 bits, constituting the RAW data 241 are accommodated in each 8-bit field of each transmission channel in one clock interval.

[0081] In the example shown in FIG. 12(b), among the 12-bit pixel data of pixel R00 arranged in row L1, data from bit 0 to bit 7 is accommodated in channel 0 at the time of clock interval 0, and data from bit 8 to bit 11 of the 12-bit pixel data of pixel R00 is accommodated in channel 1 at the time of clock interval 0. In channel 1 at the time of clock interval 0, data from bit 0 to bit 3 of the 12-bit pixel data of pixel G00 arranged in row L1 is accommodated, and in channel 2 at the time of clock interval 0, data from bit 4 to bit 11 of the 12-bit pixel data of pixel G00 is accommodated. For the pixel data of pixels R01, G01, R02, G02, R03, G03, R04, G04, R05, and G05 arranged in row L1, the same mapping process as the pixel data of pixel R00 and pixel G00 is performed.

[0082] In the example shown in FIG. 12(c), among the 12-bit pixel data of pixel G10 arranged in row L2, data from bit 0 to bit 7 is accommodated in channel 0 at the time of clock interval 0, and data from bit 8 to bit 11 of the 12-bit pixel data of pixel G10 is accommodated in channel 1 at the time of clock interval 0. In channel 1 at the time of clock interval 0, data from bit 0 to bit 3 of the 12-bit pixel data of pixel B10 arranged in row L2 is accommodated, and in channel 2 at the time of clock interval 0, data from bit 4 to bit 11 of the 12-bit pixel data of pixel B10 is accommodated. For the pixel data of pixels G11, B11, G12, B12, G13, B13, G14, B14, G15, and B15 arranged in row L2, the same mapping process as the pixel data of pixel G10, pixel B10, pixel G11, and pixel B11 is performed.

[0083] According to Modification Example (4), the imaging device 20 can efficiently output the RAW data 241 using an existing HDMI cable 30. Also, the position of the accommodation boundary of each pixel data of the RAW data 241 is included in the position of the accommodation boundary of each pixel data of the developed data 242 in the YUV444 format 24-bit mode. If the imaging device 20 and the image recording device 40 support the transmission format for the developed data 242, they can support the transmission process of the RAW data 241.

[0084] (5) FIG. 13 is a diagram for explaining an example of the transmission format when the RAW data 241 is output via the HDMI cable 30 from the imaging device 20 in Modification Example (5). FIG. 13(a) shows an arrangement example in a dot sequential manner in the data memory 24 of each 12-bit R pixel data 4, G pixel data 5, and B pixel data 6 of the RAW data 241 when the RAW data 241 is stored instead of the YUV422 data composed of 12 bits for each component for transmission in the YUV422 format 24-bit mode. In row L1, it shows how the pixel data of each 12-bit pixel R00, G00, R01, G01, R02, G02, R03, G03, R04, G04, R05, and G05 are sequentially arranged in the horizontal direction Ma. Further, in row L2 following row L1, it shows how the pixel data of each 12-bit pixel G10, B10, G11, B11, G12, B12, G13, B13, G14, B14, G15, and B15 are sequentially arranged in the horizontal direction Ma.

[0085] In FIGS. 13(b) and (c), a total of 24 bits of data can be accommodated in each clock interval. Following the example of the YUV422 format 24-bit mode, 24 bits of data for a total of 2 pixels, each 12 bits that make up the RAW data 241, are accommodated in each 8-bit field of each transmission channel in one clock interval.

[0086] In the example shown in FIG. 13(b), for channel 0 at clock interval 0, among the 12-bit pixel data of pixel R00 arranged in row L1, data from bit 0 to bit 3 is accommodated, and for channel 1 at clock interval 0, among the 12-bit pixel data of pixel R00, data from bit 4 to bit 11 is accommodated. For channel 0 at clock interval 0, among the 12-bit pixel data of pixel R01 arranged in row L1, data from bit 0 to bit 3 is accommodated, and for channel 2 at clock interval 0, among the 12-bit pixel data of pixel R01, data from bit 4 to bit 11 is accommodated. For channel 0 at clock interval 1, among the 12-bit pixel data of pixel G00 arranged in row L1, data from bit 0 to bit 3 is accommodated, and for channel 1 at clock interval 1, among the 12-bit pixel data of pixel G00, data from bit 4 to bit 11 is accommodated. For channel 0 at clock interval 1, among the 12-bit pixel data of pixel G01 arranged in row L1, data from bit 0 to bit 3 is accommodated, and for channel 2 at clock interval 1, among the 12-bit pixel data of pixel G01, data from bit 4 to bit 11 is accommodated. Pixel data of pixels R02, G02, R03, G03, R04, G04, R05, and G05 arranged in row L1 also undergoes the same mapping process as the pixel data of pixel R00, pixel G00, pixel R01, and pixel G01.

[0087] In the example shown in FIG. 13(c), for channel 0 at the clock interval 0, among the 12-bit pixel data of pixel G10 arranged in row L2, data from bit 0 to bit 3 is accommodated, and for channel 1 at the clock interval 0, among the 12-bit pixel data of pixel G10, data from bit 4 to bit 11 is accommodated. For channel 0 at the clock interval 0, among the 12-bit pixel data of pixel G11 arranged in row L2, data from bit 0 to bit 3 is accommodated, and for channel 2 at the clock interval 0, among the 12-bit pixel data of pixel G11, data from bit 4 to bit 11 is accommodated. For channel 0 at the clock interval 1, among the 12-bit pixel data of pixel B10 arranged in row L2, data from bit 0 to bit 3 is accommodated, and for channel 1 at the clock interval 1, among the 12-bit pixel data of pixel B10, data from bit 4 to bit 11 is accommodated. For channel 0 at the clock interval 1, among the 12-bit pixel data of pixel B11 arranged in row L2, data from bit 0 to bit 3 is accommodated, and for channel 2 at the clock interval 1, among the 12-bit pixel data of pixel B11, data from bit 4 to bit 11 is accommodated. For the pixel data of pixels G12, B12, G13, B13, G14, B14, G15, and B15 arranged in row L2, the same mapping process as the pixel data of pixel G10, pixel B10, pixel G11, and pixel B11 is performed.

[0088] According to the modification example (5), the imaging device 20 can efficiently output the RAW data 241 externally using the existing HDMI cable 30. Also, the position of the accommodation boundary of each pixel data of the RAW data 241 is included in the position of the accommodation boundary of each pixel data of the developed data 242 in the YUV422 format 24-bit mode. If the imaging device 20 and the image recording device 40 support the transmission format for the developed data 242, they can support the transmission process of the RAW data 241.

[0089] (6) Fig. 14 is a diagram for explaining an example of a transmission format when RAW data 241 is output from the imaging device 20 in the modification example (6) via the HDMI cable 30. Fig. 14(a) shows an arrangement example in a dot sequential manner in the data memory 24 of each 16-bit R pixel data 4, G pixel data 5, and B pixel data 6 of the RAW data 241 when the RAW data 241 is stored instead of the YUV422 data composed of 12 bits for each component for transmission in the YUV422 format 24-bit mode. In row L1, it shows how the pixel data of each 16-bit pixel R00, G00, R01, G01, R02, and G02 are sequentially arranged in the horizontal direction Ma. Further, in row L2 following row L1, it shows how the pixel data of each 16-bit pixel G10, B10, G11, B11, G12, and B12 are sequentially arranged in the horizontal direction Ma.

[0090] In Figs. 14(b) and (c), a total of 24 bits of data can be accommodated in each clock interval. However, following the example of the YUV422 format 24-bit mode, 24 bits of data for a total of 1.5 pixels of each 16 bits constituting the RAW data 241 are accommodated in a total of three fields, 8 bits for each transmission channel, in one clock interval.

[0091] In the example shown in FIG. 14(b), for channel 0 at clock interval 0, it accommodates data from bit 0 to bit 3 out of the 16-bit pixel data of pixel R00 arranged in row L1. For channel 1 at clock interval 0, it accommodates data from bit 4 to bit 11 out of the 16-bit pixel data of pixel R00. For channel 0 at clock interval 1, it accommodates data from bit 12 to bit 15 out of the 16-bit pixel data of pixel R00. For channel 1 at clock interval 1, for the 16-bit pixel data of pixel G00 arranged in row L1, it accommodates data from bit 0 to bit 7. For channel 0 at clock interval 0, it accommodates data from bit 8 to bit 11 out of the 16-bit pixel data of pixel G00. For channel 2 at clock interval 0, it accommodates data from bit 12 to bit 15 out of the 16-bit pixel data of pixel G00. For channel 2 at clock interval 0, for the 16-bit pixel data of pixel R01 arranged in row L1, it accommodates data from bit 0 to bit 3. For channel 0 at clock interval 1, it accommodates data from bit 4 to bit 7 out of the 16-bit pixel data of pixel R01. For channel 2 at clock interval 1, it accommodates data from bit 8 to bit 15 out of the 16-bit pixel data of pixel R01. For the pixel data of pixels G01, R02, and G02 arranged in row L1, the same mapping process as that for the pixel data of pixel R00, pixel G00, and pixel R01 is performed.

[0092] In the example shown in FIG. 14(c), for channel 0 at clock interval 0, it accommodates data from bit 0 to bit 3 out of the 16-bit pixel data of pixel G10 arranged in row L2. For channel 1 at clock interval 0, it accommodates data from bit 4 to bit 11 out of the 16-bit pixel data of pixel G10. For channel 0 at clock interval 1, it accommodates data from bit 12 to bit 15 out of the 16-bit pixel data of pixel G10. For channel 1 at clock interval 1, it accommodates data from bit 0 to bit 7 out of the 16-bit pixel data of pixel B10 arranged in row L2. For channel 0 at clock interval 0, it accommodates data from bit 8 to bit 11 out of the 16-bit pixel data of pixel B10. For channel 2 at clock interval 0, it accommodates data from bit 12 to bit 15 out of the 16-bit pixel data of pixel B10. For channel 2 at clock interval 0, it accommodates data from bit 0 to bit 3 out of the 16-bit pixel data of pixel G11 arranged in row L2. For channel 0 at clock interval 1, it accommodates data from bit 4 to bit 7 out of the 16-bit pixel data of pixel G11. For channel 2 at clock interval 1, it accommodates data from bit 8 to bit 15 out of the 16-bit pixel data of pixel G11. For the pixel data of pixels B11, G12, and B12 arranged in row L2, the same mapping process as the pixel data of pixel G10, pixel B10, and pixel G11 is performed. According to the modification example (6), the imaging device 20 can efficiently output the RAW data 241 to the outside using the existing HDMI cable 30.

[0093] (7) Figure 15 is a diagram for explaining an example of a transmission format when RAW data 241 is output from imaging device 20 via HDMI cable 30 in modification example (7). Figure 15(a) shows an arrangement example in a dot sequential manner in data memory 24 of 16-bit R pixel data 4, G pixel data 5, and B pixel data 6 of each 16-bit of RAW data 241 when RAW data 241 is stored instead of YUV422 data composed of 8 bits for each component for transmission in YUV422 format 16-bit mode. In row L1, it shows how pixel data of each 16-bit pixel R00, G00, R01, G01, R02, and G02 are arranged in sequence in the horizontal direction Ma. Further, in row L2 following row L1, it shows how pixel data of each 16-bit pixel G10, B10, G11, B11, G12, and B12 are arranged in sequence in the horizontal direction Ma.

[0094] In Figures 15(b) and (c), a total of 24 bits of data can be accommodated in each clock interval. Following the example of the YUV422 format 16-bit mode, for two channels excluding transmission channel 0 in one clock interval, 8 bits each are used to accommodate 16-bit data for a total of one pixel of RAW data 241 in two fields.

[0095] In the example shown in Figure 15(b), in channel 1 at clock interval 0, data from bits 0 to 7 of the 16-bit pixel data of pixel R00 arranged in row L1 is accommodated, and in channel 1 at clock interval 1, data from bits 8 to 15 of the 16-bit pixel data of pixel R00 is accommodated. In channel 2 at clock interval 0, data from bits 0 to 7 of the 16-bit pixel data of pixel G00 arranged in row L1 is accommodated, and in channel 2 at clock interval 1, data from bits 8 to 15 of the 16-bit pixel data of pixel G00 is accommodated. For the pixel data of pixels R01, G01, R02, and G02 arranged in row L1, the same mapping process as the pixel data of pixel R00 and pixel G00 is performed.

[0096] In the example shown in FIG. 15(c), for channel 1 at the time of clock interval 0, among the 16-bit pixel data of pixel G10 arranged in row L2, data from bit 0 to bit 7 is accommodated, and for channel 1 at the time of clock interval 1, among the 16-bit pixel data of pixel G10, data from bit 8 to bit 15 is accommodated. For channel 2 at the time of clock interval 0, among the 16-bit pixel data of pixel B10 arranged in row L2, data from bit 0 to bit 7 is accommodated, and for channel 2 at the time of clock interval 1, among the 16-bit pixel data of pixel B10, data from bit 8 to bit 15 is accommodated. For the pixel data of pixels G11, B11, G12, and B12 arranged in row L2, the same mapping process as the pixel data of pixel G10 and pixel B10 is performed.

[0097] According to Modification (7), the position of the accommodation boundary of each pixel data of RAW data 241 is included in the position of the accommodation boundary of each pixel data of developed data 242 in the YUV422 format 16-bit mode. If the imaging device 20 and the image recording device 40 support the transmission format for the developed data 242, they can support the transmission process of the RAW data 241.

[0098] (8) FIG. 16 is a diagram for explaining an example of the transmission format when RAW data 241 is output from the imaging device 20 via the HDMI cable 30 in Modification (8). FIG. 16(a) shows an arrangement example in a dot sequential manner in the data memory 24 of each 12-bit R pixel data 4, G pixel data 5, and B pixel data 6 of RAW data 241 when RAW data 241 is stored instead of YUV422 data composed of 8 bits for each component for transmission in the YUV422 format 16-bit mode. In row L1, it shows how the pixel data of each 12-bit pixel R00, G00, R01, G01, R02, G02, R03, and G03 are sequentially arranged in the horizontal direction Ma. Further, in row L2 following row L1, it shows how the pixel data of each 12-bit pixel G10, B10, G11, B11, G12, B12, G13, and B13 are sequentially arranged in the horizontal direction Ma.

[0099] In FIGS. 16(b) and 16(c), although a total of 24-bit data can be accommodated in each clock interval, following the example of the YUV422 format 16-bit mode, for two channels excluding transmission channel 0 in one clock interval, 8 bits each are accommodated in a total of two fields, and for each 12-bit one pixel of the RAW data 241 and the remaining 4-bit 16-bit data.

[0100] In the example shown in FIG. 16(b), in channel 1 at clock interval 0, 0 to 7 bits of the 12-bit pixel data of pixel R00 arranged in row L1 are accommodated, and in channel 1 at clock interval 1, 8 to 11 bits of the 12-bit pixel data of pixel R00 are accommodated. In channel 2 at clock interval 0, 4 to 11 bits of the 12-bit pixel data of pixel G00 arranged in row L1 are accommodated, and in channel 1 at clock interval 1, 0 to 3 bits of the 12-bit pixel data of pixel G00 are accommodated. In channel 2 at clock interval 1, 0 to 7 bits of the 12-bit pixel data of pixel R01 arranged in row L1 are accommodated, and in channel 1 at clock interval 2, 8 to 11 bits of the 12-bit pixel data of pixel R01 are accommodated. In channel 1 at clock interval 2, 0 to 3 bits of the 12-bit pixel data of pixel G01 arranged in row L1 are accommodated, and in channel 1 at clock interval 3, 4 to 11 bits of the 12-bit pixel data of pixel G01 are accommodated.

[0101] For channel 2 during the clock interval 2, it accommodates the data from bit 0 to bit 7 of the 12-bit pixel data of pixel R02 arranged in row L1. For channel 2 during the clock interval 3, it accommodates the data from bit 8 to bit 11 of the 12-bit pixel data of pixel R02. For channel 2 during the clock interval 3, it accommodates the data from bit 0 to bit 3 of the 12-bit pixel data of pixel G02 arranged in row L1. For channel 1 during the clock interval 4, it accommodates the data from bit 4 to bit 11 of the 12-bit pixel data of pixel G02. For channel 2 during the clock interval 4, it accommodates the data from bit 8 to bit 11 of the 12-bit pixel data of pixel R03 arranged in row L1. For channel 1 during the clock interval 5, it accommodates the data from bit 0 to bit 7 of the 12-bit pixel data of pixel R03. For channel 2 during the clock interval 4, it accommodates the data from bit 0 to bit 3 of the 12-bit pixel data of pixel G03 arranged in row L1. For channel 2 during the clock interval 5, it accommodates the data from bit 4 to bit 11 of the 12-bit pixel data of pixel G03.

[0102] In the example shown in FIG. 16(c), for channel 1 at clock interval 0, among the 12-bit pixel data of pixel G10 arranged in row L2, data from bit 0 to bit 7 is accommodated, and for channel 1 at clock interval 1, among the 12-bit pixel data of pixel G10, data from bit 8 to bit 11 is accommodated. For channel 2 at clock interval 0, among the 12-bit pixel data of pixel B10 arranged in row L2, data from bit 4 to bit 11 is accommodated, and for channel 1 at clock interval 1, among the 12-bit pixel data of pixel B10, data from bit 0 to bit 3 is accommodated. For channel 2 at clock interval 1, among the 12-bit pixel data of pixel G11 arranged in row L2, data from bit 0 to bit 7 is accommodated, and for channel 1 at clock interval 2, among the 12-bit pixel data of pixel G11, data from bit 8 to bit 11 is accommodated. For channel 1 at clock interval 2, among the 12-bit pixel data of pixel B11 arranged in row L2, data from bit 0 to bit 3 is accommodated, and for channel 1 at clock interval 3, among the 12-bit pixel data of pixel B11, data from bit 4 to bit 11 is accommodated.

[0103] For channel 2 during clock interval 2, it accommodates the data from bit 0 to bit 7 of the 12-bit pixel data of pixel G12 arranged in row L2. For channel 2 during clock interval 3, it accommodates the data from bit 8 to bit 11 of the 12-bit pixel data of pixel G12. For channel 2 during clock interval 3, it accommodates the data from bit 0 to bit 3 of the 12-bit pixel data of pixel B12 arranged in row L2. For channel 1 during clock interval 4, it accommodates the data from bit 4 to bit 11 of the 12-bit pixel data of pixel B12. For channel 2 during clock interval 4, it accommodates the data from bit 8 to bit 11 of the 12-bit pixel data of pixel G13 arranged in row L2. For channel 1 during clock interval 5, it accommodates the data from bit 0 to bit 7 of the 12-bit pixel data of pixel G13. For channel 2 during clock interval 4, it accommodates the data from bit 0 to bit 3 of the 12-bit pixel data of pixel B13 arranged in row L2. For channel 2 during clock interval 5, it accommodates the data from bit 4 to bit 11 of the 12-bit pixel data of pixel B13. According to the modification example (8), the imaging device 20 can externally output the RAW data 241 using the existing HDMI cable 30.

[0104] (9) Figure 17 is a diagram for explaining an example of a transmission format when RAW data 241 is output from the imaging device 20 in the modification example (9) via the HDMI cable 30. Figure 17(a) shows an arrangement example of each 16-bit R pixel data 4, G pixel data 5, and B pixel data 6 of the RAW data 241 in the data memory 24 in a line sequential method or a plane sequential method when the RAW data 241 is stored instead of YUV422 data composed of 8 bits for each component for transmission in the YUV422 format 16-bit mode. Note that the arrangement example of the D pixel data 7 which is dummy data is omitted from the illustration. In the row L1, the state where the pixel data of each 16-bit pixel R00, G00, and R01 are sequentially arranged in the horizontal direction Ma is shown. Further, in the row L2 following the row L1, the state where the pixel data of each 16-bit pixel G10, B10, and G11 are sequentially arranged in the horizontal direction Ma is shown.

[0105] In Figures 17(b) and (c), although a total of 24 bits of data can be accommodated in each clock interval, following the example of the YUV422 format 16-bit mode, by using two intervals of clocks, for one channel of only the transmission channel 1, 16-bit data for one pixel in total of each 16-bit data constituting the RAW data 241 is accommodated in two fields by 8 bits each.

[0106] In the example shown in FIG. 17(b), for channel 1 at clock interval 0, among the 16-bit pixel data of pixel R00 arranged in row L1, data from bit 0 to bit 7 is accommodated, and for channel 1 at clock interval 1, among the 16-bit pixel data of pixel R00, data from bit 8 to bit 15 is accommodated. For channel 1 at clock interval 2, among the 16-bit pixel data of pixel G00 arranged in row L1, data from bit 0 to bit 7 is accommodated, and for channel 1 at clock interval 3, among the 16-bit pixel data of pixel G00, data from bit 8 to bit 15 is accommodated. For channel 1 at clock interval 4, among the 16-bit pixel data of pixel R01 arranged in row L1, data from bit 0 to bit 7 is accommodated, and for channel 1 at clock interval 5, among the 16-bit pixel data of pixel R01, data from bit 8 to bit 15 is accommodated.

[0107] In the example shown in FIG. 17(c), for channel 1 at clock interval 0, among the 16-bit pixel data of pixel G10 arranged in row L2, data from bit 0 to bit 7 is accommodated, and for channel 1 at clock interval 1, among the 16-bit pixel data of pixel G10, data from bit 8 to bit 15 is accommodated. For channel 1 at clock interval 2, among the 16-bit pixel data of pixel B10 arranged in row L2, data from bit 0 to bit 7 is accommodated, and for channel 1 at clock interval 3, among the 16-bit pixel data of pixel B10, data from bit 8 to bit 15 is accommodated. For channel 1 at clock interval 4, among the 16-bit pixel data of pixel G11 arranged in row L2, data from bit 0 to bit 7 is accommodated, and for channel 1 at clock interval 5, among the 16-bit pixel data of pixel G11, data from bit 8 to bit 15 is accommodated.

[0108] According to Modification Example (9), the position of the accommodation boundary of each pixel data of RAW data 241 is included in the position of the accommodation boundary of each pixel data of developed data 242 in the YUV422 format 16-bit mode. If the imaging device 20 and the image recording device 40 correspond to the transmission format for the developed data 242, they can correspond to the transmission process of the RAW data 241.

[0109] (10) FIG. 18 is a diagram for explaining an example of a transmission format when RAW data 241 is output from the imaging device 20 in the modification example (10) via the HDMI cable 30. FIG. 18(a) shows an arrangement example of each 16-bit R pixel data 4, G pixel data 5, and B pixel data 6 of the RAW data 241 in the data memory 24 in a plane sequential method or a plane and dot sequential method when the RAW data 241 is stored instead of the YUV420 data composed of 16 bits for each component for transmission in the YUV420 format 48-bit mode. Note that the arrangement example of the D pixel data 7 which is dummy data is omitted from the illustration. In the row L1, the pixel data of each 16-bit pixel R00, G00, R01, G01, R02, and G02 are arranged in order in the horizontal direction Ma. Further, in the row L2 following the row L1, the pixel data of each 16-bit pixel G10, B10, G11, B11, G12, and B12 are arranged in order in the horizontal direction Ma.

[0110] In FIGS. 18(b) and (c), a total of 24 bits of data can be accommodated in each clock interval. Following the example of the YUV420 format 48-bit mode, for two channels excluding the transmission channel 0 in one clock interval, 8 bits each are used to accommodate a total of 16 bits of data for one pixel of the RAW data 241 in two fields.

[0111] In the example shown in FIG. 18(b), for channel 1 at clock interval 0, among the 16-bit pixel data of pixel R00 arranged in row L1, data from bit 0 to bit 7 is accommodated, and for channel 1 at clock interval 1, among the 16-bit pixel data of pixel R00, data from bit 8 to bit 15 is accommodated. For channel 2 at clock interval 0, among the 16-bit pixel data of pixel G00 arranged in row L1, data from bit 0 to bit 7 is accommodated, and for channel 2 at clock interval 1, among the 16-bit pixel data of pixel G00, data from bit 8 to bit 15 is accommodated. For the pixel data of pixels R01, G01, R02, and G02 arranged in row L1, the same mapping process as the pixel data of pixel R00 and pixel G00 is performed.

[0112] In the example shown in FIG. 18(c), for channel 1 at clock interval 0, among the 16-bit pixel data of pixel G10 arranged in row L2, data from bit 0 to bit 7 is accommodated, and for channel 1 at clock interval 1, among the 16-bit pixel data of pixel G10, data from bit 8 to bit 15 is accommodated. For channel 2 at clock interval 0, among the 16-bit pixel data of pixel B10 arranged in row L2, data from bit 0 to bit 7 is accommodated, and for channel 2 at clock interval 1, among the 16-bit pixel data of pixel B10, data from bit 8 to bit 15 is accommodated. For the pixel data of pixels G11, B11, G12, and B12 arranged in row L2, the same mapping process as the pixel data of pixel G10 and pixel B10 is performed.

[0113] According to the modification example (10), the position of the accommodation boundary of each pixel data of the RAW data 241 is included in the position of the accommodation boundary of each pixel data of the developed data 242 in the YUV420 format 48-bit mode. If the imaging device 20 and the image recording device 40 correspond to the transmission format for the developed data 242, they can support the transmission process of the RAW data 241.

[0114] (11) FIG. 19 is a diagram for explaining an example of a transmission format when RAW data 241 is output from the imaging device 20 in the modification example (11) via the HDMI cable 30. FIG. 19(a) shows an arrangement example of each 16-bit R pixel data 4, G pixel data 5, and B pixel data 6 of the RAW data 241 in the data memory 24 in a plane sequential method or a plane-by-plane sequential method when the RAW data 241 is stored instead of YUV420 data composed of 8 bits for each component for transmission in the YUV420 format 24-bit mode. Note that an arrangement example of D pixel data 7 which is dummy data is omitted from the illustration. In row L1, it is shown that pixel data of pixels R00, G00, R01, G01, R02, and G02 each having 16 bits are sequentially arranged in the horizontal direction Ma. Further, in row L2 following row L1, it is shown that pixel data of pixels G10, B10, G11, B11, G12, and B12 each having 16 bits are sequentially arranged in the horizontal direction Ma.

[0115] In FIGS. 19(b) and (c), a total of 24 bits of data can be accommodated in each clock interval. However, following the example of the YUV420 format 24-bit mode, for two channels excluding transmission channel 0 in one clock interval, 8 bits each are used to accommodate 16-bit data for a total of one pixel constituting the RAW data 241 in two fields.

[0116] In the example shown in FIG. 19(b), for channel 1 at the clock interval 0, among the 16-bit pixel data of pixel R00 arranged in row L1, data from bit 0 to bit 7 is accommodated, and for channel 2 at the clock interval 0, among the 16-bit pixel data of pixel R00, data from bit 8 to bit 15 is accommodated. For channel 1 at the clock interval 1, among the 16-bit pixel data of pixel G00 arranged in row L1, data from bit 0 to bit 7 is accommodated, and for channel 2 at the clock interval 1, among the 16-bit pixel data of pixel G00, data from bit 8 to bit 15 is accommodated. For the pixel data of pixels R01, G01, R02, and G02 arranged in row L1, the same mapping process as the pixel data of pixel R00 and pixel G00 is performed.

[0117] In the example shown in FIG. 19(c), for channel 1 at the clock interval 0, among the 16-bit pixel data of pixel G10 arranged in row L2, data from bit 0 to bit 7 is accommodated, and for channel 2 at the clock interval 0, among the 16-bit pixel data of pixel G10, data from bit 8 to bit 15 is accommodated. For channel 1 at the clock interval 1, among the 16-bit pixel data of pixel B10 arranged in row L2, data from bit 0 to bit 7 is accommodated, and for channel 2 at the clock interval 1, among the 16-bit pixel data of pixel B10, data from bit 8 to bit 15 is accommodated. For the pixel data of pixels G11, B11, G12, and B12 arranged in row L2, the same mapping process as the pixel data of pixel G10 and pixel B10 is performed.

[0118] According to the modification example (11), the position of the accommodation boundary of each pixel data of the RAW data 241 is included in the position of the accommodation boundary of each pixel data of the developed data 242 in the YUV420 format 24-bit mode. If the imaging device 20 and the image recording device 40 correspond to the transmission format for the developed data 242, the transmission process of the RAW data 241 can be supported.

[0119] (12) FIG. 20 is a diagram for explaining an example of a transmission format when RAW data 241 is output from the imaging device 20 in the modification example (12) via the HDMI cable 30. FIG. 20(a) shows an arrangement example of each 12-bit R pixel data 4, G pixel data 5, and B pixel data 6 of the RAW data 241 in the data memory 24 in a line sequential method or a plane sequential method when the RAW data 241 is stored instead of the YUV420 data composed of 12 bits for each component for transmission in the YUV420 format 36-bit mode. Note that the arrangement example of the D pixel data 7 which is dummy data is omitted from the illustration. In row L1, it is shown that the pixel data of pixels R00, G00, R01, G01, R02, G02, R03, and G03 of 12 bits each are arranged in order in the horizontal direction Ma. Further, in row L2 following row L1, it is shown that the pixel data of pixels G10, B10, G11, B11, G12, B12, G13, and B13 of 12 bits each are arranged in order in the horizontal direction Ma.

[0120] In FIGS. 20(b) and (c), although a total of 24 bits of data can be accommodated in each clock interval, following the example of the YUV420 format 36-bit mode, the total 48-bit data of 4 pixels of 12 bits each constituting the RAW data 241 is accommodated in a total of 6 fields of 8 bits each for 2 channels excluding the transmission channel 0 in each of 3 consecutive clock intervals.

[0121] In the example shown in FIG. 20(b), in channel 1 at clock interval 0, the data from bit 0 to bit 7 of the 12-bit pixel data of pixel R00 arranged in row L1 is accommodated, and in channel 1 at clock interval 1, the data from bit 8 to bit 11 of the 12-bit pixel data of pixel R00 is accommodated. In channel 2 at clock interval 0, the data from bit 0 to bit 7 of the 12-bit pixel data of pixel G00 arranged in row L1 is accommodated, and in channel 2 at clock interval 1, the data from bit 8 to bit 11 of the 12-bit pixel data of pixel G00 is accommodated.

[0122] Channel 1 during clock interval 1 accommodates 0 to 3 bits of data out of the 12 bits of pixel data of pixel R01 arranged in row L1, and channel 1 during clock interval 2 accommodates 4 to 11 bits of data out of the 12 bits of pixel data of pixel R01. Channel 2 during clock interval 1 accommodates 0 to 3 bits of data out of the 12 bits of pixel data of pixel G01 arranged in row L1, and channel 2 during clock interval 2 accommodates 4 to 11 bits of data out of the 12 bits of pixel data of pixel G01. The same mapping process as for the pixel data of pixels R00, pixel G00, pixel R01 and pixel G01 is also performed on the pixel data of pixels R02, G02, R03, and G03 arranged in row L1.

[0123] 20(c), channel 1 during clock interval 0 accommodates 0 to 7 bits of data of the 12-bit pixel data of pixel G10 arranged in row L2, and channel 1 during clock interval 1 accommodates 8 to 11 bits of data of the 12-bit pixel data of pixel G10. Channel 2 during clock interval 0 accommodates 0 to 7 bits of data of the 12-bit pixel data of pixel B10 arranged in row L2, and channel 2 during clock interval 1 accommodates 8 to 11 bits of data of the 12-bit pixel data of pixel B10.

[0124] For channel 1 during clock interval 1, it accommodates the data from bit 0 to bit 3 of the 12-bit pixel data of pixel G11 arranged in row L2. For channel 1 during clock interval 2, it accommodates the data from bit 4 to bit 11 of the 12-bit pixel data of pixel G11. For channel 2 during clock interval 1, it accommodates the data from bit 0 to bit 3 of the 12-bit pixel data of pixel B11 arranged in row L2. For channel 2 during clock interval 2, it accommodates the data from bit 4 to bit 11 of the 12-bit pixel data of pixel B11. For channel 2 during clock interval 1, it accommodates the data from bit 0 to bit 3 of the 12-bit pixel data of pixel B11 arranged in row L2. For channel 2 during clock interval 2, it accommodates the data from bit 4 to bit 11 of the 12-bit pixel data of pixel B11. For the pixel data of pixels G12, B12, G13, and B13 arranged in row L2, the same mapping process as the pixel data of pixel G10, pixel B10, pixel G11, and pixel B11 is performed.

[0125] According to the modification example (12), the position of the accommodation boundary of each pixel data of the RAW data 241 is included in the position of the accommodation boundary of each pixel data of the developed data 242 in the YUV420 format 36-bit mode. If the imaging device 20 and the image recording device 40 are compatible with the transmission format for the developed data 242, they can be compatible with the transmission process of the RAW data 241.

[0126] (13) In the above-described embodiments and modifications, in each clock interval of the transmission format when the RAW data 241 is output from the imaging device 20 via the HDMI cable 30, three channels from transmission channel 0 to 2 are provided, and 8-bit data can be accommodated in each field assigned to each channel. In the above-described embodiments and modifications, when accommodating a total of 24-bit data in the three channels from channel 0 to 2 in each clock interval, it was decided to use them in the order of channel 0, 1, and 2. However, the order of the transmission channels is not limited to this, and for example, it may be in the order of channel 2, 1, and 0, or for example, it may be in the order of channel 1, 0, and 2. Taking the first embodiment as an example, as shown in FIG. 7, when accommodating a total of 24-bit data in the three channels from channel 0 to 2 in each clock interval, it is used in the order of channel 0, 1, and 2. However, as shown in FIG. 21, it may be in the order of channel 2, 1, and 0, or as shown in FIG. 22, it may be in the order of channel 1, 0, and 2. The same applies to the second embodiment and other modifications.

[0127] (14) In the above-described embodiments and modifications, the transmission format of the RAW data 241 is associated with the transmission formats of YUV data such as the YUV444 format 48-bit mode and the YUV422 format 24-bit mode. However, the transmission format of the RAW data 241 does not necessarily have to be associated with the transmission format of the YUV data. The transmission format of the RAW data 241 may be associated with the transmission format of the RGB data. Alternatively, the transmission format of the RAW data 241 may freely accommodate the RAW data 241 in the three channels from channel 0 to 2 in each clock interval or in a plurality of clock intervals. In that case, the sizes of the R pixel data 4, G pixel data 5, and B pixel data 6 that make up the RAW data 241 may be sizes other than 16 bits and 12 bits used in the above-described embodiments and modifications, for example, 14 bits.

[0128] In the above-described embodiments and modifications, since the connection member connecting the imaging device 20 and the image recording device 40 is the HDMI cable 30, the transmission format of the RAW data 241 is the HDMI transmission format. However, the connection member connecting the imaging device 20 and the image recording device 40 may be an SDI cable. In that case, the SDI transmission format is used for the transmission format of the RAW data 241.

[0129] In the above, various embodiments and modifications have been described, but the present invention is not limited to these contents. Other aspects conceivable within the scope of the technical idea of the present invention are also included in the scope of the present invention.

[0130] The disclosure content of the following priority-based application is incorporated herein by reference. Japanese Patent Application No. 2018-74272 (filed on April 6, 2018)

Explanation of Reference Numerals

[0131] 1 Y pixel data, 2 U pixel data, 3 V pixel data, 4 R pixel data, 5 G pixel data, 6 B pixel data, 7 D pixel data, 10 image transmission and recording system, 11 image transmission and recording system, 20 imaging device, 21 imaging device control unit, 22 image sensor, 23 sensor data input circuit, 24 data memory, 25 development processing unit, 26 output control unit, 27 display unit, 30 HDMI cable, 40 image recording device, 41 image recording device control unit, 42 external input control unit, 43 image processing unit, 44 storage device, 45 display output control unit, 46 display unit, 241 RAW data, 242 developed data, 261 display output control unit, 262 external output control unit.

Claims

[Claim 1] an image sensor that captures an image of a subject and outputs an image signal; a development processing unit that generates development data based on the imaging signal; an output control unit which, for a predetermined transmission format having a plurality of channels and fields, at least one field including a plurality of fields each assigned to a different channel among the plurality of channels, places first pixel data in the at least one field when outputting the imaging signal, divides and places second pixel data corresponding to a position of the first pixel data in the developed data in the plurality of fields, and outputs the developed data to an external device in the predetermined transmission format via a connection member connecting to the external device; An imaging device comprising:

Images