Transistor

Abstract

To provide a display device in which images can be rewritten for only an optional region, or a display device capable of partial driving in which a circuit structure including wires is simplified.SOLUTION: Shift of a selection signal in a shift register included in a scan line driving circuit and supply of the selection signal to a scan line are independently controlled. Thus, images can be rewritten only for an optional region. This operation is achieved by providing a wire that supplies a clock signal or a signal representing a fixed potential. Therefore, the display device including such wires is a display device capable of partial driving, in which a circuit structure including the wires is simplified.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a display device. [Background technology]

[0002] A display device that can reduce power consumption by partially rewriting images has been developed. In such a display device, some of the scanning lines are turned off in order to partially rewrite the image. The scanning line driver circuit includes a scanning line driver circuit capable of driving only a part of the scanning line (also called partial driving).

[0003] In Patent Document 1, a scanning line driving circuit (gate driving section) capable of realizing partial driving is described. Specifically, the scanning line driving circuit (gate driving section) disclosed in Patent Document 1 is The number of participants is divided into several groups. Each group is assigned a different starting point. The operation is controlled by a scanning start signal. The scanning line driver circuit (gate driver) inputs a start pulse (scanning start signal) to each group. By controlling this, partial drive is achieved. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2007-004176 A Summary of the Invention [Problem to be solved by the invention]

[0005] However, in the display device disclosed in Patent Document 1, it is difficult to know which area the image is to be rewritten. The only way to decide whether to perform the calculation is to select each group in advance. You cannot choose to redraw the image for every scanline (e.g., every scanline). In the display device disclosed in Patent Document 1, the number of signals required to drive the scanning line driving circuit is The number of the scanning line driving circuits increases according to the number of groups into which the scanning line driving circuits are divided. The number of wirings increases according to the number of groups. When the pixel unit is formed on the same substrate as the pixel unit, the substrate on which the pixel unit is formed and the external circuit are separated according to the number of groups. The number of connection points with roads will increase.

[0006] In view of the above-mentioned problems, one embodiment of the present invention is a method for rewriting an image only in an arbitrary area. Another object of the present invention is to provide a display device capable of partial driving. One object of the present invention is to simplify the structure of a circuit including wiring in a display device that can display an image. One embodiment of the present invention has at least one of the above objects. [Means for solving the problem]

[0007] The above problem is solved by the fact that the scanning line driving circuit selectively supplies a selection signal to each of the plurality of scanning lines. For example, the scanning line driving circuit may be provided with a plurality of pulse output circuits. In the case where the shift register is configured as The selection signal is shifted to the subsequent pulse output circuit using the clock signal and By selectively using a fixed potential and a fixed potential to supply a signal to the scanning line, a plurality of scanning It is possible to selectively apply a selection signal to the scan lines. When the clock signal is used, it is a selection signal, and when it is a fixed potential, it is a non-selection signal. By designing the gates so that the gates are aligned in a direction perpendicular to the scanning line, it is possible to control the supply of selection signals to the scanning lines. .

[0008] Specifically, one aspect of the present invention is a method for detecting a pixel value by a pixel array including a plurality of pixels arranged in m rows and n columns; A first scanning line electrically connected to n pixels arranged in the first row of the first scanning line, mth scanning line electrically connected to n pixels arranged in the mth row among the pixels of the mth row; a first pulse output circuit electrically connected to the first scanning line, and an mth pulse output circuit electrically connected to the kth pulse output circuit (k is , a natural number between 2 and m) is a wiring whose source and drain supply a clock signal the other of the source and drain is electrically connected to the k+1 pulse output circuit. a first transistor, one of a source and a drain of which is connected to the clock signal or is electrically connected to a wiring that supplies a fixed potential, and the other of the source and drain is a second transistor electrically connected to the scanning line; and a second transistor electrically connected to the k-1th pulse output circuit. In response to an input signal, the potential of the gate of the first transistor and the potential of the gate of the second transistor are and a control circuit for controlling the potential of the gate of the transistor.

[0009] In this specification, etc., when something is explicitly stated as singular, it is understood to be singular. However, it is not limited to this, and it is also possible to have a plurality of them. In particular, where something is explicitly stated as plural, it is preferable that it be plural. However, the present invention is not limited to this and may be singular.

[0010] In this specification, the terms "first," "second," "third," and the like refer to various elements, members, regions, layers, Used to describe an area in a way that distinguishes it from others. Thus, first, second, third, etc. The term does not limit the number of elements, members, regions, layers, areas, etc. , "first" can be replaced with "second" or "third", etc. Effect of the Invention

[0011] In a display device according to one embodiment of the present invention, a selection signal in a shift register included in a scanning line driver circuit is It is possible to independently control the shift of the signal and the supply of the selection signal to the scanning line. Therefore, it is possible to selectively supply a selection signal to each of the multiple scanning lines. That is, the display device of one embodiment of the present invention rewrites an image only in an arbitrary region. It is possible to do so.

[0012] In addition, in the display device of one embodiment of the present invention, the above operation is performed by using a clock signal or a fixed potential. This can be achieved by providing wiring for supplying signals. The display device according to one embodiment of the present invention is a display device capable of partial driving, and has a circuit configuration including wiring. It is possible to simplify the configuration. [Brief description of the drawings]

[0013] [Figure 1] FIG. 1A is a diagram showing an example of a display device, and FIG. 1B is a circuit diagram showing an example of a pixel. [Diagram 2] 1A is a diagram showing a configuration example of a scanning line driving circuit, FIG. 1B is a timing chart showing an operation example of the scanning line driving circuit, and FIG. 1C is a diagram showing a configuration example of a pulse output circuit. [Diagram 3] FIG. 2A is a circuit diagram showing an example of a pulse output circuit, and FIGS. 2B and 2C are timing charts showing an example of the operation of the pulse output circuit. [Figure 4] FIG. 2 is a diagram showing an example of the configuration of a controller. [Diagram 5]FIG. 1 is a cross-sectional view illustrating an example of a transistor. [Figure 6] FIG. 13 shows characteristics of a transistor. [Figure 7] Circuit diagram of an element for evaluating transistor characteristics. [Figure 8] 1 is a timing chart of an element for evaluating transistor characteristics. [Figure 9] FIG. 13 shows characteristics of a transistor. [Figure 10] FIG. 13 shows characteristics of a transistor. [Figure 11] FIG. 13 shows characteristics of a transistor. [Figure 12] 1A and 1B are circuit diagrams showing an example of a pulse output circuit. [Figure 13] 1A and 1B are circuit diagrams showing an example of a pulse output circuit. [Figure 14] 1A and 1B are circuit diagrams showing an example of a pulse output circuit. [Figure 15] 1A to 1C are cross-sectional views illustrating an example of a transistor. [Figure 16] 1A to 1F are diagrams showing examples of electronic devices. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and may be modified in any form without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various modifications may be made to the details. The present invention should not be construed as being limited to the description of the following embodiments.

[0015] (One example of a display device) Hereinafter, a display device according to one embodiment of the present invention will be described with reference to FIGS.

[0016] FIG. 1A is a diagram showing a configuration example of a display device. The display device shown in FIG. A scanning line driving circuit 11, a signal line driving circuit 12, and a controller 13, each of which m lines (m The scanning lines 14 are arranged parallel or approximately parallel to each other, and the signal line driver 15 is arranged parallel to the scanning lines 14. n signal lines 15 (n is a natural number of 2 or more) whose potentials are controlled by an operation circuit 12; Furthermore, the pixel section 10 has a plurality of pixels 16 arranged in a matrix (m rows and n columns). Each scanning line 14 corresponds to at least one of a plurality of pixels 16 arranged in a matrix. Each signal line 15 is electrically connected to a plurality of pixels 16 arranged in a row. Among the plurality of pixels 16 arranged in a row, the plurality of pixels 16 arranged in any one of the columns are supplied with electricity. The scanning line driving circuit 11 is electrically connected to the controller 13. A start signal for the scanning line drive circuit (GSP), a clock signal for the scanning line drive circuit (GCK), Signals such as the circuit clock signal (PGCK), high power supply potential (Vdd), and low power supply potential A driving power supply such as (Vss) is input to the signal line driving circuit 12. A start signal (SP) for the signal line driver circuit and a clock signal (S CK), data signal (DATA), and other signals, as well as high power supply potential (Vdd), low power supply potential ( A driving power supply such as Vss is input.

[0017] FIG. 1B is a diagram showing an example of a circuit diagram of a pixel 16 included in the display device shown in FIG. In the pixel 16 shown in FIG. 1B, the gate is electrically connected to the scanning line 14, and the source and A transistor 17 having one electrode and one drain electrically connected to a signal line 15, The other electrode of the transistor 17 is electrically connected to the other of the source and drain. A capacitor 18 is electrically connected to a wiring (also called a capacitance line) that supplies a potential. (also called a pixel electrode) is connected to the other of the source and drain of the transistor 17 and the capacitor element 18 The other electrode (also called the counter electrode) supplies a counter potential. The liquid crystal element 19 is electrically connected to a wiring. In addition, the capacitance potential and the opposing potential can be set to the same potential. It is possible.

[0018] (Configuration example of the scanning line driving circuit 11) FIG. 2A shows a configuration example of the scanning line driver circuit 11 included in the display device shown in FIG. The scanning line driving circuit 11 shown in FIG. 2(A) is a first scanning line driving circuit clock signal. A wiring for supplying a clock signal (GCK1) for the fourth scanning line driver circuit to a wiring for supplying a clock signal (GCK4) for the fourth scanning line driver circuit A wiring for supplying a partial clock signal (PGCK1) for the first scanning line driving circuit. A wiring for supplying a partial clock signal (PGCK4) for the first to fourth scanning line driver circuits, A first pulse output circuit 20_1 to a first pulse output circuit 20_2 electrically connected to the scanning line 14 arranged in the first row, an m-th pulse output circuit 20_m electrically connected to the scanning line 14 arranged in the m-th row; has.

[0019] FIG. 2B is a diagram showing an example of a specific waveform of the above signal. The clock signal (GCK1) for the scanning line driver circuit periodically goes to a high level potential (Fig. 2(B) ) is the same potential as the high power supply potential (Vdd) and the low level potential (Figure 2(B) is the same potential as the low power supply potential The duty ratio of the signal is 1 / 2, and the first The second scanning line driving circuit clock signal (GCK2) is a clock signal for the first scanning line driving circuit. The third scanning line driving circuit is a signal that is shifted in phase by 1 / 4 period from the first scanning line driving signal (GCK1). The clock signal (GCK3) for the first scanning line driving circuit is derived from the clock signal (GCK1) for the first scanning line driving circuit. The signal is shifted in phase by 1 / 2 period (i.e., the first scanning line driving circuit clock signal ( The fourth scanning line driving circuit clock signal (GCK4) is an inverted signal of the fourth scanning line driving circuit clock signal (GCK1). ) is a signal whose phase is shifted by 3 / 4 cycle from the first scanning line driving circuit clock signal (GCK1). (That is, it is an inverted signal of the clock signal (GCK2) for the second scanning line driving circuit.) The partial clock signal (PGCK1) for the first scanning line driving circuit is The clock signal (GCK1) and the fixed potential (in Fig. 2(B) are the low power supply potential (Vss) and The signal selectively indicates either one of the two potentials. The control circuit determines which signal (GCK1 or fixed potential) the clock signal (PGCK1) indicates. Similarly, the second scanning line driving circuit partial clock signal (PG CK2) is either the second scanning line driving circuit clock signal (GCK2) or a fixed potential The third scanning line driving circuit partial clock signal (PGCK3) is , the third scanning line driving circuit clock signal (GCK3) or a fixed potential is selectively The fourth scanning line driving circuit partial clock signal (PGCK4) is a signal indicating the fourth scanning line driving circuit partial clock signal (PGCK4). This signal selectively indicates either the scan line driver clock signal (GCK4) or a fixed potential. be.

[0020] In the above-mentioned display device, the first pulse output circuit 20_1 to the m-th pulse output circuit The circuit 20_m may be a circuit having the same configuration. However, the pulse output circuit The electrical connection relationship between the terminals of the path varies depending on the pulse output circuit. The relationship will be explained with reference to FIGS.

[0021] Each of the first pulse output circuit 20_1 to the m-th pulse output circuit 20_m has a terminal The terminals 21 to 28 are input terminals. Terminal 26 and terminal 28 are output terminals.

[0022] First, the terminal 21 will be described. The terminal 21 of the first pulse output circuit 20_1 is connected to the scanning line Electrically connected to the wiring that supplies the start signal (GSP) for the drive circuit, the second pulse output The terminals 21 of the input circuit 20_2 to the m-th pulse output circuit 20_m are connected to the terminals 21 of the preceding pulse output circuit. It is electrically connected to terminal 28.

[0023] Next, the terminal 22 will be described. The 4a+1th pulse output circuit (a=0, 1, 2... The terminal 22 of (m-4) / 4) supplies a clock signal (GCK1) for the first scanning line driving circuit. The terminal 22 of the 4a+2 pulse output circuit is electrically connected to the wiring that supplies the second scanning It is electrically connected to the wiring that supplies the clock signal (GCK2) for the line driver circuit, and the 4th The terminal 22 of the pulse output circuit supplies a clock signal (GCK3) for the third scanning line driving circuit. The terminal 22 of the 4a+4th pulse output circuit is electrically connected to the wiring that supplies the 4th scan It is electrically connected to a wiring that supplies a clock signal (GCK4) for the line driver circuit.

[0024] Next, terminal 23 will be described. Terminal 23 of the 4a+1th pulse output circuit is the second It is electrically connected to the wiring that supplies the clock signal (GCK2) for the scanning line driving circuit, and the 4th The terminal 23 of the +2 pulse output circuit is a clock signal (GCK3) for the third scanning line driving circuit. The terminal 23 of the 4a+3 pulse output circuit is electrically connected to the wiring that supplies the 4 The fourth a The terminal 23 of the +4 pulse output circuit receives the clock signal (GCK1) for the first scanning line driving circuit. The power supply 11 is electrically connected to a wiring that supplies the power supply 11.

[0025] Next, the terminal 24 will be described. The terminal 24 of the 4a+1th pulse output circuit is the third It is electrically connected to the wiring that supplies the clock signal (GCK3) for the scanning line driving circuit, and the 4th The terminal 24 of the +2 pulse output circuit is a clock signal (GCK4) for the fourth scanning line driving circuit. The terminal 24 of the 4a+3 pulse output circuit is electrically connected to the wiring that supplies the first It is electrically connected to the wiring that supplies the clock signal (GCK1) for the scanning line driving circuit, and the 4th The terminal 24 of the +4 pulse output circuit outputs a clock signal (GCK2) for the second scanning line driving circuit. The power supply 11 is electrically connected to a wiring that supplies the power supply 11.

[0026] Next, the terminal 25 will be described. The terminal 25 of the 4a+1th pulse output circuit is Electrically connected to a wiring that supplies a partial clock signal (PGCK1) for the scanning line driving circuit, The terminal 25 of the 4a+2-th pulse output circuit is connected to the second scanning line driving circuit partial clock signal ( PGCK2) and terminal 2 of the 4a+3 pulse output circuit. 5 is electrically connected to the wiring for supplying the partial clock signal (PGCK3) for the third scanning line driving circuit. The terminal 25 of the 4a+4 pulse output circuit is connected to the fourth scanning line driving circuit partial clock. It is electrically connected to the wiring that supplies the lock signal (PGCK4).

[0027] Next, the terminal 26 will be described. The xth pulse output circuit (x is a natural number greater than or equal to 1 and less than or equal to m) The terminals 26 (number of terminals) are electrically connected to the scanning lines 14 arranged in the xth row.

[0028] Next, the terminal 27 will be described. The terminal 27 of the (b+2)th pulse output circuit is electrically connected to the terminal 28 of the (b+2)th pulse output circuit, and the terminal 27 of the (m)th pulse output circuit is electrically connected to the terminal 28 of the (b+2)th pulse output circuit. The terminal 27 of the pulse output circuit of −1 is a stop signal for the first scanning line driving circuit (GSTP1 ), and the terminal 27 of the mth pulse output circuit is electrically connected to the wiring that supplies the second scanning It is electrically connected to the wiring that supplies the stop signal (GSTP2) for the line driver circuit. The first scanning line driving circuit stop signal (GSTP1) is assumed to be the (m+1)th pulse output circuit. If the m+1-th pulse output circuit is provided with a terminal 28, the m+1-th pulse output circuit will have a corresponding signal output from the terminal 28. Similarly, the second scanning line driving circuit stop signal (GSTP2) is a signal corresponding to the temporary If the (m+2)th pulse output circuit is provided in the (m+2)th pulse output circuit, the terminal These signals correspond to the signals output from the 28. providing an (m+1)th pulse output circuit and an (m+2)th pulse output circuit as Mie circuits; Alternatively, the controller 13 may directly output the signal to the scanning line driving circuit 11. can be supplied.

[0029] The connection relationship of the terminals 28 of each pulse output circuit has already been described. The following is hereby incorporated by reference.

[0030] (Example of pulse output circuit configuration) FIG. 3A is a diagram showing an example of the configuration of the pulse output circuit shown in FIGS. 2A and 2C. The pulse output circuit shown in FIG. 3(A) includes transistors 31 to 41.

[0031] The transistor 31 has a configuration in which one of the source and drain supplies a high power supply potential (Vdd). The gate is electrically connected to a terminal 21. To be continued.

[0032] The transistor 32 has a configuration in which one of the source and drain supplies a low power supply potential (Vss). The other of the source and drain is electrically connected to a line (hereinafter also referred to as a low power supply potential line). It is electrically connected to the other of the source and drain of the transistor 31 .

[0033] The transistor 33 has one of a source and a drain electrically connected to the terminal 22. The other of the source and drain is electrically connected to terminal 28.

[0034] The transistor 34 has one of a source and a drain electrically connected to a low power supply line. The other of the source and drain is electrically connected to terminal 28, and the gate of transistor 32 It is electrically connected to the gate.

[0035] The transistor 35 has one of a source and a drain electrically connected to a low power supply line. The other of the source and drain is connected to the gate of transistor 32 and the gate of transistor 34. The gate is electrically connected to terminal 21.

[0036] The transistor 36 has one of a source and a drain electrically connected to a high power supply potential line. The other of the source and drain is connected to the gate of transistor 32, the gate of transistor 34, and the other of the source and drain of transistor 35, and the gate is connected to terminal 2. 7. One of the source and drain of the transistor 36 is electrically connected to the low voltage A power supply that is higher than the power supply potential (Vss) and lower than the high power supply potential (Vdd) It may also be electrically connected to a wiring that supplies a potential (Vcc).

[0037] The transistor 37 has one of a source and a drain electrically connected to a high power supply potential line. The gate is electrically connected to the terminal 24. One of the terminals may be electrically connected to a wiring that supplies a power supply potential (Vcc). Cut.

[0038] The transistor 38 has a source and a drain that are connected to the gate of the transistor 32. The gate of transistor 34, the other of the source and drain of transistor 35, and The other of the source and drain of the transistor 36 is electrically connected to the other of the source and drain of the transistor 36. The transistor 37 has its gate electrically connected to the terminal 23. are electrically connected.

[0039] The transistor 39 has a source and a drain that are the same as the source and drain of the transistor 31. the other of the inputs and the other of the source and drain of the transistor 32. The other of the source and drain is electrically connected to the gate of transistor 33, and the gate is connected to a high voltage It is electrically connected to a power supply potential line.

[0040] The transistor 40 has one of its source and drain electrically connected to the terminal 25. The other of the drain and the gate is electrically connected to the terminal 26, and the gate of the transistor 33 is The other of the source and drain of the transistor 39 is electrically connected to the ground terminal of the transistor 39 .

[0041] The transistor 41 has one of a source and a drain electrically connected to a low power supply line. The other of the source and drain is electrically connected to terminal 26, and the gate of transistor 32 the gate of transistor 34; the other of the source and drain of transistor 35; The other of the source and drain of transistor 36 and the source and drain of transistor 38 The input is electrically connected to one of the inputs.

[0042] In the following description, the gate of the transistor 33, the source and drain of the transistor 39 are The node to which the other drain and the gate of the transistor 40 are electrically connected is referred to as node A. The gate of transistor 32, the gate of transistor 34, and the source of transistor 35 and the other of the source and drain of transistor 36, and the other of the source and drain of transistor 38 The node to which one of the source and drain of the transistor 41 and the gate of the transistor 41 are electrically connected In this description, the node is referred to as Node B.

[0043] (Example of pulse output circuit operation) An example of the operation of the above-mentioned pulse output circuit will be described with reference to FIGS. FIG. 3B shows a first scanning line driving circuit, which is input to the terminal 25 of the pulse output circuit. Partial clock signal for the fourth scanning line driving circuit (PGCK1) to partial clock signal for the fourth scanning line driving circuit (PGC K4) is the first scanning line driving circuit clock signal (GCK1) to the fourth scanning line driving circuit clock signal (GCK2). Pulse output circuit when either of the clock signals (GCK4) for the line driver circuit is selected The potentials of the signals input to the terminals of the MOSFETs 1 and 2, as well as the potentials of the nodes A and B, are shown in FIG. 3(C) is a part for a first scanning line driving circuit, which is input to the terminal 25 of the pulse output circuit. Clock signal (PGCK1) to partial clock signal for the fourth scanning line driving circuit (PGCK4) When any one of the potentials of the pulse output circuit is a fixed potential (low power supply potential Vss), The potentials of the signals input to the terminals and the potentials of the nodes A and B are shown. 3B and 3C, the first pulse output circuit 20_1 under each condition is The signals input to each terminal and the signals output from the terminal 26 of the first pulse output circuit 20_1 The signal (Gout1) and the signal (SRout1) output from terminal 28 are added in parentheses. In addition, the output signal (Gout2) of the terminal 26 of the second pulse output circuit 20_2 and and an output signal (SRout2) of the terminal 28 of the third pulse output circuit 20_3, 6 output signal (Gout3) and the output signal of terminal 28 (SRout3 = first pulse output The input signal of the terminal 27 of the circuit 20_1 is also shown. , SRout represents an output signal for a scanning line of the pulse output circuit, 4 represents an output signal to a subsequent pulse output circuit.

[0044] First, referring to FIG. 3B, the first running pulse is input to the terminal 25 of the pulse output circuit. Partial clock signal for scanning line driving circuit (PGCK1) - Partial clock signal for fourth scanning line driving circuit Any one of the signals (PGCK4) is a clock signal (GCK1) for the first scanning line driving circuit. 4. The fourth scanning line driving circuit clock signal (GCK4) will be explained below. Reveal.

[0045] In a period t1, a high power supply potential (Vdd) is input to the terminal 21 of the pulse output circuit. This causes the transistors 31 and 35 to be turned on. The potential of the high level (the potential of the transistor 31 or the transistor 39 from the high power supply potential (Vdd) The voltage at node B drops to the low power supply voltage (Vss). In response to this, the transistors 33 and 40 are turned on, and the transistor 32 , 34, and 41 are turned off. As a result, during the period t1, The signal output from terminal 28 becomes the signal input to terminal 22, and is output from terminal 26. The signal that is input to the terminal 25 is the signal that is input to the terminal 25. The signals input to the terminals 22 and 25 of the output circuit are both at the low power supply potential (Vss). Therefore, during the period t1, the pulse output circuit is connected to terminal 2 of the subsequent pulse output circuit. 1, and outputs a low power supply potential (Vss) to the scanning line electrically connected to the terminal 26. Although it does not directly affect the output signal of the pulse output circuit during the period t1, Since the power supply potential (Vss) is input, the transistor 38 is turned off, and a high Since the power supply potential (Vdd) is input, the transistor 37 is turned on, and the terminal 27 is Since the power supply potential (Vss) is input, the transistor 36 is turned off.

[0046] During a period t2, a high power supply potential (Vdd) is applied to the terminals 22 and 25 of the pulse output circuit. The potential of the node A (potential of the source of the transistor 39) is input during the period t1. Therefore, the transistor 39 is turned off. At this time, a high power supply potential (Vdd) is input to the terminals 22 and 25, The capacitive coupling between the source and gate of transistor 33 and the source and gate of transistor 40 Therefore, the potential of the node A (the potential of the gate of the transistor 33 and the potential of the gate of the transistor 40) The level of the load (the load) increases further (bootstrap operation). By doing so, it is possible to output a high voltage without lowering the potential output from the terminals 28 and 26. Therefore, during the period t2, the pulse output circuit The path is connected to the scanning line electrically connected to the terminal 21 and the terminal 26 of the subsequent pulse output circuit. The power supply potential (Vdd) is output. Note that the output signal of the pulse output circuit during the period t2 is However, the low power supply potential (Vss) is input to the terminal 24, so the transistor 37 is in the off state.

[0047] In a period t3, a low power supply potential (Vss) is input to the terminal 21 of the pulse output circuit. This causes the transistors 31 and 35 to be turned off. At this time, the node A is in a floating state. Therefore, the transistor 33 and the transistor 40 are maintained in the on state. As a result, during the period t3, the signal output from the terminal 28 of the pulse output circuit is The signal output from terminal 26 is input to terminal 25. During the period t3, the terminals 22 and 25 of the pulse output circuit are A high power supply potential (Vdd) is input to both of the pulses during the period t3. The output circuit is a scanning circuit electrically connected to the terminals 21 and 26 of the subsequent pulse output circuit. The output of the pulse output circuit during the period t3 is Although it is not directly related to the input signal, the high power supply potential (Vdd) is input to terminal 23, The resistor 38 is turned on.

[0048] During a period t4, a high power supply potential (Vdd) is applied to the terminals 24 and 27 of the pulse output circuit. This causes the transistors 36 and 37 to be turned on. The potential of B is a high level potential (high power supply potential (Vdd) to transistor 36, transistor The potential of the transistor 37 or 38 drops by the threshold voltage of the transistor 38. As a result, the transistors 32, 34, and 41 are turned on. By turning on the transistor 39, the source (one of the source and drain) of the transistor 39 is turned on. The potential of the transistor 39 becomes the low power supply potential (Vss). Therefore, the potential of node A drops to the low power supply potential (Vss). As a result, during the period t4, the pulse output circuit The signal output from the terminal 28 and the signal output from the terminal 26 are connected to a low power supply potential (Vss Therefore, during the period t4, the pulse output circuit A low power supply potential (Vss) is output to the scanning lines electrically connected to the terminals 21 and 26. do.

[0049] After the period t5, a high power supply potential (Vdd) is input to the terminal 21 of the pulse output circuit. Until the power supply voltage Vss is applied to the node A, the node B remains at the high level. Therefore, during this period, the pulse output circuit maintains the pulse output A low power supply potential (Vss) is output to the scanning lines electrically connected to the terminals 21 and 26. do.

[0050] Next, referring to FIG. 3(C), the first Partial clock signal for scanning line driving circuit (PGCK1) to the fourth partial clock signal for scanning line driving circuit When any one of the clock signals (PGCK4) is at a fixed potential (low power supply potential Vss), He explains.

[0051] In a period t1, a high power supply potential (Vdd) is input to the terminal 21 of the pulse output circuit. As described above, during the period t1, the signal output from the terminal 28 of the pulse output circuit is the signal input to terminal 22, and the signal output from terminal 26 is the signal input to terminal 25. During the period t1, the terminals 22 and The signals input to 25 are both at the low power supply potential (Vss). The pulse output circuit is electrically connected to the terminals 21 and 26 of the subsequent pulse output circuit. A low power supply potential (Vss) is output to the connected scan line.

[0052] In a period t2, a high power supply potential (Vdd) is input to the terminal 22 of the pulse output circuit. As described above, by performing the bootstrap operation, the voltage output from the terminal 28 However, the high power supply potential (Vdd) can be achieved without lowering the potential. Contrary to the description, the signal input to terminal 25 does not change from the low power supply potential (Vss). Therefore, the signal output from the terminal 26 of the pulse output circuit remains at the low power supply potential (Vss). There is even one.

[0053] In a period t3, a low power supply potential (Vss) is input to the terminal 21 of the pulse output circuit. As described above, during the period t3, the signal output from the terminal 28 of the pulse output circuit is the signal input to terminal 22, and the signal output from terminal 26 is the signal input to terminal 25. During the period t3, a high voltage is applied to the terminal 22 of the pulse output circuit. A power supply potential (Vdd) is input to terminal 21, and a low power supply potential (Vss) is input to terminal 25. Therefore, during the period t3, the pulse output circuit supplies a high voltage to the terminal 21 of the subsequent pulse output circuit. A power supply potential (Vdd) is output to the scan line electrically connected to the terminal 26, and a low power supply potential (Vss ) to output.

[0054] During a period t4, a high power supply potential (Vdd) is applied to the terminals 24 and 27 of the pulse output circuit. As described above, during the period t4, the pulse is output from the terminal 28 of the pulse output circuit. The signal input to the terminal 25 and the signal output from the terminal 26 are at the low power supply potential (Vss). Therefore, during the period t4, the pulse output circuit is connected to the terminal 21 of the subsequent pulse output circuit, A low power supply potential (Vss) is output to the scan line electrically connected to the terminal 26 .

[0055] After the period t5, a high power supply potential (Vdd) is input to the terminal 21 of the pulse output circuit. Until the power supply voltage Vss is applied to the node A, the node B remains at the high level. Therefore, during this period, the pulse output circuit maintains the pulse output A low power supply potential (Vss) is output to the scanning lines electrically connected to the terminals 21 and 26. do.

[0056] (Regarding a pulse output circuit and a scanning line driving circuit having the pulse output circuit) In the above-described pulse output circuit, the period t2 and the period At t3, a selection signal (high power supply potential (Vdd)) is output to the scan line or not. Specifically, the pulse output circuit is configured such that a signal input to the terminal 25 is a first scanning line driving circuit. If it is a clock signal for the circuit, the selection signal is output and the fixed potential (low power supply potential (Vss)) In this case, the pulse output circuit outputs a non-selection signal. It also has the function of shifting the selection signal to the subsequent pulse output circuit regardless of the operation. In other words, a shift register can be configured by using a plurality of such pulse output circuits. do.

[0057] In the display device disclosed in this specification, the scanning line driving circuit has the shift register. Therefore, the display device can control the supply of the selection signal for each scanning line. That is, the display device disclosed in this specification rewrites an image only in an arbitrary area. It is a display device capable of doing so.

[0058] In addition, the display device disclosed in this specification performs the above operation by controlling a first scanning line driving circuit clock. Wiring that supplies a signal indicating a clock signal (GCK1) or a fixed potential (low power supply potential (Vss)) -Fourth scanning line driving circuit clock signal (GCK4) or fixed potential (low power supply potential (Vss This can be achieved by providing wiring that supplies a signal indicating Therefore, the display device disclosed in this specification is a display device capable of partial driving, but does not require wiring. This is a display device in which the configuration of the circuits including the display device can be simplified.

[0059] In addition, whether the clock signal or the fixed potential is supplied to the wiring is determined by the controller 1. The specific configuration of the controller 13 and the wiring are as follows: An example of a method for selecting a signal to be output will be described.

[0060] (Example of controller 13 configuration) FIG. 4 shows a control system having three modes: a normal mode, a partial drive mode, and a standby mode. FIG. 1 is a diagram showing an example of the configuration of the roller 13. Note that the normal mode is the first scanning line driving mode described above. Partial clock signal for the circuit (PGCK1) to partial clock signal for the fourth scanning line driving circuit (P Regardless of the period, the first scanning line driving circuit clock signal (GCK1) to the fourth This is the mode in which the signal is the same as the clock signal (GCK4) for the scanning line driving circuit. The partial driving mode is the above-mentioned first scanning line driving circuit partial clock signal (PGCK1) to The fourth scanning line driving circuit partial clock signal (PGCK4) is a clock signal for the first scanning line driving circuit. The same signal as the clock signal (GCK1) to the fourth scanning line driving circuit clock signal (GCK4) The standby mode is a mode in which the scanning line driving circuit 11 and the signal This is a mode in which a clock signal or the like is not supplied to the signal line driver circuit 12. The controller 13 includes a signal generating circuit 131, a memory circuit 132, a comparison circuit 133, and a selection circuit. circuit 134 and a display control circuit 135.

[0061] The signal generating circuit 131 operates the scanning line driving circuit 11 and the signal line driving circuit 12 to generate a pixel Specifically, the pixel section 10 is a circuit that generates a signal for forming an image on the pixel section 10. Image signals (Data) input to multiple pixels arranged in a trix shape, scanning line drive A signal (for example, a start signal (SP ), clock signal (CK), and high power supply potential (Vdd) and low power supply potential (Vdd) This is a circuit that generates and outputs the power supply potential (Vss) and other voltages. In the example shown in FIG. 3, a signal generating circuit 131 outputs an image signal (Data) to a memory circuit 132. The display control circuit 135 is then provided with a control signal for controlling the operation of the scanning line driving circuit 11 or the signal line driving circuit 12. The signal generating circuit 131 outputs a signal to the memory circuit 132 to control the If the image signal (Data) is an analog signal, it is converted via an A / D converter, etc. The image signal (Data) can then be converted into a digital signal.

[0062] The memory circuit 132 stores image signals for forming a first image to a second image in the pixel portion 10. A plurality of memories 13 for storing image signals for forming n images (n being a natural number). The memory 136 is a dynamic random access memory (DRAM). ess Memory), SRAM (Static Random Access Me The memory 136 may be configured using a memory element such as a memory cell. The number of memories 136 may be any number as long as the memory 136 is configured to store an image signal for each image formed in the memory 136. In addition, the image signals stored in the plurality of memories 136 are compared. The signal is selectively read out by a path 133 and a selection circuit 134.

[0063] The comparison circuit 133 compares the kth image (k is an arbitrary value between 1 and n) stored in the memory circuit 132 with the kth image (k is an arbitrary value between 1 and n). Selectively select an image signal for forming an image k+1) and an image signal for forming an image k+2. The kth image signal is read out from the kth pixel, compared, and the difference is detected. The image and the (k+1)th image are images that are successively displayed in the pixel section 10. The difference is detected by comparing the image signals at 133. Depending on the difference, the controller 1 It is determined whether the mode of 3 is a normal mode, a partial drive mode, or a standby mode. do.

[0064] The selection circuit 134 selects an image signal to the pixel unit 10 based on the difference detected by the comparison circuit 133. Specifically, the selection circuit 134 is a circuit that selects the output of the comparison circuit 133. If the mode is determined to be the partial drive mode, one frame of image signal is output. When the camera is in standby mode, the image signal is selectively output, and when the camera is in standby mode, the image signal is not output. It is a simple circuit.

[0065] The display control circuit 135 receives a start signal (SP), a clock signal (CK), a high power supply potential ( A scanning line driver 11 and a signal line driver 22 for control signals such as a low power supply potential (Vdd) and a low power supply potential (Vss) are connected to the scanning line driver 11 and the signal line driver 23. This is a circuit that controls the supply to the operation circuit 12.

[0066] Specifically, when the comparison circuit 133 judges that the normal mode is selected, the selection circuit 134 The image signal (Data) supplied from the scanning line 13 is output to the signal line driving circuit 12. The driver circuit 11 and the signal line driver circuit 12 are supplied with control signals (start signal (SP), (CK), high power supply potential (Vdd), and low power supply potential (Vss) At this time, the first partial clock for the scanning line driving circuit supplied to the scanning line driving circuit 11 is The partial clock signal (PGCK1) to the partial clock signal (PGCK4) for the fourth scanning line driving circuit are The first scanning line driving circuit clock signal (GCK1) to the fourth scanning line driving clock signal (G This signal is the same as CK4.

[0067] In addition, when the comparison circuit 133 judges that the partial drive mode is selected, the selection circuit 134 The image signal (Data) supplied from the image sensor 11 is selectively output to the signal line driving circuit 12, A control signal (start signal (SP)) is sent to the scanning line driving circuit 11 and the signal line driving circuit 12. , clock signal (CK), high power supply potential (Vdd), and low power supply potential (Vss) At this time, the first scanning line driving circuit portion supplied to the scanning line driving circuit 11 is Clock signal (PGCK1) to partial clock signal for the fourth scanning line driving circuit (PGCK4) The first scanning line driving circuit clock is generated in response to the image signal (Data) that is selectively output. The same signal as the clock signal (GCK1) to the clock signal (GCK4) for the fourth scanning line driving circuit or becomes a signal that selectively indicates a fixed potential.

[0068] When the comparator circuit 133 judges that the standby mode is selected, the selection circuit 134 selects the image When the image signal (Data) is not supplied, the scanning line driving circuit 11 and the signal line driving circuit 1 2, control signals (start pulse signal (SP), clock signal (CK), high power supply voltage In other words, the comparator circuit 13 does not supply the low power supply potential (Vdd, Vss, etc.). When the standby mode is determined by the scanning line driving circuit 11 and the signal line driving circuit 12, completely stop the operation of

[0069] However, if the period determined to be the standby mode is short, the high power supply potential (Vdd) and the low power supply potential It is also possible to configure the device so that the power supply potential (Vss) is continuously supplied. And the low power supply potential (Vss) is supplied to the wiring when the potential of the wiring is higher than the high power supply potential (Vdd) or The potential of the power supply is fixed to the low power supply potential (Vss). The line will change to a high power supply potential (Vdd) or a low power supply potential (Vss). Since changes in the power supply potential (Vdd) and the power supply potential (Vss) are accompanied by power consumption, The interruption and re-supply of power may result in increased power consumption. In such a case, a configuration in which the high power supply potential (Vdd) and the low power supply potential (Vss) are continuously supplied is used. In the above description, "not supplying" a signal means that the A potential different from a predetermined potential is supplied to a wiring that supplies a signal, or a potential is applied to the wiring. This refers to a state in which a node that is electrically connected is in a floating state.

[0070] In addition, the standby mode may be prolonged, or the driving may be limited to a specific area in the partial drive mode. If the scanning lines are in a non-selected state for a long period of time, the liquid crystal element 19 is directly exposed to the scanning lines for a long period of time. This may cause the device to burn out. Therefore, the polarity of the voltage applied to the liquid crystal element for each predetermined frame or each predetermined period is It is preferable to reverse the gender.

[0071] In the controller 13, the scanning line driving circuit 11 and the signal line driving circuit 1 By controlling the operation of 2, it is possible to reduce the power consumption of the display device.

[0072] (An example of the transistor 17 provided in the pixel 16) The transistor 17 provided in the pixel 16 of the display device described above is in an off state for a long period of time. Therefore, the transistor 17 has excellent off characteristics (off A transistor having a low leakage current is preferable. In the following, a transistor having a low leakage current is preferable as the transistor 17. An example of a transistor will be described with reference to FIG. The transistor includes an oxide semiconductor layer having a high purity. By optimizing the gate insulating film, it is possible to reduce the off-state current to an extremely low level (described in detail below). Therefore, there is a possibility that an image signal may not be input to a particular pixel for a long period of time. The transistor 17 provided in the pixel 16 of the display device to be used is preferably a Moreover, the above-mentioned pulse output circuit can be configured using the transistor. That is, the transistors can be used as the transistors 31 to 41. In this case, the number of manufacturing processes can be reduced, leading to reduced costs and improved yields.

[0073] The transistor 211 shown in FIG. 5 has a gate electrode provided on a substrate 220 having an insulating surface. a gate insulating layer 222 provided on the gate layer 221; a source layer provided on the oxide semiconductor layer 223; 5, the transistor 21 has a gate electrode 224a and a drain layer 224b. an insulating layer 225 covering the oxide semiconductor layer 223 and in contact with the oxide semiconductor layer 223; A protective insulating layer 226 is shown.

[0074] As described above, the transistor 211 illustrated in FIG. 5 includes the oxide semiconductor layer 223 as a semiconductor layer. The oxide semiconductor used for the oxide semiconductor layer 223 is a quaternary metal oxide. In-Sn-Ga-Zn-O system, which is a ternary metal oxide, In-Ga-Zn-O system, In-Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-G a-Zn-O system, Sn-Al-Zn-O system, binary metal oxide In-Zn-O system, Sn-Zn-O series, Al-Zn-O series, Zn-Mg-O series, Sn-Mg-O series, In-M The material is made of In-O, Sn-O, Zn-O, or other single-element metal oxides. In addition, the oxide semiconductor may include SiO 2 Here, for example, An In-Ga-Zn-O-based oxide semiconductor is an oxide containing at least In, Ga, and Zn. There is no particular limitation on the composition ratio. In addition, elements other than In, Ga, and Zn may be included. stomach.

[0075] The oxide semiconductor layer 223 is formed of a compound represented by the chemical formula InMO 3 (ZnO) m (m>0) A thin film having a thickness of 100 nm or less can be used. Here, M is selected from Ga, Al, Mn, and Co. It represents one or more metal elements. For example, M is Ga, Ga and Al, Ga and Mn, Alternatively, Ga and Co can be selected.

[0076] In addition, when using an In-Zn-O-based material as an oxide semiconductor, the target used The composition ratio is In:Zn=50:1 to 1:2 in atomic ratio (In in mole ratio). 2 O 3 ZnO=25:1 to 1:4), preferably In:Zn=20:1 to 1:1 (molar ratio Converted to In 2 O 3 In:ZnO=10:1 to 1:2), more preferably In:Zn= 15:1 to 1.5:1 (converted to molar ratio: In 2 O 3 :ZnO=15:2~3:4) For example, the target used for forming an In-Zn-O-based oxide semiconductor has an atomic ratio of When In:Zn:O=X:Y:Z, Z>1.5X+Y.

[0077] In order to suppress fluctuations in electrical characteristics, the oxide semiconductor described above is designed to be free of hydrogen and moisture, which are factors that cause fluctuations. By intentionally eliminating impurities such as hydroxyl groups or hydrides (also called hydrogen compounds), It is an oxide semiconductor that has been purified and made electrically i-type (intrinsic).

[0078] Therefore, the less hydrogen there is in the oxide semiconductor, the better. There are very few carriers (close to zero) originating from hydrogen or oxygen vacancies in the semiconductor layer. The carrier density is 1×10 12 / cm 3 Less than 1 x 10 11 / cm 3 is less than That is, the carrier density due to hydrogen or oxygen vacancies in the oxide semiconductor layer is reduced to almost zero. Since the number of carriers derived from hydrogen, oxygen vacancies, and the like in the oxide semiconductor layer is extremely small, It is possible to reduce the leakage current (off-state current) when the transistor is in the off state. In addition, the low impurity levels due to hydrogen and oxygen vacancies make it highly resistant to light irradiation, temperature changes, and The change and deterioration of electrical characteristics due to the application of a bias can be reduced. The smaller the value, the more preferable. The current value per 1 μm of channel width (w) is preferably 100 zA (zeptoamperes) or less. Preferably, it is 10 zA or less, and more preferably, it is 1 zA or less. There is no hot carrier degradation, so the electrical characteristics of the transistor are not affected by these factors. .

[0079] In this way, the hydrogen contained in the oxide semiconductor layer is thoroughly removed, resulting in a highly purified oxide semiconductor layer. A transistor that uses an oxide semiconductor for a channel formation region has an extremely low off-state current. That is, when the transistor is off, the oxide semiconductor layer acts as an insulator. On the other hand, the oxide semiconductor layer can be regarded as a conductor for transistors. In the on-state, it is expected to have a higher current supply capacity than a semiconductor layer made of amorphous silicon. It is possible to do so.

[0080] The substrate 220 having an insulating surface may be, for example, barium borosilicate glass or aluminophore. A glass substrate such as silicic glass can be used.

[0081] In the transistor 211, an insulating film serving as a base film is provided between the substrate 220 and the gate layer 221. The undercoat film has a function of preventing the diffusion of impurity elements from the substrate, and is preferably a nitride film. A silicon film, a silicon oxide film, a silicon nitride oxide film, or a silicon oxynitride film is selected from the group consisting of a silicon film, a silicon oxide film, a silicon nitride film, and a silicon oxide film. The insulating film can be formed by a laminate structure of one or more films.

[0082] The material of the gate layer 221 is molybdenum, titanium, chromium, tantalum, tungsten, aluminium, etc. Aluminum, copper, neodymium, scandium, and other metal materials, or alloys containing these as the main components The material can be formed in a single layer or in a laminate.

[0083] The gate insulating layer 222 is formed by depositing silicon oxide using a plasma CVD method or a sputtering method. Con layer, silicon nitride layer, silicon oxynitride layer, silicon oxynitride layer, aluminum oxide layer layer, an aluminum nitride layer, an aluminum oxynitride layer, an aluminum oxynitride layer, or an oxide The hafnium layer can be formed as a single layer or a laminate. For example, the first gate insulating layer A silicon nitride layer (Si) with a thickness of 50 nm to 200 nm was formed by plasma CVD. N y (y>0) is formed on the first gate insulating layer as a second gate insulating layer having a thickness of 5n. A silicon oxide layer (SiO x (x>0) can be stacked .

[0084] The conductive film used for the source layer 224a and the drain layer 224b is, for example, Al, Cr , Cu, Ta, Ti, Mo, W, or an alloy containing the above elements Alternatively, an alloy film of the above elements can be used. A high melting point metal layer such as Ti, Mo, W, etc. is laminated on either or both of the upper and lower sides of the metal layer. In addition, in order to prevent the occurrence of hillocks and whiskers in the Al film, By using aluminum material with added elements (Si, Nd, Sc, etc.), heat resistance is improved. It becomes possible to do so.

[0085] In addition, the source layer 224a and the drain layer 224b (wiring layers formed from the same layers as these) The conductive film (including the conductive metal oxide) may be formed of a conductive metal oxide. As for indium oxide (In 2 O 3 ), tin oxide (SnO 2 ), zinc oxide (ZnO), Indium oxide tin oxide alloy (In 2 O 3 - SnO 2 (abbreviated as ITO), indium oxide In zinc oxide alloy (In 2 O 3 -ZnO) or silicon oxide on these metal oxide materials can be used.

[0086] The insulating layer 225 is typically a silicon oxide film, a silicon oxynitride film, or an aluminum oxide film. An inorganic insulating film such as an aluminum oxynitride film or an aluminum oxide nitride film can be used.

[0087] The protective insulating layer 226 is a silicon nitride film, an aluminum nitride film, a silicon oxynitride film, a nitride film, a silicon ... An inorganic insulating film such as an aluminum oxide film can be used.

[0088] In addition, a planarizing insulating layer is formed on the protective insulating layer 226 to reduce surface irregularities caused by the transistor. The planarization insulating film may be formed using a material such as polyimide, acrylic, or benzocyclobutene. In addition to the above organic materials, low dielectric constant materials (low In addition, multiple insulating films made of these materials can be stacked. A planarizing insulating film may be formed by performing the above-mentioned process.

[0089] <Off-state current of transistor> Next, the off-state current of a transistor including a highly purified oxide semiconductor layer was measured. The results will be explained.

[0090] First, the off-state current of a transistor including a highly purified oxide semiconductor layer is sufficiently small. Considering the fact that the channel width W is large enough, 1 m, a transistor is prepared and the off-current The off-current of a transistor with a channel width W of 1 m was measured. In FIG. 6, the horizontal axis represents the gate voltage VG, and the vertical axis represents the drain current ID. When the voltage VD is +1V or +10V, the gate voltage VG is in the range of -5V to -20V. The off-current of the transistor is 1×10, which is the detection limit.-12 It is clear that it is below A. In addition, the off-state current of the transistor (here, the value per 1 μm of channel width) was 1 A. A / μm(1×10 -18 It was found that the maximum capacitance was less than 1.5 A / μm.

[0091] Next, the off-state current of a transistor including a highly purified oxide semiconductor layer is measured more accurately. As described above, the results obtained by the present invention will be described. The off-state current of the transistor is 1×10 -12 A or below Therefore, we fabricated a device for evaluating the characteristics and obtained a more accurate value of the off-state current ( The results of the determination of the concentration of 100 ppm or less (values ​​below the detection limit of the measuring instrument) are explained below.

[0092] First, the characteristic evaluation element used in the current measurement method will be described with reference to FIG.

[0093] The characteristic evaluation element shown in FIG. 7 has three measurement systems 800 connected in parallel. 0 is a capacitor element 802, a transistor 804, a transistor 805, and a transistor 806 The transistor 804 and the transistor 808 include a high-purity In the present embodiment, a transistor including a gate insulating film was used.

[0094] In the measurement system 800, one of the source and drain of a transistor 804 and a capacitance element One terminal of 802 and one of the source and drain of the transistor 805 are connected to a power supply (V In addition, the source and drain of the transistor 804 are connected to On the other hand, one of the source and drain of the transistor 808 and the other terminal of the capacitor 802 and the gate of the transistor 805 are electrically connected to each other. The other of the source and drain of transistor 808 and one of the source and drain of transistor 806 The gate of the transistor 806 is electrically connected to a power supply (the power supply that provides V1). In addition, the other of the source and drain of the transistor 805 and the source of the transistor 806 The other of the source and drain is electrically connected to an output terminal.

[0095] The gate of the transistor 804 is connected to a resistor R1, R2, and R3. A potential Vext_b2 is supplied to the gate of the transistor 808 to control the A potential Vext_b1 is supplied to control the ON and OFF states of the switch 808. The potential Vout is output from the output terminal.

[0096] Next, a current measuring method using the above-mentioned characteristic evaluation element will be described.

[0097] First, an outline of the initial period during which a potential difference is applied to measure the off-state current will be described. In the initial period, the gate of the transistor 808 is connected to the transistor 808 to turn the transistor 808 on. A potential Vext_b1 is input to the other of the source and drain of the transistor 804. A node that is electrically connected (i.e., one of the source and drain of the transistor 808, The other terminal of the capacitor 802 and the gate of the transistor 805 are electrically connected to A potential V1 is applied to a node A, which is a power supply (power supply voltage V1). Here, the potential V1 is, for example, a high potential. Moreover, the transistor 804 is kept in an off state.

[0098] Thereafter, a potential V ext_b1 is input to turn off the transistor 808. After the transistor 804 is turned off, the potential V1 is set to a low potential. The potential V2 is set to the same potential as the potential V1. When the initial period is over, the node A and the source and drain of the transistor 804 A potential difference is generated between node A and the source and drain of transistor 808. Since a potential difference occurs between the drain and the other drain, the transistor 804 and the transistor A small amount of charge flows through the transistor 808. In other words, an off-current occurs.

[0099] Next, an outline of the measurement period of the off-state current will be described. The potential (V2) of one of the source and drain of the transistor 804 and the potential (V3) of the source of the transistor 808 are connected to the The other potential (V1) of the source and drain is fixed at a low potential. The potential of the node A is not fixed (floating state). Charge flows through transistor 804 and transistor 808 and is held at node A over time. The charge stored at node A fluctuates. In other words, the output potential Vout of the output terminal also fluctuates.

[0100] Details of the relationship between the potentials during the initial period in which the potential difference is applied and the subsequent measurement period The details (timing chart) are shown in Figure 8.

[0101] In the initial period, first, the potential Vext_b2 is set to the ON state by the transistor 804. This makes the potential of node A V2, that is, the low potential ( Note that it is not essential to apply a low potential (VSS) to node A. The potential Vext_b2 is set to a potential (low potential) at which the transistor 804 is turned off. Then, the transistor 804 is turned off. The potential (high potential) is set so that the transistor 808 is turned on. The potential of A becomes V1, that is, the high potential (VDD). Then, Vext_b1 is This sets the node A to a floating potential so that the resistor 808 is turned off. The initial period ends when the switching state is reached.

[0102] In the subsequent measurement period, electric charges flow into node A at potentials V1 and V2. Or, the potential is set so that charge flows out from node A. Here, potential V1 and potential V2 is the low potential (VSS). However, at the timing when the output potential Vout is measured, In order to operate the output circuit, V1 must be temporarily set to a high potential (VDD). Note that the period when V1 is at a high potential (VDD) is short enough that it does not affect the measurement. Between.

[0103] When a potential difference is applied as described above and the measurement period is started, the voltage at node A The amount of charge held by the transistor fluctuates, and the potential at node A fluctuates accordingly. This means that the potential of the gate of the resistor 805 fluctuates over time. The potential of the output potential Vout of the transistor also changes.

[0104] A method for calculating the off-state current from the obtained output potential Vout will be described below.

[0105] Before calculating the off-state current, the relationship between the potential VA of node A and the output potential Vout is calculated. This makes it possible to obtain the potential VA of the node A from the output potential Vout. From the above relationship, the potential VA of node A is expressed as a function of the output potential Vout as follows: It is possible.

[0106]

number

[0107] The charge QA at node A is determined by the potential VA at node A, the capacitance CA connected to node A, Using a constant (const), it is expressed as follows: The quantity CA is the capacitance of the capacitive element 802 plus the other capacitances.

[0108]

number

[0109] The current IA at node A is the charge flowing into (or out of) node A. Since this is the time derivative of , the current IA at node A is expressed as follows:

[0110]

number

[0111] In this way, the capacitance CA connected to node A and the output potential Vout of the output terminal are The current IA of node A can be calculated.

[0112] By using the method described above, the current that flows between the source and drain of the transistor in the off state The leakage current (off current) can be measured.

[0113] Here, a highly purified oxide film with a channel length L=10 μm and a channel width W=50 μm is used. A transistor 804 having a highly purified oxide semiconductor layer In each of the parallel measurement systems 800, a capacitance element 80 The capacitance values ​​of each of the elements 2 were set to 100fF, 1pF, and 3pF.

[0114] In the above measurements, VDD = 5 V and VSS = 0 V. In principle, the potential V1 is set to VSS, and a 100 msec. Vout was measured as VDD for a certain period. The time Δt was set to approximately 30,000 sec.

[0115] FIG. 9 shows the relationship between the elapsed time Time in the current measurement and the output potential Vout. From FIG. 9, it can be seen that the potential changes over time.

[0116] FIG. 10 shows the off-state current at room temperature (25° C.) calculated from the above current measurement. 10 shows the source-drain voltage of the transistor 804 or the transistor 808. 10 shows the relationship between V and the off-current I. Under these conditions, the off-current was found to be about 40zA / μm. It was found that the off-state current was 10zA / μm or less under the condition of a drain voltage of 3.1V. In addition, 1zA is 10 -21 Represents A.

[0117] Furthermore, the off-state current calculated from the above current measurement in a temperature environment of 85°C FIG. 11 shows the transistor 804 or the transistor 1 shows the relationship between the source-drain voltage V and the off-current I of the transistor 808. From 1, when the source-drain voltage is 3.1 V, the off-current is 100 zA / μm It was found that the following was true.

[0118] As described above, in a transistor including a highly purified oxide semiconductor layer, the off-state current It was confirmed that it was small enough.

[0119] (Modifications of the display device) The display device having the above-described structure is one embodiment of the present invention, and the following points are different from the display device: The present invention also includes a display device having the same.

[0120] <Modification of the pulse output circuit> For example, the pulse output circuit shown in FIG. 3A may be configured to include a source and drain. One of the source and drain is electrically connected to a high power supply potential line, and the other of the source and drain is a transistor. The gate of transistor 32, the gate of transistor 34, and the source and drain of transistor 35. the other of the source and drain of transistor 36, the source and drain of transistor 38 The drain of the transistor 41 is electrically connected to one of the drains of the transistor 41 and the gate of the transistor 41 is reset. A transistor 50 electrically connected to the Reset terminal is added (FIG. 12( A) can be applied to the reset terminal. A high-level potential is input during the period, and a low-level potential is input during the other periods. That is, the transistor 50 is a transistor that is turned on during the vertical blanking period. This allows the potential of each node to be initialized during the vertical blanking period. Therefore, it is possible to prevent malfunction.

[0121] In addition, as a pulse output circuit, a transistor is used in the pulse output circuit shown in FIG. It is also possible to apply a configuration in which 36 is removed (see FIG. 12(B)). Therefore, the number of transistors constituting the pulse output circuit can be reduced. This makes it possible to reduce the layout area of ​​the output circuit and improve the yield.

[0122] In addition, as a pulse output circuit, a transistor is used in the pulse output circuit shown in FIG. It is also possible to apply a configuration in which 39 is removed (see FIG. 13(A)). Therefore, the number of transistors constituting the pulse output circuit can be reduced. This makes it possible to reduce the layout area of ​​the output circuit and improve the yield.

[0123] In addition, as a pulse output circuit, the pulse output circuit shown in FIG. One of the inputs is connected to the gate of transistor 33 and the source and drain of transistor 39. The other of the source and drain is electrically connected to the gate of the transistor 40. A transistor 51 is added, the gate of which is electrically connected to the high power supply potential line. The transistor 51 may have the structure shown in FIG. During periods t2 and t3 shown in FIG. 3(B) and (C), the transistor is in the off state. By adding the gate of the transistor 33, the gate of the transistor 33 is turned on during the periods t2 and t3. This makes it possible to cut off the electrical connection between the gate of the transistor 40 and the gate of the transistor 40. The pulse output circuit is provided with a transistor 51 (see FIG. 13B). The advantages of the former configuration will be described in detail below in comparison with the latter configuration (see FIG. 3(A)).

[0124] First, a case where the transistor 51 is not provided will be described. If the signal repeats high power supply potential (Vdd) and low power supply potential (Vss), the period t2, t3 In this case, the output signal at the terminal 28 and the output signal at the terminal 26 are both at the high power supply potential (Vdd). At this time, the potential of the gates of the transistors 33 and 40 (potential of node A) is Capacitive coupling between the source and gate of transistor 33 and capacitive coupling between the source and gate of transistor 40 On the other hand, the signal input to the terminal 25 becomes higher than the high power supply potential (Vdd). When the potential of the power supply is fixed to the low potential (Vss), the output of the terminal 28 during the periods t2 and t3 The signal is at the high power supply potential (Vdd), and the output signal at terminal 26 is at the low power supply potential (Vss). At this time, the potential of the gates of the transistors 33 and 40 (potential of node A) is A potential higher than the high power supply potential (Vdd) is generated only by the capacitive coupling between the source and gate of the transistor 33. In addition, the transistor 40 drives the scan line, so the transistor 36. The gate of the transistor 40 becomes a large load when the potential is increased by the capacitive coupling. Therefore, in order to operate the pulse output circuit, the channel length of the transistor 33 must be Therefore, it is necessary to increase the channel width (W / L) that is used.

[0125] In contrast, when the transistor 51 is provided, the transistor The electrical connection between the gate of the transistor 33 and the gate of the transistor 40 is thus cut off. Only the potential of the gate of the transistor 33 can be increased by capacitive coupling. Therefore, the load on the capacitive coupling can be reduced. In addition, the channel length of the transistor 36 is reduced. Since there is no need to increase the width (W / L), the layout area can be reduced. .

[0126] In FIG. 13B, the gate of the transistor 51 is electrically connected to the high power supply potential line. The gate is electrically connected to the block terminal (Block). 14(A)) or electrically connected to terminal 25 (see FIG. 14(B)). It is possible to use the block terminal (Block) as a terminal 25. Clock signal for the first scanning line driving circuit (GCK1) to clock signal for the fourth scanning line driving circuit When a signal identical to any of (GCK4) is input, a high-level potential is input, When a fixed potential (low power supply potential (Vss)) is input, if a low-level potential is input That is, the transistor 51 receives a clock signal for the first scanning line driving circuit at the terminal 25. The clock signal (GCK1) to the fourth scanning line driving circuit clock signal (GCK4) are the same as When a signal is input, it is turned on and a fixed potential (low power supply potential (Vss)) is input. This allows the gate of transistor 33 and the transistor This allows the timing at which the electrical connection of the gate of the transistor 40 is cut off to be made earlier. In addition, in the case where the gate of the transistor 51 is electrically connected to the terminal 25 (see FIG. 14B), The advantage of this method is that it does not require the addition of any new signals.

[0127] <Modifications of Transistor> In the display device described above, the transistor 17 provided in the pixel 16 is A configuration in which a transistor 211 with a bottom gate structure called a channel etch type is applied (see Fig. 5) is shown, the transistor 17 is not limited to this configuration. It is possible to apply the transistors shown in 5(A) to (C).

[0128] A transistor 510 shown in FIG. 15A is a channel protection type (also called a channel stop type). This is one of the bottom gate structures known as bottom gate structures.

[0129] The transistor 510 includes a gate layer 221, a gate insulator 222, and a gate insulating layer 223 on a substrate 220 having an insulating surface. A dielectric layer 222, an oxide semiconductor layer 223, and a choke covering a channel formation region of the oxide semiconductor layer 223. The insulating layer 511, which functions as a channel protection layer, the source layer 224a, and the drain layer 224b are The source layer 224a, the drain layer 224b, and the insulating layer 511 are covered and protected. An insulating layer 226 is formed.

[0130] The transistor 520 shown in FIG. 15B is a bottom-gate transistor. A gate layer 221, a gate insulating layer 222, a source The source layer 224a, the drain layer 224b, and the oxide semiconductor layer 223. An insulating layer 225 is provided to cover the gate electrode 224a and the drain layer 224b and to be in contact with the oxide semiconductor layer 223. A protective insulating layer 226 is further formed on the insulating layer 225.

[0131] In the transistor 520, the gate insulating layer 222 is formed by the substrate 220 and the gate layer 221. A source layer 224a and a drain layer 224b are provided on the gate insulating layer 222. The gate insulating layer 222, the source layer 224a, and the drain The oxide semiconductor layer 223 is provided over the layer 224b.

[0132] The transistor 530 shown in FIG. 15C is one of the top-gate transistors. The transistor 530 is formed on the substrate 220 having an insulating surface, with an insulating layer 531, an oxide A semiconductor layer 223, a source layer 224a, a drain layer 224b, a gate insulating layer 222, a gate The source layer 224a and the drain layer 224b are connected to the wiring layers 532a and 532b. The wiring layer 532b is provided adjacent to and electrically connected to the first and second electrodes 532a and 532b.

[0133] The insulating layers 511 and 531 are typically made of a silicon oxide film, a silicon oxynitride film, or an oxide An inorganic insulating film such as an aluminum nitride film or an aluminum oxynitride film can be used. The conductive film used for the wiring layer 532a and the wiring layer 532b is, for example, Al, C. An element selected from the group consisting of r, Cu, Ta, Ti, Mo, and W, or a composite material containing the above elements. The film may be made of gold or an alloy of the above elements. A high melting point metal layer such as Ti, Mo, or W is laminated on either or both of the upper and lower sides of each metal layer. In addition, in order to prevent the occurrence of hillocks and whiskers in the Al film, Heat resistance is improved by using Al material with added elements (Si, Nd, Sc, etc.). It is possible to do so.

[0134] (Regarding various electronic devices equipped with display devices) An example of an electronic device incorporating the display device disclosed in this specification will be described below with reference to FIG. This will be explained in light of the above.

[0135] FIG. 16A shows a notebook personal computer. It is composed of a housing 2202, a display unit 2203, a keyboard 2204, and the like.

[0136] FIG. 16B is a diagram showing a personal digital assistant (PDA), and the main body 2211 has a display unit 2 213, an external interface 2215, and an operation button 2214. There is also a stylus 2212 as an accessory for operation.

[0137] FIG. 16C is a diagram showing an electronic book 2220 as an example of electronic paper. The book 2220 is composed of two cases, a case 2221 and a case 2223. Case 2221 and the housing 2223 are integrated by a shaft portion 2237. With this configuration, the electronic book 2220 can be opened and closed with the opening and closing action being performed around the axis. It can be used like a paper book.

[0138] A display unit 2225 is incorporated in the housing 2221, and a display unit 2227 is incorporated in the housing 2223. The display unit 2225 and the display unit 2227 are configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a text is displayed on the right display unit (display unit 2225 in FIG. 16C) and An image can be displayed on the display portion (the display portion 2227 in FIG. 16C).

[0139] FIG. 16C shows an example in which an operating unit and the like are provided in the housing 2221. For example, The housing 2221 includes a power source 2231, operation keys 2233, a speaker 2235, etc. The operation keys 2233 can be used to turn pages. The device may be configured to include a keyboard, a pointing device, etc. On the side of the device, there are external connection terminals (earphone terminal, USB terminal, or AC adapter and US A terminal that can be connected to various cables such as B cable, etc., and a recording medium insertion section, etc. Furthermore, the electronic book 2220 may be configured to have a function as an electronic dictionary. You may do so.

[0140] The electronic book 2220 may be configured to transmit and receive information wirelessly. The desired book data can be purchased and downloaded from the electronic book server. It is also possible.

[0141] Electronic paper can be applied to any field as long as it displays information. For example, in addition to e-books, posters, in-car advertisements on trains and other vehicles, credit cards, etc. The present invention can be applied to displays on various cards such as credit cards.

[0142] FIG. 16D is a diagram showing a mobile phone. The mobile phone includes a housing 2240 and The housing 2241 is made up of two housings, a display panel 2242 and a screen. Speaker 2243, microphone 2244, pointing device 2246, camera The housing 2240 is provided with a lens 2247 for receiving the image, an external connection terminal 2248, and the like. The mobile phone is equipped with a solar cell 2249 for charging the mobile phone, an external memory slot 2250, etc. In addition, the antenna is built into the housing 2241.

[0143] The display panel 2242 has a touch panel function, and an image is displayed on the display panel 2242 as shown in FIG. The multiple operation keys 2245 are shown by dotted lines. A boost circuit is implemented to boost the voltage output from module 2249 to the voltage required for each circuit. In addition to the above configuration, a non-contact IC chip, a small recording device, etc. are also included. It can also be written as:

[0144] The display direction of the display panel 2242 changes appropriately depending on the usage mode. Since it has a camera lens 2247 on the same surface as the lens 2242, video calls are possible. The speaker 2243 and the microphone 2244 are not limited to voice calls, The housing 2240 and the housing 2241 can be slid together. As shown in Figure 16(D), the device can be folded from the unfolded state to the folded state, making it easy to carry. Suitable miniaturization is possible.

[0145] The external connection terminal 2248 can be connected to various cables such as AC adapters and USB cables. The external memory slot 2250 can store data and other information. By inserting a recording medium, it is possible to store and transfer a larger amount of data. In addition, it may be equipped with an infrared communication function, a television receiving function, etc.

[0146] FIG. 16E is a diagram showing a digital camera. The digital camera has a main body 226. 1, display unit (A) 2267, eyepiece unit 2263, operation switch 2264, display unit (B) 22 It is composed of 65, battery 2266, etc.

[0147] FIG. 16(F) is a diagram showing a television device. In the television device 2270, A display unit 2273 is built into the housing 2271. The display unit 2273 displays images. In this case, the housing 2271 is supported by a stand 2275. The configuration shown is as follows.

[0148] The television device 2270 can be operated using an operation switch provided on the housing 2271 or a separate remote. This can be done by using a remote control operation device 2280. The channel and volume can be controlled by the 2279, and the display 2273 shows In addition, the remote control unit 2280 can be used to control the video. A display unit 2277 for displaying information output from the device 2280 may be provided.

[0149] The television device 2270 is preferably configured to include a receiver, a modem, etc. The receiver can receive general television broadcasts. By connecting the device to a wired or wireless communication network, It is used to communicate information either directly (i.e., between a sender and a receiver, or between receivers themselves) or in a two-way manner (i.e., between a sender and a receiver, or between receivers themselves). It is possible to do so. [Explanation of symbols]

[0150] 10 Pixel section 11 Scanning line driving circuit 12 Signal line driver circuit 13 Controller 14 Scan Lines 15 Signal Line 16 pixels 17 Transistor 18 Capacitive element 19 Liquid crystal elements 20_1~20_m Pulse output circuit 20_x Pulse output circuit 21~28 Terminals 31~41 Transistor 50, 51 Transistors 131 Signal generation circuit 132 Memory circuit 133 Comparison circuit 134 Selection circuit 135 Display control circuit 136 Memory 211 Transistor 220 Substrate 221 Gate Layer 222 Gate Insulation Layer 223 Oxide Semiconductor Layer 224a Source Layer 224b Drain layer 225 Insulating Layer 226 Protective Insulation Layer 510 Transistor 511 Insulating layer 520 Transistor 530 Transistor 531 Insulating layer 532a wiring layer 532b wiring layer 800 Measurement System 802 Capacitive element 804 Transistor 805 Transistor 806 Transistor 808 Transistor 2201 Main unit 2202 Case 2203 Display section 2204 Keyboard 2211 Main unit 2212 Stylus 2213 Display section 2214 Operation button 2215 External Interface 2220 E-books 2221 Case 2223 Case 2225 Display section 2227 Display section 2231 Power supply 2233 Operation key 2235 Speaker 2237 Shaft 2240 Case 2241 Case 2242 Display Panel 2243 Speaker 2244 Microphone 2245 Operation Key 2246 Pointing Device 2247 Camera Lenses 2248 External connection terminal 2249 Solar Cell 2250 external memory slot 2261 Main unit 2263 Eyepiece 2264 Operation switch 2265 Display section (B) 2266 Battery 2267 Display section (A) 2270 Television Equipment 2271 Case 2273 Display section 2275 Stand 2277 Display section 2279 Operation Key 2280 Remote Controlled Device

Claims

1. A multi-stage circuit, at least one circuit of the plurality of stages of circuits includes first to tenth transistors and first to fifth wirings; the first circuit has a function of outputting a first signal to the first wiring; the first wiring is always electrically connected to the gate of the transistor of the pixel; one of the source and the drain of the first transistor is always electrically connected to the first wiring; the other of the source and the drain of the first transistor is always electrically connected to the second wiring; one of the source and the drain of the second transistor is always electrically connected to the third wiring; the other of the source and the drain of the second transistor is always electrically connected to the first wiring; one of the source and the drain of the third transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the third transistor is always electrically connected to the gate of the fourth transistor; one of the source and the drain of the fourth transistor is always electrically connected to the other of the source and the drain of the fifth transistor; the other of the source and the drain of the fourth transistor is always electrically connected to the fourth wiring; one of the source and the drain of the fifth transistor is always electrically connected to the third wiring; one of the source and the drain of the sixth transistor is always electrically connected to the gate of the fourth transistor; the other of the source and the drain of the sixth transistor is always electrically connected to the one of the source and the drain of the seventh transistor; a first power supply potential is supplied to the gate of the sixth transistor; the gate of the seventh transistor is always electrically connected to the fifth wiring; one of the source and the drain of the eighth transistor is always electrically connected to the third wiring; the other of the source and the drain of the eighth transistor is always electrically connected to the gate of the second transistor; one of the source and the drain of the ninth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the ninth transistor is always electrically connected to the one of the source and the drain of the tenth transistor, the other of the source and the drain of the tenth transistor is always electrically connected to the gate of the sixth transistor; a gate of the ninth transistor and a gate of the tenth transistor are input with mutually different signals; Semiconductor device.

2. A multi-stage circuit, at least one circuit of the plurality of stages of circuits includes first to tenth transistors and first to fifth wirings; the first circuit has a function of outputting a first signal to the first wiring; the first wiring is always electrically connected to the gate of the transistor of the pixel; one of the source and the drain of the first transistor is always electrically connected to the first wiring; the other of the source and the drain of the first transistor is always electrically connected to the second wiring; one of the source and the drain of the second transistor is always electrically connected to the third wiring; the other of the source and the drain of the second transistor is always electrically connected to the first wiring; one of the source and the drain of the third transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the third transistor is always electrically connected to the gate of the fourth transistor; one of the source and the drain of the fourth transistor is always electrically connected to the other of the source and the drain of the fifth transistor; the other of the source and the drain of the fourth transistor is always electrically connected to the fourth wiring; one of the source and the drain of the fifth transistor is always electrically connected to the third wiring; one of the source and the drain of the sixth transistor is always electrically connected to the gate of the fourth transistor; the other of the source and the drain of the sixth transistor is always electrically connected to the one of the source and the drain of the seventh transistor; a first power supply potential is supplied to the gate of the sixth transistor; the gate of the seventh transistor is always electrically connected to the fifth wiring; one of the source and the drain of the eighth transistor is always electrically connected to the third wiring; the other of the source and the drain of the eighth transistor is always electrically connected to the gate of the second transistor; one of the source and the drain of the ninth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the ninth transistor is always electrically connected to the one of the source and the drain of the tenth transistor, the other of the source and the drain of the tenth transistor is always electrically connected to the gate of the sixth transistor; a gate of the ninth transistor and a gate of the tenth transistor are input with different signals; the third wiring has a function of supplying a second power supply potential; the fourth wiring has a function of supplying a clock signal; Semiconductor device.

3. In claim 1 or claim 2, the third transistor has a function of controlling a conduction state between a gate of the first transistor and a gate of the fourth transistor; Semiconductor device.

4. In any one of claims 1 to 3, Each of the first to tenth transistors has the same polarity. Semiconductor device.

Images