Semiconductor device, manufacturing method, and apparatus

Abstract

To provide a semiconductor device having high reliability against static electricity.SOLUTION: A semiconductor device has: a semiconductor layer having a first face, an element region, and an end; a wiring layer arranged on the first face side; an insulator part arranged between the element region and the end in a plan view of the first face and penetrating the semiconductor layer; a first plug including a conductor, arranged between the first face and the wiring layer, and arranged between the element region and the insulator part in the plan view of the first face; and a second plug including a conductor, arranged between the first face and the wiring layer, and arranged between the end and the insulator part in the plan view of the first face. The first plug and the second plug are electrically connected through the wiring layer. The conductor included in the first plug is connected to a first conductivity type first semiconductor region arranged in the semiconductor layer. The first semiconductor region is arranged in a second conductivity type second semiconductor region arranged in the semiconductor layer.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to semiconductor devices, manufacturing methods, and apparatus. [Background technology]

[0002] As semiconductor devices become more highly integrated, there is a trend to further reduce the size of transistors and other semiconductor elements to further increase packaging density. For example, in recent years, stacked back-illuminated solid-state imaging devices have become widespread, in which a pixel substrate on which pixels are formed is stacked with a control substrate on which a control circuit for controlling the pixels and processing pixel signals is formed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2020-065016 A Summary of the Invention [Problem to be solved by the invention]

[0004] In Patent Document 1, in order to improve the reliability of a semiconductor device, a guard ring is formed along the outer periphery of a semiconductor chip with an isolation region in which an insulating film is embedded, and a wiring structure made up of multiple wiring layers and multiple insulators stacked together. In such a configuration, there is a possibility that the elements in the semiconductor layer and the guard ring may be destroyed by the influence of static electricity during manufacturing and use. [Means for solving the problem]

[0005] One aspect of the present disclosure is a semiconductor device comprising: a semiconductor layer having a first surface and having an element region and an end portion; a wiring layer arranged on a side of the first surface; an insulator portion arranged between the element region and the end portion in a planar view with respect to the first surface and penetrating the semiconductor layer; a first plug including a conductor and arranged between the first surface and the wiring layer and arranged between the element region and the insulator portion in a planar view with respect to the first surface; and a second plug including a conductor and arranged between the first surface and the wiring layer and arranged between the end portion and the insulator portion in a planar view with respect to the first surface, wherein the first plug and the second plug are electrically connected by the wiring layer, the conductor included in the first plug is connected to a first semiconductor region of a first conductivity type arranged in the semiconductor layer, and the first semiconductor region is arranged inside a second semiconductor region of a second conductivity type arranged in the semiconductor layer. Effect of the Invention

[0006] According to at least one embodiment of the present disclosure, a semiconductor device with improved reliability against the effects of static electricity can be provided. [Brief description of the drawings]

[0007] [Figure 1] 1 is a schematic diagram illustrating a configuration of a semiconductor device according to a first embodiment. [Diagram 2] 1 is a schematic diagram illustrating a configuration of a semiconductor device according to a first embodiment. [Diagram 3] 1 is a schematic diagram showing a moisture-resistant structure according to a first embodiment. [Figure 4] FIG. 2 is a diagram illustrating a problem associated with the first embodiment. [Diagram 5] 3 is a table showing the polarity of a semiconductor layer according to the first embodiment. [Figure 6] 1 is a schematic diagram showing a configuration of a moisture-resistant structure according to a first embodiment. [Figure 7] FIG. 4 is a schematic diagram illustrating a configuration of a semiconductor device according to a second embodiment. [Figure 8] FIG. 11 is a schematic diagram showing a configuration of a semiconductor device according to a third embodiment. [Figure 9] FIG. 13 is a schematic diagram showing a configuration of a device according to a fourth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] The embodiments described below are intended to embody the technical ideas of the present disclosure, and are not intended to limit the present disclosure. The sizes and positional relationships of the components shown in each drawing may be exaggerated to clarify the description. In the following description, the same components may be designated by the same reference numerals, and the description may be omitted.

[0009] Hereinafter, the embodiments of the present disclosure will be described in detail with reference to the drawings. In the following description, terms indicating specific directions or positions (for example, "upper", "lower", "right", "left" and other terms including these terms) will be used as necessary. For example, when the semiconductor device is a photoelectric conversion device, the semiconductor layer has a first surface and a second surface opposite to the first surface and on which light is incident. In the following description of the embodiments, the term "upper" refers to the direction from the second surface to the first surface in the semiconductor layer. The use of these terms is for the purpose of facilitating understanding of the embodiments with reference to the drawings, and the technical scope of the present disclosure is not limited by the meaning of these terms.

[0010] In this specification, a plan view means a view from a direction perpendicular to the first surface of the semiconductor layer. A cross-sectional view means a view of a cross section perpendicular to the first surface of the semiconductor layer. When the light incident surface of the semiconductor layer is a rough surface when viewed microscopically, the plan view is defined based on the light incident surface of the semiconductor layer when viewed macroscopically.

[0011] In this specification, when the terms "N-type" and "P-type" are used simply, they refer to the net type minus the amount compensated for by impurities of the opposite conductivity type. For example, a region where the concentration of added P-type impurities is higher than the concentration of added N-type impurities is a P-type semiconductor region. Conversely, a region where the concentration of added N-type impurities is higher than the concentration of added P-type impurities is an N-type semiconductor region.

[0012] (First embodiment) A first embodiment will be described with reference to Figures 1 to 5. In this embodiment, a stacked back-illuminated CMOS sensor will be described as an example of a semiconductor device. However, each embodiment is not limited to this and can be applied to other examples of semiconductor devices. For example, the semiconductor device may be a front-illuminated CMOS sensor or a SPAD sensor, and can also be applied to semiconductor devices other than image sensors, such as distance measuring devices (devices for distance measurement using focus detection or TOF (Time Of Flight)) and photometric devices (devices for measuring the amount of incident light, etc.).

[0013] Fig. 1 is a plan view of a semiconductor device 10 according to this embodiment. Fig. 1 shows the semiconductor device 10 for one chip. The semiconductor device 10 has holes 20 exposing pads 30 for external connection, for example, on the periphery. A moisture-resistant structure 50 is provided between the pads and a chip end 60, which is the periphery of the chip portion.

[0014] 2 is a cross-sectional view of the semiconductor device 10 according to the present embodiment taken along the line AA′, i.e., showing the vicinity of the moisture-resistant structure 50. The semiconductor device 10 is a laminated body in which a semiconductor layer 100 and a semiconductor layer 200 are laminated. Between the semiconductor layer 100 and the semiconductor layer 200, there are a wiring structure 100a and a wiring structure 200a.

[0015] The wiring structure 100 a includes an insulating film 103 , a plug 104 , a wiring layer 105 , an insulating film 106 , a wiring layer 107 , a via plug 108 , an insulating film 109 , a via plug 110 , a wiring layer 111 , an insulating film 112 , a junction via 113 , and a junction metal 114 .

[0016] An element isolation 101 and gate electrodes 102 of a plurality of transistors are provided in a semiconductor layer 100. The element isolation 101 has, for example, an STI (Shallow Trench Isolation) structure, and defines an element region (active region) of the semiconductor layer 100.

[0017] The wiring structure 200a includes an insulating film 203, a plug 204, a wiring layer 205, an insulating film 206, a via plug 207, a wiring layer 208, an insulating film 209, a via plug 210, a wiring layer 211, an insulating film 212, a junction via 213, and a junction metal 214. Furthermore, the wiring structure 200a has a moisture-resistant structure 50 for suppressing moisture from penetrating from the chip end 60.

[0018] The semiconductor layer 200 is provided with an element isolation 201, gate electrodes 202 of a plurality of transistors, and a photoelectric conversion unit 215 that receives incident light and generates charges. The element isolation 201 has an STI structure or a DTI (Deep Trench Isolation) structure, and defines an element region (active region) of the semiconductor layer 200. The element isolation 201 may penetrate the semiconductor layer 200 in the vertical direction. Alternatively, the element isolation 201 may not penetrate the semiconductor layer 200 in the vertical direction. For example, the element isolation 201 may extend from the light incident surface of the semiconductor layer 200 to the opposing surface and not penetrate the opposing surface, or may extend from the surface of the semiconductor layer 200 opposing the light incident surface to the light incident surface and not penetrate the light incident surface.

[0019] The moisture-resistant structure 50 has a trench 310 as an insulator portion that vertically penetrates the semiconductor layer 200, a plug (first plug) 311, a plug (second plug) 312, a wiring layer 313, and a via plug 314. The moisture-resistant structure 50 is formed in the process of forming the plug 204, the wiring layer 205, the via plug 207, the wiring layer 208, the via plug 210, and the wiring layer 211, and is disposed along the inner side of the chip end portion 60.

[0020] The plug 311 is located on the opposite side of the trench 310 from the chip end 60. The plug 312 is located between the trench 310 and the chip end 60. The semiconductor layer 200 has a semiconductor region (second semiconductor region) 240 on the photoelectric conversion section 215 side with respect to the trench 310, and a semiconductor region (fourth semiconductor region) 260 on the chip end 60 side with respect to the trench 310. The plug 311 and the plug 312 have a conductor, and the semiconductor region 240 and the semiconductor region 260 are electrically connected via the plug 311, the plug 312, the wiring layer 31, and the via plug 314. The semiconductor layer 200 and the plug 311 are electrically connected in a contact region (first semiconductor region) 230. Similarly, the semiconductor layer 200 and the plug 312 are electrically connected in a contact region (third semiconductor region) 250.

[0021] A metal oxide film 216 is provided on the light incidence surface of the semiconductor layer 200. Typically, this may be a tantalum oxide film. An anti-reflection film 217 is provided above the metal oxide film 216. The anti-reflection film may be an aluminum oxide film. An insulating film 218 is provided on the anti-reflection film 217. This insulating film 218 may be a single layer film of any one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film, or a laminated film of a combination of these.

[0022] A color filter 219 is provided on the insulating film 218. Although detailed illustration of the color filter 219 is omitted, a color filter corresponding to any one of red, blue, and green is provided for each pixel. Typically, the color filter 219 can be a Bayer array or a quad Bayer array. Note that this is not limited to this example, and the color filter may be a filter of a color corresponding to a complementary color. Also, a filter corresponding to infrared light may be provided, or a pixel corresponding to white that transmits all wavelengths of red, green, and blue may be provided. As an example of a pixel corresponding to white, there is a structure in which a color filter material is not provided in the layer of the color filter 219, but instead is filled with an insulating film.

[0023] A microlens 220 is provided on the color filter 219. Note that the microlens 220 is not essential, and a structure in which the microlens 220 is omitted may be used.

[0024] 3 is a plan view of the moisture-resistant structure 50 in this embodiment seen through from the top in FIG. 2. The trench 310 can be arranged along the chip end portion 60. Here, the wiring layer 313 on the chip end portion 60 side of the trench 310 is electrically connected to the wiring layer 313 on the opposite side to the chip end portion 60. Furthermore, the plug 311 is electrically connected to the via plug 314 through the wiring layer 313. Furthermore, the plug 312 is electrically connected to the via plug 314 through the wiring layer 313.

[0025] The problem to be solved by this embodiment will be described with reference to Fig. 4. Fig. 4(a) shows a case where the semiconductor region 240 and the semiconductor region 260 are not electrically connected in the moisture-resistant structure 50. In this configuration, damage 400 to the semiconductor layer and elements, and damage 410 to the moisture-resistant structure may occur due to the effects of charge-up that may occur during the manufacturing process and static electricity that may occur during product operation.

[0026] FIG. 4(b) is a diagram showing a structure for suppressing the destruction 400 of the semiconductor layer and the element and the destruction 410 of the moisture-resistant structure. In FIG. 4(b), the semiconductor region 240 and the semiconductor region 260 are electrically connected via the wiring layer 313 of the moisture-resistant structure 50. This can mitigate charge-up that may occur during the manufacturing process and suppress the destruction 400 of the semiconductor layer and the element and the destruction 410 of the moisture-resistant structure. However, a decrease 430 in dark current and sensitivity may occur due to the effect that the charge 420 that may occur at the chip end portion 60 moves to the photoelectric conversion unit 215 through the moisture-resistant structure 50. This embodiment suppresses the decrease 430 in dark current and sensitivity.

[0027] Specifically, the conductivity types of the contact region 230 and the semiconductor region 240 are made to be opposite polarities. Similarly, the conductivity types of the contact region 250 and the semiconductor region 260 may be made to be opposite polarities. These methods can suppress the decrease 430 in dark current and sensitivity described in FIG. 4(b).

[0028] 5 shows combinations of the conductivity types of the contact region 230, the semiconductor region 240, the contact region 250, and the semiconductor region 260. Here, combinations 1 to 11 are described as examples of combinations that are effective in solving the above-mentioned problems in either this embodiment or the third embodiment described later. Combinations 12 and 13 are described as examples that are ineffective in solving the above-mentioned problems. The effect on adjacent chips will be described later in the explanation of the third embodiment.

[0029] In this embodiment, the combination 1 shown in Fig. 5 is used, that is, the conductivity type of the contact region 230 is the first conductivity type (P type in this embodiment), the conductivity type of the semiconductor region 240 is the second conductivity type (N type in this embodiment), the conductivity type of the contact region 250 is the second conductivity type, and the conductivity type of the semiconductor region 260 is the second conductivity type. By forming a PN junction with the conductivity type of the contact region 230 and the conductivity type of the semiconductor region 240 being opposite in polarity, it is possible to suppress the movement of the charge 420 that may be generated at the chip end 60 to the photoelectric conversion unit 215. Similarly, when combinations 3, 4, 6, 7, 8, and 9 are used among the combinations shown in Fig. 5, it is possible to suppress the movement of the charge within the chip.

[0030] Next, the layout of the moisture-resistant structure 50 in this embodiment will be described with reference to Fig. 6. Fig. 6(a) is a schematic diagram showing a configuration in which a trench 310 is provided around the entire outer periphery (along the chip end 60) of the semiconductor device 10, plugs 311 and 312 are provided along the trench 310, and a wiring layer 313 is provided to cover them. With this configuration, floating of the semiconductor layer 200 including the chip end 60 can be suitably avoided.

[0031] The moisture-resistant structure 50 at the chip diagonal portion may be bent at a 45-degree angle as shown in the top view of Fig. 6. This can reduce variations in the line width and depth of the trench 310 during manufacturing. For example, if the chip diagonal portion is a right angle, the line width becomes thicker during processing of the trench 310, which can easily cause voids, resulting in a defective guard ring.

[0032] 6(b) shows a form in which the plug 311, the plug 312, and the wiring layer 313 are intermittently connected to the trench 310. As long as at least a portion of the trench 310 is electrically connected to the plug 311, the plug 312, and the wiring layer 313, the effects described in this embodiment can be obtained.

[0033] In Fig. 6(c), the connection parts are provided only at the diagonal parts of the chip. Also, in Fig. 6(c), the connection parts are electrically connected to the wiring layer 313. In this case, a path with higher conductivity than the semiconductor layer 200 can be used, so that the time lag to the applied voltage is small, and floating can be quickly avoided.

[0034] Fig. 6(d) is a modification of Fig. 6(c), showing a form in which the trenches 310 provided around the chip edge 60 are provided discontinuously. When the trenches 310 are provided discontinuously, isolation regions 315 may be formed in the interrupted portions by a technique such as ion implantation. Formation of such isolation regions 315 is particularly effective against line width variations in processing of the portions where the trenches 310 are bent.

[0035] The shapes of the above-described Figs. 6(a) to (d) may be formed by combining the respective features.

[0036] The wiring of the wiring layer 760 forms an electrical path between the contact region 230 and the contact region 250. The potential of the wiring of this wiring layer 760 can be floating, but a ground voltage or a power supply voltage may also be applied.

[0037] Second Embodiment The present embodiment will be described focusing on the differences from the first embodiment. In other words, the matters described in the first embodiment can also be applied to the present embodiment.

[0038] The second embodiment will be described with reference to Fig. 7. This embodiment is an example in which the configuration described in the first embodiment is applied to a CMOS sensor in which a pixel region and a pixel transistor are formed on separate substrates.

[0039] The pixel substrate (first substrate) 3000 has a semiconductor layer 500, a photoelectric conversion portion 510, a floating diffusion 520, a gate electrode 530, and an insulating film 540. The pixel transistor substrate (second substrate) 4000 has a semiconductor layer 600, a gate electrode 610, a source-drain region 620, a barrier metal 640, a plug 650, a through electrode 660, a wiring layer 670, and an insulating film 680.

[0040] The moisture-resistant structure 700 has a trench 710, a through via 720, a barrier metal 730, a through electrode 740 located on the opposite side of the trench 710 with respect to the chip end portion 60, a through electrode 750 located on the chip end portion 60 side, a wiring layer 760, and a via plug 770. Each part of the moisture-resistant structure 700 can be formed simultaneously in the process of forming the pixel transistor substrate.

[0041] The pixel substrate 3000 and the pixel transistor substrate 4000 are bonded via a bonding surface 800 , and are electrically connected via a through electrode 660 , a through electrode 740 , and a through electrode 750 .

[0042] The semiconductor layer 500 has a semiconductor region (second semiconductor region) 560 located on the photoelectric conversion section 510 side with respect to the trench 710, and a semiconductor region (fourth semiconductor region) 580 located on the end portion 60 side with respect to the trench 710. The semiconductor layer 500 also has a contact region (first semiconductor region) 550 to which the through electrode 740 is connected, and a contact region (third semiconductor region) 570 to which the through electrode 750 is connected. The contact region 550 is formed inside the semiconductor region 560, and similarly, the contact region 570 is formed inside the semiconductor region 580.

[0043] In such a structure, the technology of the present disclosure can be applied by applying the polarities in the table of FIG. 5 to the respective conductivity types of contact region 550, semiconductor region 560, contact region 570, and semiconductor region 580, as in the first embodiment.

[0044] (Third embodiment) The present embodiment will be described focusing on the differences from the first embodiment. In other words, the matters described in the first embodiment can also be applied to the present embodiment.

[0045] The third embodiment will be described with reference to Fig. 8. Note that the description of the same parts as in the first embodiment will be omitted. Fig. 8 is a diagram showing a wafer form in which two chips, a semiconductor device 1000 and a semiconductor device 2000, are divided by a scribe region 70. In the first embodiment, the effect of the technology of the present disclosure in the chip form was described in detail, but the technology of the present disclosure is also effective in the wafer form.

[0046] Specifically, chip inspection in wafer form may be performed. In the inspection, a substrate potential or a semiconductor layer potential may be shared between two adjacent chips via the scribe region 70. In this case, charge transfer may occur between the chips via the scribe region 70, and chip inspection in wafer form may not be performed accurately. By applying the moisture-resistant structure 50 of the present disclosure, charge transfer between the chips may be suppressed, and the accuracy of chip inspection in wafer form may be improved.

[0047] For example, when the polarities of the contact region 230, the semiconductor region 240, the contact region 250, and the semiconductor region 260 are combinations 2, 3, 4, 5, 10, and 11 among the combinations shown in FIG. 5, charge transfer between adjacent chips can be suppressed.

[0048] (Fourth embodiment) The fourth embodiment can be applied to all the above-mentioned embodiments. Fig. 9(a) is a schematic diagram for explaining a device 9191 equipped with a semiconductor device 930 of this embodiment. The semiconductor device 930 can be any of the semiconductor devices of the above-mentioned embodiments.

[0049] An apparatus 9191 including a semiconductor device 930 will be described in detail. As described above, the semiconductor device 930 can include a package 920 that houses the semiconductor device 910, in addition to the semiconductor device 910 having the semiconductor layer 902. The package 920 can include a base to which the semiconductor device 910 is fixed, and a lid such as glass that faces the semiconductor device 910. The package 920 can further include a bonding member such as a bonding wire or a bump that connects a terminal provided on the base and a terminal provided on the semiconductor device 910.

[0050] The device 9191 can include at least one of an optical device 940, a control device 950, a processing device 960, a display device 970, a storage device 980, and a mechanical device 990. The optical device 940 corresponds to the semiconductor device 930. The optical device 940 is, for example, a lens, a shutter, or a mirror. The control device 950 controls the semiconductor device 930. The control device 950 is, for example, a semiconductor device such as an ASIC.

[0051] The processing device 960 processes the signal output from the semiconductor device 930. The processing device 960 is a semiconductor device such as a CPU or ASIC for configuring an AFE (analog front end) or a DFE (digital front end). The display device 970 is an EL display device or a liquid crystal display device that displays information (images) obtained by the semiconductor device 930. The storage device 980 is a magnetic device or a semiconductor device that stores information (images) obtained by the semiconductor device 930. The storage device 980 is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive.

[0052] The mechanical device 990 has a moving part or a propulsion part such as a motor or an engine. In the device 9191, the signal output from the semiconductor device 930 is displayed on the display device 970, or transmitted to the outside by a communication device (not shown) included in the device 9191. For this purpose, the device 9191 preferably further includes a memory device 980 and a processing device 960 in addition to the memory circuit and arithmetic circuit included in the semiconductor device 930. The mechanical device 990 may be controlled based on the signal output from the semiconductor device 930.

[0053] The device 9191 is also suitable for electronic devices such as information terminals (e.g., smartphones and wearable devices) with a photographing function and cameras (e.g., interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). The mechanical device 990 in the camera can drive components of the optical device 940 for zooming, focusing, and shutter operation. Alternatively, the mechanical device 990 in the camera can move the semiconductor device 930 for vibration isolation operation.

[0054] The device 9191 may be transportation equipment such as a vehicle, a ship, or an aircraft. The mechanical device 990 in the transportation equipment may be used as a moving device. The device 9191 as a transportation equipment is suitable for transporting the semiconductor device 930 or for assisting and / or automating driving (piloting) by using a photographing function. The processing device 960 for assisting and / or automating driving (piloting) can perform processing for operating the mechanical device 990 as a moving device based on information obtained by the semiconductor device 930. Alternatively, the device 9191 may be a medical device such as an endoscope, a measuring device such as a distance measuring sensor, an analytical device such as an electron microscope, an office machine such as a copier, or an industrial device such as a robot.

[0055] According to the above-described embodiment, it is possible to obtain good pixel characteristics. Therefore, the value of the semiconductor device can be increased. In this case, increasing the value corresponds to at least one of adding functions, improving performance, improving characteristics, improving reliability, improving manufacturing yield, reducing environmental load, reducing costs, reducing size, and reducing weight.

[0056] Therefore, if the semiconductor device 930 according to this embodiment is used in the equipment 9191, the value of the equipment can be improved. For example, by mounting the semiconductor device 930 on a transport equipment, excellent performance can be obtained when photographing the outside of the transport equipment or measuring the external environment. Therefore, in manufacturing and selling the transport equipment, it is advantageous to decide to mount the semiconductor device according to this embodiment on the transport equipment in order to improve the performance of the transport equipment itself. In particular, the semiconductor device 930 is suitable for transport equipment that performs driving assistance and / or automatic driving of the transport equipment using information obtained by the semiconductor device.

[0057] The photoelectric conversion system and the moving object of this embodiment will be described with reference to FIGS.

[0058] 9(b) shows an example of a photoelectric conversion system related to an in-vehicle camera. The photoelectric conversion system 8000 has a photoelectric conversion device 80. The photoelectric conversion device 80 is the photoelectric conversion device (imaging device) described in any of the above embodiments. The photoelectric conversion system 8000 has an image processing unit 801 that performs image processing on a plurality of image data acquired by the photoelectric conversion device 80, and a parallax acquisition unit 802 that calculates parallax (phase difference of parallax images) from the plurality of image data acquired by the photoelectric conversion system 8000.

[0059] The photoelectric conversion system 8000 also includes a distance acquisition unit 803 that calculates the distance to the object based on the calculated parallax, and a collision determination unit 804 that determines whether or not there is a possibility of collision based on the calculated distance. Here, the parallax acquisition unit 802 and the distance acquisition unit 803 are examples of distance information acquisition means that acquire information on the distance to the object. That is, the distance information is information on the parallax, the defocus amount, the distance to the object, and the like. The collision determination unit 804 may determine the possibility of collision using any of these pieces of distance information.

[0060] The distance information acquisition means may be realized by dedicated hardware, a software module, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a combination of these.

[0061] The photoelectric conversion system 8000 is connected to a vehicle information acquisition device 810 and can acquire vehicle information such as vehicle speed, yaw rate, steering angle, etc. The photoelectric conversion system 8000 is also connected to a control ECU 820, which is a control device that outputs a control signal for generating a braking force for the vehicle based on the determination result of the collision determination unit 804. The photoelectric conversion system 8000 is also connected to an alarm device 830 that issues an alarm to the driver based on the determination result of the collision determination unit 804.

[0062] For example, when the collision probability is high as a result of the judgment by the collision judgment unit 804, the control ECU 820 performs vehicle control to avoid the collision and reduce damage by applying the brakes, releasing the accelerator, suppressing the engine output, etc. The warning device 830 warns the user by sounding a warning, displaying warning information on the screen of a car navigation system, etc., applying vibrations to the seat belt or steering wheel, etc.

[0063] In this embodiment, the surroundings of the vehicle, for example, the front or rear, are imaged by the photoelectric conversion system 8000. Fig. 9(c) shows a photoelectric conversion system for imaging the area in front of the vehicle (imaging range 850). A vehicle information acquisition device 810 sends an instruction to the photoelectric conversion system 8000 or the photoelectric conversion device 80. This configuration can further improve the accuracy of distance measurement.

[0064] Although an example of control to prevent collision with other vehicles has been described above, the present invention can also be applied to control of automatic driving by following other vehicles, control of automatic driving to prevent deviation from lanes, and the like. Furthermore, the photoelectric conversion system is not limited to vehicles such as the vehicle itself, but can be applied to moving bodies (moving devices) such as ships, aircraft, and industrial robots. For example, the present invention may have a moving body equipped with the photoelectric conversion device described in each embodiment, and a control unit that controls the movement of the moving body using a signal output by the photoelectric conversion device. In addition, the present invention can be applied not only to moving bodies, but also to a wide range of devices that use object recognition, such as an intelligent transport system (ITS).

[0065] (Other embodiments) It should be noted that the above-mentioned embodiments are merely examples of the implementation of the present disclosure, and the technical scope of the present disclosure should not be interpreted as being limited by these. In other words, the present disclosure can be implemented in various forms without departing from its technical concept or main features. For example, combinations of the elements of the above-mentioned embodiments are also within the scope of the present disclosure.

[0066] In addition, each of the embodiments described above can be appropriately modified without departing from the scope of the technical concept. The disclosure of this specification includes not only what is described in this specification, but also all matters that can be understood from this specification and the drawings attached to this specification.

[0067] The disclosure of this embodiment includes the following configurations and methods.

[0068] (Configuration 1) a semiconductor layer having a first surface and having an element region and an end portion; A wiring layer disposed on the first surface side; an insulator portion disposed between the element region and the end portion in a plan view with respect to the first surface and penetrating the semiconductor layer; a first plug including a conductor, disposed between the first surface and the wiring layer, and disposed between the element region and the insulator portion in a plan view with respect to the first surface; a second plug including a conductor, disposed between the first surface and the wiring layer, and disposed between the end portion and the insulator portion in a plan view with respect to the first surface; the first plug and the second plug are electrically connected by the wiring layer; the conductor included in the first plug is connected to a first semiconductor region of a first conductivity type arranged in the semiconductor layer; The first semiconductor region is disposed within a second semiconductor region of a second conductivity type disposed in the semiconductor layer. A semiconductor device comprising:

[0069] (Configuration 2) the conductor included in the second plug is connected to a third semiconductor region of the second conductivity type arranged in the semiconductor layer; The third semiconductor region is disposed within a fourth semiconductor region of the second conductivity type disposed in the semiconductor layer. The semiconductor device according to configuration 1,

[0070] (Configuration 3) A first substrate on which the semiconductor layer is provided and a second substrate on which a semiconductor layer different from the semiconductor layer is provided, the element region of the semiconductor layer includes a photoelectric conversion unit that receives incident light and generates charges, the different semiconductor layer includes a pixel transistor that outputs a signal based on the charge, 3. The semiconductor device according to claim 1, wherein the first substrate and the second substrate are bonded at a bonding surface.

[0071] (Configuration 4) The semiconductor device according to any one of configurations 1 to 3, wherein the insulator portion is disposed in at least a portion of an outer periphery of the semiconductor device when viewed in a plan view from the first surface.

[0072] (Configuration 5) 5. The semiconductor device according to configuration 4, wherein the insulator portion is arranged discontinuously around the entire outer periphery when viewed from the first surface.

[0073] (Configuration 6) 5. The semiconductor device according to configuration 4, wherein the insulator portion is disposed around the entire outer periphery when viewed from above the first surface.

[0074] (Configuration 7) The semiconductor device according to any one of structures 1 to 4, characterized in that, when viewed in a plan view from the first surface, the insulator portion is at least partially connected to the first plug, the second plug, and the wiring layer.

[0075] (Configuration 8) The semiconductor device according to configuration 7, wherein the insulator portion is connected to the first plug, the second plug, and the wiring layer at diagonal portions of the semiconductor device when viewed in a plan view from the first surface.

[0076] (Configuration 9) The semiconductor device according to configuration 6, wherein the insulator portion is intermittently connected to the first plug, the second plug, and the wiring layer around the entire periphery when viewed in a plan view from the first surface.

[0077] (Configuration 10) The semiconductor device according to configuration 6, wherein the insulator portion is connected to the first plug, the second plug, and the wiring layer around the entire periphery when viewed in a plan view from the first surface.

[0078] (Configuration 11) An apparatus including the semiconductor device according to any one of configurations 1 to 10, an optical device corresponding to the semiconductor device; A control device for controlling the semiconductor device; a processing device that processes a signal output from the semiconductor device; a display device for displaying information obtained by the semiconductor device; a storage device that stores information obtained by the semiconductor device; and and a mechanical device that operates based on information obtained by the semiconductor device.

[0079] (Method 1) A method for manufacturing a semiconductor device, comprising: forming an element region in a semiconductor layer having a first surface; forming a first semiconductor region of a first conductivity type within a second semiconductor region of a second conductivity type included in a semiconductor layer having a first surface; forming an insulator portion penetrating the semiconductor layer between the element region and an end portion of the semiconductor layer in a plan view with respect to the first surface; forming a first plug including a conductor in contact with the first semiconductor region and in a region between the element region and the insulator portion in a plan view with respect to the first surface; forming a second plug including a conductor on the first surface side and in a region between an end of the semiconductor layer and the insulator portion in a plan view with respect to the first surface; electrically connecting the first plug and the second plug by a wiring layer. A manufacturing method characterized by: [Explanation of symbols]

[0080] 200 Semiconductor layer 215 Photoelectric conversion unit 230 Contact Area 240 Semiconductor Area 310 Trench 311, 312 plug 313 Wiring layer

Claims

1. a semiconductor layer having a first surface and having an element region and an end portion; A wiring layer disposed on the first surface side; an insulator portion disposed between the element region and the end portion in a plan view with respect to the first surface and penetrating the semiconductor layer; a first plug including a conductor, the first plug being disposed between the first surface and the wiring layer and between the element region and the insulator portion in a plan view with respect to the first surface; a second plug including a conductor, disposed between the first surface and the wiring layer, and disposed between the end and the insulator portion in a plan view with respect to the first surface; the first plug and the second plug are electrically connected by the wiring layer; the conductor included in the first plug is connected to a first semiconductor region of a first conductivity type arranged in the semiconductor layer; The first semiconductor region is disposed within a second semiconductor region of a second conductivity type disposed in the semiconductor layer. A semiconductor device comprising:

2. the conductor included in the second plug is connected to a third semiconductor region of the second conductivity type arranged in the semiconductor layer; The third semiconductor region is disposed within a fourth semiconductor region of the second conductivity type that is disposed in the semiconductor layer.

2. The semiconductor device according to claim 1,

3. A first substrate on which the semiconductor layer is provided, and a second substrate on which a semiconductor layer different from the semiconductor layer is provided, the element region of the semiconductor layer includes a photoelectric conversion unit that receives incident light and generates charges, the different semiconductor layer includes a pixel transistor that outputs a signal based on the charge, 2. The semiconductor device according to claim 1, wherein the first substrate and the second substrate are bonded to each other at a bonding surface.

4. The semiconductor device according to claim 1 , wherein the insulator portion is disposed on at least a part of an outer periphery of the semiconductor device in a plan view from the first surface.

5. The semiconductor device according to claim 4 , wherein the insulator portion is disposed discontinuously around the entire periphery of the outer periphery in a plan view from the first surface.

6. The semiconductor device according to claim 4 , wherein the insulating portion is disposed over the entire periphery of the outer periphery in a plan view from the first surface.

7. 5 . The semiconductor device according to claim 4 , wherein the insulator portion is at least partially connected to the first plug, the second plug, and the wiring layer in a plan view from the first surface.

8. 8. The semiconductor device according to claim 7, wherein the insulator portion is connected to the first plug, the second plug, and the wiring layer at diagonal portions of the semiconductor device when viewed from the first surface.

9. 7. The semiconductor device according to claim 6, wherein the insulator portion is intermittently connected to the first plug, the second plug, and the wiring layer over an entire periphery in a plan view from the first surface.

10. 7. The semiconductor device according to claim 6, wherein the insulator portion is connected to the first plug, the second plug, and the wiring layer over the entire periphery in a plan view from the first surface.

11. A method for manufacturing a semiconductor device, comprising: forming an element region in a semiconductor layer having a first surface; forming a first semiconductor region of a first conductivity type within a second semiconductor region of a second conductivity type included in a semiconductor layer having a first surface; forming an insulator portion penetrating the semiconductor layer between the element region and an end portion of the semiconductor layer in a plan view with respect to the first surface; forming a first plug including a conductor in contact with the first semiconductor region and in a region between the element region and the insulator portion in a plan view with respect to the first surface; forming a second plug including a conductor on the first surface side and in a region between an end of the semiconductor layer and the insulator portion in a plan view with respect to the first surface; and electrically connecting the first plug and the second plug by a wiring layer. A manufacturing method characterized by:

12. An apparatus comprising the semiconductor device according to any one of claims 1 to 10, an optical device corresponding to the semiconductor device; A control device for controlling the semiconductor device; a processing device that processes a signal output from the semiconductor device; a display device for displaying information obtained by the semiconductor device; a storage device that stores information obtained by the semiconductor device; and and a mechanical device that operates based on information obtained by the semiconductor device.

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