Frequency synthesizer

Abstract

To provide a frequency synthesizer capable of simply suppressing signal strength of a spurious included in an output signal of the frequency synthesizer.SOLUTION: A frequency synthesizer includes: a DDS for outputting a DDS signal; a first multiplier for outputting a first multiplication signal obtained by multiplying a frequency of an inputted signal; a first bandpass filter for passing the first multiplication signal; a second multiplier for outputting a second multiplication signal obtained by multiplying the frequency of the inputted signal by a multiplication number different from a multiplication number of the first multiplication signal; a second bandpass filter for passing the second multiplication signal; a first switching part for connecting the DDS and either one of the first multiplier or the second multiplier according to inputted first control signal; and a control part for supplying the first control signal for connecting the multiplier and the DDS to the first switching part.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a frequency synthesizer.

Background Art

[0002] There is known a frequency synthesizer that switches and outputs signals of a plurality of predetermined frequencies using a direct digital synthesizer (DDS) (see, for example, Patent Document 1 and Patent Document 2).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] The output signal of the DDS contains spurs caused by harmonics of the frequency of the signal. Spurs may occur near the frequency of the output signal of the DDS due to aliasing. In this case, even when using a narrow-band filter such as a SAW filter with a passband of about several MHz, it may be difficult to reduce the signal intensity of the spurs, which may cause performance degradation of devices operating based on the output signal.

[0005]

Means for Solving the Problems

[0006] ​In a first aspect of the present invention, a DDS that outputs a DDS signal, a first multiplier that outputs a first multiplied signal obtained by multiplying the frequency of an input signal, a first band-pass filter that passes the first multiplied signal output by the first multiplier, a second multiplier that outputs a second multiplied signal obtained by multiplying the frequency of the input signal by a multiplication factor different from the multiplication factor of the first multiplied signal, a second band-pass filter that passes the second multiplied signal output by the second multiplier, a first switching unit that connects either the DDS, the first multiplier, or the second multiplier in accordance with an input first control signal, and a control unit that, when the DDS signal for outputting a predetermined set frequency is input among the first multiplier and the second multiplier, identifies a multiplier that outputs a multiplied signal in which the frequency difference between the spurious frequency of a predetermined order or lower and the set frequency exceeds a predetermined detuning frequency, and supplies the first control signal for connecting the identified multiplier and the DDS to the first switching unit. A frequency synthesizer is provided.

[0007] The frequency synthesizer further includes a second switching unit that connects either one of the first band-pass filter and the second band-pass filter and an output unit of the frequency synthesizer in accordance with an input second control signal, and the control unit may supply the second control signal for connecting the filter connected to the multiplier to which the first switching unit is connected to the DDS and the output unit to the second switching unit.

[0008] The frequency synthesizer further includes a storage unit that stores, in association with the set frequency, information on a multiplier preliminarily identified corresponding to the set frequency among the first multiplier and the second multiplier, and the control unit may read out the information on the multiplier corresponding to the set frequency from the storage unit and identify the multiplier that outputs the multiplied signal.

[0009] The predetermined detuning frequency may be a frequency greater than a half-value width of a pass frequency band of the first band-pass filter and the second band-pass filter.

[0010] The frequency synthesizer further includes one or more multipliers having a multiplication factor different from that of the first multiplier and the second multiplier, and one or more band-pass filters respectively connected to the one or more multipliers. The first switching unit connects, according to the first control signal, the DDS and any one of the multipliers from the first multiplier to the Nth multiplier (N is an integer of 3 or more). The control unit may supply the first switching unit with the first control signal for connecting the multiplier that outputs a signal whose frequency difference exceeds the predetermined out-of-tune frequency among the first multiplier to the Nth multiplier and the DDS.

Advantages of the Invention

[0011] According to the present invention, there is an effect that the signal strength of spurious signals included in the output signal of the frequency synthesizer can be easily suppressed.

Brief Description of the Drawings

[0012]

Figure 1

Figure 2

Figure 3

Modes for Carrying Out the Invention

[0013] <Configuration Example of Conventional Frequency Synthesizer 10> FIG. 1 shows a configuration example of a conventional frequency synthesizer 10. The frequency synthesizer 10 outputs an output signal having a set frequency from an output unit 11. The frequency synthesizer 10 includes an output unit 11, a clock signal source 20, a direct digital synthesizer (DDS) 30, a first switching unit 41, a second switching unit 42, a first narrow-band filter 51, a second narrow-band filter 52, a control unit 60, a storage unit 61, and an amplifier circuit 70.

[0014] The clock signal source 20 outputs a clock signal. The clock signal source 20 is, for example, a clock signal source capable of outputting a clock signal with a frequency specified from the control unit 60. The clock signal source 20 outputs a clock signal with a clock frequency of, for example, about 1000 MHz to about 4000 MHz. The clock signal output by the clock signal source 20 becomes the reference clock signal of the DDS 30.

[0015] The DDS 30 outputs a DDS signal based on the clock signal output from the clock signal source 20. The DDS 30 outputs a DDS signal with a frequency indicated by the control signal received from the control unit 60. The frequency of the DDS signal is, for example, a frequency between about 500 MHz and about 3000 MHz. Since the operation of the DDS 30 outputting the DDS signal is known, the description is omitted here.

[0016] The DDS signal output by the DDS 30 may include spurs caused by the Nth harmonic (N is a natural number of 2 or more) of the DDS signal. Such higher-order spurs are generated when the Nth harmonic is folded back at the clock frequency. Therefore, the frequency at which the spurs are generated changes according to the frequency of the DDS signal, the order of the harmonic, and the clock frequency. In the present embodiment, the spurs caused by the Nth harmonic of the DDS signal are referred to as Nth-order spurs or simply spurs.

[0017] The conventional frequency synthesizer 10 reduces such spurs using a narrowband filter. Since the DDS 30 outputs DDS signals with various frequencies according to the setting data, the frequency synthesizer 10 switches a plurality of narrowband filters corresponding to the setting data. FIG. 1 shows an example of the frequency synthesizer 10 capable of switching two narrowband filters.

[0018] The first switching unit 41 and the second switching unit 42 switch the narrowband filter to be connected to the DDS 30 according to the control signal received from the control unit 60. For example, the first switching unit 41 connects the DDS 30 to one of the first narrowband filter 51 and the second narrowband filter 52 according to the input first control signal. Also, the second switching unit 42 connects one of the first narrowband filter 51 and the second narrowband filter 52 to the output unit 11 according to the input second control signal.

[0019] The first narrowband filter 51 is a band-pass filter that reduces the spurious components superimposed on the DDS signal while passing the first frequency corresponding to the DDS signal of a predetermined first frequency output by the DDS 30. The second narrowband filter 52 is, similarly to the first narrowband filter 51, a band-pass filter that reduces the spurious components superimposed on the DDS signal while passing the second frequency corresponding to the DDS signal of a predetermined second frequency output by the DDS 30.

[0020] The passband widths of the first narrowband filter 51 and the second narrowband filter 52 are desirably smaller values in order to reduce spurious, for example, desirably about several MHz or less. The first narrowband filter 51 and the second narrowband filter 52 are, for example, SAW (Surface Acoustic Wave) filters, BAW (Bulk Acoustic Wave) filters, etc.

[0021] The control unit 60 controls each part of the frequency synthesizer 10. The control unit 60 supplies, for example, a control signal for designating the frequency of the clock signal of the clock signal source 20 to the clock signal source 20. The control unit 60 supplies setting data for setting the frequency of the DDS signal of the DDS 30 to the DDS 30. The control unit 60 supplies control signals for designating the connections of the first switching unit 41 and the second switching unit 42 to the first switching unit 41 and the second switching unit 42, respectively.

[0022] The control unit 60 causes, for example, a clock signal with a predetermined clock frequency to be output from the clock signal source 20 and causes a DDS signal with a predetermined first frequency to be output from the DDS 30. In this case, the control unit 60 supplies a control signal for connecting the DDS 30 and the first narrowband filter 51 to the first switching unit 41, and supplies a control signal for connecting the first narrowband filter 51 and the output unit 11 to the second switching unit 42.

[0023] Further, the control unit 60 causes a clock signal with a predetermined clock frequency to be output from the clock signal source 20 and causes a DDS signal with a predetermined second frequency to be output from the DDS 30. In this case, the control unit 60 supplies a control signal for connecting the DDS 30 and the second narrowband filter 52 to the first switching unit 41, and supplies a control signal for connecting the second narrowband filter 52 and the output unit 11 to the second switching unit 42.

[0024] Such a control unit 60 may receive an input for designating the frequency of the output signal from a user or the like. In this case, the frequency synthesizer 10 may further include an input unit or the like for the user or the like to input frequency information. Further, the control unit 60 may receive a control signal for designating the frequency of the output signal from an external device or the like. In this case, the frequency synthesizer 10 may further include a receiving circuit, a communication circuit, or the like for receiving a control signal from an external device or the like.

[0025] The control unit 60 is preferably configured by an integrated circuit or the like. The control unit 60 includes, for example, an FPGA (Field Programmable Gate Array), a DSP (Digital Signal Processor), and / or a CPU (Central Processing Unit). When at least a part of the control unit 60 is configured by a computer or the like, the storage unit 61 includes a ROM (Read Only Memory) for storing a BIOS (Basic Input Output System) or the like of a computer or the like for realizing the control unit 60, and a RAM (Random Access Memory) serving as a work area.

[0026] In addition, the storage unit 61 may store various information including an OS (Operating System), application programs, and / or a database referred to during the execution of the application programs. The storage unit 61 may include a large-capacity storage device such as an HDD (Hard Disk Drive) and / or an SSD (Solid State Drive). A processor such as a CPU functions as the control unit 60 by executing the programs stored in the storage unit.

[0027] The storage unit 61 stores, for example, setting data for outputting a DDS signal of a first frequency and setting data for outputting a DDS signal of a second frequency. Further, it is desirable that the storage unit 61 stores, in association with the setting data for outputting the DDS signal of the first frequency, a control signal for connecting the DDS 30 and the first narrowband filter 51 and connecting the first narrowband filter 51 and the output unit 11, or information for generating the control signal.

[0028] Similarly, it is desirable that the storage unit 61 stores, in association with the setting data for outputting the DDS signal of the second frequency, a control signal for connecting the DDS 30 and the second narrowband filter 52 and connecting the second narrowband filter 52 and the output unit 11, or information for generating the control signal.

[0029] The amplification circuit 70 is provided between the second switching unit 42 and the output unit 11 and amplifies the input signal. The amplification circuit 70 outputs the amplified signal from the output unit 11. Note that when the signal intensity of the signal output from the second switching unit 42 is greater than or equal to a predetermined intensity level, the amplification circuit 70 may not be provided.

[0030] The above-described conventional frequency synthesizer 10 switches the narrowband filter that passes the frequency of the DDS signal according to the frequency of the output DDS signal. In such a configuration, by making the passband width of the narrowband filter smaller, spurs included in the DDS signal can be reduced.

[0031] However, depending on the combination of the frequency of the clock signal and the frequency of the DDS signal to be output, the frequency of the aliasing spurious may be close to the frequency of the DDS signal to be output, and there may be a case where the spurious signal intensity cannot be sufficiently reduced even by using a narrow-band filter. Further, when outputting output signals of a plurality of different frequencies from the frequency synthesizer 10, as many narrow-band filters as the number of frequencies to be output are required, and the circuit scale of the system becomes large.

[0032] In addition, narrow-band filters such as SAW filters and BAW filters are expensive, and if narrow-band filters are prepared for the number of frequencies to be used, the cost of the frequency synthesizer 10 will increase. Therefore, the frequency synthesizer 100 according to the present embodiment can suppress the spurious signal intensity without using a narrow-band filter. Such a frequency synthesizer 100 will be described next.

[0033] <First Configuration Example of Frequency Synthesizer 100> FIG. 2 shows a first configuration example of the frequency synthesizer 100 according to the present embodiment. The frequency synthesizer 100 switches combinations of a plurality of multipliers and filters corresponding to the frequency of the output signal to be output. FIG. 2 shows an example of the frequency synthesizer 100 capable of switching two sets of multipliers and filters.

[0034] The frequency synthesizer 100 includes an output unit 11, a clock signal source 20, a DDS 30, a first switching unit 41, a second switching unit 42, a control unit 60, an amplifier circuit 70, a first multiplier 81, a second multiplier 82, a first band-pass filter 91, and a second band-pass filter 92. In the frequency synthesizer 100 shown in FIG. 2, components that operate substantially the same as those of the conventional frequency synthesizer 10 shown in FIG. 1 are denoted by the same reference numerals, and redundant descriptions are omitted.

[0035] The first multiplier 81 outputs a first multiplied signal obtained by multiplying the frequency of the input signal. The second multiplier 82 outputs a second multiplied signal obtained by multiplying the frequency of the input signal. The multiplication factor of the first multiplier 81 is different from the multiplication factor of the second multiplier 82. For example, the multiplication factor of the first multiplier 81 is 3 times, and the multiplication factor of the second multiplier 82 is 4 times.

[0036] The first band-pass filter 91 allows the first multiplied signal output by the first multiplier 81 to pass through. The second band-pass filter 92 allows the second multiplied signal output by the second multiplier 82 to pass through. The first band-pass filter 91 and the second band-pass filter 92 each have a predetermined pass bandwidth as will be described later.

[0037] The first switching unit 41 of the frequency synthesizer 100 connects either the DDS 30 or one of the multipliers, i.e., the first multiplier 81 and the second multiplier 82, according to the input control signal. In this embodiment, the control signal supplied from the control unit 60 to the first switching unit 41 may be referred to as the first control signal.

[0038] The second switching unit 42 of the frequency synthesizer 100 connects either the first band-pass filter 91 or the second band-pass filter 92 and the output unit 11 of the frequency synthesizer 100 via the amplifier circuit 70 according to the input control signal. In this embodiment, the control signal supplied from the control unit 60 to the second switching unit 42 may be referred to as the second control signal.

[0039] In other words, the control unit 60 supplies the first switching unit 41 with a first control signal for connecting either the DDS 30 or one of the multipliers, i.e., the first multiplier 81 and the second multiplier 82. Further, the control unit 60 supplies the second switching unit 42 with a second control signal for connecting the filter connected to the multiplier connected to the DDS 30 by the first switching unit 41 and the output unit 11.

[0040] For example, in the conventional frequency synthesizer 10 described with reference to FIG. 1, the difference between the frequency of the DDS signal and the spurious frequency closest to the frequency of the DDS signal varies from 0 MHz to about several tens of MHz depending on the setting of the clock frequency and the frequency of the DDS signal. Here, the frequency difference between the frequency of the DDS signal and the spurious frequency is referred to as the offset frequency.

[0041] Here, when the DDS signal is multiplied by a multiplier, not only the frequency of the DDS signal but also the spurious frequency is multiplied, so the offset frequency is also multiplied. In other words, when the DDS signal is passed through a multiplier as in the frequency synthesizer 100 according to the present embodiment, the offset frequency of the spurious closest to the frequency of the DDS signal can be multiplied, and the passband width of the filter can be increased.

[0042] Note that as the multiplication factor of the multiplier increases, the offset frequency also increases, but depending on the spurious, the order of folding may increase, and spurious close to the frequency of the DDS signal may occur. Therefore, it is desirable that a multiplier with an appropriate multiplication factor is set corresponding to the setting of the clock frequency and the frequency of the DDS signal of the frequency synthesizer 100. Further, it is more desirable that the frequency synthesizer 100 includes a plurality of multipliers with different multiplication factors and is configured to be able to switch and select an appropriate multiplier based on the setting of the clock frequency and the frequency of the DDS signal.

[0043] For example, consider a case where it is desired to output a signal of 1689 MHz from the frequency synthesizer 100, and an example in which the control unit 60 sets the clock frequency to 3000 MHz and the DDS signal to 563 MHz. Here, it is assumed that the control unit 60 connects the DDS 30 and the first multiplier 81, and connects the first band-pass filter 91 and the output unit 11.

[0044] As a result, the output signal of the frequency synthesizer 100 becomes a first multiplication signal obtained by multiplying the DDS signal by 3 by the first multiplier 81, and the frequency of the output signal becomes 1689 MHz. In this case, among the frequencies of the second to tenth spurs, the offset frequency of the spur closest to the first multiplication signal is 185 MHz. Therefore, the first band-pass filter 91 can reduce the spur closest to the first multiplication signal by including 1689 MHz in the passband and setting the passband width to about the offset frequency.

[0045] Next, consider the case where it is desired to output a signal of 1803 MHz from the frequency synthesizer 100. For example, when the control unit 60 sets the clock frequency to 3000 MHz and the DDS signal to 601 MHz, the frequency of the first multiplication signal obtained by multiplying the DDS signal by 3 by the first multiplier 81 becomes 1803 MHz. However, in this case, among the frequencies of the second to tenth spurs, the offset frequency of the spur closest to the first multiplication signal is 5 MHz. Therefore, it becomes difficult to reduce the spur closest to the first multiplication signal unless the passband width of the first band-pass filter 91 is a narrow-band filter of about several MHz.

[0046] Therefore, consider an example where the control unit 60 sets the clock frequency to 3000 MHz and the DDS signal to 450.75 MHz. Here, assume that the control unit 60 connects DDS30 and the second multiplier 82, and connects the second band-pass filter 92 and the output unit 11.

[0047] As a result, the output signal of the frequency synthesizer 100 becomes a second multiplication signal obtained by multiplying the DDS signal by 4 by the second multiplier 82, and the frequency of the output signal becomes 1803 MHz. In this case, among the frequencies of the second to tenth spurs, the offset frequency of the spur closest to the second multiplication signal is 155 MHz. Therefore, the second band-pass filter 92 can reduce the spur closest to the second multiplication signal by including 1803 MHz in the passband and setting the passband width to about the offset frequency.

[0048] In this way, when the control unit 60 inputs a DDS signal for outputting a multiplied signal of a predetermined set frequency among the first multiplier 81 and the second multiplier 82, the control unit 60 identifies a multiplier that outputs a multiplied signal in which the frequency difference between the spurious frequency equal to or lower than a predetermined order and the set frequency exceeds a predetermined deviation frequency. Here, it is desirable that the combination of the predetermined set frequency and the multiplier that outputs a multiplied signal exceeding the predetermined deviation frequency is stored in the storage unit 61 in advance.

[0049] In other words, the storage unit 61 stores, in association with the set frequency, information on the multiplier that has been specified in advance corresponding to the set frequency among the first multiplier 81 and the second multiplier 82. The storage unit 61 may further store the information on the multiplier in association with the clock frequency. Note that the predetermined deviation frequency is, for example, a frequency greater than the half-value bandwidth of the pass frequency band of the first band-pass filter 91 and the second band-pass filter 92. Also, the predetermined deviation frequency may be a frequency approximately equal to the pass frequency bandwidth of the first band-pass filter 91 and the second band-pass filter 92, or a frequency greater than the pass frequency bandwidth.

[0050] Thereby, the control unit 60 can identify the multiplier that outputs the multiplied signal by reading out the information on the multiplier corresponding to the set frequency from the storage unit 61. Alternatively, the control unit 60 may calculate the frequency at which spurious occurs using an equation, and identify the multiplier corresponding to the set frequency based on the calculated result.

[0051] For example, if the frequency of the DDS signal is F DDS , and the difference between the frequency of the DDS signal and the frequency of the N-th order spurious is F delta,Np,Fsn (F DDS ), then the difference is calculated as follows. Here, Np is the order of the spurious, F sn is the clock frequency of the clock signal, floor() is a function for truncating the decimal part, and mod(x, y) is a function for obtaining the remainder when x is divided by y.

[0052] (Equation 1) F delta,Np,Fsn (FDDS ) = -F DDS + mod{floor(F DDS × Np / (F sn / 2)), 2} × {(F sn / 2) - mod(F DDS × Np, F sn / 2)} + [1 - mod{floor(F DDS × Np / (F sn / 2)), 2}] × mod(F DDS × Np, F sn / 2)

[0053] Then, the control unit 60 sets the clock frequency and the frequency of the DDS signal in order to output an output signal of a predetermined set frequency from the frequency synthesizer 100 corresponding to the multiplication factor of the specified multiplier. Further, the control unit 60 supplies a first control signal for connecting the specified multiplier and the DDS 30 to the first switching unit 41, and supplies a second control signal for connecting the filter connected to the specified multiplier and the output unit 11 to the second switching unit 42.

[0054] As described above, the frequency synthesizer 100 according to the present embodiment selects the multiplier with the larger off-tuning frequency from the spurious and outputs an output signal of a predetermined set frequency. Thereby, for example, even in a band-pass filter with a pass-band width exceeding about several tens of MHz to about 100 MHz, spurious can be reduced.

[0055] Therefore, the frequency synthesizer 100 does not have to use expensive narrow-band filters such as SAW filters and BAW filters as the first band-pass filter 91 and the second band-pass filter 92. The first band-pass filter 91 and the second band-pass filter 92 may be, for example, LC filters formed by inductor elements and capacitor elements. In other words, the frequency synthesizer 100 according to the present embodiment can easily suppress the signal strength of the spurious signal included in the output signal of the frequency synthesizer 100 by using an inexpensive filter.

[0056] In addition, since the frequency synthesizer 100 can increase the passband bandwidths of the first bandpass filter 91 and the second bandpass filter 92, the number of settable frequencies that can be set as the output signal of the frequency synthesizer 100 can be increased.

[0057] For example, from equation (1), in a 3000 MHz clock signal, when the first multiplied signal output from the first multiplier 81 is changed from 1664 MHz to 1688 MHz (when the DDS signal of DDS30 is changed from 554.7 MHz to 562.7 MHz), the offset frequency gradually increases from 101 MHz to 187 MHz. Then, when the first multiplied signal is changed from 1688 MHz to 1740 MHz (when the DDS signal of DDS30 is changed from 562.7 MHz to 580 MHz), the offset frequency gradually decreases from 187 MHz to 100 MHz.

[0058] In other words, when the first multiplied signal from 1664 MHz to 1740 MHz is output, the offset frequency is 100 MHz or more. Therefore, for example, if the center frequency of the passband of the first bandpass filter 91 is set to about 1702 MHz and the passband width is set to about 100 MHz, it can be seen that spurs can be reduced even when the first multiplied signal from about 1664 MHz to about 1740 MHz is output.

[0059] Similarly, in a 3000 MHz clock signal, when the second multiplied signal output from the second multiplier 82 is changed from 1772 MHz to 1846 MHz (when the DDS signal of DDS30 is changed from 443 MHz to 461.5 MHz), the offset frequency gradually increases from 101 MHz to 231 MHz. Then, when the second multiplied signal is changed from 1846 MHz to 1933 MHz (when the DDS signal of DDS30 is changed from 461.5 MHz to 483.3 MHz), the offset frequency gradually decreases from 231 MHz to 101 MHz.

[0060] In other words, when outputting the second harmonic signal from 1772 MHz to 1933 MHz, the offset frequency becomes 100 MHz or higher. Therefore, for example, if the center frequency of the passband of the second bandpass filter 92 is set to about 1853 MHz and the passband width is set to about 100 MHz, it can be understood that spurs can be reduced even when outputting the second harmonic signal from at least about 1803 MHz to about 1903 MHz.

[0061] Note that since the values of the above first harmonic signal and second harmonic signal change with the clock signal, by setting the clock signal to a different frequency, it is also possible to output the first harmonic signal and the second harmonic signal having frequencies different from the above-described frequencies.

[0062] As described above, when the frequency synthesizer 100 according to the present embodiment inputs a DDS signal for outputting an output signal having a set frequency in a predetermined frequency band at a predetermined clock frequency, a multiplier that outputs a harmonic signal in which the frequency difference between the frequency of the spur below a predetermined order and the set frequency exceeds a predetermined offset frequency is specified. By using the specified multiplier, an output signal with reduced spurs can be output. It is desirable that the information on the set frequency of such a predetermined frequency band is stored in the storage unit 61.

[0063] In the frequency synthesizer 100 according to the above-described embodiment, an example in which two sets of a multiplier and a bandpass filter are provided has been described, but the present invention is not limited to this. The frequency synthesizer 100 may include three or more sets of a multiplier and a bandpass filter. Needless to say, the multiplication factors of the plurality of multipliers are different from each other, and the plurality of bandpass filters correspond to the same set of multipliers and have different passbands.

[0064] <Second Configuration Example of Frequency Synthesizer 100> FIG. 3 shows a second configuration example of the frequency synthesizer 100 according to the present embodiment. The frequency synthesizer 100 in the second configuration example shows an example including three sets of a multiplier and a band-pass filter. The frequency synthesizer 100 further includes a third multiplier 83 and a third band-pass filter 93. Also, the first switching unit 41 connects, in accordance with the first control signal, either one of the multipliers from the first multiplier 81 to the third multiplier 83 and the DDS 30. The second switching unit 42 connects, in accordance with the second control signal, either one of the band-pass filters from the first band-pass filter 91 to the third band-pass filter 93 and the output unit 11.

[0065] As described above, the frequency synthesizer 100 may further include one or more multipliers having a multiplication factor different from the multiplication factors of the first multiplier 81 and the second multiplier 82, and one or more band-pass filters respectively connected to the one or more multipliers. In other words, the frequency synthesizer 100 includes N multipliers (N is an integer of 3 or more) that multiply the frequencies of signals input with different multiplication factors, and N band-pass filters respectively connected to the plurality of multipliers.

[0066] In this case, the first switching unit 41 connects, in accordance with the first control signal, the DDS 30 and either one of the multipliers from the first multiplier 81 to the Nth multiplier. Then, the control unit 60 supplies the first switching unit 41 with a first control signal for connecting the multiplier that outputs a signal having a frequency difference exceeding a predetermined detuning frequency among the multipliers from the first multiplier 81 to the Nth multiplier and the DDS 30.

[0067] Similarly, the second switching unit 42 connects, in accordance with the second control signal, either one of the band-pass filters from the first band-pass filter 91 to the Nth band-pass filter and the output unit 11. Then, the control unit 60 supplies the second switching unit 42 with a second control signal for connecting the band-pass filter connected to the multiplier connected to the DDS 30 and the output unit 11.

[0068] By adopting such a configuration, the frequency synthesizer 100 can improve the degree of freedom of parameters to be set when outputting an output signal with reduced spurs. Here, the parameters include the clock frequency of the clock signal, the frequency of the DDS signal, a predetermined offset frequency, the multiplication factor of the multiplier to be used, and the like. Also, the number of settable frequencies that can be set as the output signal of the frequency synthesizer 100 can be increased.

[0069] As described above, the present invention has been described using embodiments. However, the technical scope of the present invention is not limited to the scope described in the above embodiments, and various modifications and changes are possible within the scope of the gist. For example, all or part of the device can be functionally or physically distributed and integrated in any unit. Also, new embodiments resulting from any combination of a plurality of embodiments are included in the embodiments of the present invention. The effects of the new embodiments resulting from the combination have the effects of the original embodiments combined.

Description of Reference Numerals

[0070] 10 Frequency synthesizer 11 Output unit 20 Clock signal source 30 DDS 41 First switching unit 42 Second switching unit 51 First narrowband filter 52 Second narrowband filter 60 Control unit 61 Storage unit 70 Amplification circuit 81 First multiplier 82 Second multiplier 83 Third multiplier 91 First bandpass filter 92 Second bandpass filter 93 Third bandpass filter 100 Frequency synthesizer

Claims

1. A DDS that outputs a DDS signal, A first multiplier that outputs a first multiplied signal obtained by multiplying the frequency of the input signal, A first band-pass filter that allows the first multiplied signal output by the first multiplier to pass through, A second multiplier that outputs a second multiplied signal obtained by multiplying the frequency of the input signal by a multiplication factor different from that of the first multiplied signal, A second band-pass filter that allows the second multiplied signal output by the second multiplier to pass through, A first switching unit that connects either the DDS or one of the multipliers among the first multiplier and the second multiplier according to the input first control signal, A control unit that, when the DDS signal for outputting a predetermined set frequency is input among the first multiplier and the second multiplier, identifies a multiplier that outputs a multiplied signal in which the frequency difference between the spurious frequency of a predetermined order or lower and the set frequency exceeds a predetermined detuning frequency, and supplies the first control signal for connecting the identified multiplier and the DDS to the first switching unit A frequency synthesizer comprising the above.

2. Further comprising a second switching unit that connects either one of the first band-pass filter and the second band-pass filter and the output unit of the frequency synthesizer according to the input second control signal, The control unit supplies the second switching unit with the second control signal for connecting the filter connected to the multiplier to which the first switching unit is connected to the DDS and the output unit. The frequency synthesizer according to Claim 1.

3. Further comprising a storage unit that stores in association with the set frequency information on a multiplier specified in advance corresponding to the set frequency among the first multiplier and the second multiplier, The control unit reads out information on the multiplier corresponding to the set frequency from the storage unit and identifies the multiplier that outputs the multiplied signal. The frequency synthesizer according to Claim 1.

4. The predetermined detuning frequency is a frequency greater than the half-value width of the pass frequency band of the first band-pass filter and the second band-pass filter. The frequency synthesizer according to Claim 1.

5. One or more multipliers having a multiplication factor different from that of the first multiplier and the second multiplier, One or more band-pass filters respectively connected to the one or more multipliers Further comprising the above. The first switching unit connects, according to the first control signal, the DDS and any one of the multipliers from the first multiplier to the Nth multiplier (N is an integer of 3 or more). The control unit supplies the first switching unit with the first control signal for connecting the DDS and the multiplier that outputs a signal whose frequency difference exceeds the predetermined out-of-tune frequency among the multipliers from the first multiplier to the Nth multiplier. The frequency synthesizer according to any one of claims 1 to 4.

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