Chiplet package including semiconductor packaging substrate formed by 3D printing, and electronic device including the same

Abstract

To provide apparatuses, servers, systems, materials, and methods for operating for 3D printing based consumer tailor made semiconductor packaging that simplify the interconnect process and reduce the cost of the interconnect process by using 3D printing to form interconnect structures.SOLUTION: A packaging structure has a single layer body as a substrate 2101 for electrical connection between electronic components and at least one conductive interconnect 2103 formed inside a body, and the at least one interconnect includes one side and the other side exposed to the outside of the body and a line connecting the one side and the other side, and the line crosses transversely or longitudinally through the interior of the single layer body and has a specific curvature in some sections.SELECTED DRAWING: Figure 21

Description

Technical Field

[0001] Various embodiments of the present invention relate to an apparatus, a server, a system, a material, and an operating method thereof for 3D printing-based consumer order-made semiconductor packaging.

Background Art

[0002] The semiconductor industry tends to be lower in price and further lighter, smaller, more multifunctional, and higher in performance.

[0003] The semiconductor process includes wafer manufacturing, pre-processes for generating chips, and post-processes for packaging chips. The improvement speed of the system by semiconductor miniaturization technology based on Moore's law has been braked, and semiconductor packaging, which is a post-process, has attracted attention as a core technology that can create new added value.

[0004] Semiconductor packaging is a technology for electrical connection and protection between semiconductor components, and can significantly improve chip performance by increasing the electrical connection distance and number between semiconductor components.

[0005] In recent years, with the development of various types of application products, the development needs for packaging technology to provide order-made packaging structures for the diverse needs of semiconductor customers have been increasing.

Summary of the Invention

Problems to be Solved by the Invention

[0006] Semiconductor packaging is a technology for electrical connection and protection between semiconductor components, and it is a technology that can significantly improve chip performance by increasing the electrical connection distance and number between semiconductor components. However, conventionally, among the semiconductor packaging costs, the cost of the interconnection process accounts for most of the costs, so it is very costly, and it is not easy to design interconnection structures of various patterns. Moreover, the more complex the structure becomes, the more rapidly the cost increases. Similarly, conductor demand is used not only in conventional IT products but also in AI / automobiles / smart factories, and various types of customer-ordered semiconductor chips are required. However, it has been difficult to solve this problem with conventional established semiconductor production facilities.

[0007] According to various embodiments, an apparatus, a server, a system, a material, and an operation method therefor for 3D printing-based consumer-ordered semiconductor packaging can simplify the interconnection process and reduce the cost of the interconnection process by forming an interconnection structure using 3D printing. In addition, an apparatus, a server, a system, a material, and an operation method therefor for 3D printing-based consumer-ordered semiconductor packaging can generate a substrate having a shape suitable for the purpose (for example, a shape that fits the internal free space of the product), and at the same time form interconnection structures of various patterns, thereby excluding the conventional separate interconnection process from the semiconductor packaging process and optimizing the process cost items.

[0008] In the case of a semiconductor substrate, it is also necessary to improve the material so as to lower the dielectric constant and CTE in accordance with the use of the semiconductor. To solve this problem, the above-mentioned problems can be improved by using polymers and oligomers combined with specific monomers.

[0009] The problems to be solved by the present invention are not limited to the problems mentioned above, and other problems not mentioned can be clearly understood by those having ordinary knowledge in the technical field to which the present invention belongs from the following description.

Means for Solving the Problems

[0010] According to various embodiments, a substrate for electrical connection between electronic components includes a body having a single-layer structure and at least one conductive interconnect formed inside the body. The at least one interconnect includes one side and the other side exposed to the outside of the body, and a line connecting the one side and the other side. The line traverses horizontally or vertically through the inside of the body having the single-layer structure and may be configured to have a specific curvature in some sections, and a substrate can be provided.

[0011] According to various embodiments, an electronic device includes a plurality of electronic components and a substrate including a body having a single-layer structure and at least one conductive interconnect formed inside the body. The at least one interconnect includes one side and the other side exposed to the outside of the body, and a line connecting the one side and the other side. The line traverses horizontally or vertically through the inside of the body having the single-layer structure and has a specific curvature in some sections. Among the plurality of electronic components, a first electronic component and the second electronic component are electrically connected by the at least one interconnect, and an electronic device can be provided.

[0012] According to various embodiments, the means for solving the problem is not limited to the above-described means, and the means not mentioned will be clearly understood by those having ordinary knowledge in the technical field to which the present invention belongs from this specification and the accompanying drawings.

Advantages of the Invention

[0013] According to various embodiments, an apparatus, a server, a system, a material, and an operating method thereof for 3D printing-based consumer order-made semiconductor packaging can simplify an interconnect process and reduce the cost of the interconnect process by forming an interconnect structure using 3D printing.

[0014] In particular, according to various embodiments, the oligomer containing the monomer represented by Chemical Formula 1 is composed of a polyimide component known to have a low dielectric constant and a low CTE for most of its structure. Therefore, it can have the dielectric constant value and CTE value for the above purpose, and has a structure with a very large number of (meth)acrylate functional groups per unit volume. When the (meth)acrylate functional group is sensitive to light, it is interconnected to form a very dense polymer network. Such a structure can reduce the thermal expansion rate and have the characteristic of having a low CTE value.

[0015] Furthermore, the oligomer containing the monomer represented by Chemical Formula 1 has a structure with a very large number of methacrylate functional groups per unit volume and extremely little free volume that is not sensitive to light. As a result, it can achieve a very high resolution (less than 10 μm) required for semiconductor packaging.

[0016] Also, according to various embodiments, the devices, servers, systems, materials, and their operating methods for 3D printing-based consumer-ordered semiconductor packaging can generate a substrate with a shape suitable for the purpose (e.g., suitable for the shape of the internal empty space of the product), and at the same time form various patterns of interconnect structures, thereby excluding the conventional separate interconnect process from the semiconductor packaging process and optimizing the process cost items.

Brief Description of the Drawings

[0017]

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Best Mode for Carrying Out the Invention

[0018] The electronic devices according to various embodiments disclosed in this specification can be devices in various forms. The electronic device can include, for example, a portable communication device (e.g., a smartphone), a computer device, a portable multimedia device, a portable medical device, a camera, a wearable device, or a home appliance device. The electronic devices according to the embodiments of this specification are not limited to the devices described above.

[0019] The various embodiments described herein and the terms used therein are not intended to limit the technical features described herein to specific embodiments, but should be understood to include various modifications, equivalents, or alternatives of such embodiments. With respect to the description of the drawings, similar reference numerals can be used for similar or related components. The singular form of a noun corresponding to an item can include one or more of the items unless clearly indicated otherwise in the relevant context. As used herein, each of the phrases "A or B," "at least one of A and B," "at least one of A or B," "A, B, or C," "at least one of A, B, and C," and "at least one of A, B, or C" can include any of the items listed together in the corresponding phrase of that phrase, or all possible combinations thereof. Terms such as "first," "second," "initial," or "second" can be used merely to distinguish one component from another corresponding component and do not limit the component in other aspects (e.g., importance or order). When a certain (e.g., first) component is referred to as "coupled" or "connected" to a different (e.g., second) component, with or without the terms "functionally" or "communicatively," it means that the certain component can be directly (e.g., wired), wirelessly, or via a third component connected to the other component.

[0020] The term "module" used in the various embodiments described herein can include units implemented in hardware, software, or firmware. For example, it can be used interchangeably with terms such as logic, logical block, component, or circuit. A module can be an integrally configured component or the smallest unit or a part of the component that executes one or more functions. For example, according to one embodiment, a module can be implemented in the form of an ASIC (application-specific integrated circuit).

[0021] Various embodiments of this specification can be realized as software (e.g., a program) including one or more instruction words stored in a storage medium (e.g., a built-in memory or an external memory) that can be read by a machine (e.g., an electronic device). For example, a processor (e.g., a processor) of a machine (e.g., an electronic device) can call and execute at least one of the one or more instruction words stored from the storage medium. This enables the machine to operate so as to execute at least one function by the at least one called instruction word. The one or more instruction words may include code generated by a compiler or code executable by an interpreter. The storage medium readable by the machine can be provided in the form of a non-transitory storage medium. Here, "non-transitory" only means that the storage medium is a tangible device and does not include a signal (e.g., an electromagnetic wave), and this term does not distinguish between the case where data is stored semi-permanently in the storage medium and the case where it is stored temporarily.

[0022] According to one embodiment, the methods according to various embodiments disclosed herein may be provided included in a computer program product. A computer program product can be traded as a commodity between a seller and a purchaser. The computer program product can be distributed in the form of a storage medium readable by a machine (e.g., a compact disc read only memory (CD-ROM)), or can be distributed online (e.g., downloaded or uploaded) directly between two user devices (e.g., smartphones) via an application store (e.g., the App Store (registered trademark)), or. In the case of online distribution, at least a part of the computer program product can be stored at least temporarily or generated temporarily in a storage medium readable by a machine such as the memory of a manufacturer's server, an application store's server, or a relay server.

[0023] According to various embodiments, each component of the above-described components (e.g., a module or a program) can include one or more individuals, and some of the plurality of individuals may be separately arranged from other components. According to various embodiments, one or more of the above-described components or operations can be omitted, or one or more other components or operations can be added. Alternatively or additionally, a plurality of components (e.g., a module or a program) can be integrated into one component. In this case, the integrated component can execute one or more functions of each of the plurality of components in the same or similar manner as those executed by the component among the plurality of components before integration. According to various embodiments, the operations executed by a module, a program, or other components are executed sequentially, in parallel, repeatedly, or heuristically, or one or more of the operations are executed in a different order, or omitted, or one or more other operations can be added.

[0024] According to various embodiments, there can be provided a substrate for electrical connection between electronic components, the substrate including a main body having a single-layer structure and at least one interconnect portion having conductivity formed inside the main body, the at least one interconnect portion including one side and the other side exposed to the outside of the main body and a line connecting the one side and the other side, the line configured to traverse horizontally or vertically through the inside of the main body having the single-layer structure and to have a specific curvature in some sections.

[0025] According to various embodiments, the at least one interconnect portion includes a first interconnect portion and a second interconnect portion, the specific inclination of the first interconnect portion being a first inclination, and the specific inclination of the second interconnect portion being a second inclination different from the first inclination, and there can be provided a substrate.

[0026] According to various embodiments, the body can provide a substrate configured to correspond to the shape of the empty space inside the electronic product where the substrate is disposed, based on a 3D printing process.

[0027] According to various embodiments, one side of the at least one interconnecting portion is connected to a first electronic component of the electronic device, and the other side is configured to be connected to a second electronic component of the electronic device, and a substrate can be provided.

[0028] According to various embodiments, the at least one interconnecting portion includes a plurality of conductive members, and a first density of the plurality of conductive members in a first region adjacent to the first electronic component of the substrate is configured to be different from a second density of the plurality of conductive members in a second region adjacent to the second electronic component of the substrate, and a substrate can be provided.

[0029] According to various embodiments, the body can provide a substrate configured to include at least one other structure and / or at least one member in a portion other than the portion where the at least one interconnecting portion is disposed.

[0030] According to various embodiments, the at least one structure can include an empty space structure for releasing heat generated from the substrate, and a substrate can be provided.

[0031] According to various embodiments, the substrate can be provided to be connected to an additional structure including at least one other interconnecting portion.

[0032] According to various embodiments, a density of the at least one interconnecting portion of the substrate can be configured to be lower than a density of the at least one other interconnecting portion of the additional structure, and a substrate can be provided.

[0033] According to various embodiments, the substrate and the additional substrate can be provided such that the substrate and the additional substrate are connected in a manner that they are joined to each other, or the substrate and the additional substrate are connected such that the additional substrate is laminated on the substrate.

[0034] According to various embodiments, there is provided an electronic device including a plurality of electronic components, and a substrate including a single-layer body and at least one conductive interconnect formed inside the body, wherein the at least one interconnect includes one side and the other side exposed to the outside of the body, and a line connecting the one side and the other side, the line traversing horizontally or vertically through the inside of the single-layer body and having a specific curvature in some sections, and among the plurality of electronic components, a first electronic component and the second electronic component can be provided to be electrically connected by the at least one interconnect.

[0035] According to various embodiments, the at least one interconnect includes a first interconnect and a second interconnect, the specific inclination of the first interconnect is a first inclination, and the specific inclination of the second interconnect is a second inclination different from the first inclination, and an electronic device can be provided.

[0036] According to various embodiments, an electronic device can be provided, wherein the body is configured to correspond to the shape of the empty space inside the electronic product on which the substrate is disposed based on a 3D printing process.

[0037] According to various embodiments, an electronic device can be provided, wherein one side of the at least one interconnect is connected to a first electronic component of the electronic device, and the other side is configured to be connected to a second electronic component of the electronic device.

[0038] According to various embodiments, the at least one interconnect portion includes a plurality of conductive members, and a first density of the plurality of conductive members in a first region adjacent to the first electronic component of the substrate is configured to be different from a second density of the plurality of conductive members in a second region adjacent to the second electronic component of the substrate, and an electronic device can be provided.

[0039] According to various embodiments, there is provided a substrate material for electrical connection between electronic components, including a first composition containing an oligomer containing a monomer represented by the following Chemical Formula 1, a compound containing at least two acrylate functional groups, and a photoinitiator, or a cured product thereof.

[0040] [Chemical Formula 1] In Chemical Formula 1 above, R1 to R4 are the same as or different from each other, and are each independently a substituted or unsubstituted C1 to C40 alkyl group, Ar1 and Ar2 are the same as or different from each other, and are each independently a substituent containing a (meth)acrylate functional group, n1 is an integer of 1 or more and 50 or less.

[0041] According to various embodiments, there is provided a substrate material for electrical connection between electronic components, in which a weight ratio of the oligomer containing the monomer represented by Chemical Formula 1 to the compound containing at least two acrylate functional groups is 40:30 to 75:10.

[0042] According to various embodiments, R1 to R4 are the same as or different from each other, and are each independently a C1 to C10 alkyl group substituted or unsubstituted with a halogen group, and Ar1 and Ar2 are the same as or different from each other, and are each independently a substituent containing a (meth)acrylate and a hydroxy group as functional groups, and a substrate material for electrical connection between electronic components is provided.

[0043] According to various embodiments, there is provided a material for a substrate for electrical connection between electronic components, further comprising a second composition containing an oligomer containing a monomer represented by the following chemical formula 2, a compound containing at least two acrylate functional groups, and a photoinitiator, or a cured product thereof.

[0044] [Chemical formula 2] JPEG2025088784000003.jpg22170In the above chemical formula 2, n2 and n3 are integers from 30 to 60, n4 is an integer from 3 to 100.

[0045] According to various embodiments, the photoinitiator is one or more selected from the group consisting of triazine compounds, biimidazole compounds, acetophenone compounds, O-acyl oxime compounds, thioxanthone compounds, phosphine oxide compounds, coumarin compounds, and benzophenone compounds, providing a material for a substrate for electrical connection between electronic components.

[0046] According to various embodiments, the weight ratio of the oligomer containing the monomer represented by the chemical formula 2 to the compound containing at least two acrylate functional groups is 5:60 to 20:40, providing a material for a substrate for electrical connection between electronic components.

[0047] According to various embodiments, the oligomer containing the monomer represented by the chemical formula 1 has the following structural formula, providing a material for a substrate for electrical connection between electronic components. JPEG2025088784000004.jpg53170In the above structural formula, the definition of a1 is the same as that in the chemical formula 1.

[0048] According to various embodiments, the oligomer containing the monomer represented by the chemical formula 2 has the following structural formula, providing a material for a substrate for electrical connection between electronic components. JPEG2025088784000005.jpg26170In the above structural formula, the definitions of n2 to n4 are the same as those in the chemical formula 2.

[0049] According to various embodiments, the cured product of the first composition has a dielectric constant of 2.5 to 3.0 and a coefficient of thermal expansion (CTE) of 10 ppm K -1 or more and 20 ppm K -1 and provides a substrate material for electrical connection between electronic components having a resolution in the order of μm according to a three-dimensional printing process.

[0050] According to various embodiments, the cured product of the second composition has a dielectric constant of 3.3 to 3.6 and a coefficient of thermal expansion (CTE) of 5 ppm K -1 or more and 10 ppm K -1 and provides a substrate material for electrical connection between electronic components having a resolution in the order of μm according to a three-dimensional printing process.

[0051] According to various embodiments, there is provided a substrate for electrical connection between electronic components, including the substrate material for electrical connection between electronic components described above.

[0052] According to various embodiments, when the first composition and the second composition are cured: a substrate material can be provided, with a surface roughness realized to be 0.5 μm or less.

[0053] According to various embodiments, when holes are formed in a substrate formed based on the curing of the at least one monomer, a substrate material can be provided, with the inner surface roughness of the holes realized to be 0.5 μm or less.

[0054] According to various embodiments, as an operation method of a server, an operation of receiving a first file for a drawing of a semiconductor packaging substrate from each of a plurality of electronic devices of a plurality of different users, an operation of obtaining a second file for a 3D printing process based on the received first file, and an operation of providing at least one control signal for generating the substrate corresponding to the second file with at least one 3D printer based on the second file, wherein the substrate is configured to include at least one conductive member different for each of the first files, an operation method can be provided.

[0055] According to various embodiments, the operation of obtaining the second file can provide an operation method including an operation of adjusting the size of the substrate in the first file.

[0056] According to various embodiments, the operation of adjusting the size of the substrate includes an operation of comparing the actual size of the generated substrate with the size of the substrate in the drawing file and / or the printing file, and an operation of adjusting the size of the substrate based on the difference value, and an operation method can be provided.

[0057] According to various embodiments, as a process method, a step of providing a substrate including at least one interconnected structure generated based on 3D printing inside, and a step of hydrophilizing the surface of at least one interconnected structure inside the substrate, a step of providing a fluid metal on the hydrophilized surface of the at least one interconnected structure inside the substrate, and a step of growing a metal on the interconnect based on the fluid metal, a process method can be provided.

[0058] According to various embodiments, as a semiconductor packaging module, a single first semiconductor chip, a first surface facing the lower surface of the first semiconductor chip, a second surface opposite to the first surface, and a substrate including at least one first conductive member inside between the first surface and the second surface, are provided. The at least one first conductive member includes a first portion exposed through the first surface, a second portion exposed through the second surface, and a line connecting between the first portion and the second portion. The first portion is electrically connected to the first semiconductor chip, the second portion is configured to be electrically connectable to other electronic components, and the line is configured to cross the main body of the single-layer structure and have a specific inclination in at least a part of the section. A semiconductor packaging module can be provided.

[0059] According to various embodiments, as an antenna packaging module, a plurality of antennas, a first surface and a second surface having different inclinations respectively, at least one first conductive member exposed through the first surface, and a substrate including at least one second conductive member exposed through the second surface are included. The first surface and the second surface face different directions respectively. The at least one first conductive member is electrically connected to a first antenna group arranged on the first surface among the plurality of antennas, and the at least one second conductive member is electrically connected to a second antenna group arranged on the second surface among the plurality of antennas. An antenna packaging module can be provided.

[0060] 1. Customized 3D Printing System The customized 3D printing system 1 according to various embodiments may be a system configured to manufacture products adapted to various types of devices (or equipment) required by consumers in an optimized (or efficiency - enhanced) process based on 3D printing technology.

[0061] For example, the made-to-order type 3D printing system 1 can be configured to generate a packaging structure including an ultra-fine interconnect structure (or a metal wire structure, or a pipeline structure, or a conductive member) for a semiconductor chip (e.g., a processor, an antenna chip, etc.). The ultra-fine interconnect structure may be formed to be compatible with various types of devices based on 3D printing. The made-to-order type 3D printing system 1 can reduce the operation burden of the packaging process for realizing a high-performance semiconductor provided for each electronic device based on 3D printing technology.

[0062] Also, for example, the made-to-order type 3D printing system 1 can be configured to manufacture a structure having a shape corresponding to the shape of a narrow internal space within an electronic device and providing electrical connection between other electronic components. For example, the structure for providing the electrical connection can include a socket.

[0063] In addition to the described examples, the made-to-order type 3D printing system 1 can provide a service for manufacturing products corresponding to various types of electronic devices (or various consumer needs) based on an optimal process.

[0064] Hereinafter, for the sake of convenience of explanation, the made-to-order type 3D printing system 1 that provides a manufacturing service for a packaging structure will be described as an example. However, it is obvious to those skilled in the art that the various described embodiments can be applied mutatis mutandis to the made-to-order type 3D printing system 1 for manufacturing other various structures.

[0065] 2. Components of the Made-to-Order Type 3D Printing System Hereinafter, examples of the components of the above-described made-to-order type 3D printing system 1 according to various embodiments will be described.

[0066] FIG. 1 is a diagram showing an example of components of the made-to-order printing system 1 according to various embodiments. Hereinafter, with reference to FIG. 2, FIG. 1 will be further described.

[0067] FIG. 2 is a diagram for explaining an example of an application product of a structure manufactured by the made-to-order printing system 1 according to various embodiments.

[0068] According to various embodiments, referring to FIG. 1, the made-to-order 3D printing system 1 can include a server 10, a packaging device 20, and a user device 30. On the other hand, without being limited to the described and / or illustrated examples, the made-to-order 3D printing system 1 may be configured to include more components and / or even fewer components. For example, without implementing the server 10, the packaging device 20 may be configured to execute all functions of the server 10. Also, the server 10 may be provided in a form connected to the packaging device 20 as an add-on device.

[0069] According to various embodiments, the server 10 is at least one electronic device of an administrator for providing a manufacturing service for a packaging structure, and may be configured to manage the entire structure manufacturing service. For example, the server 10 can receive information from the consumer's user device 30 and / or transmit information to the user device 30. As an example, the server 10 can receive a drawing file for the structure to be manufactured from the user device 30. Also, as an example, the server 10 can transmit information about the structure manufactured by the packaging device 20 to the user device 30. Also, for example, the server 10 can control the packaging device 20. As an example, the server 10 can convert the drawing file received from the user device 30 into a print file, and by controlling the packaging device 20 based on the print file, the packaging device 20 can manufacture a packaging structure.

[0070] According to various embodiments, the packaging device 20 can include at least one device (or facility) for manufacturing a packaging structure 100 including a fine interconnection structure and connecting the packaging structure to at least one semiconductor chip (or at least one electronic component), as shown in FIG. 2. Details of the packaging device 20 will be described more specifically later with reference to FIGS. 6 to 7. Referring to FIG. 2, the packaging structure 100 can be configured to be provided in various types of devices 201, 202, 203, 204, 205 based on 3D printing technology.

[0071] According to various embodiments, the user device 30 can be a device of a consumer who requests a manufacturing service for a packaging structure. The user device 30 can be various types of electronic devices available to a consumer (or user), such as at least one PC, tablet, smartphone, HMD (head mounted display) device, etc. The user device 30 can acquire a drawing file generated by a consumer and transmit it to the server 10 as described above.

[0072] 2.1 Details by Component Hereinafter, examples of the components of the above-described made-to-order type 3D printing system 1 according to various embodiments will be further described.

[0073] 2.1.1 Server 10 and User Device 30 FIG. 3 is a diagram for explaining a configuration example of the server 10 and the user device 20 according to various embodiments. Hereinafter, FIG. 3 will be described with reference to FIGS. 4 to 5.

[0074] FIG. 4 is a diagram for explaining an example of a design program 361 according to various embodiments. FIG. 5 is a diagram for explaining an example of a conversion program 331 according to various embodiments.

[0075] According to various embodiments, referring to FIG. 3, server 10 includes a first processor 310, a first communication circuit 320, and a first memory 330 that stores a conversion program 331. User device 30 can include a second processor 340, a second communication circuit 350, and a second memory 360 that stores a design program 361. On the other hand, without being limited to the described and / or illustrated examples, server 10 and / or user device 30 may be configured to include more devices and / or further include fewer devices. For example, server 10 and / or user device 30 can further include a speaker (not shown), a microphone (not shown), a touch screen (not shown), a display (not shown), etc.

[0076] According to various embodiments, first processor 310 and second processor 340 can execute software (or computer code, or program, or instructions, or modules) to control at least one other component (e.g., a hardware or software component) connected to first processor 310 and second processor 340, and may be configured to perform various data processing or operations. According to one embodiment, as at least part of the data processing or operation, first processor 310 and second processor 340 can load instructions or data received from other components into volatile memory, process the instructions or data stored in the volatile memory, and store the resulting data in non-volatile memory. According to one embodiment, first processor 310 and second processor 340 can include a main processor (e.g., a central processing unit or an application processor) and an auxiliary processor (e.g., a graphics processing unit, an image signal processor, a sensor hub processor, or a communication processor) that can operate independently of or together with it. Additionally or alternatively, the auxiliary processor can be configured to use less power than the main processor or to be specialized for a specified function. The auxiliary processor can be configured separately from or as part of the main processor.

[0077] According to various embodiments, the first communication circuit 320 and the second communication circuit 330 can assist in establishing a wireless communication channel between devices and performing communication via the established communication channel. The communication circuit (e.g., the first communication circuit 320 and / or the second communication circuit 330) may be operated independently of the processor (e.g., the first processor 310 and / or the second processor 340) and may be configured to include one or more communication processors that assist in wireless communication, but is not limited to the described examples.

[0078] According to various embodiments, the first memory 330 and the second memory 360 can store various data used by at least one component of the server 10 and the user device 20 (e.g., the first processor 310 and the second processor 340). For example, the first memory 330 may be configured to store the conversion program 331, and the second memory 360 may be configured to store the design program 361. Based on the execution of the programs (e.g., the conversion program 331 and the design program 361) by the above-described processors (e.g., the first processor 310 and the second processor 340), the server 10 and the user device 30 can provide functions corresponding to the programs for their respective devices (e.g., the server 10 and the user device 20).

[0079] According to various embodiments, the design program 361 can be configured to generate a drawing file for a packaging structure. As an example, the drawing file may be a CAD file including the design of the packaging structure, but is not limited to the described example and can have various types of formats for including the design of a three-dimensional structure for the design of the structure. For example, as shown in FIG. 4, the design program 361 can be configured to provide a function enabling both chip design and package design. For example, conventionally, a chip design program for chip design and a package design program for package design have been separately realized, so that each of the chip and the package cannot be designed in a form considering each other, resulting in a resource burden for design. The design program 361 according to various embodiments may be configured to provide an integrated interface for integrated design of a chip and a packaging structure, integrated rules (or integrated parameters) for chip and package design, and an integrated tool. The integrated interface can mean a graphic user interface for a consumer (or user) to draw a chip and a package using an integrated tool (such as a drawing tool). The integrated rules (or integrated parameters) can mean physical characteristics, material characteristics, and electrical characteristics such as size, which are applied to a chip and a packaging designed based on the design program 361. For example, the design program 361 may be configured to generate a mask drawing file for a chip and a 3D drawing file for a packaging structure. The consumer can use the design program installed in the user device 30 to design a chip and a packaging structure corresponding to the chip on the integrated interface based on the integrated rules. Thereby, as the design considering each of the chip and the package becomes possible, the resources for design are reduced, the connectivity (for example, electrical connectivity, physical connectivity) between the manufactured chip and the manufactured packaging structure is improved, and high-quality semiconductor packaging can be executed.

[0080] According to various embodiments, the conversion program 331 can be configured to generate a print file corresponding to a drawing file. As an example, the print file may be an STL file including the design of a packaging structure, but is not limited to the described example and can be a file having various types of formats for 3D printing. Based on the print file, the packaging device 20 described below can manufacture a packaging structure. Referring to FIG. 5, according to one embodiment, the conversion program 331 can be configured to generate a print file including a plurality of packaging structures 403 based on the packaging structure 401 included in the drawing file. At this time, the conversion program 331 can be configured to determine the number of the plurality of packaging structures included in the print file based on the number of packaging structures required by the consumer. Thereby, the productivity of the packaging structure 100 manufactured during the process execution of the packaging device 20 is improved, and thus, it can be executed in an optimal process for the production requirement quantity of the consumer, and the process operation burden can be reduced.

[0081] According to various embodiments, the conversion program 331 can generate a print file corresponding to a packaging structure including at least one through structure (or hole structure) based on a packaging structure including an interconnect portion included in the drawing file. That is, the conversion program 331 can generate a print file for the outer shape of the structure excluding the interconnect portion of the metal material. This is by the 3D printing device 610 described below.

[0082] On the other hand, without being limited to the described and / or illustrated examples, the above-described conversion program 331 is stored in the user device 30, and the print file converted by the user device 30 is provided to the server 10, or the design program 361 is stored in the server 10, and the user device 30 connects to the server 10 to utilize the design program 361, and the made-to-order type 3D printing system 1 can also be realized.

[0083] 2.1.1 Packaging Device 20 FIG. 6 is a diagram for explaining an example of the configuration of the package device 20 according to various embodiments. Hereinafter, FIG. 6 will be further described with reference to FIG. 7.

[0084] FIG. 7 is a diagram for explaining a configuration example of the packaging device 20 according to various embodiments.

[0085] According to various embodiments, referring to FIG. 6, the packaging device 20 can include a printing device 610, a metallization process device 620, a bump generation device 630, a bonding device 640, and a test analysis device 650 for generating a packaging structure. Referring to FIG. 7, the devices (or facilities) of the packaging device 20 described above may be provided in a form that enables continuous processes with each other. For example, it may be implemented in a form in which each device is connected step by step based on at least one trailer, and the processes for the packaging structure moving on the trailer can be executed by the above-described devices 610, 620, 630, 640, 650. The packaging structure may mean at least one of a substrate (or dielectric layer) generated by the printing device 610, a substrate including an interconnect generated by the metallization process device 620, a substrate with bumps formed by the bump generation device 630, or a substrate physically connected to other electronic components (for example, chips and / or packaging substrates) and other electronic components by the bonding device 640. On the other hand, without being limited to the described and / or illustrated examples, the packaging device 20 can be configured to include more devices (or facilities) or even fewer devices (or facilities). For example, the packaging device 20 may be configured to include only the 3D printing device 610 and the metallization process device 620 and be configured to generate a structure (or substrate) including various types of fine interconnects, but is not limited to the described example.

[0086] According to various embodiments, the 3D printing device 610 can be configured to form a substrate including at least one empty space structure (or hole structure) based on a 3D printing process and a printing file. The 3D printing device can be implemented by a device that executes a 3D printing process based on at least one of a material extrusion type method such as FDM (fused deposition modeling) or FFF (fused filament fabrication), a photopolymerization type method such as SLA (stereolithography), DLP (digital light processing), CLIP (continuous liquid interface production technology), LCD (liquid crystal display), and PuSL (projection micro streolithopraphy), a powder sintering method such as SLS (stereolithography), SLM (selective laser melting), DMLS (direct metal laser sintering), and MJP (multi-jet printing), a binder injection method such as CJP (color jet printer) or IJP (ink jet printer), a Sheet Lamination method such as LOM (laminated object manufacturing), SDL (selective deposition lamination), and VLM (viscous lithography manufacturing), or a directed energy deposition method such as DMT (laser-aided direct metal tooling), LMD (laser metal deposition), and LENS (laser engineered net shaping). Since the 3D printing method is a well-known technology, a specific description thereof will be omitted.Therefore, the material of the substrate generated by the 3D printing device 610 may select at least one of a photo (e.g., ultraviolet ray, infrared ray, visible light) curable material or a thermosetting material based on the above-described 3D printing method.

[0087] According to various embodiments, the 3D printing device 610 may be configured to generate a substrate with a resolution (or resolution) in the unit of μm. The resolution may include, but is not limited to, 2 μm, 10 μm, and 25 μm.

[0088] According to various embodiments, the metallization process device 620 may be configured to generate at least one interconnect (or at least one metal wire) inside the substrate generated by the 3D printing device 610. For example, as shown in FIG. 7, the metallization process device 620 may fill and grow (or fill with metal) a conductive material (e.g., metal) in at least one through structure inside the substrate.

[0089] According to various embodiments, the bump generation device 630 may generate bumps on the surface of the substrate for electrical connection with other electronic components (e.g., chip packaging substrate, etc.). The types of the bumps may include at least one of a copper material pillar and a lead material bump (Cu pillar + Solder bump) disposed on the pillar, a stud-shaped lead material bump, or a ball-shaped lead material bump, but are not limited to the described examples, and bumps can be formed with various materials and various shapes. Since it is a well-known technology, specific descriptions are omitted. On the other hand, the bump generation device 630 may form UBM (under bump metallurgy) on the portion where the interconnect is exposed before bump formation.

[0090] According to various embodiments, the bonding device 640 can physically connect a substrate on which bumps are formed to other electronic components (e.g., a chip packaging substrate, etc.). Since this is a well-known technique, specific description thereof will be omitted.

[0091] According to various embodiments, the test and analysis device 650 can be configured to perform test and analysis on the packaging structure generated by the packaging device 20. The types of the test and analysis can include electromagnetic simulation, thermal durability, pulse response, interconnectivity test and analysis using optical non-destructive inspection, etc., and test and analysis for detecting process intermittent defects.

[0092] 3. Process Hereinafter, an example of a process based on the packaging device 20 according to various embodiments will be described.

[0093] FIG. 8 is a flowchart showing an example of a process according to various embodiments. Operations can be executed regardless of the order of operations shown and / or described, and more operations can be executed and / or fewer operations can be executed. Hereinafter, with reference to FIG. 9, FIG. 8 will be further described.

[0094] FIG. 9 is a diagram for explaining examples of a substrate generation process, a metallization process, a bump formation process, and a bonding process according to various embodiments.

[0095] According to various embodiments, a packaging device 20 (e.g., a 3D printing device 610) can form a 3DP (3D printing)-based substrate in operation 801. For example, the packaging device 20 can form a substrate including at least one internal structure based on 3DP. For example, the at least one internal structure can include a through structure. As shown in 901 of FIG. 9, the packaging device 20 (e.g., the 3D printing device 610) can generate a substrate 911 having at least one through structure 913 formed therein corresponding to a print file based on 3D printing. At this time, based on 3DP, the substrate 911 is formed in a shape that conforms to consumer needs (or conforms to various types of electronic devices), so that the space inside the electronic device can be optimized and the quality of the form factor of the electronic device can be improved.

[0096] Also, for example, the packaging device 20 can form a substrate including at least one external structure based on 3DP.

[0097] According to various embodiments, a packaging device 20 (e.g., a metallization process device 620) can perform a metallization process in operation 803. For example, as shown in 903 of FIG. 9, the packaging device 20 (e.g., the metallization process device 620) can form at least one interconnect portion 931 (or metal wire) inside the substrate 911 by metallizing at least one through structure 913 inside the substrate 911.

[0098] According to various embodiments, a packaging device 20 (e.g., a bump generation device 630) can perform a metallization process in operation 805. For example, as shown in 905 of FIG. 9, the packaging device 20 (e.g., the bump generation device 630) can form bumps 951 on the substrate 911. Each bump 951 is formed at a portion of at least one interconnect portion 931 exposed on the outer surface of the substrate 911 and can be electrically connected.

[0099] According to various embodiments, the packaging device 20 (e.g., bonding device 640) can execute a bonding process in operation 807. For example, as shown in 907 of FIG. 9, the packaging device 20 (e.g., bonding device 640) can physically connect the bumps 951 formed on the substrate 911 and at least one other electronic component (e.g., chip 973) to electrically connect the substrate 911 and at least one other electronic component (e.g., chip 973). Based on at least one interconnect 931 formed inside the substrate 911, an electrical connection can be formed between the electronic components physically (or electrically) connected to the substrate 911. At this time, since the interconnect 931 can be realized in various forms by the above-described 3DP substrate forming process 801, compared with members for conventional packaging (e.g., redistribution layer (RDL), through silicon via (TSV)), etc., it is formed with a simpler and more efficient electrical connection structure without a complex electrical connection structure, so that the product quality can be improved and the electrical energy loss can also be reduced.

[0100] According to various embodiments, the semiconductor packaging process can be simplified based on the above-described steps 801, 803, 805, 807. For example, the process for forming an existing interconnect structure (e.g., a redistribution layer (RDL), a through silicon via (TSV)) can include forming a dielectric layer (e.g., a substrate), a photomask process (hole formation process), filling with a conductive material, forming a metal seed layer, forming a photoresist, forming a rewiring layer, and etching. The packaging apparatus 20 according to various embodiments can reduce the process steps and streamline the packaging process by performing only a single step of forming a 3DP-based substrate (801) instead of a multi-step process of forming holes based on a photomask after forming the dielectric layer. Also, the packaging apparatus 20 can reduce the process steps and streamline the packaging process by performing a microfluidic metal-based metallization process on a substrate (801) with a photo-through structure instead of a multi-step process including forming a metal seed layer, forming a photoresist, forming a rewiring layer, and etching.

[0101] Hereinafter, examples of each process according to various embodiments will be specifically described.

[0102] 3.1 3DP-based Substrate 911 Formation Process 3.1.1 Substrate 911 Formation Process and Materials of Substrate 911 FIG. 10a is a flowchart showing an example of the process for forming a 3DP-based substrate 911 according to various embodiments. Operations can be performed regardless of the order of operations shown and / or described, and more operations can be performed and / or fewer operations can be performed. Hereinafter, FIG. 10 will be further described with reference to FIG. 11.

[0103] FIG. 10b is a diagram for explaining an example of the material of a substrate including Chemical Formula 1 according to various embodiments. FIG. 10c is a diagram for explaining an example of the material of a substrate including Chemical Formula 2 according to various embodiments.

[0104] According to various embodiments, in operation 1001, a packaging device 20 (e.g., a 3D printing device 610) can provide a material for generating a substrate 911 (or a dielectric layer).

[0105] According to various embodiments, the material can be a material having at least one of the characteristics processable based on 3D printing or the characteristics for semiconductor packaging. The material can be configured to have at least one of the characteristics processable or the characteristics for semiconductor packaging, which will be exemplarily described below.

[0106] For example, as the processable characteristic, the material can have a curable characteristic based on various types of 3D printing methods described above. As an example, the material can have a thermosetting and / or photocuring characteristic.

[0107] The material will be described more specifically below.

[0108] According to various embodiments, the term "substituted" means that a hydrogen atom bonded to a carbon atom of a compound is replaced by another substituent, and the position to be substituted is not limited to the position where a hydrogen atom is substituted, that is, the position where a substituent can be substituted. When two or more substitutions occur, the two or more substituents may be the same or different from each other.

[0109] As used herein, "substituted or unsubstituted" means substituted or unsubstituted with one or more substituents selected from the group consisting of deuterium; a halogen group; a cyano group; a C1-C60 alkyl group; a C2-C60 alkenyl group; a C2-C60 alkynyl group; a C3-C60 cycloalkyl group; a C2-C60 heterocycloalkyl group; a C6-C60 aryl group; a C2-C60 heteroaryl group; a silyl group; a phosphine oxide group; and an amine group, or a substituent in which two or more substituents selected from the exemplified substituents are linked.

[0110] 3.1.1.1 First Composition or Its Cured Product According to various embodiments, the substrate material has a first composition or its cured product, which includes an oligomer containing a monomer represented by the following Chemical Formula 1, a compound containing at least two acrylate functional groups, and a photoinitiator.

[0111] [Chemical Formula 1] JPEG2025088784000006.jpg42170At this time, the first composition can be included as it is or its cured product can be included, and the cured product of the first composition can be a photosensitive polyimide photocuring resin.

[0112] According to various embodiments, R1 to R4 may be the same as or different from each other, and each may independently be a substituted or unsubstituted C1 - C40 alkyl group.

[0113] According to various embodiments, R1 to R4 may be the same as or different from each other, and each may independently be a substituted or unsubstituted C1 - C30 alkyl group.

[0114] According to various embodiments, R1 to R4 may be the same as or different from each other, and each may independently be a substituted or unsubstituted C1 - C10 alkyl group.

[0115] According to various embodiments, R1 to R4 may be the same as or different from each other, and each may independently be a C1 - C10 alkyl group substituted or unsubstituted with a halogen group.

[0116] According to various embodiments, R1 to R4 may be the same as or different from each other, and each may independently be a linear C1 - C10 alkyl group substituted or unsubstituted with a halogen group.

[0117] According to various embodiments, R1 to R4 may be the same as or different from each other, and each may independently be a trifluoromethyl group.

[0118] According to various embodiments, R1 to R4 may be the same as each other.

[0119] According to various embodiments, Ar1 and Ar2 may be the same as or different from each other, and each may independently be a substituent containing a (meth)acrylate functional group.

[0120] As used herein, (meth)acrylate means including both acrylate and methacrylate. The (meth)acrylate resin may be, for example, a copolymer of a (meth)acrylic acid ester monomer and a monomer containing a crosslinkable functional group.

[0121] According to various embodiments, Ar1 and Ar2 may be the same as or different from each other, and each may independently be a substituent containing a (meth)acrylate functional group, and can be represented by the following structural formula. JPEG2025088784000007.jpg57170JPEG2025088784000008.jpg18170

[0122] According to various embodiments, the oligomer containing the monomer represented by Chemical Formula 1 is composed of a polyimide component known to have a low dielectric constant and a low CTE in most of its structure, and can have the above-described desired dielectric constant value and CTE value. In a structure where the number of (meth)acrylate functional groups per unit volume is very large, when the (meth)acrylate functional group is sensitive to light, they are interconnected to form a very dense polymer network. Such a structure has the characteristic that the expansion rate due to heat is low and a low CTE value can be achieved.

[0123] Furthermore, the oligomer containing the monomer represented by Chemical Formula 1 has a structure where the number of methacrylate functional groups per unit volume is very large, and the free volume that is not sensitive to light is extremely small, whereby a very high resolution (less than 10 μm) required for semiconductor packaging can be achieved.

[0124] In various embodiments, the compound containing at least two acrylate functional groups can be trimethylolpropane triacrylate.

[0125] The compound containing at least two acrylate functional groups helps to further deepen the connectivity between the monomers of Formula 1 and can have a low CTE value, and plays a role in assisting the monomers of Formula 1 in the solid state to dissolve into a solution state that enables 3D printing.

[0126] In various embodiments, the photoinitiator can be one or more substituents selected from the group consisting of triazine-based compounds, biimidazole compounds, acetophenone-based compounds, O-acryloxime-based compounds, thioxanthone-based compounds, phosphine oxide-based compounds, coumarin-based compounds, and benzophenone-based compounds.

[0127] Specifically, as the photoinitiator, triazine compounds such as 2,4-trichloromethyl-(4'-methoxyphenyl)-6-triazine, 2,4-trichloromethyl-(4'-methoxystyryl)-6-triazine, 2,4-trichloromethyl-(fipronil)-6-triazine, 2,4-trichloromethyl-(3',4'-dimethoxyphenyl)-6-triazine, 3-{4-[2,4-bis(trichloromethyl)-s-triazin-6-yl]phenylthio}propanoic acid, 2,4-trichloromethyl-(4'-ethylbiphenyl)-6-triazine or 2,4-trichloromethyl-(4'-methylbiphenyl)-6-triazine; biimidazole compounds such as 2,2'-bis(2-chlorophenyl)-4,4',5,5'-tetraphenylbiimidazole or 2,2'-bis(2,3-dichlorophenyl)-4,4',5,5'-tetraphenylbiimidazole; acetophenone compounds such as 2-hydroxy-2-methyl-1-phenylpropan-1-one, 1-(4-isopropylphenyl)-2-hydroxy-2-methylpropan-1-one, 4-(2-hydroxyethoxy)-phenyl(2-hydroxy)propyl ketone, 1-hydroxycyclohexyl phenyl ketone, 2,2-dimethoxy-2-phenylacetophenone, 2-methyl-(4-methylthiophenyl)-2-morpholino-1-propan-1-one (Irgacure-907) or 2-benzyl-2-dimethylamino-1-(4-morpholinophenyl)-butan-1-one (Irgacure-369); O-acyl oxime compounds such as Irgacure OXE 01 and Irgacure OXE 02 from Ciba Geigy; benzophenone compounds such as 4,4'-bis(dimethylamino)benzophenone or 4,4'-bis(diethylamino)benzophenone; thioxanthone compounds such as 2,4-diethylthioxanthone, 2-chlorothioxanthone, isopropylthioxanthone or diisopropylthioxanthone; phosphine oxide compounds such as 2,4,6-trimethylbenzoyldiphenylphosphine oxide, bis(2,6-dimethoxybenzoyl)-2,4,4-trimethylpentylphosphine oxide or bis(2,6-dichlorobenzoyl)propylphosphine oxide;Coumarin compounds such as 3,3'-carbonylvinyl-7-(diethylamino)coumarin, 3-(2-benzothiazolyl)-7-(diethylamino)coumarin, 3-benzoyl-7-(diethylamino)coumarin, 3-benzoyl-7-methoxy-coumarin or 10,10'-carbonylbis[1,1,7,7-tetramethyl-2,3,6,7-tetrahydro-1H,5H,11H-Cl]-benzopyrano[6,7,8-ij]-quinolizin-11-one can be used alone or in combination of two or more, but not limited thereto.;

[0128] Specifically, the photoinitiator can be 2-hydroxy-2-methylpropiophenone.

[0129] In various embodiments, the weight ratio of the oligomer containing the monomer represented by Chemical Formula 1 to the compound containing at least two acrylate functional groups can satisfy a ratio of 40:30 to 75:10, specifically 50:20 to 65:5.

[0130] Including the above range, the CTE and dielectric constant of the substrate to be included later are compatible and can have a resolution in the unit of μm according to the three-dimensional printing process.

[0131] At this time, the cured product of the first composition has a dielectric constant of 2.5 to 3.0 and a coefficient of thermal expansion (CTE) of 10 ppm K -1 above 20 ppm K -1 and can have a resolution in the unit of μm according to the three-dimensional printing process.

[0132] Hereinafter, a production example of producing a photosensitive polyimide photocurable resin by curing the first composition will be described.

[0133] <Production Example> 1) Production of an oligomer containing the monomer represented by Chemical Formula 1 4 g of 2,2’-bis(3-amino-4-hydroxyphenyl)hexafluoropropane dissolved in 25 mL of methylpyrrolidone was gradually added with 4.041 g of 2,2’-bis(3,4-dicarboxy-phenyl)hexafluoropropane dianhydride at 0 °C under an argon atmosphere.

[0134] After stirring the mixture at 0 °C for 6 hours, 0.357 g of maleic anhydride was added and stirred for an additional 1 hour to obtain a light brown solution.

[0135] The temperature was raised to 60 °C and held for 2 hours, then raised to 110 °C and held for 2 hours, and finally raised to 205 °C and held for 4 hours to form a polyimide oligomer.

[0136] After cooling to 30 °C, 3.093 g of glycidyl methacrylate, 30 mg of triethylamine, 50 mg of tetraethylammonium bromide, and 50 mg of hydroquinone were added to the resulting solution and stirred at 100 °C for 4 hours.

[0137] After cooling to room temperature, the solution was poured into 100 mL of distilled water for precipitation. After filtering the precipitated powder, it was dried in vacuo at 40 °C for 12 hours or more to obtain an oligomer containing the monomer represented by Chemical Formula 1. JPEG2025088784000009.jpg54170

[0138] 2) Production of photocurable resin by curing The oligomer containing the monomer represented by Chemical Formula 1 prepared above, trimethylolpropane triacrylate, and methylpyrrolidone were mixed at a weight ratio of 60:10:30, and then 2 wt% of 2-hydroxy-2-methylpropiophenone was added to the mixture.

[0139] At this time, the weight ratio of monomer A to monomer B can be positioned between 50:20 and 65:5.

[0140] 3.1.1.2 Second composition or its cured product According to various embodiments, there is provided a substrate material for electrical connection between electronic components, further comprising a second composition containing an oligomer containing a monomer represented by the following chemical formula 2, a compound containing at least two acrylate functional groups, and a photoinitiator, or a cured product thereof.

[0141] [Chemical formula 2] JPEG2025088784000010.jpg26170 In various embodiments, the oligomer containing the monomer represented by the chemical formula 2 may have the following structural formula.

[0142] JPEG2025088784000011.jpg24170 In the above structural formula, the definitions of n2 to n4 are the same as those in the chemical formula 2.

[0143] When curing the second composition of the present application, the cured product may be a POSS photocurable resin containing a supramolecular polymerizable crosslinking agent.

[0144] In the case of the substrate according to the present application, the second composition may be included together with the above-described first composition.

[0145] At this time, as can also be confirmed in FIG. 10c, supramolecular polymerization occurs between the 4,4'-methylenediphenyldiurea functional groups contained inside the monomer represented by chemical formula 2, thereby inducing the methacrylate functional groups located at the ends of the monomer represented by chemical formula 2 to aggregate at a high density.

[0146] Due to the effect of the aggregated methacrylate functional groups, the photocurable resin containing chemical formula 2 enables 3D printing with high resolution, thereby achieving the very high resolution (less than 10 μm) required for semiconductor packaging.

[0147] Also, due to the effect of the aggregated methacrylate functional groups, after exposure to light, the network between the monomers of chemical formula 2 is induced to have a dense structure, and has a low CTE and a low dielectric loss.

[0148] In various embodiments, the compound containing at least two acrylate functional groups can be a POSS acrylate and can be represented by the following structural formula. JPEG2025088784000012.jpg80170

[0149] By including POSS acrylate in the second composition as described above, when it contains this, it is known to have a low dielectric constant and a low CTE and can be composed of a silica (SiO 2 ) component and can have desired dielectric constant values and CTE values.

[0150] The photoinitiator contained in the second composition can have the description of the photoinitiator contained in the first composition described above applied as it is.

[0151] In various embodiments, the weight ratio of the oligomer containing the monomer represented by Chemical Formula 2 to the compound containing at least two acrylate functional groups can be 5:60 to 20:40, and specifically can be 10:55 to 15:30.

[0152] In various embodiments, the cured product of the second composition has a dielectric constant of 3.3 to 3.6 and a coefficient of thermal expansion (CTE) of 5 ppm K -1 or more and 10 ppm K -1 and can also have a resolution in the unit of μm according to the three-dimensional printing process.

[0153] In various embodiments, in the case of a substrate material, it can simultaneously contain the cured product of the first composition (photosensitive polyimide photocurable resin) and the cured product of the second composition (POSS photocurable resin containing a supramolecular polymerizable crosslinking agent) described above, and at this time, the weight ratio of the two cured products can be 30:60 to 50:40.

[0154] Hereinafter, a production example of producing a photosensitive polyimide photocurable resin by curing the second composition will be described.

[0155] <Production Example> 1) Production of an oligomer containing the monomer represented by Chemical Formula 2 50 mL of chloroform was added to a flask containing 10 g of aminopropyl-terminated polydimethylsiloxane, and 0.7 mL of triethylamine was added.

[0156] 0.375 g of 4,4'-methylenediphenyldiisocyanate was dissolved in 15 mL of chloroform, and this solution was dropped into the flask one drop at a time at room temperature over 90 minutes to form 4,4'-methylenediphenyl diurea functional groups between the polydimethylsiloxane macromolecules.

[0157] At this time, the reaction was carried out under an argon atmosphere free of moisture.

[0158] Next, 1.1 mL of methacryloyloxyethyl isocyanate was added to the reaction solution, and then the reaction was carried out at room temperature for 2 hours to bond it to both ends of the monomer.

[0159] Next, 500 mL of methanol was added to the solution after the reaction was completed, the floating solution was discarded, and the precipitated solid substance was dried at room temperature to obtain an oligomer containing the monomer of macrochemical formula 2.

[0160] 2) Production of photocurable resin The oligomer containing the monomer of chemical formula 2 and the POSS acrylate compound were mixed at a weight ratio of 10:90, and then 2-hydroxy-2-methylpropiophenone was added at 2 weight ratios of the mixture.

[0161] At this time, for viscosity adjustment of the photocurable resin, tetrahydrofuran can be added at 0 weight ratio or more and less than 50 weight ratio of the above mixture.

[0162] As a characteristic for the semiconductor packaging, the material can have a characteristic (or a curable characteristic) that enables a process in the order of micrometers based on the semiconductor packaging. In other words, the material can have a resolution in the order of micrometers. The order of micrometers includes a range of 2 micrometers or more and 25 micrometers or less, and can preferably be 2 micrometers, 10 micrometers, and 25 micrometers. Thereby, the width of the through-structure formed inside the substrate 911 is formed in the order of micrometers, and then, by forming the width of the interconnecting portion (or metal wire) formed by the metallization process into a fine interconnecting portion in the order of micrometers, an optimal electrical connection between electronic components (e.g., chips) can be provided.

[0163] On the other hand, without being limited to the described examples, as a characteristic for the semiconductor packaging, the material can be configured to have a characteristic that enables a process in the order of nanometers. In other words, the material can have a resolution in the order of nanometers.

[0164] For example, as a characteristic for the semiconductor packaging, after the material is cured based on a 3D printing process, depending on the type of electronic product (e.g., substrate) to which the substrate 911 is provided (or physically connected), it can have a dielectric constant characteristic as shown in the following [Table 1], but without being limited to the described examples, it may be configured to have a dielectric constant exceeding the described range depending on the type of product.

[0165]

Table 1

[0166] Thereby, the loss rate of the electrical connection signal through the interconnecting portion can be reduced. Also, for example, as a characteristic for the semiconductor packaging, after the material is cured based on a 3D printing process, it can be configured to have a loss tangent of 0.01 or less, but without being limited to the described examples, it may be configured to have a loss tangent exceeding the described range depending on the type of product as in the case of the above-described dielectric constant.

[0167] Also, for example, as a characteristic for the semiconductor packaging, after the material is cured based on a 3D printing process, the surface roughness may be achieved to be 0.7 μm or less, or preferably 0.5 μm or less, but is not limited to the described examples and may be configured to have a roughness exceeding the described range depending on the type of the product described above. Thereby, the inner surface roughness of the through-hole structure (for example, a hole) formed inside the substrate 911 may be achieved to be 0.7 μm or less as described above, or preferably 0.5 μm or less. By achieving the inner roughness of the through-hole structure within the described range, subsequently, the growth of the metal based on the metallization process becomes smooth, and the electrical connectivity can be improved. Also, for example, as a characteristic for the semiconductor packaging, it can have a coefficient of thermal expansion of 41 ppm / °C or less, or preferably 35 ppm / °C or less, but is not limited to the described examples and may be configured to have a coefficient of thermal expansion exceeding the described range depending on the type of the product. By configuring the substrate 911 to have a coefficient of thermal expansion within the described range, when heat is applied to the electronic product provided with the substrate 911, the deformation rate due to heat is limited, and the physical connection quality with other electronic products (for example, a substrate, a chip) physically connected to the substrate 911 can be improved.

[0168] According to various embodiments, the material can be configured to include at least one monomer as shown in FIG. 10b. The at least one monomer can be configured to have a curing property based on the 3DP method described above. On the other hand, without being limited to the illustrated and / or described examples, the material can be a material such as glass, ceramic, plastic, etc.

[0169] According to various embodiments, the packaging device 20 (e.g., 3D printing device 610) can perform 3D printing in operation 1003 and generate a substrate having at least one internal structure (e.g., a through structure) in operation 1005. For example, the 3D printing can include photocuring and thermosetting. Preferably, the 3D printing may be performed based on UV. In this case, after forming the substrate based on UV having a first strength, a processing step for removing the remaining substances on the substrate based on UV having a second strength higher than the first strength can be continuously performed. For example, when the 3D printing method of the packaging device 20 (e.g., 3D printing device 610) is the PuSL method, the material can be cured in layer units with CNC-level accuracy, and as a process result, a substrate 911 (or a dielectric layer) having at least one through structure can be generated.

[0170] According to various embodiments, the unit of the width of at least one internal structure (e.g., a through structure) can be in μm units.

[0171] According to various embodiments, the aspect ratio of at least one internal structure (e.g., a through structure) can be realized to be 10 or more, but is not limited to the described examples.

[0172] According to various embodiments, the packaging device 20 (e.g., 3D printing device 610) can generate at least one structure formed at a position different from the position where the through-structure is formed, in addition to the at least one internal structure in at least a part of the operation of generating the through-structure. For example, the packaging device 20 (e.g., 3D printing device 610) can form empty spaces of various shapes inside the substrate 911. The empty space is formed at a position different from the position where the at least one through-structure is formed, and can improve the heat dissipation performance generated from the substrate 911 and / or reduce the physical stress applied to the substrate 911. Also, for example, the packaging device 20 (e.g., 3D printing device 610) can generate a water channel structure. Through the water channel structure, a fluid for discharging the waste heat of the substrate 911 can be provided. Also, for example, in addition to the above structures, the packaging device (e.g., 3D printing device 610) can realize the substrate 911 so as to include a structure or configuration for providing functions of various configurations that can be realized around a conventional semiconductor package. As various configurations and / or structures for realizing various conventional functions are integrated in the substrate 911, the size of the packaging structure decreases, enabling the realization of more efficient electronic products.

[0173] 3.1.2 Substrate 911 External Structure Formation Process FIG. 11a is a flowchart showing an example of a process for forming a 3DP-based substrate 911 according to various embodiments. Operations can be executed regardless of the order of operations shown and / or described, and more operations can be executed and / or fewer operations can be executed. Hereinafter, FIG. 11a will be further described with reference to FIGS. 11b and 11c.

[0174] FIG. 11b is a diagram for explaining an example of a process for forming an external structure of the substrate 911 according to various embodiments. FIG. 11c is a diagram for explaining an example of a process for forming an external structure of the substrate 911 according to various embodiments.

[0175]

[0175] According to various embodiments, the packaging device 20 (e.g., 3D printing device 610) can provide a material for substrate generation in operation 1101 and perform 3D printing in operation 1103.

[0176]

[0175] According to various embodiments, the packaging device 20 (e.g., 3D printing device 610) can generate a substrate having at least one external structure in operation 1105. For example, referring to 1101S to 1103S in FIG. 11b, the packaging device 20 (e.g., 3D printing device 610) can form at least one of a base layer 1100a, a conductive layer 1100b disposed on the base layer 1100a, an external protruding structure 1100c having a specific thickness disposed on the conductive layer 1100b, or a protective layer 1100d disposed on the conductive layer 1100b based on 3DP. For example, the packaging device 20 (e.g., 3D printing device 610) can form the external protruding structure 1100c and the protective layer 1100d based on 3DP for the structure in which the base layer 1100a and the conductive layer 1100b are formed. However, it is not limited to the described examples, and the packaging device 20 (e.g., 3D printing device 610) can also perform a process of forming all of the base layer 1100a, the conductive layer 1100b, the external protruding structure 1100c, and the protective layer 1100d based on 3DP.

[0177]

[0175] According to various embodiments, the material of the base layer 1100a can be a dielectric material such as ceramic.

[0178]

[0175] According to various embodiments, the material of the conductive layer 1100b can be a metal material such as copper.

[0179] According to various embodiments, the material of the external protruding structure 1100c can be a fluorine-based Teflon (registered trademark) or the like as a hydrophobic substance, and the material of the protective layer 1100d can be PMMA or the like as a hydrophilic substance. However, it is not limited to the described examples, and the material of the external protruding structure 1100c and the material of the protective layer 1100d can be realized by various materials that can be removed by a specific solvent. At this time, the external protruding structure 1100c can be configured to have properties different from those of the protective layer 1100d described later. As an example, the material of the external protruding structure 1100c can have hydrophobicity, and the material of the protective layer 1100d can have hydrophilicity. However, the materials of the external protruding structure 1100c and the protective layer 1100d may be realized to have properties opposite to those of the described examples. Thereby, only one of the external protruding structure 1100c and the protective layer 1100d can be configured to be removed by a specific solvent.

[0180] According to various embodiments, the material of the external protruding structure 1100c can be a material having a first resolution (for example, Teflon or the like), and the material of the protective layer 1100d can be a material having a second resolution lower than the first resolution (for example, PMMA or the like). As shown in FIG. 11b, the external protruding structure 1100c and the protective layer 1000d can be realized in a form in contact with each other. However, due to the external protruding structure 1100c having a higher resolution, the roughness (or resolution) of the outline (outer contour) of the protective layer 1100d in contact with the external protruding structure 1100c can be ensured at a specific level or higher (for example, at or above the resolution level of the external protruding structure 1100c).

[0181] According to various embodiments, by performing the step of forming the external protruding structure 1100c of the Teflon material, the resolution of the protective layer 1100d formed based on 3DP can be guaranteed to be at a specific level or higher. For example, the protective layer 1100d uses a Teflon material. According to various embodiments, in operation 1107, the packaging apparatus 20 can perform an additional process. For example, referring to 1105S in FIG. 11b, 1107S and 1109S in FIG. 11c, the packaging apparatus 20 provides a first solvent (e.g., a hydrophobic solvent) to remove the external protruding structure 1100c, etches the conductive layer 1100b that is exposed as the external protruding structure 1100c is removed, and can perform an additional process of providing a second solvent (e.g., a hydrophilic solvent) having properties different from those of the first solvent to remove the protective layer 1100d. As a result, a conductive layer having a specific external structure (or pattern) P can be formed on the base layer 1100a. The width W of the specific external structure P can be realized with a resolution in μm corresponding to the resolution of the material of the 3DP substrate described above. Thereby, compared with the process of performing etching using a conventional exposure process, the etching process can be performed based on 3DP without equipment for the exposure process, so the convenience of the process is improved and the operation burden can be reduced.

[0182] According to various embodiments, the structure 1100 manufactured by the packaging apparatus 20 can be used privately to form an electric circuit. At this time, the heat generated in the structure 1100 by the pattern P can be released with excellent performance.

[0183] 3.1.2 Method for Generating Substrate 911 FIG. 12 is a flowchart for explaining an example of operations for generating a substrate 911 based on a drawing file received from a user device according to various embodiments. The operations may be executed regardless of the order and relationship of the illustrated and / or described operations, more operations may be executed, and / or fewer operations may be executed. Hereinafter, with reference to FIG. 13, FIG. 12 will be further described.

[0184] FIG. 13 is a diagram for explaining an example of operations for generating different substrates 911 according to a drawing file received from a user device according to various embodiments.

[0185] According to various embodiments, an order-made type 3D printing system 1 (e.g., server 10) can obtain drawing files from each of a plurality of user devices in operation 1201 and obtain a printing file based on the drawing files in operation 1203. For example, referring to FIG. 13, each of various consumers attempting to use the order-made type 3D printing system 1 can operate a different user device (e.g., the first user device 1301, the second user device 1302). Each different user device (e.g., the first user device 1301, the second user device 1302) is configured to store a design program 361 and can generate drawing files (e.g., the first drawing file and the second drawing file) based on the design program 361. The server 10 can receive drawing files (e.g., the first drawing file and the second drawing file) from each of the plurality of user devices (e.g., the first user device 1301, the second user device 1302) and obtain different printing files (e.g., the first printing file and the second printing file) based on the conversion program 331.

[0186] According to various embodiments, the made-to-order 3D printing system 1 (e.g., the packaging device 20) can provide a material for substrate generation in operation 1205, execute 3D printing in operation 1207, and generate a substrate having at least one internal structure (e.g., a through structure) of the type corresponding to the drawing file in operation 1209. The operations 1205 to 1290 of the made-to-order 3D printing system 1 (e.g., the packaging device 20) can be executed in the same way as the operations 1001 to 1005 of the above-described packaging device 20 (e.g., the 3D printing device 610), so duplicate explanations are omitted. Referring to FIG. 13, the server 10 can transmit a control signal for controlling the packaging device 20 (e.g., the 3D printing device 610) to generate a substrate corresponding to the printing file to the packaging device 20 (e.g., the 3D printing device 610) based on the printing file (e.g., the first printing file and the second printing file). Alternatively, without being limited to the described examples, the server 10 can also provide the printing file to the packaging device 20 so that the packaging device 20 directly executes the 3D printing process based on the printing file. The packaging device 20 (e.g., the 3D printing device 610) can generate different substrates (or dielectric layers) 1300a and 1300b respectively based on the printing file (e.g., the first printing file and the second printing file) received from the server 10. The different substrates 1300a and 1300b can be configured to include different through structures as shown in FIG. 13.

[0187] 3.1.3 Substrate 911 Generation Correction Operation FIG. 14 is a flowchart for explaining an operation example of correcting the size of the substrate 911 in at least a part of the 3DP-based substrate forming operations according to various embodiments. The operations can be executed regardless of the order and relationship of the illustrated and / or described operations, and more operations can be executed and / or fewer operations can be executed. Hereinafter, FIG. 13 will be further described with reference to FIGS. 15 and 16.

[0188] FIG. 15 is a diagram for explaining an operation example of correcting the size according to various embodiments. FIG. 16 is a diagram for explaining an operation example of correcting the size of the server 10 according to various embodiments.

[0189] According to various embodiments, the made-to-order 3D printing system 1 (e.g., the server 10) can acquire drawing files from each of a plurality of user devices in operation 1401, and can acquire a printing file based on the drawing files in operation 1403. Since the operations 1401 to 1403 of the made-to-order 3D printing system 1 (e.g., the server 10) may be executed like the operations 1201 to 1203 of the made-to-order 3D printing system 1 (e.g., the server 10) described above, duplicate explanations are omitted.

[0190] According to various embodiments, the made-to-order 3D printing system 1 (e.g., the packaging device 20) can provide a material for substrate generation in operation 1405, execute 3D printing in operation 1407, and generate a substrate having at least one internal structure (e.g., a through structure) of the type corresponding to the drawing file in operation 1409. Since the operations 1405 to 1409 of the made-to-order 3D printing system 1 (e.g., the packaging device 20) can be executed like the operations 1205 to 1009 of the made-to-order 3D printing system 1 (e.g., the packaging device 20) described above, duplicate explanations are omitted.

[0191] According to various embodiments, an order-made type 3D printing system 1 (e.g., a packaging device 20) can modify the size characteristics of a substrate based on comparing the size characteristics of the generated substrate with the size characteristics of the design in the file in operation 1411. For example, the size characteristics may mean the sizes of the components constituting the substrate 911. As an example, it may mean the width and / or length of the body of the substrate 911, the diameter and / or width of the through structure (or hole) formed inside the substrate 911, or the size of other formed physical structures.

[0192] Referring to FIG. 15, the size characteristics of the input design (e.g., the design included in the print file) and the output scale (e.g., the substrate 911 manufactured by the packaging device 20) can be different from each other. In order to remove and / or reduce the difference in the size characteristics, the server 10 can execute an operation of correcting (or modifying, or changing) the size characteristics of the design included in the print file.

[0193] In one embodiment, as shown in FIG. 16(a), the server 10 is configured to further include a correction program 1610. Based on the correction program 1610, the server 10 can compare the size characteristics of the design included in the print file with the size characteristics of the manufactured substrate 911, and modify the size characteristics of the substrate 911 in the print file based on the comparison result. For example, when the size characteristics of the substrate 911 are larger than the size characteristics of the substrate 911 in the print file, the server 10 can reduce the size characteristics of the substrate 911 in the print file. When the size characteristics of the substrate 911 are smaller than the size characteristics of the substrate 911 in the print file, the server 10 can increase the size characteristics of the substrate 911 in the print file. Thereby, based on the print file with the modified size characteristics, the server 10 can generate a substrate 911 having size characteristics corresponding to the drawing file (i.e., meeting the needs of consumers) by executing 3DP-based substrate generation again.

[0194] Also, in one embodiment, as shown in FIG. 16(b), the server 10 is configured to further include a conversion AI module 1620, and based on the conversion AI module 1620, a drawing file can be converted into a print file having optimized size characteristics. For example, the conversion AI module 1620 can be an artificial intelligence model that learns the drawing file received from the user device and the finally corrected print file as training data. Since the learning is a well-known technique based on cartographic learning methods such as regression and classification (e.g., SVM (support vector machine)), non-cartographic learning methods such as clustering, and reinforcement learning methods such as deep learning, specific descriptions are omitted. For example, as described above, the server 10 acquires a print file corrected based on the drawing file and the correction program 1610, uses the drawing file as input data, and uses the corrected print file as output data, and by running, when a drawing file is input, a conversion AI module 1620 configured to output a print file can be generated. Since the print file output from the conversion AI module 1620 is a print file corrected in consideration of the correction error, the process can be efficiently executed without the complicated correction operation using the correction program 1610.

[0195] On the other hand, without being limited to the described and / or illustrated examples, the correction program 1610 and the conversion AI module 1620 can be implemented in a 3D printing device 610 other than the server 10 and configured to perform the above-described operations.

[0196] 3.2 Metallization process FIG. 17 is a flowchart for explaining an example of a metallization process according to various embodiments. The operations may be executed regardless of the order and relationship of the illustrated and / or described operations, and more operations may be executed and / or fewer operations may be executed. Hereinafter, with reference to FIGS. 18 and 19, FIG. 17 will be further described.

[0197] FIG. 18 is a diagram for explaining an example of a metallization apparatus 620 for a metallization process according to various embodiments. FIG. 19 is a diagram for explaining an example of an operation of removing internal defects formed in a through-structure inside a substrate 911 during a metallization process according to various embodiments.

[0198] According to various embodiments, an order-made type 3D printing system 1 (for example, a packaging apparatus 20) can generate a substrate 1800 in operation 1701. The operation 1701 of the order-made type 3D printing system 1 (for example, a packaging apparatus 610) can be executed as described in the above “3. 3DP-based substrate forming process”, and thus overlapping explanations are omitted. The metallization apparatus 620 can receive (or be provided with) the substrate 1800 generated by the 3D printing apparatus 610 via a trailer, and can continue to perform a metallization process on the received substrate 1800 based on a fluid conductive material (for example, a fluid metal). The fluid conductive material can include fluid copper, but is not limited to the described example, and can be various materials having conductivity.

[0199] According to various embodiments, as shown in FIG. 18(a), the metallization apparatus 620 includes a base 1820 on which a substrate 1800 having at least one through-structure 1800a, 1800b formed therein is placed, a providing member 1830 (for example, a pipe) for providing a fluid conductive material (for example, a fluid metal), a storage structure 1810 for storing a fluid conductive material (for example, a fluid metal), and a pump (not shown) for transmitting the fluid conductive material from the storage structure 1810 to the substrate 1800 via the providing member 1830. However, without being limited to the described and / or illustrated example, the metallization apparatus 620 can be configured to include more components or fewer components.

[0200] According to various embodiments, the base 1820 of the metallization device 620 may include a body 1821 on which the substrate 1800 is placed and a recovery structure 1822 for recovering a fluid metal substance, as shown in FIG. 18(b). A protrusion for mounting the substrate 1800 may be formed on the body 1821. As an example, as shown in FIG. 18(b), a protrusion may be formed on the inner surface of the side surface of the body 1821. The body 1821 may be designed such that the height of the side surface of the body 1821 is higher than the position of the surface of the substrate 1800 when the substrate 1800 is mounted. Thereby, the fluid conductive substance FM can be smoothly provided by the providing member 1830 on the substrate 1800. Further, through holes for removing and / or recovering the fluid conductive substance FM remaining after the metallization process may be formed on at least a part of the surface of the body 1821. As an example, as shown in FIG. 18(b), through holes may be formed on the lower surface of the body 1821. The recovery structure 1822 is disposed at a position for recovering the remaining fluid conductive substance FM after the process provided from the through holes, and the fluid conductive substance FM can be provided again to the storage structure 1810 through the pipe 1823. The recovery may be performed by the above-described pump (not shown).

[0201] According to various embodiments, a made-to-order type 3D printing system 1 (for example, the metallization device 620) can perform a surface hydrophilization process in operation 1703. For example, referring to FIG. 19(a), the metallization device 620 can hydrophilize (1901) the inner surface of a through structure 1900 (for example, a hole) formed inside the substrate 1800. As an example, the metallization device 620 can perform hydrophilization based on at least one of plasma treatment, atomic layer deposition, or chemical vapor deposition. Thereby, an oxide film (MOX) in atomic units may be formed on the inner surface of the through structure 1900. By hydrophilizing the inner surface of the through structure 1900, subsequent metal growth can be performed smoothly.

[0202] According to various embodiments, the custom 3D printing system 1 (e.g., the metallization device 620) can perform a metal growth process in operation 1705. For example, referring to FIG. 19(a), the metallization device 620 can grow a metal 1905 on the inner surface of the hydrophilized through-hole structure 1900, and as a result, form fine interconnects (or metal wires) inside the substrate 1800.

[0203] According to various embodiments, the metallization device 620 can perform metal seed layer 1903 formation and metal growth (1905) based on at least one of electroless plating or electroplating. For example, the electroless plating can be based on capillary action and / or microfluidic regulation. For example, in at least a part of the operation of performing electroless plating by utilizing the capillary action, the metallization device 620 provides the fluid conductive material FM to the substrate 1800 via the providing member 830, and can control the fluid conductive material FM on the substrate 1800 to penetrate into the μm-scale through-hole structure 1900 inside the substrate 1800 by capillary action. Also, for example, the metallization device 620 can provide the fluid conductive material FM and control the flow rate in a state where the micro-providing member 830 formed in μm units is inserted into the μm-scale through-hole structure 1900 of the substrate 1800. For example, in electroplating, an anode and a cathode are arranged, and a power source is applied to at least one of the anode and the cathode to provide the fluid conductive material FM to the surface of the through-hole structure 1900 inside the substrate 1800. In at least a part of the operation of performing electroplating, the metallization device 1820 can perform an operation of applying a constant voltage, an operation of applying a reverse voltage, and an operation of refraining from applying a voltage for a micro through-hole structure having a high aspect ratio (for example, having an aspect ratio of 10 or more). For example, the metallization device 1820 can perform metal growth using a constant voltage (or current) during a first period, perform metal dissolution using a reverse pulse voltage (or current) during a second period, and can have a pause period by refraining from applying a voltage during a third period, and the first period, the second period, and the third period can be defined as one cycle. The metallization device 1820 repeats one cycle, and can advance a uniform plating process by adjusting the concentration of ion distribution by adjusting the time lengths of the first period, the second period, and the third period respectively. At this time, the first period for applying the pulse voltage and the second period for applying the reverse pulse voltage can be set to be different. For example, the first period may be set to be longer than the second period, but is not limited to the described example, and may be set conversely.

[0204] In one embodiment, the metallization apparatus 620 can utilize electroless plating for both the formation of the metal seed layer 1903 and the growth of the metal 1905.

[0205] For example, the metallization apparatus 620 can perform both the formation of the metal seed layer 1903 and the growth of the metal 1905 based on capillary action. The metallization apparatus 620 adjusts the amount of the fluid conductive material FM provided on the upper portion of the substrate 1800 using the providing member 1830 as described above, and adjusts the amount of the fluid conductive material FM provided in the through-hole structure 1900 by capillary action, thereby performing the formation of the metal seed layer 1903 and the growth of the metal 1905. As an example, the metallization apparatus 620 provides a first amount of the fluid conductive material FM for the formation of the metal seed layer 1903, and after the metal seed layer 1903 is formed, provides a second amount of the fluid conductive material FM greater than the first amount to grow the metal 1905. However, the present invention is not limited to the described example, and the amount of the fluid conductive material FM may be set conversely. At this time, the metallization apparatus 620 can vary the process conditions (e.g., temperature) during a first period in which the metal seed layer 1903 is formed and a second period in which the metal 1905 grows. For example, the temperature in the second period can be set to grow the metal faster than the temperature in the first period. However, the present invention is not limited to the described example, and the temperature may be set conversely.

[0206] Also, for example, the metallization apparatus 620 can form the metal seed layer 1903 based on capillary action and perform the growth of the metal 1905 based on microfluidic adjustment. After the metal seed layer 1903 is formed based on capillary action, the metallization apparatus 620 can perform metal growth by providing the fluid conductive material FM with the micro-providing member 830 formed in μm units inserted into the through-hole structure 1900 of the substrate 1800 in μm units. As an example, the metallization apparatus 620 provides the fluid conductive material FM at a first flow rate for the formation of the metal seed layer 1903, and after the metal seed layer 1903 is formed, provides the fluid conductive material FM at a second flow rate slower than the first flow rate to grow the metal 1905. However, the flow rate of the fluid conductive material FM can also be set conversely.

[0207] Also, for example, any of the metallization apparatuses 620 can perform the formation of the metal seed layer 1903 and the growth of the metal 1905 based on microfluidic adjustment. The metallization apparatus 620 can perform the formation of the metal seed layer 1903 and the growth of the metal 1905 based on adjusting the flow rate of the fluid conductive substance FM in a state where the micro-providing member 830 formed in μm units is inserted into the through-structure 1900 in μm units of the substrate 1800.

[0208] Also, in one embodiment, the metallization apparatus 620 can form the metal seed layer 1903 based on electroless plating and grow the metal 1905 based on electroplating.

[0209] Also, in one embodiment, the metallization apparatus 620 can form the metal seed layer 1903 based on electroplating and grow the metal 1905 based on electroless plating.

[0210] Also, in one embodiment, the metallization apparatus 620 can form the metal seed layer 1903 based on electroplating and grow the metal 1905.

[0211] According to various embodiments, the metallization apparatus 1820 can perform an operation for removing and / or reducing the internal defect V formed in the through-structure 1900 as shown in FIG. 19(b) in at least a part of the metallization process. The internal defect is a void and can mean an empty space that the fluid conductive substance FM could not fill, but is not limited to the described example and may mean foreign matter other than the fluid conductive substance FM. The detection of the internal defect V can be detected by a connectivity test using the test analysis apparatus 650 described above, but is not limited to the described example.

[0212] For example, when the metallization device 1820 utilizes electroless plating in at least a part of the operation of removing the internal defect V, the amount and flow rate of the fluid conductive substance FM can be controlled to remove and / or reduce the internal defect V. As an example, when the internal defect V occurs, the metallization device 1820 can increase the amount of the fluid conductive substance FM or dynamically change the flow rate, so that the fluid conductive substance FM is provided as the internal defect V, thereby removing and / or reducing the internal defect V.

[0213] Also, for example, the metallization device 1820 further includes a vibration device (not shown) (or an ultrasonic device) on the base 1820 where the substrate 1800 is disposed, and in at least a part of the operation of removing the internal defect V, by providing vibration to the substrate 1800 using the vibration device (or ultrasonic device), the fluid conductive substance FM is provided as the internal defect V, thereby removing and / or reducing the internal defect V.

[0214] 3.3 Bump formation and bonding process According to various embodiments, the packaging device 20 can perform the process of forming bumps on the substrate 910 including the interconnecting portion as described above and physically and / or electrically connecting to other electronic components (e.g., chip packaging substrate), and specific descriptions are omitted.

[0215] 3.4 Other processes According to various embodiments, the packaging device 20 can generate a packaging structure (e.g., a substrate with bumps) in a form physically and / or electrically connected to a conventional interconnect structure. For example, the packaging device 20 (e.g., the bonding device 640) can bond a packaging structure (e.g., a substrate with bumps) to a conventional interconnect structure (e.g., a redistribution layer RDL, a through-silicon via TSV). Also, for example, the packaging device 20 further additionally includes equipment (not shown) for generating a conventional interconnect structure, and can form a conventional interconnect structure on the packaging structure (e.g., a substrate with bumps).

[0216] 4. Packaging Structure and Application Products Hereinafter, examples of a packaging structure generated by the above-described made-to-order type 3DP system 1 according to various embodiments and application products to which the packaging structure is applied will be described.

[0217] FIG. 20 is a diagram for explaining examples of a packaging structure and application products according to various embodiments.

[0218] According to various embodiments, referring to FIG. 20, a packaging structure 2000 is formed by a packaging device 20 (e.g., a 3D printing device 610, a metallization device 620, a bump generation device 630, and a bonding device 640), and the packaging structure 2000 may be provided in another application product 3000 and used.

[0219] According to various embodiments, the packaging structure 2000 can be realized as a first type of packaging structure 2001 that includes only the 3D printing interconnection structure 2001a (for example, a structure formed based on the process of the packaging device 20 described above) and a second type of packaging structure 2003 in which the 3D printing interconnection structure 2001a and the conventional high-resolution structure 2003a (for example, redistribution layer RDL, through-silicon via TSV) are physically and / or electrically connected. Examples of each structure will be specifically described.

[0220] According to various embodiments, the application product 3000 can include various types of devices as described above with reference to FIG. 2 as a product including the packaging structure 2000 and a plurality of electronic components (for example, a first electronic component 3000a and a second electronic component 3000b) connected to the packaging structure 2000.

[0221] 4.1 Packaging Structure 4.1.1 First Type Structure 2001 FIG. 21 is a diagram for explaining an example of a first type of packaging structure according to various embodiments. FIG. 22 is an exploded perspective view of an example of a first type of packaging structure according to various embodiments.

[0222] According to various embodiments, referring to FIG. 21, the first type of packaging structure 2001 may include a substrate 2101 (or a dielectric layer), at least one interconnect 2103 (or a metal wire) included therein, at least one bump 2015 connected to the at least one interconnect 2103, and other internal structures (configurations) 2107. At this time, referring to FIG. 22, the bump 2015 includes interconnects 2105a and 2105b connected to the upper and lower portions of the interconnect, respectively. The types of the interconnects 2105a and 2105b may be different as illustrated, or may be the same. On the other hand, without being limited to the described and / or illustrated examples, the first type of packaging structure 2001 may be configured to include more components and / or fewer components.

[0223] According to various embodiments, the substrate 2101 (or the dielectric layer) can be realized by the 3D printing device 610 as described above. The substrate 2101 (or the dielectric layer) may be realized as a single layer so as to be different from the conventional high-resolution structure 2003a realized by a plurality of layers. For example, the layer is a component that physically separates the dielectric layer. As an example, the layer can separate the upper and lower portions of the dielectric layer with a layer of a conductive material different from the material of the dielectric layer as a reference.

[0224] According to various embodiments, the substrate 2101 (or the dielectric layer) can be configured to have various shapes by the 3D printing device 610. For example, the substrate 2101 can be realized in a shape corresponding to the shape of the internal space in the application product 3000 where the packaging structure 2001 is disposed. The shape can include various shapes not limited to the described examples such as a hexahedron shape, a polygonal prism such as a triangular prism, a circular column, and a spherical shape.

[0225] According to various embodiments, the at least one interconnecting portion 2103 can be formed in various directions. For example, the at least one interconnecting portion 2103 can include a first portion exposed through the upper surface of the substrate 2101, a second portion exposed through the lower surface, and a line connecting between the first portion and the second portion. The line can be configured to cross horizontally and / or vertically inside the substrate 2101 of the single-layer structure described above, and can be configured to have a specific curvature (or angle, or inclination) in some sections. When a plurality of interconnecting portions are realized, as shown in FIG. 21, at least one of the curvature-formed portions between at least two of the plurality of interconnecting portions, the number of curvature-formed portions, or the numerical value of the curvature can be configured to be different respectively. As the at least one interconnecting portion 2103 realized in the substrate 2101 can be realized in various shapes, when applied to the various types of application products 3000 described above, the interconnecting portion 2101 can be optimally formed in a form adapted to the application product 3000, and can provide efficient electrical connectivity between the electronic components included in the application product 3000.

[0226] According to various embodiments, the at least one interconnecting portion 2103 can include a first type of interconnecting portion 2103a exposed to the outside through different surfaces from each other and a second type of interconnecting portion 2103b exposed to the outside through the same surface. The first type of interconnecting portion 2103a is a type of interconnecting portion configured to electrically connect an electronic component (e.g., a chip) disposed on the upper surface and an electronic component (e.g., a packaging substrate) disposed on the lower surface, and as an example, can be an interconnecting portion for fan-out. The first type of interconnecting portion 2103a can be configured to provide the function of a conventional through-silicon via TSV. The second type of interconnecting portion 2103b can be a type of interconnecting portion configured to electrically connect a plurality of electronic components (e.g., a plurality of chips) disposed on the upper surface. The second type of interconnecting portion 2103b can be configured to provide the function of a conventional redistribution layer RDL.

[0227] As a result, as the first type of interconnect 2103a included in the first portion 2101a of the substrate 2101 performs the function of a conventional through-silicon via (TSV) and the second type of interconnect 2103b included in the second portion 2101b is configured to perform the function of a redistribution layer (RDL), the first type of packaging structure 2001 can provide efficiency to perform all the functions of a plurality of conventional interconnect structures (TSV, RDL).

[0228] On the other hand, without being limited to the described and / or illustrated examples, as described above, since the interconnect 2103 can be implemented in various ways to meet consumer needs, it is also possible to form a packaging structure 2101 that includes only the first type of interconnect 2103a or only the second type of interconnect 2103b.

[0229] According to various embodiments, other internal structures (configurations) 2107 can be formed at positions different from the positions where the above-described interconnects 2103 are formed. For example, the other internal structures (configurations) 2107 can include empty spaces of various shapes inside the substrate 2101. The empty spaces are formed at positions different from the positions where the interconnects 2103 are formed, and can improve the heat dissipation performance generated from the substrate 2101 and / or reduce the physical stress applied to the substrate 2101. Also, for example, the other internal structures (configurations) 2107 can generate a water channel structure. Through the water channel structure, a fluid for discharging the waste heat of the substrate 2101 can be provided. Also, for example, in addition to the above-described structure, the other internal structures (configurations) 2107 can include a structure or configuration for providing functions of various configurations that can be realized around a conventional semiconductor package. As a result, as configurations and / or structures for realizing various conventional functions are integrated in the substrate 2101, the size of the packaging structure is reduced, making it possible to realize a more efficient electronic product.

[0230] 4.1.1.1 Various examples of the first type of packaging structure 2001 FIG. 23 is a diagram for explaining various examples of the first type of packaging structure according to various embodiments.

[0231] Referring to FIG. 23, the first type of packaging structure 2001 according to various embodiments can be provided in various shapes.

[0232] For example, as shown in FIG. 23(a), the substrate 2101 can include at least one interconnect 2103 for connecting a plurality of chips 2301a, 2303a, 2305a, 2307a. The at least one interconnect 2103 can include types of interconnects for connecting adjacent chips (e.g., the first chip 2301a and the second chip 2303a, the second chip 2303a and the third chip 2305a, the third chip 2305a and the fourth chip 2307a), and types of interconnects for connecting spaced-apart chips (e.g., the first chip 2301a and the fourth chip 2307a).

[0233] Also, for example, as shown in FIG. 23(b), the substrate 2101 can be configured to include a plurality of protruding portions on which a plurality of chips 2301b, 2303b, 2305b, 2307b, 2309b are respectively disposed, and can be configured to include at least one interconnect 2103 through which a first portion is exposed through the side surfaces of each of the plurality of protruding portions and a second portion is exposed through the bottom surface.

[0234] Also, for example, as shown in FIG. 23(c), the substrate 2101 can be configured to include at least one interconnect 2103 for electrically connecting a plurality of chips 2301c, 2303c, 2305c, 2307c disposed on a plurality of side surfaces.

[0235] 4.1.2 Second type of structure 2003 FIG. 24 is a diagram for explaining various examples of the second type of packaging structure 2003 according to various embodiments.

[0236] According to various embodiments, the second type of packaging structure 2003 is realized in a form that physically (or electrically) connects the first type of packaging structure 2001a and the conventional interconnection structure 2401a (e.g., redistribution layer RDL) as shown in FIG. 24(a), and can be realized based on performing a process (e.g., a vapor deposition process) of forming a conventional interconnection structure 2401b (e.g., redistribution layer RDL) on the first type of packaging structure 2001a as shown in FIG. 24(b).

[0237] According to various embodiments, at least one interconnecting portion 2103 of the first type of packaging structure 2001a and at least one interconnecting portion of the second type of packaging structures 2401a, 2401b can be electrically connected to each other.

[0238] According to various embodiments, the first density of the interconnecting portions included in the first type of packaging structure 2001a (e.g., the mass of the interconnecting portions per unit volume and / or the number of interconnecting portions) and the second density of the interconnecting portions included in the conventional interconnection structures 2401a, 2401b can be different. For example, the first density of the interconnecting portions of the first type of packaging structure 2001a can be configured to be smaller than the second density of the interconnecting portions of the conventional interconnection structures 2401a, 2401b. That is, by additionally arranging the conventional interconnection structures 2401a, 2401b with a high density of interconnecting portions, the resolution of the electrical connection can be improved.

[0239] 4.2 Application Products According to various embodiments, an application product (or electronic device) can be configured to include various types of electronic components (or semiconductor elements). At this time, various types of electronic components (or semiconductor elements, or electronic elements) may be electrically connected (or operatively connected) to each other to provide at least one function. The above-described packaging structure 2000 (for example, the first type of packaging structure 2001, the second type of packaging structure 2003) can be used to electrically (or operatively) connect electronic components (or semiconductor elements) variously mounted for each application product (or electronic device).

[0240] 4.2.1 Chip Packaging FIG. 25 is a diagram for explaining an example of a packaging structure used in an application product according to various embodiments. Hereinafter, with reference to FIGS. 26 to 27, FIG. 25 will be further described.

[0241] FIG. 26 is a diagram for explaining an example of a first type of packaging structure 2001 used in a chip package according to various embodiments. FIG. 27 is a diagram for explaining an example of a second type of packaging structure 2003 according to various embodiments.

[0242] According to various embodiments, the above-described packaging structure 2000 (e.g., the first type of packaging structure 2001, the second type of packaging structure 2003) can be used for a chip package for at least one chip included in various types of application products (or electronic devices). For example, referring to FIG. 25, the packaging structure 2000 can be used to electrically (or operatively) connect at least one chip 2501 and an electronic component 2503. The chip 2501 can be understood as a broad concept including an electronic circuit (e.g., an integrated circuit (IC) such as a memory chip, a CPU, an AP, a GPU, an NPU, etc.) in which two or more semiconductor elements each performing a function are electrically (or operatively) connected, as well as individual electronic elements (e.g., semiconductor elements such as diodes, transistors, MOSFETs, etc., and resistors, etc.).

[0243] According to various embodiments, the package for the at least one chip can include packages such as a system on chip (SOC) form in which semiconductor elements are generated on a single chip, a system in package form in which different chips are generated in a single unit structure, and a chip-let form, wafer-level packages (WLPs) such as Fan-out WLP form, Fan-out PLP form, and Fan-in WLP form, and packages for mobile processors such as 3D Fan-out, etc., but is not limited to the described examples and can include more types of packages.

[0244] 4.2.1.1 Single Chip Package According to various embodiments, referring to FIG. 26(a), the first type of packaging structure 2001 can be configured to electrically connect the chip 2601a and the substrate S. The first portion of at least one interconnect 2103 exposed from the upper surface of the substrate 2001a is electrically connected to the chip 2601a, and the second portion of at least one interconnect 2103 exposed from the lower surface of the substrate 2001a can be electrically connected to the substrate S. Thereby, the electrical signal generated in the chip 2601a is provided to the substrate S, and the electrical signal can be provided to other components via the substrate S.

[0245] According to various embodiments, the distance between at least one interconnect 2103 may vary according to each part of the substrate 2001a. For example, as shown in FIG. 26(a), the distance between the interconnects 2103 in the portion close to the chip 2601a may be smaller than the distance between the interconnects 2103 in the portion close to the substrate S. In other words, the density of the interconnects 2103 in the portion close to the chip 2601a can be configured to be smaller than the density of the interconnects 2103 in the portion close to the substrate S.

[0246] According to various embodiments, one type of packaging structure 2001 used for the single-chip package can be used for through-silicon via (TSV) applications.

[0247] 4.2.1.2 Multi-chip Package According to various embodiments, referring to FIG. 26(b), the first type of packaging structure 2001 can be configured to electrically connect a plurality of chips 2601b and 2603b to each other and to electrically connect the plurality of chips 2601b and 2603b to a substrate S. For example, as shown in FIG. 26(b), at least one interconnecting portion of the substrate 2001a can be configured to include the first type of interconnecting portion 2103a and the second type of interconnecting portion 2103b described above. Thereby, the plurality of chips 2601b and 2603b are connected to the substrate S via the first type of interconnecting portion 2103a, and the plurality of chips 2601b and 2603b can be electrically connected to each other via the second type of interconnecting portion 2103b. The first type of interconnecting portion 2103a can be configured to have different distances according to regions of the substrate 2001a, together with the interconnecting portion 2103 in the single-chip package described above.

[0248] 4.2.1.3 Hybrid Package According to various embodiments, as shown in FIG. 27, the second type of packaging structure 2003 can be used for a chip package.

[0249] In one embodiment, as shown in FIG. 27(a), a conventional high-resolution interconnect structure 2003a (e.g., a redistribution layer RDL) can be used for a higher density (or resolution) input application of electrical signals to a first type of structure 2001a including a first type of interconnect 2103a. A second type of packaging structure 2003 can include a first type of packaging structure 2001a and a conventional high-resolution interconnect structure 2003a (e.g., a redistribution layer RDL) disposed on the first type of packaging structure 2001a. Each of the plurality of chips 2701a, 2703a is electrically connected to a conventional high-resolution interconnect structure 2003a (e.g., a redistribution layer RDL), the interconnects of the conventional high-resolution interconnect structure 2003a are electrically connected to the interconnects 2103 of the substrate 2001a, and the interconnects 2103 of the substrate 2001a can be electrically connected to a packaging substrate (not shown).

[0250] Also, in one embodiment, as shown in FIG. 27(b), a conventional high-resolution interconnect structure 2003a (e.g., a redistribution layer RDL) can be used for a higher density (or resolution) output application of electrical signals to a first type of structure 2001a including a first type of interconnect 2103a. A second type of packaging structure 2003 can include a first type of packaging structure 2001a and a conventional high-resolution interconnect structure 2003a (e.g., a redistribution layer RDL) disposed below the first type of packaging structure 2001a. The first chip 2701b is electrically connected to the interconnects 2103 of the substrate 2001a, a conventional high-resolution interconnect structure 2003a (e.g., a redistribution layer RDL) is electrically connected to the interconnects 2103 exposed through the lower surface of the substrate 2001a, and the conventional high-resolution interconnect structure 2003a can be electrically connected to other electronic components (e.g., a plurality of chips 2703b, 2705b).

[0251] Also, in one embodiment, as shown in FIG. 27(c), a first type of packaging structure 2001 including a first type of interconnecting portion 2103a and a second type of interconnecting portion 2103b and a second type of packaging structure 2003 including a conventional high-resolution interconnecting structure 2003a (e.g., redistribution layer RDL) can be provided. Since the electrical connection relationship can be formed as described above with reference to FIGS. 27(a) and (b), redundant descriptions are omitted.

[0252] Also, in one embodiment, as shown in FIG. 27(d), the conventional interconnecting structure 2003a can be realized in a form included in the first type of packaging structure 2001. For example, the conventional high-resolution interconnecting structure 2003a can be realized in a form inserted into the upper recess of the substrate 2001a. That is, the conventional high-resolution interconnecting structure 2003a can be realized on the substrate 2001a so as to perform the function of the second type of interconnecting portion 2103b described above. Without being limited to the described and / or illustrated examples, the substrate 2001a can also be configured to include a silicon through electrode TSV that includes the second type of interconnecting portion 2103b but is configured to perform the function of the first type of interconnecting portion 2103a in a side portion.

[0253] 4.2.2 Antenna in Package (AIP) FIG. 28 is a diagram for explaining an example of a packaging structure used for an antenna in package according to various embodiments. Hereinafter, with reference to FIG. 29, FIG. 28 will be further described.

[0254] FIG. 29 is a diagram for explaining an example of a packaging structure used for an antenna in package according to various embodiments.

[0255] According to various embodiments, referring to FIG. 28, the packaging structure 2000 can be provided to electrically connect the antenna 2801 (or antenna chip) and other electronic components 2803 (e.g., communication processor, packaging substrate).

[0256] In one embodiment, the packaging structure 2000 can be utilized in various forms (e.g., for curved surface type, free form antenna packaging). For example, referring to FIG. 29(a), the substrate 2001a includes a plurality of surfaces 2901a, 2901b that are realized to face in different directions (or at different angles to each other, or with different inclinations respectively), and can be configured to have a formation corresponding to the shape of the free space inside an application product (e.g., a mobile phone). Antenna chips 2801a, 2801b, 2801c, 2801d can be arranged on each of the plurality of surfaces 2901a, 2901b. A first group of antenna chips 2801c, 2801d can be arranged on the first surface 2901a, and a second group of antenna chips 2801a, 2801b can be arranged on the second surface 2901b. The substrate 2001a includes a plurality of interconnects 2103 that are electrically connected to the respective antenna chips 2801a, 2801b, 2801c, 2801d. The first group of interconnects penetrates through the region corresponding to the first surface 2901a and is electrically connected to the first group of antenna chips 2801c, 2801d, and the second group of interconnects can penetrate through the region corresponding to the second surface 2901b and be electrically connected to the second group of antenna chips 2801a, 2801b. A plurality of bumps 2902a are formed at the lower part of the substrate 2001a, which are electrically connected to the plurality of interconnects 2103 and can be electrically connected to other electronic components 2803a. Thereby, by being electrically connected to other electronic components 2803, the first group of antenna chips 2801c, 2801d and the second group of antenna chips 2801a, 2801b can broadcast radio signals in different directions respectively.

[0257] On the other hand, although not shown, the substrate 2001a can be realized in various shapes such as an L-shape, and as described above, the antenna chips 2801a, 2801b, 2801c, and 2801d are arranged on a surface formed so as to face different directions, and can be used for an antenna-in-package.

[0258] Also, in one embodiment, the packaging structure 2000 can be used for an antenna waveguide package having a coaxial structure. For example, referring to FIG. 29(b), the substrate 2001a is configured to include a coaxial interconnect portion 2103, and the coaxial interconnect portion 2103 can electrically connect the antenna chip 2801e and other electronic components 2803a via bump 2902b. At this time, the coaxial interconnect portion 2103 has a concentric structure including a ground 2911, a dielectric 2913, and a metal 2915, and can be configured so that there is no reflection and radiation during the process of transmitting and / or receiving a radio signal. In the case of a conventional coaxial-structure antenna waveguide package, a plurality of layers are formed inside the substrate, resulting in signal reflection loss between the layers. However, with the packaging structure 2000 according to various embodiments, the substrate 2001a is formed of a single layer, and as the coaxial interconnect portion 2103 is efficiently realized, the above-described problems can be solved.

[0259] On the other hand, in at least a part of the above-described steps, the step of forming the ground 2911 and the dielectric 2913 can be further included so that the interconnect portion 2103 includes not only a metal but also the ground 2911 and the dielectric 2913. For example, during the 3DP-based substrate forming step 801, the step of forming the ground 2911 and the dielectric 2913 inside the through-hole structure can be additionally executed. Also, for example, during the metallization step 803, the step of forming the ground 2911 and the dielectric 2913 inside the through-hole structure can be additionally executed.

[0260] 4.2.3 Other Application Products According to various embodiments, the packaging structure 2000 can be used in various ways to optimize the electrical connection between the electronic components included inside the application product based on having a substrate shape and an interconnect structure that are adapted to consumer needs (or various types of application products), as described above.

[0261] For example, the packaging structure 2000 can be used for socket applications. For example, the socket may mean a test socket for testing a chip (e.g., memory, ASIC, etc.). It can be a test socket where the performance of the chip can be grasped through the substrate output that forms a space where the chip can be mounted using printing and through holes. As a result, the printing process can be enabled without being limited by the shape or number of chips.

Claims

1. A semiconductor packaging module, comprising: a single first semiconductor chip; a substrate including a first surface opposite a bottom surface of the first semiconductor chip, a second surface opposite the first surface, and at least one first interconnect structure therein between the first surface and the second surface; the at least one first interconnect structure includes a first portion exposed through the first surface, a second portion exposed through the second surface, and a line connecting the first portion and the second portion; the first portion is electrically connected to the first semiconductor chip; the second portion is configured to be electrically connectable to another electronic component, The line extends across the single-layer structure body and is configured to have a specific inclination in at least a portion of the line. Semiconductor packaging module.

2. Further comprising a second semiconductor chip, the substrate further includes at least one second interconnect structure; the at least one second interconnect structure further includes a third portion exposed through the first surface, a fourth portion exposed through the first surface, and a second line connecting the third portion and the fourth portion; the third portion is connected to the first semiconductor chip, and the fourth portion is connected to the second semiconductor chip. The semiconductor packaging module of claim 1 .

3. A second semiconductor chip; a structure including at least one second interconnect structure; the first semiconductor chip and the second semiconductor chip are electrically connected via a portion of the at least one second interconnect structure; a remaining portion of the at least one second interconnect structure electrically connected to the at least one first interconnect structure of the substrate; The semiconductor packaging module of claim 1 .

4. A first density of the at least one first interconnect structure is lower than a second density of the at least one second interconnect structure. The semiconductor packaging module according to claim 3 .

5. The substrate is A single-layer structure body, at least one first interconnect structure formed within the body; the at least one first interconnect structure includes a first end exposed through a first surface of the substrate, a second end exposed through a second surface of the substrate, and a line connecting the first end and the second end; The line extends laterally and / or longitudinally through the interior of the single-layered body and is configured to be able to form a specific curvature in some sections. The semiconductor packaging module of claim 1 .

6. The at least one first interconnect structure includes a third interconnect structure and a fourth interconnect structure; the curvature of the line of the third interconnect structure is a first curvature; the curvature of the line of the fourth interconnect structure is a second curvature different from the first curvature; The semiconductor packaging module according to claim 5 .

7. The body is configured to correspond to the shape of an empty space inside an electronic product in which the substrate is placed. The semiconductor packaging module according to claim 5 .

8. The at least one first interconnection structure has a first end configured to be connected to a first electronic component of an electronic device and a second end configured to be connected to a second electronic component of the electronic device. The semiconductor packaging module of claim 7 .

9. The density of the at least one first interconnect structure in a first region of the substrate adjacent to the first electronic component is a first density, and the density of the at least one interconnect structure in a second region of the substrate adjacent to the second electronic component is a second density different from the first density. The semiconductor packaging module of claim 8 .

10. The main body is configured to include at least one other structure and / or at least one other member in a portion other than the portion in which the at least one first interconnection structure is arranged. The semiconductor packaging module of claim 8 .

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