Power converter

Abstract

To provide a power converter capable of improving power efficiency while correcting a surge voltage and loss imbalance among switching elements.SOLUTION: A power converter includes: a first capacitor and a second capacitor; a first switching element to a sixth switching element; and a load. Switching between a third output state and a first output state is executed via a second dead time state, and switching between the third output state and the second output state is executed via a first dead-time state. When transitioning between the third output state and the second dead time state, a fifth switching element completes either to turn on the third switching element before the third switching element or turns off the same after the third switching element, or when transitioning between the third output state and the first dead time state, the sixth switching element, performs at least one of the following operations: completing the turn-on before the second switching element or completing the turn-off after the second switching element.SELECTED DRAWING: Figure 8

Description

Technical Field

[0001] The present invention relates to a power converter including a three-level inverter.

Background Art

[0002] In recent years, multi-level inverters have been actively studied in response to the need for higher bus voltages in power converters. For example, Patent Document 1 proposes a circuit of a multi-level inverter called ANPC (Active Neutral-Point-Clamped).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in the prior art, there are surges and unbalances in losses between switching elements, resulting in problems such as a decrease in power efficiency and reliability.

[0005] The present invention has been made in view of the above problems, and an object thereof is to provide a power converter that can correct the imbalance of surge voltage and loss between switching elements and improve power efficiency.

Means for Solving the Problems

[0006] The power converter according to the present invention connects a first capacitor and a second capacitor in series between the positive electrode and the negative electrode of a DC power supply, further connects first to fourth switching elements in series between the positive electrode and the negative electrode of the DC power supply, and connects a fifth switching element between the connection point of the first and second switching elements and the connection point of the first and second capacitors, and connects a sixth switching element between the connection point of the third and fourth switching elements and the connection point of the first and second capacitors, and connects the connection point of the second and third switching elements and a load. A first output state is a state in which the first, second, and sixth switching elements are ON and the third, fourth, and fifth switching elements are OFF; a second output state is a state in which the third, fourth, and fifth switching elements are ON and the first, second, and sixth switching elements are OFF; a third output state is a state in which the second, third, fifth, and sixth switching elements are ON and the first and fourth switching elements are OFF; a first dead time state is a state in which the third and fifth switching elements are ON and the first, second, fourth, and sixth switching elements are OFF; a second dead time state is a state in which the second and sixth switching elements are ON and the first, third, fourth, and fifth switching elements are OFF. The switching from the third output state to the first output state passes through the second dead time state, the switching from the third output state to the second output state passes through the first dead time state. When transitioning between the third output state and the second dead time state, the fifth switching element performs at least one of the operations of completing turn-on before the third switching element or completing turn-off with a delay. When transitioning between the third output state and the first dead time state, the sixth switching element performs at least one of the operations of completing turn-on before the second switching element or completing turn-off with a delay.

Advantages of the Invention

[0007] According to the present disclosure, it is possible to provide a power converter capable of correcting the imbalance of the surge voltage and loss between the switching elements and improving the power efficiency. Further features related to the present invention will become apparent from the description in this specification and the attached drawings. In addition, problems, configurations, and effects other than those described above will be clarified by the description of the following embodiments.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

Figure 4

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Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Modes for Carrying Out the Invention

[0009] First, hereinafter, a reference example useful for understanding this embodiment will be described with reference to the drawings. Hereinafter, a three-phase inverter power conversion device will be taken as an example, but it can also be applied to a single-phase inverter, a multi-phase inverter, and a converter. FIG. 1 is a schematic diagram showing a three-phase inverter power converter, which is also described in Patent Document 1. The device in FIG. 1 is a three-level ANPC (Active Neutral-Point-Clamped) inverter with three phases (hereinafter simply referred to as an ANPC inverter). As shown in FIG. 1, in the ANPC inverter, DC power supplies Vdc1 and Vdc2 are connected in series. The high-potential terminal of DC power supply Vdc1 is the P terminal, the connection point between DC power supplies Vdc1 and Vdc2 is the mid-potential terminal O terminal, and the low-potential terminal of DC power supply Vdc2 is the N terminal. A smoothing capacitor C1 is connected between the P terminal and the O terminal, and a smoothing capacitor C2 is also connected between the O terminal and the N terminal. Capacitors C1 and C2 may be connected in parallel in multiple numbers. The P, O, and N terminals are further connected to the main circuit part that becomes the U, V, and W phases.

[0010] Taking the U phase as an example, the specific configuration will be described with reference to FIG. 2. As shown in FIG. 2(a), the U phase includes a first switching element Q1, a second switching element Q2, a third switching element Q3, a fourth switching element Q4, a fifth switching element Q5, and a sixth switching element Q6. Each switching element is a MOSFET, but it is not limited to this, and it may be a parallel connection body of a semiconductor switching element and a diode. Also, the semiconductor switching element may be, for example, a semiconductor switching element such as an IGBT in addition to a MOSFET. The diode may be, for example, a diode such as a PN junction diode or a Schottky barrier diode. The materials of the above switching elements may be materials such as Si, SiC, GaN, and GaO. Also, two or more types of the above switching elements may be hybrid-mounted. In FIG. 2(a), the illustration of the capacitor is omitted. Hereinafter, in order to avoid redundant expressions, "switching elements Q1 to Q6" may be simply referred to as "Q1 to Q6".

[0011] The first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 are connected in series between the terminal P and the terminal N in this order. A fifth switching element Q5 is connected between the intermediate connection point between the first switching element Q1 and the second switching element Q2 and the O terminal. A sixth switching element Q6 is connected between the intermediate connection point between the third switching element Q3 and the fourth switching element Q4 and the O terminal. Also, the intermediate connection point between the second switching element Q2 and the third switching element Q3 is called the AC terminal, and the AC terminal is connected to a load (see FIG. 1).

[0012] Also, as shown in FIG. 2(b), the switching of the switching elements Q1 to Q6 is controlled by individual gate drivers (GD). The switching signals of the individual gate drivers are generated from the PWM generator 20 of the controller 10.

[0013] Next, the energization method of the ANPC inverter will be described. Normally, the DC power supplies Vdc1 and Vdc2 have a voltage of half of the bus voltage, that is, VDC / 2. Also, the O terminal is set as the voltage neutral point with a potential of 0. Then, the potential of the P terminal becomes +VDC / 2, and the potential of the N terminal becomes -VDC / 2. The voltage between the P terminal and the N terminal is exactly the bus voltage VDC. In this state, to energize the AC terminal and the P terminal, it is necessary to turn on at least the first switching element Q1 and the second switching element Q2 simultaneously. Similarly, to energize the AC terminal and the N terminal, it is necessary to turn on at least the third switching element Q3 and the fourth switching element Q4 simultaneously.

[0014] On one hand, when energizing the AC terminal and the O terminal, there are two paths. That is, as shown in FIG. 9 to be described later, a first path (route 1) formed by turning on the second switching element Q2 and the fifth switching element Q5 simultaneously, and a second path (route 2) formed by turning on the third switching element Q3 and the sixth switching element Q6 simultaneously. To energize the AC terminal and the O terminal, it is necessary to put at least one of these two paths in an energized state. When the AC terminal is energized with the P terminal, the O terminal, and the N terminal respectively, the potential of the AC terminal becomes +VDC / 2, 0, and -VDC / 2 voltages respectively. In this way, the voltage output level of the AC terminal has three levels.

[0015] Next, with reference to FIGS. 3 to 5, the control method of the ANPC inverter, particularly the control method of the reference example in which the AC terminal and the O terminal are energized by the above two paths, will be described. FIG. 3 is a state transition diagram showing the control method of the ANPC inverter in the reference example, showing the state of the switches and the switching elements that are turned on corresponding to the state of the switches. FIG. 4 is a time chart showing the control method in the reference example, showing the ON / OFF of each switching element and the voltage Vout of the AC terminal. FIG. 5 is a diagram for explaining the case where switching loss and switching surge occur in the negative cycle.

[0016] First, as shown in FIG. 3, the states when the AC terminal is energized with the P terminal, the O terminal, and the N terminal respectively are referred to as state P, state O, and state N. State P, state O, and state N correspond to tp, to, and tn shown in FIG. 4 respectively. The transition between state P and state O is called the positive cycle, and the transition between state O and state P is called the negative cycle. Since the operation of the positive cycle is the same as that of the negative cycle, the description is omitted, and only the transition operation of the negative cycle will be described.

[0017] As shown in FIGS. 3 and 4, at state N(tn), switching elements Q3, Q4, and Q5 are ON, and the voltage of the AC terminal is -VDC / 2. At state O(to), switching elements Q2, Q3, Q5, and Q6 are ON, and the output voltage of the AC terminal is 0. Here, at state O, between the O terminal and the AC terminal, routes 1 (Q2 and Q5) and route 2 (Q3 and Q6) are simultaneously energized, and an equal current flows through both paths. When transitioning from state N to state O, it passes through an intermediate state called state NO(tx) (in the positive cycle, it is state PO(ty)). At state NO(tx), switching elements Q3 and Q5 are ON.

[0018] Here, when the switching element is switched, if the direction of the current during conduction is opposite to the forward direction of the diode provided in the switching element, switching loss and surge voltage will occur in the switching element. FIG. 5 is a diagram showing a case where loss and surge voltage occur. FIG. 5 shows a case of transitioning between state N or state O and the intermediate state NO, and the switching elements where loss or surge occurs are surrounded by an "〇" mark.

[0019] First, as shown in FIG. 5(a), when shifting from state NO to state N, switching element Q4 turns on. If the current after turning on (state N) flows from the AC terminal to the N terminal, switching loss during turn-on occurs in switching element Q4, and recovery loss and recovery surge occur in switching elements Q2 and Q6.

[0020] On the other hand, as shown in FIG. 5(b), when shifting from state N to state NO, switching element Q4 turns off. If the conduction current at state N flows from the AC terminal to the N terminal, switching loss and surge voltage during turn-off occur in switching element Q4.

[0021] Next, as shown in FIG. 5(c), when shifting from state NO to state O, switching elements Q2 and Q6 are turned on simultaneously. When the conduction current (state O) flows from the O terminal to the AC terminal, switching losses occur in switching elements Q2 and Q6, and recovery losses and recovery surges occur in switching element Q4.

[0022] Then, as shown in FIG. 5(d), when shifting from state O to state NO, switching elements Q2 and Q6 are turned off simultaneously. When the current was flowing from the O terminal to the AC terminal in state O, turn-off losses and surge voltages occur in switching elements Q2 and Q6.

[0023] FIG. 6 is a diagram comparing the surge voltages and losses that occur in switching elements Q2, Q3, Q5, and Q6 in the reference example. First, the difference in the surge voltages generated in these will be explained. Here, the surge voltage is an overvoltage caused by the parasitic capacitance of the switching element being excessively charged due to the influence of the inductance component near the element when the switching element is turned off.

[0024] Generally, the larger the inductance component of a circuit, the higher the surge voltage generated in the switching element. However, since the inductance components on the paths where the switching elements Q2 and Q6 are located (the path starting from the O terminal and returning to the N terminal) are different, a difference occurs in the surge voltages generated in both switching elements. Specifically, the path where the switching element Q6 is located is O terminal → Q6 → Q4 → N terminal. On the other hand, the path where the switching element Q2 is located is O terminal → Q5 → Q2 → Q3 → Q4 → N terminal, and it can be seen that this path is longer than the path where Q6 is located. Therefore, the surge voltage generated in the switching element Q2 is larger than the surge voltage generated in the switching element Q6. The same applies in the positive cycle, and the surge voltage generated in the switching element Q3 is larger than the surge voltage generated in the switching element Q5. In summary, as shown in Fig. 6(a), the switching surge voltages generated in the switching elements Q2 and Q3 are larger than the switching surge voltages generated in the switching elements Q5 and Q6.

[0025] Next, the difference in losses generated in the above-mentioned switching elements will be described. Here, the losses generated in the switching element include conduction losses caused by heat generated while the current is flowing and switching losses caused by heat generated during switching. The magnitudes of these losses are proportional to the magnitude of the current flowing through the element.

[0026] A conduction current flows through the switching element Q4 in state N, and a conduction current flows through the switching element Q6 in state O. In contrast, a conduction current flows through the switching element Q3 both in state O and in state N. Therefore, it can be seen that the conduction loss of the switching element Q3 is higher than the conduction losses of the switching elements Q4 and Q6. Also, since the conduction current flows equally through the switching elements Q3 and Q6 in state O, the current when the switching elements Q3 and Q6 switch is also equal. Thus, the switching losses generated in the switching elements Q3 and Q6 are of the same degree. Therefore, considering the total loss (conduction loss and switching loss), it can be seen that the loss generated in the switching element Q3 is greater than the loss generated in the switching element Q6. The same applies in the positive cycle, and considering the total loss, the loss generated in the switching element Q2 is greater than the loss generated in the switching element Q5. In summary, as shown in Fig. 6(b), the losses generated in the switching elements Q2 and Q3 are greater than the losses generated in the switching elements Q5 and Q6.

[0027] As described above, as shown in Fig. 6, it can be seen that in the switching elements Q2 and Q3, both the loss and the surge voltage are greater than those in the switching elements Q5 and Q6. Thus, in the ANPC inverter, there is a problem of imbalance in loss and surge voltage between the switching elements.

[0028] <Example 1> Hereinafter, embodiments of the present invention will be described with reference to the drawings. Fig. 7 is a state transition diagram showing the control method of the ANPC inverter in Embodiment 1 of the present invention. Fig. 8 is a time chart showing the control method of the ANPC inverter in Embodiment 1. Hereinafter, the differences from the reference example will be described.

[0029] In this embodiment, it is different from the state transition diagram of the reference example in that state Odf is added between state PO and state O, and state Oec is added between state NO and state O. State Odf corresponds to td and tf shown in FIG. 7, and state Oec corresponds to te and tc shown in FIG. 7. Comparing the time chart in this embodiment shown in FIG. 8 with the time chart of the reference example shown in FIG. 4, it can be seen that times te and tc (tf and td in the positive cycle) are added before and after time to. At these times, for example, in the negative cycle, times te and tc are the times when only switching elements Q3 and Q5 are ON, and no current flows anywhere. This time is defined as dead time in this specification. The same applies to tf and td in the positive cycle.

[0030] Also in this embodiment, since the operation of the positive cycle is the same as that of the negative cycle, the description is omitted, and only the transition operation of the negative cycle is described. As shown in FIG. 9, there are two current conduction routes in states O and Oec. In state Oec, switching element Q2 is OFF and switching elements Q3, Q5, and Q6 are ON, and current mainly flows through route 2. Then, considering the transition from state NO (state where only Q3 and Q5 are ON) to state O (state where Q2, Q3, Q5, and Q6 are ON) via state Oec (state where Q6 is also ON in addition to Q3 and Q5), at the moment of transition to state Oec, current first mainly flows on route 2. After a while, switching element Q2 turns on and the state changes to O, and the current is shared so that it flows evenly on both routes 1 and 2.

[0031] On the contrary, when transitioning from state O to state NO via state Oec, current first flows evenly on both routes in state O. Next, in state Oec, the current in route 1 is reduced and the current on route 2 increases. Eventually, all the current that was flowing on route 1 may flow to route 2. In this state, the switching element Q6 is turned off and the state transitions to state NO. That is, in the reference example, while transitioning from state O to state NO, the switching elements Q2 and Q6 were simultaneously turned off with current flowing evenly, resulting in equivalent switching losses. However, in this embodiment, while transitioning from state O to state NO, first Q2 is turned off with current flowing evenly through the switching elements Q2 and Q6, and then Q6 is turned off with the current concentrated on route 2.

[0032] Summarizing these, when transitioning between state O and state Oec, the fifth switching element performs at least one of the operations of completing turn-on before the third switching element or completing turn-off with a delay. Similarly, during the positive cycle, when transitioning between state O and state Odf, the sixth switching element performs at least one of the operations of completing turn-on before the second switching element or completing turn-off with a delay.

[0033] As described above, in the reference example, the currents during switching flowing through the switching elements Q2 and Q6 were equal. However, in the case of this embodiment, the switching element Q6 switches with a larger current than the switching element Q2. Therefore, in this embodiment, the switching loss generated in Q6 becomes larger than the switching loss generated in Q2. The same applies during the positive cycle, and the switching loss generated in Q5 becomes larger than the switching loss generated in Q3. Regarding the switching losses of Q2 and Q3, at the moment of turn-off, unlike the reference example, Q5 and Q6 are still in the ON state, and the current is not completely cut off but flows towards Q5 and Q6. Therefore, the switching losses generated in Q2 and Q3 become smaller than in the case of the reference example.

[0034] Also, the times te and tc of state Oec are preferably smaller than the time to of state O. By setting it in this way, the increase in the conduction loss of the switching element Q6 in state Oec can be ignored.

[0035] FIG. 10 is a diagram comparing the surge voltages and losses generated in the switching elements Q2, Q3, Q5, and Q6 in this embodiment. The solid line and the broken line are the results of this embodiment and the reference example, respectively. Since the switching element Q2 is switched at a smaller current than in the reference example, the surge voltage in the switching element Q2 is reduced. On the other hand, since the switching element Q6 is switched at a larger current than in the reference example, the surge voltage in the switching element Q6 has increased. The same applies to the positive cycle, the surge voltage generated in the switching element Q3 is reduced, and the surge voltage generated in the switching element Q5 increases. Therefore, the imbalance of the switching surge voltages between the switching elements Q2 (Q3) and the switching elements Q5 (Q6) is corrected and becomes the same level.

[0036] Furthermore, since the switching element Q2 is switched at a smaller current than in the reference example, the switching loss in the switching element Q2 is reduced. On the other hand, since the switching element Q6 is switched at a larger current than in the reference example, the switching loss in the switching element Q6 has increased. Since the conduction loss can be ignored as described above, it is at the same level as the reference example. Therefore, considering the total loss (conduction loss and switching loss), the loss imbalance between the switching elements Q2 (Q3) and the switching elements Q5 (Q6) is corrected and becomes the same level.

[0037] As described above, according to this embodiment, the imbalance of the losses and surge voltages in the switching elements of the ANPC inverter is reduced.

[0038] In order to obtain the effects in the above-described present embodiment, it is essential to pass through the state Oec (Q3, Q5, and Q6 are ON) during the transition between the state NO (Q3 and Q5 are ON) and the state O (Q2, Q3, Q5, and Q6 are ON). That is, it is essential to execute either of the operations that Q6 is turned on before Q2 until the transition from the state NO to the state O, and Q6 is turned off after Q2 until the transition from the state O to the state NO.

[0039] Here, "ON" and "OFF" in this specification respectively refer to "completion of the turn-on operation" and "completion of the turn-off operation", and more specifically, respectively refer to "maximization of the main current flowing through the element" and "minimization of the main current flowing through the element". Also, the start of turn-on (turn-off) refers to the start of the rise (fall) of the voltage applied to the element. Further, the completion of turn-on (turn-off) respectively refers to the net drain current becoming 100% (0%).

[0040] In the above-described Example 1, both te and tc (td and tf) are set before and after the state O, but depending on the situation, only one of te or tc (td or tf) may be set. For example, when the turn-off loss is significant and the imbalance is large, only tc (td) may be set. Further, the lengths of te, tc, td, and tf are preferably set longer than the switching delay time of the switching element (the time from the rise or fall of the gate voltage to the rise or fall of the element main current).

[0041] The above reason will be described with reference to FIG. 11. It takes a time T1 from when the switching element Q6 (Q5) starts to turn on (starts to rise in gate voltage) until current actually starts to flow through Q6 (Q5). If the turn-on of the switching element Q2 (Q3) is started during this time T1, current will start to flow through Q2 (Q3) before the current flowing through Q6 (Q5) has completely risen, and a sufficient imbalance correction effect cannot be obtained.

[0042] The same applies during turn-off. It takes a time T2 from when the switching element Q2 (Q3) starts to turn off until the current actually flowing through Q2 (Q3) begins to decrease. If the turn-off of the switching element Q6 (Q5) is started during this time T2, the current flowing through Q6 (Q5) also begins to decrease before the current flowing through Q2 (Q3) is minimized, and a sufficient imbalance correction effect cannot be obtained.

[0043] The settings of te, tc, td, and tf may be set by the PWM generator 20 on the controller 10 side shown in FIG. 2, may be set by adding a time adjustment circuit between the PWM generator 20 and the gate driver, or may be set by adding a time adjustment circuit inside the gate driver.

[0044] <Example 2> Next, the power converter according to Example 2 will be described. Hereinafter, mainly the parts different from Example 1 will be described. In Example 1, dead times te, tc, td, and tf were set to introduce a shift in the switching timing between the switching element Q6 (Q5) and the switching element Q2 (Q3) to correct the imbalance of the surge voltage and loss. On the other hand, in this example, a shift in the switching timing is realized by setting different switching speeds for the switching element Q6 (Q5) and the switching element Q2 (Q3).

[0045] Specifically, the turn-on speed of the switching element Q5 (Q6) is set to be faster than that of the switching element Q2 (Q3). For example, the turn-on drive resistance of the switching element Q5 (Q6) is set to be smaller than the turn-on drive resistance of the switching element Q2 (Q3).

[0046] In addition to the drive resistance, the current during drive may also be set. For example, the turn-on gate current of the switching element Q5 (Q6) is set higher than the turn-on gate current of the switching element Q2 (Q3). Then, even if the switching element Q5 (Q6) and the switching element Q2 (Q3) start to increase the gate voltage at the same timing, the gate voltage of the switching element Q5 (Q6) exceeds the threshold voltage first, and the main current starts to flow through the switching element Q5 (Q6) earlier than through the switching element Q2 (Q3).

[0047] On the other hand, it is also possible to set the turn-off speed of the switching element Q5 (Q6) slower than that of the switching element Q2 (Q3). For example, the turn-off drive resistance of the switching element Q5 (Q6) is set larger than the turn-off drive resistance of the switching element Q2 (Q3). In addition to the drive resistance, the current during drive may be set. For example, the turn-off gate current of the switching element Q5 (Q6) is set lower than the turn-on gate resistance of the switching element Q2 (Q3). Then, even if the switching element Q5 (Q6) and the switching element Q2 (Q3) start to decrease the gate voltage at the same timing, since the gate voltage drop of the switching element Q5 (Q6) becomes slower, the timing at which the main current of Q5 (Q6) starts to decrease is also delayed compared to Q2 (Q3).

[0048] When the turn-on (turn-off) drive resistance or the turn-on (turn-off) gate current of each switching element is set as described above, even if each switching element is started to be turned on simultaneously, since the current starts to flow through the switching element Q5 (Q6) earlier than through the switching element Q2 (Q3), the current during turn-on is large and the turn-on loss becomes larger. Similarly, even if each switching element is turned off simultaneously, at the time of turn-off, since the main current starts to decrease with the switching element Q5 (Q6) lagging behind the switching element Q2 (Q3), the current during turn-off is large and the turn-off loss and the surge voltage become larger. Therefore, similar to the first embodiment, the imbalance in the loss and the surge voltage in the switching element is corrected.

[0049] <Example 3> Next, the power converter according to Example 3 will be described. Hereinafter, among Example 3, the parts different from the above-described examples will be mainly described. In this example, by selecting elements having different threshold voltages for the switching element Q6 (Q5) and the switching element Q2 (Q3), a deviation in switching timing is realized.

[0050] Specifically, an element having a threshold voltage smaller than that of the switching element Q2 (Q3) is selected as the switching element Q5 (Q6). Then, even if the switching element Q5 (Q6) and the switching element Q2 (Q3) start to increase the gate voltage at the same timing, the gate voltage of the switching element Q5 (Q6) exceeds the threshold voltage first, and the main current starts to flow through the switching element Q5 (Q6) earlier than through the switching element Q2 (Q3). On the other hand, even if the switching element Q5 (Q6) and the switching element Q2 (Q3) start to decrease the gate voltage at the same timing, since the threshold voltage of the switching element Q5 (Q6) is low, the main current drop end timing is delayed.

[0051] By selecting the switching elements in this way, since the current starts to flow through the switching element Q5 (Q6) earlier than through the switching element Q2 (Q3) at turn-on, the current at turn-on increases, and the turn-on loss also becomes larger. Also, at turn-off, since the main current drop time of the switching element Q5 (Q6) is longer than that of the switching element Q2 (Q3), the current at turn-off increases, and the turn-off loss and the surge voltage also become larger. Therefore, similar to the above-described examples, the imbalance in loss and surge voltage in the switching element is corrected.

[0052] <Example 4> Next, the power converter according to Example 4 will be described. Among Example 4, the parts different from the above-described examples will be mainly described. In this example, by setting different gate voltages (negative biases) at OFF for the switching element Q6 (Q5) and the switching element Q2 (Q3), a deviation in switching timing is realized.

[0053] Specifically, the OFF-state gate voltage of the switching element Q5 (Q6) is adjusted to be higher than the OFF-state gate voltage of the switching element Q2 (Q3). For example, the OFF-state gate voltage of the switching element Q5 (Q6) is adjusted to -1V, and the OFF-state gate voltage of the switching element Q2 (Q3) is adjusted to -3V. Then, even if the gate voltages of the switching element Q5 (Q6) and the switching element Q2 (Q3) start to rise at the same timing and at the same speed, the gate voltage of the switching element Q5 (Q6) will exceed the threshold voltage first, and the main current will start to flow through the switching element Q5 (Q6) earlier than through the switching element Q2 (Q3). On the other hand, during turn-off, the lower the OFF-state gate voltage, the faster the gate voltage drops, that is, the faster the turn-off speed. Therefore, even if the gate voltages of the switching element Q5 (Q6) and the switching element Q2 (Q3) start to drop at the same timing, the gate voltage drop speed of the switching element Q5 (Q6) is slow, so the timing at which the current starts to drop is also delayed.

[0054] In this way, since the current starts to flow through the switching element Q5 (Q6) earlier than through the switching element Q2 (Q3) during turn-on, the current during turn-on is large, and the turn-on loss becomes larger. Also, during turn-off, since the main current starts to drop later in the switching element Q5 (Q6) than in the switching element Q2 (Q3), the current during turn-off becomes large, and the turn-off loss and the surge voltage also become larger. Therefore, similar to the above-described embodiments, the imbalance in losses and surge voltages in the switching element is corrected.

[0055] According to the embodiments of the present invention described above, the following operational effects can be obtained.

[0056] (1) The power converter according to the present invention includes a first capacitor and a second capacitor connected in series between the positive and negative electrodes of a DC power supply, a first to fourth switching element connected in series in this order between the positive and negative electrodes of the DC power supply and in parallel with the first and second capacitors, a fifth switching element connected between the connection point of the first and second switching elements and the connection point of the first and second capacitors, a sixth switching element connected between the connection point of the third and fourth switching elements and the connection point of the first and second capacitors, and a load connected to the connection point of the second and third switching elements. The power converter is configured such that the first, second, and sixth switching elements are ON, and the third, fourth, and fifth switching elements are OFF, which is defined as the first output state; the third, fourth, and fifth switching elements are ON, and the first, second, and sixth switching elements are OFF, which is defined as the second output state; the second, third, fifth, and sixth switching elements are ON, and the first and fourth switching elements are OFF, which is defined as the third output state; the third and fifth switching elements are ON, and the first, second, fourth, and sixth switching elements are OFF, which is defined as the first dead time state; the second and sixth switching elements are ON, and the first, third, fourth, and fifth switching elements are OFF, which is defined as the second dead time state. When switching between the third output state and the first output state via the second dead time state, or when switching between the third output state and the second output state via the first dead time state, or when transitioning between the third output state and the second dead time state, the fifth switching element performs at least one of the operations of completing turn-on earlier than the third switching element or completing turn-off with a delay, or when transitioning between the third output state and the first dead time state, the sixth switching element performs at least one of the operations of completing turn-on earlier than the second switching element or completing turn-off with a delay.

[0057] With the above configuration, it is possible to correct the imbalance of the surge voltage and loss between the switching elements and improve the power efficiency.

[0058] (2) When transitioning from the third output state to the second dead time, the fifth switching element starts turning off with a delay of at least the time from when the gate voltage of the third switching element starts to decrease until the main current starts to decrease. Or, when transitioning from the third output state to the first dead time, the sixth switching element starts turning off with a delay of at least the time from when the gate voltage of the second switching element starts to decrease until the main current starts to decrease. As a result, since the main current of the third (second) switching element surely starts to decrease before the main current of the fifth (sixth) switching element also decreases, it is possible to prevent the fifth (sixth) switching element from completing the turn-off first, and it becomes possible to surely correct the imbalance.

[0059] (3) When transitioning from the second dead time to the third output state, the fifth switching element starts turning on at least the time from when the gate voltage of the fifth switching element starts to increase until the main current starts to increase, before the third switching element starts turning on. Or, when transitioning from the first dead time to the third output state, the sixth switching element starts turning on at least the time from when the gate voltage of the sixth switching element starts to increase until the main current starts to increase, before the second switching element starts turning on. As a result, similar to (2), it is possible to prevent the third (second) switching element from completing the turn-on first, and it becomes possible to surely correct the imbalance.

[0060] (4) Set the turn-on drive resistance of the fifth switching element to be lower than that of the third switching element so that the turn-on speed of the fifth switching element is faster than that of the third switching element, or set the turn-on drive resistance of the sixth switching element to be lower than that of the second switching element so that the turn-on speed of the sixth switching element is faster than that of the second switching element. Thus, even if the fifth (sixth) switching element and the third (second) switching element are turned on simultaneously, since the fifth (sixth) switching element completes turn-on first, the effects of the present invention can be surely obtained.

[0061] (5) Set the turn-on gate current of the fifth switching element to be higher than that of the third switching element so that the turn-on speed of the fifth switching element is faster than that of the third switching element, or set the turn-on gate current of the sixth switching element to be higher than that of the second switching element so that the turn-on speed of the sixth switching element is faster than that of the second switching element. Thus, similar to (4), even if the fifth (sixth) switching element and the third (second) switching element are turned on simultaneously, since the fifth (sixth) switching element completes turn-on first, the effects of the present invention can be surely obtained.

[0062] (6) Set the turn-off drive resistance of the fifth switching element to be higher than the turn-on drive resistance of the third switching element so that the turn-off speed of the fifth switching element is slower than the turn-off speed of the third switching element, or set the turn-off drive resistance of the sixth switching element to be higher than the turn-off drive resistance of the second switching element so that the turn-off speed of the sixth switching element is slower than the turn-off speed of the second switching element. Thus, even if the fifth (sixth) switching element and the third (second) switching element are turned off simultaneously, since the fifth (sixth) switching element turns off later, the effects of the present invention can be surely obtained.

[0063] (7) Set the turn-off gate current of the fifth switching element to be lower than the turn-on gate current of the third switching element so that the turn-off speed of the fifth switching element is slower than the turn-on speed of the third switching element, or set the turn-off gate current of the sixth switching element to be lower than the turn-off gate current of the second switching element so that the turn-off speed of the sixth switching element is slower than the turn-off speed of the second switching element. Thus, similar to (6), even if the fifth (sixth) switching element and the third (second) switching element are turned off simultaneously, since the fifth (sixth) switching element turns off later, the effects of the present invention can be surely obtained.

[0064] (8) Select the fifth switching element and the third switching element such that the threshold voltage of the fifth switching element is lower than the threshold voltage of the third switching element, or select the sixth switching element and the second switching element such that the threshold voltage of the sixth switching element is lower than the threshold voltage of the second switching element. Thus, similar to the above, since the fifth (sixth) switching element turns on earlier (turns off later) than the third (second) switching element, the effects of the present invention can be surely obtained.

[0065] Adjust the OFF-state gate voltages of the fifth switching element and the third switching element so that the OFF-state gate voltage of the fifth switching element is higher than that of the third switching element, or adjust the OFF-state gate voltages of the sixth switching element and the second switching element so that the OFF-state gate voltage of the sixth switching element is higher than that of the second switching element. Thereby, the same effect as (8) can be obtained.

[0066] As described above, some embodiments of the present invention have been described. However, the present invention is not limited to the above-described embodiments, and can be implemented in various configurations without departing from the spirit thereof. For example, a configuration in which the setting methods of the first to fourth embodiments are arbitrarily combined can also be easily considered. These modifications are included in the invention described in the claims and the equivalent scope thereof.

Description of Reference Numerals

[0067] Vdc1 to Vdc2... DC power supplies, C1 to C2... smoothing capacitors (first and second capacitors), L... load, Q1 to Q6... semiconductor switching elements (first to sixth switching elements)

Claims

1. A power converter that connects a first capacitor and a second capacitor in series between the positive and negative electrodes of a DC power supply, further connects a first to a fourth switching element in series between the positive and negative electrodes of the DC power supply, and connects a fifth switching element between the connection point of the first and second switching elements and the connection point of the first and second capacitors, and connects a sixth switching element between the connection point of the third and fourth switching elements and the connection point of the first and second capacitors, and connects the connection point of the second and third switching elements and a load, wherein a state where the first, second, and sixth switching elements are ON and the third, fourth, and fifth switching elements are OFF is defined as a first output state, a state where the third, fourth, and fifth switching elements are ON and the first, second, and sixth switching elements are OFF is defined as a second output state, and a state where the second, third, fifth, and sixth switching elements are ON and the first and fourth switching elements are OFF is defined as a third output state, a state where the third and fifth switching elements are ON and the first, second, fourth, and sixth switching elements are OFF is defined as a first dead time state, and a state where the second and sixth switching elements are ON and the first, third, fourth, and fifth switching elements are OFF is defined as a second dead time state, the switching between the third output state and the first output state is via the second dead time state, and the switching between the third output state and the second output state is via the first dead time state, when transitioning between the third output state and the second dead time state, the fifth switching element performs at least one of the operations of completing turn-on earlier than the third switching element or completing turn-off with a delay, or when transitioning between the third output state and the first dead time state, the sixth switching element performs at least one of the operations of completing turn-on earlier than the second switching element or completing turn-off with a delay, characterized by the above power converter.

2. The power converter according to Claim 1, wherein When transitioning from the third output state to the second dead time state, the fifth switching element starts turning off with a delay of at least the time from when the gate voltage of the third switching element starts to decrease until the main current starts to decrease, or When transitioning from the third output state to the first dead time state, the sixth switching element starts turning off with a delay of at least the time from when the gate voltage of the second switching element starts to decrease until the main current starts to decrease. A power converter characterized by this.

3. The power converter according to claim 1, When transitioning from the second dead time state to the third output state, the fifth switching element starts turning on at least the time from when the gate voltage of the fifth switching element starts to increase until the main current starts to increase, prior to the start of turn-on of the third switching element, or When transitioning from the first dead time state to the third output state, the sixth switching element starts turning on at least the time from when the gate voltage of the sixth switching element starts to increase until the main current starts to increase, prior to the start of turn-on of the second switching element. A power converter characterized by this.

4. The power converter according to claim 1, The turn-on drive resistance of the fifth switching element is set lower than the turn-on drive resistance of the third switching element so that the turn-on speed of the fifth switching element is faster than the turn-on speed of the third switching element, or The turn-on drive resistance of the sixth switching element is set lower than the turn-on drive resistance of the second switching element so that the turn-on speed of the sixth switching element is faster than the turn-on speed of the second switching element. A power converter characterized by this.

5. The power converter according to claim 1, The turn-on gate current of the fifth switching element is set higher than the turn-on gate current of the third switching element so that the turn-on speed of the fifth switching element is faster than the turn-on speed of the third switching element, or The turn-on gate current of the sixth switching element is set higher than the turn-on gate current of the second switching element so that the turn-on speed of the sixth switching element is faster than the turn-on speed of the second switching element. A power converter characterized by this. **Claim 6** The power converter according to claim 1, The turn-off drive resistance of the fifth switching element is set higher than the turn-on drive resistance of the third switching element so that the turn-off speed of the fifth switching element is slower than the turn-off speed of the third switching element, or The turn-off drive resistance of the sixth switching element is set higher than the turn-off drive resistance of the second switching element so that the turn-off speed of the sixth switching element is slower than the turn-off speed of the second switching element. A power converter characterized by this. **Claim 7** The power converter according to claim 1, The turn-off gate current of the fifth switching element is set lower than the turn-on gate current of the third switching element so that the turn-off speed of the fifth switching element is slower than the turn-on speed of the third switching element, or The turn-off gate current of the sixth switching element is set lower than the turn-off gate current of the second switching element so that the turn-off speed of the sixth switching element is slower than the turn-off speed of the second switching element. A power converter characterized by this. **Claim 8** The power converter according to claim 1, The fifth switching element and the third switching element are selected so that the threshold voltage of the fifth switching element is lower than the threshold voltage of the third switching element, or The sixth switching element and the second switching element are selected so that the threshold voltage of the sixth switching element is lower than the threshold voltage of the second switching element. A power converter characterized by this. **Claim 9** The power converter according to claim 1, The turn-off gate voltages of the fifth switching element and the third switching element are adjusted so that the turn-off gate voltage of the fifth switching element is higher than the turn-off gate voltage of the third switching element, or Adjusting the OFF-state gate voltages of the sixth switching element and the second switching element such that the OFF-state gate voltage of the sixth switching element is higher than the OFF-state gate voltage of the second switching element. A power converter characterized by this.

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