Semiconductor device

Abstract

To provide a semiconductor device of a novel structure, which can retain storage contents even in a situation where power is not supplied during storage retention period and which has no limits on the number of write times.SOLUTION: A semiconductor device comprises a transistor and a capacitative element. The transistor includes a first oxide semiconductor layer, a source electrode and a drain electrode which contact the first oxide semiconductor layer, a gate electrode overlapping the first oxide semiconductor layer and a gate insulation layer provided between the first oxide semiconductor layer and the gate electrode. The capacitative element includes a source electrode or a drain electrode, a second oxide semiconductor layer which contacts the source electrode or the drain electrode and a capacitative element electrode which contacts the second oxide semiconductor layer.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The disclosed invention relates to a semiconductor device using a semiconductor element and a driving method thereof.

Background Art

[0002] Memory devices using semiconductor elements are roughly classified into volatile ones in which stored contents are lost when power supply is cut off, and non-volatile ones in which stored contents are retained even when power supply is cut off.

[0003] A typical example of a volatile memory device is DRAM (Dynamic Random Access Memory). DRAM stores information by selecting a transistor constituting a memory element and accumulating charges in a capacitance element.

[0004] From the above principle, in DRAM, since the charges in the capacitance element are lost when information is read out, a rewrite operation is required again every time information is read out. Also, in the transistor constituting the memory element, due to the leakage current (off-current) between the source and the drain in the off state, etc., charges flow out or flow in even when the transistor is not selected, so the data retention period is short. For this reason, a rewrite operation (refresh operation) is necessary at a predetermined cycle, and it is difficult to reduce power consumption. Also, since stored contents are lost when power supply is cut off, another memory device using a magnetic material or an optical material is required for long-term storage.

[0005] Another example of a volatile memory device is SRAM (Static Random Access ​​There is (a memory). SRAM uses circuits such as flip - flops to retain the stored content, so it does not require a refresh operation and is advantageous over DRAM in this regard. However, because it uses circuits such as flip - flops, there is a problem that the unit price per storage capacity becomes high. Also, in terms of the stored content being lost when the power

[0006] supply is cut off, there is no difference from DRAM. A representative example of a non - volatile memory device is flash memory. Flash memory has a floating gate between the gate electrode and the channel formation region of a transistor, and stores data by holding charges in the floating gate. Therefore, the data retention period is extremely long (semi -

[0007] permanent), and it has the advantage that the refresh operation required for volatile memory devices is unnecessary (see, for example, Patent Document 1). However, the gate insulating layer constituting the memory element deteriorates due to the tunnel current generated during writing, so there is a problem that the memory element stops functioning after a predetermined number of writes. To mitigate the influence of this problem, for example, a technique for

[0008] equalizing the number of writes of each memory element is adopted. However, to realize this, complex peripheral circuits are required. Thus, even if such or it takes a relatively long time for removal, and it is not easy to speed up writing and erasing There is also such a problem.

Prior Art Documents

Patent Documents

[0009]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0010] In view of the above problems, in one aspect of the disclosed invention, the memory content can be retained even in a situation where no power is supplied during the memory retention time, and there is no limit on the number of write operations. One of the objectives is to provide a semiconductor device with a new structure. and there is no limit on the number of write operations, and to provide a semiconductor device with a new structure. One of the purposes is to provide a semiconductor device.

Means for Solving the Problems

[0011] In the disclosed invention, a material capable of sufficiently reducing the off-current of a transistor, for example, an oxide semiconductor material which is a wide-gap semiconductor, is used to form a semiconductor device. By using a semiconductor material capable of sufficiently reducing the off-current of a transistor, it is possible to retain information over a long period of time. Furthermore, since the oxide semiconductor material has a high dielectric constant, by using the oxide semiconductor material as the dielectric of a capacitive element, it is possible to increase the capacitance per unit area. For example, an oxide semiconductor material which is a wide-gap semiconductor is used to form a semiconductor device. By using a semiconductor material capable of sufficiently reducing the off-current of a transistor, it is possible to retain information over a long period of time. Furthermore, since the oxide semiconductor material has a high dielectric constant, by using the oxide semiconductor material as the dielectric of a capacitive element, it is possible to increase the capacitance per unit area.

[0012] One aspect of the present invention has a transistor and a capacitive element. The transistor has a gate electrode, a gate insulating layer on the gate electrode, a first oxide semiconductor layer overlapping the gate electrode on the gate insulating layer, and a source electrically connected to the first oxide semiconductor layer on the first oxide semiconductor layer. a gate insulating layer on the gate electrode, a first oxide semiconductor layer overlapping the gate electrode on the gate insulating layer, and a source electrically connected to the first oxide semiconductor layer on the first oxide semiconductor layer. It has a source electrode and a drain electrode, and the capacitor element is made of the same conductive layer as the source electrode or the drain electrode. A semiconductor device having a first electrode made of the same conductive layer, a second oxide semiconductor layer in contact with the first electrode, and a second electrode in contact with the second oxide semiconductor layer.

[0013] Another aspect of the present invention has a transistor and a capacitor element. The transistor has a gate electrode, a gate insulating layer on the gate electrode, a first oxide semiconductor layer overlapping the gate electrode on the gate insulating layer, a source electrode and a drain electrode electrically connected to the first oxide semiconductor layer on the first oxide semiconductor layer, an insulating layer on the first oxide semiconductor layer, the source electrode, and the drain electrode, and an electrode overlapping the first oxide semiconductor layer on the insulating layer. The capacitor element has a first electrode, a second oxide semiconductor layer in contact with the first electrode, and a second electrode made of the same conductive layer as the source electrode or the drain electrode in contact with the second oxide semiconductor layer.

[0014] Another aspect of the present invention has a transistor and a capacitor element. The transistor has a source electrode and a drain electrode, a first oxide semiconductor layer electrically connected to the source electrode and the drain electrode on the source electrode and the drain electrode, a gate insulating layer on the first oxide semiconductor layer, and a gate electrode overlapping the first oxide semiconductor layer on the gate insulating layer. The capacitor element has a first electrode made of the same conductive layer as the source electrode or the drain electrode, a second oxide semiconductor layer in contact with the first electrode, and a second electrode in contact with the second oxide semiconductor layer.

[0015] Further, a metal oxide layer may be provided between the first electrode and the second oxide semiconductor layer. .

[0016] Further, a metal oxide layer may be provided between the second electrode and the second oxide semiconductor layer. .

[0017] Further, the gate electrode may be formed of an In-Ga-Zn-O-N based compound conductor. It may be.

[0018] Further, the second oxide semiconductor layer may contain one or more elements of silicon, germanium, cerium, titanium, tungsten, aluminum, copper, yttrium, lanthanum, and vanadium at a concentration of 1×10 atoms / cm 20 or more. 3 It may contain.

[0019] Further, the first oxide semiconductor layer and the second oxide semiconductor layer are non-single crystal, and have a triangular or hexagonal atomic arrangement when viewed from the ab plane, and on the c-axis, it contains an oxide semiconductor having a layered metal element or a phase in which a metal element and an oxygen element are layered, or it may contain an oxynitride semiconductor that is non-single crystal, has a triangular or hexagonal atomic arrangement when viewed from the ab plane, and on the c-axis, it contains a layered metal element or a phase in which a metal element and an oxygen element are layered. It may contain. It may contain.

[0020] Further, it may have a transistor, a capacitor element, and a drive circuit composed of a material other than an oxide semiconductor. It may have.

[0021] Note that in the above, a transistor may be formed using an oxide semiconductor, but the disclosed invention is not limited to this. Materials that can achieve off-current characteristics equivalent to those of an oxide semiconductor, For example, a wide-gap semiconductor material having an energy gap Eg greater than 3 electron volts ( more specifically, for example, silicon carbide) may be applied.

[0022] In addition, in this specification and the like, terms such as "upper" and "lower" do not limit the positional relationship of the components to be "directly above" or "directly below". For example, in the expression "gate electrode on the gate insulating layer" excludes those that include other components between the gate insulating layer and the gate electrode.

[0023] Also, in this specification and the like, terms such as "electrode" and "wiring" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where a plurality of "electrodes" and "wirings" are integrally formed.

[0024] Also, the functions of "source" and "drain" may be interchanged when different polarities of transistors are employed or when the direction of current changes in the circuit operation. Therefore, in this specification and the like, the terms "source" and "drain" are assumed to be interchangeable.

[0025] In addition, in this specification and the like, "electrically connected" includes cases where they are connected via "something having some electrical action". Here, "something having some electrical action" is not particularly limited as long as it enables the transfer of electrical signals between the connection targets.

[0026] For example, "something having some electrical action" includes electrodes, wirings, and transistors switching elements, resistor elements, inductors, and other elements with various functions. Included. Effect of the Invention

[0027] Since a transistor using an oxide semiconductor has an extremely low off-state current, It is possible to retain the memory contents for a much longer period of time. This eliminates the need for refresh operations or makes it possible to reduce the frequency of refresh operations to an extremely low level. Therefore, power consumption can be reduced. Also, when there is no power supply (although the potential is Even if the contents are stored in a hard disk (preferably fixed), it is possible to retain the contents for a long period of time. It is possible.

[0028] In addition, since oxide semiconductor materials have a high dielectric constant, they can be used as dielectrics for capacitance elements. By using this, it is possible to increase the capacitance per unit area. Since the area of ​​the quantum elements is reduced, high integration is possible, and the semiconductor device can be made smaller. It is also possible to reduce the frequency of refresh operations and further reduce power consumption. It is.

[0029] In addition, the semiconductor device according to the disclosed invention does not require a high voltage to write information. There is no problem with degradation of the capacitance. For example, unlike conventional non-volatile memory, the floating gate Since there is no need to inject electrons into the floating gate or extract electrons from the floating gate, The problem of deterioration of the gate insulating layer does not occur at all. The device does not have the limit on the number of times it can be rewritten, which is a problem with conventional non-volatile memory, and is reliable. Furthermore, the on and off states of transistors allow the Since writing can be performed, high-speed operation can be easily achieved. Also, there is an advantage that the operation for erasing information is unnecessary.

[0030] Furthermore, transistors using materials other than oxide semiconductors can achieve sufficient high-speed operation, so various circuits (logic circuits, drive circuits, etc.) that require high-speed operation can be preferably realized.

[0031] Therefore, by integrating peripheral circuits such as drive circuits using transistors made of materials other than oxide semiconductors (transistors capable of higher-speed operation than transistors using oxide semiconductors), a memory circuit using transistors made of oxide semiconductors and capacitor elements, a semiconductor device having unprecedented characteristics can be realized.

Brief Description of the Drawings

[0032]

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Mode for Carrying Out the Invention

[0033] An example of an embodiment of the present invention will be described below with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art can easily understand that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not interpreted as being limited to the description of the embodiments shown below.

[0034] In addition, the position, size, range, etc. of each component shown in the drawings and the like may not represent the actual position, size, range, etc. for the sake of easy understanding. For this reason, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings and the like.

[0035] It should be noted that the ordinal numbers such as "first", "second", "third", etc. in this specification and the like are attached to avoid confusion of components, and it is noted that they are not numerically limiting.

[0036] (Embodiment 1) In this embodiment, the configuration and manufacturing method of a semiconductor device according to an aspect of the present invention will be described​​ 、Referring to FIGS. 1 to 3, an explanation will be given.

[0037] 〈Cross-sectional Structure of Semiconductor Device〉 FIG. 1 is an example of the structure of a semiconductor device. FIGS. 1(A) to 1(D) show the cross-section of the semiconductor device. The semiconductor devices shown in FIGS. 1(A) and 1(C) have a transistor 160 using an oxide semiconductor in the channel formation region and a capacitor element 164 using an oxide semiconductor in the dielectric. The semiconductor devices shown in FIGS. 1(B) and 1(D) have a transistor 162 using an oxide semiconductor in the channel formation region and a capacitor element 164 using an oxide semiconductor in the dielectric.

[0038] Note that although the transistor is described as an n-channel type transistor, it goes without saying that a p-channel type transistor can be used. Also, since the technical essence of the disclosed invention lies in using an oxide semiconductor for the transistor 160, the transistor 162, and the capacitor element 164 to hold information, the specific configuration of the semiconductor device does not necessarily have to be limited to what is shown here.

[0039] The transistor 160 in FIG. 1(A) has a gate electrode 148a provided on an insulating layer 140, a gate insulating layer 146 covering the gate electrode 148a, a first oxide semiconductor layer 144a overlapping the gate electrode 148a on the gate insulating layer 146, and a source electrode or drain electrode 142b and a drain electrode or source electrode 142a electrically connected to the first oxide semiconductor layer 144a on the first oxide semiconductor layer 144a. Note that the transistor 160 is not limited to being provided on the insulating layer 140, and it may be, for example, on a substrate having an insulating surface. ​​​​​​​​​​​​​

[0040] In FIG. 1(A), the capacitive element 164 includes a first electrode 148b, a second oxide semiconductor layer 144b in contact with the first electrode 148b, and a source electrode or a drain electrode 142b in contact with the second oxide semiconductor layer 144b. Here, the source electrode or the drain electrode 142b functions as the second electrode of the capacitive element 164. That is to say, it can also be described as follows. The capacitive element 164 includes a first electrode 148b, a second oxide semiconductor layer 144b, and a second electrode. The second electrode is made of the same conductive layer as the source electrode or the drain electrode 142b. Preferably, the work function of the first electrode 148b is larger than the electron affinity of the second oxide semiconductor layer 144b. For example, when an In—Ga—Zn—O-based oxide is used as the second oxide semiconductor layer 144b, its electron affinity is about 4.6 electron volts. In this case, materials having a work function larger than the electron affinity of the second oxide semiconductor layer 144b include indium nitride, zinc nitride, nickel, molybdenum oxide, tungsten oxide, In—Ga—Zn—O—N-based compound conductors, and the like. If (the work function of the first electrode 148b)−(the electron affinity of the second oxide semiconductor layer 144b) is 0.5 electron volts or more, preferably 1 electron volt or more, in most cases, electrons do not flow into the second oxide semiconductor layer 144b. That is, the second oxide semiconductor layer 144b exhibits sufficient insulation and can be used for a capacitive element.

[0041] That is, it can also be said as follows. The capacitive element 164 includes a first electrode 148b, a second oxide semiconductor layer 144b, and a second electrode. The second electrode is made of the same conductive layer as the source electrode or the drain electrode 142b. Preferably, the work function of the first electrode 148b is larger than the electron affinity of the second oxide semiconductor layer 144b. For example, when an In—Ga—Zn—O-based oxide is used as the second oxide semiconductor layer 144b, its electron affinity is about 4.6 electron volts. In this case, materials having a work function larger than the electron affinity of the second oxide semiconductor layer 144b include indium nitride, zinc nitride, nickel, molybdenum oxide, tungsten oxide, In—Ga—Zn—O—N-based compound conductors, and the like. If (the work function of the first electrode 148b)−(the electron affinity of the second oxide semiconductor layer 144b) is 0.5 electron volts or more, preferably 1 electron volt or more, in most cases, electrons do not flow into the second oxide semiconductor layer 144b. That is, the second oxide semiconductor layer 144b exhibits sufficient insulation and can be used for a capacitive element.

[0042] Preferably, the work function of the first electrode 148b is larger than the electron affinity of the second oxide semiconductor layer 144b. For example, when an In—Ga—Zn—O-based oxide is used as the second oxide semiconductor layer 144b, its electron affinity is about 4.6 electron volts. In this case, materials having a work function larger than the electron affinity of the second oxide semiconductor layer 144b include indium nitride, zinc nitride, nickel, molybdenum oxide, tungsten oxide, In—Ga—Zn—O—N-based compound conductors, and the like. If (the work function of the first electrode 148b)−(the electron affinity of the second oxide semiconductor layer 144b) is 0.5 electron volts or more, preferably 1 electron volt or more, in most cases, electrons do not flow into the second oxide semiconductor layer 144b. That is, the second oxide semiconductor layer 144b exhibits sufficient insulation and can be used for a capacitive element. Preferably, the work function of the first electrode 148b is larger than the electron affinity of the second oxide semiconductor layer 144b. For example, when an In—Ga—Zn—O-based oxide is used as the second oxide semiconductor layer 144b, its electron affinity is about 4.6 electron volts. In this case, materials having a work function larger than the electron affinity of the second oxide semiconductor layer 144b include indium nitride, zinc nitride, nickel, molybdenum oxide, tungsten oxide, In—Ga—Zn—O—N-based compound conductors, and the like. If (the work function of the first electrode 148b)−(the electron affinity of the second oxide semiconductor layer 144b) is 0.5 electron volts or more, preferably 1 electron volt or more, in most cases, electrons do not flow into the second oxide semiconductor layer 144b. That is, the second oxide semiconductor layer 144b exhibits sufficient insulation and can be used for a capacitive element. Preferably, the work function of the first electrode 148b is larger than the electron affinity of the second oxide semiconductor layer 144b. For example, when an In—Ga—Zn—O-based oxide is used as the second oxide semiconductor layer 144b, its electron affinity is about 4.6 electron volts. In this case, materials having a work function larger than the electron affinity of the second oxide semiconductor layer 144b include indium nitride, zinc nitride, nickel, molybdenum oxide, tungsten oxide, In—Ga—Zn—O—N-based compound conductors, and the like. If (the work function of the first electrode 148b)−(the electron affinity of the second oxide semiconductor layer 144b) is 0.5 electron volts or more, preferably 1 electron volt or more, in most cases, electrons do not flow into the second oxide semiconductor layer 144b. That is, the second oxide semiconductor layer 144b exhibits sufficient insulation and can be used for a capacitive element.

[0043] (The work function of the first electrode 148b)−(the electron affinity of the second oxide semiconductor layer 144b) is 0.5 electron volts or more, preferably 1 electron volt or more, then in most cases, electrons do not flow into the second oxide semiconductor layer 144b. That is, the second oxide semiconductor layer 144b exhibits sufficient insulation and can be used for a capacitive element. That is, the second oxide semiconductor layer 144b exhibits sufficient insulation and can be used for a capacitive element. That is, the second oxide semiconductor layer 144b exhibits sufficient insulation and can be used for a capacitive element.

[0044] (Work function of the first electrode 148b)-(Electron affinity of the second oxide semiconductor layer 144b) Even if the potential is 0.5 eV or more, the potential may vary depending on the material of the source electrode or drain electrode 142b. As a result, electrons are transferred from the source or drain electrode 142b to the second oxide semiconductor layer 144b. This is because the work function of the source or drain electrode 142b is This can occur when the electron affinity of the second oxide semiconductor layer 144b is smaller than that of the second oxide semiconductor layer 144b. In this case, the voltage applied to the first electrode 148b and the source or drain electrode 142b and Depending on the voltage and polarity, it can function as a capacitance element without causing the inflow of electrons. However, if the source electrode or drain electrode 142b is made of the same material as the first electrode 148b, If the material is made of the materials listed above or materials with equivalent or higher work functions, the voltage and It can be used as a capacitive element regardless of its polarity.

[0045] Here, the first oxide semiconductor layer 144a and the second oxide semiconductor layer 144b are formed of hydrogen or the like. It is preferable that the impurities are sufficiently removed to achieve a high level of purity. In addition, the supply of sufficient oxygen reduces the defect levels in the energy gap. Specifically, for example, the first oxide semiconductor layer 144a and the second oxide semiconductor layer The hydrogen concentration in the oxide semiconductor layer 144b is 5×10 19 atoms / cm 3 The following is preferable: 5×10 18 atoms / cm 3 Less than or equal to 5×10 17 atoms / cm 3 The above-mentioned first oxide semiconductor layer 144a and the second oxide semiconductor layer 1 The hydrogen concentration in 44b was measured by secondary ion mass spectrometry (SIMS). Thus, in the first oxide semiconductor layer 144a and the second oxide semiconductor layer 144b in which the hydrogen concentration is sufficiently reduced to achieve high purity and the defect levels in the energy gap due to oxygen deficiency are reduced by sufficient supply of oxygen, the carrier concentration is less than 1×10 / cm , desirably less than 1×1 0 12 / cm 3 , more desirably less than 1.45×10 0 11 / cm 3 . For example, 10 / cm 3 The off-current (the value obtained by dividing the off-current by the channel width of the transistor) at room temperature is on the order of 10 zA / μm to 100 zA / μm (1 zA (zeptoampere) is 1×10 A). -21 As such, by using an i-type (intrinsic) or substantially i-type oxide semiconductor, a transistor 160 with extremely excellent off-current characteristics can be obtained. Also, when the oxide semiconductor layer is i-type (intrinsic) or substantially i-type, the dielectric constant can be increased. Specifically, the relative dielectric constant of the In-Ga-Zn-O-based oxide semiconductor layer can be set to about 15. This is sufficiently higher compared to the relative dielectric constant of silicon oxide being about 4.

[0046] Therefore, by using an i-type (intrinsic) or substantially i-type oxide semiconductor layer as the dielectric of the capacitor element 164, the capacitance per unit area of the capacitor element 164 can be increased.

[0047] Also, the oxide semiconductor layer can be single crystal, polycrystalline (also referred to as polycrystal), or amorphous. Which state to take.

[0048] Preferably, the oxide semiconductor layer is a CAAC-OS (C Axis Aligned Cr ystalline Oxide Semiconductor) layer.

[0049] The CAAC-OS layer is neither a perfect single crystal nor a perfect amorphous material. The CAAC-OS layer is an oxide semiconductor layer having a crystal-amorphous mixed-phase structure with crystal parts in an amorphous phase. Note that the crystal parts are often sized to fit within a cube with a side length of less than 100 nm. Also, in an observation image by a transmission electron microscope (TEM: Transmission Electron Micro scope), the boundary between the amorphous part and the crystal part contained in the CAAC-OS layer is not clear. Also, grain boundaries (also referred to as grain boundaries.) cannot be confirmed in the CAAC-OS layer by TEM. Therefore, in the CAAC-OS layer, the reduction in electron mobility due to grain boundaries is suppressed.

[0050] The crystal parts contained in the CAAC-OS layer have their c-axes aligned in a direction parallel to the normal vector of the surface to be formed of the CAAC-OS layer or the normal vector of the surface, and when viewed from a direction perpendicular to the ab plane, they have a trigonal or hexagonal atomic arrangement, and when viewed from a direction perpendicular to the c-axis, the metal atoms are arranged in layers or the metal atoms and oxygen atoms are arranged in layers. Note that the directions of the a axis and b axis may be different between different crystal parts. In this specification, when simply described as perpendicular, the range of 85° or more and 95° or less is also included.

[0051] Note that in the CAAC-OS layer, the distribution of the crystal parts may not be uniform. For example, CAA ​​​When growing crystals from the surface side of the oxide semiconductor layer in the process of forming the CAAC-OS layer, the proportion of the crystal part may be higher near the surface than near the formation surface. Also, by adding impurities to the CAAC-OS layer, the crystal part may be amorphous in the impurity addition region. The c-axis of the crystal part included in the CAAC-OS layer aligns in a direction parallel to the normal vector of the formation surface or the normal vector of the surface of the CAAC-OS layer. Therefore, depending on the shape of the CAAC-OS layer (the cross-sectional shape of the formation surface or the cross-sectional shape of the surface), they may face different directions. Also, the direction of the c-axis of the crystal part is parallel to the normal vector of the formation surface or the normal vector of the surface when the CAAC-OS layer is formed. The crystal part is formed by film formation or by performing a crystallization process such as heat treatment after film formation. When growing crystals from the surface side of the oxide semiconductor layer in the process of forming the CAAC-OS layer, the proportion of the crystal part may be higher near the surface than near the formation surface. Also, by adding impurities to the CAAC-OS layer, the crystal part may be amorphous in the impurity addition region. When growing crystals from the surface side of the oxide semiconductor layer in the process of forming the CAAC-OS layer, the proportion of the crystal part may be higher near the surface than near the formation surface. Also, by adding impurities to the CAAC-OS layer, the crystal part may be amorphous in the impurity addition region.

[0052] The c-axis of the crystal part included in the CAAC-OS layer aligns in a direction parallel to the normal vector of the formation surface or the normal vector of the surface of the CAAC-OS layer. Therefore, depending on the shape of the CAAC-OS layer (the cross-sectional shape of the formation surface or the cross-sectional shape of the surface), they may face different directions. Also, the direction of the c-axis of the crystal part is parallel to the normal vector of the formation surface or the normal vector of the surface when the CAAC-OS layer is formed. The crystal part is formed by film formation or by performing a crystallization process such as heat treatment after film formation. The c-axis of the crystal part included in the CAAC-OS layer aligns in a direction parallel to the normal vector of the formation surface or the normal vector of the surface of the CAAC-OS layer. Therefore, depending on the shape of the CAAC-OS layer (the cross-sectional shape of the formation surface or the cross-sectional shape of the surface), they may face different directions. Also, the direction of the c-axis of the crystal part is parallel to the normal vector of the formation surface or the normal vector of the surface when the CAAC-OS layer is formed. The crystal part is formed by film formation or by performing a crystallization process such as heat treatment after film formation. The c-axis of the crystal part included in the CAAC-OS layer aligns in a direction parallel to the normal vector of the formation surface or the normal vector of the surface of the CAAC-OS layer. Therefore, depending on the shape of the CAAC-OS layer (the cross-sectional shape of the formation surface or the cross-sectional shape of the surface), they may face different directions. Also, the direction of the c-axis of the crystal part is parallel to the normal vector of the formation surface or the normal vector of the surface when the CAAC-OS layer is formed. The crystal part is formed by film formation or by performing a crystallization process such as heat treatment after film formation. The c-axis of the crystal part included in the CAAC-OS layer aligns in a direction parallel to the normal vector of the formation surface or the normal vector of the surface of the CAAC-OS layer. Therefore, depending on the shape of the CAAC-OS layer (the cross-sectional shape of the formation surface or the cross-sectional shape of the surface), they may face different directions. Also, the direction of the c-axis of the crystal part is parallel to the normal vector of the formation surface or the normal vector of the surface when the CAAC-OS layer is formed. The crystal part is formed by film formation or by performing a crystallization process such as heat treatment after film formation. The c-axis of the crystal part included in the CAAC-OS layer aligns in a direction parallel to the normal vector of the formation surface or the normal vector of the surface of the CAAC-OS layer. Therefore, depending on the shape of the CAAC-OS layer (the cross-sectional shape of the formation surface or the cross-sectional shape of the surface), they may face different directions. Also, the direction of the c-axis of the crystal part is parallel to the normal vector of the formation surface or the normal vector of the surface when the CAAC-OS layer is formed. The crystal part is formed by film formation or by performing a crystallization process such as heat treatment after film formation. The c-axis of the crystal part included in the CAAC-OS layer aligns in a direction parallel to the normal vector of the formation surface or the normal vector of the surface of the CAAC-OS layer. Therefore, depending on the shape of the CAAC-OS layer (the cross-sectional shape of the formation surface or the cross-sectional shape of the surface), they may face different directions. Also, the direction of the c-axis of the crystal part is parallel to the normal vector of the formation surface or the normal vector of the surface when the CAAC-OS layer is formed. The crystal part is formed by film formation or by performing a crystallization process such as heat treatment after film formation.

[0053] A transistor using the CAAC-OS layer can reduce fluctuations in electrical characteristics due to irradiation with visible light or ultraviolet light. Therefore, the transistor has high reliability. A transistor using the CAAC-OS layer can reduce fluctuations in electrical characteristics due to irradiation with visible light or ultraviolet light. Therefore, the transistor has high reliability.

[0054] Also, part of the oxygen constituting the oxide semiconductor layer may be replaced with nitrogen.

[0055] Also, the second oxide semiconductor layer 144b may contain more oxygen than the stoichiometric composition ratio. Also, it may contain any one or more elements of metals such as silicon, germanium, and cerium, titanium, tungsten, aluminum, copper, yttrium, lanthanum, vanadium, etc. By containing these elements, the insulating property of the second oxide semiconductor layer 144b can be enhanced. Also, the second oxide semiconductor layer 144b may contain more oxygen than the stoichiometric composition ratio. Also, it may contain any one or more elements of metals such as silicon, germanium, and cerium, titanium, tungsten, aluminum, copper, yttrium, lanthanum, vanadium, etc. By containing these elements, the insulating property of the second oxide semiconductor layer 144b can be enhanced. Also, the second oxide semiconductor layer 144b may contain more oxygen than the stoichiometric composition ratio. Also, it may contain any one or more elements of metals such as silicon, germanium, and cerium, titanium, tungsten, aluminum, copper, yttrium, lanthanum, vanadium, etc. By containing these elements, the insulating property of the second oxide semiconductor layer 144b can be enhanced. Also, the second oxide semiconductor layer 144b may contain more oxygen than the stoichiometric composition ratio. Also, it may contain any one or more elements of metals such as silicon, germanium, and cerium, titanium, tungsten, aluminum, copper, yttrium, lanthanum, vanadium, etc. By containing these elements, the insulating property of the second oxide semiconductor layer 144b can be enhanced. Also, the second oxide semiconductor layer 144b may contain more oxygen than the stoichiometric composition ratio. Also, it may contain any one or more elements of metals such as silicon, germanium, and cerium, titanium, tungsten, aluminum, copper, yttrium, lanthanum, vanadium, etc. By containing these elements, the insulating property of the second oxide semiconductor layer 144b can be enhanced.

[0056] For silicon, germanium, and metal elements, the concentration is 1×10 20 at oms / cm 3 or more, preferably 1×10 21 atoms / cm 3 or more, more preferably 5×10 21 atoms / cm 3 or more.

[0057] In the transistor 160 and the capacitor element 164, the end portions of the gate electrode 148a, the first electrode 148b, the gate insulating layer 146, the first oxide semiconductor layer 144a, and the second oxide semiconductor layer 144b are preferably tapered. Here, the taper angle is , for example, 30° or more and 60° or less. The taper angle refers to the inclination angle formed by the side surface and the bottom surface of the layer having a tapered shape (for example, the gate electrode 148a) when observed from a direction perpendicular to the cross-section (a plane perpendicular to the surface of the substrate). By forming the end portions of the gate electrode 148a, the first electrode 148b, the gate insulating layer 146, the first oxide semiconductor layer 144a, and the second oxide semiconductor layer 144b into a tapered shape, the coverage of the source electrode or the drain electrode 142b and the drain electrode or the source electrode 142a can be improved, and step discontinuity can be prevented.

[0058] An insulating layer 150 is provided over the transistor 160 and the capacitor element 164.

[0059] The transistor 162 and the capacitor element 164 shown in FIG. 1(B) are modified examples of the transistor 160 and the capacitor element 164 shown in FIG. 1(A).

[0060] The difference between the configuration shown in FIG. 1A and the configuration shown in FIG. 1B is the transistor 162 is at the point including the electrode 152 on the insulating layer 150. The transistor 162 has a channel Above and below the first oxide semiconductor layer 144a having the formation region, two gate electrodes are provided via an insulating layer. The transistor is a dual-gate transistor having an electrode layer. 162 is a gate electrode 148a, a gate insulating layer 146 on the gate electrode 148a, and a gate A first oxide semiconductor layer 144a overlapping the gate electrode 148a on the gate insulating layer 146; A source electrically connected to the first oxide semiconductor layer 144a on the second oxide semiconductor layer 144a is The semiconductor device has a source electrode or drain electrode 142b and a drain electrode or source electrode 142a. Further, the first oxide semiconductor layer 144a, the source or drain electrode 142b, and and an insulating layer 150 on the drain or source electrode 142a, and a first and an electrode 152 overlapping with the oxide semiconductor layer 144a.

[0061] In FIG. 1B, the gate electrode 148a and the electrode 152 function together as a gate electrode. The potential of the electrode 152 may be the same as or different from that of the gate electrode 148a. The gate electrode 148a and the gate electrode 148b may be connected to GND, 0V, or may be in a floating state. The electrode 152 controls the electric field applied to the first oxide semiconductor layer 144a. The threshold voltage of the transistor 162 can be controlled.

[0062] The transistor 160 and the capacitor 164 shown in FIG. 1 is a modified example of the capacitor 160 and the capacitive element 164.

[0063] The difference between the configuration shown in FIG. 1(A) and the configuration shown in FIG. 1(C) lies in the capacitive element 16 of FIG. 1(C). In 4, the first electrode 148b has a metal oxide layer 149b on the surface in contact with the second oxide semiconductor layer 144b. Furthermore, in the capacitive element 164 of FIG. 1(C), the source electrode or the drain electrode 142b has a metal oxide layer 141b on the surface in contact with the second oxide semiconductor layer 144b. Furthermore, in the transistor 160 of FIG. 1(C), the drain electrode or the source electrode 142a may have a metal oxide layer 141a on the surface in contact with the first oxide semiconductor layer 144a.

[0064] When the second oxide semiconductor layer 144b is in contact with the first electrode 148b, oxygen may be taken away from the second oxide semiconductor layer 144b by the first electrode 148b. When oxygen is taken away from the second oxide semiconductor layer 144b, the oxygen deficiency increases. When the oxygen deficiency in the second oxide semiconductor layer 144b increases, its conductivity increases, and there is a risk that it will no longer function as a dielectric of the capacitive element.

[0065] Therefore, it is preferable to use the first electrode 148b having the metal oxide layer 149b in contact with the second oxide semiconductor layer 144b. The metal oxide layer 149b can prevent oxygen from being taken away from the second oxide semiconductor layer 144b by the first electrode 148b. Furthermore, oxygen can be supplied from the metal oxide layer 149b to the second oxide semiconductor layer 144b to further reduce the oxygen deficiency in the second oxide semiconductor layer 144b.

[0066] Also, the metal oxide layer 141b and the metal oxide layer 141a are preferably layers of highly conductive metal oxides. By using a layer with a high conductivity, the capacitive element 164 and the transistor​​​​​​​​ The electrical connection with the terminal 160 can be kept in good condition.

[0067] Also, when the second oxide semiconductor layer 144b is in contact with the source electrode or the drain electrode 142b oxygen may be taken away from the second oxide semiconductor layer 144b by the source electrode or the drain electrode 142b. When oxygen is taken away from the second oxide semiconductor layer 144b, oxygen deficiency increases. When the oxygen deficiency of the second oxide semiconductor layer 144b increases, its conductivity increases and it may no longer function as a dielectric of the capacitive element.

[0068] Therefore, it is preferable that the source electrode or the drain electrode 142b has a metal oxide layer 141b in contact with the second oxide semiconductor layer 144b. The metal oxide layer 141b can prevent oxygen from being taken away from the second oxide semiconductor layer 144b by the source electrode or the drain electrode 142b. Also, the drain electrode or the source electrode 142a having a metal oxide layer 141a in contact with the first oxide semiconductor layer 144a may be used. Note that the drain electrode or the source electrode 142a can be formed simultaneously with the metal oxide layer 141b. By forming the metal oxide layer 141b and the metal oxide layer 141a, oxygen can be supplied to the first oxide semiconductor layer 144a and the second oxide semiconductor layer 144b, and the oxygen deficiency of the first oxide semiconductor layer 144a and the second oxide semiconductor layer 144b can be further reduced. The metal oxide layer 141b and the metal oxide layer 141a supply oxygen to the first oxide semiconductor layer 144a and the second oxide semiconductor layer 144b, and the oxygen deficiency of the first oxide semiconductor layer 144a and the second oxide semiconductor layer 144b can be further reduced. .

[0069] Whether oxygen is taken away from the second oxide semiconductor layer 144b or not may depend on conditions in subsequent processes and the like. When oxygen is not taken away from the second oxide semiconductor layer 144b, the metal It is not necessary to form the oxide layer 149b and the metal oxide layer 141b.

[0070] In addition, in FIG. 1(C), the case of having the metal oxide layer 149b and the metal oxide layer 141b is illustrated, but it is not limited thereto. It may have only the metal oxide layer 149b or only the metal oxide layer 141b. Having only the metal oxide layer 149b or only the metal oxide layer 141b is preferable because the capacitance per unit area becomes larger.

[0071] The transistor 162 and the capacitor element 164 shown in FIG. 1(D) are modified examples of the transistor 160 and the capacitor element 164 in FIG. 1(C).

[0072] The difference between the configuration shown in FIG. 1(C) and the configuration shown in FIG. 1(D) is that the transistor 162 in FIG. 1(D) includes the electrode 152 on the insulating layer 150. The transistor 162 is a dual-gate transistor having two gate electrode layers arranged via insulating layers above and below the channel region. Specifically, the transistor 162 has a gate electrode 148a, a first oxide semiconductor layer 144a on the gate electrode 148a, and a source electrode or drain electrode 142b and a drain electrode or source electrode 142a electrically connected to the first oxide semiconductor layer 144a on the first oxide semiconductor layer 144a. Further, it has an insulating layer 150 on the first oxide semiconductor layer 144a, the source electrode or drain electrode 142b, and the drain electrode or source electrode 142a, and an electrode 152 overlapping the first oxide semiconductor layer 144a on the insulating layer 150.

[0073] In FIG. 1(D), both the gate electrode 148a and the electrode 152 function as gate electrodes. ​​​​​​​​The potential of the electrode 152 may be the same as or different from that of the gate electrode 148a, and may be GND, 0V, or in a floating state. By controlling the electric field applied to the first oxide semiconductor layer 144a by the gate electrode 148a and the electrode 152, the threshold voltage of the transistor 162 can be controlled.

[0074] <Method for manufacturing a semiconductor device> Next, a method for manufacturing the transistors 160 and 162 shown in FIGS. 1(A) and 1(B) will be described with reference to FIGS. 2 to 3.

[0075] First, a conductive layer is formed on the insulating layer 140, and the conductive layer is processed to form the first electrode 148b and the gate electrode 148a (see FIG. 2(A)).

[0076] The insulating layer 140 is formed using a material containing an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, etc. Also, the insulating layer 140 can be formed using an organic insulating material such as polyimide or acrylic. The insulating layer 1 40 can be formed in a single-layer structure or a laminated structure using the above-described materials. In the present embodiment form, the case where silicon oxide is used as the insulating layer 140 will be described.

[0077] Note that the locations where the transistors 160 and 162 are formed are not limited to above the insulating layer 140. For example, it may be fabricated on a substrate having an insulating surface. As the substrate, an insulating substrate made of an insulator such as a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, etc., or a semiconductor substrate made of a semiconductor material such as silicon, or a conductive substrate made of a conductor such as metal or stainless steel ​Substrates, those with their surfaces coated with insulating materials, etc. can be used. Also, Flexible substrates such as plastic sticks generally tend to have a low heat resistance temperature, but can be used if they can withstand subsequent manufacturing processes.

[0078] The first electrode 148b and the gate electrode 148a can be formed using metal materials such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, neodymium, scandium, or alloy materials mainly composed of these. Note that the first electrode 148b and the gate electrode 148a may have a single-layer structure or a laminated structure. For example, a two-layer structure with copper laminated on a copper-magnesium-aluminum alloy layer can also be used, or a three-layer structure with molybdenum, aluminum, and molybdenum laminated in that order can also be used.

[0079] Also, the first electrode 148b and the gate electrode 148a may be formed using materials with a large work function such as In-Ga-Zn-O-N-based compound conductors. By using a material with a large work function such as an In-Ga-Zn-O-N-based compound conductor for the gate electrode 148a, electrical characteristics such as the threshold voltage of the transistor 160 can be controlled.

[0080] Next, an insulating layer is formed, and the insulating layer is processed to form a gate insulating layer 146 that covers the gate electrode 148a (see Fig. 2(B)). The insulating layer is processed to remove the insulating layer from above the first electrode 148b, so that the first electrode 148b can be provided in contact with the second oxide semiconductor layer 144b formed later. Thereby, the layer that functions as the dielectric of the capacitor element 164 can be made only the second oxide semiconductor layer 144b. Thereby, the dielectric​​​​​​​​​​​​ When used by laminating an insulating layer and a second oxide semiconductor layer 144b as an electric body, compared with the case of using them laminated, the dielectric of the capacitance element 164 can be formed thinner. By forming the dielectric of the capacitance element 164 thinner, the capacitance per unit area of the capacitance element 164 can be increased.

[0081] The gate insulating layer 146 can be formed using a CVD method, a sputtering method, or the like. Also, the gate insulating layer 146 is preferably formed to contain silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or the like. The gate insulating layer 146 may have a single-layer structure, or may have a laminated structure by combining the above materials. Also, its thickness is not particularly limited, but when miniaturizing the semiconductor device, it is desirable to make it thinner in order to ensure the operation of the transistor. For example, when using silicon oxide, it can be 1 nm or more and 100 nm or less, preferably 10 nm or more and 50 nm or less.

[0082] Also, an insulating material containing a group 13 element and oxygen may be used for the gate insulating layer 146. Many oxide semiconductor materials contain a group 13 element, and an insulating material containing a group 13 element has good compatibility with an oxide semiconductor. By using this for an insulating layer in contact with the oxide semiconductor layer, the state of the interface with the oxide semiconductor layer can be kept good. Here, the insulating material containing a group 13 element means that the insulating material contains one or a plurality of group 13 elements. Examples of the insulating material containing a group 13 element include aluminum oxide. Since aluminum oxide has the property of being difficult to transmit water, using this material is also preferable in terms of preventing water from entering the oxide semiconductor layer.

[0083] In addition, the insulating layer in contact with the first oxide semiconductor layer 144a is preferably in a state where oxygen is more abundant than the stoichiometric composition ratio by means of heat treatment in an oxygen atmosphere, addition of oxygen, etc. The addition of oxygen can be carried out using doping, ion implantation, ion doping, etc. Doping with oxygen means adding oxygen to the bulk. Here, the term "bulk" is used to clarify that oxygen is added not only to the surface of the thin layer but also to the inside of the thin layer. Also, oxygen doping includes oxygen plasma doping in which plasmaized oxygen is added to the bulk. For example, when aluminum oxide is used as the insulating layer in contact with the first oxide semiconductor layer 144a, by performing heat treatment in an oxygen atmosphere or oxygen doping, the composition of aluminum oxide can be made Al

[0084] O (X = 3 + α, 0 < α < 1). 2 O X

[0085] By performing oxygen doping treatment, etc., an insulating layer having a region where oxygen is more abundant than the stoichiometric composition ratio can be formed. When such an insulating layer having such a region is in contact with the oxide semiconductor layer, excess oxygen in the insulating layer is supplied to the oxide semiconductor layer, reducing oxygen defects in the oxide semiconductor layer and at the interface between the oxide semiconductor layer and the insulating layer, and the oxide semiconductor layer can be made into an i-type or made as close as possible to an i-type.

[0086] Note that the insulating layer having a region where oxygen is more abundant than the stoichiometric composition ratio may be applied to the insulating layer formed as the underlying layer of the transistor 160 instead of the gate insulating layer 146, may be applied to the insulating layer 150 fabricated in a later process, or may be applied to a plurality or all of these. ​​​​​​​​​​​​ .

[0087] In this embodiment, silicon oxide formed by a sputtering method and having a thickness of 10 nm or more and 50 nm or less is used as the gate insulating layer 146.

[0088] Next, an oxide semiconductor layer is formed, and the oxide semiconductor layer is processed to form a first oxide semiconductor layer 144a so as to overlap with the gate electrode 148a on the gate insulating layer 146. At the same time, a second oxide semiconductor layer 144b is formed in contact with the first electrode 148b or the metal oxide layer 149b (see FIG. 2(C)).

[0089] As the material used for the oxide semiconductor layer, quaternary metal oxides such as In-Sn-Ga-Zn-O-based oxides, ternary metal oxides such as In-Ga-Zn-O-based oxides, In-Sn-Zn-O-based oxides, In-Al-Zn-O-based oxides, Sn-Ga-Zn-O-based oxides, Al-Ga-Zn-O-based oxides, Sn-Al-Zn-O-based oxides, binary metal oxides such as In-Zn-O-based oxides, Sn-Zn-O-based oxides, Al-Zn-O-based oxides, Zn-Mg-O-based oxides, Sn-Mg-O-based oxides, In-Mg-O-based oxides, In-Ga-O-based oxides, In-O-based oxides, Sn-O-based oxides, Zn-O-based oxides, etc. can be used. Further, SiO may be included in the above materials. Here, for example, the In-Ga-Zn-O-based oxide means an oxide layer having indium (In), gallium (Ga), and zinc (Zn), and its composition ratio is not particularly limited. Further, elements other than In, Ga, and Zn may be included. 2

[0090] Also, the thickness of the oxide semiconductor layer is desirably 3 nm or more and 30 nm or less. When the oxide semiconductor layer is made too thick (for example, 50 nm or more), the transistor may become normally-on because of this. Also, the capacitance of the capacitive element 164 becomes small as compared with the thickness of the second oxide semiconductor layer 144b.

[0091] The oxide semiconductor layer is desirably manufactured in a manner that makes it difficult for impurities such as hydrogen, water, hydroxyl groups, or hydrides to be incorporated. The oxide semiconductor layer can be manufactured using, for example, a sputtering method.

[0092] In this embodiment, the oxide semiconductor layer is formed by a sputtering method using a target of In-Ga-Zn-O-based oxide.

[0093] As the target of In-Ga-Zn-O-based oxide, for example, an oxide target having a composition ratio of In 2 O 3 :Ga 2 O 3 :ZnO = 1:1:1 [mole ratio] can be used. Note that the material and composition of the target do not necessarily have to be limited as described above. For example, an oxide target having a composition 2 O 3 :Ga 2 O 3 :ZnO = 1:1:2 [mole ratio] can also be used. The relative density of the oxide target is 90% or more and 100% or less, preferably 95% or more and

[0094] 99.9% or less. By using a metal oxide target having a high relative density, the formed oxide semiconductor layer can be made into a dense layer because of this.

[0095] ​ Further, the oxide semiconductor layer is preferably a CAAC-OS layer. The i-type (intrinsic semiconductor) or substantially i-type CAAC-OS layer with reduced impurities and added oxygen can be formed, for example, as follows.

[0096] First, a first oxide semiconductor layer is formed on a substrate by a sputtering method, a molecular beam epitaxy method, an atomic layer deposition method, or a pulsed laser deposition method. When forming, the substrate is heated so that an oxide semiconductor layer with a higher proportion of crystal regions to amorphous regions can be obtained. For example, the substrate temperature may be 150°C or higher and 450°C or lower. Preferably, the substrate temperature is 200°C or higher and 250°C or lower. By increasing the substrate temperature, the oxide of CAAC-OS can be further crystallized.

[0097]

[0098] Next, a first heat treatment may be performed on the substrate. By performing the first heat treatment, an oxide semiconductor layer with a higher proportion of crystal regions to amorphous regions can be obtained. The first heat treatment may be performed, for example, at 200°C or higher and below the strain point of the substrate. Preferably, it is 200°C or higher and 250°C or lower. By performing the heat treatment, substances containing hydrogen atoms included in the oxide semiconductor layer can be further removed. The atmosphere is not limited, but it is performed in an oxidizing atmosphere, an inert atmosphere, or a reduced-pressure atmosphere. The treatment time is 3 minutes to 24 hours. The longer the treatment time, the more an oxide semiconductor layer with a higher proportion of crystal regions to amorphous regions can be formed, but a heat treatment exceeding 24 hours is not preferable because it causes a decrease in productivity.

[0099] ​​​​​​​​​​​​​​An oxidizing atmosphere is an atmosphere containing an oxidizing gas. The oxidizing gas is oxygen, ozone, or nitrous oxide, etc., and preferably does not contain water, hydrogen, etc. For example, the purity of oxygen, ozone, and nitrous oxide introduced into the heat treatment equipment is 8N (99.999999%) or more, preferably 9N (99.9999999%) or more. The oxidizing atmosphere may be used by mixing an oxidizing gas with an inert gas. In that case, it is assumed that the oxidizing gas is contained at least at 10 ppm or more.

[0100] Here, the inert atmosphere is an atmosphere mainly composed of an inert gas such as nitrogen, rare gas (helium, neon, argon, krypton, xenon), etc. Specifically, it is an atmosphere in which the reactive gas such as an oxidizing gas is less than 10 ppm.

[0101] The first heat treatment can use an RTA (Rapid Thermal Anneal) apparatus. By using RTA, it is possible to perform heat treatment at a temperature equal to or higher than the strain point of the substrate for a limited time. Therefore, the time required to form an oxide semiconductor layer having a higher ratio of the crystalline region to the amorphous region can be shortened.

[0102] As the oxide, a material represented by the chemical formula InMO 3 (ZnO) m (m>0) may be used. Here, M represents one or more metal elements selected from Ga, Al, Mn, and Co. For example, as M, Ga, Ga and Al, Ga and Mn, or Ga and Co etc. may be used.

[0103] Also, nitrogen is 5×10 19 / cm 3 or more, preferably 1×10 20 / cm​​​3 7 atomic % or more The In-Ga-Zn-O-based oxide containing less than 7 atomic % forms an oxide containing a c-axis-oriented hexagonal crystal structure, and between the In-O crystal plane (the crystal plane containing indium and oxygen) and the In-O crystal plane, a layer having a single layer of Ga and Zn is provided. Alternatively, in the In-Ga-Zn-O-based oxide containing nitrogen within the above range, between the In-O crystal plane and the In-O crystal plane, a layer having a plurality of layers of Ga and Zn may be provided.

[0104] Further, a second oxide semiconductor layer may be formed on the first oxide semiconductor layer to form an oxide laminate. The first oxide semiconductor layer and the second oxide semiconductor layer can be formed by the same method.

[0105] When forming the second oxide semiconductor layer, by forming while heating the substrate, the second oxide semiconductor layer can be crystallized with the first oxide semiconductor layer as a seed crystal.

[0106] Note that after forming the second oxide semiconductor layer, a second heat treatment may be performed. The second heat treatment may be performed in the same manner as the first heat treatment. By performing the second heat treatment, an oxide laminate with a higher ratio of crystal regions to amorphous regions can be obtained. Alternatively, by performing the second heat treatment, the second oxide semiconductor layer can be crystallized with the first oxide semiconductor layer as a seed crystal. At this time, it may be homoepitaxial growth composed of the same element for the first oxide semiconductor layer and the second oxide semiconductor layer. Alternatively, it may be heteroepitaxial growth composed of at least one or more different elements for the first oxide semiconductor layer and the second oxide semiconductor layer.

[0107] ​​​​​​​​​​​By reducing impurities and adding oxygen in the above method, it is possible to form CAAC-OS that is of type I (intrinsic semiconductor) or substantially of type I. By forming such an oxide semiconductor layer, a transistor with extremely excellent characteristics can be realized.

[0108] In addition, when the oxide semiconductor is type-I (intrinsified) or substantially type-I, the dielectric constant can be increased. Specifically, the relative dielectric constant of an In-Ga-Zn-O-based oxide can be about 15 This is much higher compared to the relative dielectric constant of silicon oxide being about 4. Therefore, by using an oxide semiconductor that is type-I (intrinsified) or substantially type-I as the dielectric of the capacitor element 164, the capacitance per unit area of the capacitor element 164 can be increased.

[0109] In addition, after processing the oxide semiconductor layer to form the first oxide semiconductor layer 144a and the second oxide semiconductor layer 144b, oxygen may be added to the second oxide semiconductor layer 144b. In addition, one or more elements of metals such as silicon, germanium, and cerium, titanium, tungsten, aluminum, copper, yttrium, lanthanum, vanadium, etc. may be added to the second oxide semiconductor layer 144b. By adding these elements, the insulation of the second oxide semiconductor layer 144b can be enhanced.

[0110] As a method of addition, an ion implantation method or an ion doping method can be used. As the addition concentration, in the case of oxygen, it is 1×10 16 atoms / cm 3 or more and 2×10 20 atoms / cm 3 ​​​​​​​It is preferable to be as follows. If the oxygen concentration is within this range, it can be incorporated into the oxide semiconductor without imparting strain or the like to the crystal. In the case of silicon, germanium, and metal elements, it can be 1×10 or more, preferably 1×10 20 atoms / cm 3 or more, more preferably 5×10 2 1 atoms / cm 3 or more, and still more preferably 5×10 21 atoms / cm 3 or more. This can be achieved.

[0111] Next, a conductive layer 142 is formed (see FIG. 2(D)). The conductive layer 142 can be formed of the same material and configuration as the first electrode 148 b and the gate electrode 148a.

[0112] Next, the conductive layer 142 is processed to form a source electrode or a drain electrode 142b and a drain electrode or a source electrode 142a (see FIG. 3(A)).

[0113] Next, an insulating layer 150 is formed so as to cover the source electrode or the drain electrode 142b, the drain electrode or the source electrode 142a and the first oxide semiconductor layer 144a. The insulating layer 15 0 is formed using a material containing an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide nium. By using a material with a low dielectric constant ( low-k) for the insulating layer 150, when various electrodes and wirings are provided on the insulating layer 150, it is possible to sufficiently reduce the capacitance caused by overlap , which is preferable. Note that a porous insulating layer using the above-described material may be applied to the insulating layer 150. In the porous insulating layer, since the dielectric constant is lower than that of an insulating layer with a high density , it is possible to further reduce the capacitance caused by electrodes and wirings , which is preferable. This is possible. Also, the insulating layer 150 can be formed using an organic insulating material such as polyimide or acrylic. It is also possible to form it using the above materials. The insulating layer 150 can be formed in a single-layer structure or a laminated structure using the above materials (see Fig. 3(B)).

[0114] As described above, the transistor 160 and the capacitor element 164 using the oxide semiconductor layer are completed (see Fig. 3(B)).

[0115] Furthermore, an electrode 152 may be formed on the insulating layer 150. The electrode 152 can be formed with the same material and configuration as the first electrode 14 8b and the gate electrode 148a. The transistor 162 can control electrical characteristics such as the threshold voltage by the electrode 1 52.

[0116] As described above, the transistor 162 having the electrode 152 is completed (see Fig. 3(C)).

[0117] Next, the manufacturing methods of the transistor 160 and the transistor 162 shown in Figs. 1(C) and 1(D) will be described.

[0118] First, the insulating layer 140 is formed. Regarding the insulating layer 140, the description about Fig. 1(A) can be referred to.

[0119] Next, a conductive layer is formed on the insulating layer 140, and the conductive layer is processed to form the first electrode 148b and the gate electrode 148a. Next, before the first electrode 148b comes into contact with the oxide semiconductor layer to be formed later, the first electrode 148b is oxidized, or a metal oxide layer 149b is formed using a sputtering method or a CV D method.

[0120] The materials and structures of the first electrode 148b and the gate electrode 148a are shown in FIG. However, high-density oxygen plasma treatment or thermal oxidation can be used. When the metal oxide layer 149b is formed, the first electrode 148b and the gate electrode 148 It is preferable that a contains tungsten, titanium or zirconium. This is because these oxides have high electrical conductivity. Alternatively, a layer containing the metal oxide may be formed as the metal oxide layer 149b. The time for this may be before the insulating layer is formed or after the gate insulating layer 146 is formed. A metal oxide layer may be laminated on both the first electrode 148b and the gate electrode 148a. It may be laminated on only one electrode 148b.

[0121] The method for forming the metal oxide layer 149b is not particularly limited, but may be, for example, high-density oxygen plasma treatment. The high density oxygen plasma treatment can be carried out by, for example, helium, argon, This is done using a mixture of oxygen and rare gases such as krypton and xenon. In this case, plasma By exciting the plasma with microwaves, a high density plasma with a low electron temperature can be generated. The oxygen radicals (OH radicals) generated in such high-density plasma can be By oxidizing the surface of the first electrode 148b by the method described above, the thickness of the first electrode 148b can be reduced by 1 nm or more. A metal oxide layer 149b having a thickness of 20 nm or less, preferably 5 nm to 10 nm, is formed. It is possible.

[0122] The oxidation of the first electrode 148b by the high-density oxygen plasma treatment described above is a solid-phase growth. In addition, the interface state density between the first electrode 148b and the metal oxide layer 149b is extremely low. is achievable. Also, by directly oxidizing the first electrode 148b through high-density oxygen plasma treatment it is possible to suppress the variation in the thickness of the formed metal oxide layer 149b.

[0123] Alternatively, the metal oxide layer 149b may be formed by thermally oxidizing the first electrode 148b in this way. Thus, when using thermal oxidation, it is necessary to use a substrate having a certain degree of heat resistance .

[0124] Alternatively, the metal oxide layer 149b may be formed by processing a layer formed by a sputtering method or a CVD method . Regarding the formation method by the sputtering method, the formation method of the oxide semiconductor layer described later can be referred to .

[0125] In this embodiment, a metal oxide layer 149b with a thickness of 5 nm or more and 10 nm or less is formed by high-density oxygen plasma treatment .

[0126] The metal oxide layer 149b can prevent oxygen from being taken away from the second oxide semiconductor layer 144b formed in a later process to the first electrode 148b. Also, oxygen can be supplied from the metal oxide layer 149b to the second oxide semiconductor layer 144b formed in a later process, and the oxygen deficiency of the second oxide semiconductor layer 144b can be further reduced. Moreover, by using a metal oxide layer 149b with high conductivity, a decrease in the capacitance of the capacitive element 164 can be prevented . b to the second oxide semiconductor layer 144b formed in a later process, and the oxygen deficiency of the second oxide semiconductor layer 144b can be further reduced. Moreover, by using a metal oxide layer 149b with high conductivity, a decrease in the capacitance of the capacitive element 164 can be prevented . .

[0127] Next, an insulating layer is formed, and the insulating layer is processed to form a gate insulating layer 146 so as to cover the gate electrode 148a. Regarding the gate insulating layer 146, the description about FIG. 1(A) can be referred to .

[0128] ​ Next, an oxide semiconductor layer is formed, and the oxide semiconductor layer is processed to form a first oxide semiconductor layer 144a so as to overlap with the gate electrode 148a on the gate insulating layer 146. At the same time, a second oxide semiconductor layer 144b is formed in contact with the first electrode 148b or the metal oxide layer 149b. For the oxide semiconductor layer, the first oxide semiconductor layer 144a, and the second oxide semiconductor layer 144b, reference can be made to the description of FIG. 1(A). Next, a metal oxide layer is formed. The metal oxide layer can be formed using a CVD method, a sputtering method, or the like. The metal oxide layer preferably has a structure containing tungsten oxide, titanium oxide, zirconium oxide, or an In-Ga-Zn-O-N-based compound. This is because these metal oxides have high conductivity. The thickness of the metal oxide layer is not particularly limited, but can be formed, for example, in the range of 1 nm or more and 20 nm or less, preferably 5 nm or more and 10 nm or less. Next, a conductive layer 142 is formed. The conductive layer 142 can be formed of the same material and configuration as the first electrode 148b and the gate electrode 148a. It is preferable to form a metal oxide layer before the conductive layer 142 comes into contact with the first oxide semiconductor layer 144a and the second oxide semiconductor layer 144b. Next, the conductive layer 142 and the metal oxide layer are processed to form a source electrode or drain electrode 142b, a metal oxide layer 141b, a drain electrode or source electrode 142a, and a metal oxide layer 141a.

[0129] Next, a metal oxide layer is formed. The metal oxide layer can be formed using a CVD method, a sputtering method, or the like. The metal oxide layer preferably has a structure containing tungsten oxide, titanium oxide, zirconium oxide, or an In-Ga-Zn-O-N-based compound. This is because these metal oxides have high conductivity. The thickness of the metal oxide layer is not particularly limited, but can be formed, for example, in the range of 1 nm or more and 20 nm or less, preferably 5 nm or more and 10 nm or less. Next, a metal oxide layer is formed. The metal oxide layer can be formed using a CVD method, a sputtering method, or the like. The metal oxide layer preferably has a structure containing tungsten oxide, titanium oxide, zirconium oxide, or an In-Ga-Zn-O-N-based compound. This is because these metal oxides have high conductivity. The thickness of the metal oxide layer is not particularly limited, but can be formed, for example, in the range of 1 nm or more and 20 nm or less, preferably 5 nm or more and 10 nm or less. Next, a metal oxide layer is formed. The metal oxide layer can be formed using a CVD method, a sputtering method, or the like. The metal oxide layer preferably has a structure containing tungsten oxide, titanium oxide, zirconium oxide, or an In-Ga-Zn-O-N-based compound. This is because these metal oxides have high conductivity. The thickness of the metal oxide layer is not particularly limited, but can be formed, for example, in the range of 1 nm or more and 20 nm or less, preferably 5 nm or more and 10 nm or less. Next, a metal oxide layer is formed. The metal oxide layer can be formed using a CVD method, a sputtering method, or the like. The metal oxide layer preferably has a structure containing tungsten oxide, titanium oxide, zirconium oxide, or an In-Ga-Zn-O-N-based compound. This is because these metal oxides have high conductivity. The thickness of the metal oxide layer is not particularly limited, but can be formed, for example, in the range of 1 nm or more and 20 nm or less, preferably 5 nm or more and 10 nm or less. Next, a metal oxide layer is formed. The metal oxide layer can be formed using a CVD method, a sputtering method, or the like. The metal oxide layer preferably has a structure containing tungsten oxide, titanium oxide, zirconium oxide, or an In-Ga-Zn-O-N-based compound. This is because these metal oxides have high conductivity. The thickness of the metal oxide layer is not particularly limited, but can be formed, for example, in the range of 1 nm or more and 20 nm or less, preferably 5 nm or more and 10 nm or less. Next, a metal oxide layer is formed. The metal oxide layer can be formed using a CVD method, a sputtering method, or the like. The metal oxide layer preferably has a structure containing tungsten oxide, titanium oxide, zirconium oxide, or an In-Ga-Zn-O-N-based compound. This is because these metal oxides have high conductivity. The thickness of the metal oxide layer is not particularly limited, but can be formed, for example, in the range of 1 nm or more and 20 nm or less, preferably 5 nm or more and 10 nm or less.

[0130] Next, a metal oxide layer is formed. The metal oxide layer can be formed using a CVD method, a sputtering method, or the like. The metal oxide layer preferably has a structure containing tungsten oxide, titanium oxide, zirconium oxide, or an In-Ga-Zn-O-N-based compound. This is because these metal oxides have high conductivity. The thickness of the metal oxide layer is not particularly limited, but can be formed, for example, in the range of 1 nm or more and 20 nm or less, preferably 5 nm or more and 10 nm or less. Next, a metal oxide layer is formed. The metal oxide layer can be formed using a CVD method, a sputtering method, or the like. The metal oxide layer preferably has a structure containing tungsten oxide, titanium oxide, zirconium oxide, or an In-Ga-Zn-O-N-based compound. This is because these metal oxides have high conductivity. The thickness of the metal oxide layer is not particularly limited, but can be formed, for example, in the range of 1 nm or more and 20 nm or less, preferably 5 nm or more and 10 nm or less. Next, a metal oxide layer is formed. The metal oxide layer can be formed using a CVD method, a sputtering method, or the like. The metal oxide layer preferably has a structure containing tungsten oxide, titanium oxide, zirconium oxide, or an In-Ga-Zn-O-N-based compound. This is because these metal oxides have high conductivity. The thickness of the metal oxide layer is not particularly limited, but can be formed, for example, in the range of 1 nm or more and 20 nm or less, preferably 5 nm or more and 10 nm or less. Next, a metal oxide layer is formed. The metal oxide layer can be formed using a CVD method, a sputtering method, or the like. The metal oxide layer preferably has a structure containing tungsten oxide, titanium oxide, zirconium oxide, or an In-Ga-Zn-O-N-based compound. This is because these metal oxides have high conductivity. The thickness of the metal oxide layer is not particularly limited, but can be formed, for example, in the range of 1 nm or more and 20 nm or less, preferably 5 nm or more and 10 nm or less.

[0131] Next, a metal oxide layer is formed. The metal oxide layer can be formed using a CVD method, a sputtering method, or the like. The metal oxide layer preferably has a structure containing tungsten oxide, titanium oxide, zirconium oxide, or an In-Ga-Zn-O-N-based compound. This is because these metal oxides have high conductivity. The thickness of the metal oxide layer is not particularly limited, but can be formed, for example, in the range of 1 nm or more and 20 nm or less, preferably 5 nm or more and 10 nm or less. Next, a metal oxide layer is formed. The metal oxide layer can be formed using a CVD method, a sputtering method, or the like. The metal oxide layer preferably has a structure containing tungsten oxide, titanium oxide, zirconium oxide, or an In-Ga-Zn-O-N-based compound. This is because these metal oxides have high conductivity. The thickness of the metal oxide layer is not particularly limited, but can be formed, for example, in the range of 1 nm or more and 20 nm or less, preferably 5 nm or more and 10 nm or less. Next, a metal oxide layer is formed. The metal oxide layer can be formed using a CVD method, a sputtering method, or the like. The metal oxide layer preferably has a structure containing tungsten oxide, titanium oxide, zirconium oxide, or an In-Ga-Zn-O-N-based compound. This is because these metal oxides have high conductivity. The thickness of the metal oxide layer is not particularly limited, but can be formed, for example, in the range of 1 nm or more and 20 nm or less, preferably 5 nm or more and 10 nm or less.

[0132] By using the highly conductive metal oxide layer 141a, the electrical connection between the capacitor element 164 and the transistor 16 0 can be kept good. Also, the metal oxide layer 141b and the metal oxide layer 141a can prevent oxygen from being taken away from the first oxide semiconductor layer 144a and the second oxide semiconductor layer 1 44b. Furthermore, oxygen can be supplied from the metal oxide layer 141b and the metal oxide layer 141a to the first oxide semiconductor layer 144a and the second oxide semiconductor layer 144b, and the oxygen deficiency in the first oxide semiconductor layer 144a and the second oxide semiconductor layer 144b can be reduced.

[0133] Next, an insulating layer 150 is formed so as to cover the source electrode or drain electrode 142b, the metal oxide layer 141b, the drain electrode or source electrode 142a, the metal oxide layer 141a, and the first oxide semiconductor layer 144a . The insulating layer 150 can be formed of the same material and configuration as the gate insulating layer 146 .

[0134] As described above, the transistor 160 and the capacitor element 164 using the oxide semiconductor layer are completed (see Fig. 1(C)).

[0135] Furthermore, an electrode 152 may be formed on the insulating layer 150. The electrode 152 can be formed of the same material and configuration as the first electrode 14 8b and the gate electrode 148a. The electrode 1 52 can control electrical characteristics such as the threshold voltage of the transistor 162.

[0136] As described above, the transistor 162 having the electrode 152 is completed (see Fig. 1(D)).

[0137] (Embodiment 2) In this embodiment, a configuration of a semiconductor device different from that of the first embodiment and a method for manufacturing the same will be described. , which will be described with reference to FIGS. 4 to 8.

[0138] 〈Cross-sectional configuration of semiconductor device〉 FIG. 4 is an example of the configuration of a semiconductor device. FIGS. 4(A) and 4(B) show the cross section. The semiconductor device shown in FIGS. 4(A) and 4(B) includes a transistor 160 using an oxide semiconductor in a channel formation region and a capacitor element 164 using an oxide semiconductor in a dielectric. It has.

[0139] The transistor 160 in FIG. 4(A) includes a source electrode or a drain electrode 142b and a drain electrode or a source electrode 142a provided on an insulating layer 140, and a source electrode or a drain electrode 142b and a drain electrode or a source electrode 142a, and a first oxide semiconductor layer 144a electrically connected to the source electrode or a drain electrode 142b and a drain electrode or a source electrode 142a, a gate insulating layer 146 covering the first oxide semiconductor layer 144a, and a gate electrode 148a overlapping the first oxide semiconductor layer 144a on the gate insulating layer 146. It has. It has.

[0140] The capacitor element 164 in FIG. 4(A) includes a source electrode or a drain electrode 142b, a second oxide semiconductor layer 144b in contact with the source electrode or a drain electrode 142b, and a first electrode 148b in contact with the second oxide semiconductor layer 144b. Here, the source electrode or the drain electrode 142b functions as the second electrode of the capacitor element 164. That is, it can also be said as follows. The capacitor element 164 includes a first electrode 148b and

[0141] That is, it can also be said as follows. The capacitor element 164 includes a first electrode 148b and It has a second oxide semiconductor layer 144b and a second electrode. The second electrode is made of the same conductive layer as the source electrode or the drain electrode 142b.

[0142] An insulating layer 150 is provided over the transistor 160 and the capacitor element 164.

[0143] The transistor 160 and the capacitor element 164 shown in FIG. 4(B) are modified examples of the transistor 160 and the capacitor element 164 shown in FIG. 4(A).

[0144] The difference between the configuration shown in FIG. 4(A) and the configuration shown in FIG. 4(B) is that in the capacitor element 164 of FIG. 4(B), the source electrode or the drain electrode 142b has a metal oxide layer 149b on the surface in contact with the second oxide semiconductor layer 144b. Further, in the capacitor element 164 of FIG. 4(B), the first electrode 148b has a metal oxide layer 141b on the surface in contact with the second oxide semiconductor layer 144b. Further, in the transistor 160 of FIG. 4(B), the drain electrode or the source electrode 142a may have a metal oxide layer 149a on the surface in contact with the first oxide semiconductor layer 144a.

[0145] When the second oxide semiconductor layer 144b is in contact with the source electrode or the drain electrode 142b, oxygen may be taken away from the second oxide semiconductor layer 144b by the source electrode or the drain electrode 142b. When oxygen is taken away from the second oxide semiconductor layer 144b, oxygen deficiency increases. The second oxide semiconductor layer 144b with increased oxygen deficiency may become highly conductive and may fail to function as a dielectric of the capacitor element.

[0146] ​​​​​​​​​​​​​Therefore, it is preferable that the source electrode or the drain electrode 142b has a metal oxide layer 149b in contact with the second oxide semiconductor layer 144b. The metal oxide layer 149b can prevent oxygen from being taken away from the second oxide semiconductor layer 144b. Also, a drain electrode or a source electrode 142a having a metal oxide layer 149a in contact with the first oxide semiconductor layer 144a may be used. By forming the metal oxide layer 149b and the metal oxide layer 149a, oxygen can be supplied to the second oxide semiconductor layer 144b, and the oxygen deficiency in the second oxide semiconductor layer 144b can be further reduced. Also, when the second oxide semiconductor layer 144b is in contact with the first electrode 148b, there is a possibility that oxygen is taken away from the second oxide semiconductor layer 144b by the first electrode 148b. When oxygen is taken away from the second oxide semiconductor layer 144b, the oxygen deficiency increases. When the oxygen deficiency in the second oxide semiconductor layer 144b increases, the conductivity increases, and there is a risk that it will no longer function as a dielectric of the capacitive element. Therefore, it is preferable that the first electrode 148b has a metal oxide layer 141b in contact with the second oxide semiconductor layer 144b. The metal oxide layer 141b can prevent oxygen from being taken away from the second oxide semiconductor layer 144b by the source electrode or the drain electrode 142b. Also, simultaneously with the metal oxide layer 141b, a metal oxide layer 141a may be formed between the gate insulating layer 146 and the gate electrode 148a. Note that whether or not oxygen is taken away from the second oxide semiconductor layer 144b depends on conditions in subsequent processes and the like. Moreover, when the second oxide semiconductor layer 144b is in contact with the first electrode 148b, there is a possibility that oxygen is taken away from the second oxide semiconductor layer 144b by the first electrode 148b. When oxygen is taken away from the second oxide semiconductor layer 144b, the oxygen deficiency increases. When the oxygen deficiency in the second oxide semiconductor layer 144b increases, the conductivity increases, and there is a risk that it will no longer function as a dielectric of the capacitive element. Therefore, it is preferable that the first electrode 148b has a metal oxide layer 141b in contact with the second oxide semiconductor layer 144b. The metal oxide layer 141b can prevent oxygen from being taken away from the second oxide semiconductor layer 144b by the source electrode or the drain electrode 142b. Also, simultaneously with the metal oxide layer 141b, a metal oxide layer 141a may be formed between the gate insulating layer 146 and the gate electrode 148a. Note that whether or not oxygen is taken away from the second oxide semiconductor layer 144b depends on conditions in subsequent processes and the like.

[0147] Moreover, when the second oxide semiconductor layer 144b is in contact with the first electrode 148b, there is a possibility that oxygen is taken away from the second oxide semiconductor layer 144b by the first electrode 148b. When oxygen is taken away from the second oxide semiconductor layer 144b, the oxygen deficiency increases. When the oxygen deficiency in the second oxide semiconductor layer 144b increases, the conductivity increases, and there is a risk that it will no longer function as a dielectric of the capacitive element. Therefore, it is preferable that the first electrode 148b has a metal oxide layer 141b in contact with the second oxide semiconductor layer 144b. The metal oxide layer 141b can prevent oxygen from being taken away from the second oxide semiconductor layer 144b by the source electrode or the drain electrode 142b. Also, simultaneously with the metal oxide layer 141b, a metal oxide layer 141a may be formed between the gate insulating layer 146 and the gate electrode 148a. Note that whether or not oxygen is taken away from the second oxide semiconductor layer 144b depends on conditions in subsequent processes and the like. Moreover, when the second oxide semiconductor layer 144b is in contact with the first electrode 148b, there is a possibility that oxygen is taken away from the second oxide semiconductor layer 144b by the first electrode 148b. When oxygen is taken away from the second oxide semiconductor layer 144b, the oxygen deficiency increases. When the oxygen deficiency in the second oxide semiconductor layer 144b increases, the conductivity increases, and there is a risk that it will no longer function as a dielectric of the capacitive element. Therefore, it is preferable that the first electrode 148b has a metal oxide layer 141b in contact with the second oxide semiconductor layer 144b. The metal oxide layer 141b can prevent oxygen from being taken away from the second oxide semiconductor layer 144b by the source electrode or the drain electrode 142b. Also, simultaneously with the metal oxide layer 141b, a metal oxide layer 141a may be formed between the gate insulating layer 146 and the gate electrode 148a.

[0148] Therefore, it is preferable that the first electrode 148b has a metal oxide layer 141b in contact with the second oxide semiconductor layer 144b. The metal oxide layer 141b can prevent oxygen from being taken away from the second oxide semiconductor layer 144b by the source electrode or the drain electrode 142b. Also, simultaneously with the metal oxide layer 141b, a metal oxide layer 141a may be formed between the gate insulating layer 146 and the gate electrode 148a. Note that whether or not oxygen is taken away from the second oxide semiconductor layer 144b depends on conditions in subsequent processes and the like. Moreover, when the second oxide semiconductor layer 144b is in contact with the first electrode 148b, there is a possibility that oxygen is taken away from the second oxide semiconductor layer 144b by the first electrode 148b. When oxygen is taken away from the second oxide semiconductor layer 144b, the oxygen deficiency increases. When the oxygen deficiency in the second oxide semiconductor layer 144b increases, the conductivity increases, and there is a risk that it will no longer function as a dielectric of the capacitive element. Therefore, it is preferable that the first electrode 148b has a metal oxide layer 141b in contact with the second oxide semiconductor layer 144b. The metal oxide layer 141b can prevent oxygen from being taken away from the second oxide semiconductor layer 144b by the source electrode or the drain electrode 142b. Also, simultaneously with the metal oxide layer 141b, a metal oxide layer 141a may be formed between the gate insulating layer 146 and the gate electrode 148a. Note that whether or not oxygen is taken away from the second oxide semiconductor layer 144b depends on conditions in subsequent processes and the like.

[0149] Note that whether or not oxygen is taken away from the second oxide semiconductor layer 144b depends on conditions in subsequent processes and the like. Therefore, it can be influenced. When oxygen is not removed from the second oxide semiconductor layer 144b, the metal It is not necessary to form the oxide layer 149b and the metal oxide layer 141b.

[0150] <Method for manufacturing a semiconductor device> Next, a method for manufacturing the transistor 160 shown in FIG. 4(A) will be described with reference to FIGS. 5 to 6. to explain.

[0151] First, a conductive layer 142 is formed on the insulating layer 140 (see FIG. 5(A)).

[0152] The material and configuration of the conductive layer 142 can refer to the description in Embodiment 1.

[0153] Next, the conductive layer 142 is processed to form the source electrode or drain electrode 142b and the drain electrode or source electrode 142a (see FIG. 5(B)).

[0154] Next, an oxide semiconductor layer is formed, and the oxide semiconductor layer is processed to be electrically connected to the source electrode or drain electrode 142b and the drain electrode or source electrode 142a, and the first oxide semiconductor layer 144a is formed. At the same time, the oxide semiconductor layer is processed to form the second oxide semiconductor layer 144b in contact with the source electrode or drain electrode 142b (see FIG. 5(C)). At this time, it is preferable to perform the first heat treatment. Regarding the material and configuration of the oxide semiconductor layer and the first heat treatment, the description in Embodiment 1 can be referred to. form the second oxide semiconductor layer 144b in contact with the source electrode or drain electrode 142b (see FIG. 5(C)). At this time, it is preferable to perform the first heat treatment. Regarding the material and configuration of the oxide semiconductor layer and the first heat treatment, the description in Embodiment 1 can be referred to. form the second oxide semiconductor layer 144b in contact with the source electrode or drain electrode 142b (see FIG. 5(C)). At this time, it is preferable to perform the first heat treatment. Regarding the material and configuration of the oxide semiconductor layer and the first heat treatment, the description in Embodiment 1 can be referred to. form the second oxide semiconductor layer 144b in contact with the source electrode or drain electrode 142b (see FIG. 5(C)). At this time, it is preferable to perform the first heat treatment. Regarding the material and configuration of the oxide semiconductor layer and the first heat treatment, the description in Embodiment 1 can be referred to. be possible.

[0155] Next, an insulating layer is formed on the first oxide semiconductor layer 144a, and the insulating layer is processed to form the gate insulating layer 146 (see FIG. 5(D)). The material and configuration of the gate insulating layer 146 are , the description of Embodiment 1 can be referred to.

[0156] After forming the insulating layer, it is desirable to perform a second heat treatment in an inert gas atmosphere or an oxygen atmosphere. The heat treatment may be performed in the same manner as the first heat treatment. When the insulating layer contains oxygen, oxygen is supplied to the first oxide semiconductor layer 144a and the second oxide semiconductor layer 144b, and the oxygen deficiency of the first oxide semiconductor layer 144a and the second oxide semiconductor layer 144b is compensated, so that an i-type (intrinsic semiconductor) or substantially i-type oxide semiconductor layer can be formed. .

[0157] As described above, by applying at least one of the first heat treatment and the second heat treatment, the oxide semiconductor layer can be purified to a high purity so that the substance containing its hydrogen atoms is minimized. .

[0158] Note that, in this embodiment, the second heat treatment is performed after forming the insulating layer, but the timing of the second heat treatment is not limited to this. For example, it may be performed after processing the insulating layer to form the gate insulating layer 146. Alternatively, the second heat treatment may be performed after the first heat treatment, or the second heat treatment may be combined with the first heat treatment, or the first heat treatment may be combined with the second heat treatment.

[0159] In addition, oxygen doping may be performed on the second oxide semiconductor layer 144b. By performing oxygen doping on the second oxide semiconductor layer 144b, the second oxide semiconductor layer 144b can be made closer to the i-type. Regarding the method of oxygen doping, the description about the gate insulating layer in Embodiment 1 can be referred to.

[0160] Next, a conductive layer 148 is formed (see FIG. 6(A)). The material and configuration of the conductive layer 148 can refer to the description of Embodiment 1. The description of Embodiment 1 can be referred to.

[0161] Next, the conductive layer 148 is processed to form a gate electrode 148a so as to overlap with the first oxide semiconductor layer 144a on the gate insulating layer 146. At the same time, a first electrode 148b is formed in contact with the second oxide semiconductor layer 144b (see FIG. 6(B)). Next, an insulating layer 150 is formed so as to cover the first electrode 148b, the second oxide semiconductor layer 144b, the gate insulating layer 146, and the gate electrode 148a. The material and configuration of the insulating layer 150 can refer to the description of Embodiment 1 (see FIG. 6(C)). b.

[0162] Next, an insulating layer 150 is formed so as to cover the first electrode 148b, the second oxide semiconductor layer 144b, the gate insulating layer 146, and the gate electrode 148a. The material and configuration of the insulating layer 150 can refer to the description of Embodiment 1 (see FIG. 6(C)). The material and configuration of the insulating layer 150 can refer to the description of Embodiment 1. (see FIG. 6(C)).

[0163] As described above, the transistor 160 and the capacitor element 164 using the oxide semiconductor layer are completed (see FIG. 6(C)). (see FIG. 6(C)).

[0164] Next, a method for manufacturing the transistor 160 shown in FIG. 4(B) will be described.

[0165] First, a conductive layer 142 is formed on the insulating layer 140, and a metal oxide layer is formed on the conductive layer 142. The material and configuration of the conductive layer 142 and the metal oxide layer can refer to the description of Embodiment 1. The material and configuration of the conductive layer 142 and the metal oxide layer can refer to the description of Embodiment 1. can be referred to.

[0166] Next, the conductive layer 142 and the metal oxide layer are processed to form a source electrode or drain electrode 14 2b, a metal oxide layer 149b, a drain electrode or source electrode 142a, and a metal oxide layer 149a.

[0167] Next, an oxide semiconductor layer is formed, and the oxide semiconductor layer is processed to form a source electrode or drain In this way, the first oxide semiconductor layer 144a is formed so as to be electrically connected to the in electrode 142b and the drain electrode or source electrode 142a. At the same time, the oxide semiconductor layer is processed to form the second oxide semiconductor layer 144b in contact with the metal oxide layer 149b. For the material and structure of the oxide semiconductor layer, reference can be made to the description in Embodiment 1.

[0168] Next, an insulating layer is formed on the first oxide semiconductor layer 144a, and the insulating layer is processed to form the gate insulating layer 146. For the material and structure of the gate insulating layer 146, reference can be made to the description in Embodiment 1 and FIG. 4(A).

[0169] Next, before the first oxide semiconductor layer 144a and the second oxide semiconductor layer 144b come into contact with the conductive layer 148, a metal oxide layer is formed between the first oxide semiconductor layer 144a and the second oxide semiconductor layer 144b and the conductive layer 148. For the material and structure of the metal oxide layer, reference can be made to the description in Embodiment 1.

[0170] Next, the conductive layer 148 is formed. For the material and structure of the conductive layer 148, reference can be made to the description in Embodiment 1.

[0171] Next, the metal oxide layer and the conductive layer 148 are processed to form the metal oxide layer 141a and the gate electrode 148a so as to overlap with the first oxide semiconductor layer 144a on the gate insulating layer 146. At the same time, in contact with the second oxide semiconductor layer 144b, the metal oxide layer 141b and the first electrode 148b are formed.

[0172] Next, the first electrode 148b, the second oxide semiconductor layer 144b, the gate insulating layer 146, the gate​​​​​​​​​​​ An insulating layer 150 is formed so as to cover the top electrode 148a. The material and structure of the insulating layer 150 can refer to the description of Embodiment 1.

[0173] As described above, the transistor 160 and the capacitor element 164 using the oxide semiconductor layer are completed.

[0174] <Cross-sectional configuration of semiconductor device> FIGS. 7 and 8 are examples of the configuration of a semiconductor device. FIGS. 7(A), 7(B), and 8 (A) to FIGS. 8(C) show cross-sections of the semiconductor device. The semiconductor devices shown in FIGS. 7(A), 7(B), and 8 (A) to FIGS. 8(C) include a transistor 160 or a transistor 162 using an oxide semiconductor in a channel formation region, and a capacitor element 1 64 using an oxide semiconductor in a dielectric.

[0175] The transistor 160 in FIG. 7(A) includes a gate electrode 14 8a provided on the insulating layer 140, a gate insulating layer 146 covering the gate electrode 148a, a source electrode or a drain electrode 142b and a drain electrode or a source electrode 142a on the gate insulating layer 146, and a first oxide semiconductor layer 144a that is electrically connected to the source electrode or the drain electrode 142b and the drain electrode or the source electrode 142a and overlaps the gate electrode 148a on the gate insulating layer 146. Note that the transistor 160 may have a structure including a metal oxide layer that contacts the source electrode or the drain electrode 142b and the drain electrode or the source electrode 142a on the gate insulating layer 146. The source electrode or the drain electrode 142b and the drain electrode or the source electrode 142a

[0176] ​​​​​The capacitive element 164 in FIG. 7(A) includes a first electrode 148b, a second oxide semiconductor layer 144b in contact with the first electrode 148b, and a source electrode or drain electrode 142b in contact with the second oxide semiconductor layer 144b. Here, the source electrode or drain electrode 142b functions as the second electrode of the capacitive element 164. That is to say, it can also be described as follows. The capacitive element 164 includes a first electrode 148b, a second oxide semiconductor layer 144b, and a second electrode. The second electrode is made of the same conductive layer as the source electrode or drain electrode 142b. Namely, it can also be said as follows. The capacitive element 164 has a first electrode 148b, a second oxide semiconductor layer 144b, and a second electrode. The second electrode is composed of the same conductive layer as the source electrode or drain electrode 142b. That is, it can also be said as follows. The capacitive element 164 has a first electrode 148b, a second oxide semiconductor layer 144b, and a second electrode. The second electrode consists of the same conductive layer as the source electrode or drain electrode 142b.

[0177] That is to say, it can also be stated as follows. The capacitive element 164 has a first electrode 148b, a second oxide semiconductor layer 144b, and a second electrode. The second electrode is made of the same conductive layer as the source electrode or drain electrode 142b. That is, it can also be said as follows. The capacitive element 164 has a first electrode 148b, a second oxide semiconductor layer 144b, and a second electrode. The second electrode is composed of the same conductive layer as the source electrode or drain electrode 142b. That is, it can also be said as follows. The capacitive element 164 has a first electrode 148b, a second oxide semiconductor layer 144b, and a second electrode. The second electrode consists of the same conductive layer as the source electrode or drain electrode 142b.

[0178] Note that the capacitive element 164 may be configured to have a metal oxide layer on the surface of the first electrode 148b where the first electrode 148b is in contact with the second oxide semiconductor layer 144b. Also, the capacitive element 164 may be configured to have a metal oxide layer on the second oxide semiconductor layer 144b. Note that the capacitive element 164 can also be configured to have a metal oxide layer on the surface of the first electrode 148b where the first electrode 148b contacts the second oxide semiconductor layer 144b. Also, the capacitive element 164 can be configured to have a metal oxide layer on the second oxide semiconductor layer 144b. Note that the capacitive element 164 can also be configured to have a metal oxide layer on the surface of the first electrode 148b where the first electrode 148b contacts the second oxide semiconductor layer 144b. Also, the capacitive element 164 can be configured to have a metal oxide layer on the second oxide semiconductor layer 144b. Note that the capacitive element 164 can also be configured to have a metal oxide layer on the surface of the first electrode 148b where the first electrode 148b contacts the second oxide semiconductor layer 144b. Also, the capacitive element 164 can be configured to have a metal oxide layer on the second oxide semiconductor layer 144b.

[0179] Also, an insulating layer 150 is provided over the transistor 160 and the capacitive element 164. Also, an insulating layer 150 is provided above the transistor 160 and the capacitive element 164.

[0180] The transistor 162 and the capacitive element 164 shown in FIG. 7(B) are modified examples of the transistor 160 and the capacitive element 164 shown in FIG. 7(A). The difference between the configuration shown in FIG. 7(A) and the configuration shown in FIG. 7(B) is that the transistor 162 in FIG. 7(B) includes an electrode 152 over the insulating layer 150. The transistor 162 has two gates via an insulating layer above and below a first oxide semiconductor layer 144a having a channel formation region.

[0181] The difference between the configuration shown in FIG. 7(A) and the configuration shown in FIG. 7(B) is that the transistor 162 in FIG. 7(B) includes an electrode 152 on the insulating layer 150. The transistor 162 has two gates via an insulating layer above and below a first oxide semiconductor layer 144a having a channel formation region. The difference between the configuration shown in FIG. 7(A) and the configuration shown in FIG. 7(B) is that the transistor 162 in FIG. 7(B) includes an electrode 152 on the insulating layer 150. The transistor 162 has two gates via an insulating layer above and below a first oxide semiconductor layer 144a having a channel formation region. The difference between the configuration shown in FIG. 7(A) and the configuration shown in FIG. 7(B) is that the transistor 162 in FIG. 7(B) includes an electrode 152 on the insulating layer 150. The transistor 162 has two gates via an insulating layer above and below a first oxide semiconductor layer 144a having a channel formation region. It is a dual-gate transistor in which an electrode layer is disposed. Specifically, the transistor 162 includes a gate electrode 148a, a gate insulating layer 146 on the gate electrode 148a, and a source electrode or drain electrode 142b and a drain electrode or source electrode 142a on the gate insulating layer 146, a first oxide semiconductor layer 144a that is electrically connected to the source electrode or drain electrode 142b and the drain electrode or source electrode 142a on the source electrode or drain electrode 142a, an insulating layer 150 on the source electrode or drain electrode 142b, the drain electrode or source electrode 142a, and the first oxide semiconductor layer, and an electrode 152 that overlaps the first oxide semiconductor layer 144a on the insulating layer 150.

[0182] In FIG. 7(B), both the gate electrode 148a and the electrode 152 function as gate electrodes. The potential of the electrode 152 may be the same as or different from that of the gate electrode 148a, and may be GND, 0 V, or in a floating state. By controlling the electric field applied to the first oxide semiconductor layer 144a by the gate electrode 148a and the electrode 152, the threshold voltage of the transistor 162 can be controlled.

[0183] The transistor 160 and the capacitor element 164 shown in FIG. 8(A) are modified examples of the transistor 160 and the capacitor element 164 shown in FIG. 7(A).

[0184] The difference between the configuration shown in FIG. 7(A) and the configuration shown in FIG. 8(A) lies in the method of forming the capacitor electrode of the capacitor element 164. In FIG. While the rain electrode 142b is provided, in FIG. 8(A), the source electrode or drain The electrode 147b is provided on the electrode 142b.

[0185] The transistor 160 and the capacitor element 164 shown in FIG. 8(B) are variations of the trans istor 162 and the capacitor element 164 shown in FIG. 7(B).

[0186] The difference between the configuration shown in FIG. 7(B) and the configuration shown in FIG. 8(B) is the capacitor electrode formation method of the capacitor element 164. In FIG. 7(B), on the first electrode 148b, the source electrode or drain While the rain electrode 142b is provided, in FIG. 8(B), the source electrode or drain The first electrode 148b is provided on the electrode 142b.

[0187] Note that the transistor 162 can also have a configuration in which a metal oxide layer in contact with the source electrode or drain electrode 142b, the drain electrode or source electrode 142a, and the electrode 152 is provided on the gate insulating layer 146.

[0188] The transistor 160 in FIG. 8(C) includes a first oxide semiconductor layer 144a provided on the insulating layer 140, a source electrode or drain electrode 142b that is electrically connected to the first oxide semiconductor layer 144a on the first oxide semiconductor layer 144a, and a drain electrode or source electrode 142a, a gate insulating layer 146 on the first oxide semiconductor layer 144a, the source electrode or drain electrode 142b, and the drain electrode or source electrode 142a, and a gate electrode 148a that overlaps the first oxide semiconductor layer 144a on the gate insulating layer 146. Note that the transistor 160 has a source electrode on the first oxide semiconductor layer 144a. ​​​​​​​Or a metal oxide layer 141b in contact with the drain electrode 142b, and the drain electrode or source It is also possible to adopt a configuration having a metal oxide layer 141a in contact with the electrode 142a.

[0189] The capacitor element 164 in FIG. 8(C) includes an electrode 147b, a second oxide semiconductor layer 144b and a source electrode or drain electrode 142b. Note that the capacitor element 164 has a metal oxide layer on the surface of the electrode 147b where the electrode 147b is in contact with the second oxide semiconductor layer 144b. It is also possible to adopt a configuration in which the capacitor element 164 has a metal oxide layer on the second oxide semiconductor layer 144b. 44b.

[0190] The transistor 160 and the capacitor element 164 in FIG. 8(D) are modified examples of the transistor 160 and the capacitor element 164 shown in FIG. 8(C).

[0191] The difference between the configuration shown in FIG. 8(C) and the configuration shown in FIG. 8(D) is that the transistor 160 in FIG. 8(D) has impurity regions 144c and 144d in the first oxide semiconductor layer 144a.

[0192] The impurity regions 144c and 144d can be self-alignedly formed by implanting impurities through the gate insulating layer 146 using the source electrode or drain electrode 142 b, the drain electrode or source electrode 142a, and the gate electrode 148a as masks.

[0193] As the impurity, nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), etc., which are group V (group 15) elements, can be used. In this embodiment, an example of implanting nitrogen is shown. ​​​​​​

[0194] As an impurity injection method, an ion implantation method, an ion doping method, or the like can be used. In the ion implantation method, a source gas is plasmaized, and ion species contained in this plasma are extracted, mass-separated, and ions having a predetermined mass are accelerated to form an ion beam and then implanted into the object to be processed. Further, in the ion doping method, a source gas is plasmaized and ion species are extracted from the plasma by the action of a predetermined electric field, and the extracted ion species are accelerated without mass separation and implanted into the object to be processed as an ion beam. By performing nitrogen implantation using an ion implantation method involving mass separation, it is possible to prevent elements other than the desired impurity (nitrogen here) such as metal elements from being added to the first oxide semiconductor layer 144a. Also, since the ion doping method can increase the area irradiated with the ion beam compared to the ion implantation method, the tact time can be shortened by adding impurities using the ion doping method. The nitrogen concentration in the impurity region 144c and the impurity region 144d is preferably 5×10 atoms / c

[0195] m 19 atoms / c m 3 or more. The nitrogen concentration in the impurity region 144c and the impurity region 144d is measured by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectroscopy).

[0196] Also, the nitrogen concentration in the above-mentioned impurity region 144c and the impurity region 144d is 1×10 2 0 atoms / cm 3If it is less than 7 atomic%, impurity regions 144c and After heat treatment is performed after the formation of impurity regions 144d, the crystal structure becomes a wurtzite-type structure. There is. The temperature of the heat treatment is preferably 300°C or higher and 600°C or lower, more preferably 350°C or higher and 5 00°C or lower.

[0197] Also, as shown in this embodiment, by performing an impurity implantation process through the gate insulating layer 146, excessive damage to the first oxide semiconductor layer 144a can be reduced.

[0198] In this embodiment, although a method of introducing impurities through the gate insulating layer 146 has been exemplified, it is not limited to this. For example, an impurity implantation process may be performed through an insulating layer formed later.

[0199] In this way, in the first oxide semiconductor layer 144a, by providing impurity regions so as to sandwich the channel formation region, the impurity regions have a smaller energy gap than the channel formation region and are more conducive to carrier flow. Therefore, by using a transistor with such a configuration, information can be written at high speed.

[0200] Also, by providing impurity regions so as to sandwich the channel formation region, a structure is formed that relaxes the electric field concentration at the drain electrode end.

[0201] Also, impurity regions 144c and 144d can be called low-resistance regions (also referred to as n-type regions) because the resistance of the first oxide semiconductor layer 144a becomes low due to the injection of impurities.

[0202] ​​​​Note that in FIG. 8(D), a method for forming low-resistance regions (impurity regions 144c and 144d) in an oxide semiconductor was illustrated. However, in a transistor using an oxide semiconductor, as one of the methods for fabricating an impurity region that functions as a source region or a drain region by a self-alignment process, a method is disclosed in which the surface of the oxide semiconductor layer is exposed and argon plasma treatment is performed to reduce the resistivity of the region of the oxide semiconductor layer exposed to the plasma (S. Jeon et al., "180nm Gate Length Amorphous InGaZnO Thin Film Transistor for High Density Image Sensor Application", IEDM Tech. Dig., p.504, 2010.). However, in the above fabrication method, after forming the gate insulating layer, it is necessary to partially remove the gate insulating layer to expose the portion that should become the source region or the drain region. Therefore, when the gate insulating layer is removed, the underlying oxide semiconductor layer is also partially overetched, and the thickness of the portion that should become the source region or the drain region becomes small. As a result, the resistance of the source region or the drain region increases, and characteristic defects of the transistor due to overetching are likely to occur. To advance the miniaturization of the transistor, it is necessary to adopt a dry etching method with high processing accuracy. However, the above overetching significantly tends to occur when a dry etching method that cannot sufficiently ensure the selectivity between the oxide semiconductor layer and the gate insulating layer is adopted. However, in the above fabrication method, after forming the gate insulating layer, it is necessary to partially remove the gate insulating layer to expose the portion that should become the source region or the drain region. Therefore, when the gate insulating layer is removed, the underlying oxide semiconductor layer is also partially overetched, and the thickness of the portion that should become the source region or the drain region becomes small. As a result, the resistance of the source region or the drain region increases, and characteristic defects of the transistor due to overetching are likely to occur. However, in the above fabrication method, after forming the gate insulating layer, it is necessary to partially remove the gate insulating layer to expose the portion that should become the source region or the drain region. Therefore, when the gate insulating layer is removed, the underlying oxide semiconductor layer is also partially overetched, and the thickness of the portion that should become the source region or the drain region becomes small. As a result, the resistance of the source region or the drain region increases, and characteristic defects of the transistor due to overetching are likely to occur. Note that in FIG. 8(D), a method for forming low-resistance regions (impurity regions 144c and 144d) in an oxide semiconductor was illustrated. However, in a transistor using an oxide semiconductor, as one of the methods for fabricating an impurity region that functions as a source region or a drain region by a self-alignment process, a method is disclosed in which the surface of the oxide semiconductor layer is exposed and argon plasma treatment is performed to reduce the resistivity of the region of the oxide semiconductor layer exposed to the plasma (S. Jeon et al., "180nm Gate Length Amorphous InGaZnO Thin Film Transistor for High Density Image Sensor Application", IEDM Tech. Dig., p.504, 2010.). Note that in FIG. 8(D), a method for forming low-resistance regions (impurity regions 144c and 144d) in an oxide semiconductor was illustrated. However, in a transistor using an oxide semiconductor, as one of the methods for fabricating an impurity region that functions as a source region or a drain region by a self-alignment process, a method is disclosed in which the surface of the oxide semiconductor layer is exposed and argon plasma treatment is performed to reduce the resistivity of the region of the oxide semiconductor layer exposed to the plasma (S. Jeon et al., "180nm Gate Length Amorphous InGaZnO Thin Film Transistor for High Density Image Sensor Application", IEDM Tech. Dig., p.504, 2010.). Note that in FIG. 8(D), a method for forming low-resistance regions (impurity regions 144c and 144d) in an oxide semiconductor was illustrated. However, in a transistor using an oxide semiconductor, as one of the methods for fabricating an impurity region that functions as a source region or a drain region by a self-alignment process, a method is disclosed in which the surface of the oxide semiconductor layer is exposed and argon plasma treatment is performed to reduce the resistivity of the region of the oxide semiconductor layer exposed to the plasma (S. Jeon et al., "180nm Gate Length Amorphous InGaZnO Thin Film Transistor for High Density Image Sensor Application", IEDM Tech. Dig., p.504, 2010.). Note that in FIG. 8(D), a method for forming low-resistance regions (impurity regions 144c and 144d) in an oxide semiconductor was illustrated. However, in a transistor using an oxide semiconductor, as one of the methods for fabricating an impurity region that functions as a source region or a drain region by a self-alignment process, a method is disclosed in which the surface of the oxide semiconductor layer is exposed and argon plasma treatment is performed to reduce the resistivity of the region of the oxide semiconductor layer exposed to the plasma (S. Jeon et al., "180nm Gate Length Amorphous InGaZnO Thin Film Transistor for High Density Image Sensor Application", IEDM Tech. Dig., p.504, 2010.).

[0203] However, in the above fabrication method, after forming the gate insulating layer, it is necessary to partially remove the gate insulating layer to expose the portion that should become the source region or the drain region. Therefore, when the gate insulating layer is removed, the underlying oxide semiconductor layer is also partially overetched, and the thickness of the portion that should become the source region or the drain region becomes small. As a result, the resistance of the source region or the drain region increases, and characteristic defects of the transistor due to overetching are likely to occur. However, in the above fabrication method, after forming the gate insulating layer, it is necessary to partially remove the gate insulating layer to expose the portion that should become the source region or the drain region. Therefore, when the gate insulating layer is removed, the underlying oxide semiconductor layer is also partially overetched, and the thickness of the portion that should become the source region or the drain region becomes small. As a result, the resistance of the source region or the drain region increases, and characteristic defects of the transistor due to overetching are likely to occur. However, in the above fabrication method, after forming the gate insulating layer, it is necessary to partially remove the gate insulating layer to expose the portion that should become the source region or the drain region. Therefore, when the gate insulating layer is removed, the underlying oxide semiconductor layer is also partially overetched, and the thickness of the portion that should become the source region or the drain region becomes small. As a result, the resistance of the source region or the drain region increases, and characteristic defects of the transistor due to overetching are likely to occur. However, in the above fabrication method, after forming the gate insulating layer, it is necessary to partially remove the gate insulating layer to expose the portion that should become the source region or the drain region. Therefore, when the gate insulating layer is removed, the underlying oxide semiconductor layer is also partially overetched, and the thickness of the portion that should become the source region or the drain region becomes small. As a result, the resistance of the source region or the drain region increases, and characteristic defects of the transistor due to overetching are likely to occur. However, in the above fabrication method, after forming the gate insulating layer, it is necessary to partially remove the gate insulating layer to expose the portion that should become the source region or the drain region. Therefore, when the gate insulating layer is removed, the underlying oxide semiconductor layer is also partially overetched, and the thickness of the portion that should become the source region or the drain region becomes small. As a result, the resistance of the source region or the drain region increases, and characteristic defects of the transistor due to overetching are likely to occur. However, in the above fabrication method, after forming the gate insulating layer, it is necessary to partially remove the gate insulating layer to expose the portion that should become the source region or the drain region. Therefore, when the gate insulating layer is removed, the underlying oxide semiconductor layer is also partially overetched, and the thickness of the portion that should become the source region or the drain region becomes small. As a result, the resistance of the source region or the drain region increases, and characteristic defects of the transistor due to overetching are likely to occur.

[0204] To advance the miniaturization of the transistor, it is necessary to adopt a dry etching method with high processing accuracy. However, the above overetching significantly tends to occur when a dry etching method that cannot sufficiently ensure the selectivity between the oxide semiconductor layer and the gate insulating layer is adopted. To advance the miniaturization of the transistor, it is necessary to adopt a dry etching method with high processing accuracy. However, the above overetching significantly tends to occur when a dry etching method that cannot sufficiently ensure the selectivity between the oxide semiconductor layer and the gate insulating layer is adopted. To advance the miniaturization of the transistor, it is necessary to adopt a dry etching method with high processing accuracy. However, the above overetching significantly tends to occur when a dry etching method that cannot sufficiently ensure the selectivity between the oxide semiconductor layer and the gate insulating layer is adopted.

[0205] For example, if the oxide semiconductor layer has a sufficient thickness, over-etching is not a problem. However, when the channel length is set to 200 nm or less, in order to prevent the short-channel effect, the thickness of the oxide semiconductor layer in the portion that becomes the channel formation region is required to be 20 nm or less, preferably 10 nm or less. When dealing with such a thin oxide semiconductor layer, over-etching of the oxide semiconductor layer is not preferable because, as described above, it increases the resistance of the source region or the drain region and causes poor transistor characteristics. However, as in the present embodiment, by performing impurity implantation into the oxide semiconductor layer without exposing the oxide semiconductor layer and while leaving the gate insulating layer, over-etching of the oxide semiconductor

[0206] layer can be prevented, and excessive damage to the oxide semiconductor layer can be reduced. Therefore, the characteristics and reliability of the transistor can be improved. Further, the configuration shown in the present embodiment can be used in appropriate combination with the configurations shown in other embodiments.

[0207] (Embodiment 3) In the present embodiment, an example of the memory cell 170 configured using the semiconductor devices of Embodiment 1 and Embodiment 2 is shown with reference to FIG. 9.

[0208] (Embodiment 3) In the present embodiment, an example of the memory cell 170 configured using the semiconductor devices of Embodiment 1 and Embodiment 2 is shown with reference to FIG. 9.

[0209] <Configuration of Memory Cell> A cross-sectional view of the memory cell 170 is shown in FIG. 9(A), a top view of the memory cell 170 is shown in FIG. 9(B), and a circuit diagram of the memory cell 170 is shown in FIG. 9(C).

[0210] In FIGS. 9(A) and 9(B), a semiconductor device corresponding to FIG. 1(A) is shown. However, the One embodiment is not limited to this. Alternatively, the configuration of another semiconductor device having a similar function may be applied. .

[0211] The memory cell 170 shown in FIGS. 9A, 9B, and 9C includes a transistor 160 and It has a capacitance element 164 .

[0212] In the memory cell 170 shown in FIG. The source electrode 142a is disposed through an opening in the insulating layer 150 and the insulating layer 154. It is electrically connected to the line 156. In FIG. 9A, the insulating layer 150 and the insulating layer 1 54 is laminated, but is not limited to this. Alternatively, only one layer may be provided.

[0213] In the memory cell 170 shown in FIG. 9C, a first wiring (also called a bit line BL) and a The second transistor 160 is electrically connected to one of the source electrode and the drain electrode. The wiring (also called the word line WL) and the gate electrode of the transistor 160 are electrically connected. The other of the source electrode or the drain electrode of the transistor 160 is connected to A third wiring (also referred to as a capacitance line CL) is electrically connected to one of the electrodes of the capacitor 164. ) is electrically connected to the other electrode of the capacitor 164.

[0214] Here, the transistor 160 is formed using the oxide semiconductor described in Embodiments 1 and 2. The transistor using the oxide semiconductor described in the first and second embodiments is applied. The off-state current of the transistor is extremely small. By setting 60 to the off state, the potential applied to the capacitive element 164 can be held for an extremely long time. Note that the transistor 160 using an oxide semiconductor has a channel length (L) of 10 nm or more and 1000 nm or less, so it has the characteristics of low power consumption and extremely high operating speed. Moreover, the capacitive element 164 is applied with a capacitive element using the oxide semiconductor described in Embodiments 1 and 2 as a dielectric. Since the oxide semiconductor has a high dielectric constant, by using it as the dielectric of the capacitive element 164, the capacitance per unit area of the capacitive element 164 can be increased. In the semiconductor device shown in FIG. 9(C), by taking advantage of the characteristic that the potential applied to the capacitive element 164 can be held, information can be written, held, and read as follows. First, writing and holding of information will be described. Here, for simplicity, it is assumed that the potential of the third wiring is fixed. First, the potential of the second wiring is set to a potential at which the transistor 160 is turned on, and the transistor 160 is turned on. As a result, the potential of the first wiring is applied to one of the electrodes of the capacitive element 164. That is, a predetermined charge is applied to the capacitive element 164 (writing). Then, the potential of the second wiring is set to a potential at which the transistor 160 is turned off, and the transistor 160 is turned off, so that the charge applied to the capacitive element 164 is held (holding). As described above, the transistor 160 has an extremely small off-current, so it can hold the charge for a long time.

[0215]

[0216]

[0217]

[0218] ​​​​​​​​​​​​​Next, the reading of information will be described. When a predetermined potential (constant potential) is applied to the first wiring and the potential of the second wiring is set to a potential at which the transistor 160 is turned on, the first wiring takes on different potentials according to the amount of charge held in the capacitor element 164. Therefore, the information being held can be read by observing the potential of the first wiring. When the potential of the second wiring is set to a potential at which the transistor 160 is turned on while a predetermined potential (constant potential) is applied to the first wiring, the first wiring takes on different potentials according to the amount of charge held in the capacitor element 164. For this reason, the information being held can be read by observing the potential of the first wiring. By looking at the potential of the first wiring, the information being held can be read.

[0219] Note that when information is read, the charge in the capacitor element 164 is lost, so it is necessary to pay attention to the fact that re-writing needs to be performed. Note that when information is read, the charge in the capacitor element 164 is lost, so it is necessary to be careful about performing re-writing again.

[0220] Next, the rewriting of information will be described. The rewriting of information is performed in the same way as the writing and holding of the above information. That is, the potential of the second wiring is set to a potential at which the transistor 160 is turned on, and the transistor 160 is turned on. As a result, the potential of the first wiring (the potential related to the new information) is applied to one of the electrodes of the capacitor element 164. Then, the potential of the second wiring is set to a potential at which the transistor 160 is turned off, and the transistor 160 is turned off, so that the capacitor element 164 assumes a state in which charge related to new information is applied. Next, the rewriting of information will be described. The rewriting of information is carried out in the same manner as the writing and holding of the above information. That is, the potential of the second wiring is set to a potential at which the transistor 160 is turned on, and the transistor 160 is turned on. As a result, the potential of the first wiring (the potential related to the new information) is applied to one of the electrodes of the capacitor element 164. After that, the potential of the second wiring is set to a potential at which the transistor 160 is turned off, and the transistor 160 is turned off. By doing so, the capacitor element 164 assumes a state in which charge related to new information is applied. In this way, the semiconductor device according to the disclosed invention can directly rewrite information by re-writing the information again. For this reason, high-speed operation of the semiconductor device is realized.

[0221] In this way, the semiconductor device according to the disclosed invention can directly rewrite information by re-writing the information again. Therefore, high-speed operation of the semiconductor device is achieved.

[0222] Note that the above description is for the case of using an n-type transistor (n-channel transistor) with electrons as carriers, but it goes without saying that a p-type transistor with holes as majority carriers can be used instead of the n-type transistor. Note that the above description pertains to the case of using an n-type transistor (n-channel transistor) with electrons as carriers, but it goes without saying that a p-type transistor with holes as majority carriers can be used instead of the n-type transistor. Of course, a p-type transistor with holes as majority carriers can be used instead of the n-type transistor.

[0223] (Embodiment 4) In this embodiment, a semiconductor device configured using the semiconductor devices of Embodiments 1 to 3 will be described with reference to FIGS. 10 to 12. Regarding the configuration of the semiconductor device, it will be described with reference to FIGS. 10 to 12.

[0224] 〈Configuration of Semiconductor Device〉 FIG. 10(A) shows a conceptual diagram illustrating an example of the configuration of a semiconductor device. A semiconductor device according to an aspect of the present invention has a memory circuit at the upper part and peripheral circuits such as a drive circuit and a control circuit that require high-speed operation to drive the memory circuit at the lower part, and is a semiconductor device having a stacked structure. Note that the drive circuit and the control circuit may be logic circuits or may have analog circuits. Further, they may have arithmetic circuits. The semiconductor device shown in FIG. 10(A) has a memory cell array 201 having a plurality of memory cells as a memory circuit at the upper part, and at the lower part, a first drive circuit 211, a second drive circuit 212, a third drive circuit 213, a fourth drive circuit 214, a fifth drive circuit 215, a controller 218, an address buffer 221, an I / O buffer 220, and other peripheral circuits 210 necessary for operating the memory cell array 201. The first drive circuit 211 has a column decoder 217a and a sense amplifier group 216a, and the second drive circuit 212 has a column decoder 217b and a sense amplifier group 216b. As the substrate on which the peripheral circuit 210 shown in FIG. 10(A) is provided, for example, a semiconductor substrate made of a Group 14 element such as silicon, germanium, silicon germanium, silicon carbide, a compound semiconductor substrate such as gallium arsenide or indium phosphide, an SOI substrate, etc. may be applied.

[0225] The semiconductor device shown in FIG. 10(A) has a memory cell array 201 having a plurality of memory cells as a memory circuit at the upper part, and at the lower part, a first drive circuit 211, a second drive circuit 212, a third drive circuit 213, a fourth drive circuit 214, a fifth drive circuit 215, a controller 218, an address buffer 221, an I / O buffer 220, and other peripheral circuits 210 necessary for operating the memory cell array 201. The first drive circuit 211 has a column decoder 217a and a sense amplifier group 216a, and the second drive circuit 212 has a column decoder 217b and a sense amplifier group 216b. 3 drive circuit 213, fourth drive circuit 214, fifth drive circuit 215, controller 21 8, address buffer 221, I / O buffer 220, etc. have peripheral circuits 210 necessary for operating the memory cell array 201. The first drive circuit 211 has a column decoder 217a and a sense amplifier group 216a, and the second drive circuit 212 has a column decoder 217b and a sense amplifier group 216b. der 217a and sense amplifier group 216a, and the second drive circuit 212 has a column decoder 217b and a sense amplifier group 216b. der 217b and sense amplifier group 216b.

[0226] As the substrate on which the peripheral circuit 210 shown in FIG. 10(A) is provided, for example, a semiconductor substrate made of a Group 14 element such as silicon, germanium, silicon germanium, silicon carbide, a compound semiconductor substrate such as gallium arsenide or indium phosphide, an SOI substrate, etc. may be applied. Further, a compound semiconductor substrate such as gallium arsenide or indium phosphide, an SOI substrate, etc. may be applied. ​​​​It is possible. In general, a "SOI substrate" refers to a substrate having a silicon layer provided on an insulating surface. However, in this specification and the like, a substrate having a semiconductor layer made of a material other than silicon provided on an insulating surface is also included. Further, the SOI substrate includes those having a configuration in which a semiconductor layer is provided via an insulating layer on any insulating substrate such as a glass substrate. By forming the peripheral circuit 210 using the above-described substrate, the peripheral circuit 210 can be operated at high speed, which is preferable. In the present specification, a substrate having a semiconductor layer made of a material other than silicon provided on an insulating surface is also included. Further, the SOI substrate includes those having a configuration in which a semiconductor layer is provided via an insulating layer on any insulating substrate such as a glass substrate. It is assumed to include. By forming the peripheral circuit 210 using the above-described substrate, the peripheral circuit 210 can be operated at high speed, which is preferable. Since it can be made to operate, it is preferable.

[0227] 〈Cross-sectional configuration of semiconductor device〉 FIG. 10(B) is a cross-sectional view of a semiconductor device. The semiconductor device shown in FIG. 10 has a memory cell array 201 at the upper part and a peripheral circuit 210 at the lower part. In the upper memory cell array 201, there is a transistor 160 using an oxide semiconductor, and in the lower peripheral circuit 210, there is a transistor 159 using a semiconductor material other than an oxide semiconductor. For details of the memory cell 170 provided at the upper part of the semiconductor device, reference can be made to the descriptions in Embodiments 1 to 3. In the upper memory cell array 201, there is a transistor 160 using an oxide semiconductor, and in the lower peripheral circuit 210, there is a transistor 159 using a semiconductor material other than an oxide semiconductor. In the upper memory cell array 201, there is a transistor 160 using an oxide semiconductor, and in the lower peripheral circuit 210, there is a transistor 159 using a semiconductor material other than an oxide semiconductor. Note that for details of the memory cell 170 provided at the upper part of the semiconductor device, reference can be made to the descriptions in Embodiments 1 to 3. For details of the memory cell 170 provided at the upper part of the semiconductor device, reference can be made to the descriptions in Embodiments 1 to 3. It can be considered.

[0228] For the transistor 159 and the transistor 160, either an n-channel type transistor or a p-channel type transistor can be used. Here, the transistor 159 and the transistor 160 will both be described as n-channel type transistors. Further, in one aspect of the present invention, the technical essence lies in using a semiconductor material capable of sufficiently reducing an off-current such as an oxide semiconductor to hold information for the transistor 160 and the capacitor element 164. Therefore, materials used in the semiconductor device, the structure of the semiconductor device, etc. For the transistor 159 and the transistor 160, either an n-channel type transistor or a p-channel type transistor can be used. Here, the transistor 159 and the transistor 160 will both be described as n-channel type transistors. In one aspect of the present invention, the technical essence lies in using a semiconductor material capable of sufficiently reducing an off-current such as an oxide semiconductor to hold information. For the transistor 160 and the capacitor element 164, a semiconductor material capable of sufficiently reducing an off-current such as an oxide semiconductor is used. For the transistor 160 and the capacitor element 164, a semiconductor material capable of sufficiently reducing an off-current such as an oxide semiconductor is used. Therefore, materials used in the semiconductor device, the structure of the semiconductor device, etc. It is not necessary to limit the specific configuration to what is shown here.

[0229] The transistor 159 is provided on a substrate 100 containing a semiconductor material (e.g., silicon, etc.) with a channel formation region 116, an impurity region 120 provided so as to sandwich the channel formation region 116, a metal compound region 124 in contact with the impurity region 120, a gate insulating layer 108 provided on the channel formation region 1 16, a gate electrode 110 provided on the gate insulating layer 108, and a source electrode or drain electrode 1 30b, a drain electrode or source electrode 130a, which is electrically connected to the metal compound region 124. Further, an insulating layer 128 is provided so as to cover the transistor 16 0. The source electrode or drain electrode 130 b, the drain electrode or source electrode 130a is electrically connected to the metal compound region 124 through an opening formed in the insulating layer 128. Also, on the insulating layer 128, an electrode 136a is formed in contact with the source electrode or drain electrode 130b, and an electrode 136b is formed in contact with the drain electrode or source electrode 130a. Also, an element isolation insulating layer 106 is provided on the substrate 100 so as to surround the transistor 159. In order to achieve high integration, it is desirable to adopt a configuration in which the transistor

[0230] 159 has no sidewall insulating layer as shown in FIG. 10(B). On the other hand, when emphasizing the characteristics of the transistor 159, a sidewall insulating layer may be provided on the side surface of the gate electrode 110, and the impurity region 120 may be provided including regions having different impurity concentrations formed in a region overlapping with the sidewall insulating layer. 159.

[0231] ​​​In the transistor 160 of FIG. 10(B), the transistor 160 or the transistor 162 shown in Embodiments 1 to 3 can be applied.

[0232] In the capacitor element 164, the capacitor element 164 shown in Embodiments 1 to 3 can be applied.

[0233] An insulating layer 150 and an insulating layer 154 are provided over the transistor 160 and the capacitor element 164. And a wiring 156 is electrically connected to a drain electrode or a source electrode 142a of the transistor 160 through an opening formed in the insulating layer 150, the insulating layer 154, etc. The wiring 156 is a wiring that electrically connects one memory cell and other memory cells. Further, the wiring 156 is electrically connected to the drain electrode or the source electrode 142a and the electrode 126, and is electrically connected to the electrode 130c via the electrode 126. Thereby, the lower layer peripheral circuit 210 and the upper layer memory cell array 201 can be electrically connected.

[0234] In the semiconductor device shown in FIG. 10(B), an insulating layer 140 is provided between the upper memory cell array 201 and the lower peripheral circuit 210.

[0235] In the transistor 159, a semiconductor material other than an oxide semiconductor is used. As the semiconductor material other than the oxide semiconductor, for example, silicon, germanium, silicon germanium, silicon carbide, or gallium arsenide, etc. can be used, and it is preferable to use a single crystal semiconductor. Alternatively, an organic semiconductor material or the like may be used. A transistor using such a semiconductor material can operate at a sufficiently high speed. Therefore, a material other than the oxide semiconductor ​​​​​​​​​​​​​With the transistors used, various circuits (logic circuits, drive circuits, etc.) that require high-speed operation can be suitably realized.

[0236] On the other hand, in the transistor 160, an oxide semiconductor material is used. As disclosed in this specification A transistor using the oxide semiconductor material shown can achieve an extremely small off-current . Due to this characteristic, in the memory cell 170, it is possible to retain the stored content for an extremely long time . That is, the refresh operation becomes unnecessary or the frequency of the refresh operation can be made extremely low, so that the power consumption can be reduced. Also , even when there is no power supply (however, it is desirable that the potential is fixed) , it is possible to retain the stored content for a long time.

[0237] In addition, a capacitor element 164 to which a capacitor element using the above-described oxide semiconductor as a dielectric is applied . Since the oxide semiconductor has a high dielectric constant, by using it as the dielectric of the capacitor element 164, the capacitance per unit area of the capacitor element 164 can be increased.

[0238] In this way, by integrating a peripheral circuit such as a drive circuit using a transistor using a material other than the oxide semiconductor (a transistor capable of operating at a higher speed than a transistor using the oxide semiconductor) and a memory circuit having a transistor using the oxide semiconductor (more broadly, a transistor having a sufficiently small off-current ) and a capacitor element using the oxide semiconductor, a semiconductor device having unprecedented characteristics can be realized. ) and a capacitor element using the oxide semiconductor, a semiconductor device having unprecedented characteristics can be realized.

[0239] Note that in FIG. 10, a single-layer memory cell array 201 is stacked on the peripheral circuit 210 Although an example has been shown, one aspect of the present invention is not limited thereto. As shown in FIGS. 11 and 12, two or more memory cell arrays may be stacked.

[0240] FIGS. 11 and 12 are cross-sectional views of a memory device. The memory device shown in FIGS. 11 and 12 has a plurality of memory cells formed in multiple layers at the upper part and a peripheral circuit 304 at the lower part. Among the plurality of memory cells, memory cell 370a and memory cell 370b are shown as representatives.

[0241] Note that the transistor 371a and the capacitor element 372a included in the memory cell 370a are shown in representative form. The transistor 371b and the capacitor element 372b included in the memory cell 370b are shown as representatives. The transistors 371a and 371b are transistors in which a channel is formed in an oxide semiconductor layer. Since the configuration of the transistor in which a channel is formed in the oxide semiconductor layer is the same as the configuration described in other embodiments, the description thereof is omitted. The capacitor elements 372a and 372b are capacitor elements using an oxide semiconductor as a dielectric. Since the capacitor element using an oxide semiconductor as a dielectric is the same as the configuration described in other embodiments, the description thereof is omitted.

[0242] An electrode 351a formed in the same layer as the source electrode and the drain electrode of the transistor 371a is electrically connected to the electrode 303a by an electrode 352a. An electrode 351c formed in the same layer as the source electrode and the drain electrode of the transistor 371b is electrically connected to the electrode 303c by an electrode 352c.

[0243] ​​​​In addition, the peripheral circuit 304 uses a semiconductor material other than an oxide semiconductor for a channel formation region. The transistor 301 is made of a semiconductor material (e.g., silicon An element isolation insulating layer 306 is provided on a substrate 300 including the above-mentioned elements, and the element isolation insulating layer 306 surrounds the substrate 300. A transistor can be obtained by forming a channel region in the region. The transistor 301 can be formed on a semiconductor layer such as a silicon layer on an insulating surface. Alternatively, the transistor may have a channel formed in the silicon layer of the SOI substrate. The configuration of the transistor 301 can be a known configuration, so the description will be omitted. Omitted.

[0244] Between the layer in which the transistor 371a is formed and the layer in which the transistor 301 is formed, The wiring 310a and the transistor 301 are formed. An insulating layer 340a is provided between the wiring 310a and the wiring 310b. An insulating layer 341a is provided between them, and a wiring 310b and a transistor 371a are formed. An insulating layer 342a is provided between the layers.

[0245] Similarly, a layer in which the transistor 371b is formed and a layer in which the transistor 371a is formed Between the wiring 310c and the transistor, a wiring 310c and a wiring 310d are formed. An insulating layer 340b is provided between the layer on which the stator 371a is formed and the wiring 310c and the wiring An insulating layer 341b is provided between the wiring 310d and the transistor 371. An insulating layer 342b is provided between the layer on which b is formed.

[0246] Insulating layers 340a, insulating layer 341a, insulating layer 342a, insulating layer 340b, insulating layer 341b, Insulating layer 342b functions as an interlayer insulating layer, and its surface can be planarized. It can be done.

[0247] Wiring 310a, wiring 310b, wiring 310c, and wiring 310d can be used to make electrical connections between memory cells, electrical connections between the peripheral circuit 304 and the memory cells, and so on. It can be done.

[0248] The electrode 303 included in the peripheral circuit 304 can be electrically connected to the circuit provided above. It can be done.

[0249] For example, as shown in FIG. 11, the electrode 303 can be electrically connected to the wiring 310a by the electrode 355. The wiring 310a can be electrically connected to the electrode 351b by the electrode 353a. The electrode 351b is formed in the same layer as the transistor 371a, and although not shown in the figure, it can be electrically connected to the transistor 371a or the capacitor element 372a. Also, the electrode 351b can be electrically connected to the wiring 353b by the electrode 352b. The wiring 353b can be electrically connected to the wiring 310c by the electrode 303b. It can be done. The electrode 351b is formed in the same layer as the transistor 371a, and although not shown in the figure, it can be electrically connected to the transistor 371a or the capacitor element 372a. It can be done. Also, the electrode 351b can be electrically connected to the wiring 353b by the electrode 352b. The wiring 353b can be electrically connected to the wiring 310c by the electrode 303b. It can be done.

[0250] In FIG. 11, an example is shown in which the electrical connection between the electrode 303 and the transistor 371a is made via the wiring 310a, but it is not limited to this. The electrical connection between the electrode 303 and the transistor 371a may be made via the wiring 310b, or may be made via both the wiring 310a and the wiring 310b. Also, as shown in FIG. 12, the electrical connection between the electrode 303 and the transistor 371a may be made without passing through either the wiring 310a or the wiring 310b. The electrical connection between the electrode 303 and the transistor 371a is not limited to this example. The electrical connection between the electrode 303 and the transistor 371a may be made via the wiring 310b, or may be made via both the wiring 310a and the wiring 310b. Also, as shown in FIG. 12, the electrical connection between the electrode 303 and the transistor 371a may be made without passing through either the wiring 310a or the wiring 310b. In FIG. 12, the electrical connection between the electrode 303 and the transistor 371a may be made without passing through either the wiring 310a or the wiring 310b. The electrode 303 is electrically connected to the wiring 353b by the electrode 353. The wiring 353b is electrically connected to the source or drain of the transistor 371a. Thus, an electrical connection between the electrode 303 and the transistor 371a can be established.

[0251] In FIGS. 11 and 12, a configuration in which two memory cells (memory cell 370a and memory cell 3 70b) are stacked is shown as an example, but the number of stacked memory cells is not limited to this. It is not limited thereto.

[0252] Also, in FIGS. 11 and 12, between the layer in which the transistor 371a is formed and the layer in which the transistor 3 01 is formed, a configuration is shown in which two wiring layers, namely, a wiring layer in which the wiring 310a is formed and a wiring layer in which the wiring 310b is formed, are provided, but the present invention is not limited to this. Between the layer in which the transistor 371a is formed and the layer in which the transistor 301 is formed, one wiring layer may be provided, or three or more wiring layers may be provided. It is not limited thereto. One wiring layer may be provided, or three or more wiring layers may be provided.

[0253] Also, in FIGS. 11 and 12, between the layer in which the transistor 371b is formed and the layer in which the transistor 3 71a is formed, a configuration is shown in which two wiring layers, namely, a wiring layer in which the wiring 310c is formed and a wiring layer in which the wiring 310d is formed, are provided, but the present invention is not limited to this. Between the layer in which the transistor 371b is formed and the layer in which the transistor 371a is formed, one wiring layer may be provided, or three or more wiring layers may be provided. It is not limited thereto.

[0254] (Embodiment 5) In the present embodiment, the semiconductor device described in the previous embodiment is applied to a mobile phone, a smartphone, An example of applying to a portable device such as an e - book will be described with reference to FIGS. 13 to 16.

[0255] In portable devices such as mobile phones, smartphones, and e - books, SRAM or DRAM is used for temporary storage of image data. The reason for using SRAM or DRAM is that flash memory has a slow response and is not suitable for image processing. On the other hand, when SRAM or DRAM is used for temporary storage of image data, it has the following characteristics.

[0256] As shown in FIG. 13(A), a normal SRAM has one memory cell composed of six transistors 401 to 406, and is driven by an X - decoder 407 and a Y - decoder 408. Transistors 403 and 405, and transistors 404 and 406 form inverters, enabling high - speed driving. However, since one memory cell is composed of six transistors, it has the drawback of a large cell area. When the minimum dimension of the design rule is F, the memory cell area of SRAM is usually 100 - 150F. 2 Therefore, SRAM has the problem that the unit price per bit is the highest among various memories.

[0257] On the other hand, as shown in FIG. 13(B), a DRAM memory cell is composed of a transistor 411 and a capacitance element 412, and is driven by an X - decoder 413 and a Y - decoder 414. One cell has a configuration of one transistor and one capacitance, and the area is small. The memory cell area of DRAM is usually 10F or less. 2 However, DRAM always needs to be refreshed. ​​​​​​​​​​​​There is a problem that a shu is required and power consumption occurs even when rewriting is not performed. There is.

[0258] However, the memory cell area of the semiconductor device described in the previous embodiment is around 10F 2 or so , and frequent refreshing is not required. Therefore, a memory cell with a small area and reduced power consumption can be obtained. It can be made.

[0259] Next, FIG. 14 is a block diagram of a portable device. The portable device shown in FIG. 14 includes an RF circuit 501, an analog baseband circuit 502, a digital baseband circuit 503, a battery 504 , a power supply circuit 505, an application processor 506, a flash memory 510, a dis play controller 511, a memory circuit 512, a display 513, a touch sensor 5 19, an audio circuit 517, a keyboard 518, etc. The display 513 is composed of a display unit 514, a source driver 515, and a gate driver 516 . The application processor 506 has a CPU 507, a DSP 508, and an interface 509 (IF509). Generally, the memory circuit is composed of SRAM or DRAM , but by adopting the semiconductor device described in the previous embodiment for the memory circuit 512 , a portable device with high-speed information writing and reading and reduced power consumption can be obtained .

[0260] Next, FIG. 15 is an example in which the semiconductor device described in the previous embodiment is used for the memory circuit 600 of the display. The memory circuit 600 shown in FIG. 15 includes a memory 602, a memory 603, , a switch 604, a switch 605, and a memory controller 601. It is configured by Memory 602 and memory 603 are applied with the semiconductor device described in the previous embodiment. .

[0261] First, certain image data is formed by an application processor (not shown). This formed image data (input image data 1) is stored in memory 602 via switch 604. Then, the image data (stored image data 1) stored in memory 602 is sent to display 607 via switch 605 and display controller 606 and is displayed.

[0262] When there is no change in the input image data 1, the stored image data 1 is normally read from memory 602 via switch 605 by the display controller 606 at a period of about 30 to 60 Hz.

[0263] Next, for example, when the user performs an operation to rewrite the screen (that is, when there is a change in the input image data), the application processor forms new image data (input image data 2 ). The input image data 2 is stored in memory 603 via switch 604. During this time, the stored image data 1 is also periodically read from memory 602 via switch 605. When the new image data (stored image data 2) is completely stored in memory 603, starting from the next frame of display 607, the stored image data 2 is read out, and the stored image data 2 is sent to display 607 via switch 605 and display controller 606, and the display is performed. This reading continues until new image data is stored in memory 602.

[0264] ​​​​​​In this way, the memory 602 and the memory 603 alternately write and read data. The display 607 is displayed by reading out the data from the memory 602. The memory 603 is not limited to being separate memories, but may be a single memory divided and used. The semiconductor device described in the above embodiment may be used for the memory 602 and the memory 603. By using this technology, information can be written and read at high speed and power consumption is reduced. The display may be a display having a display.

[0265] Next, FIG. 16 is a block diagram of an electronic book. The electronic book shown in FIG. , power supply circuit 702, microprocessor 703, flash memory 704, audio circuit 70 5, keyboard 706, memory circuit 707, touch panel 708, display 709, The display controller 710 is configured as the semiconductor device described in the previous embodiment. The device can be used with a memory circuit 707. The memory circuit 707 temporarily stores the contents of the book. An example of a function that temporarily holds the contents of an e-book is For example, when a user is reading an e-book, the user may want to use the highlight function. In such a case, it is necessary to mark a specific part. The e-book has a highlight function that allows you to change the display color, underline, and By making the text bold or changing the font, you can differentiate it from the surroundings. The highlight function is a function that remembers and retains information about the areas specified by the user. If this information is to be stored for a longer period of time, it may be copied to flash memory 704. Even in such a case, the semiconductor device described in the above embodiment can be used. Therefore, an electronic book with high-speed information writing and reading and reduced power consumption can be achieved. It can be achieved.

[0266] (Embodiment 6) In this embodiment, when applying the semiconductor device described in the above embodiment to an electronic device, it will be described with reference to FIG. 17. In this embodiment, when applying the above semiconductor device to an electronic device such as a computer, a mobile phone (also referred to as a cellular phone or a mobile phone device), a portable information terminal (including a portable game machine, an audio reproduction device, etc.), a digital camera, a camera such as a digital video camera, an electronic paper, a television device (also referred to as a television or a television receiver), etc., it will be described. When applying the above semiconductor device to an electronic device, it will be described.

[0267] FIG. 17(A) shows a notebook personal computer, which is composed of a housing 801, a housing 802, a display unit 803, a keyboard 804, etc. At least one of the housing 801 and the housing 802 is provided with the semiconductor device shown in the previous embodiment. Therefore, a notebook personal computer with high-speed information writing and reading and reduced power consumption is realized. When applying the above semiconductor device to an electronic device, it will be described. A notebook personal computer with high-speed information writing and reading and reduced power consumption is realized.

[0268] FIG. 17(B) shows a tablet terminal 810. The tablet terminal 810 includes a housing 811 having a display unit 8 12, a housing 813 having a display unit 814, operation buttons 815, and an external interface 816. In addition, a stylus 817 for operating the tablet terminal 810, etc. are provided. Electronic circuits are provided inside the housing 811 and the housing 813, and the semiconductor device shown in the previous embodiment is provided in the electronic circuits. Therefore, when applying the above semiconductor device to an electronic device, it will be described. A tablet terminal with high-speed information writing and reading and reduced power consumption is realized.

[0269] FIG. 17(C) shows an electronic book 820 equipped with an electronic paper, which is composed of two housings, a housing 821 and a housing 82 3. Display units 8 25 and a display unit 827 are provided in the housing 821 and the housing 823, respectively. The housing 821 and the housing 823 are connected by a shaft portion 837 and can perform an opening / closing operation about the shaft portion 837. Further, the housing 8 21 is provided with a power source 831, operation keys 833, a speaker 835, etc. At least one of the housing 821 and the housing 823 is provided with the semiconductor device shown in the previous embodiment. Therefore, an electronic book with high-speed information writing and reading and reduced power consumption is realized.

[0270] FIG. 17(D) shows a mobile phone, which is composed of two housings, a housing 840 and a housing 841. Furthermore, the housing 840 and the housing 841 can be slid and overlapped from the state of being unfolded as shown in FIG. 17(D), enabling miniaturization suitable for portability. Also, the housing 841 is provided with a display panel 842, a speaker 843, a microphone 844, operation keys 845, a pointing device 846, a camera lens 847, an external connection terminal 84 8, etc. The housing 840 is provided with a solar cell 849 for charging the mobile phone , an external memory slot 850, etc. The antenna is built in the housing 841. At least one of the housing 840 and the housing 841 is provided with the semiconductor device shown in the previous embodiment. Therefore, information writing and reading are fast and power consumption is reduced. is provided. Therefore, information writing and reading are fast and power consumption A mobile phone with reduced power consumption is realized.

[0271] FIG. 17(E) is a digital camera, which is composed of a main body 861, a display unit 867, an eyepiece 863, an operation switch 864, a display unit 865, a battery 866, etc. A semiconductor device shown in the previous embodiment is provided inside the main body 861. Therefore, a digital camera with high-speed information writing and reading and reduced power consumption is realized. .

[0272] FIG. 17(F) is a television device 870, which is composed of a housing 871, a display unit 873, a stand 875, etc. The operation of the television device 870 can be performed by switches provided in the housing 871 or a remote control operation unit 880. A semiconductor device shown in the previous embodiment is mounted on the housing 871 and the remote control operation unit 880. Therefore, a television device with high-speed information writing and reading and reduced power consumption is realized. .

[0273] As described above, the electronic devices shown in this embodiment are equipped with the semiconductor devices according to the previous embodiment. Therefore, electronic devices with reduced power consumption are realized.

[0274] In the following Examples 1 and 2, the results of actually fabricating an oxide semiconductor layer and measuring its relative permittivity will be described with reference to FIGS. 18 to 20.

Example

[0275] As shown in FIG. 18(A), a 100-nm oxide semiconductor (denoted as OS in the figure) layer was formed on a p-type silicon substrate, and its CV (capacitance and voltage) was measured. In this example, the oxide semiconductor An In-Sn-Zn-O-based oxide was used as the conductor. Specifically, an oxide semiconductor layer was formed by sputtering using an oxide target with an atomic ratio of In:Sn:Zn = 2: 1:3 (atomic ratio). From the obtained CV measurement results, the capacitance (C )(see Fig. 18(B)) was determined 0 , and the relative permittivity was calculated using Equation 1 from the capacitance (C ). Here, let the relative permittivity of the oxide semiconductor be ε, the permittivity of vacuum be ε 0 , the area be S, and the relative permittivity be d. The measurement results of CV are shown in Fig. 19. The horizontal axis represents the applied voltage, and the vertical axis represents the capacitance. The number of samples n 0 = 7. As a result of the calculation, the relative permittivity (d) of the oxide semiconductor layer formed using an oxide target with an atomic ratio of In:Sn:Zn = 2:1:3 was approximately 20.

[0276]

Equation

[0277] is shown in Fig. 19. The horizontal axis represents the applied voltage, and the vertical axis represents the capacitance. The number of samples n = 7. As a result of the calculation, the relative permittivity (d) of the oxide semiconductor layer formed using an oxide target with an atomic ratio of In:Sn:Zn = 2:1:3 was approximately 20. The relative permittivity (d) of the oxide semiconductor layer formed using an oxide target with an atomic ratio of In:Sn:Zn = 2:1:3 was approximately 20.

Example

[0278] In this example, an In-Ga-Zn-O-based oxide formed using an oxide target with an atomic ratio of In:Ga:Zn = 1:1:1 was used as the oxide semiconductor, and the relative permittivity was measured in the same manner as in Example 1. The measurement results of CV are shown in Fig. 20. The number of samples n = 5. As a result of the calculation, the relative permittivity (d) of the oxide semiconductor layer formed using an oxide target with an atomic ratio of In:Ga:Zn = 1:1:1 was approximately 15.

[0279] The measurement results of CV are shown in Fig. 20. The number of samples n = 5. As a result of the calculation, the relative permittivity (d) of the oxide semiconductor layer formed using an oxide target with an atomic ratio of In:Ga:Z n = 1:1:1 was approximately 15. The relative permittivity (d) of the oxide semiconductor layer formed using an oxide target with an atomic ratio of In:Ga:Zn = 1:1:1 was approximately 15.

[0280] From the results of Example 1 and Example 2, the relative permittivity of the oxide semiconductor layer has a relative permittivity of approximately 4 It has been shown to be sufficiently high compared to the silicon oxide to be formed.

Explanation of Signs

[0281] 100 Substrate 106 Element isolation insulating layer 108 Gate insulating layer 110 Gate electrode 116 Channel formation region 120 Impurity region 124 Metal compound region 126 Electrode 128 Insulating layer 130a Drain electrode or source electrode 130b Source electrode or drain electrode 130c Electrode 136a Electrode 136b Electrode 140 Insulating layer 141a Metal oxide layer 141b Metal oxide layer 142 Conductive layer 142a Drain electrode or source electrode 142b Source electrode or drain electrode 144a First oxide semiconductor layer 144b Second oxide semiconductor layer 144c Impurity region 144d Impurity region 146 Gate insulating layer 147b Electrode 148 Conductive layer 148a Gate electrode 148b First electrode 149a Metal oxide layer 149b Metal oxide layer 150 Insulating layer 152 Electrode 154 Insulating layer 156 Wiring 159 Transistor 160 Transistor 162 Transistor 164 Capacitor element 170 Memory cells 201 Memory cell array 210 Peripheral circuits 211 Driving circuit 212 Driving circuit 213 Driving circuit 214 Driving circuit 215 Driving circuit 216a Sense amplifier group 216b Sense amplifier group 217a Column decoder 217b Column decoder 218 Controller 220 I / O buffer 221 Address buffer 300 Substrate 301 Transistor 303 Electrode 303a Electrode 303b Electrode 303c Electrode 304 Peripheral circuits 306 Element isolation insulating layer 310a Wiring 310b Wiring 310c Wiring 310d Wiring 340a Insulating layer 340b Insulating layer 341a Insulating layer 341b Insulating layer 342a Insulating layer 342b Insulating layer 351a Electrode 351b Electrode 351c Electrode 352a Electrode 352b Electrode 352c Electrode 353 Electrode 353a Electrode 353b Wiring 355 Electrode 370a Memory cells 370b Memory cells 371a Transistor 371b Transistor 372a capacitance element 372b capacitance element 401 transistor 402 transistor 403 transistor 404 transistor 405 transistor 406 transistor 407 X decoder 408 Y decoder 411 transistor 412 capacitance element 413 X decoder 414 Y decoder 501 RF circuit 502 analog baseband circuit 503 digital baseband circuit 504 battery 505 power supply circuit 506 application processor 507 CPU 508 DSP 509 interface 510 flash memory 511 display controller 512 memory circuit 513 display 514 display unit 515 source driver 516 gate driver 517 audio circuit 518 keyboard 519 touch sensor 600 memory circuit 601 memory controller 602 memory 603 memory 604 switch 605 switch 606 display controller 607 display 701 battery 702 power supply circuit 703 Microprocessor 704 Flash Memory 705 Audio Circuit 706 Keyboard 707 Memory Circuit 708 Touch Panel 709 Display 710 Display Controller 801 Housing 802 Housing 803 Display Unit 804 Keyboard 810 Tablet Terminal 811 Housing 812 Display Unit 813 Housing 814 Display Unit 815 Operation Button 816 External Interface 817 Stylus 820 E-book 821 Housing 823 Housing 825 Display Unit 827 Display Unit 831 Power Supply 833 Operation Key 835 Speaker 837 Shaft Portion 840 Housing 841 Housing 842 Display Panel 843 Speaker 844 Microphone 845 Operation Key 846 Pointing Device 847 Camera Lens 848 External Connection Terminal 849 Solar Cell 850 External Memory Slot 861 Main Body 863 Eyepiece 864 Operation Switch 865 Display Unit 866 Battery 867 Display Unit 870 Television apparatus 871 Housing 873 Display unit 875 Stand 880 Remote control unit

Claims

[Claim 1] A transistor and a capacitor are included. the transistor includes a gate electrode, a gate insulating layer on the gate electrode, a first oxide semiconductor layer overlapping with the gate electrode on the gate insulating layer, a source electrode and a drain electrode electrically connected to the first oxide semiconductor layer on the first oxide semiconductor layer, an insulating layer on the first oxide semiconductor layer, the source electrode, and the drain electrode, and an electrode overlapping with the first oxide semiconductor layer on the insulating layer; the capacitor includes a first electrode, a second oxide semiconductor layer in contact with the first electrode, and a second electrode in contact with the second oxide semiconductor layer and made of the same conductive layer as the source electrode or the drain electrode; The first oxide semiconductor layer and the second oxide semiconductor layer are an oxide semiconductor which is non-single crystal and has a triangular or hexagonal atomic arrangement as viewed from the a-b plane, and includes a phase in which a metal element is arranged in a layered manner or the metal element and an oxygen element are arranged in a layered manner along the c-axis; or an oxynitride semiconductor which is non-single crystal and has a triangular or hexagonal atomic arrangement as viewed from the a-b plane, and includes a phase in which a metal element is arranged in a layered manner or the metal element and an oxygen element are arranged in a layered manner along the c-axis.

Images