Display device and manufacturing method of the display device

Abstract

To suppress deterioration of reliability.SOLUTION: A display device according an embodiment, comprises: a first inorganic insulation layer that is arranged over a display region that displays an image and a peripheral region on the side from the display region; an organic insulation layer that is arranged onto the first inorganic insulation layer; a lower electrode that is arranged onto the organic insulation layer in the display region; an organic layer that is arranged onto the lower electrode, and contains a light emission layer; an upper electrode that is arranged onto the organic layer; a second inorganic insulation layer that is arranged onto the organic insulation layer, and includes an open exposing an edge part of the organic insulation layer in the peripheral region; a plurality of wirings that is arranged to between the substrate and the first inorganic insulation layer, and is crossed to the edge part in a plan view; and a plurality of protection layers that is crossed to the edge part in the plan view. One of the protection layers is opposite to one of the wirings, and is overlapped with the first inorganic insulation layer exposed from the organic insulation layer in the open.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] Embodiments of the present invention relate to a display device and a method for manufacturing the display device.

Background Art

[0002] In recent years, display devices applying organic light-emitting diodes (OLEDs) as display elements have been put into practical use. This display element includes a pixel circuit including a thin-film transistor, a lower electrode connected to the pixel circuit, an organic layer covering the lower electrode, and an upper electrode covering the organic layer. The organic layer includes functional layers such as a hole transport layer and an electron transport layer in addition to the light-emitting layer. In the process of manufacturing such a display element, a technique for suppressing a decrease in reliability is required.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Patent Document 7

Summary of the Invention

Problems to be Solved by the Invention

[0004] An object of the present invention is to provide a display device and a method for manufacturing the display device capable of suppressing a decrease in reliability.

Means for Solving the Problem

[0005] According to one embodiment, a display device includes a substrate, a first inorganic insulating layer disposed above the substrate and extending over a display area for displaying an image and a peripheral area outside the display area, an organic insulating layer disposed on the first inorganic insulating layer, a lower electrode disposed on the organic insulating layer in the display area, an organic layer including a light-emitting layer disposed on the lower electrode, an upper electrode disposed on the organic layer, a second inorganic insulating layer disposed on the organic insulating layer and having an opening exposing an edge of the organic insulating layer in the peripheral area, a plurality of wirings disposed between the substrate and the first inorganic insulating layer and intersecting the edge in a plan view, and a plurality of protective layers intersecting the edge in a plan view, wherein one of the protective layers faces one of the wirings and overlaps the first inorganic insulating layer exposed from the organic insulating layer in the opening.

[0006] According to one embodiment, a method for manufacturing a display device includes forming a wiring above a substrate, forming a first inorganic insulating layer on the wiring, forming an organic insulating layer on the first inorganic insulating layer, forming a lower electrode on the organic insulating layer, forming a protective layer facing the wiring and overlapping the first inorganic insulating layer exposed from the organic insulating layer, forming a second inorganic insulating layer covering the organic insulating layer and the protective layer, forming an opening overlapping an edge of the organic insulating layer in the second inorganic insulating layer, forming an organic layer on the lower electrode, and forming an upper electrode on the organic layer.

Brief Description of the Drawings

[0007]

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MODE FOR CARRYING OUT THE INVENTION

[0008] One embodiment will be described with reference to the drawings. The disclosure is merely an example, and for those skilled in the art, obvious appropriate modifications that maintain the gist of the invention are naturally included in the scope of the present invention. Also, for the purpose of making the description clearer, the drawings may schematically represent the width, thickness, shape, etc. of each part compared to the actual aspect, but this is merely an example and does not limit the interpretation of the present invention. Further, in this specification and each drawing, components that exhibit the same or similar functions as those described above with respect to the previously shown drawings may be given the same reference numerals, and detailed descriptions thereof may be omitted as appropriate.

[0009] Note that in the drawings, for ease of understanding as necessary, the X-axis, Y-axis, and Z-axis orthogonal to each other are described. The direction along the X-axis is referred to as the first direction X, the direction along the Y-axis is referred to as the second direction Y, and the direction along the Z-axis is referred to as the third direction Z. Looking at various elements parallel to the third direction Z is referred to as a plan view. The first direction X and the second direction Y are directions parallel to the main surface of the substrate constituting the display device, and the third direction Z corresponds to the thickness direction (the normal direction of the main surface) of the display device.

[0010] The display device according to this embodiment is an organic electroluminescence display device including an organic light-emitting diode (OLED) as a display element, and can be mounted on a television, a personal computer, in-vehicle equipment, a tablet terminal, a smartphone, a mobile phone terminal, or the like.

[0011] FIG. 1 is a diagram showing a configuration example of a display device DSP.

[0012] The display device DSP includes a display panel PNL having a display area DA for displaying an image and a peripheral area SA outside the display area DA on an insulating substrate 10. The substrate 10 may be glass or a resin film having flexibility.

[0013] In this embodiment, the shape of the substrate 10 in plan view is rectangular. The substrate 10 in the illustrated example has a long side parallel to the first direction X and a short side parallel to the second direction Y. However, the shape of the substrate 10 in plan view is not limited to a rectangle, and may be other shapes such as a square, a circle, or an ellipse.

[0014] The display area DA includes a plurality of pixels PX arranged in a matrix in the first direction X and the second direction Y. The pixel PX includes a plurality of sub-pixels SP. In one example, the pixel PX includes a sub-pixel SP1 of a first color, a sub-pixel SP2 of a second color, and a sub-pixel SP3 of a third color. The first color, the second color, and the third color are different from each other. Note that the pixel PX may include sub-pixels SP of other colors such as white, together with or instead of the sub-pixels SP1, SP2, and SP3.

[0015] The sub-pixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a driving transistor 3, and a capacitor 4. The pixel switch 2 and the driving transistor 3 are switching elements constituted by, for example, thin film transistors.

[0016] The gate electrode of pixel switch 2 is connected to the scanning line GL. One of the source electrode and the drain electrode of pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of driving transistor 3 and capacitor 4. In driving transistor 3, one of the source electrode and the drain electrode is connected to the power supply line PL and capacitor 4, and the other is connected to the anode of display element DE.

[0017] Note that the configuration of pixel circuit 1 is not limited to the illustrated example. For example, pixel circuit 1 may include more thin film transistors and capacitors.

[0018] Display element DE is an organic light emitting diode (OLED) as a light emitting element, and may be referred to as an organic EL element.

[0019] Peripheral region SA includes a plurality of mounting terminals MT and a plurality of inspection terminals TT. Mounting terminal MT is a terminal electrically connected to a signal source such as a flexible printed circuit board or an IC chip, and is electrically connected to various wirings (scanning line, signal line, power supply line, touch sensor wiring, etc.) in display region DA. Inspection terminal TT is a terminal electrically connected to an inspection device for performing inspections such as short circuits and disconnections of various wirings and operation confirmation of various circuits. These inspection terminals TT are electrically connected to mounting terminal MT via connection wiring CN, for example. Also, inspection terminal TT is connected to at least one of a plurality of wirings LA and LB extending toward substrate end 10E. That is, the plurality of inspection terminals TT includes an inspection terminal TT connected only to wiring LA and an inspection terminal TT connected to both wiring LA and wiring LB.

[0020] In the illustrated example, the plurality of mounting terminals MT and the plurality of inspection terminals TT are both arranged along substrate end 10E and are aligned in the first direction X.

[0021] Figure 2 is a diagram showing an example of the layout of sub-pixels SP1, SP2, and SP3.

[0022] In the illustrated example, sub-pixels SP2 and SP3 are arranged in the second direction Y. Sub-pixels SP1 and SP2 are arranged in the first direction X, and sub-pixels SP1 and SP3 are arranged in the first direction X.

[0023] When the sub-pixels SP1, SP2, and SP3 are in such a layout, in the display area DA, columns in which the sub-pixels SP2 and SP3 are alternately arranged in the second direction Y and columns in which a plurality of sub-pixels SP1 are arranged in the second direction Y are formed. These columns are alternately arranged in the first direction X.

[0024] Note that the layout of the sub-pixels SP1, SP2, and SP3 is not limited to the example of FIG. 2. As another example, the sub-pixels SP1, SP2, and SP3 in each pixel PX may be arranged in order in the first direction X.

[0025] In the display area DA, an insulating layer 5 and a partition wall 6 are arranged. The insulating layer 5 has openings AP1, AP2, and AP3 in the sub-pixels SP1, SP2, and SP3, respectively. The insulating layer 5 having these openings AP1, AP2, and AP3 may be referred to as a rib.

[0026] The partition wall 6 overlaps the insulating layer 5 in a plan view. The partition wall 6 is formed in a lattice shape surrounding the openings AP1, AP2, and AP3. It can also be said that the partition wall 6 has openings in the sub-pixels SP1, SP2, and SP3 similar to the insulating layer 5. The partition wall 6 has conductivity and is electrically connected to the mounting terminal MT of the common potential among the plurality of mounting terminals MT shown in FIG. 1.

[0027] The sub-pixels SP1, SP2, and SP3 each include display elements DE1, DE2, and DE3 as display elements DE.

[0028] The display element DE1 of the sub-pixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 that respectively overlap with the aperture AP1. The peripheral portion of the lower electrode LE1 is covered with an insulating layer 5. The lower electrode LE1, the organic layer OR1, and the upper electrode UE1 are surrounded by a partition wall 6 in a plan view. The peripheral portions of the organic layer OR1 and the upper electrode UE1 respectively overlap with the insulating layer 5 in a plan view. The organic layer OR1 includes, for example, a light-emitting layer that emits light in the blue wavelength range.

[0029] The display element DE2 of the sub-pixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that respectively overlap with the aperture AP2. The peripheral portion of the lower electrode LE2 is covered with an insulating layer 5. The lower electrode LE2, the organic layer OR2, and the upper electrode UE2 are surrounded by a partition wall 6 in a plan view. The peripheral portions of the organic layer OR2 and the upper electrode UE2 respectively overlap with the insulating layer 5 in a plan view. The organic layer OR2 includes, for example, a light-emitting layer that emits light in the green wavelength range.

[0030] The display element DE3 of the sub-pixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that respectively overlap with the aperture AP3. The peripheral portion of the lower electrode LE3 is covered with an insulating layer 5. The lower electrode LE3, the organic layer OR3, and the upper electrode UE3 are surrounded by a partition wall 6 in a plan view. The peripheral portions of the organic layer OR3 and the upper electrode UE3 respectively overlap with the insulating layer 5 in a plan view. The organic layer OR3 includes, for example, a light-emitting layer that emits light in the red wavelength range.

[0031] In the illustrated example, the outer shapes of the lower electrodes LE1, LE2, and LE3 are shown by dotted lines, and the outer shapes of the organic layers OR1, OR2, and OR3 and the upper electrodes UE1, UE2, and UE3 are shown by dashed-dotted lines. Note that the outer shapes of the illustrated lower electrodes, organic layers, and upper electrodes do not necessarily reflect the exact shapes.

[0032] The lower electrodes LE1, LE2, and LE3 correspond to, for example, the anode of the display element. The upper electrodes UE1, UE2, and UE3 correspond to the cathode or the common electrode of the display element and are in contact with the partition wall 6.

[0033] The lower electrode LE1 is electrically connected to the pixel circuit 1 (see FIG. 1) of the sub-pixel SP1. The lower electrode LE2 is electrically connected to the pixel circuit 1 of the sub-pixel SP2. The lower electrode LE3 is electrically connected to the pixel circuit 1 of the sub-pixel SP3.

[0034] In the illustrated example, the areas of the openings AP1, AP2, and AP3 are different from each other. The area of the opening AP1 is larger than the area of the opening AP2, and the area of the opening AP2 is larger than the area of the opening AP3. In other words, the area of the lower electrode LE1 exposed from the opening AP1 is larger than the area of the lower electrode LE2 exposed from the opening AP2, and the area of the lower electrode LE2 exposed from the opening AP2 is larger than the area of the lower electrode LE3 exposed from the opening AP3.

[0035] FIG. 3 is a schematic cross-sectional view of the display device DSP along the line A-B in FIG. 2.

[0036] The circuit layer 11 is disposed on the substrate 10. The circuit layer 11 includes various circuits such as the pixel circuit 1 shown in FIG. 1, various wirings such as the scanning line GL, the signal line SL, and the power line PL, and various insulating layers. The circuit layer 11 is covered by an insulating layer 12. The insulating layer 12 is an organic insulating layer that planarizes the unevenness generated by the circuit layer 11.

[0037] The lower electrodes LE1, LE2, and LE3 are disposed on the insulating layer 12 and are spaced apart from each other. The insulating layer 5 is an inorganic insulating layer and is disposed on the insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The opening AP1 of the insulating layer 5 overlaps the lower electrode LE1, the opening AP2 overlaps the lower electrode LE2, and the opening AP3 overlaps the lower electrode LE3. The peripheral portions of the lower electrodes LE1, LE2, and LE3 are covered by the insulating layer 5. The lower electrodes LE1, LE2, and LE3 are connected to the respective pixel circuits 1 of the sub-pixels SP1, SP2, and SP3 through contact holes provided in the insulating layer 12. Note that the contact holes in the insulating layer 12 are omitted in FIG. 3.

[0038] The partition wall 6 includes a conductive lower part 61 disposed on the insulating layer 5 and an upper part 62 disposed on the lower part 61. The upper part 62 has a width larger than that of the lower part 61. Both ends of the upper part 62 protrude beyond the side surfaces of the lower part 61. Such a shape of the partition wall 6 is called an overhang shape.

[0039] In the illustrated example, the lower part 61 has a conductive layer 63 disposed on the insulating layer 5 and a conductive layer 64 disposed on the conductive layer 63. For example, the conductive layer 63 is formed thinner than the conductive layer 64. Also, in the illustrated example, both ends of the conductive layer 63 protrude from the side surfaces of the conductive layer 64. The upper part 62 has a thin film 65 disposed on the conductive layer 64 and a thin film 66 disposed on the thin film 65. Both ends of the thin films 65 and 66 protrude from the side surfaces of the conductive layer 64. The thin films 65 and 66 may be conductive layers or insulating layers.

[0040] The organic layer OR1 contacts the lower electrode LE1 through the opening AP1, covers the lower electrode LE1 exposed from the opening AP1, and its peripheral part is located on the insulating layer 5. The upper electrode UE1 covers the organic layer OR1 and contacts the lower part 61.

[0041] The organic layer OR2 contacts the lower electrode LE2 through the opening AP2, covers the lower electrode LE2 exposed from the opening AP2, and its peripheral part is located on the insulating layer 5. The upper electrode UE2 covers the organic layer OR2 and contacts the lower part 61.

[0042] The organic layer OR3 contacts the lower electrode LE3 through the opening AP3, covers the lower electrode LE3 exposed from the opening AP3, and its peripheral part is located on the insulating layer 5. The upper electrode UE3 covers the organic layer OR3 and contacts the lower part 61.

[0043] In the illustrated example, the sub-pixel SP1 has a cap layer CP1 and a sealing layer SE1, the sub-pixel SP2 has a cap layer CP2 and a sealing layer SE2, and the sub-pixel SP3 has a cap layer CP3 and a sealing layer SE3. The cap layers CP1, CP2, and CP3 each have a role as an optical adjustment layer for improving the light extraction efficiency of the light emitted from the organic layers OR1, OR2, and OR3. Note that the cap layers CP1, CP2, and CP3 may be omitted.

[0044] The cap layer CP1 is disposed on the upper electrode UE1. The cap layer CP2 is disposed on the upper electrode UE2. The cap layer CP3 is disposed on the upper electrode UE3.

[0045] The sealing layer SE1 is disposed on the cap layer CP1, contacts the partition wall 6, and continuously covers each member of the sub-pixel SP1. The sealing layer SE2 is disposed on the cap layer CP2, contacts the partition wall 6, and continuously covers each member of the sub-pixel SP2. The sealing layer SE3 is disposed on the cap layer CP3, contacts the partition wall 6, and continuously covers each member of the sub-pixel SP3.

[0046] In the illustrated example, a part of each of the organic layer OR1, the upper electrode UE1, and the cap layer CP1 is located on the partition wall 6 around the sub-pixel SP1. These portions are separated from the portions located in the opening AP1 (the portions constituting the display element DE1) of the organic layer OR1, the upper electrode UE1, and the cap layer CP1.

[0047] Similarly, a part of each of the organic layer OR2, the upper electrode UE2, and the cap layer CP2 is located on the partition wall 6 around the sub-pixel SP2, and these portions are separated from the portions located in the opening AP2 (the portions constituting the display element DE2) of the organic layer OR2, the upper electrode UE2, and the cap layer CP2.

[0048] Similarly, a part of each of the organic layer OR3, the upper electrode UE3, and the cap layer CP3 is located on the partition wall 6 around the sub-pixel SP3, and these portions are separated from the portions located in the opening AP3 (the portions constituting the display element DE3) among the organic layer OR3, the upper electrode UE3, and the cap layer CP3.

[0049] In the following description, the multilayer body including the organic layer OR1, the upper electrode UE1, and the cap layer CP1 is referred to as a stacked film FL1, the multilayer body including the organic layer OR2, the upper electrode UE2, and the cap layer CP2 is referred to as a stacked film FL2, and the multilayer body including the organic layer OR3, the upper electrode UE3, and the cap layer CP3 is referred to as a stacked film FL3.

[0050] The ends of the sealing layers SE1, SE2, SE3 and the ends of the stacked films FL1, FL2, FL3 are each located on the partition wall 6. In the illustrated example, the stacked film FL1 and the sealing layer SE1 on the partition wall 6 between the sub-pixels SP1 and SP2 are separated from the stacked film FL2 and the sealing layer SE2 on the same partition wall 6. Also, the stacked film FL1 and the sealing layer SE1 on the partition wall 6 between the sub-pixels SP1 and SP3 are separated from the stacked film FL3 and the sealing layer SE3 on the same partition wall 6.

[0051] The partition wall 6 and the sealing layers SE1, SE2, SE3 are covered by a resin layer 13. The resin layer 13 is covered by a sealing layer 14. The sealing layer 14 is covered by a resin layer 15.

[0052] The insulating layer 5, the sealing layers SE1, SE2, SE3, and the sealing layer 14 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3), for example.

[0053] The lower part 61 of the partition wall 6 is formed of a conductive material and is electrically connected to the upper electrodes UE1, UE2, and UE3. The conductive layer 63 is formed of a titanium-based material such as titanium or a titanium compound, for example. The conductive layer 64 is formed of a material different from that of the conductive layer 63 and the upper part 62, and is formed of an aluminum-based material such as aluminum or an aluminum compound, for example.

[0054] The upper part 62 of the partition wall 6 is formed of a conductive material, for example, but may also be formed of an insulating material. The upper part 62 is formed of a material different from that of the lower part 61. The thin film 65 is formed of a titanium-based material such as titanium or a titanium compound, for example. The thin film 66 is formed of an oxide conductive material such as indium tin oxide (ITO), for example.

[0055] The lower electrodes LE1, LE2, and LE3 are a multilayer body including a transparent layer formed of an oxide conductive material such as indium tin oxide (ITO), for example, and a reflective layer formed of a metal material such as silver. In one example, the lower electrodes LE1, LE2, and LE3 are a multilayer body including a reflective layer between a pair of transparent layers. The lower transparent layer functions as an adhesion layer that adheres to the insulating layer 12.

[0056] The organic layer OR1 includes the light-emitting layer EM1. The organic layer OR2 includes the light-emitting layer EM2. The organic layer OR3 includes the light-emitting layer EM3. The light-emitting layer EM1, the light-emitting layer EM2, and the light-emitting layer EM3 are formed of different materials from each other. In one example, the light-emitting layer EM1 is formed of a material that emits light in the blue wavelength range, the light-emitting layer EM2 is formed of a material that emits light in the green wavelength range, and the light-emitting layer EM3 is formed of a material that emits light in the red wavelength range. In addition, each of the organic layers OR1, OR2, and OR3 includes a plurality of functional layers such as a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer.

[0057] The upper electrodes UE1, UE2, and UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg), for example.

[0058] The cap layers CP1, CP2, and CP3 are a multilayer body of a plurality of thin films. The plurality of thin films are all transparent and have different refractive indices from each other.

[0059] The illustrated circuit layer 11, insulating layer 12, and insulating layer 5 are arranged across the display area DA and the peripheral area SA.

[0060] Figure 4 is a schematic cross-sectional view of the display device DSP along the C-D line in Figure 1.

[0061] The insulating layer 111 is an inorganic insulating layer and is arranged on the substrate 10. The plurality of wirings LA are arranged on the insulating layer 111. Such wirings LA are formed of a semiconductor such as polycrystalline silicon, for example. The insulating layer 112 is an inorganic insulating layer, is arranged on the insulating layer 111, and covers the wiring LA. The plurality of wirings LB are arranged on the insulating layer 112. Such wirings LB are formed of a metal material such as molybdenum, tungsten, titanium, aluminum, etc., for example. Also, the wiring LB is formed of the same material as the scanning line GL shown in Figure 1, for example. The insulating layer 113 is an inorganic insulating layer, is arranged on the insulating layer 112, and covers the wiring LB. The insulating layer 114 is an organic insulating layer and is arranged on the insulating layer 113.

[0062] The insulating layers 111, 112, and 113 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), etc., for example.

[0063] These insulating layers 111, 112, 113, 114, and the wirings LA and LB are included in the circuit layer 11 shown in Figure 3.

[0064] The insulating layer 12 is arranged on the insulating layer 114. The laminate of the insulating layer 12 and the insulating layer 114 is collectively referred to as the organic insulating layer IL. The insulating layer 5 is arranged on the insulating layer 12.

[0065] Next, a mother board 100 for a display device for collectively manufacturing a plurality of display devices DSP will be described (hereinafter simply referred to as the mother board).

[0066] FIG. 5 is a plan view showing a configuration example of the mother board 100.

[0067] The mother board 100 includes, on a large substrate 10, a plurality of panel portions PP and a margin portion MP outside these panel portions PP. The large substrate 10 is formed, for example, in a rectangular shape. In the illustrated example, two panel portions PP are shown as the plurality of panel portions PP, but more panel portions may be arranged in a matrix in the first direction X and the second direction Y. Each of the panel portions PP is taken out by cutting the mother board 100 along a cut line CL. Each of the taken-out panel portions PP corresponds to the display panel PNL shown in FIG. 1 and includes a display area DA and a peripheral area SA. The margin portion MP includes, for example, a plurality of TEG terminals TG electrically connected to a test element group (Test Element Group) or the like.

[0068] The connection wiring CA is arranged across the panel portion PP and the margin portion MP and electrically connects adjacent inspection terminals TT. The connection wiring CB is arranged in the margin portion MP and electrically connects the TEG terminal TG and the inspection terminal TT. When the mother board 100 is cut along the cut line CL, a part of the connection wiring CA remains in the display panel PNL as the wiring LA shown in FIG. 1, and a part of the connection wiring CB remains in the display panel PNL as the wiring LB shown in FIG. 1.

[0069] FIG. 6 is a plan view showing a configuration example of an area 100A of the mother board 100 shown in FIG. 5.

[0070] The cut line CL indicated by the dashed-dotted line in the figure can be the outer shape of the display panel PNL shown in FIG. 1. The organic insulating layer IL has an opening OPA along the outer shape of the panel portion PP. The cut line CL overlaps the opening OPA. The opening OPA is a penetrating portion of the organic insulating layer IL and exposes the base of the organic insulating layer IL.

[0071] In the illustrated region 100A, the insulating layer 5 has edges E11, E21, E32, E32. The insulating layer 12 has edges E12, E22. The insulating layer 114 has edges E13, E23. The edge E12 is located between the edge E11 and the edge E13. The edge E12 is located between the edge E21 and the edge E23. That is, in the organic insulating layer IL, the insulating layer 114 extends more toward the cut line CL than the insulating layer 12. The opening OPA is formed between the edges E13 and E23 that face each other with the cut line CL interposed therebetween.

[0072] The insulating layer 5 has an opening OPB that exposes the edges E12, E22 of the insulating layer 12 and the edges E13, E23 of the insulating layer 114. A part of the insulating layer 5 is located in the opening OPA. In a plan view, a part of the opening OPB overlaps the opening OPA.

[0073] One inspection terminal TT has one connection wiring CA and one connection wiring CB connected thereto. The connection wiring CA has a meandering portion and has a high resistance.

[0074] In a plan view, the connection wiring CA and the connection wiring CB intersect the edges E11, E12, E13, E31, E32, E23, E22, E21, respectively. The connection wiring CA and the connection wiring CB overlap the peripheral partition 7 in the region overlapping the organic insulating layer IL. The connection wiring CA and the connection wiring CB do not overlap the peripheral partition 7 and are bent so as to bypass the peripheral partition 7 in the region (opening OPA) where they do not overlap the organic insulating layer IL. Details of the peripheral partition 7 will be described later.

[0075] Each of the protective layers PR intersects with the edges E11, E12, E13, E31, E32, E23, E22, E21 respectively in a plan view and overlaps with the connection wiring CA or the connection wiring CB. More specifically, one protective layer PR is disposed at the intersections of one connection wiring CA and the edges E11, E12, E13, E31, and the other protective layer PR is disposed at the intersections of one connection wiring CA and the edges E32, E23, E22, E21. Also, one protective layer PR is disposed at the intersections of one connection wiring CB and the edges E11, E12, E13, E31, and the other protective layer PR is disposed at the intersections of one connection wiring CB and the edges E32, E23, E22, E21.

[0076] In a plan view, the edge E13 and the edge E31 face each other with a gap therebetween. Each of the edge E13 and the edge E31 is formed to have a zigzag shape between the connection wiring CA and the connection wiring CB.

[0077] In the illustrated example, the edge E31 and the edge E13 each extend in the first direction X and face each other with a gap in the second direction Y. The edge E31 has a tapered portion TP1 that bends so as to taper toward the edge E13 between the connection wiring CA and the connection wiring CB. The edge E13 has a tapered portion TP2 that bends so as to taper toward the edge E31 between the connection wiring CA and the connection wiring CB. The tapered portion TP1 is located between the two tapered portions TP2 and does not overlap the tapered portion TP2.

[0078] Similarly, the edge E23 and the edge E32 face each other with a gap and are formed to have a zigzag shape between the connection wiring CA and the connection wiring CB.

[0079] When the region 100A is severed by the cut line CL, the inspection terminal TT remains on the display panel, the connection wiring CA between the inspection terminal TT and the cut line CL remains on the display panel as the wiring LA, and the connection wiring CB between the inspection terminal TT and the cut line CL remains on the display panel as the wiring LB.

[0080] FIG. 7 is a cross-sectional view showing a configuration example of the mother substrate 100 along the E-F line in FIG. 6. Here, a cross-section including the overlapping portion of the connection wiring CB and the protective layer PR is shown.

[0081] The connection wiring CA is disposed on the insulating layer 111 and covered with the insulating layer 112. The connection wiring CB is disposed on the insulating layer 112, covered with the insulating layer 113, and intersects the connection wiring CA.

[0082] The insulating layer 114 included in the organic insulating layer IL is disposed on the insulating layer 113, and the insulating layer 12 is disposed on the insulating layer 114. In one example, the insulating layer 12 is thicker than the insulating layer 114. The insulating layer 12 is formed so as to have a stepped cross-section. The insulating layer 12 having such a stepped cross-section is formed by adjusting the partial exposure amount. Further, the insulating layer 12 recedes from the insulating layer 114. The slopes of the insulating layer 114 and the insulating layer 12 overlap the opening OPB. Thus, the organic insulating layer IL has a stepped cross-section in the region overlapping the opening OPB.

[0083] The protective layer PR faces the connection wiring CB via the insulating layer 113 in the third direction Z and overlaps the insulating layer 113 exposed from the organic insulating layer IL at the opening OPB. Although not shown, also in the overlapping portion of the connection wiring CA and the protective layer PR, the protective layer PR faces the connection wiring CA via the insulating layer 113 in the third direction Z and overlaps the insulating layer 113 exposed from the organic insulating layer IL at the opening OPB.

[0084] In the present embodiment, the protective layer PR includes a protective layer PR1 and a protective layer PR2 formed of a material different from that of the protective layer PR1. The protective layer PR2 is disposed on the protective layer PR1.

[0085] The protective layer PR1 is formed of a metal material such as molybdenum, tungsten, titanium, aluminum, etc. The protective layer PR1 is in contact with the insulating layer 113 and also in contact with the insulating layer 114. One end of the protective layer PR1 is located between the insulating layer 114 and the insulating layer 12, and the other end of the protective layer PR1 is located between the insulating layer 114 and the protective layer PR2.

[0086] The protective layer PR2 is formed of the same material as the above-described lower electrode LE. The protective layer PR2 is in contact with the insulating layer 113, the protective layer PR1, and the insulating layer 12 respectively. One end of the protective layer PR2 is located between the insulating layer 12 and the insulating layer 5, and the other end of the protective layer PR2 is located between the insulating layer 113 and the insulating layer 5.

[0087] The plurality of peripheral partition walls 7 are arranged on the insulating layer 5 in a region overlapping the organic insulating layer IL and a region not overlapping the organic insulating layer IL (opening OPA). Each of the peripheral partition walls 7 has a lower portion 71 arranged on the insulating layer 5 and an upper portion 72 arranged on the lower portion 71. Although not described in detail, the lower portion 71 is a multilayer body of a conductive layer formed of, for example, a titanium-based material and a conductive layer formed of, for example, an aluminum-based material, similar to the lower portion 61. The upper portion 72 is a multilayer body of a thin film formed of, for example, a titanium-based material and a thin film formed of, for example, an oxide conductive material, similar to the upper portion 62. The upper portion 72 has a larger width than the lower portion 71. Both ends of the upper portion 72 protrude beyond the side surfaces of the lower portion 71.

[0088] Thus, the peripheral partition wall 7 has the same overhanging shape as the partition wall 6 shown in FIG. 3. The peripheral partition wall 7 can be formed in the same process as the partition wall 6. In this case, the lower portion 71 and the lower portion 61 are formed of the same material in the same process, and the upper portion 72 and the upper portion 62 are formed of the same material in the same process.

[0089] Next, a method for manufacturing the display device DSP will be described.

[0090] First, as shown in FIG. 8, a part of the circuit layer is formed on the substrate 10. That is, after forming the insulating layer 111 on the substrate 10, a semiconductor connection wiring CA (not shown here) is formed on the insulating layer 111. Then, an insulating layer 112 is formed on the connection wiring CA and the insulating layer 111, and after forming the connection wiring CB made of a metal material on the insulating layer 112, an insulating layer 113 is formed on the connection wiring CB and the insulating layer 112.

[0091] Subsequently, an organic insulating layer IL and a protective layer PR are formed.

[0092] First, as shown in FIG. 9, an insulating layer 114, which is a part of the organic insulating layer IL, is formed on the insulating layer 113. By patterning the insulating layer 114, an edge E13 is formed. At this time, as shown in FIG. 6, the edge E13 is formed to have a zigzag shape.

[0093] Then, as shown in FIG. 10, as a part of the protective layer PR, a protective layer PR1 that intersects the edge E13 directly above the connection wiring CB is formed. The protective layer PR1 is in contact with the insulating layer 113 and extends over the insulating layer 114. Such a protective layer PR1 is formed by forming a metal layer on the insulating layer 113 and the insulating layer 114 and patterning this metal layer. The metal layer for forming the protective layer PR1 is, for example, a multilayer body in which a molybdenum-based metal layer is positioned between a pair of titanium-based metal layers.

[0094] Then, as shown in FIG. 11, an insulating layer 12, which is a part of the organic insulating layer IL, is formed. When patterning the insulating layer 12, by adjusting the exposure amount, a stepped cross-section is formed. In the vicinity of the edge E12, one end of the protective layer PR1 is covered. The edge E12 is recessed more than the edge E13. The opening OPA of the organic insulating layer IL is defined by the edge E13.

[0095] Then, as shown in FIG. 12, as part of the protective layer PR, a protective layer PR2 that intersects the edges E12 and E13 directly above the connection wiring CB is formed. The protective layer PR2 is in contact with the insulating layer 113, overlaps the protective layer PR1, and extends over the insulating layer 12. Such a protective layer PR2 is formed by forming a conductive layer for forming the lower electrode over the insulating layer 113 and the organic insulating layer IL, and patterning this conductive layer, thereby forming it simultaneously with the lower electrode. The conductive layer for forming the lower electrode is, for example, a multilayer body in which a silver-based reflective layer is located between a pair of transparent layers (ITO layers).

[0096] In this way, the organic insulating layer IL and the protective layer PR are formed through the steps described with reference to FIGS. 9 to 12.

[0097] Subsequently, as shown in FIG. 13, an insulating layer 5 is formed so as to cover the organic insulating layer IL and the protective layer PR. Thereafter, a peripheral partition wall 7 having a lower portion 71 located above the insulating layer 5 and an upper portion 72 located above the lower portion 71 and protruding from the side surface of the lower portion 71 is formed.

[0098] Subsequently, as shown in FIG. 14, the insulating layer 5 is patterned to form an opening OPB that overlaps the edges E12 and E13. As a result, edges E11 and E31 that define the opening OPB are formed. At this time, the edge E31 is formed to have a zigzag shape as shown in FIG. 6.

[0099] Such insulating layers 111, 112, 113, 114, 12, and 5 are also formed in the panel portion.

[0100] Next, a method for manufacturing a display element in the panel portion will be described. Note that illustrations below the insulating layer 12 are omitted in the respective figures for explaining the following manufacturing method.

[0101] As shown in FIG. 15, the lower electrode LE1 of the sub-pixel SP1, the lower electrode LE2 of the sub-pixel SP2, and the lower electrode LE3 of the sub-pixel SP3 are formed simultaneously with the protective layer PR2 as described above. The partition wall 6 is formed simultaneously with the peripheral partition wall 7 and has a lower portion 61 located on the insulating layer 5 and an upper portion 62 located on the lower portion 61 and protruding from the side surface of the lower portion 61. That is, the lower portion 61 of the partition wall 6 is formed simultaneously with the lower portion 71 of the peripheral partition wall 7, and the upper portion 62 is formed simultaneously with the upper portion 72. The openings AP1, AP2, and AP3 in the insulating layer 5 are formed simultaneously with the opening OPB.

[0102] Note that the step of forming the openings AP1, AP2, AP3, and OPB in the insulating layer 5 may be performed before forming the partition wall 6 and the peripheral partition wall 7, or may be performed after forming the partition wall 6 and the peripheral partition wall 7.

[0103] Subsequently, the display element DE1 is formed.

[0104] First, as shown in FIG. 16, a stacked film FL1 including an organic layer OR1, an upper electrode UE1, and a cap layer CP1 is formed. The step of forming the stacked film FL1 includes a step of forming an organic layer OR1 in contact with the lower electrode LE1 at the opening AP1, a step of forming an upper electrode UE1 covering the organic layer OR1 and in contact with the lower portion 61 of the partition wall 6, and a step of forming a cap layer CP1 located on the upper electrode UE1. Further, the step of forming the organic layer OR1 includes steps of forming a hole injection layer, a hole transport layer, an electron blocking layer, a light emitting layer, a hole blocking layer, an electron transport layer, an electron injection layer, etc. respectively. The organic layer OR1, the upper electrode UE1, and the cap layer CP1 are each formed by evaporation using the partition wall 6 as a mask. That is, on the lower electrode LE1, an organic layer OR1 including a light emitting layer EM1, an upper electrode UE1, and a cap layer CP1 are sequentially formed to form the stacked film FL1. The stacked film FL1 is divided into a plurality of portions by the overhanging partition wall 6. These organic layer OR1, upper electrode UE1, and cap layer CP1 are continuously formed while maintaining a vacuum environment.

[0105] Thereafter, a sealing layer SE1 is formed on the stacked film FL1 by depositing an inorganic insulating material. The sealing layer SE1 is formed by CVD (Chemical Vapor Deposition). The sealing layer SE1 continuously covers each divided portion of the stacked film FL1 and the partition wall 6.

[0106] Subsequently, as shown in FIG. 17, a resist RS patterned into a predetermined shape is formed on the sealing layer SE1. The resist RS overlaps with the sub-pixel SP1 and a part of the surrounding partition wall 6.

[0107] Subsequently, as shown in FIG. 18, etching is performed using the resist RS as a mask, and the sealing layer SE1 and the stacked film FL1 exposed from the resist RS are sequentially removed. In this etching, after removing the sealing layer SE1 exposed from the resist RS, the cap layer CP1 exposed from the sealing layer SE1 is removed, and further, after removing the upper electrode UE1 exposed from the cap layer CP1, the organic layer OR1 exposed from the upper electrode UE1 is removed. As a result, the lower electrode LE2 of the sub-pixel SP2 and the lower electrode LE3 of the sub-pixel SP3 are exposed. Thereafter, the resist RS is removed. As a result, a display element DE1 is formed in the sub-pixel SP1.

[0108] Subsequently, as shown in FIG. 19, a display element DE2 is formed. The procedure for forming the display element DE2 is the same as the procedure for forming the display element DE1. That is, an organic layer OR2 including a light-emitting layer EM2, an upper electrode UE2, and a cap layer CP2 are sequentially formed on the lower electrode LE2 to form a stacked film FL2. Thereafter, a sealing layer SE2 is formed on the stacked film FL2. Thereafter, a resist is formed on the sealing layer SE2, and the sealing layer SE2, the cap layer CP2, the upper electrode UE2, and the organic layer OR2 are patterned by etching using this resist as a mask. After this patterning, the resist is removed. As a result, a display element DE2 is formed in the sub-pixel SP2, and the lower electrode LE3 of the sub-pixel SP3 is exposed.

[0109] Subsequently, as shown in FIG. 20, a display element DE3 is formed. The procedure for forming the display element DE3 is the same as that for forming the display element DE1. That is, an organic layer OR3 including a light-emitting layer EM3, an upper electrode UE3, and a cap layer CP3 are sequentially formed on the lower electrode LE3 to form a stacked film FL3. Thereafter, a sealing layer SE3 is formed on the stacked film FL3. Thereafter, a resist is formed on the sealing layer SE3, and the sealing layer SE3, the cap layer CP3, the upper electrode UE3, and the organic layer OR3 are patterned by etching using this resist as a mask. After this patterning, the resist is removed. Thereby, the display element DE3 is formed in the sub-pixel SP3.

[0110] Thereafter, the resin layer 13, the sealing layer 14, and the resin layer 15 shown in FIG. 3 are sequentially formed. Then, the mother substrate 100 is cut along the cut line CL, and the display device DSP is completed. When the mother substrate 100 is cut along the cut line CL, the region from the cut line CL to the inspection terminal TT side in the region 100A shown in FIG. 6 remains in the display device DSP. Also, when the mother substrate 100 is cut along the cut line CL, the region on the left side of the figure from the cut line CL in the cross-sectional view shown in FIG. 7 remains in the display device DSP.

[0111] In the above manufacturing process, it is assumed that the display element DE1 is formed first, then the display element DE2 is formed, and finally the display element DE3 is formed. However, the formation order of the display elements DE1, DE2, and DE3 is not limited to this example.

[0112] As described above, since the insulating layer 5 has the opening OPB overlapping the edge of the organic insulating layer IL, the concentration of local stress in the vicinity of the edge E13 can be suppressed. Thereby, the lifting of the insulating layer 5 from the organic insulating layer IL can be suppressed.

[0113] In addition, when the stacked film FL1 is formed, the stacked film FL1 is partially divided by the overhanging peripheral partition wall 7. Compared with the case where the stacked film FL1 is not divided by the peripheral partition wall 7, the area of the continuous stacked film FL1 is reduced, and the stress that can occur in the stacked film FL1 is dispersed. Further, the insulating layer 5 and the stacked film FL1 are suppressed by the peripheral partition wall 7 and the sealing layer SE1. Therefore, it is possible to suppress the lifting of the stacked film FL1 from the insulating layer 5.

[0114] Further, when the organic insulating layer IL has a stepped cross-section whose thickness decreases toward the opening OPA, the formation of a steep step is suppressed. The smaller the thickness of the organic insulating layer IL, the smaller the elongation. Therefore, when the stacked film FL1 is formed on the organic insulating layer IL, the strain of the stacked film FL1 is small, and local stress concentration in the stacked film FL1 can be suppressed. Thereby, when the stacked film FL1 is formed near the opening OPB, it is possible to suppress the lifting of the stacked film FL1 from the insulating layer 5 and the organic insulating layer IL.

[0115] Here, problems that may occur when the stacked film FL1 and the insulating layer 5 lift off from the substrate and break will be described. The insulating layer 5 and the stacked film FL1 detached from the substrate float in the manufacturing apparatus as foreign matter and can become a source of contamination. Further, when the floating foreign matter adheres to the processing substrate, it may cause various defects.

[0116] On the other hand, according to the present embodiment, it is possible to suppress the detachment of the insulating layer 5 and the stacked film FL1. Thereby, contamination of the manufacturing apparatus and generation of undesired foreign matter are suppressed. Therefore, a decrease in reliability is suppressed.

[0117] Note that the same effect can be obtained even when the stacked film FL1 is replaced with the display element DE2 in the stacked film FL2, or when the stacked film FL1 is replaced with the stacked film FL3 for forming the display element DE3.

[0118] By the way, in a region where the organic insulating layer IL does not exist, insulating layers 111, 112, and 113, which are inorganic insulating layers of the same type as the insulating layer 5, are located directly below the insulating layer 5. Therefore, when dry etching is performed to form the opening OPB in the insulating layer 5, the insulating layers 111, 112, and 113 may also be removed.

[0119] FIG. 21 is a cross-sectional view for explaining the problems of the comparative example.

[0120] In the illustrated comparative example, the protective layer PR is not provided directly above the connection wiring CB. In this case, in a region where the organic insulating layer IL does not exist directly below the insulating layer 5, when the opening OPB is formed in the insulating layer 5, there is a possibility that an opening OPC that penetrates the insulating layers 111, 112, and 113 is formed, and moreover, the connection wiring CB may also be penetrated.

[0121] When such a problem occurs, it causes a disconnection of the connection wiring CB. For this reason, conduction between the TEG terminal TG and the inspection terminal TT cannot be ensured, which causes problems in the subsequent inspection process. Also, although not shown, the connection wiring CA also causes a disconnection in the same manner as the connection wiring CB. For this reason, in the manufacturing process, the function of the connection wiring CA as a shorting ring is impaired. Furthermore, the connection wiring CA and the connection wiring CB are exposed at the opening OPC. Therefore, when a conductive material remains at the opening OPC in a subsequent process, an undesired short circuit occurs between the connection wiring CA and the connection wiring CB.

[0122] According to the present embodiment, as shown in FIGS. 6 and 7, the protective layer PR overlaps the connection wiring CA and the connection wiring CB, respectively, and covers the insulating layer 113 located directly above these connection wirings. Therefore, when the opening OPB is formed in the insulating layer 5, the insulating layer 113 located directly above the connection wiring is protected, and the formation of an undesired opening OPC is suppressed. Thereby, disconnection of the connection wiring and exposure of the connection wiring from the insulating layer 113 are suppressed. Therefore, a decrease in reliability can be suppressed.

[0123] In addition, the protective layers PR1 and PR2 are made of materials different from the inorganic insulating material, such as semiconductor or metal materials. Therefore, in the dry etching process for processing the insulating layer 5, the protective layer PR functions as an etching stopper. Further, the protective layer PR2 is made of a material different from the protective layer PR1, for example, the material for forming the lower electrode, and covers the protective layer PR1. Therefore, when patterning the lower electrode, the protective layer PR1 is protected by the protective layer PR2.

[0124] Also, in plan view, the connection wirings CA and CB in the region not overlapping with the organic insulating layer IL are bent so as to bypass the peripheral partition wall 7 as shown in FIG. 6. Therefore, even if the connection wiring is exposed, it does not overlap with the peripheral partition wall 7, and an undesired short circuit through the peripheral partition wall 7 can be suppressed.

[0125] Next, the effects of the edge portions E13 and E31 having a zigzag shape will be described.

[0126] FIG. 22 is a diagram for explaining one of the effects of the present embodiment. As shown on the left side of the figure, between the connection wiring CA and the connection wiring CB, the edge portions E13 and E31 have a zigzag shape. As shown on the right side of the figure, in a subsequent manufacturing process, when the conductive material RC remains along the edge portion E13, the conductive material RC is divided by the taper portion TP2. Also, when the conductive material RC remains along the edge portion E31, the conductive material RC is divided by the taper portion TP1. Therefore, as described with reference to FIG. 21, even if the connection wirings CA and CB are exposed from the opening OPC, an undesired short circuit through the conductive material RC can be suppressed.

[0127] FIG. 23 is a cross-sectional view for explaining the problem of the comparative example. As shown on the left side of the figure, between the connection wiring CA and the connection wiring CB, the edge portions E13 and E31 are formed in a straight line. As shown on the right side of the figure, if conductive material RC remains along edge E13 and edge E31 in subsequent manufacturing processes, the conductive material RC is continuously formed between connection wiring CA and connection wiring CB. For this reason, as described with reference to FIG. 21, when connection wiring CA and connection wiring CB are exposed from opening OPC, a short circuit between connection wiring CA and connection wiring CB is caused via the conductive material RC.

[0128] Next, a configuration example of another display device DSP will be described.

[0129] FIG. 24 is a diagram showing another configuration example of the display device DSP.

[0130] The configuration example shown in FIG. 24 is different from the configuration example shown in FIG. 1 in that the display area DA is formed as a substantially circular area and the outer shape of the substrate 10 is generally formed in an arc shape. The configuration of the display area DA is as described with reference to FIGS. 1 to 3.

[0131] The peripheral area SA includes a plurality of mounting terminals MT. In the illustrated example, the substrate 10 has a linear substrate edge 10E, and the plurality of mounting terminals MT are arranged along the substrate edge 10E and are arranged side by side in the first direction X. In the illustrated example, the inspection terminal TT shown in FIG. 1 is not provided in the peripheral area SA.

[0132] The mounting terminal MT is a terminal that is electrically connected to a signal source such as a flexible printed circuit board or an IC chip, and is electrically connected to various wirings (scanning lines, signal lines, power lines, touch sensor wirings, etc.) in the display area DA. Further, the mounting terminal MT is connected to a wiring LN that extends toward the substrate edge 10E.

[0133] Next, a mother substrate 100 for collectively manufacturing a plurality of display devices DSP shown in FIG. 24 will be described.

[0134] FIG. 25 is a plan view showing a configuration example of the mother substrate 100.

[0135] The mother substrate 100 includes, on a large substrate 10, a plurality of panel portions PP and a margin portion MP outside these panel portions PP. The large substrate 10 is formed, for example, in a rectangular shape. In the illustrated example, two panel portions PP are shown as the plurality of panel portions PP, but more panel portions may be arranged in a matrix in the first direction X and the second direction Y.

[0136] The one-dot chain line in the figure is the primary cut line CL1, and the two-dot chain line in the figure is the final cut line CL2. Each of the panel portions PP is taken out by cutting the mother substrate 100 along the final cut line CL2 after cutting along the primary cut line CL1. Each of the taken-out panel portions PP corresponds to the display panel PNL shown in FIG. 24.

[0137] The margin portion MP includes inspection terminals TT and TEG terminals TG. The inspection terminals TT are located between the primary cut line CL1 and the final cut line CL2. The TEG terminals TG are located outside the primary cut line CL1.

[0138] The connection wiring CA is arranged in the margin portion MP and electrically connects adjacent inspection terminals TT. The connection wiring CB is arranged in the margin portion MP and electrically connects the TEG terminals TG and the inspection terminals TT. The connection wiring CN is arranged across the panel portion PP and the margin portion MP and electrically connects the inspection terminals TT and the mounting terminals MT.

[0139] FIG. 26 is a plan view showing the substrate 10 after the mother substrate 100 is cut along the primary cut line CL1.

[0140] When the mother substrate 100 is cut along the primary cut line CL1, the substrate 10 is formed in a rectangular shape, and a part of the connection wiring CA remains on the substrate 10 as the wiring LA, and a part of the connection wiring CB remains on the substrate 10 as the wiring LB.

[0141] After that, when the mother substrate 100 is severed along the final cut line CL2, a part of the connection wiring CN remains on the display panel PNL as the wiring LN shown in FIG. 24.

[0142] When the vicinity of the intersection between the connection wiring CN and the final cut line CL2 is enlarged, as in the example shown in FIG. 6, each of the protective layers PR intersects with the edges E11, E12, E13, E31, E32, E23, E22, E21 respectively and overlaps the connection wiring CN. Also, between adjacent connection wirings CN, the edges E13, E31, E23, E32 are bent so as to have a zigzag shape. Therefore, the same effects as those of the above-described configuration example can be obtained.

[0143] In the above embodiment, for example, a part of the wiring LA or the connection wiring CA, a part of the wiring LB or the connection wiring CB, and a part of the wiring LN or the connection wiring CN correspond to a plurality of wirings. Also, a part of the wiring LA or the connection wiring CA corresponds to the first wiring, and a part of the wiring LB or the connection wiring CB corresponds to the second wiring. The insulating layer 113 corresponds to the first inorganic insulating layer, and the insulating layer 5 corresponds to the second inorganic insulating layer. The insulating layer 114 corresponds to the first layer of the organic insulating layer IL, and the insulating layer 12 corresponds to the second layer of the organic insulating layer IL. In the protective layer PR, the protective layer PR1 corresponds to the first protective layer, and the protective layer PR2 corresponds to the second protective layer. In the peripheral partition 7, the lower part 71 corresponds to the first lower part, and the upper part 72 corresponds to the first upper part. In the partition 6, the lower part 61 corresponds to the second lower part, and the upper part 62 corresponds to the second upper part.

[0144] As described above, according to the present embodiment, it is possible to provide a display device and a method for manufacturing the same that can suppress a decrease in reliability.

[0145] Based on the display device and the method for manufacturing the same described as embodiments of the present invention above, all display devices and the methods for manufacturing the same that can be appropriately designed and modified by those skilled in the art also belong to the scope of the present invention as long as they include the gist of the present invention.

[0146] Within the scope of the idea of the present invention, those skilled in the art can conceive of various modifications, and those modifications are also understood to belong to the scope of the present invention. For example, for the above-described embodiments, those obtained by appropriately adding, deleting, or changing the design of components by those skilled in the art, or those obtained by adding, omitting, or changing conditions of processes, are also included in the scope of the present invention as long as they have the gist of the present invention.

[0147] In addition, regarding other operational effects brought about by the aspects described in the above-described embodiments, those that are obvious from the description of this specification or that can be appropriately conceived by those skilled in the art are naturally understood to be brought about by the present invention.

Explanation of Reference Numerals

[0148] DSP... Display device 10... Substrate 5... Inorganic insulating layer AP1, AP2, AP3... Opening OPB... Opening 6... Partition wall 61... Lower part 62... Upper part 7... Peripheral partition wall 71... Lower part 72... Upper part DE1, DE2, DE3... Display element (organic EL element) LE1, LE2, LE3... Lower electrode UE1, UE2, UE3... Upper electrode OR1, OR2, OR3... Organic layer DA... Display area SA... Peripheral area 100... Mother substrate PP... Panel part MP... Margin part CL... Cut line CL1... Primary cut line CL2... Final cut line IL... Organic insulating layer 12... Insulating layer 114... Insulating layer OPA... Opening

Claims

1. a substrate, a first inorganic insulating layer disposed above the substrate and extending across a display area for displaying an image and a peripheral area outside the display area; an organic insulating layer disposed on the first inorganic insulating layer; a lower electrode disposed on the organic insulating layer in the display area; an organic layer disposed on the lower electrode and including a light-emitting layer; an upper electrode disposed on the organic layer; a second inorganic insulating layer disposed on the organic insulating layer and having an opening exposing an edge of the organic insulating layer in the peripheral area; a plurality of wirings disposed between the substrate and the first inorganic insulating layer and intersecting the edge in plan view; a plurality of protective layers intersecting the edge in plan view, and comprising: one of the protective layers faces one of the wirings and overlaps the first inorganic insulating layer exposed from the organic insulating layer in the opening; a display device.

2. further comprising mounting terminals disposed in the peripheral area and electrically connected to a signal source; inspection terminals electrically connected to the mounting terminals; at least one of the wirings is connected to the inspection terminals; The display device according to claim 1.

3. The plurality of wirings include a first wiring formed of a semiconductor and a second wiring formed of a metal material; The display device according to claim 2.

4. The first wiring and the second wiring are connected to the same inspection terminal; in plan view, the edges of the organic insulating layer and the second inorganic insulating layer face each other and have a zigzag shape between the first wiring and the second wiring; The display device according to claim 3.

5. The protective layer is formed of a metal material, and includes a first protective layer in contact with the first inorganic insulating layer and a second protective layer formed of the same material as the lower electrode and disposed on the first protective layer. The display device according to claim 1.

6. The organic insulating layer includes a first layer disposed on the first inorganic insulating layer and a second layer disposed on the first layer. One end of the first protective layer is located between the first layer and the second layer, and the other end is located between the first inorganic insulating layer and the second protective layer. One end of the second protective layer is located between the second layer and the second inorganic insulating layer, and the other end is located between the first inorganic insulating layer and the second inorganic insulating layer. The display device according to claim 5.

7. The organic insulating layer has a stepped cross section with a reduced thickness in a region overlapping the opening. The display device according to claim 1.

8. Further, a plurality of peripheral partition walls disposed in the peripheral region are provided. Each of the plurality of peripheral partition walls has a first lower portion disposed on the second inorganic insulating layer and a first upper portion disposed on the first lower portion and protruding from a side surface of the first lower portion. In a plan view, the wiring in a region not overlapping the organic insulating layer is bent so as to bypass the peripheral partition wall. The display device according to claim 1.

9. Further, in the display region, a partition wall having a second lower portion disposed on the second inorganic insulating layer and formed of a conductive material and a second upper portion disposed on the second lower portion and protruding from a side surface of the second lower portion is provided. The second lower portion is formed of the same material as the first lower portion. The second upper part is formed of the same material as the second upper part, The lower electrode, the organic layer, and the upper electrode are surrounded by the partition wall, The upper electrode is in contact with the second lower part of the partition wall, The display device according to claim 8.

10. Furthermore, a cap layer disposed on the upper electrode and surrounded by the partition wall, A sealing layer formed of an inorganic insulating material and disposed on the cap layer, An end portion of the sealing layer is located on the partition wall, The display device according to claim 9.

11. Form wiring above the substrate, Form a first inorganic insulating layer on the wiring, Form an organic insulating layer on the first inorganic insulating layer, Form a lower electrode on the organic insulating layer, Form a protective layer that faces the wiring and overlaps the first inorganic insulating layer exposed from the organic insulating layer, Form a second inorganic insulating layer that covers the organic insulating layer and the protective layer, In the second inorganic insulating layer, form an opening that overlaps an edge portion of the organic insulating layer, Form an organic layer on the lower electrode, Form an upper electrode on the organic layer, A method for manufacturing a display device.

12. The wiring is formed of a semiconductor or metal material, The method for manufacturing a display device according to claim 11.

13. When forming the organic insulating layer, form the edge portion of the organic insulating layer to have a zigzag shape, When forming the opening in the second inorganic insulating layer, form the edge portion of the second inorganic insulating layer facing the edge portion of the organic insulating layer to have a zigzag shape, The method for manufacturing a display device according to claim 11.

14. The step of forming the organic insulating layer is a step of forming a first layer on the first inorganic insulating layer, and a step of forming a second layer on the first layer, The step of forming the protective layer is before forming the second layer, forming a first protective layer in contact with the first inorganic insulating layer and extending on the first layer, after forming the second layer, forming a second protective layer overlapping the first protective layer and extending on the second layer, A method for manufacturing a display device according to claim 11.

15. The first protective layer is formed of a metal material, The second protective layer is formed of the same material as the lower electrode. A method for manufacturing a display device according to claim 14.

16. Further, forming a peripheral partition wall having a first lower portion located on the second inorganic insulating layer and a first upper portion located on the first lower portion and protruding from a side surface of the first lower portion, forming a partition wall having a second lower portion located on the second inorganic insulating layer and a second upper portion located on the second lower portion and protruding from a side surface of the second lower portion, The first lower portion and the second lower portion are formed of the same material in the same process, The first upper portion and the second upper portion are formed of the same material in the same process. A method for manufacturing a display device according to claim 11.

17. Further, forming a cap layer on the upper electrode, The organic layer, the upper electrode, and the cap layer are formed by evaporation using the partition wall as a mask. A method for manufacturing a display device according to claim 16.

18. Further, forming a sealing layer of an inorganic insulating material on the cap layer, A resist patterned into a predetermined shape is formed on the encapsulation layer, etching is performed using the resist as a mask to remove the encapsulation layer, the cap layer, the upper electrode, and the organic layer that are exposed from the resist, The method for manufacturing a display device according to claim 17.

Images