Method for manufacturing semiconductor device

Abstract

To suppress characteristic degradation of a transistor in a driver circuit.SOLUTION: A semiconductor device comprises: a first switch for controlling whether to set a potential state of an output signal or not by turning it on or off according to a first input signal; and a second switch for controlling whether to set the potential state of the output signal by turning it on or off according to a second input signal. The turning on or off of the first switch or the second switch brings first wiring and second wiring into a conductive state or a non-conductive state.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Relates to a semiconductor device, a display device, a liquid crystal display device, a driving method thereof, or a method for producing them. In particular, it relates to a semiconductor device, a display device, a liquid crystal display device having a driving circuit formed on the same substrate as the pixel portion, or a driving method thereof. Or, it relates to an electronic device having the semiconductor device, the display device, or the liquid crystal display device.

Background Art

[0002] In recent years, display devices have been actively developed due to the increase in large display devices such as liquid crystal televisions. In particular, a technique for forming a driving circuit such as a gate driver on the same substrate as the pixel portion using a transistor composed of a non-single crystal semiconductor greatly contributes to cost reduction and reliability improvement, and thus is actively developed. A transistor composed of a non-single crystal semiconductor causes deterioration such as fluctuations in threshold voltage or a decrease in mobility. As this transistor deteriorates, it becomes difficult for the driving circuit to operate, and there is a problem that an image cannot be displayed. Therefore, Patent Document 1, Patent Document 2, and Non-Patent Document 1 disclose a shift register capable of suppressing the deterioration of a transistor (hereinafter also referred to as a pull-down transistor) having a function of lowering the output signal of a flip-flop to the L level (also referred to as a low level). In these documents, two pull-down transistors are used. These two pull-down transistors are connected between the output terminal of the flip-flop and the wiring to which VSS (hereinafter referred to as a negative power supply) is supplied. Then, one pull-down transistor and the other pull-down transistor are alternately turned on (on state

[0003] is also referred to as an on state) (also referred to as) becomes. By doing so, the time for each pull-down transistor to turn on becomes shorter, so that deterioration of the characteristics of the pull-down transistor can be suppressed.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Non-Patent Documents

[0005]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] In the configuration of the conventional technology, the potential of the gate of the transistor (hereinafter also referred to as the pull-up transistor) for controlling the output signal to a high level may be higher than the positive power supply voltage or the high-level potential of the clock signal . For this reason, a large voltage may be applied to the pull-up transistor . Or, a large voltage may be applied to the transistor connected to the gate of the pull-up transistor . Or, the transistor may be inferior Even when converted, the channel width of the transistors constituting the shift register may be large so that the shift register operates. Or, when the channel width of the transistor is large, there is a possibility that the transistor may be easily short-circuited between the gate and the source or drain. Or, when the channel width of the transistor increases, the parasitic capacitance of each transistor constituting the shift register may increase. Or, when the channel width of the transistor is large, the transistor may be easily short-circuited between the gate and the source or drain. Or, when the channel width of the transistor increases, the parasitic capacitance of each transistor constituting the shift register may increase. when the channel width of the transistor increases, the parasitic capacitance of each transistor constituting the shift register may increase. when the channel width of the transistor increases, the parasitic capacitance of each transistor constituting the shift register may increase.

[0007] One aspect of the present invention is to suppress deterioration of transistor characteristics. Or, one aspect of the present invention is to reduce the channel width of the transistor. Or, one aspect of the present invention is to suppress deterioration of the characteristics of the pull-up transistor or reduce the channel width. Or, one aspect of the present invention is to increase the amplitude of the output signal. Or, one aspect of the present invention is to increase the on-time of the transistor included in the pixel. Or, one aspect of the present invention is to improve insufficient writing to the pixel. Or, one aspect of the present invention is to reduce the channel width of the transistor. Or, one aspect of the present invention is to suppress deterioration of the characteristics of the pull-up transistor or reduce the channel width. Or, one aspect of the present invention is to increase the amplitude of the output signal. Or, one aspect of the present invention is to increase the on-time of the transistor included in the pixel. Or, one aspect of the present invention is to improve insufficient writing to the pixel. Or, one aspect of the present invention is to suppress deterioration of the characteristics of the pull-up transistor or reduce the channel width. Or, one aspect of the present invention is to increase the amplitude of the output signal. Or, one aspect of the present invention is to increase the on-time of the transistor included in the pixel. Or, one aspect of the present invention is to improve insufficient writing to the pixel. Or, one aspect of the present invention is to increase the amplitude of the output signal. Or, one aspect of the present invention is to increase the on-time of the transistor included in the pixel. Or, one aspect of the present invention is to improve insufficient writing to the pixel. Or, one aspect of the present invention is to increase the on-time of the transistor included in the pixel. Or, one aspect of the present invention is to improve insufficient writing to the pixel. Or, one aspect of the present invention is to improve insufficient writing to the pixel. Or, one aspect of the present invention is to shorten the fall time of the output signal. Or, one aspect of the present invention is to shorten the rise time of the output signal. Or, one aspect of the present invention is to prevent a video signal from being written from a pixel belonging to one row to a pixel belonging to another row. Or, one aspect of the present invention is to reduce the fluctuation of the fall time of the output signal of the drive circuit. Or, one aspect of the present invention is to make the influence of the feed-through to each pixel constant. Or, one aspect of the present invention is to reduce crosstalk. Or, one aspect of the present invention is to reduce the layout area. Or, one aspect of the present invention is to narrow the frame of the display device. Or, one aspect of the present invention is to make the display device high-definition one aspect of the present invention is to prevent a video signal from being written from a pixel belonging to one row to a pixel belonging to another row. Or, one aspect of the present invention is to reduce the fluctuation of the fall time of the output signal of the drive circuit. Or, one aspect of the present invention is to make the influence of the feed-through to each pixel constant. Or, one aspect of the present invention is to reduce crosstalk. Or, one aspect of the present invention is to reduce the layout area. Or, one aspect of the present invention is to narrow the frame of the display device. Or, one aspect of the present invention is to make the display device high-definition one aspect of the present invention is to prevent a video signal from being written from a pixel belonging to one row to a pixel belonging to another row. Or, one aspect of the present invention is to reduce the fluctuation of the fall time of the output signal of the drive circuit. Or, one aspect of the present invention is to make the influence of the feed-through to each pixel constant. Or, one aspect of the present invention is to reduce crosstalk. Or, one aspect of the present invention is to reduce the layout area. Or, one aspect of the present invention is to narrow the frame of the display device. Or, one aspect of the present invention is to make the display device high-definition one aspect of the present invention is to reduce the fluctuation of the fall time of the output signal of the drive circuit. Or, one aspect of the present invention is to make the influence of the feed-through to each pixel constant. Or, one aspect of the present invention is to reduce crosstalk. Or, one aspect of the present invention is to reduce the layout area. Or, one aspect of the present invention is to narrow the frame of the display device. Or, one aspect of the present invention is to make the display device high-definition one aspect of the present invention is to make the influence of the feed-through to each pixel constant. Or, one aspect of the present invention is to reduce crosstalk. Or, one aspect of the present invention is to reduce the layout area. Or, one aspect of the present invention is to narrow the frame of the display device. Or, one aspect of the present invention is to make the display device high-definition one aspect of the present invention is to reduce crosstalk. Or, one aspect of the present invention is to reduce the layout area. Or, one aspect of the present invention is to narrow the frame of the display device. Or, one aspect of the present invention is to make the display device high-definition one aspect of the present invention is to reduce the layout area. Or, one aspect of the present invention is to narrow the frame of the display device. Or, one aspect of the present invention is to make the display device high-definition is to achieve this. Or, one aspect of the present invention aims to increase the yield. Or, one aspect of the present invention aims to reduce the manufacturing cost. Or, one aspect of the present invention aims to reduce the ringing of the output signal. Or, one aspect of the present invention aims to reduce the delay of the output signal. Or, one aspect of the present invention aims to reduce the power consumption. Or, one aspect of the present invention aims to reduce the current supply capacity of the external circuit. Or, one aspect of the present invention aims to reduce the size of the external circuit or the size of the display device having the external circuit. Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not necessarily need to solve all of these problems.

[0008] One aspect of the present invention includes a driving circuit that receives a first input signal, a second input signal, and a third input signal and outputs an output signal, and pixels having liquid crystal elements, wherein the voltage applied to the liquid crystal elements is set according to the output signal. The driving circuit includes a first switch and a second switch that turn on or off according to the third input signal, a third switch that controls whether the first input signal is input according to whether the first switch turns on or off and controls whether to set the potential state of the output signal according to the first input signal, and a fourth switch that controls whether the second input signal is input according

[0009] One aspect of the present invention has a driving circuit to which a first input signal, a second input signal, and a third input signal are input, a pixel having a liquid crystal element, and a voltage applied to the liquid crystal element according to the output signal is set, and the driving circuit has a gate, a source, and a drain, a first transistor to which the third input signal is input to the gate and the first input signal is input to one of the source and the drain, a second transistor having a gate, a source, and a drain, the third input signal being input to the gate and the second input signal being input to one of the source and the drain, a third transistor having a gate, a source, and a drain, the gate being electrically connected to the other of the source and the drain of the first transistor, and controlling whether to set the potential state of the output signal by turning on or off, a fourth transistor having a gate, a source, and a drain, the gate being electrically connected to the other of the source and the drain of the second transistor, and controlling whether to set the potential state of the output signal by turning on or off, and is a liquid crystal display device having the above. One aspect of the present invention has a driving circuit to which a first input signal, a second input signal, a third input signal, and a fourth input signal are input, a pixel having a liquid crystal element, and a voltage applied to the liquid crystal element according to the output signal is set, and the driving circuit has a first wiring to which the first input signal is input, a second wiring to which the second input signal is input, a third wiring to which the third input signal is input, a fourth wiring to which the fourth input signal is input, a gate, a source, and a drain, the gate being electrically connected to the third wiring, and one of the source and the drain

[0010] a first transistor electrically connected to a first wiring, a gate, a source, and a drain having a drain, the gate being electrically connected to a third wiring, and one of the source and the drain being electrically connected to a second wiring; a second transistor having a gate, a source, and a drain, the gate being electrically connected to the other of the source and the drain of the first transistor, and one of the source and the drain being electrically connected to a fourth wiring; a third transistor having a gate, a source, and a drain, the gate being electrically connected to the other of the source and the drain of the second transistor, and one of the source and the drain being electrically connected to the fourth wiring; a fourth transistor having a gate, a source, and a drain, the gate being electrically connected to the other of the source and the drain of the second transistor, and one of the source and the drain being electrically connected to the fourth wiring; and a fifth wiring electrically connected to the other of the source and the drain of the third transistor and the other of the source and the drain of the fourth transistor, the applied potential being the potential of the output signal, wherein the liquid crystal display device comprises: One aspect of the present invention is a driving circuit that receives a first input signal, a second input signal, a third input signal, and a fourth input signal and outputs an output signal, and a pixel having a liquid crystal element, wherein a voltage applied to the liquid crystal element is set according to the output signal. The driving circuit includes a first wiring to which the first input signal is input, a second wiring to which the second input signal is input, a third wiring to which the third input signal is input, a fourth wiring to which the fourth input signal is input, a first transistor having a gate, a source, and a drain, wherein the gate and one of the source and the drain are electrically connected to the first wiring, a second transistor having a gate, a source, and a drain, wherein the gate and one of the source and the drain are electrically connected to the second wiring, a gate

[0011] signal, and a pixel having a liquid crystal element, wherein a voltage applied to the liquid crystal element is set according to the output signal. The driving circuit includes a first wiring to which the first input signal is input, a second wiring to which the second input signal is input, a third wiring to which the third input signal is input, a fourth wiring to which the fourth input signal is input, a first transistor having a gate, a source, and a drain, wherein the gate and one of the source and the drain are electrically connected to the first wiring, a second transistor having a gate, a source, and a drain, wherein the gate and one of the source and the drain are electrically connected to the second wiring, a gate and a drain, and a third transistor having a gate, a source, and a drain, wherein the gate and one of the source and the drain are electrically connected to the third wiring, and a fourth transistor having a gate, a source, and a drain, wherein the gate and one of the source and the drain are electrically connected to the fourth wiring, wherein the driving circuit further includes a first transistor having a gate, a source, and a drain, wherein the gate and one of the source and the drain are electrically connected to the first wiring, a second transistor having a gate, a source, and a drain, wherein the gate and one of the source and the drain are electrically connected to the second wiring, a third transistor having a gate, a source, and a drain, wherein the gate and one of the source and the drain are electrically connected to the third wiring, a fourth transistor having a gate, a source, and a drain, wherein the gate and one of the source and the drain are electrically connected to the fourth wiring, a first wiring to which the first input signal is input, a second wiring to which the second input signal is input, a third wiring to which the third input signal is input, a fourth wiring to which the fourth input signal is input, a first transistor having a gate, a source, and a drain, wherein the gate and one of the source and the drain are electrically connected to the first wiring, a second transistor having a gate, a source, and a drain, wherein the gate and one of the source and the drain are electrically connected to the second wiring, a third transistor having a gate, a source, and a drain, wherein the gate and one of the source and the drain are electrically connected to the third wiring, a fourth transistor having a gate, a source, and a drain, wherein the gate and one of the source and the drain are electrically connected to the fourth wiring, a first transistor having a gate, a source, and a drain, wherein the gate and one of the source and the drain are electrically connected to the first wiring, a second transistor having a gate, a source, and a drain, wherein the gate and one of the source and the drain are electrically connected to the second wiring, a third transistor having a gate, a source, and a drain, wherein the gate and one of the source and the drain are electrically connected to the third wiring, a fourth transistor having a gate, a source, and a drain, wherein the gate and one of the source and the drain are electrically connected to the fourth wiring, a first transistor having a gate, a source, and a drain, wherein the gate and one of the source and the drain are electrically connected to the first wiring, a second transistor having a gate, a source, and a drain, wherein the gate and one of the source and the drain are electrically connected to the second wiring, a third transistor having a gate, a source, and a drain, wherein the gate and one of the source and the drain are electrically connected to the third wiring, a fourth transistor having a gate, a source, and a drain, wherein the gate and one of the source and the drain are electrically connected to the fourth wiring, a second transistor having a gate, a source, and a drain, wherein the gate and one of the source and the drain are electrically connected to the second wiring, a gate ​, having a source and a drain, and the gate is electrically connected to the other of the source and the drain of the first transistor A third transistor in which one of the source and the drain is electrically connected to a third wiring, and the gate is electrically connected to the other of the source and the drain of the first transistor A fourth transistor having a gate, a source, and a drain, the gate being electrically connected to the other of the source and the drain of the second transistor, and one of the source and the drain being electrically connected to a fourth wiring A fourth transistor having a gate, a source, and a drain, the gate being electrically connected to the other of the source and the drain of the second transistor, and one of the source and the drain being electrically connected to a fourth wiring A fourth transistor having a gate, a source, and a drain, the gate being electrically connected to the other of the source and the drain of the second transistor, and one of the source and the drain being electrically connected to a fourth wiring And a fifth wiring that is electrically connected to the other of the source and the drain of the third transistor and the other of the source and the drain of the fourth transistor, and the applied potential becomes the potential of the output signal. A liquid crystal display device having a fifth wiring that is electrically connected to the other of the source and the drain of the third transistor and the other of the source and the drain of the fourth transistor, and the applied potential becomes the potential of the output signal.

[0012] One aspect of the present invention is a drive circuit that receives a first input signal and a second input signal and outputs an output signal, and a pixel that has a liquid crystal element and has a voltage applied to the liquid crystal element set according to the output signal. A drive circuit that receives a first input signal and a second input signal and outputs an output signal, and a pixel that has a liquid crystal element and has a voltage applied to the liquid crystal element set according to the output signal. The drive circuit includes a first wiring to which a first input signal is input, a second wiring to which a second input signal is input, a first transistor having a gate, a source, and a drain, and the gate and one of the source and the drain are electrically connected to the first wiring. A second transistor having a gate, a source, and a drain, and the gate and one of the source and the drain are electrically connected to the second wiring. A second transistor having a gate, a source, and a drain, and the gate and one of the source and the drain are electrically connected to the second wiring. A third transistor having a gate, a source, and a drain, and the gate and one of the source and the drain are electrically connected to the other of the source and the drain of the first transistor. A third transistor having a gate, a source, and a drain, and the gate and one of the source and the drain are electrically connected to the other of the source and the drain of the first transistor. A fourth transistor having a gate, a source, and a drain, and the gate and one of the source and the drain are electrically connected to the other of the source and the drain of the second transistor. A fourth transistor having a gate, a source, and a drain, and the gate and one of the source and the drain are electrically connected to the other of the source and the drain of the second transistor. A fourth transistor having a gate, a source, and a drain, and the gate and one of the source and the drain are electrically connected to the other of the source and the drain of the second transistor. A fourth transistor having a gate, a source, and a drain, and the gate and one of the source and the drain are electrically connected to the other of the source and the drain of the second transistor. electrically connected to the other party and the other of the source and drain of the fourth transistor, and provided with a third wiring whose potential becomes the potential of the output signal, is a liquid crystal display device.

[0013] In addition, in one aspect of the present invention, the channel width of the third transistor can be made equal to the channel width of the fourth transistor.

[0014] Further, in one aspect of the present invention, the channel width of the first transistor can be made smaller than the channel width of the third transistor, and the channel width of the second transistor can be made smaller than the channel width of the fourth transistor.

[0015] One aspect of the present invention includes a drive circuit that receives a first input signal and a second input signal and outputs an output signal, and a pixel having a liquid crystal element, wherein a voltage applied to the liquid crystal element is set according to the output signal. The drive circuit includes a first wiring to which the first input signal is input, a second wiring to which the second input signal is input, a first transistor having a gate, a source, and a drain, wherein the gate and one of the source and the drain are electrically connected to the first wiring, and a second transistor having a gate, a source, and a drain, wherein the gate and one of the source and the drain are electrically connected to the second wiring. The drive circuit further includes a first diode having a positive electrode and a negative electrode, wherein the positive electrode is electrically connected to the other of the source and the drain of the first transistor, a second diode having a positive electrode and a negative electrode, wherein the positive electrode is electrically connected to the other of the source and the drain of the second transistor, and a third wiring electrically connected to the negative electrode of the first diode and the negative electrode of the second diode, and provided with a potential that becomes the potential of the output signal. is a liquid crystal display device.

[0016] In one aspect of the present invention, the channel width of the first transistor can be made equal to the channel width of the second transistor.

[0017] One aspect of the present invention is an electronic device including at least the liquid crystal display device described in any of the above and an operation switch that controls the operation of the liquid crystal display device.

[0018] Note that various forms of switches can be used. As an example of a switch, an electrical switch or a mechanical switch can be used. That is, the switch only needs to be able to control current and is not limited to a specific one.

[0019] As an example of a switch, a transistor (for example, a bipolar transistor, a MOS transistor, etc.), a diode (for example, a PN diode, a PIN diode, a Schottky diode, a MIM (Metal Insulator Metal) diode, a MIS (Metal Insulator Semiconductor) diode, a diode-connected transistor, etc.), or a logic circuit combining these can be used. As an example of a mechanical switch, there is a switch using MEMS (Micro Electro Mechanical System) technology such as a digital micromirror device (DMD). The switch has an electrode that can be mechanically moved, and by moving the electrode, conduction and non-conduction are controlled to operate.

[0020] Note that as the switch, both an N-channel transistor and a P-channel transistor can be used to form a CMOS-type switch. ​​​​​​​​​​​​​

[0021] Note that a display element, a display device having the display element, a light-emitting element, and a light-emitting device having the light-emitting element can use various forms or have various elements. As an example of a display element, a display device, a light-emitting element, or a light-emitting device, an EL (electroluminescence) element (an EL element including an organic substance and an inorganic substance, an organic EL element, an inorganic EL element), an LED (white LED, red LED, green LED, blue LED, etc.), a transistor (a transistor that emits light according to current), an electron-emitting element, a liquid crystal element, electronic ink, an electrophoretic element, a grating light valve (GLV), a digital micromirror device (DMD), a carbon nanotube, etc., and there are those having a display medium in which contrast, luminance, reflectance, transmittance, etc. change due to an electromagnetic action. Further, the display device can be a plasma display or a piezoelectric ceramic display. As an example of a display device using an EL element, there is an EL display, etc. As an example of a display device using an electron-emitting element, there is a field emission display (FED) or a surface-conduction electron-emitter display (SED) type flat display, etc. As an example of a display device using a liquid crystal element, there is a liquid crystal display (transmissive liquid crystal display, transflective liquid crystal display, reflective liquid crystal display, direct-view type liquid crystal display, projection type liquid crystal display), etc. As an example of a display device using electronic ink or an electrophoretic element, there is electronic paper, etc. As an example of a liquid crystal element, light transmission or non-transmission is controlled by the optical modulation action of liquid crystal. (Transmissive liquid crystal display, transflective liquid crystal display, reflective liquid crystal display, direct-view type liquid crystal display, projection type liquid crystal display), etc. As an example of a display device using electronic ink or an electrophoretic element, there is electronic paper, etc.

[0022] As an example of a liquid crystal element, light transmission or non-transmission is controlled by the optical modulation action of liquid crystal. There is an element. The element can be composed of a pair of electrodes and a liquid crystal layer. Note that the optical modulation effect of the liquid crystal is controlled by an electric field applied to the liquid crystal (including an electric field in the horizontal direction, vertical direction, or diagonal direction). Specifically, as an example of a liquid crystal element, nematic liquid crystal, cholesteric liquid crystal, smectic liquid crystal, discotic liquid crystal, thermotropic liquid crystal, lyotropic liquid crystal, low molecular weight liquid crystal, high molecular weight liquid crystal, polymer dispersed liquid crystal (PDLC), ferroelectric liquid crystal, antiferroelectric liquid crystal, main chain type liquid crystal, side chain type high molecular weight liquid crystal, plasma addressed liquid crystal (PALC), banana type liquid crystal, TN (Twisted Nematic) mode, STN (Super Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, MVA (Multi-domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment), ASV (Advanced Super View) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optical Compensated Birefringence) mode, ECB (Electrically Controlled Birefringence) mode including an electric field in the horizontal direction, vertical direction, or diagonal direction). Specifically, as an example of a liquid crystal element, nematic liquid crystal, cholesteric liquid crystal, smectic liquid crystal, discotic liquid crystal, thermotropic liquid crystal, lyotropic liquid crystal, low molecular weight liquid crystal, high molecular weight liquid crystal, polymer dispersed liquid crystal (PDLC), ferroelectric liquid crystal, antiferroelectric liquid crystal, main chain type liquid crystal, side chain type high molecular weight liquid crystal, plasma addressed liquid crystal (PALC), banana type liquid crystal, TN (Twisted Nematic) mode, STN (Super Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, MVA (Multi-domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment), ASV (Advanced Super View) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optical Compensated Birefringence) mode, ECB (Electrically Controlled Birefringence) mode nematic liquid crystal, cholesteric liquid crystal, smectic liquid crystal, discotic liquid crystal, thermotropic liquid crystal, lyotropic liquid crystal, low molecular weight liquid crystal, high molecular weight liquid crystal, polymer dispersed liquid crystal (PDLC), ferroelectric liquid crystal, antiferroelectric liquid crystal, main chain type liquid crystal, side chain type high molecular weight liquid crystal, plasma addressed liquid crystal (PALC), banana type liquid crystal, TN (Twisted Nematic) mode, STN (Super Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, MVA (Multi-domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment), ASV (Advanced Super View) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optical Compensated Birefringence) mode, ECB (Electrically Controlled Birefringence) mode nematic liquid crystal, cholesteric liquid crystal, smectic liquid crystal, discotic liquid crystal, thermotropic liquid crystal, lyotropic liquid crystal, low molecular weight liquid crystal, high molecular weight liquid crystal, polymer dispersed liquid crystal (PDLC), ferroelectric liquid crystal, antiferroelectric liquid crystal, main chain type liquid crystal, side chain type high molecular weight liquid crystal, plasma addressed liquid crystal (PALC), banana type liquid crystal, TN (Twisted Nematic) mode, STN (Super Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, MVA (Multi-domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment), ASV (Advanced Super View) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optical Compensated Birefringence) mode, ECB (Electrically Controlled Birefringence) mode nematic liquid crystal, cholesteric liquid crystal, smectic liquid crystal, discotic liquid crystal, thermotropic liquid crystal, lyotropic liquid crystal, low molecular weight liquid crystal, high molecular weight liquid crystal, polymer dispersed liquid crystal (PDLC), ferroelectric liquid crystal, antiferroelectric liquid crystal, main chain type liquid crystal, side chain type high molecular weight liquid crystal, plasma addressed liquid crystal (PALC), banana type liquid crystal, TN (Twisted Nematic) mode, STN (Super Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, MVA (Multi-domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment), ASV (Advanced Super View) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optical Compensated Birefringence) mode, ECB (Electrically Controlled Birefringence) mode nematic liquid crystal, cholesteric liquid crystal, smectic liquid crystal, discotic liquid crystal, thermotropic liquid crystal, lyotropic liquid crystal, low molecular weight liquid crystal, high molecular weight liquid crystal, polymer dispersed liquid crystal (PDLC), ferroelectric liquid crystal, antiferroelectric liquid crystal, main chain type liquid crystal, side chain type high molecular weight liquid crystal, plasma addressed liquid crystal (PALC), banana type liquid crystal, TN (Twisted Nematic) mode, STN (Super Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, MVA (Multi-domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment), ASV (Advanced Super View) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optical Compensated Birefringence) mode, ECB (Electrically Controlled Birefringence) mode nematic liquid crystal, cholesteric liquid crystal, smectic liquid crystal, discotic liquid crystal, thermotropic liquid crystal, lyotropic liquid crystal, low molecular weight liquid crystal, high molecular weight liquid crystal, polymer dispersed liquid crystal (PDLC), ferroelectric liquid crystal, antiferroelectric liquid crystal, main chain type liquid crystal, side chain type high molecular weight liquid crystal, plasma addressed liquid crystal (PALC), banana type liquid crystal, TN (Twisted Nematic) mode, STN (Super Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, MVA (Multi-domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment), ASV (Advanced Super View) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optical Compensated Birefringence) mode, ECB (Electrically Controlled Birefringence) mode nematic liquid crystal, cholesteric liquid crystal, smectic liquid crystal, discotic liquid crystal, thermotropic liquid crystal, lyotropic liquid crystal, low molecular weight liquid crystal, high molecular weight liquid crystal, polymer dispersed liquid crystal (PDLC), ferroelectric liquid crystal, antiferroelectric liquid crystal, main chain type liquid crystal, side chain type high molecular weight liquid crystal, plasma addressed liquid crystal (PALC), banana type liquid crystal, TN (Twisted Nematic) mode, STN (Super Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, MVA (Multi-domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment), ASV (Advanced Super View) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optical Compensated Birefringence) mode, ECB (Electrically Controlled Birefringence) mode nematic liquid crystal, cholesteric liquid crystal, smectic liquid crystal, discotic liquid crystal, thermotropic liquid crystal, lyotropic liquid crystal, low molecular weight liquid crystal, high molecular weight liquid crystal, polymer dispersed liquid crystal (PDLC), ferroelectric liquid crystal, antiferroelectric liquid crystal, main chain type liquid crystal, side chain type high molecular weight liquid crystal, plasma addressed liquid crystal (PALC), banana type liquid crystal, TN (Twisted Nematic) mode, STN (Super Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, MVA (Multi-domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment), ASV (Advanced Super View) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optical Compensated Birefringence) mode, ECB (Electrically Controlled Birefringence) mode nematic liquid crystal, cholesteric liquid crystal, smectic liquid crystal, discotic liquid crystal, thermotropic liquid crystal, lyotropic liquid crystal, low molecular weight liquid crystal, high molecular weight liquid crystal, polymer dispersed liquid crystal (PDLC), ferroelectric liquid crystal, antiferroelectric liquid crystal, main chain type liquid crystal, side chain type high molecular weight liquid crystal, plasma addressed liquid crystal (PALC), banana type liquid crystal, TN (Twisted Nematic) mode, STN (Super Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, MVA (Multi-domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment), ASV (Advanced Super View) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optical Compensated Birefringence) mode, ECB (Electrically Controlled Birefringence) mode nematic liquid crystal, cholesteric liquid crystal, smectic liquid crystal, discotic liquid crystal, thermotropic liquid crystal, lyotropic liquid crystal, low molecular weight liquid crystal, high molecular weight liquid crystal, polymer dispersed liquid crystal (PDLC), ferroelectric liquid crystal, antiferroelectric liquid crystal, main chain type liquid crystal, side chain type high molecular weight liquid crystal, plasma addressed liquid crystal (PALC), banana type liquid crystal, TN (Twisted Nematic) mode, STN (Super Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, MVA (Multi-domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment), ASV (Advanced Super View) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optical Compensated Birefringence) mode, ECB (Electrically Controlled Birefringence) mode nematic liquid crystal, cholesteric liquid crystal, smectic liquid crystal, discotic liquid crystal, thermotropic liquid crystal, lyotropic liquid crystal, low molecular weight liquid crystal, high molecular weight liquid crystal, polymer dispersed liquid crystal (PDLC), ferroelectric liquid crystal, antiferroelectric liquid crystal, main chain type liquid crystal, side chain type high molecular weight liquid crystal, plasma addressed liquid crystal (PALC), banana type liquid crystal, TN (Twisted Nematic) mode, STN (Super Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, MVA (Multi-domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment), ASV (Advanced Super View) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optical Compensated Birefringence) mode, ECB (Electrically Controlled Birefringence) mode nematic liquid crystal, cholesteric liquid crystal, smectic liquid crystal, discotic liquid crystal, thermotropic liquid crystal, lyotropic liquid crystal, low molecular weight liquid crystal, high molecular weight liquid crystal, polymer dispersed liquid crystal (PDLC), ferroelectric liquid crystal, antiferroelectric liquid crystal, main chain type liquid crystal, side chain type high molecular weight liquid crystal, plasma addressed liquid crystal (PALC), banana type liquid crystal, TN (Twisted Nematic) mode, STN (Super Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, MVA (Multi-domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment), ASV (Advanced Super View) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optical Compensated Birefringence) mode, ECB (Electrically Controlled Birefringence) mode nematic liquid crystal, cholesteric liquid crystal, smectic liquid crystal, discotic liquid crystal, thermotropic liquid crystal, lyotropic liquid crystal, low molecular weight liquid crystal, high molecular weight liquid crystal, polymer dispersed liquid crystal (PDLC), ferroelectric liquid crystal, antiferroelectric liquid crystal, main chain type liquid crystal, side chain type high molecular weight liquid crystal, plasma addressed liquid crystal (PALC), banana type liquid crystal, TN (Twisted Nematic) mode, STN (Super Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, MVA (Multi-domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment), ASV (Advanced Super View) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optical Compensated Birefringence) mode, ECB (Electrically Controlled Birefringence) mode nematic liquid crystal, cholesteric liquid crystal, smectic liquid crystal, discotic liquid crystal, thermotropic liquid crystal, lyotropic liquid crystal, low molecular weight liquid crystal, high molecular weight liquid crystal, polymer dispersed liquid crystal (PDLC), ferroelectric liquid crystal, antiferroelectric liquid crystal, main chain type liquid crystal, side chain type high molecular weight liquid crystal, plasma addressed liquid crystal (PALC), banana type liquid crystal, TN (Twisted Nematic) mode, STN (Super Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, MVA (Multi-domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment), ASV (Advanced Super View) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optical Compensated Birefringence) mode, ECB (Electrically Controlled Birefringence) mode nematic liquid crystal, cholesteric liquid crystal, smectic liquid crystal, discotic liquid crystal, thermotropic liquid crystal, lyotropic liquid crystal, low molecular weight liquid crystal, high molecular weight liquid crystal, polymer dispersed liquid crystal (PDLC), ferroelectric liquid crystal, antiferroelectric liquid crystal, main chain type liquid crystal, side chain type high molecular weight liquid crystal, plasma addressed liquid crystal (PALC), banana type liquid crystal, TN (Twisted Nematic) mode, STN (Super Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, MVA (Multi-domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment), ASV (Advanced Super View) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optical Compensated Birefringence) mode, ECB (Electrically Controlled Birefringence) mode nematic liquid crystal, cholesteric liquid crystal, smectic liquid crystal, discotic liquid crystal, thermotropic liquid crystal, lyotropic liquid crystal, low molecular weight liquid crystal, high molecular weight liquid crystal, polymer dispersed liquid crystal (PDLC), ferroelectric liquid crystal, antiferroelectric liquid crystal, main chain type liquid crystal, side chain type high molecular weight liquid crystal, plasma addressed liquid crystal (PALC), banana type liquid crystal, TN (Twisted Nematic) mode, STN (Super Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, MVA (Multi-domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment), ASV (Advanced Super View) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optical Compensated Birefringence) mode, ECB (Electrically Controlled Birefringence) mode Those using a guest-host mode, a blue phase mode, etc. are available. However, the present invention is not limited thereto, and various liquid crystal elements can be used.

[0023] In addition, various structures of transistors can be used as the transistor. Therefore, there is no limitation on the type of transistor. As an example of the transistor, a thin film transistor (TFT) having an amorphous semiconductor film typified by amorphous silicon, polycrystalline silicon, microcrystalline (also referred to as microcrystal, nanocrystal, semi-amorphous ) silicon, etc. can be used.

[0024] In addition, as an example of the transistor, ZnO, a-InGaZnO, SiGe, GaAs , IZO (indium zinc oxide), ITO (indium tin oxide), SnO, TiO, a transistor having a compound semiconductor or an oxide semiconductor such as AlZnSnO (AZTO), or a thin film transistor in which these compound semiconductors or oxide semiconductors are thinned can be used.

[0025] In addition, as an example of the transistor, a transistor formed by using an inkjet method or a printing method can be used.

[0026] In addition, as an example of the transistor, a transistor having an organic semiconductor or a carbon nanotube can be used.

[0027] In addition, various structures of transistors can be used as the transistor. For example, as the transistor, a MOS type transistor, a junction type transistor, a bipolar transistor, etc. can be used.​​​​

[0028] Also, as an example of the transistor, a transistor with a multi-gate structure having two or more gate electrodes can be used.

[0029] Also, as an example of the transistor, a transistor having a structure in which gate electrodes are disposed above and below the channel can be applied.

[0030] Also, as an example of the transistor, structures such as a structure in which a gate electrode is disposed above the channel region, a structure in which a gate electrode is disposed below the channel region, a positive stagger structure, an inverse stagger structure, a structure in which the channel region is divided into a plurality of regions, a structure in which the channel regions are connected in parallel, or a structure in which the channel regions are connected in series can be used.

[0031] Also, as an example of the transistor, a transistor having a structure in which a source electrode or a drain electrode overlaps with the channel region (or a part thereof) can be used.

[0032] Also, as an example of the transistor, a transistor having a structure provided with an LDD (Lightly Doped Drain ) region can be applied.

[0033] Also, the type of the substrate on which the transistor is formed is not limited to a specific one, and transistors can be formed using various substrates. As an example of the substrate, a semiconductor substrate, a single crystal substrate (e.g., a silicon substrate), an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a metal substrate, a stainless steel substrate, a substrate having a stainless steel foil, a tungsten substrate, a substrate having a tungsten foil, a flexible substrate, a bonded substrate, etc. can be used. Examples include a film, paper containing fibrous materials, or a base film. An example of a glass substrate is barium borosilicate glass, aluminoborosilicate glass, or soda lime glass and the like. Examples of flexible substrates include plastics represented by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), or synthetic resins having flexibility such as acrylic. Examples of laminated films include polypropylene, polyester, vinyl, polyvinyl fluoride, or vinyl chloride and the like. Examples of base films include polyester, polyamide, polyimide, inorganic vapor deposition films, or papers. In particular, by manufacturing transistors using semiconductor substrates, single crystal substrates, or SOI substrates, etc., transistors with less variation in characteristics, size, or shape, high current capacity, and small size can be manufactured. When a circuit is configured with such transistors, power consumption reduction of the circuit or high integration of the circuit can be achieved.

[0034] Note that a transistor may be formed using a certain substrate, and then the transistor may be transposed to another substrate and arranged on the other substrate. Examples of the substrate onto which the transistor is transposed include, in addition to the substrates on which the above-described transistors can be formed, paper substrates, cellophane substrates, stone substrates, wood substrates, cloth substrates (including natural fibers (silk, cotton, hemp), synthetic fibers (nylon, polyurethane, polyester) or regenerated fibers (acetate, cupra, rayon, recycled polyester)), leather substrates, or rubber substrates. By using these substrates, improvement of the electrical characteristics of the transistor or reduction of the power consumption of the transistor can be achieved. ​ can be achieved, and further, the reliability and heat resistance of the device using the transistor can be improved, and the weight can be reduced, or the device can be made thinner.

[0035] In addition, all of the circuits necessary to realize a predetermined function can be formed on the same substrate (for example, a glass substrate, a plastic substrate, a single crystal substrate, or an SOI substrate, etc.). In this way, cost reduction by reducing the number of parts, or improvement of reliability by reducing the number of connection points with circuit components can be achieved.

[0036] It is also possible not to form all of the circuits necessary to realize a predetermined function on the same substrate. That is, a part of the circuits necessary to realize a predetermined function is formed on a certain substrate, and another part of the circuits necessary to realize a predetermined function can be formed on another substrate. For example, a part of the circuits necessary to realize a predetermined function can be formed on a glass substrate, and another part of the circuits necessary to realize a predetermined function can be formed on a single crystal substrate (or an SOI substrate). Then, the single crystal substrate on which another part of the circuits necessary to realize a predetermined function is formed can be connected to the glass substrate by COG (Chip On G lass), and it is possible to arrange the device (also referred to as an IC chip) having circuits provided on the substrate on the glass substrate. Or, the IC chip can be connected to the glass substrate using TAB (Tape Automated Bonding), COF (Chip On Fil m), SMT (Surface Mount Technology), or a printed circuit board, etc. In this way, a part of the circuit is a pixel (Tape Automated Bonding), COF (Chip On Fil m), SMT (Surface Mount Technology), or a printed circuit board, etc. can be used to connect to the glass substrate. In this way, since a part of the circuit is a pixel By being formed on the same substrate as the section, it is possible to reduce costs by reducing the number of components, or improve reliability by reducing the number of connection points to circuit components. In particular, in a circuit in a portion where the drive voltage is large, or in a circuit in a portion where the drive frequency is high, etc., the power consumption often increases. Therefore, such a circuit is formed on a substrate different from the pixel section (for example, a single crystal substrate) to constitute an IC chip. By using this IC chip, an increase in power consumption can be prevented. In particular, in a circuit in a portion where the drive voltage is large, or in a circuit in a portion where the drive frequency is high, etc., the power consumption often increases. In particular, in a circuit in a portion where the drive voltage is large, or in a circuit in a portion where the drive frequency is high, etc., the power consumption often increases. Therefore, such a circuit is formed on a substrate different from the pixel section (for example, a single crystal substrate) to constitute an IC chip. Therefore, such a circuit is formed on a substrate different from the pixel section (for example, a single crystal substrate) to constitute an IC chip. By using this IC chip, an increase in power consumption can be prevented.

[0037] Note that as the transistor, for example, an element having at least three terminals including a gate, a drain, and a source can be used. The element has a channel region between the drain region and the source region, and current can flow through the drain region, the channel region, and the source region. Here, since the source and the drain change depending on the structure or operating conditions of the transistor, etc., it is difficult to limit which one is the source or the drain. Therefore, the region functioning as the source and the region functioning as the drain may not be called the source or the drain. In that case, as an example, either one of the source and the drain may be denoted as the first terminal, the first electrode, or the first region, and the other may be denoted as the second terminal, the second electrode, or the second region. Also, the gate may be denoted as the third terminal or the third electrode. Note that as the transistor, for example, an element having at least three terminals including a gate, a drain, and a source can be used. The element has a channel region between the drain region and the source region, and current can flow through the drain region, the channel region, and the source region. The element has a channel region between the drain region and the source region, and current can flow through the drain region, the channel region, and the source region. Here, since the source and the drain change depending on the structure or operating conditions of the transistor, etc., it is difficult to limit which one is the source or the drain. Therefore, the region functioning as the source and the region functioning as the drain may not be called the source or the drain. Therefore, the region functioning as the source and the region functioning as the drain may not be called the source or the drain. In that case, as an example, either one of the source and the drain may be denoted as the first terminal, the first electrode, or the first region, and the other may be denoted as the second terminal, the second electrode, or the second region. In that case, as an example, either one of the source and the drain may be denoted as the first terminal, the first electrode, or the first region, and the other may be denoted as the second terminal, the second electrode, or the second region. Also, the gate may be denoted as the third terminal or the third electrode.

[0038] Note that the transistor may be an element having at least three terminals including a base, an emitter, and a collector. Also in this case, as an example, either one of the emitter and the collector may be denoted as the first terminal, the first electrode, or the first region, and the other of the emitter and the collector may be denoted as the second Note that the transistor may be an element having at least three terminals including a base, an emitter, and a collector. In that case, as an example, either one of the emitter and the collector may be denoted as the first terminal, the first electrode, or the first region, and the other of the emitter and the collector may be denoted as the second It may be described as a terminal, a second electrode, or a second region. When a bipolar transistor is used as the transistor, it is possible to rephrase the description of the gate based on that term.

[0039] In addition, when it is explicitly described that A and B are connected, it includes the case where A and B are electrically connected, the case where A and B are functionally connected, and the case where A and B are directly connected. Here, A and B are assumed to be objects (for example, devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.). Therefore, it is not limited to the predetermined connection relationship, for example, the connection

[0040] relationship shown in the figure or the text, but also includes those outside the connection relationship shown in the figure or the text. As an example of the case where A and B are electrically connected, an element

[0041] that enables electrical connection between A and B (for example, a switch, a transistor, a capacitive element, an inductor, a resistive element, a diode, etc.) can be connected by one or more between A and B. As an example of the case where A and B are functionally connected, a circuit that enables functional connection between A and B (for example, a logic circuit (inverter, NAND circuit, NOR circuit, etc.), a signal conversion circuit One or more (such as a memory circuit and a control circuit) can be connected between A and B. In addition, as an example, even if another circuit is interposed between A and B, when the signal output from A is transmitted to B, A and B are considered to be functionally connected. In addition, as an example, even if another circuit is interposed between A and B, when the signal output from A is transmitted to B, A and B are considered to be functionally connected. Transmitted, then A and B are considered to be functionally connected.

[0042] In addition, when it is explicitly described that A and B are electrically connected, it includes the case where A and B are electrically connected (that is, connected with another element or another circuit interposed between A and B), the case where A and B are functionally connected (that is, functionally connected with another circuit interposed between A and B), and the case where A and B are directly connected (that is, connected without another element or another circuit interposed between A and B). That is, when it is explicitly described that they are electrically connected, it is considered to be the same as when it is only explicitly described that they are connected. The case where A and B are electrically connected (that is, connected with another element or another circuit interposed between A and B), the case where A and B are functionally connected (that is, functionally connected with another circuit interposed between A and B), and the case where A and B are directly connected (that is, connected without another element or another circuit interposed between A and B). The case where A and B are electrically connected (that is, connected with another element or another circuit interposed between A and B), the case where A and B are functionally connected (that is, functionally connected with another circuit interposed between A and B), and the case where A and B are directly connected (that is, connected without another element or another circuit interposed between A and B). The case where A and B are directly connected (that is, connected without another element or another circuit interposed between A and B). That is, it includes the case where A and B are connected without another element or another circuit interposed between A and B). That is, when it is explicitly described that they are electrically connected, it is considered to be the same as when it is only explicitly described that they are connected. That is, when it is explicitly described that they are electrically connected, it is considered to be the same as when it is only explicitly described that they are connected.

[0043] In addition, when it is explicitly described that B is formed on A, or B is formed on A, it is not limited to the case where B is directly formed in contact with A. It also includes the case where they are not in direct contact, that is, the case where another object is interposed between A and B. Here, A and B are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.). When it is explicitly described that B is formed on A, or B is formed on A, it is not limited to the case where B is directly formed in contact with A. It also includes the case where they are not in direct contact, that is, the case where another object is interposed between A and B. That is, it also includes the case where they are not in direct contact, that is, the case where another object is interposed between A and B. Here, A and B are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.). Here, A and B are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.). That is, it is assumed that A and B are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

[0044] Therefore, for example, when it is explicitly described that layer B is formed on (or on) layer A, it includes the case where layer B is directly formed in contact with layer A, and the case where another layer (for example, layer C or layer D, etc.) is directly formed in contact with layer A and layer B is directly formed on it. When it is explicitly described that layer B is formed on (or on) layer A, it includes the case where layer B is directly formed in contact with layer A, and the case where another layer (for example, layer C or layer D, etc.) is directly formed in contact with layer A and layer B is directly formed on it. Directly in contact with layer A, another layer (for example, layer C or layer D, etc.) is formed, and layer B is directly formed on it. including the case where it is formed. Note that another layer (for example, layer C, layer D, etc.) may be a single layer or a multi-layer.

[0045] Furthermore, the same applies to the case where it is explicitly described that B is formed above A. It is not limited to the case where B is in direct contact with A, and includes the case where another object is interposed between A and B. Therefore, for example, in the case where it is said that layer B is formed above layer A, it includes the case where layer B is formed in direct contact with layer A and the case where another layer (for example, layer C, layer D, etc.) is formed in direct contact with layer A and layer B is formed in direct contact with it. Note that another layer (for example, layer C, layer D, etc.) may be a single layer or a multi-layer. layer or a multi-layer. layer or a multi-layer. layer or a multi-layer.

[0046] Note that when explicitly describing that B is formed on A, B is formed above A, or B is formed above A, it is to be included that B is formed obliquely upward. Also, the same applies to the case where B is formed below A or B is formed below A.

[0047]

[0047] Note that for what is explicitly described as singular, it is desirable to be singular. However, it is not limited to this, and it is also possible to be plural. Similarly, for what is explicitly described as plural, it is desirable to be plural. However, it is not limited to this and it is also possible to be singular.

[0048]

[0048] Note that in the figure, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.

[0049] ​ Note that the drawings schematically show ideal examples and are not limited to the shapes or values shown in the drawings. For example, the drawings may include variations in shape due to manufacturing techniques, variations in shape due to errors, variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing deviations. Note that technical terms are often used for the purpose of describing specific embodiments or examples. However, one aspect of the invention is not to be construed as being limited by technical terms. Note that terms not defined (including scientific and technical terms such as technical terms or academic terms) can be used as having a meaning equivalent to the general meaning understood by a person skilled in the art. Terms defined by a dictionary or the like are preferably interpreted in a meaning that does not conflict with the background of the related art. Note that terms such as "first," "second," "third," etc. are used to distinguish various elements, members, regions, layers, areas from others. Therefore, terms such as "first," "second," "third," etc. do not limit the number of elements, members, regions, layers, areas, etc. Further, for example, "the first" can be replaced with "the second" or "the third," etc.

[0050] Note that terms indicating spatial arrangements such as "above," "upward," "below," "downward," "sideways," "right," "left," "diagonally," "in the back," "in the front," "inside," "outside," or "in the middle" are often used to easily show the relationship between one element or feature and another element or feature by the drawings. However, it is not limited to this, and these spatial arrangements are shown Note that the drawings schematically show ideal examples and are not limited to the shapes or values shown in the drawings. For example, the drawings may include variations in shape due to manufacturing techniques, variations in shape due to errors, variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing deviations.

[0051] Note that technical terms are often used for the purpose of describing specific embodiments or examples. However, one aspect of the invention is not to be construed as being limited by technical terms. Note that terms not defined (including scientific and technical terms such as technical terms or academic terms) can be used as having a meaning equivalent to the general meaning understood by a person skilled in the art. Terms defined by a dictionary or the like are preferably interpreted in a meaning that does not conflict with the background of the related art. Note that terms such as "first," "second," "third," etc. are used to distinguish various elements, members, regions, layers, areas from others. Therefore, terms such as "first," "second," "third," etc. do not limit the number of elements, members, regions, layers, areas, etc. Further, for example, "the first" can be replaced with "the second" or "the third," etc. Note that terms indicating spatial arrangements such as "above," "upward," "below," "downward," "sideways," "right," "left," "diagonally," "in the back," "in the front," "inside," "outside," or "in the middle" are often used to easily show the relationship between one element or feature and another element or feature by the drawings. However, it is not limited to this, and these spatial arrangements are shown

[0052] Note that terms such as "first," "second," "third," etc. are used to distinguish various elements, members, regions, layers, areas from others. Therefore, terms such as "first," "second," "third," etc. do not limit the number of elements, members, regions, layers, areas, etc. Further, for example, "the first" can be replaced with "the second" or "the third," etc. Note that terms indicating spatial arrangements such as "above," "upward," "below," "downward," "sideways," "right," "left," "diagonally," "in the back," "in the front," "inside," "outside," or "in the middle" are often used to easily show the relationship between one element or feature and another element or feature by the drawings. However, it is not limited to this, and these spatial arrangements are shown Note that terms such as "first," "second," "third," etc. are used to distinguish various elements, members, regions, layers, areas from others. Therefore, terms such as "first," "second," "third," etc. do not limit the number of elements, members, regions, layers, areas, etc. Further, for example, "the first" can be replaced with "the second" or "the third," etc. Note that terms indicating spatial arrangements such as "above," "upward," "below," "downward," "sideways," "right," "left," "diagonally," "in the back," "in the front," "inside," "outside," or "in the middle" are often used to easily show the relationship between one element or feature and another element or feature by the drawings. However, it is not limited to this, and these spatial arrangements are shown

[0053] Note that terms indicating spatial arrangements such as "above," "upward," "below," "downward," "sideways," "right," "left," "diagonally," "in the back," "in the front," "inside," "outside," or "in the middle" are often used to easily show the relationship between one element or feature and another element or feature by the drawings. However, it is not limited to this, and these spatial arrangements are shown Note that terms indicating spatial arrangements such as "above," "upward," "below," "downward," "sideways," "right," "left," "diagonally," "in the back," "in the front," "inside," "outside," or "in the middle" are often used to easily show the relationship between one element or feature and another element or feature by the drawings. However, it is not limited to this, and these spatial arrangements are shown Note that terms indicating spatial arrangements such as "above," "upward," "below," "downward," "sideways," "right," "left," "diagonally," "in the back," "in the front," "inside," "outside," or "in the middle" are often used to easily show the relationship between one element or feature and another element or feature by the drawings. However, it is not limited to this, and these spatial arrangements are shown Note that terms indicating spatial arrangements such as "above," "upward," "below," "downward," "sideways," "right," "left," "diagonally," "in the back," "in the front," "inside," "outside," or "in the middle" are often used to easily show the relationship between one element or feature and another element or feature by the drawings. However, it is not limited to this, and these spatial arrangements are shown The term "above" can include other directions in addition to the direction depicted in the figure. For example, when explicitly shown as B above A, it is not limited to B being directly above A. Since the devices in the figure can be flipped or rotated 180°, it is possible that B is below A. Thus, the term "above" can include the direction of "below" in addition to the direction of "above". However, not limited to this, since the devices in the figure can be rotated in various directions, the term "above" can include directions such as "sideways", "to the right", "to the left", "diagonal", "towards the back", "towards the front", "inward", "outward", "outside", or "inside", etc. in addition to the directions of "above" and "below". That is, it can be interpreted appropriately according to the situation.

[0054] One aspect of the present invention has a first switch connected between a first wiring and a second wiring, and a second switch connected between the first wiring and the second wiring. In a first period, the first switch is turned on and the second switch is turned off. In a second period, the first switch is turned off and the second switch is turned off. In a third period, the first switch is turned off and the second switch is turned on. In a fourth period, the first switch is turned off and the second switch is turned off.

[0055] One aspect of the present invention has a first path and a second path between a first wiring and a second wiring. In a first period, the first wiring and the second wiring are in a conductive state via the first path. In a second period, the first wiring and the second wiring are in a non-conductive state. In a third period, At this time, the first wiring and the second wiring are in a conductive state via the second path, and in the fourth period At this time, the first wiring and the second wiring are in a non-conductive state.

[0056] One aspect of the present invention has a first transistor and a second transistor. The first terminal of the first transistor is connected to the first wiring, the second terminal of the first transistor is connected to the second wiring, the gate of the first transistor is connected to the third wiring, the first terminal of the second transistor is connected to the first wiring, the second terminal of the second transistor is connected to the second wiring, and the gate of the second transistor is connected to the fourth wiring. The first terminal of the first transistor is connected to the first wiring, the second terminal of the first transistor is connected to the second wiring, the gate of the first transistor is connected to the third wiring, the first terminal of the second transistor is connected to the first wiring, the second terminal of the second transistor is connected to the second wiring, and the gate of the second transistor is connected to the fourth wiring. The first terminal of the first transistor is connected to the first wiring, the second terminal of the first transistor is connected to the second wiring, the gate of the first transistor is connected to the third wiring, the first terminal of the second transistor is connected to the first wiring, the second terminal of the second transistor is connected to the second wiring, and the gate of the second transistor is connected to the fourth wiring. The first terminal of the first transistor is connected to the first wiring, the second terminal of the first transistor is connected to the second wiring, the gate of the first transistor is connected to the third wiring, the first terminal of the second transistor is connected to the first wiring, the second terminal of the second transistor is connected to the second wiring, and the gate of the second transistor is connected to the fourth wiring. The first terminal of the first transistor is connected to the first wiring, the second terminal of the first transistor is connected to the second wiring, the gate of the first transistor is connected to the third wiring, the first terminal of the second transistor is connected to the first wiring, the second terminal of the second transistor is connected to the second wiring, and the gate of the second transistor is connected to the fourth wiring.

[0057] One aspect of the present invention has a first transistor and a second transistor. In the first period, the first transistor is turned on and the second transistor is turned off. In the second period, the first transistor is turned off and the second transistor is turned on. In the third period, the first transistor is turned off and the second transistor is turned off. In the fourth period, the first transistor is turned off and the second transistor is turned on. In the first period, the first transistor is turned on and the second transistor is turned off. In the second period, the first transistor is turned off and the second transistor is turned on. In the third period, the first transistor is turned off and the second transistor is turned off. In the fourth period, the first transistor is turned off and the second transistor is turned on. In the fourth period, the first transistor is turned off and the second transistor is turned on.

[0058] One aspect of the present invention has a first transistor, a second transistor, and a third transistor. The first terminal of the first transistor is connected to the first wiring, the second terminal of the first transistor is connected to the second wiring, the gate of the first transistor is connected to the third wiring, the first terminal of the second transistor is connected to the first wiring, the second terminal of the second transistor is connected to the second wiring, the gate of the second transistor is connected to the fourth wiring. The first terminal of the first transistor is connected to the first wiring, the second terminal of the first transistor is connected to the second wiring, the gate of the first transistor is connected to the third wiring, the first terminal of the second transistor is connected to the first wiring, the second terminal of the second transistor is connected to the second wiring, the gate of the second transistor is connected to the fourth wiring. The first terminal of the first transistor is connected to the first wiring, the second terminal of the first transistor is connected to the second wiring, the gate of the first transistor is connected to the third wiring, the first terminal of the second transistor is connected to the first wiring, the second terminal of the second transistor is connected to the second wiring, the gate of the second transistor is connected to the fourth wiring. The first terminal of the first transistor is connected to the first wiring, the second terminal of the first transistor is connected to the second wiring, the gate of the first transistor is connected to the third wiring, the first terminal of the second transistor is connected to the first wiring, the second terminal of the second transistor is connected to the second wiring, the gate of the second transistor is connected to the fourth wiring. The first terminal of the first transistor is connected to the first wiring, the second terminal of the first transistor is connected to the second wiring, the gate of the first transistor is connected to the third wiring, the first terminal of the second transistor is connected to the first wiring, the second terminal of the second transistor is connected to the second wiring, the gate of the second transistor is connected to the fourth wiring. The first terminal of the third transistor is connected to the fifth wiring. The second terminal is connected to the second wiring, and the gate of the third transistor is connected to the sixth wiring. It is something that is done. Effect of the Invention

[0059] According to one embodiment of the present invention, deterioration of the characteristics of a transistor can be suppressed. The embodiment allows the channel width of the transistor to be reduced. It is possible to suppress the deterioration of the characteristics of the transistor and to reduce the channel width. According to one embodiment of the present invention, a layout area can be reduced. Alternatively, one embodiment of the present invention can provide a display device with high resolution. Alternatively, one embodiment of the present invention can increase the yield. According to one embodiment of the present invention, manufacturing costs can be reduced. Alternatively, one embodiment of the present invention can reduce the current supply capability of an external circuit. Alternatively, one aspect of the present invention is to provide a method for manufacturing a semiconductor device having an external circuit. The size of the display device can be reduced. [Brief description of the drawings]

[0060]

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Embodiments for Carrying Out the Invention

[0061] Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments can be implemented in many different ways, and it will be easily understood by those skilled in the art that the form and details can be variously changed without departing from the spirit and its scope. Therefore, the present embodiments should not be construed as being limited to the described content. In the configurations described below, the same reference numerals are used to indicate the same components among different drawings, and detailed descriptions of the same parts or parts having similar functions are omitted.

[0062] Note that the content described in one embodiment (even part of the content) can be applied to, combined with, or replaced with the content described in another part (even part of the content) in that embodiment, and / or the content described in one or more other embodiments (even part of the content). That is, operations such as application, combination, or replacement can be performed.

[0063] Note that the content described in the embodiments refers to the content described using various drawings in each embodiment, or the content described using the text described in the specification. That is, it is the content described using the text described in the specification.

[0064] Note that the diagram (even part of it) described in one embodiment can be another part of that diagram, Another figure (which may be a part) described in the embodiment, and / or, by combining with the figure (which may be a part) described in one or more other embodiments, more figures can be further constituted.

[0065] In addition, in the figure or text described in a certain embodiment, it is possible to take out a part of it to constitute an aspect of the invention. Therefore, when a figure or text describing a certain part is described, the content obtained by taking out a part of the figure or text is also disclosed as an aspect of the invention and can constitute an aspect of the invention. Therefore, for example, active elements (such as transistors, diodes, etc.), wirings, passive elements (capacitor elements, resistor elements, etc.), conductive layers, insulating layers, semiconductor layers, organic materials, inorganic materials, components, substrates, modules, devices, solids, liquids, gases, operation methods, manufacturing methods, etc., when one or more are described in drawings (cross-sectional views, plan views, circuit diagrams, block diagrams, flowcharts, process diagrams, perspective views, elevation views, layout diagrams, timing charts, structure diagrams, schematic diagrams, graphs, tables, optical path diagrams, vector diagrams, state diagrams, waveform diagrams, photographs, chemical formulas, etc.) or text, it is possible to take out a part of it to constitute an aspect of the invention.

[0066] (Embodiment 1) In this embodiment, an example of a semiconductor device will be described. The semiconductor device of this embodiment is as an example, applicable to various drive circuits such as shift registers, gate drivers, or source drivers. Note that the semiconductor device of this embodiment can be indicated as a drive circuit or a circuit .

[0067] First, the semiconductor device of the present embodiment will be described with reference to FIG. 1(A). FIG. 1(A) The semiconductor device has a plurality of switches such as switches 11_1 to 11_2. The switches 11_1 to 11_2 are connected between wiring 111 and wiring 112. However, this is not limited thereto, and the semiconductor device can have three or more switches.

[0068] Next, signals, voltages, etc. input to or output from each wiring will be described.

[0069] As an example, assume that a signal OUT is output from wiring 111. The signal OUT can be, for example, a signal having a first potential state and a second potential state. For example, the signal O UT can often be a digital signal having two states, a H level (also referred to as a high level) and an L level, and can function as an output signal. Therefore, wiring 111 can function as a signal line. In particular, wiring 111 can be extended and arranged in the pixel portion and can be connected to a pixel. For example, in the case of a liquid crystal display device, wiring 111 can be connected to a pixel having a liquid crystal element, and a voltage applied to the liquid crystal element can be set according to the potential of wiring 111. Or, the wiring 111 can be connected to the gate of a transistor (for example, a selection transistor or a switching transistor) included in the pixel. In such a case, the signal OUT can function as a selection signal, a transfer signal, a start signal, a reset signal, a gate signal, or a scan signal. Therefore, wiring 111 can function as a gate signal line (gate line) or a scan line.

[0070] ​​​As an example, it is assumed that a signal CK1 is input to the wiring 112. The signal CK1 can be a signal having, for example, a first potential state and a second potential state. For example, the signal CK1 is often a digital signal that repeats between two states of an H level and an L level, and can function as a clock signal. Therefore, the wiring 112 can function as a signal line or a clock signal line. However, it is not limited to this, and various other signals, various voltages, or various currents can be input to the wiring 111 or the wiring 112. For example, a voltage can be supplied to the wiring 111 or the wiring 112, and these wirings can function as power supply lines. For example, it can be a signal having a first potential state and a second potential state. For example, the signal CK 1 is often a digital signal that repeats between two states of an H level and an L level, and can function as a clock signal. Therefore, the wiring 112 can function as a signal line or a clock signal line. However, it is not limited to this, and the wiring 111, or the wiring 112 can also have various other signals, various voltages, or various currents input thereto. For example, a voltage can be supplied to the wiring 111 or the wiring 112, and these wirings can function as power supply lines. As an example, let the potential of the signal in the first potential state, that is, the L-level signal, be V1, and the potential of the signal in the second potential state, that is, the H-level signal, be V2. And let V2 > V1. However, it is not limited to this, and the potential of the L-level signal can be lower than V1 or higher than V1. Or, the potential of the H-level signal can be lower than V2 or higher than V2. For example, depending on the circuit configuration, even when a signal is described as an H-level signal, its potential may be lower than V2 or higher than V2. Or, depending on the circuit configuration, even when a signal is described as an L-level signal, its potential may be lower than V1 or higher than V1. As an example, let the potential of the signal in the first potential state, that is, the L-level signal, be V1, and the potential of the signal in the second potential state, that is, the H-level signal, be V2. And let V2 > V1. However, it is not limited to this, and the potential of the L-level signal can be lower than V1 or higher than V1. Or, the potential of the H-level signal can be lower than V2 or higher than V2. For example, depending on the circuit configuration, even when a signal is described as an H-level signal, its potential may be lower than V2 or higher than V2. Or, depending on the circuit configuration, even when a signal is described as an L-level signal, its potential may be lower than V1 or higher than V1.

[0071] As an example, let the potential of the signal in the first potential state, that is, the L-level signal, be V1, and the potential of the signal in the second potential state, that is, the H-level signal, be V2. And let V2 > V1. However, it is not limited to this, and the potential of the L-level signal can be lower than V1 or higher than V1. Or, the potential of the H-level signal can be lower than V2 or higher than V2. For example, depending on the circuit configuration, even when a signal is described as an H-level signal, its potential may be lower than V2 or higher than V2. Or, depending on the circuit configuration, even when a signal is described as an L-level signal, its potential may be lower than V1 or higher than V1. As an example, let the potential of the signal in the first potential state, that is, the L-level signal, be V1, and the potential of the signal in the second potential state, that is, the H-level signal, be V2. And let V2 > V1. However, it is not limited to this, and the potential of the L-level signal can be lower than V1 or higher than V1. Or, the potential of the H-level signal can be lower than V2 or higher than V2. For example, depending on the circuit configuration, even when a signal is described as an H-level signal, its potential may be lower than V2 or higher than V2. Or, depending on the circuit configuration, even when a signal is described as an L-level signal, its potential may be lower than V1 or higher than V1. As an example, let the potential of the signal in the first potential state, that is, the L-level signal, be V1, and the potential of the signal in the second potential state, that is, the H-level signal, be V2. And let V2 > V1. However, it is not limited to this, and the potential of the L-level signal can be lower than V1 or higher than V1. Or, the potential of the H-level signal can be lower than V2 or higher than V2. For example, depending on the circuit configuration, even when a signal is described as an H-level signal, its potential may be lower than V2 or higher than V2. Or, depending on the circuit configuration, even when a signal is described as an L-level signal, its potential may be lower than V1 or higher than V1. As an example, let the potential of the signal in the first potential state, that is, the L-level signal, be V1, and the potential of the signal in the second potential state, that is, the H-level signal, be V2. And let V2 > V1. However, it is not limited to this, and the potential of the L-level signal can be lower than V1 or higher than V1. Or, the potential of the H-level signal can be lower than V2 or higher than V2. For example, depending on the circuit configuration, even when a signal is described as an H-level signal, its potential may be lower than V2 or higher than V2. Or, depending on the circuit configuration, even when a signal is described as an L-level signal, its potential may be lower than V1 or higher than V1. As an example, let the potential of the signal in the first potential state, that is, the L-level signal, be V1, and the potential of the signal in the second potential state, that is, the H-level signal, be V2. And let V2 > V1. However, it is not limited to this, and the potential of the L-level signal can be lower than V1 or higher than V1. Or, the potential of the H-level signal can be lower than V2 or higher than V2. For example, depending on the circuit configuration, even when a signal is described as an H-level signal, its potential may be lower than V2 or higher than V2. Or, depending on the circuit configuration, even when a signal is described as an L-level signal, its potential may be lower than V1 or higher than V1. As an example, let the potential of the signal in the first potential state, that is, the L-level signal, be V1, and the potential of the signal in the second potential state, that is, the H-level signal, be V2. And let V2 > V1. However, it is not limited to this, and the potential of the L-level signal can be lower than V1 or higher than V1. Or, the potential of the H-level signal can be lower than V2 or higher than V2. For example, depending on the circuit configuration, even when a signal is described as an H-level signal, its potential may be lower than V2 or higher than V2. Or, depending on the circuit configuration, even when a signal is described as an L-level signal, its potential may be lower than V1 or higher than V1. As an example, let the potential of the signal in the first potential state, that is, the L-level signal, be V1, and the potential of the signal in the second potential state, that is, the H-level signal, be V2. And let V2 > V1. However, it is not limited to this, and the potential of the L-level signal can be lower than V1 or higher than V1. Or, the potential of the H-level signal can be lower than V2 or higher than V2. For example, depending on the circuit configuration, even when a signal is described as an H-level signal, its potential may be lower than V2 or higher than V2. Or, depending on the circuit configuration, even when a signal is described as an L-level signal, its potential may be lower than V1 or higher than V1. As an example, let the potential of the signal in the first potential state, that is, the L-level signal, be V1, and the potential of the signal in the second potential state, that is, the H-level signal, be V2. And let V2 > V1. However, it is not limited to this, and the potential of the L-level signal can be lower than V1 or higher than V1. Or, the potential of the H-level signal can be lower than V2 or higher than V2. For example, depending on the circuit configuration, even when a signal is described as an H-level signal, its potential may be lower than V2 or higher than V2. Or, depending on the circuit configuration, even when a signal is described as an L-level signal, its potential may be lower than V1 or higher than V1.

[0072] Note that "generally" includes various errors such as errors due to noise, errors due to process variations, errors due to variations in the manufacturing process of elements, and / or measurement errors. Note that "generally" includes various errors such as errors due to noise, errors due to process variations, errors due to variations in the manufacturing process of elements, and / or measurement errors.

[0073] Note that, generally, voltage refers to the difference in electric potential (also called potential difference) between two points, and electric potential refers to the electrostatic energy (electrical potential energy) possessed by a unit charge in an electrostatic field at a certain point. However, in an electronic circuit, even for a single point, for example, the potential difference between the potential of that point and the reference potential (also called reference potential) may be used as a value. Also, since the values of voltage and potential can both be represented in volts (V) in a circuit diagram or the like, it is difficult to distinguish them. Therefore, in the documents of this application (specification and claims), unless otherwise specified, even for a single point, voltage may be used as a value. The electric potential refers to the electrostatic energy (electrical potential energy) possessed by a unit charge in an electrostatic field at a certain point. However, in an electronic circuit, even for a single point, for example, the potential difference between the potential of that point and the reference potential (also called reference potential) may be used as a value. Also, since the values of voltage and potential can both be represented in volts (V) in a circuit diagram or the like, it is difficult to distinguish them. Therefore, in the documents of this application (specification and claims), unless otherwise specified, even for a single point, voltage may be used as a value. Note that, generally, voltage refers to the difference in electric potential (also called potential difference) between two points, and electric potential refers to the electrostatic energy (electrical potential energy) possessed by a unit charge in an electrostatic field at a certain point. However, in an electronic circuit, even for a single point, for example, the potential difference between the potential of that point and the reference potential (also called reference potential) may be used as a value.

[0074] Note that signal CK1 can be balanced or unbalanced. By balanced, it means that the period of being at the H level and the period of being at the L level in one cycle are approximately equal. By unbalanced, it means that the period of being at the H level and the period of being at the L level are different. Here, "different" means that the range of being approximately equal is excluded. By balanced, it means that the period of being at the H level and the period of being at the L level in one cycle are approximately equal. By unbalanced, it means that the period of being at the H level and the period of being at the L level are different. Here, "different" means that the range of being approximately equal is excluded. Note that signal CK1 can be balanced or unbalanced. By balanced, it means that the period of being at the H level and the period of being at the L level in one cycle are approximately equal. By unbalanced, it means that the period of being at the H level and the period of being at the L level are different. Here, "different" means that the range of being approximately equal is excluded.

[0075] Next, the functions of switches 11_1 to 11_2 will be described. Switches 11_1 to 11_2 have the function of controlling the conduction state between wiring 111 and wiring 112. Therefore, as shown in FIG. 1(B), there are multiple paths such as paths 21_1 to 21_2 between wiring 111 and wiring 112. Alternatively, switches 11_1 and 11_2 have the function of controlling whether to set the potential state of signal OUT. However, it is not limited to this, and switches 11_1 to 11_2 can have various other functions. Next, the functions of switches 11_1 to 11_2 will be described. Switches 11_1 to 11_2 have the function of controlling the conduction state between wiring 111 and wiring 112. Therefore, as shown in FIG. 1(B), there are multiple paths such as paths 21_1 to 21_2 between wiring 111 and wiring 112. Alternatively, switches 11_1 and 11_2 have the function of controlling whether to set the potential state of signal OUT. However, it is not limited to this, and switches 11_1 to 11_2 can have various other functions. Next, the functions of switches 11_1 to 11_2 will be described. Switches 11_1 to 11_2 have the function of controlling the conduction state between wiring 111 and wiring 112.

[0076] When referring to the path between wiring A (for example, wiring 111) and wiring B (for example, wiring 112), a switch can be connected between wiring A and wiring B. However, it is not limited to this, and various elements (for example, transistors, diodes, resistance elements, or capacitance elements, etc.) or various circuits (for example, buffer circuits, inverter circuits, or shift register circuits, etc.) can be connected between wiring A and wiring B. Therefore, for example, elements such as resistance elements or transistors can be connected in series or in parallel with switch 11_1.

[0077] Next, the operation of the semiconductor device in Fig. 1(A) will be described with reference to an example of the timing chart in Fig. 2(A). However, it is not limited to this, and the semiconductor device in Fig. 1(A) can be controlled by various timings.

[0078] The timing chart in Fig. 2(A) shows the signal CK1, the state (on or off) of switch 11_1, the state (on or off) of switch 11_2, and the waveform of signal OUT, respectively. The timing chart in Fig. 2(A) has a plurality of periods, and each period has a plurality of sub-periods. For example, the timing chart in Fig. 2(A) has a plurality of periods (hereinafter, the period is also referred to as a frame period) such as period T1 and period T2. Period T1 has a plurality of sub-periods (hereinafter, the sub-period is also referred to as one gate selection period) such as period A1, period B1, period C1, period D1, and period E1, and period T2 has a plurality of sub-periods such as period A2, period B2, period C2, period D2, and period E2. However, it is not limited to this, and Fig. 2 (A)'s timing chart may have a period different from periods T1 and T2, or it is possible to omit one of periods T1 and T2. Or, period T1 may have various periods in addition to periods A1 to E1, or it is possible to omit any one of periods A1 to E1. Or, period T2 may have various periods in addition to periods A2 to E2, or it is possible to omit any one of periods A2 to E2. Note that, as an example, the semiconductor device in Fig. 1(A) is assumed to perform operations in periods T1 and T2 alternately. However, it is not limited to this, and the semiconductor device in Fig. 1(A) can perform operations in periods T1 and T2 in various orders. Note that, as an example, in period T1, the semiconductor device in Fig. 1(A) is assumed to repeat the operations in period D1 and the operations in period E1 until switch 11_1 turns on. And when switch 11_1 turns on, the semiconductor device in Fig. 1(A) is assumed to perform the operations in period A1, the operations in period B1, and the operations in period C1 in order. After that, until switch 11_1 turns on again, the semiconductor device in Fig. 1(A) is assumed to repeat the operations in period D1 and the operations in period E1. However, it is not limited to this, and the semiconductor device in Fig. 1(A) can perform the operations in periods A1 to E1 in various orders. Note that, as an example, in period T2, the semiconductor device in Fig. 1(A) is assumed to repeat the operations in period D2 and the operations in period E2 until switch 11_2 turns on.

[0079] Note that, as an example, the semiconductor device in Fig. 1(A) is assumed to perform operations in periods T1 and T2 alternately. However, it is not limited to this, and the semiconductor device in Fig. 1(A) can perform operations in periods T1 and T2 in various orders. Note that, as an example, in period T1, the semiconductor device in Fig. 1(A) is assumed to repeat the operations in period D1 and the operations in period E1 until switch 11_1 turns on. And when switch 11_1 turns on, the semiconductor device in Fig. 1(A) is assumed to perform the operations in period A1, the operations in period B1, and the operations in period C1 in order.

[0080] Note that, as an example, in period T1, the semiconductor device in Fig. 1(A) is assumed to repeat the operations in period D1 and the operations in period E1 until switch 11_1 turns on. And when switch 11_1 turns on, the semiconductor device in Fig. 1(A) is assumed to perform the operations in period A1, the operations in period B1, and the operations in period C1 in order. After that, until switch 11_1 turns on again, the semiconductor device in Fig. 1(A) is assumed to repeat the operations in period D1 and the operations in period E1. However, it is not limited to this, and the semiconductor device in Fig. 1(A) can perform the operations in periods A1 to E1 in various orders. Note that, as an example, in period T2, the semiconductor device in Fig. 1(A) is assumed to repeat the operations in period D2 and the operations in period E2 until switch 11_2 turns on. And when switch 11_2 turns on, the semiconductor device in Fig. 1(A) is assumed to perform the operations in period A2, the operations in period B2, and the operations in period C2 in order. After that, until switch 11_2 turns on again, the semiconductor device in Fig. 1(A) is assumed to repeat the operations in period D2 and the operations in period E2. However, it is not limited to this, and the semiconductor device in Fig. 1(A) can perform the operations in periods A2 to E2 in various orders. Note that, as an example, in period T1, the semiconductor device in Fig. 1(A) is assumed to repeat the operations in period D1 and the operations in period E1 until switch 11_1 turns on. And when switch 11_1 turns on, the semiconductor device in Fig. 1(A) is assumed to perform the operations in period A1, the operations in period B1, and the operations in period C1 in order.

[0081] Note that, as an example, in period T2, the semiconductor device in Fig. 1(A) is assumed to repeat the operations in period D2 and the operations in period E2 until switch 11_2 turns on. And when switch 11_2 turns on, the semiconductor device in Fig. 1(A) is assumed to perform the operations in period A2, the operations in period B2, and the operations in period C2 in order. And when switch 11_2 in FIG. 1(A) is turned on, the operations in period A2, the operation in period B2, and the operation in period C2 shall be performed in sequence. After that, until switch 11_2 in FIG. 1(A) is turned on again, the operations in period D2 and the operations in period E2 shall be repeated. However, it is not limited to this, and the semiconductor device in FIG. 1(A) can perform the operations in periods A2 to E2 in various orders. The operation in period T1 will be described. In period T1, switch 11_1 is turned on or off, and switch 11_2 is turned off. In period A1 of period T1, as shown in FIG. 2(D), switch 11_1 is turned on and switch 11_2 is turned off. Therefore, as shown in FIG. 2(E), path 21_1 becomes conductive and path 21_2 becomes non-conductive. Then, the signal (for example, a signal CK1 of L level) input to wiring 112 is supplied to wiring 111 through switch 11_1. Therefore, signal OUT becomes L level. In period B1 of period T1, as shown in FIG. 2(D), switch 11_1 remains on and switch 11_2 remains off. Therefore, as shown in FIG. 2(E), path 21_1 remains conductive and path 21_2 remains non-conductive. Then, the signal (for example, a signal CK1 of H level) input to wiring 112 is supplied to wiring 111 through switch 11_1. Therefore, signal OUT becomes H level. It is possible.

[0082] The operation in period T1 will be described. In period T1, switch 11_1 is turned on or off, and switch 11_2 is turned off. In period A1 of period T1, as shown in FIG. 2(D), switch 11_1 is turned on and switch 11_2 is turned off. Therefore, as shown in FIG. 2(E), path 21_1 becomes conductive and path 21_2 becomes non-conductive. Then, the signal (for example, a signal CK1 of L level) input to wiring 112 is supplied to wiring 111 through switch 11_1. Therefore, signal OUT becomes L level.

[0083] In period A1 of period T1, as shown in FIG. 2(D), switch 11_1 is turned on and switch 11_2 is turned off. Therefore, as shown in FIG. 2(E), path 21_1 becomes conductive and path 21_2 becomes non-conductive. Then, the signal (for example, a signal CK1 of L level) input to wiring 112 is supplied to wiring 111 through switch 11_1. Therefore, signal OUT becomes L level. Thus, path 21_1 becomes conductive and path 21_2 becomes non-conductive. Then, the signal (for example, a signal CK1 of L level) input to wiring 112 is supplied to wiring 111 through switch 11_1. Therefore, signal OUT becomes L level. In period B1 of period T1, as shown in FIG. 2(D), switch 11_1 remains on and switch 11_2 remains off. Therefore, as shown in FIG. 2(E), path 21_1 remains conductive and path 21_2 remains non-conductive. Then, the signal (for example, a signal CK1 of H level) input to wiring 112 is supplied to wiring 111 through switch 11_1. Therefore, signal OUT becomes H level. (For example, a signal CK1 of L level) is supplied to wiring 111 through switch 11_1. Therefore, signal OUT becomes L level. Therefore, signal OUT becomes L level.

[0084] In period B1 of period T1, as shown in FIG. 2(D), switch 11_1 remains on and switch 11_2 remains off. Therefore, as shown in FIG. 2(E), path 21_1 remains conductive and path 21_2 remains non-conductive. Then, the signal (for example, a signal CK1 of H level) input to wiring 112 is supplied to wiring 111 through switch 11_1. Therefore, signal OUT becomes H level. Thus, path 21_1 remains conductive and path 21_2 remains non-conductive. Then, the signal (for example, a signal CK1 of H level) input to wiring 112 is supplied to wiring 111 through switch 11_1. Therefore, signal OUT becomes H level. 21_1 remains conductive and path 21_2 remains non-conductive. Then, the signal (for example, a signal CK1 of H level) input to wiring 112 is supplied to wiring 111 through switch 11_1. Therefore, signal OUT becomes H level. The signal (for example, a signal CK1 of H level) input to wiring 112 is supplied to wiring 111 through switch 11_1. Therefore, signal OUT becomes H level. Therefore, signal OUT becomes H level.

[0085] During period C1 of period T1, as shown in FIG. 2(B), switch 11_1 turns off , and switch 11_2 remains off. Therefore, as shown in FIG. 2(C), path 21_ 1 becomes non-conductive, and path 21_2 remains non-conductive. Then, wiring 111 and wiring 112 become non-conductive, so the signal (e.g., L-level signal CK1) input to wiring 112 is not supplied to wiring 111.

[0086] Note that during period C1 of period T1, the timing at which switch 11_1 turns off is often later than the timing at which signal CK1 becomes L-level. Therefore, before switch 11_1 turns off, the signal (e.g., L-level signal CK1) input to wiring 112 is often supplied to wiring 111 via switch 11_1. Thus, signal OUT becomes L-level. However, it is not limited to this, and it is possible to supply an L-level signal or voltage V1 to wiring 111. Before switch 11_1 turns off, the signal (e.g., L-level signal CK1) input to wiring 112 is often supplied to wiring 111 via switch 11_1. Thus, signal OUT becomes L-level. However, it is not limited to this, and it is possible to supply an L-level signal or voltage V1 to wiring 111. Before switch 11_1 turns off, the signal (e.g., L-level signal CK1) input to wiring 112 is often supplied to wiring 111 via switch 11_1. Thus, signal OUT becomes L-level. However, it is not limited to this, and it is possible to supply an L-level signal or voltage V1 to wiring 111. Before switch 11_1 turns off, the signal (e.g., L-level signal CK1) input to wiring 112 is often supplied to wiring 111 via switch 11_1. Thus, signal OUT becomes L-level. However, it is not limited to this, and it is possible to supply an L-level signal or voltage V1 to wiring 111. Before switch 11_1 turns off, the signal (e.g., L-level signal CK1) input to wiring 112 is often supplied to wiring 111 via switch 11_1. Thus, signal OUT becomes L-level. However, it is not limited to this, and it is possible to supply an L-level signal or voltage V1 to wiring 111.

[0087] During periods D1 and E1 of period T1, as shown in FIG. 2(B), switch 11_1 and switch 11_2 remain off. Therefore, as shown in FIG. 2(C), path 2 1_1 and path 21_2 remain non-conductive. Thus, wiring 111 and wiring 11 2 become non-conductive, so the signal input to wiring 112 is not supplied to wiring 111 and remains as it is. Therefore, signal OUT remains at L-level.

[0088] Next, the operation during period T2 will be described. During period T2, switch 11_1 turns off , and switch 11_2 turns on or off.

[0089] During period A2 of period T2, as shown in FIG. 2(F), switch 11_1 turns off , and switch 11_2 turns on. Therefore, as shown in FIG. 2(G), path 21_1 becomes non-conductive, and path 21_2 becomes conductive. Then, the signal input to wiring 112 (e.g., signal CK1 at L level) is supplied to wiring 111 via switch 11_2 . Therefore, signal OUT becomes L level.

[0090] During period B2 of period T2, as shown in FIG. 2(F), switch 11_1 remains off , and switch 11_2 remains on. Therefore, as shown in FIG. 2(G), path 21_1 remains non-conductive, and path 21_2 remains conductive. Then, the signal input to wiring 112 (e.g., signal CK1 at H level) is supplied to wiring 111 via switch 11_2. Therefore, signal OUT becomes H level.

[0091] During period C2 of period T2, as shown in FIG. 2(B), switch 11_1 remains off , and switch 11_2 turns off. Therefore, as shown in FIG. 2(C), path 21_ 1 remains non-conductive, and path 21_2 becomes non-conductive. Then, wiring 111 and wiring 112 become non-conductive, so the signal input to wiring 112 (e.g., signal at L level CK1) is not supplied to wiring 111.

[0092] Note that in period C2 of period T2, the timing when switch 11_2 turns off is often later than the timing when signal CK1 becomes L level. Therefore, before switch 11_2 turns off, the signal input to wiring 112 (e.g., signal CK1 at L level) is switched It is often supplied to wiring 111 via switch 11_2. Therefore, signal OUT becomes the L level. However, it is not limited to this, and it is possible to supply an L-level signal or voltage V1 to wiring 111. However, it is not limited to this, and it is possible to supply an L-level signal or voltage V1 to wiring 111. It is possible.

[0093] During period D2 and period E2 of period T2, as shown in FIG. 2(B), switches 11_1 and 11_2 remain off. Therefore, as shown in FIG. 2(C), paths 2 1_1 and path 21_2 remain non-conductive. Therefore, wiring 111 and wiring 11 2 become non-conductive, so the signal input to wiring 112 is not supplied to wiring 111 and remains as it is. Therefore, signal OUT remains at the L level.

[0094] As described above, by switching the period during which each switch is turned on, the number of times the switch is turned on can be reduced, or the time the switch is turned on can be shortened. Therefore, it is possible to suppress the characteristic degradation of elements or circuits used as switches. Therefore, it is possible to suppress the characteristic degradation of elements or circuits used as switches, and various merits can be obtained. For example, when wiring 111 has a function as a gate signal line or a scanning line, or when wiring 111 is connected to a pixel, the video signal held by the pixel may be affected by the waveform of signal OUT. For example, when the potential of signal OUT does not rise to V2, the time the transistor (e.g., a selection transistor or a switching transistor) in the pixel is turned on becomes short. As a result, insufficient writing of the video signal to the pixel may occur, and the display quality may deteriorate. Or, signal OU By suppressing the characteristic degradation of elements or circuits used as switches, various merits can be obtained. For example, when wiring 111 has a function as a gate signal line or a scanning line, or when wiring 111 is connected to a pixel, the video signal held by the pixel may be affected by the waveform of signal OUT. For example, when the potential of signal OUT does not rise to V2, the time the transistor (e.g., a selection transistor or a switching transistor) in the pixel is turned on becomes short. As a result, insufficient writing of the video signal to the pixel may occur, and the display quality may deteriorate. Or, signal OUT

[0095] Or, by being able to suppress the characteristic degradation of elements or circuits used as switches, various merits can be obtained. For example, when wiring 111 has a function as a gate signal line or a scanning line, or when wiring 111 is connected to a pixel, the video signal held by the pixel may be affected by the waveform of signal OUT. For example, when the potential of signal OUT does not rise to V2, the time the transistor (e.g., a selection transistor or a switching transistor) in the pixel is turned on becomes short. As a result, insufficient writing of the video signal to the pixel may occur, and the display quality may deteriorate. Or, signal OUT Or, by being able to suppress the characteristic degradation of elements or circuits used as switches, various merits can be obtained. For example, when wiring 111 has a function as a gate signal line or a scanning line, or when wiring 111 is connected to a pixel, the video signal held by the pixel may be affected by the waveform of signal OUT. For example, when the potential of signal OUT does not rise to V2, the time the transistor (e.g., a selection transistor or a switching transistor) in the pixel is turned on becomes short. As a result, insufficient writing of the video signal to the pixel may occur, and the display quality may deteriorate. Or, signal OUT is connected to a pixel, the video signal held by the pixel may be affected by the waveform of signal OUT. For example, when the potential of signal OUT does not rise to V2, the time the transistor (e.g., a selection transistor or a switching transistor) in the pixel is turned on becomes short. As a result, insufficient writing of the video signal to the pixel may occur, and the display quality may deteriorate. Or, signal OUT If the potential does not rise to V2, the time the transistor (e.g., a selection transistor or a switching transistor) in the pixel is turned on becomes short. As a result, insufficient writing of the video signal to the pixel may occur, and the display quality may deteriorate. Or, signal OU For example, a selection transistor or a switching transistor) is turned on becomes short. As a result, insufficient writing of the video signal to the pixel may occur, and the display quality may deteriorate. Or, signal OUT results in insufficient writing of the video signal to the pixel, and the display quality may deteriorate. Or, signal OU When the fall time and rise time of T become long, there may be a case where a video signal is written to pixels belonging to another row instead of the selected row. As a result, the display quality deteriorates. Or, when the fall time of signal OUT varies, the influence of feed-through on the video signal held by the pixel may vary. As a result, display non-uniformity occurs. However, the semiconductor device of the present embodiment can suppress deterioration of the characteristics of the element or circuit used as the switch. Therefore, since the potential of signal OUT can be raised to V2, the on-time of the transistor included in the pixel can be lengthened . As a result, since the video signal can be written to the pixel in sufficient time, the display quality can be improved

[0096] . Or, since the fall time and rise time of signal OUT can be shortened, it is possible to prevent a video signal from being written to pixels belonging to another row instead of the pixels belonging to the selected row . As a result, the display quality can be improved . Or, since the variation in the fall time of signal OUT can be suppressed, the variation in the influence of feed-through on the video signal held by the pixel can be suppressed . Therefore, display non-uniformity can be suppressed . In addition, in period T1, period B1 can be called the selection period, and periods A1, C1, D1, and period E1 can be called non-selection periods. Similarly, in period T2, period B 2 can be called the selection period, and periods A2, C2, D2, and period E2 can be called non-selection periods .

[0097]

[0098] During period T1, the periods when switch 11_1 is on (periods A1 and A2) are referred to as the first period, and the periods when switch 11_1 is off (periods C1, D1, and period E1) can be referred to as the second period. Similarly, during period T2, periods A2 and period B2 can be referred to as the third period, and periods C2, D2, and period E2 can be referred to as the fourth period.

[0099] Note that period T1 and period T2 are referred to as the frame period, and periods A1 - E1 and periods A2 - E2 can be referred to as sub - periods, or one - gate selection periods.

[0100] Note that a period or a sub - period can be replaced with a step, a process, or an operation, etc. It is possible.

[0101] Note that during period T1, before period A1, periods D1 and E1 can be repeatedly arranged in sequence. Similarly, during period T2, before period A2, periods D2 and E2 can be repeatedly arranged in sequence. In such a case, the time from the start time of period T1 to the start time of period A1 and the time from the start time of period T2 to the start time of period A2 are preferably approximately equal. However, it is not limited to this.

[0102] Note that as shown in FIG. 1(C), switch 11_1 and switch 11_2 can be on during the same period. In this case, as shown in FIG. 1(D), path 21_1 and path 21_2 are in a conductive state during the same period. Therefore, the signal input to wiring 112 is supplied to wiring 111 via switch 11_1 and switch 11_2. However, it is not limited to this.

[0103] As shown in FIG. 1E, the semiconductor device includes switches 11_1 to 11_N (N is 2 or more). It is possible to have multiple switches, each of which is a natural number above. _N is connected between the wiring 111 and the wiring 112. The switches 11_1 to 11_N are It has the same function as the switch 11_1 or the switch 11_2. As shown in FIG. 1, there are paths 21_1 to 21_N between the wiring 111 and the wiring 112. There is.

[0104] In addition, when the semiconductor device has N switches, as shown in FIG. For example, in the timing chart of FIG. The intervals T1 to TN are arranged in order. However, this is not limited to this. In this embodiment, It is possible to arrange the periods T1 to TN in various orders. It is possible to omit any of the periods T1 to TN. For example, the period Ti (i is any one of 1 to N) is divided into periods Ai to Ei. Each of the periods Ai to Ei can have a plurality of sub-periods. In the same manner as in the periods A2 to E2, the switches 11_1 to 11_N (for example, For example, switches 11_1 to 11_i-1 and switches 11_i+1 to 11_N are turned off. Then, in periods Ai and Bi of period Ti, switch 11_i is turned on. , during periods Ci, Di, and Ei of period Ti, the switch 11_i is turned off.

[0105] Note that by making N large, the number of times each switch is turned on, or the number of times each The time for the switch to turn on can be reduced. However, if N is too large, the number of switches will increase too much, and the circuit scale will become large. Therefore, N is preferably 6 or less . More preferably, it is preferably 4 or less. Even more preferably, it is preferably 3 or 2. However, it is not limited thereto.

[0106] As shown in FIG. 1(G), the wiring 112 can be divided into a plurality of wirings such as wirings 112A to 112B. And the switch 11_1 can be connected between the wiring 111 and the wiring 112A, and the switch 11_2 can be connected between the wiring 111 and the wiring 112B. The wirings 112A to 112B can be connected to various other wirings or various elements.

[0107] Similar to FIG. 1(G), in FIG. 1(E) as well, the wiring 112 can be divided into a plurality of wirings.

[0108] (Embodiment 2) In this embodiment, an example of a semiconductor device is shown. The semiconductor device of this embodiment can have the semiconductor device described in Embodiment 1. In particular, the configuration when, for example, a transistor is used as the switch included in the semiconductor device described in Embodiment 1 will be described. However, it is not limited thereto, and various elements or various circuits can be used as the switch. Note that the description of the content described in Embodiment 1 is omitted. Note that the content of this embodiment can be appropriately combined with the content described in Embodiment 1.

[0109] ​​​​​First, the semiconductor device of the present embodiment will be described with reference to FIG. 4(A). FIG. 4(A) The semiconductor device has a circuit 100. The circuit 100 has the same configuration as that in the case where a transistor is used as a switch in the configuration described in Embodiment 1. In FIG. 4(A), a transistor 101_1 is used as the switch 11_1 in FIG. 1(A), and the configuration in the case where a transistor 101_2 is used as the switch 11_ 2 is shown. Therefore, the transistor 101_1 has the same function as the switch 11_1, and the transistor 101_2 has the same function as the switch 11_2. However, it is not limited thereto, and in the configuration described in Embodiment 1, a transistor can be used as a switch. Alternatively, as the switch a CMOS switch or the like can be used. Note that the transistors 101_1 and 101_2 are assumed to be N-channel type. An N-channel type transistor is assumed to turn on when the potential difference (Vgs) between the gate and the source exceeds the threshold voltage (Vth). However, it is not limited thereto, and the transistor 101_1 and / or the transistor 101_2 can be P-channel type. A P-channel type transistor is assumed to turn on when the potential difference (Vg

[0110] s) between the gate and the source is lower than the threshold voltage (Vth). Next, the connection relationship of the semiconductor device in FIG. 4(A) will be described. The first terminal of the transistor 101_1 is connected to the wiring 112, and the second terminal of the transistor 101_1 is connected to the wiring 111. The first terminal of the transistor 101_2 is connected to the wiring 112, and the transist or 101_2 has the same function as the switch 11_2. However, it is not limited thereto, and in the configuration described in Embodiment 1, a transistor can be used as a switch. Alternatively, as the switch s) between the gate and the source is lower than the threshold voltage (Vth).

[0111] Next, the connection relationship of the semiconductor device in FIG. 4(A) will be described. The first terminal of the transistor 101_1 is connected to the wiring 112, and the second terminal of the transistor 101_1 is connected to the wiring 111. The first terminal of the transistor 101_2 is connected to the wiring 112, and the transist or 101_2 is connected to the wiring 111. The second terminal of transistor 101_2 is connected to wiring 111.

[0112] Note that the connection point between the gate of transistor 101_1 and circuit 10 is denoted as node n1, and the connection point between the gate of transistor 101_2 and circuit 10 is denoted as node n2. Note that nodes n1 and n2 can be referred to as wiring.

[0113] Next, the functions of transistor 101_1 and transistor 101_2 will be described. do.

[0114] Transistor 101_1 has a function of controlling the timing of supplying the potential of wiring 112 to wiring 111 according to the potential of node n1. For example, when a voltage (e.g., voltage V1 or voltage V2) is supplied to wiring 112, transistor 101_1 has a function of controlling the timing of supplying the voltage supplied to wiring 112 to wiring 111 according to the potential of node n1. Another example is when a signal (e.g., signal CK1) is input to wiring 112. Transistor 101_1 has a function of controlling the timing of supplying the signal input to wiring 112 to wiring 111 according to the potential of node n1. In such a case, when signal CK1 is at the L level, transistor 101_1 has a function of controlling the timing of supplying the L-level signal CK1 to wiring 111. Or, transistor 101_1 has a function of controlling the timing when signal OUT becomes the L level. Or, when signal CK1 is at the H level, transistor 101_1 has a function of controlling the timing of supplying the H-level signal CK1 to wiring 111. Or, transistor 101_1 has a function of controlling the timing when signal OUT is at the H level. at the L level, transistor 101_1 has a function of controlling the timing of supplying the L-level signal CK1 to wiring 111. Or, transistor 101_1 has a function of controlling the timing when signal OUT becomes the L level. Or, when signal CK1 is at the H level, transistor 101_1 has a function of controlling the timing of supplying the H-level signal CK1 to wiring 111. Or, transistor 101_1 has a function of controlling the timing when signal OUT is at the H level. at the L level, transistor 101_1 has a function of controlling the timing of supplying the L-level signal CK1 to wiring 111. Or, transistor 101_1 has a function of controlling the timing when signal OUT becomes the L level. Or, when signal CK1 is at the H level, transistor 101_1 has a function of controlling the timing of supplying the H-level signal CK1 to wiring 111. Or, transistor 101_1 has a function of controlling the timing when signal OUT is at the H level. becomes the L level. Or, when signal CK1 is at the H level, transistor 101_1 has a function of controlling the timing of supplying the H-level signal CK1 to wiring 111. Or, transistor 101_1 has a function of controlling the timing when signal OUT is at the H level. at the H level, transistor 101_1 has a function of controlling the timing of supplying the H-level signal CK1 to wiring 111. Or, transistor 101_1 has a function of controlling the timing when signal OUT becomes the H level. Or, transistor 101_1 has a function of controlling the timing when signal OUT is at the H level. It has a function of controlling the timing to turn on. At this time, node n1 can be in a floating state. In this case, transistor 101_1 has a function of raising the potential of node n1 in response to the rise of the potential of wiring 111. Or, transistor 101_ 1 has a function of performing a bootstrap operation. Or, transistor 101_1 has a function of controlling whether to set the potential state of signal OUT by turning on or off according to the signal input to the gate.

[0115] Transistor 101_2 has a function of controlling the timing to supply the potential of wiring 112 to wiring 111 according to the potential of node n2. For example, when a voltage (e.g., voltage V1 or voltage V2) is supplied to wiring 112, transistor 101_2 has a function of controlling the timing to supply the voltage supplied to wiring 112 to wiring 111 according to the potential of node n2. As another example, when a signal (e.g., signal CK1) is input to wiring 112, transistor 101_2 has a function of controlling the timing to supply the signal input to wiring 112 to wiring 111 according to the potential of node n2. In such a case, when signal CK1 is at the L level, transistor 101_2 has a function of controlling the timing to supply the L-level signal CK1 to wiring 111. Or, transistor 101_2 has a function of controlling the timing when signal OUT becomes the L level. Or, when signal CK1 is at the H level, transistor 101_2 has a function of controlling the timing to supply the H-level signal CK1 to wiring 111. Or, transistor 101_2 has a function of controlling the timing when signal OUT becomes the H level. At this time, node n2 can be in a floating state. ​​​​​​​​​​​​ This is possible. In this case, transistor 101_2 has the function of raising the potential of node n2 in response to the rise in the potential of wiring 111. Or, transistor 101_ 2 has the function of performing a bootstrap operation. Or, transistor 101_1 has the function of controlling whether to set the potential state of signal OUT by turning on or off in response to the signal input to the gate.

[0116] As shown in FIG. 4(B), the semiconductor device of the present embodiment may have circuit 10. For example, circuit 10 may be connected to wiring 113, wiring 114, wiring 115_1, wiring 11 5_2, wiring 116, wiring 117, the gate of transistor 101_1, the gate of transistor 10 1_2, and / or wiring 111. However, it is not limited thereto. Depending on the configuration of circuit 10, circuit 10 may be connected to other wiring or other nodes. Or, circuit 10 may not be connected to wiring 113, wiring 114, wiring 115_1, wiring 115_2 , wiring 116, wiring 117, the gate of transistor 101_1, the gate of transistor 101_2 , and / or wiring 111.

[0117] Circuit 10 often has one or two or more transistors. The polarities of these transistors are often the same as those of transistors 101_1 to 101_2, and are often N-channel type. However, it is not limited thereto, and circuit 10 may have P-channel type transistors. Or, circuit 10 may have N-channel type transistors and P-channel type transistors. That is, circuit 10 may be a CMOS circuit. ​

[0118] From the wiring 111, a signal OUT is output in the same manner as in the first embodiment. The wiring 1 12 is assumed to receive a signal CK1 in the same manner as in the first embodiment. When referring to the signal CK 2, the signal CK2 is often an inverted signal of the signal CK1 or a signal whose phase is shifted from the signal CK1 by 1 80°. Assume that a voltage V2 is supplied to the wiring 113 . The voltage V2 can function as a power supply voltage, a reference voltage, or a positive power supply voltage. Therefore, the wiring 113 can function as a power supply line. A signal is applied to the wiring 114 SP is assumed to be input. The signal SP can function as a start signal . Therefore, the wiring 114 can function as a signal line. For example, in a configuration having a plurality of semiconductor devices, when the wiring 114 is connected to the wiring 11 1 of a semiconductor device in another stage (for example, the previous stage), the signal SP can function as a selection signal, a transfer signal, a start signal, a reset signal, a gate signal, or a scan signal. In this case, the wiring 114 can function as a gate signal line or a scan line. Assume that a signal is applied to the wiring 115_1 SEL1 is input. The signal SEL1 repeats between the H level and the L level every certain period (for example, every frame period ) and can function as a clock signal, a selection signal, or a control signal . Therefore, the wiring 115_1 can function as a signal line. Assume that a signal is applied to the wiring 115_2 SEL2 is input. The signal SEL2 is often an inverted signal of the signal SEL1 or a signal whose phase is shifted from the signal SEL1 by 180° . Therefore, the wiring 115_2 can function as a signal line. The wiring 11 Let it be assumed that a signal RE is input to 6. The signal RE functions as a reset signal. Thus, the wiring 116 can function as a signal line. In particular, , assume that a plurality of semiconductor devices are connected. In this case, if the wiring 116 is connected to the wiring 111 of a semiconductor device in another stage (for example, the next stage ), the signal RE can function as a selection signal, a transfer signal, , a start signal, a reset signal, a gate signal, or a scan signal. In this case, the wiring 116 can function as a gate signal line or a scan line. Let it be assumed that a voltage V1 is supplied to the wiring 117. The voltage V1 can function as a power supply voltage, a reference voltage, , a ground voltage, or a negative power supply voltage. Thus, the wiring 11 7 can function as a power supply line. However, it is not limited to this, and various signals, various voltages, or various currents can be supplied to the wiring 111 , the wiring 112, the wiring 113, the wiring 114, the wiring 115_1, the wiring 115_2, the wiring 116 , and the wiring 117.

[0119] Note that the signal CK1 or the signal CK2 can be balanced or unbalanced (also referred to as non - balanced). Similarly, the signal SEL1 or the signal SEL2 can be balanced or unbalanced (also referred to as non - balanced).

[0120] The circuit 10 controls the timing of supplying a signal or a voltage, etc. to the node n1, the node n2, and / or the wiring 111 according to the voltage V1, the signal CK2, the signal SP, the signal SEL1, the signal SEL2, the signal RE , the potential of the node n1, the potential of the node n2, and / or the signal OUT. ​​​has the function to perform. Or, circuit 10 has the voltage V1, signal CK2, signal SP, signal SEL1 , signal SEL2, signal RE, voltage V1, the potential of node n1, the potential of node n2, and / or has the function to control the potential of node n1, the potential of node n2, and / or the potential of wiring 11 in response to signal OUT. For example, circuit 10 has the function to supply a signal or voltage V2 at H level to node n1 and / or node n2. Or, circuit 10 has the function to supply a signal or voltage V1 at L level to node n1, node n2, and / or wiring 111. Or, circuit 10 has the function not to supply a signal or voltage etc. to node n1 and / or node n2. Or, circuit 10 has the function to raise the potential of node n1 and / or the potential of node n2. Or, circuit 10 has the function to decrease or maintain the potential of node n1, the potential of node n2, and / or the potential of wiring 111. Or, circuit 10 has the function to make node n1 and / or node n2 in a floating state. However, without being limited thereto, circuit 10 can have various other functions. Or, circuit 10 does not necessarily have all of the above functions. Next, an example of the operation of this embodiment will be described. Here, as an example, the operation of the semiconductor device in FIG. 4(B) will be described with reference to the timing chart in FIG. 4(C), FIGS. 5(A) to 5( E), and FIGS. 6(A) to 6(E). The timing chart in FIG. 4(C) shows signal CK1, signal CK2, signal SP, signal RE, the potential of node n1 (Va1) , the potential of node n2 (Va2), and signal OUT. Note that the timing chart in FIG. 2(A)

[0121] Next, an example of the operation of this embodiment will be described. Here, as an example, the operation of the semiconductor device in FIG. 4(B) will be described with reference to the timing chart in FIG. 4(C), FIGS. 5(A) to 5( E), and FIGS. 6(A) to 6(E). The timing chart in FIG. 4(C) shows signal CK1, signal CK2, signal SP, signal RE, the potential of node n1 (Va1) , the potential of node n2 (Va2), and signal OUT. Note that the timing chart in FIG. 2(A) The parts common to the chart are omitted from the description. Note that the operation of the semiconductor device in Fig. 4(B) can be applied to the content described in this embodiment or the content described in other embodiments. It is possible.

[0122] First, in period A1, as shown in Fig. 5(A), the signal SP becomes the H level, the signal SEL1 becomes the H level, and the signal SEL2 becomes the L level. Therefore, circuit 10 supplies the H-level signal SP or voltage V2 to node n1. Then, circuit 10 raises the potential of node n1. After that, when the potential of node n1 reaches V1 + Vth101_1 (Vth101_1: threshold voltage of transistor 101_1) + Vx, transistor 101_1 turns on. At this time, Vx is a value greater than 0. Therefore, wiring 112 and wiring 111 become conductive through transistor 101_1, so the L-level signal CK1 is supplied from wiring 112 to wiring 111 through transistor 101_1. As a result, the signal OUT becomes the L level. After that, the potential of node n1 further rises. However, since the supply of voltage or signal from circuit 10 to node n1 stops, circuit 10 and node n1 become non-conductive. As a result, node n1 becomes a floating state, and the potential of node n1 is maintained at V1 + Vth101_1 + Vx.

[0123] Note that in period A1, circuit 10 can supply a signal or voltage V2 of the L level to node n2.

[0124] Note that in period A1, circuit 10 can supply a signal or voltage V2 of the L level to wiring 111.

[0125] Next, in period B1, as shown in FIG. 5(B), signal SP becomes the L level, and signal S EL1 remains at the H level, and signal SEL2 remains at the L level. Therefore, circuit 1 0 does not supply a voltage or a signal or the like to node n1. Therefore, node n1 remains in a floating state, and the potential of node n1 remains at V1 + Vth101_1 + Vx becomes. That is, since transistor 101_1 remains on, wiring 112 and wiring 111 remain in a conductive state via transistor 101_1. At this time, signal CK1 is L rises from the level to the H level, so the potential of wiring 111 starts to rise. Then, node Since n1 remains in a floating state, the potential of node n1 is between the gate of transistor 101_1 and rises due to the parasitic capacitance between the second terminals. This is a so-called bootstrap operation. In this way, by the potential of node n1 rising to V2 + Vth101_1 + Vx , it becomes possible to raise the potential of wiring 111 to V2. In this way, signal OU T becomes the H level.

[0126] Note that in period B1, circuit 10 can supply a signal or voltage V2 of the L level to node n2.

[0127] Also, in period B1, circuit 10 can refrain from supplying a signal or voltage or the like to wiring 111.

[0128] Next, in period C1, as shown in FIG. 5(C), signal RE becomes the H level. Therefore , circuit 10 supplies a signal or voltage V1 of the L level to node n1, node n2, and / or wiring 111. Then, the potential of node n1, the potential of node n2, and / or the wiring​​ The potential of the transistor 101_1 and the transistor 101_2 is V1. Since the signal 1_2 is turned off, the wiring 112 and the wiring 111 are not electrically connected to each other. OUT becomes L level.

[0129] In the period C1, the potential of the node n1 decreases to the L level. It is possible to set the timing when CK1 drops to L level earlier. Then, as shown in FIG. 5(E), the signal CK1 at L level is output from the wiring 112 to the transistor. The potential can be supplied to the wiring 111 through the transistor 101_1. The channel width of 1_1 is, for example, a transistor other than the transistor 101_1. In some cases, the channel width of the wiring 111 is often larger than that of other transistors. In other words, the fall time of the signal OUT can be shortened. Therefore, in order to reduce the potential of the wiring 111, the circuit 10 needs to output an L-level signal or When the voltage V1 is supplied to the wiring 111, and when the signal CK1 at the L level is supplied to the transistor When the signal is supplied to the wiring 111 through the first input 101_1, or when the signal is supplied to the circuit 10 through the first input 101_2, the signal is at an L level. A voltage V1 is supplied to the wiring 111, and a signal CK1 of L level is supplied to the transistor from the wiring 112. There are three patterns: one in which the power is supplied to the wiring 111 via the power supply 101_1; and one in which the power is supplied to the wiring 111 via the power supply 101_2.

[0130] Next, in periods D1 and E1, as shown in FIG. 5(D), the circuit 10 outputs a voltage V A signal of 1 or L level is supplied to the node n1, the node n2, and / or the wiring 111. Then, the potential of the node n1, the potential of the node n2, and / or the potential of the wiring 111 are V1 remain as they are. Therefore, transistors 101_1 and 101_2 are off and remain so, so that wiring 112 and wiring 111 remain in a non-conductive state. And signal O UT remains at the L level.

[0131] Next, in period A2, as shown in FIG. 6(A), signal SP becomes the H level, signal S EL1 becomes the L level, and signal SEL2 becomes the H level. Therefore, circuit 10 supplies the H level signal SP or voltage V2 to node n2. And circuit 10 raises the potential of node n2. After that, when the potential of node n2 reaches V1 + Vth101_2 (Vth10 1_2: threshold voltage of transistor 101_2) + Vx, transistor 1 01_2 turns on. At this time, Vx is a value greater than 0. Therefore, wiring 112 and wiring 111 become conductive through transistor 101_2, so that the L level signal C K1 is supplied from wiring 112 to wiring 111 through transistor 101_2. As a result, signal OUT becomes the L level. After that, the potential of node n2 further rises. However, since the supply of voltage or signal from circuit 10 to node n2 stops, circuit 10 and node n2 become non-conductive. As a result, node n2 becomes a floating state, and the potential of node n2 is maintained at V1 + Vth101_2 + Vx. In addition, in period A2, circuit 10 can supply a signal or voltage V2 at the L level to node n1.

[0132] In addition, in period A2, circuit 10 can supply a signal or voltage V2 at the L level to wiring 111.

[0133]

[0134] ​​​​​​ Next, in period B2, as shown in FIG. 6(B), the signal SP becomes the L level, and the signal S EL1 remains at the L level, and the signal SEL2 remains at the H level. Therefore, circuit 1 0 does not supply a voltage or a signal to the node n2. Therefore, the node n2 remains in a floating state, and the potential of the node n2 remains at V1 + Vth101_2 + Vx . That is, since the transistor 101_2 remains on, the wiring 112 and the wiring 111 remain in a conductive state via the transistor 101_2. At this time, the signal CK1 is L and rises from the level to the H level, so the potential of the wiring 111 starts to rise. Then, the node n2 remains in a floating state, so the potential of the node n2 is between the gate of the transistor 101_2 and the second terminal and rises due to the parasitic capacitance. This is a so-called bootstrap operation. In this way, the potential of the node n2 rises to V2 + Vth101_2 + Vx, whereby the potential of the wiring 111 can rise to V2. In this way, the signal OU T becomes the H level.

[0135] Note that in period B2, the circuit 10 can supply a signal or voltage V2 of the L level to the node n1.

[0136] Note that in period B2, the circuit 10 can refrain from supplying a signal or voltage to the wiring 111.

[0137] Next, in period C2, as shown in FIG. 6(C), the signal RE becomes the H level. Therefore , the circuit 10 supplies a signal or voltage V2 of the L level to the node n1, the node n2, and / or the wiring 111. Then, the potential of the node n1, the potential of the node n2, and / or the wiring​​ The potential of the transistor 101_1 and the transistor 101_2 is V1. Since the signal 1_2 is turned off, the wiring 112 and the wiring 111 are not electrically connected to each other. OUT becomes L level.

[0138] In the period C2, the signal CK1 becomes higher than the timing at which the potential of the node n2 decreases. It is possible to set the timing for the signal to decrease to the L level earlier. As shown in FIG. 6E, the signal CK1 at the L level is supplied from the wiring 112 to the transistor 10. The signal can be supplied to the wiring 111 through the transistor 101_2. For example, when other transistors are included, the channel width is set to be smaller than the channel width of the other transistors. Since the potential of the wiring 111 is often large, the potential of the wiring 111 can be quickly reduced. The fall time of OUT can be shortened. Therefore, the potential of the wiring 111 is reduced. In order to achieve this, for example, when the circuit 10 supplies an L-level signal or voltage V1 to the wiring 111, , the L-level signal CK1 is input from the wiring 112 to the wiring 111 via the transistor 101_2. When the signal V1 is supplied to the wiring 111, or when the circuit 10 supplies a signal or voltage V1 of L level to the wiring 111, Furthermore, the signal CK1 at the L level is input from the wiring 112 to the wiring 111 via the transistor 101_2. In some cases, they are supplied to

[0139] Next, in periods D2 and E2, as shown in FIG. 6(D), the circuit 10 supplies a voltage V A signal of 1 or L level is supplied to the node n1, the node n2, and / or the wiring 111. Then, the potential of the node n1, the potential of the node n2, and / or the potential of the wiring 111 are V1 remain as they are. Therefore, transistors 101_1 and 101_2 are off and remain so, thus keeping wiring 112 and wiring 111 in a non-conductive state. And signal O UT remains at the L level.

[0140] As described above, during period T1, transistor 101_2 turns off, and during period T2 transistor 101_1 turns off. Therefore, the number of times transistors 101_1 and 101_2 turn on, or the time for which transistors 101_1 and 101_2 turn on is reduced. Thus, degradation of the characteristics of transistors 1 01_1 and 101_2 can be suppressed.

[0141] As described above, the semiconductor device of this embodiment can suppress degradation of the characteristics of the transistors. Also, since the potential of the H level of signal OUT can be raised to V2, the on-time of the transistors included in the pixel can be lengthened. As a result, since a video signal can be written within a sufficient time in the pixel, the display quality can be improved. Or, since the fall time and rise time of signal OUT can be shortened, it is possible to prevent a video signal for a pixel belonging to another row from being written to the pixel belonging to the selected row. As a result, the display quality can be improved. Also since the variation in the fall time of signal OUT can be suppressed, the variation in the influence of feed-through on the video signal held by the pixel can be suppressed. Therefore, display non-uniformity can be suppressed. As a result, the display quality can be improved. Also since the variation in the fall time of signal OUT can be suppressed, the variation in the influence of feed-through on the video signal held by the pixel can be suppressed. Therefore, display non-uniformity can be suppressed. As a result, display non-uniformity can be suppressed.

[0142] Alternatively, in the semiconductor device of the present embodiment, the polarities of all transistors can be N-channel type or P -channel type. Therefore, compared with a CMOS circuit, the number of processes can be reduced, the yield can be improved, the reliability can be improved, or the cost can be reduced. In particular, when all transistors are N-channel type, including the pixel portion and the like, it is possible to use, for example, an amorphous semiconductor, a microcrystalline semiconductor, an organic semiconductor, or an oxide semiconductor as the semiconductor layer of the transistor. However, transistors using these semiconductors are often prone to deterioration. However, the semiconductor device of the present embodiment can suppress the deterioration of the transistor. .

[0143] Alternatively, even when the characteristics of the transistor deteriorate, it is not necessary to increase the channel width of the transistor so that the semiconductor device can operate. Therefore, the channel width of the transistor can be reduced. This is because the semiconductor device of the present embodiment can suppress the deterioration of the transistor.

[0144] Note that the circuit 10 can supply a signal or voltage V1 at the L level to the node n1 during the periods C1, D1, E1, A2, B2, C2, D2, and / or E2, and can also not supply a voltage or signal or the like to the node n1. However, it is not limited to this.

[0145] Note that the circuit 10 can supply a signal or voltage V1 at the L level to the node n2 during the periods A1, B1, C1, D1, E1, C2, D2, and / or E2, and can also not supply a voltage or signal or the like to the node n2. ​​​​​​​However, it is not limited to this.

[0146] Note that circuit 10 can supply an L-level signal or voltage V1 to wiring 111 during period A1, period C1, period D1, period E1, period A2, period C2, period D2, and / or period E2, and can also not supply a voltage or signal or the like to wiring 111. However, it is not limited to this. However, it is not limited to this.

[0147] Note that signals CK1 and CK2 can be unbalanced. FIG. 7(A) shows, as an example, a timing chart in a case where the period during which the signal is at the H level is shorter than the period during which the signal is at the L level within one cycle. By doing so, an L-level signal CK1 is supplied to wiring 111 during period C1 or period C2, so that the fall time of signal OUT can be shortened. Or, when wiring 111 is extended and arranged in the pixel portion, it is possible to prevent an improper video signal from being written into the pixel. However, it is not limited to this, and it is possible that the period during which the signal is at the H level is longer than the period during which the signal is at the L level within one cycle.

[0148] Note that a multiphase clock signal can be used in the semiconductor device of this embodiment. For example, when represented by n (n is a natural number), an n + 1-phase clock signal refers to n + 1 clock signals whose periods are shifted by 1 / (n + 1) cycle each. Or, any two of the multiphase clock signals can be input to wiring 112 and wiring 113, respectively. FIG. 7(B) shows, as an example, a timing chart in a case where a 3-phase clock signal is used in the semiconductor device. However, it is not limited to this.

[0149] ​​​​​​​​​​​Note that, the larger n is, the smaller the clock frequency becomes, so that power consumption can be reduced. However, if n is too large, the number of signals increases, so that the layout area may increase or the scale of the external circuit may increase. Therefore, it is preferable that n < 8. More preferably, it is preferable that n < 6. Even more preferably, it is preferable that n = 4 or n = 3. However, it is not limited thereto.

[0150] Note that, since the transistor 101_1 and the transistor 101_2 have the same function, the channel width of the transistor 101_1 and the channel width of the transistor 101_2 are preferably substantially equal. In this way, by making the transistor sizes substantially equal, the current supply capabilities of the transistors can be made substantially equal. Or, the degrees of deterioration of the transistors can be made substantially equal. Therefore, even if a plurality of transistors are switched and used, the waveforms of the signal OUT can be made substantially equal. However, it is not limited thereto, and the channel width of the transistor 101_1 and the channel width of the transistor 101_2 can be different.

[0151] Note that, when referring to the channel width of a transistor, this can be rephrased as the W / L (W: channel width, L: channel length) ratio of the transistor.

[0152] Note that, the transistor 101_1 and the transistor 101_2 can be turned on in the same period. For example, in the period B1 or the period B2, when the transistor 101_1 and the transistor 101_2 are turned on, only one of the transistors is turned on The potential of wiring 111 can be raised faster than in the case where it becomes N. Therefore, the rising time of signal OUT T can be shortened.

[0153] Note that, as shown in FIG. 8(A), wiring 112 can be divided into a plurality of wirings such as wirings 112A to 112B. Then, the first terminal of transistor 101_1 can be connected to wiring 112 A, and the first terminal of transistor 101_2 can be connected to wiring 112B. In addition, wirings 112A to 112B can be connected to other wirings, nodes, etc. as possible.

[0154] Note that, as in FIG. 8(A), also in FIGS. 4(A) to (B), wiring 112 can be divided into a plurality of wirings ( for example, wirings 112A to 112B).

[0155] Note that, as shown in FIG. 8(B), a capacitive element 121_1 can be connected between the gate and the second terminal of transistor 101_1, and a capacitive element 121_2 can be connected between the gate and the second terminal of transistor 101_2. By doing so, during the bootstrap operation, the potential of node n1 or the potential of node n2 is likely to rise. Therefore, the Vgs of transistor 101_1 and transistor 101_2 can be increased, and thus the channel width of these transistors can be reduced. Or, the falling time or the rising time of signal OUT can be shortened. However, it is not limited to this, and one of capacitive element 121_1 and capacitive element 121_2 can be omitted. Also, the capacitive element can be connected between the gate (node n1, node n2) of the transistor and the second terminal (wiring 1 ​​​​It is possible to connect to (12). Alternatively, as a capacitive element, for example, a MIS capacitor can be used.

[0156] Note that the material of one electrode of the capacitive element 121_1 and the capacitive element 121_2 is, for example, tra nsistor 101_1 and the same material as the gate of the transistor 101_2 is preferable. The material of the other electrode of the capacitive element 121_1 and the capacitive element 121_2 is the same as the source or drain of the transistor 101_1 and the transistor 101_2. It is preferable. By doing so, the layout area can be reduced. Also, the capacitance value can be increased. However, it is not limited to this. As the material of one electrode and the other electrode of the capacitive element 121_1 and the capacitive element 121_2, various materials can be used.

[0157] Note that the capacitance value of the capacitive element 121_1 and the capacitance value of the capacitive element 121_2 are preferably approximately equal. Alternatively, the area where one electrode and the other electrode of the capacitive element 121_1 overlap and the area where one electrode and the other electrode of the capacitive element 121_2 overlap are preferably approximately equal. By doing so, even when the transistors are switched and used, the Vgs of the transistor 101_1 and the Vgs of the transistor 101_2 can be made approximately equal. Therefore, the waveform of the signal OUT can be made approximately equal. However, it is not limited to this. The capacitance value of the capacitive element 121_1 and the capacitance value of the capacitive element 121_2 can be different. Alternatively, the area where one electrode and the other electrode of the capacitive element 121_1 overlap and the area where one electrode and the other electrode of the capacitive element 121_2 overlap can be different.​​​​ There is.

[0158] Note that, similar to FIG. 8(B), in FIGS. 4(A) to (B) and FIG. 8(A) as well, a capacitance element 121_1 can be connected between the gate and the second terminal of the transistor 101_1. There is. Or, a capacitance element 121_2 can be connected between the gate and the second terminal of the transistor 101_2. There is. Or, a capacitance element 121_2 can be connected between the gate and the second terminal of the transistor 101_2. It is possible to connect.

[0159] Note that, as shown in FIG. 8(C), the circuit 100 can have a plurality of transistors such as the transistors 101_1 to 101_N. The first terminals of the transistors 101_1 to 101_N are connected to the wiring 112, and the second terminals of the transistors 101_1 to 101_N are connected to the wiring 111. And the gates of the transistors 101_1 to 101_N are made the nodes n1 to nN, respectively. This configuration of FIG. 8(C) corresponds to the configuration in the case where a transistor is used as the switch in the first embodiment. Therefore, the transistors 101_1 to 101_N have the same function as the switches 11_1 to 11_N. Note that, as shown in FIG. 8(C), the circuit 100 can have a plurality of transistors such as the transistors 101_1 to 101_N. The first terminals of the transistors 101_1 to 101_N are connected to the wiring 112, and the second terminals of the transistors 101_1 to 101_N are connected to the wiring 111. And the gates of the transistors 101_1 to 101_N are made the nodes n1 to nN, respectively. This configuration of FIG. 8(C) corresponds to the configuration in the case where a transistor is used as the switch in the first embodiment. Therefore, the transistors 101_1 to 101_N have the same function as the switches 11_1 to 11_N. N are connected to the wiring 112, and the second terminals of the transistors 101_1 to 101_N are connected to the wiring 111. And the gates of the transistors 101_1 to 101_N are made the nodes n1 to nN, respectively. This configuration of FIG. 8(C) corresponds to the configuration in the case where a transistor is used as the switch in the first embodiment. Therefore, the transistors 101_1 to 101_N have the same function as the switches 11_1 to 11_N. And the gates of the transistors 101_1 to 101_N are made the nodes n1 to nN, respectively. This configuration of FIG. 8(C) corresponds to the configuration in the case where a transistor is used as the switch in the first embodiment. Therefore, the transistors 101_1 to 101_N have the same function as the switches 11_1 to 11_N. Note that, as shown in FIG. 8(C), the circuit 100 can have a plurality of transistors such as the transistors 101_1 to 101_N. The first terminals of the transistors 101_1 to 101_N are connected to the wiring 112, and the second terminals of the transistors 101_1 to 101_N are connected to the wiring 111. And the gates of the transistors 101_1 to 101_N are made the nodes n1 to nN, respectively. This configuration of FIG. 8(C) corresponds to the configuration in the case where a transistor is used as the switch in the first embodiment. Therefore, the transistors 101_1 to 101_N have the same function as the switches 11_1 to 11_N. Note that, as shown in FIG. 8(C), the circuit 100 can have a plurality of transistors such as the transistors 101_1 to 101_N. The first terminals of the transistors 101_1 to 101_N are connected to the wiring 112, and the second terminals of the transistors 101_1 to 101_N are connected to the wiring 111. And the gates of the transistors 101_1 to 101_N are made the nodes n1 to nN, respectively. This configuration of FIG. 8(C) corresponds to the configuration in the case where a transistor is used as the switch in the first embodiment. Therefore, the transistors 101_1 to 101_N have the same function as the switches 11_1 to 11_N.

[0160] Note that, the larger N is, the shorter the number of times each transistor is turned on or the time each transistor is turned on becomes. Therefore, deterioration of the transistor characteristics can be suppressed. However, if N is too large, the number of transistors increases, so the circuit scale becomes large. Therefore, it is preferable that N < 6. More preferably, it is preferable that N < 4. Even more preferably, it is preferable that N = 3 or N = 2. Note that, the larger N is, the shorter the number of times each transistor is turned on or the time each transistor is turned on becomes. Therefore, deterioration of the transistor characteristics can be suppressed. However, if N is too large, the number of transistors increases, so the circuit scale becomes large. Therefore, it is preferable that N < 6. More preferably, it is preferable that N < 4. Even more preferably, it is preferable that N = 3 or N = 2. Note that, the larger N is, the shorter the number of times each transistor is turned on or the time each transistor is turned on becomes. Therefore, deterioration of the transistor characteristics can be suppressed. However, if N is too large, the number of transistors increases, so the circuit scale becomes large. Therefore, it is preferable that N < 6. More preferably, it is preferable that N < 4. Even more preferably, it is preferable that N = 3 or N = 2. Note that, the larger N is, the shorter the number of times each transistor is turned on or the time each transistor is turned on becomes. Therefore, deterioration of the transistor characteristics can be suppressed. However, if N is too large, the number of transistors increases, so the circuit scale becomes large. Therefore, it is preferable that N < 6. More preferably, it is preferable that N < 4. Even more preferably, it is preferable that N = 3 or N = 2. Note that, the larger N is, the shorter the number of times each transistor is turned on or the time each transistor is turned on becomes. Therefore, deterioration of the transistor characteristics can be suppressed. However, if N is too large, the number of transistors increases, so the circuit scale becomes large. Therefore, it is preferable that N < 6. More preferably, it is preferable that N < 4. Even more preferably, it is preferable that N = 3 or N = 2.

[0161] Note that, similar to FIG. 8(C), in FIGS. 4(A) to (B) and FIGS. 8(A) to (B) as well, The circuit 100 has a plurality of transistors, namely transistors 101_1 to 101_N. This is possible. In particular, in FIG. 8(A), when the circuit 100 has a plurality of transistors, namely transistors 101_1 to 101_N, it is possible to divide the wiring 112 into N wirings. This is possible. In particular, in FIG. 8(B), when the circuit 100 has a plurality of transistors, namely transistors 101_1 to 101_N, it is possible to connect capacitor elements between the gates of transistors 101_1 to 101_ N and the second terminals of transistors 101_1 to 101_N, respectively. This is possible.

[0162] As shown in FIG. 8(D), transistor 101_1 can be replaced with a diode 101a_1 in which one terminal (hereinafter also referred to as the positive electrode) is connected to node n1 and the other terminal (hereinafter also referred to as the negative electrode) is connected to wiring 111. Similarly, transistor 101_2 can be replaced with a diode 101a_2 in which one terminal (hereinafter also referred to as the positive electrode) is connected to node n2 and the other terminal (hereinafter also referred to as the negative electrode) is connected to wiring 111. However, it is not limited thereto. As shown in FIG. 8(E), by connecting the first terminal of transistor 101_1 to node n1, transistor 101_1 can be configured in a diode-connected manner. Similarly, by connecting the first terminal of transistor 101_2 to node n2, transistor 101_2 can be diode-connected configured. As shown in FIGS. 8(D) to (E), FIGS. 4(A) to (B), and FIGS. 8(A) to (C), it is also possible to replace the transistor with a diode. Or, the transistor can be replaced with a diode. configured in a diode-connected manner. This is possible.

[0163] Note that, similar to FIGS. 8(D) to (E), in FIGS. 4(A) to (B) and FIGS. 8(A) to (C) as well, it is possible to replace the transistor with a diode. Or, the transistor can be replaced with a diode. can be configured in a diode-connected configuration.

[0164] As shown in FIG. 8(F), the output signal can be split into two. Therefore the semiconductor device can have a circuit 120. The circuit 120 has transistors 122_1 to 122_2. The circuit 120 has the same function as the circuit 100 The transistors 122_1 to 122_2 each have the same function as the transistors 1 01_1 to 101_2. The first terminal of the transistor 122_1 is connected to the wire 112, the second terminal of the transistor 122_1 is connected to the wiring 211, and the gate of the transistor 122_1 is connected to the node n1. The first terminal of the transistor 122_2 is connected to the wiring 112, the second terminal of the transistor 122_2 is connected to the wiring 211 and the gate of the transistor 122_2 is connected to the node n2. Thus, the transistor 101_1 and the transistor 122_1 are controlled at the same timing, and the transistor 101_2 and the transistor 122_2 are controlled at the same timing . Therefore, the signal output from the wiring 211 becomes H level or L level at substantially the same timing as the signal OUT.

[0165] When the signal output from the wiring 111 functions as a gate signal or a selection signal, the signal output from the wiring 211 can function as a transfer signal, a reset signal, or a gate signal, etc. In such a case, since the load of the wiring 111 is often larger than the load of the wiring 211, the channel width of the transistor 101_1 is larger than that of the transistor It is preferably larger than the channel width of transistor 122_1. Similarly, the channel width of transistor 102 _2 is preferably larger than the channel width of transistor 122_2 . However, it is not limited thereto.

[0166] Similar to FIG. 8(F), in FIGS. 4(A) to (B) and FIGS. 8(A) to (E) as well, the semiconductor device can split the output signal into two by having circuit 120 . And circuit 120 can have a plurality of transistors such as transistors 122_1 to 122_2 . In particular, in FIG. 8(C), when circuit 100 has a plurality of transistors such as transistors 101_1 to 101_N, circuit 120 can have N transistors .

[0167] Next, a specific example of circuit 10 will be described. First, referring to FIG. 9(A), the configuration when circuit 10 has circuit 200 will be described. Circuit 200 shows a part of circuit 10. Circuit 200 is connected to wiring 114, wiring 115_1, wiring 115_2, node n1, and / or , node n2. However, it is not limited thereto, and circuit 200 can be connected to other wiring or other nodes.

[0168] Circuit 200 often has one or two or more transistors. The polarities of these transistors are often the same as the polarities of transistors 101_1 to 101_2 and are often of the N-channel type. However, it is not limited thereto, and circuit 200 can have P-channel transistors . Or, circuit 200 can have N-channel transistors and a P-channel transistor. That is, circuit 200 can include C It can be a MOS circuit.

[0169] Circuit 200 controls the timing of supplying a signal or voltage to node n1 and / or node n2 according to signal SP, signal SEL1, signal SEL2, the potential of node n1, and / or the potential of node n2. In this way, circuit 200 has the function of controlling the potential of node n1 and / or the potential of node n2. For example, circuit 200 has the function of supplying a signal or voltage V2 of an H level to node n1 and / or node n2. Alternatively, circuit 200 has the function of supplying a signal or voltage V1 of an L level to node n1 and / or node n2. Alternatively, circuit 200 has the function of not supplying a signal or voltage or the like to node n1 and / or node n2. Alternatively, circuit 200 has the function of increasing the potential of node n1 and / or the potential of node n2. Alternatively, circuit 200 has the function of decreasing or maintaining the potential of node n1 and / or the potential of node n2. Alternatively, circuit 200 has the function of floating node n1 and / or node n2.

[0170] Here, an example of circuit 200 will be described with reference to FIG. 9(B). Circuit 200 includes a plurality of transistors such as transistors 201_1 to 201_2. The first terminal of transistor 2 01_1 is connected to wiring 115_1, the second terminal of transistor 201_1 is connected to the gate of transistor 101_1, and the gate of transistor 201_1 is connected to wiring 114. The first terminal of transistor 201_2 is connected to wiring 115_2 ​and the second terminal of transistor 201_2 is connected to the gate of transistor 101_2, and the gate of transistor 201_2 is connected to wiring 114. However, it is not limited to this, and various configurations can be used for circuit 200.

[0171] Transistors 201_1 and 201_2 preferably have the same polarity as transistors 101_1 and 101_2 and are N-channel type. However, it is not limited to this, and transistors 201_1 and / or transistor 201_2 can be P-channel type.

[0172] Transistor 201_1 has a function of controlling the conduction state between wiring 115_1 and node n1 according to the potential of wiring 114. Or, transistor 201_1 has a function of supplying the potential of wiring 115_1 to node n1 according to the potential of wiring 114. Or, transistor 201_1 has a function of turning on or off according to signal SP, or transistor 201_1 has a function of controlling whether signal SEL1 is input to transistor 101_1. Or transistor 201_1 has a function of controlling whether to set the potential state of signal OUT by turning on or off. Transistor 201_2 has a function of controlling the conduction state between wiring 115_2 and node n2 according to the potential of wiring 114. Or, transistor 201_2 has a function of supplying the potential of wiring 115_2 to node n2 according to the potential of wiring 114. Or, transistor 201_2 has a function of turning on or off according to signal SP, or transistor 201_2 It has a function of controlling whether or not the signal SEL2 is input to the transistor 101_2. Or the transistor 201_2 has a function of controlling whether or not to set the potential state of the signal OUT by turning on or off.

[0173] The operation of the semiconductor device in Fig. 9(A) will be described. Here, as an example, the case where the circuit configuration of the circuit 200 is the circuit configuration shown in Fig. 9(B) will be described. In the period A1, as shown in Fig. 10(A), since the signal SP becomes the H level, the transistor 201_1 and the transistor 201_2 turn on. Therefore, the H-level signal SEL1 is supplied from the wiring 11 5_1 to the node n1 via the transistor 201_1, and the L-level signal SE L2 is supplied from the wiring 115_2 to the node n2 via the transistor 201_2. Thus, the potential of the node n1 starts to rise, and the potential of the node n1 becomes V2. After that, when the potential of the node n1 rises from the potential of the wiring 114 (V2) to the value (V2 - Vth201_1) obtained by subtracting the threshold voltage (V th201_1) of the transistor 201_1, the transistor 201_1 turns off. Therefore, the node n1 becomes in a floating state while maintaining the potential at V2 - Vth201_1.

[0174] In the periods B1 to E1, since the signal SP becomes the L level, the transistor 201_1 and the transistor 201_2 turn off. Therefore, the wiring 115_1 and the node n1 become non-conductive, and the wiring 115_2 and the node n2 become non-conductive. Note that the schematic diagram of the semiconductor device in the period B1 is shown in Fig. 10(B), the schematic diagram of the semiconductor device in the period C1 is shown in Fig. 10(C), and the schematic diagrams of the semiconductor device in the periods D1 and E1 are shown in Fig. 10(D) ​​​​​​​ as shown in

[0175] Next, in period A2, as shown in FIG. 10(E), since the signal SP becomes the H level, transistors 201_1 and 201_2 turn on. Thus, the signal SEL1 of the L level is supplied from the wiring 115_1 to the node n1 via the transistor 201_1, and the signal SEL2 of the H level is supplied from the wiring 115_2 to the node n2 via the transistor 201_2. Thus, the potential of the node n1 becomes V1, and the potential of the node n2 starts to rise. After that, when the potential of the node n2 rises to a value (V2 - Vth201_2) obtained by subtracting the threshold voltage (Vth201_2) of the transistor 201_2 from the potential (V2) of the wiring 114, the transistor 201_2 turns off. Thus, the node n2 becomes in a floating state while maintaining the potential at V2 - Vth201_2. In periods B2 to E2, since the signal SP becomes the L level, the transistors 201_1 and 201_2 turn off. Thus, the wiring 115_1 and the node n1 become in a non-conductive state, and the wiring 115_2 and the node n2 become in a non-conductive state. Note that a schematic diagram of the semiconductor device in period B2 is shown in FIG. 10(F), a schematic diagram of the semiconductor device in period C2 is shown in FIG. 10(G), and schematic diagrams of the semiconductor device in periods D2 and E2 are shown in FIG. 10(H).

[0176] As described above, by configuring the circuit 10, any transistor of the circuit 100 can be selectively turned on or off. Also, even when turning off the transistor of the circuit 100, since a potential is applied to the gate of the transistor to be turned off from the circuit 10, the floating as shown in

[0177] As described above, by configuring the circuit 10, any transistor of the circuit 100 can be selectively turned on or off. Also, when turning off the transistor of the circuit 100, since a potential is applied to the gate of the transistor to be turned off from the circuit 10, the floating state can be avoided. It is possible to prevent the device from becoming idle.

[0178] Since the transistors 201_1 and 201_2 have the same function, The channel width of the transistor 201_1 and the channel width of the transistor 201_2 are It is preferable that the transistor sizes are roughly equal. By this, the current supply capacity can be made roughly equal. Therefore, the degree of polarization can be roughly equalized by switching transistors. In addition, the potential of the node n1 and the potential of the node n2 can be made approximately equal, so that the signal The waveform of the signal OUT can be roughly the same. However, this is not limited to this. The channel width of the transistor 201_1 and the channel width of the transistor 201_2 are different. It is possible.

[0179] The load of the transistor 201_1 (for example, node n1) is the transistor 101_1 Since the load of the transistor 201_1 is smaller than the load of the other transistor (for example, the wiring 111), The channel width is preferably smaller than the channel width of the transistor 101_1. The load of the transistor 201_2 (for example, node n2) is the load of the transistor 101_2. Since the load (e.g., the wiring 111) is often smaller than the channel of the transistor 201_2, The width of the channel is preferably smaller than the channel width of the transistor 101_2. However, the channel width of the transistor 201_1 is not limited to the above. Alternatively, the channel width of the transistor 201_2 can be larger than , may be larger than the channel width of transistor 101_2.

[0180] Note that, as shown in FIG. 9(C), when the circuit 100 has a plurality of transistors such as transistors 101_ 1 to 101_N, the circuit 200 can have a plurality of transistors such as transistors 2 01_1 to 201_N. The first terminals of the transistors 201_1 to 201_N are each connected to the wirings 115_1 to 115_N . The second terminals of the transistors 201_1 to 201_N are connected to the nodes n1 to nN . The gates of the transistors 201_1 to 201_N are connected to the wiring 114 .

[0181] Note that, as shown in FIG. 9(D), the wiring 114 can be divided into a plurality of wirings such as wirings 114A to 114B . Therefore, the wirings 114A to 114B can have the same function as the wiring 114. The gate of the transistor 201_1 is connected to the wiring 114A , and the gate of the transistor 201_2 is connected to the wiring 114B. In this case, signals with substantially the same waveform can be input to the wiring 114A and the wiring 114B respectively , or different signals can be input .

[0182] Note that, similar to FIG. 9(D), in FIG. 9(C) as well, the wiring 114 can be divided into a plurality of wirings .

[0183] Note that, as shown in FIG. 9(E), the first terminal of the transistor 201_1 and the first terminal of the transistor 2 01_2 can be connected to the same wiring. In an example of FIG. 9(E), the first terminals of the transistors 201_1 to 201_2 are connected to the wiring 115_1 . ​However, without being limited thereto, the first terminals of transistors 201_1 to 201_2 can also be connected to other various wirings. For example, the first terminals of transistors 201_1 to 201_ 2 can be connected to wiring 113 or the wiring to which signal CK2 is input, etc. is possible.

[0184] Note that, similar to FIG. 9(E), in FIGS. 9(C) to (D) as well, the first terminals of transistors 201_1 to 201_2 can be connected to the same wiring. In particular, in the case of FIG. 9(C), the first terminals of transistors 201_1 to 201_N can be connected to the same wiring. is possible.

[0185] Note that, as shown in FIG. 9(F), the first terminal of transistor 201_1 is connected to wiring 114, the second terminal of transistor 201_1 is connected to node n1, and the gate of transistor 201 _1 can be connected to wiring 115_1. The first terminal of transistor 201_2 is connected to wiring 114, the second terminal of transistor 201_2 is connected to node n2, and the gate of transistor 201_2 can be connected to wiring 115_2. In this case, assuming that in period T1, signal SEL1 is at the H level and signal SEL2 is at the L level, transistor 201_1 turns on and transistor 201_2 turns off. Thus, in period A1, the H-level signal SP is supplied from wiring 114 to node n1 via transistor 201_1, so the potential of node n1 rises. On the other hand, assuming that in period T2, signal SEL1 is at the L level and signal SEL2 is at the H level in period T2, transistor 201_1 turns off and transistor 201_2 turns on. If so, in period T2, signal SEL1 is at the L level and signal SEL2 is at the H level. Then transistor 201_1 turns off and transistor 201_2 turns on. It becomes. Therefore, in period A2, the signal SP at the H level is supplied from the wiring 114 to the node n2 via the transistor 201_2, so that the potential of the node n2 rises.

[0186] As shown in FIG. 11(A), a transistor 202_1 having a diode-connected configuration can be connected between the second terminal of the transistor 201_1 and the node n1. Similarly, a transistor 202_2 having a diode-connected configuration can be connected between the second terminal of the transistor 201_2 and the node n2. The first terminal of the transistor 202_1 is connected to the second terminal of the transistor 201_1, the second terminal of the transistor 202_1 is connected to the node n1, and the gate of the transistor 202_1 is connected to the second terminal of the transistor 201_1. The first terminal of the transistor 202_2 is connected to the second terminal of the transistor 201_2, the second terminal of the transistor 202_2 is connected to the node n2, and the gate of the transistor 202_2 is connected to the second terminal of the transistor 201_2. The transistors 201_1 and 201_2 can function as diodes. The transistor 201_1 has a function of preventing a decrease in the potential of the node n1 by becoming non-conductive. Similarly, the transistor 201_2 has a function of preventing a decrease in the potential of the node n2 by becoming non-conductive. However, it is not limited to this, and various elements or circuits can be connected between the second terminal of the transistor 201_1 and the node n1, and / or between the second terminal of the transistor 201_2 and the node n2. Or, the first terminal of the transistor 201_1 and the wiring 01_2 has a function of preventing a decrease in the potential of the node n2 by becoming non-conductive. Between the line 115_1 and / or between the first terminal of the transistor 201_2 and the wiring 115_2 It is also possible to connect various elements or circuits. For example, in FIG. 11(B) As shown, the transistor 202_1 can be connected between the first terminal of the transistor 201_1 and the wiring 1 15_1. Alternatively, the transistor 202_2 can be connected between the first terminal of the transistor 201_2 and the wiring 115_2 .

[0187] Note that, similar to FIGS. 11(A) to (B), also in FIGS. 9(C) to (F), between the second terminal of the transistor 2 01_1 and the node n1, between the second terminal of the transistor 201_2 and the node n 2, between the first terminal of the transistor 201_1 and the wiring 115_1, and / or between the first terminal of the transistor 201_2 and the wiring 115_2, various elements or circuits can be connected. In FIG. 11(C), as an example, in FIG. 9(F), between the second terminal of the transistor 201_1 and the node n1, a transistor 202_1 with a diode-connected configuration is connected, and between the second terminal of the transistor 201_2 and the node n2 a configuration is shown where a transistor 202_2 with a diode-connected configuration is connected. In FIG. 11(D), as an example, in FIG. 9(F), between the first terminal of the transistor 201_1 and the wiring 114, a transistor 202_1 with a diode-connected configuration is connected, and between the first terminal of the transistor 201_2 and the wiring 114, a transistor 202_1 with a diode-connected configuration is connected, and the configuration in this case is shown. . Note that, as shown in FIG. 11(E), the circuit 200 includes transistors 203_1 to 203_2

[0188] ​​​​It is possible to have a plurality of transistors. Transistors 203_1 to 203 _2 preferably have the same polarity as transistors 201_1 to 201_2 and are of the N-channel type. However, it is not limited to this, and transistors 203_1 to 203 _2 can be of the P-channel type. The first terminal of transistor 203_1 is connected to wiring 117, the second terminal of transistor 203_1 is connected to node n1, and the gate of transistor 203_1 is connected to wiring 115_2. The first terminal of transistor 203 _2 is connected to wiring 117, the second terminal of transistor 203_2 is connected to node n2, and the gate of transistor 203_2 is connected to wiring 115_1. However, it is not limited to this. For example, the second terminal of transistor 203_1 can be connected to node n2. Or, the second terminal of transistor 203_2 can be connected to node n1.

[0189] Note that transistor 203_1 has a function of controlling the timing at which voltage V1 is supplied to node n1 by controlling the conduction state between wiring 117 and node n1 in accordance with signal SEL2 and can function as a switch. Transistor 203_2 has a function of controlling the timing at which voltage V1 is supplied to node n2 by controlling the conduction state between wiring 117 and node n2 in accordance with signal SEL1 and can function as a switch. Thus, in period T1, voltage V1 is supplied to node n2 by transistor 203_2. Therefore, even when transistor 201_2 is off , the potential of node n2 can be fixed. Similarly, in period T2, trans istor 203_2 supplies voltage V1 to node n2. Therefore, even when transistor 201_2 is off the potential of node n2 can be fixed. Similarly, in period T2, trans The voltage V1 is supplied to the node n1 by the dissta 203_1. Therefore, even if the transistor 201_1 is off, the potential of the node n1 can be fixed. As a result, a semiconductor device with strong noise immunity can be obtained.

[0190] In addition, as shown in Fig. 11(F), the wiring 117 can be divided into a plurality of wirings such as wiring 117A to 117B. The first terminal of the transistor 203_1 and the first terminal of the transistor 203_2 can be connected to the wiring 117A and the wiring 117B, respectively. The wirings 117A to 117B can be connected to various wirings, various elements, or various nodes.

[0191] In addition, as shown in Fig. 12(A), the second terminal of the transistor 203_1 is connected to the wiring 115_ 1, and the second terminal of the transistor 203_2 can be connected to the wiring 115_2. By doing so, during the period when the transistor 203_1 is off (for example, period T1), an H-level signal is input to the first terminal of the transistor 203_1. Therefore, a reverse bias is applied to the transistor 203_1, so that degradation can be suppressed. Similarly, during the period when the transistor 203_2 is off (for example, period T2) an H-level signal is input to the first terminal of the transistor 203_2. Therefore, since a reverse bias is applied to the transistor 203_2, degradation can be suppressed.

[0192] In addition, as shown in Fig. 12(B), the transistor 203_1 and the transistor 203_ 2 can be configured to be diode-connected. For example, the transistor 203 The first terminal of _1 is connected to wiring 115_1, and the second terminal of transistor 203_1 is connected to node n1, and the gate of transistor 203_1 is connected to node n1. Similarly, the first terminal of transistor 203_2 is connected to wiring 115_2, and the transist or 203_2's second terminal is connected to node n2, and the gate of transistor 203_2 is , connected to node n2. In this case, when signal SEL2 becomes the L level during period T1 , the L-level signal SEL2 is supplied from wiring 115_2 to node n2 via transistor 203_2. Therefore, the potential of node n2 can be fixed to be approximately V1. On the other hand, during period T2, when signal SEL1 becomes the L level, the L-level signal SEL1 is supplied from wiring 115_1 to node n1 via transistor 203_1. Therefore, the potential of node n1 can be fixed to be approximately V1. However, it is not limited to this. For example, the gate of transistor 203_1 can be connected to wiring 1 15_1. Or, the gate of transistor 203_2 can be connected to wiring 115_2.

[0193] Note that, similar to FIGS. 11(E)-(F) and FIGS. 12(A)-(B), in FIGS. 9(C)-(F) , and FIGS. 11(A)-(D), circuit 200 can also have transistors 203_1-20 3_2. For example, FIG. 12(C) shows the configuration when circuit 200 has transistors 203_1-203_2 in FIG. 9(F). FIGS. 12(D )-(E) show the case when circuit 200 has transistors 203_1-203 ​shows the configuration when having _2. In FIG. 12(F), in FIG. 11(D), circuit 200 shows the configuration when having transistors 203_1 to 203_2.

[0194] Note that the second terminal of transistor 203_1 and the second terminal of transistor 203_2 can be connected to various wirings or nodes. For example, as shown in FIG. 12(E) the second terminal of transistor 203_1 can be connected to the second terminal of transistor 201_1 Similarly, the second terminal of transistor 203_2 can be connected to the second terminal of transistor 2 01_2. Or, as shown in FIG. 12(F), the second terminal of transistor 203_1 can be connected to the first terminal of transistor 201_1 Similarly, the second terminal of transistor 203_2 can be connected to the first terminal of transistor 201 _2. Note that as shown in FIG. 5(F), circuit 200 can have a plurality of transistors such as transistors 203_1 to 203_2 in addition to transistors 201_1 to 201_2

[0195] Preferably, transistors 203_1 to 203_2 have the same polarity as transistors 201_1 to 201_ 2 and are N-channel type. However, this is not limited thereto, and transistors 203_1 to 203_2 can be P-channel type The first terminal of transistor 203_1 is connected to wiring 114, the second terminal of transistor 203 _1 is connected to node n1, and the gate of transistor 203_1 is connected to wiring 1 18. The first terminal of transistor 203_2 is connected to wiring 114, and the tra The first terminal of transistor 203_1 is connected to wiring 114, the second terminal of transistor 203_1 is connected to node n1, and the gate of transistor 203_1 is connected to wiring 118. The first terminal of transistor 203_2 is connected to wiring 114, and the tra 18. The first terminal of transistor 203_2 is connected to wiring 114, and the second terminal of transistor 203_2 is connected to node n1, and the gate of transistor 203_2 is connected to wiring 118 18. The first terminal of transistor 203_2 is connected to wiring 114, and the tra The second terminal of transistor 203_2 is connected to node n2, and the gate of transistor 203_2 is connected to wiring 118. Assume that signal CK2 is input to wiring 118. Therefore, wiring 118 can function as a signal line or a clock signal line. However, it is not limited to this, and various signals, various voltages, or various currents can be input to wiring 118. Transistor 203_1 has a function of controlling the conduction state between wiring 114 and node n1 according to the potential of wiring 118. Or, transistor 203_1 has a function of supplying the potential of wiring 114 to node n1 according to the potential of wiring 118. Transistor 203_2 has a function of controlling the conduction state between wiring 114 and node n2 according to the potential of wiring 118. Or, transistor 203_2 has a function of supplying the potential of wiring 114 to node n2 according to the potential of wiring 118. However, it is not limited to this, and transistors 203_1 to 203_2 can have various other functions.

[0196] Note that the first terminal of transistor 203_1 and the first terminal of transistor 203_2 can be connected to different wirings. Note that the gate of transistor 203_1 and the gate of transistor 203_2 can be connected to different wirings.

[0197] Similar to FIG. 5(F), in FIGS. 9(C) to (F), FIGS. 11(A) to (F), and FIGS. 12(A) to (F), it is also possible to newly add transistors having the same functions as transistors 203_1 to 203_2.

[0198] ​​​​​​​​​​​​Note that, as shown in Fig. 13(A), transistors 101_1 to 101_2 and transistors 201_1 to 201_2 can be P-channel transistors. Transistors 101p_1 to 101p_2 correspond to transistors 101_1 to 101_2 and are P-channel type. Transistors 102p_1 to 102p_2 correspond to transistors 102_1 to 102_2 and are P-channel type. Then, as shown in Fig. 13(B), when the polarity of the transistor is P-channel type, voltage V1 is supplied to wiring 113, voltage V2 is supplied to wiring 117, and the potentials of signal CK1, signal SP, signal RE, node n1, the potential of node n2, and signal OUT are inverted compared to the timing chart of Fig. 4(B). It should be noted. Note that, as in Fig. 13(A), in Figs. 9(C) to (F), Figs. 11(A) to (F), and Figs. 12 (A) to (F), P-channel transistors can also be used as the transistors.

[0199] Note that, similar to Fig. 13(A), in Figs. 9(C) to (F), Figs. 11(A) to (F), and Fig. 12 (A) to (F), P-channel transistors can also be used as the transistors.

[0200] (Embodiment 3) In this embodiment, an example of a configuration different from circuit 10 described in Embodiment 2 will be described. Note that the content described in Embodiments 1 to 2 will be omitted. Note that the content described in this embodiment can be appropriately combined with the content described in Embodiments 1 to 2.

[0201] First, a specific example of circuit 10 different from that in Embodiment 2 will be described with reference to Fig. 14. The circuit 10 in Fig. 14 includes circuit 300 in addition to circuit 200. Circuit 300 is circuit 10 ​​​​​It is part of. Note that part of circuit 300 can be shared with circuit 200, and part of circuit 20 0 can be shared with circuit 300. Circuit 300 is connected to wiring 113, wiring 116, wiring 117, node n1, node n2, and / or wiring 111. However, without being limited thereto, circuit 200 can be connected to other wiring or other nodes. is possible.

[0202] Circuit 300 often has one or more transistors. The polarities of these transistors are often the same as the polarities of transistors 101_1 to 101_2 and are often of the N-channel type. However, without being limited thereto, circuit 300 can have P-channel transistors. Or, circuit 300 can have both N-channel transistors and P-channel transistors. That is, circuit 300 can be a CMOS circuit. is possible.

[0203] Circuit 300 has a function of controlling the timing of supplying a signal or voltage to node n1, node n2, and / or wiring 111 according to the signal RE, the potential of node n1, the potential of node n2, and / or the falling time of signal OUT. Thus, circuit 200 has a function of controlling the potential of node n1, the potential of node n2, and / or the potential of wiring 111. For example, circuit 200 has a function of supplying an L-level signal or voltage V1 to node n1, node n2, and / or wiring 111.

[0204] Next, an example of circuit 300 will be described with reference to FIG. 15(A). In one example of FIG. 15(A), circuit 300 includes a plurality of transistors such as transistors 301_1 to 301_2. example, circuit 300 includes a plurality of transistors such as transistors 301_1 to 301_2 , a plurality of transistors such as transistor 302, transistors 303_1 to 303_2 , transistor 304, a plurality of circuits such as circuits 310_1 to 310_2, and circuit 320 have.

[0205] Note that transistors 301_1 to 301_2, transistor 302, transistors 303 _1 to 303_2, and transistor 304 are, by way of example, N-channel type. However, it is not limited to this, and transistors 301_1 to 301_2, transistor 3 02, transistors 303_1 to 303_2, and / or transistor 304 can be P-channel type.

[0206] Note that, by way of example, as shown in FIG. 15(B), as circuits 310_1 to 310_2, and circuit 320, an inverter circuit can be used. However, it is not limited to this , and as circuits 310_1 to 310_2, and circuit 320, various other circuits can also be used .

[0207] Next, the connection relationship of circuit 300 in FIG. 15(A) will be described. The first terminal of transistor 301_1 is connected to wiring 117, and the second terminal of transistor 301_1 is connected to node n 1. The first terminal of transistor 301_2 is connected to wiring 117, and the second terminal of transistor 301_2 is connected to node n2. The first terminal of transistor 302 is connected to wiring 117, and the second terminal of transistor 302 is connected to wiring 111 . The first terminal of transistor 303_1 is connected to wiring 117, and the second terminal of transistor 303 _1 is connected to node n1, and the gate of transistor 303_1 is wiring 1​ It is connected to 16. The first terminal of transistor 303_2 is connected to wiring 117, and the second terminal of transistor 303_2 is connected to node n2, and the gate of transistor 303_2 is connected to wiring 116. The first terminal of transistor 304 is connected to wiring 117, the second terminal of transistor 304 is connected to wiring 111, and the gate of transistor 304 is connected to wiring 116. Circuit 310_1 is connected to wiring 113, node n1, wiring 117, and the gate of transistor 301_1. Circuit 310_2 is connected to wiring 1 13, node n2, wiring 117, and the gate of transistor 301_2. Circuit 320 is connected to wiring 113, wiring 111, wiring 117, and the gate of transistor 302.

[0208] Next, the functions of circuits 310_1 to 310_2 and circuit 320 will be described. Circuit 310_1 has a function of controlling the conduction state of transistor 301_1 by controlling the potential of the gate of transistor 301_1 according to the potential of node n1, and can function as a control circuit. Circuit 310_2 has a function of controlling the conduction state of transistor 301_ 2 by controlling the potential of the gate of transistor 301_2 according to the potential of node n2, and can function as a control circuit. Circuit 3 20 has a function of controlling the conduction state of transistor 302 by controlling the potential of the gate of transistor 302 according to the potential of wiring 111, and can function as a control circuit. However, it is not limited to this, and circuits 310_1 to 310_2 and circuit 320 can have various other functions.

[0209] Next, the transistors 301_1 to 301_2, the transistor 302, and the transistor 303 The functions of the transistors _1 to 303_2 and the transistor 304 will be described. The transistor 301_1 changes the electrical continuity between the wiring 117 and the node n1 in response to an output signal of the circuit 310_1. By controlling the state, the timing of supplying voltage V1 to node n1 can be controlled. The transistor 301_2 has a function of switching the input voltage Vcc to the ground potential Vcc and can function as a switch. The conduction state between the wiring 117 and the node n2 is controlled in response to the output signal of 310_2. Therefore, the switch has a function of controlling the timing of supplying the voltage V1 to the node n2. The transistor 302 can function as a By controlling the conduction state between the wiring 117 and the wiring 111, the voltage V1 is applied to the wiring 111. and can function as a switch. The transistor 303_1 turns on or off the wiring 117 and the node n1 in response to a signal RE. By controlling the timing of supplying voltage V1 to node n1, The transistor 303_2 is connected to a signal RE In response to this, the conduction state between the wiring 117 and the node n2 is controlled, thereby controlling the voltage V1. It has a function to control the timing of supplying to node n2, and can function as a switch. The transistor 304 turns on and off the wiring 117 and the wiring 111 in response to a signal RE. By controlling the state, the timing of supplying the voltage V1 to the wiring 111 can be controlled. It can function as a switch. However, it is not limited to this. Transistors 301_1 to 301_2, transistor 302, transistors 303_1 to 30 3_2, and transistor 304 can also have various other functions.

[0210] Next, an example of the operation of circuit 300 in Fig. 15(A) will be described. Note that since the operation of the semiconductor device in Fig. 15(A) has parts in common with the operation of the semiconductor device in Fig. 4(A), it will be described with reference to the timing chart in Fig. 4( C). Note that the parts in common with Embodiments 1 to 2 will not be described.

[0211] First, in period A1, as shown in Fig. 16(A), since signal RE becomes the L level, transistors 303_1 to 303_2 and transistor 304 turn off. The output signal of circuit 31 0_1 becomes the L level because the potential of node n1 becomes, for example, V2 + Vth101_1 + Vx. Thus, transistor 301_1 turns off. The output signal of circuit 310_2 becomes the H level because the potential of node n2 becomes approximately V1. Thus, transistor 301_2 turns on. The output signal of circuit 320 becomes the H level because the potential of wiring 111 becomes approximately V1. Thus, transistor 302 turns on. As a result, wiring 117 and node n1 are in a non-conductive state, wiring 117 and node n2 are in a conductive state via transistor 301_2, and wiring 117 and wiring 111 are in a conductive state via transistor 302. Thus, voltage V1 is supplied from wiring 117 to node n2 via transistor 30 1_2. Voltage V1 is supplied from wiring 117 to wiring 111 via transistor 30 2.

[0212] ​​On the other hand, in period A2, as shown in FIG. 16(B), the output signal of circuit 310_1 becomes H level because the potential of node n1 is approximately V1, and the output signal of circuit 310_2 becomes L level because the potential of node n2 is, for example, V2 + Vth101_2 + Vx. However, this is different from period A1. Thus, transistor 301_1 turns on and transistor 301_2 turns off. As a result, wiring 117 and node n1 become conductive through transistor 3 01_1, and wiring 117 and node n2 become non-conductive. Thus, voltage V1 is supplied to node n1 through wiring 117.

[0213] Next, in period B1, as shown in FIG. 16(C), since signal RE remains at L level, transistors 303_1 to 303_2 and transistor 304 remain off. The output signal of circuit 310_1 remains at L level because the potential of node n1 is, for example, V2 + Vth101_1 + Vx. Thus, transistor 301_1 remains off. The output signal of circuit 310_2 remains at H level because the potential of node n2 is approximately V1. Thus, transistor 301_2 remains on. The output signal of circuit 320 becomes L level because the potential of wiring 111 is approximately V2. Thus, transistor 302 turns off. As a result, wiring 117 and node n1 remain non-conductive, wiring 117 and node n2 become conductive through transistor 301_2, and wiring 117 and wiring 111 become non-conductive. Thus, voltage V1 is supplied from wiring 117 to node n2 through transistor 301_2.

[0214] On the other hand, in period B2, as shown in FIG. 17(A), the output signal of circuit 310_1 remains at the L level because the potential of node n1 is approximately V1, and the output signal of circuit 310_2 remains at the L level because the potential of node n2 is approximately V2 + Vth101_2 + Vx, which is different from period B1. Therefore, transistor 301_1 remains on and transistor 301_2 remains off. As a result, wiring 117 and node n1 remain in a conductive state through transistor 301_1, and wiring 117 and node n2 remain in a non-conductive state. Thus, voltage V1 is supplied to node n1 via wiring 117. Since the potential of node n1 remains approximately V1, it remains at the L level, and the output signal of circuit 310_2 remains at the L level because the potential of node n2 is approximately V2 + Vth101_2 + Vx, which is different from period B1. For example, it remains at the L level, which is different from period B1. Therefore, transistor 301_1 remains on and transistor 301_2 remains off. As a result, wiring 117 and node n1 remain in a conductive state through transistor 301_1, and wiring 117 and node n2 remain in a non-conductive state. Thus, voltage V1 is supplied to node n1 via wiring 117. Next, in periods C1 and C2, as shown in FIG. 17(B), since signal RE becomes high level, transistors 303_1 to 303_2 and transistor 304 turn on. The output signal of circuit 310_1 becomes high level because the potential of node n1 becomes approximately V1. Therefore, transistor 301_1 turns on.

[0215] The output signal of circuit 310_2 becomes high level because the potential of node n2 becomes approximately V1. Therefore, transistor 301_2 turns on. The output signal of circuit 320 becomes high level because the potential of wiring 111 becomes approximately V1. Therefore, transistor 302 turns on. As a result, wiring 117 and node n1 become conductive through transistors 301_1 and 303_1, wiring 117 and node n2 become conductive through transistors 301_2 and 303_2, and wiring 117 and wiring 111 become conductive through transistors 302 and 304. Thus, voltage V1 is from wiring 117 to... Therefore, transistor 302 turns on. As a result, wiring 117 and node n1 become conductive through transistors 301_1 and 303_1. Wiring 117 and node n2 become conductive through transistors 301_2 and 303_2. Wiring 117 and wiring 111 become conductive through transistors 302 and 304. Thus, voltage V1 is from wiring 117 to... It is supplied to node n1 via transistor 301_1 and transistor 303_1. The voltage V1 is supplied from wiring 117 to node n2 via transistor 301_2 and transistor 303_2. The voltage V1 is supplied from wiring 117 to wiring 111 via transistor 302 and transistor 304.

[0216] Next, in period D1, period D2, period E1, and period E2, as shown in FIG. 17(C), since the signal RE is at the L level, transistors 303_1 to 303_2 and transistor 304 turn off. The output signal of circuit 310_1 remains at the H level because the potential of node n1 remains approximately V1. Therefore, transistor 301_1 remains on. The output signal of circuit 310_2 remains at the H level because the potential of node n2 remains approximately V1. Therefore, transistor 301_2 remains on. The output signal of circuit 320 remains at the H level because the potential of wiring 111 remains approximately V1. Therefore, transistor 302 remains on. As a result, wiring 117 and node n1 remain conductive via transistor 301_1, wiring 117 and node n2 remain conductive via transistor 301_2, and wiring 117 and wiring 111 remain conductive via transistor 302. Therefore, the voltage V1 is supplied from wiring 117 to node n1 via transistor 301_1. The voltage V1 is supplied from wiring 117 to node n2 via transistor 301_2. The voltage V1 is supplied from wiring 117 to wiring 111 via transistor 302.

[0217] Note that since transistors 301_1 to 301_2 have similar functions to each other, it is preferable that their channel widths are approximately equal. Similarly, since transistors 303_1 to 303_2 have similar functions, it is preferable that their channel widths are approximately equal. However, it is not limited to this, and transistors 301_1 to 301_2 can have different channel widths from each other. Or, transistors 303_1 to 303_2 can have different channel widths from each other. Note that since transistors 301_1 to 301_2 have similar functions to each other, it is preferable that their channel widths are approximately equal. Similarly, since transistors 303_1 to 303_2 have similar functions, it is preferable that their channel widths are approximately equal. However, it is not limited to this, and transistors 301_1 to 301_2 can have different channel widths from each other. Or, transistors 303_1 to 303_2 can have different channel widths from each other. Note that since transistors 301_1 to 301_2 have similar functions to each other, it is preferable that their channel widths are approximately equal. Similarly, since transistors 303_1 to 303_2 have similar functions, it is preferable that their channel widths are approximately equal. However, it is not limited to this, and transistors 301_1 to 301_2 can have different channel widths from each other. Or, transistors 303_1 to 303_2 can have different channel widths from each other. Note that since transistors 301_1 to 301_2 have similar functions to each other, it is preferable that their channel widths are approximately equal. Similarly, since transistors 303_1 to 303_2 have similar functions, it is preferable that their channel widths are approximately equal. However, it is not limited to this, and transistors 301_1 to 301_2 can have different channel widths from each other. Or, transistors 303_1 to 303_2 can have different channel widths from each other. Note that since transistors 301_1 to 301_2 have similar functions to each other, it is preferable that their channel widths are approximately equal. Similarly, since transistors 303_1 to 303_2 have similar functions, it is preferable that their channel widths are approximately equal. However, it is not limited to this, and transistors 301_1 to 301_2 can have different channel widths from each other. Or, transistors 303_1 to 303_2 can have different channel widths from each other. Note that since transistors 301_1 to 301_2 have similar functions to each other, it is preferable that their channel widths are approximately equal. Similarly, since transistors 303_1 to 303_2 have similar functions, it is preferable that their channel widths are approximately equal. However, it is not limited to this, and transistors 301_1 to 301_2 can have different channel widths from each other. Or, transistors 303_1 to 303_2 can have different channel widths from each other.

[0218] Note that transistors 301_1 to 301_2 have a function of controlling the timing of supplying voltage V1 to nodes n1 to n2, and transistor 302 has a function of controlling the timing of supplying voltage V1 to wiring 111. Since the load of nodes n1 to n2 is often smaller than the load of wiring 111, it is preferable that the channel widths of transistors 301_1 to 301_2 are smaller than the channel width of transistor 302. For the same reason, it is preferable that the channel widths of transistors 303_1 to 303_2 are smaller than the channel width of transistor 304. However, it is not limited to this, and the channel widths of transistors 301_1 to 301_2 can be larger than or approximately equal to the channel width of transistor 302. Or, the channel widths of transistors 303_1 to 303_2 can be larger than or approximately equal to the channel width of transistor 304. Note that transistors 301_1 to 301_2 have a function of controlling the timing of supplying voltage V1 to nodes n1 to n2, and transistor 302 has a function of controlling the timing of supplying voltage V1 to wiring 111. Since the load of nodes n1 to n2 is often smaller than the load of wiring 111, it is preferable that the channel widths of transistors 301_1 to 301_2 are smaller than the channel width of transistor 302. For the same reason, it is preferable that the channel widths of transistors 303_1 to 303_2 are smaller than the channel width of transistor 304. However, it is not limited to this, and the channel widths of transistors 301_1 to 301_2 can be larger than or approximately equal to the channel width of transistor 302. Or, the channel widths of transistors 303_1 to 303_2 can be larger than or approximately equal to the channel width of transistor 304. Note that transistors 301_1 to 301_2 have a function of controlling the timing of supplying voltage V1 to nodes n1 to n2, and transistor 302 has a function of controlling the timing of supplying voltage V1 to wiring 111. Since the load of nodes n1 to n2 is often smaller than the load of wiring 111, it is preferable that the channel widths of transistors 301_1 to 301_2 are smaller than the channel width of transistor 302. For the same reason, it is preferable that the channel widths of transistors 303_1 to 303_2 are smaller than the channel width of transistor 304. However, it is not limited to this, and the channel widths of transistors 301_1 to 301_2 can be larger than or approximately equal to the channel width of transistor 302. Or, the channel widths of transistors 303_1 to 303_2 can be larger than or approximately equal to the channel width of transistor 304. Note that transistors 301_1 to 301_2 have a function of controlling the timing of supplying voltage V1 to nodes n1 to n2, and transistor 302 has a function of controlling the timing of supplying voltage V1 to wiring 111. Since the load of nodes n1 to n2 is often smaller than the load of wiring 111, it is preferable that the channel widths of transistors 301_1 to 301_2 are smaller than the channel width of transistor 302. For the same reason, it is preferable that the channel widths of transistors 303_1 to 303_2 are smaller than the channel width of transistor 304. However, it is not limited to this, and the channel widths of transistors 301_1 to 301_2 can be larger than or approximately equal to the channel width of transistor 302. Or, the channel widths of transistors 303_1 to 303_2 can be larger than or approximately equal to the channel width of transistor 304. Note that transistors 301_1 to 301_2 have a function of controlling the timing of supplying voltage V1 to nodes n1 to n2, and transistor 302 has a function of controlling the timing of supplying voltage V1 to wiring 111. Since the load of nodes n1 to n2 is often smaller than the load of wiring 111, it is preferable that the channel widths of transistors 301_1 to 301_2 are smaller than the channel width of transistor 302. For the same reason, it is preferable that the channel widths of transistors 303_1 to 303_2 are smaller than the channel width of transistor 304. However, it is not limited to this, and the channel widths of transistors 301_1 to 301_2 can be larger than or approximately equal to the channel width of transistor 302. Or, the channel widths of transistors 303_1 to 303_2 can be larger than or approximately equal to the channel width of transistor 304. Note that transistors 301_1 to 301_2 have a function of controlling the timing of supplying voltage V1 to nodes n1 to n2, and transistor 302 has a function of controlling the timing of supplying voltage V1 to wiring 111. Since the load of nodes n1 to n2 is often smaller than the load of wiring 111, it is preferable that the channel widths of transistors 301_1 to 301_2 are smaller than the channel width of transistor 302. For the same reason, it is preferable that the channel widths of transistors 303_1 to 303_2 are smaller than the channel width of transistor 304. However, it is not limited to this, and the channel widths of transistors 301_1 to 301_2 can be larger than or approximately equal to the channel width of transistor 302. Or, the channel widths of transistors 303_1 to 303_2 can be larger than or approximately equal to the channel width of transistor 304. Note that transistors 301_1 to 301_2 have a function of controlling the timing of supplying voltage V1 to nodes n1 to n2, and transistor 302 has a function of controlling the timing of supplying voltage V1 to wiring 111. Since the load of nodes n1 to n2 is often smaller than the load of wiring 111, it is preferable that the channel widths of transistors 301_1 to 301_2 are smaller than the channel width of transistor 302. For the same reason, it is preferable that the channel widths of transistors 303_1 to 303_2 are smaller than the channel width of transistor 304. However, it is not limited to this, and the channel widths of transistors 301_1 to 301_2 can be larger than or approximately equal to the channel width of transistor 302. Or, the channel widths of transistors 303_1 to 303_2 can be larger than or approximately equal to the channel width of transistor 304. Note that transistors 301_1 to 301_2 have a function of controlling the timing of supplying voltage V1 to nodes n1 to n2, and transistor 302 has a function of controlling the timing of supplying voltage V1 to wiring 111. Since the load of nodes n1 to n2 is often smaller than the load of wiring 111, it is preferable that the channel widths of transistors 301_1 to 301_2 are smaller than the channel width of transistor 302. For the same reason, it is preferable that the channel widths of transistors 303_1 to 303_2 are smaller than the channel width of transistor 304. However, it is not limited to this, and the channel widths of transistors 301_1 to 301_2 can be larger than or approximately equal to the channel width of transistor 302. Or, the channel widths of transistors 303_1 to 303_2 can be larger than or approximately equal to the channel width of transistor 304. Note that transistors 301_1 to 301_2 have a function of controlling the timing of supplying voltage V1 to nodes n1 to n2, and transistor 302 has a function of controlling the timing of supplying voltage V1 to wiring 111. Since the load of nodes n1 to n2 is often smaller than the load of wiring 111, it is preferable that the channel widths of transistors 301_1 to 301_2 are smaller than the channel width of transistor 302. For the same reason, it is preferable that the channel widths of transistors 303_1 to 303_2 are smaller than the channel width of transistor 304. However, it is not limited to this, and the channel widths of transistors 301_1 to 301_2 can be larger than or approximately equal to the channel width of transistor 302. Or, the channel widths of transistors 303_1 to 303_2 can be larger than or approximately equal to the channel width of transistor 304. Note that transistors 301_1 to 301_2 have a function of controlling the timing of supplying voltage V1 to nodes n1 to n2, and transistor 302 has a function of controlling the timing of supplying voltage V1 to wiring 111. Since the load of nodes n1 to n2 is often smaller than the load of wiring 111, it is preferable that the channel widths of transistors 301_1 to 301_2 are smaller than the channel width of transistor 302. For the same reason, it is preferable that the channel widths of transistors 303_1 to 303_2 are smaller than the channel width of transistor 304. However, it is not limited to this, and the channel widths of transistors 301_1 to 301_2 can be larger than or approximately equal to the channel width of transistor 302. Or, the channel widths of transistors 303_1 to 303_2 can be larger than or approximately equal to the channel width of transistor 304.

[0219] Note that as shown in FIG. 18(A), similar to Embodiments 1 to 2, wiring 117 can be divided into a plurality of wirings such as wirings 117C to 117K. Wiring 117C, Note that as shown in FIG. 18(A), similar to Embodiments 1 to 2, wiring 117 can be divided into a plurality of wirings such as wirings 117C to 117K. Wiring 117C, Wiring 117D, Wiring 117E, Wiring 117F, Wiring 117G, Wiring 117H, Wiring 117 I, Wiring 117J, and Wiring 117K are each connected to the first terminal of transistor 303_1, the first terminal of transistor 303_2, the first terminal of transistor 304, circuit 310_1, the first terminal of transistor 301_1, circuit 310_2, the first terminal of transistor 301_2 , circuit 320, and the first terminal of transistor 302. Wiring 11 7C to 117K can be connected to various wirings such as Wiring 111, Wiring 112, Wiring 113, Wiring 114, Wiring 115_1 to 115_2, Wiring 116, Wiring 118, or Wiring 211, or various nodes such as nodes n1 to n2. However, it is not limited to this, and Wiring 113 can also be divided into a plurality of wirings in the same way.

[0220] In addition, as shown in FIG. 18(B), the first terminal of transistor 303_1, the first terminal of transistor 3 03_2, and the first terminal of transistor 304 can be connected to Wiring 118.

[0221] In addition, as shown in FIG. 18(C), transistor 304 can be omitted. However, it is not limited to this, and transistor 303_1 and / or transistor 303_ 2 can be omitted.

[0222] Similar to FIG. 18(C), in FIGS. 18(A) to (B) as well, transistor 303_ 1, transistor 303_2, and / or transistor 304 can be omitted.

[0223] In addition, as shown in FIG. 19(A), circuit 320 and transistor 302 can be omitted. is possible. However, it is not limited to this, and the circuit 310_1 and the transistor 301_ 1 can be omitted, or the circuit 310_1 and the transistor 301_2 can be omitted as well.

[0224] Similar to FIG. 19(A), in FIGS. 18(A) to (C) as well, the circuit 310_1 and the transistor 301_1 can be omitted, or the circuit 310_1 and the transistor 301_2 can be omitted, or the circuit 320 and the transistor 302 can be omitted.

[0225] In addition, as shown in FIG. 19(B), the transistor 301_1 can be replaced with a diode 301a_1 whose one terminal (hereinafter also referred to as the positive electrode) is connected to the node n1 and the other terminal (hereinafter also referred to as the negative electrode) is connected to the output terminal of the circuit 310_. 1. Or, the transistor 301_2 can be replaced with a diode 301a_2 whose one terminal (hereinafter also referred to as the positive electrode) is connected to the node n2 and the other terminal (hereinafter also referred to as the negative electrode) is connected to the output terminal of the circuit 310_2. Or, the transistor 302 can be replaced with a diode 302a whose one terminal (hereinafter also referred to as the positive electrode) is connected to the wiring 111 and the other terminal (hereinafter also referred to as the negative electrode) is connected to the output terminal of the circuit 320. Or, the transistor 303_1 can be replaced with a diode 3 03a_1 whose one terminal (hereinafter also referred to as the positive electrode) is connected to the node n1 and the other terminal (hereinafter also referred to as the negative electrode) is connected to the wiring 116. Or, the transistor 303_2 can be replaced with a diode whose one terminal (hereinafter also referred to as the positive electrode) is connected to the node n2 and the other terminal (hereinafter also referred to as the negative electrode) is connected to the output terminal of the circuit 310_2. Or, the transistor 302 can be replaced with a diode 302a whose one terminal (hereinafter also referred to as the positive electrode) is connected to the wiring 111 and the other terminal (hereinafter also referred to as the negative electrode) is connected to the output terminal of the circuit 320. Or, the transistor 303_1 can be replaced with a diode 3 03a_1 whose one terminal (hereinafter also referred to as the positive electrode) is connected to the node n1 and the other terminal (hereinafter also referred to as the negative electrode) is connected to the wiring 116. Or, the transistor 303_2 can be replaced with a diode whose one terminal (hereinafter also referred to as the positive electrode) is connected to the node n2 and the other terminal (hereinafter also referred to as the negative electrode) is connected to the output terminal of the circuit 320. Or, the transistor 303_1 can be replaced with a diode 3 03a_1 whose one terminal (hereinafter also referred to as the positive electrode) is connected to the node n1 and the other terminal (hereinafter also referred to as the negative electrode) is connected to the wiring 116. Or, the transistor 303_2 can be replaced with a diode whose one terminal (hereinafter also referred to as the positive electrode) is connected to the node n2 and the other terminal (hereinafter also referred to as the negative electrode) is connected to the wiring 116. Or, the transistor 303_2 can be replaced with a diode whose one terminal (hereinafter also referred to as the positive electrode) is connected to the node n2 and the other terminal (hereinafter also referred to as the negative electrode) 03a_1 and replaced. Or, the transistor 303_2 can be replaced with a diode whose one terminal (hereinafter also referred to as the positive electrode) is connected to the node n2 and the other terminal (hereinafter also referred to as the negative electrode) is connected to the node n2 and the other terminal (hereinafter also referred to as the negative electrode) can be replaced with a diode 303a_2 connected to the wiring 116. Or , the transistor 304 can be replaced with a diode 304a in which one terminal (hereinafter also referred to as the positive electrode) is connected to the wiring 111 and the other terminal (hereinafter also referred to as the negative electrode) is connected to the wiring 116. However, it is not limited to this, and by connecting the gate of each transistor to the second terminal, it is possible to form a configuration in which the transistor is diode-connected. Or, by connecting the gate of each transistor to the first terminal, it is possible to form a configuration in which the transistor is diode-connected.

[0226] Note that, similar to FIG. 19(B), in FIGS. 18(A) to (C) and FIG. 19(A) as well, the transistors 301_1 to 301_2, the transistor 302, the transistors 303_1 to 3 03_2, and / or the transistor 304 can be replaced with diodes. Or, these transistors can be configured to be diode-connected.

[0227] Note that, as shown in FIG. 19(C), the circuits for controlling the conduction states of the transistors 301_1 to 301_2 and the transistor 302 can be shared by the transistors 301_1 to 301_2 and the transistor 302. The circuit 330 has a function of controlling the conduction states of the transistors 301_1 to 301_2 and the transistor 302 by controlling the potentials of the gates of the transistors 301_1 to 301_2 and the transistor 302 according to the potentials of the nodes n1 to n2, and can function as a control circuit. In periods A1, A2, B1, and B2 shown in FIG. 4(C), the output of the circuit 330​​​​​​​​​ Since the signal is at a potential higher than V1, either the potential of node n1 or the potential of node n2, it is at the L level Therefore, transistors 301_1 to 301_2 and transistor 302 are turned off During period C1, period C2, period D1, period D2, period E1, and period E2, the output signal of circuit 330 is at the H level because the potential of node n1 or the potential of node n2 is approximately V1 Therefore, transistors 301_1 to 301_2 and transistor 302 are turned on

[0228] Similar to FIG. 19(C), in FIGS. 18(A) to (C) and FIGS. 19(A) to (B) as well, it is possible to share the circuit for controlling the conduction states of transistors 301_1 to 301_2 and transistor 302

[0229] As shown in FIG. 20(A), when circuit 100 has a plurality of transistors such as transistors 101_1 to 101_N as in FIG. 10(C), circuit 300 can have a plurality of transistors such as transistors 301_1 to 301_N, a plurality of transistors such as transistors 303_1 to 303 _N, and a plurality of circuits such as circuits 310_1 to 310_N Transistors 301_1 to 301_N correspond to transistor 301_ 1 or transistor 301_2 and have similar functions. Transistors 303_1 to 303_N correspond to transistor 303_1 or transistor 303_2 and have similar functions. Circuits 310_1 to 310_N correspond to circuit 310_1 or circuit 310_2 and have similar functions. The first terminals of transistors 301_1 to 301_N are connected to wiring 1 ​​It is connected to 17. The second terminals of transistors 301_1 to 301_N are each connected to nodes n 1 to nN respectively. The gates of transistors 301_1 to 301_N are each connected to the output terminals of circuits 3 10_1 to 310_N. The first terminals of transistors 303_1 to 303_N are connected to wiring 117. The second terminals of transistors 303_1 to 303_N are each connected to nodes n1 to nN. The gates of transistors 303_1 to 303_N are connected to wiring 116.

[0230] Similar to FIG. 20(A), in FIGS. 18(A) to (C) and FIGS. 19(A) to (C) as well, circuit 300 can have a plurality of transistors such as transistors 301_1 to 301_N, a plurality of transistors such as transistors 303_1 to 303_N, and / or a plurality of circuits such as circuits 31 0_1 to 310_N.

[0231] When the semiconductor device has circuit 120 as shown in FIG. 8(F), as shown in FIG. 20(B), circuit 300 can have transistor 342 and transistor 344. Transistor 342 corresponds to transistor 302 and has a similar function. Transistor 344 corresponds to transistor 304 and has a similar function. The first terminal of transistor 342 is connected to wiring 117, the second terminal of transistor 342 is connected to wiring 2 11, and the gate of transistor 342 is connected to the gate of transistor 302. The first terminal of transistor 344 is connected to wiring 117, the second terminal of transistor 344 is connected to wiring 211, and the gate of transistor 344 is connected to wiring 116.

[0232] ​​​​​ Note that, similar to FIG. 20(B), in FIGS. 18(A) to (C), FIGS. 19(A) to (C), and FIG. 2 0(A) as well, the circuit 300 can have the transistor 342 and / or the transistor 3 44.

[0233] Note that, as shown in FIG. 21, as the transistors 301_1 to 301_2, the transistor 302 , the transistors 303_1 to 303_2, and the transistor 304, P-channel type transistors can be used. The transistors 301p_1 to 301p_2, the trans istor 302p, the transistors 303p_1 to 303p_2, and the transistor 30 4p respectively correspond to the transistors 301_1 to 301_2, the transistor 302, the trans istors 303_1 to 303_2, and the transistor 304 and are of P-channel type. Note that when the polarity of the transistor is of P-channel type, the voltage V1 is supplied to the wiring 113, and the voltage V2 is supplied to the wiring 117, and the output signal of the circuit 310_1, the output signal of the circuit 310_2 , the output signal of the circuit 320, the potential of the node n1, the potential of the node n2, and the signal OUT are inverted as compared with the case where the polarity of the trans istor is of N-channel type. This is noted.

[0234] Note that, similar to FIG. 21, in FIGS. 18(A) to (C), FIGS. 19(A) to (C), and FIGS. 20(A ) to (B) as well, P-channel type transistors can be used as the transistors.

[0235] Next, specific examples of the circuits 310_1 to 310_2 and the circuit 320 will be described.

[0236] First, FIG. 22(A) shows an example of the circuit 310_1. The circuit 310_1 is a trans It has a transistor 311_1 and a transistor 312_1. The first terminal of the transistor 311_1 is connected to the wiring 113, the second terminal of the transistor 311_1 is connected to the gate of the transistor 30 1_1, and the gate of the transistor 311_1 is connected to the wiring 113 . The first terminal of the transistor 312_1 is connected to the wiring 117, and the second terminal of the transistor 312 _2 is connected to the gate of the transistor 301_1, and the gate of the transistor 312_ 2 is connected to the node n1. Assume that the transistors 311_1 and 3 12_1 are of N-channel type. However, it is not limited thereto, and the transistors 311_1 and / or the transistor 312_1 can be of P-channel type . The transistor 311_1 has a function of raising the potential of the gate of the transistor 301_1 when the potential of the gate of the transistor 301_1 becomes approximately V 1, and can function as a diode . The transistor 312_1 has a function of controlling the conduction state between the wiring 117 and the transistor 301_1 according to the potential of the node n1, and has a function of controlling the timing of supplying the voltage V1 to the gate of the transistor 301_1, and can function as a switch .

[0237] The operation of the circuit 310_1 shown in FIG. 22(A) will be described. During the period A1 and the period B1, since the potential of the node n1 is higher than the threshold voltage of the transistor 312_1, the transistor 312_1 is turned on. Therefore, by making the channel width of the transistor 312_1 larger than the channel width of the transistor 311_1, the transistor 30 The potential of the gate of 1_1 is approximately V1. For example, the potential of the gate of transistor 301_1 is smaller than the sum of the potential of wiring 117 (V1) and the threshold voltage of transistor 301_1 (Vth30 1_1). During period A2, period B2, period C1, period C2, period D1, period D2, period E1, and period E2, since the potential of node n1 is approximately V1 transistor 312_1 turns off. Therefore, the potential of the gate of transistor 301_1 is the value obtained by subtracting the threshold voltage of transistor 311_1 (Vt h311_1) from the potential of wiring 113 (V2) (V2 - Vth311_1).

[0238] Note that the channel width of transistor 312_1 is preferably twice or more the channel width of transistor 311_1. More preferably, it is preferably 4 times or more. Even more preferably, it is preferably 8 times or more. However, it is not limited thereto.

[0239] Note that the gate and the first terminal of transistor 311_1 can be connected to various wirings For example, the gate and the first terminal of transistor 311_1 can be connected to wiring 112 or wiring 118. However, it is not limited thereto.

[0240] Note that the first terminal of transistor 312_1 can be connected to various wirings For example, the first wiring of transistor 312_1 can be connected to wiring 115_2 However, it is not limited thereto.

[0241] Note that as shown in Fig. 22(B), circuit 310_1 includes transistor 311_1 and In addition to transistor 312_1, it has transistors 313_1 and 314_1 This is possible. The first terminal of transistor 313_1 is connected to wiring 113, The second terminal of transistor 313_1 is connected to the gate of transistor 301_1, and the gate of transistor 313_1 is connected to the second terminal of transistor 311_1 and the second terminal of transistor 312_1. Assume that transistors 311_1 and 312_1 are N-channel type. However, it is not limited thereto, and transistors 31 1_1 and / or transistor 312_1 can be P-channel type. Transistor 313_1 has a function of controlling the timing of supplying the voltage supplied to wiring 113 to transistor 301_1, and can function as a bootstrap transistor or a switch The first terminal of transistor 314_1 is connected to wiring 117, the second terminal of transistor 314_1 is connected to the second terminal of transistor 313_1, and the gate of transistor 314_1 is connected to node n1. Transistor 314_1 has a function of controlling the timing of supplying voltage V1 to the gate of transistor 301_1 by controlling the conduction state between wiring 117 and transistor 301_1 according to the potential of node n1, and can function as a switch

[0242] Note that the first terminal of transistor 313_1 can be connected to various wirings For example, the first terminal of transistor 313_1 can be connected to wiring 112 or wiring 118 However, it is not limited thereto.

[0243] ​​​​​Note that the first terminal of transistor 314_1 can be connected to various wirings. For example, the first wiring of transistor 314_1 can be connected to wiring 115_2. However, it is not limited to this.

[0244] Note that in FIG. 22(B), as shown in FIG. 22(C), a capacitor element 315_1 can be connected between the gate and the second terminal of transistor 313_1.

[0245] Note that as shown in FIG. 22(D), circuit 300 can have transistor 316_1. The first terminal of transistor 316_1 is connected to wiring 117, the second terminal of transistor 316_1 is connected to the gate of transistor 301_1, and the gate of transistor 316_1 is connected to wiring 114. Assume that transistor 316_1 is of the N-channel type. However, it is not limited to this, and transistor 316_1 can be of the P-channel type. Transistor 316_1 has a function of controlling the timing at which voltage V1 is supplied to transistor 301_1 by controlling the conduction state between wiring 117 and the gate of transistor 301_1 in response to signal SP.

[0246] Note that similar to FIG. 22(D), in FIGS. 22(B) to (C) as well, it is possible to newly add transistor 316_1 whose first terminal is connected to wiring 117, second terminal is connected to the gate of transistor 301_1, and gate is connected to wiring 114.

[0247] Next, FIG. 23(A) shows an example of circuit 310_2. Circuit 310_2 includes transistor 3. ​​​​​​​It has 11_2 and transistor 312_2. The first terminal of transistor 311_2 is connected to wiring 113, the second terminal of transistor 311_2 is connected to the gate of transistor 301_ 2, and the gate of transistor 311_2 is connected to wiring 113. The first terminal of transistor 312_2 is connected to wiring 117, and the second terminal of transistor 312_2 is connected to the gate of transistor 301_2, and the gate of transistor 312_2 is connected to node n2. Transistors 311_2 and transistor 312 _2 shall be of N-channel type. However, it is not limited thereto, and transistor 31 1_2 and / or transistor 312_2 can be of P-channel type. Transistor 311_2 has a function of raising the potential of the gate of transistor 301_2 when the potential of the gate of transistor 301_2 is approximately V1, and can function as a diode. Transistor 312_2 has a function of controlling the timing of supplying voltage V1 to the gate of transistor 301_2 by controlling the conduction state between wiring 117 and transistor 301_2 according to the potential of node n2, and can function as a switch. The operation of circuit 310_2 shown in Fig. 23(A) will be described. During period A1 and period B1, since the potential of node n2 is higher than the threshold voltage of transistor 312_2, transistor 312_2 turns on. Therefore, by making the channel width of transistor 312_2 larger than the channel width of transistor 311_2, the potential of the gate of transistor 301 _2 becomes approximately V1. For example, the gate of transistor 301_2

[0248] The operation of circuit 310_2 shown in Fig. 23(A) will be described. During period A1 and period B1, since the potential of node n2 is higher than the threshold voltage of transistor 312_2, transistor 312_2 turns on. Therefore, by making the channel width of transistor 312_2 larger than the channel width of transistor 311_2, the potential of the gate of transistor 301 _2 becomes approximately V1. For example, the gate of transistor 301_2 _2, by making the channel width of transistor 312_2 larger than the channel width of transistor 311_2, the potential of the gate of transistor 301 _2 becomes approximately V1. For example, the gate of transistor 301_2 The potential is smaller than the sum of the potential of wiring 117 (V1) and the threshold voltage of transistor 301_2 (Vth301 _2). During period A2, period B2, period C1, period C2, period D 1, period D2, period E1, and period E2, the potential of node n2 is generally V1, so transistor 312_2 turns off. Therefore, the potential of the gate of transistor 301_2 is the value obtained by subtracting the threshold voltage of transistor 311_2 (Vth 311_2) from the potential of wiring 113 (V2) (V2 - Vth311_2).

[0249] Note that the channel width of transistor 312_2 is preferably at least twice the channel width of transistor 311_2. More preferably, it is preferably at least four times. Even more preferably, it is preferably at least eight times. However, it is not limited thereto.

[0250] Note that the gate and the first terminal of transistor 311_2 can be connected to various wirings. For example, the gate and the first terminal of transistor 311_2 can be connected to wiring 112 or wiring 118. However, it is not limited thereto.

[0251] Note that the first terminal of transistor 312_2 can be connected to various wirings. For example, the first terminal of transistor 312_2 can be connected to wiring 115_1. However, it is not limited thereto.

[0252] Note that as shown in FIG. 23(B), circuit 310_2 includes, in addition to transistor 311_2 and transistor 312_2, transistor 313_2 and transistor 314_2. ​​​A first terminal of the transistor 313_2 is connected to the wiring 113. A second terminal of the transistor 313_2 is connected to the gate of the transistor 301_2. The gate of the transistor 313_2 is connected to the second terminal of the transistor 311_2 and the The transistor 311_2 and the transistor 312_2 are connected to a second terminal of the transistor 311_3 and a second terminal of the transistor 312_4. The transistor 31 is an N-channel type. However, this is not limited to this. 1_2 and / or transistor 312_2 may be of P-channel type. The transistor 313_2 supplies the voltage supplied to the wiring 113 to the transistor 301_2. It has a function to control the timing of supplying the bootstrap transistor or switch. The transistor 314_2 can function as a By controlling the conduction state between the wiring 117 and the transistor 301_2, the voltage The timing of supplying V1 to the gate of the transistor 301_2 is controlled. It is possible for the cascade to function as a switch.

[0253] The first terminal of the transistor 313_2 can be connected to various wirings. For example, the first terminal of the transistor 313_2 is connected to the wiring 112 or the wiring 118. However, the present invention is not limited to this.

[0254] The first terminal of the transistor 314_2 can be connected to various wirings. For example, the first wiring of the transistor 314_2 may be connected to the wiring 115_1. It is possible, but not limited to this.

[0255] As shown in FIG. 23(C), between the gate and the second terminal of transistor 313_2, it is possible to connect a capacitive element 315_2.

[0256] As shown in FIG. 23(D), circuit 300 can have a transistor 316_2. The first terminal of transistor 316_2 is connected to wiring 117, and the second terminal of transistor 316_2 is connected to the gate of transistor 301_2, and the gate of transistor 316_2 is connected to wiring 114. Transistor 316_2 is assumed to be of the N-channel type. However, it is not limited thereto, and transistor 316_2 can be of the P-channel type. Transistor 316_2 controls the conductive state between wiring 117 and the gate of transistor 301_2 in response to signal SP, thereby having a function of controlling the timing at

[0257] which voltage V1 is supplied to transistor 301_2. Similar to FIG. 23(D), in FIGS. 23(B) to (C) as well, it is possible to newly add a transistor 316_2 whose first terminal is connected to wiring 117,

[0258] whose second terminal is connected to the gate of transistor 301_2, and whose gate is connected to wiring 114. Next, FIG. 24(A) shows an example of circuit 320. Circuit 320 has a transistor 321 and a transistor 322. The first terminal of transistor 321 is connected to wiring 113, the second terminal of transistor 321 is connected to is connected, and the gate of transistor 322 is connected to wiring 111. Transistor 3 21 and transistor 322 shall be of N-channel type. However, it is not limited thereto, and transistor 321 and / or transistor 322 can be of P-channel type . Transistor 321 has a function of raising the potential of the gate of transistor 302 when the potential of the gate of transistor 302 becomes approximately V1, and can function as a diode . Transistor 322 controls the conduction state between wiring 117 and transistor 302 according to the potential of wiring 111, and has a function of controlling the timing of supplying voltage V1 to the gate of transistor 302, and can function as a switch .

[0259] The operation of circuit 320 shown in Fig. 24(A) will be described. During period B1 and period B2 shown in Fig. 4(C), since the potential of wiring 111 is higher than the threshold voltage of transistor 322 , transistor 322 turns on. Therefore, by making the channel width of transistor 322 larger than the channel width of transistor 321, the potential of the gate of transistor 302 becomes approximately V1 . For example, the potential of the gate of transistor 302 is smaller than the sum of the potential of wiring 117 (V1) and the threshold voltage of transistor 302 (Vth302) . During period A1, period A2, period C1, period C2, period D1, period D2, period E1, and period E2, since the potential of wiring 111 becomes approximately V1, transistor 322 turns off . Therefore, the potential of the gate of transistor 302 is the potential of wiring 113 . ​​The value obtained by subtracting the threshold voltage (Vth321) of the transistor 321 from the bit (V2) is (V2 - Vt h321).

[0260] Note that the channel width of the transistor 322 is preferably twice or more the channel width of the transistor 321 . More preferably, it is preferably four times or more. Even more preferably , it is preferably eight times or more. However, it is not limited thereto.

[0261] Note that the gate and the first terminal of the transistor 321 can be connected to various wirings . For example, the gate and the first terminal of the transistor 321 can be connected to the wiring 112 or the wiring 11 8. However, it is not limited thereto.

[0262] Note that the first terminal of the transistor 322 can be connected to various wirings. For example , the first wiring of the transistor 322 can be connected to the wiring 112. However, it is not limited thereto.

[0263] Note that as shown in FIG. 24(B), the circuit 320 can include the transistor 321 and the transistor 322, and can also include the transistor 323 and the transistor 324 . The first terminal of the transistor 323 is connected to the wiring 113, the second terminal of the transistor 323 is connected to the gate of the transistor 302, and the gate of the transistor 323 is connected to the second terminal of the transistor 321 and the second terminal of the transistor 322. The first terminal of the transistor 324 is connected to the second terminal of the transistor 323, the second terminal of the transistor 324 is connected to the wiring 117, and the gate of the transistor 324 is connected to the wiring 111. This continues. Transistors 323 and 324 are of the N-channel type However, it is not limited to this, and transistors 323 and / or transistor 324 can be of the P-channel type. Transistor 323 has a function of controlling the timing of supplying the voltage supplied to wiring 113 to transistor 302, and can function as a boost wrapping transistor or a switch. Transistor 3 24 has a function of controlling the timing of supplying voltage V1 to the gate of transistor 302 by controlling the conduction state between wiring 117 and the gate of transistor 302 according to the potential of wiring 111, and can function as a switch.

[0264] Note that the first terminal of transistor 323 can be connected to various wirings. For example, the first wiring of transistor 323 can be connected to wiring 112 and wiring 118. However, it is not limited to this.

[0265] Note that the first terminal of transistor 324 can be connected to various wirings. For example, the first terminal of transistor 324 can be connected to wiring 118.

[0266] Note that as shown in Fig. 24(C), in addition to the configuration shown in Fig. 24(B), a capacitor element 325 can be connected between the gate and the second terminal of transistor 323.

[0267] Note that as shown in Fig. 24(D), circuit 320 can have transistor 326. The first terminal of transistor 326 is connected to wiring 117, and transistor 32 The second terminal of 6 is connected to the gate of transistor 302 and the gate of transistor 326 is connected to wiring 114. Assume that transistor 326 is an N-channel type. However, it is not limited to this, and transistor 326 can be a P-channel type. Transistor 326 controls the conduction state between wiring 117 and the gate of transistor 302 in response to signal SP, thereby having a function of controlling the timing at which voltage V1 is supplied to transistor 302.

[0268] Similar to FIG. 24(D), in FIGS. 24(B) to (C) as well, it is possible to newly add transistor 326 whose first terminal is connected to wiring 117, second terminal is connected to the gate of transistor 302, and gate is connected to wiring 114.

[0269] Next, FIG. 25(A) shows an example of circuit 330. Circuit 330 includes transistor 331, transistor 332, and transistor 333. The first terminal of transistor 331 is connected to wiring 113, the second terminal of transistor 331 is connected to the gates of transistor 301_1, transistor 301_2, and transistor 302, and the gate of transistor 331 is connected to wiring 113. The first terminal of transistor 332 is connected to wiring 117, the second terminal of transistor 332 is connected to the second terminal of transistor 331, and the gate of transistor 332 is connected to node n1. The first terminal of transistor 333 is connected to wiring 117, the second terminal of transistor 333 is connected to the second terminal of transistor 331, and the gate of transistor 333 is connected to node n. The first terminal of transistor 332 is connected to wiring 117, the second terminal of transistor 332 is connected to the second terminal of transistor 331, and the gate of transistor 332 is connected to node n1. The first terminal of transistor 333 is connected to wiring 117, the second terminal of transistor 333 is connected to the second terminal of transistor 331, and the gate of transistor 333 is connected to node n. The first terminal of transistor 333 is connected to wiring 117, and the second terminal of transistor 333 is connected to the second terminal of transistor 331. The gate of transistor 333 is connected to node n ​​​​​​​​​It is connected to 2. The transistors 331, 332, and 333 shall be of the N-channel type. However, it is not limited thereto, and the transistors 331, 332, and 333 can be of the P-channel type.

[0270] The operation of the circuit 330 shown in Fig. 25(A) will be described. During the periods A1, A2, B1, and B2 shown in Fig. 4(C), the potential of the node n1 or the potential of the node n2 becomes higher than the threshold voltage of the transistor 332 or the transistor 333, so the transistor 332 or the transistor 333 turns on. At this time, by making the channel width of the transistor 332 or the transistor 333 larger than the channel width of the transistor 331, the potentials of the gates of the transistors 301_1, 301_2, and 302 generally become V1. During the periods C1, C2, D1, D2, E1, and E2, the potential of the node n1 and the potential of the node n2 generally become V1, so the transistors 332 and 333 turn off. Therefore, the potentials of the gates of the transistors 301_1, 301_2, and 302 become a value (V2 - Vth331 + Vx) larger than the value obtained by subtracting the threshold voltage (Vth331) of the transistor 331 from the potential (V2) of the wiring 113. At this time, Vx is a value greater than 0.

[0271] Note that the channel width of the transistor 332 or the channel width of the transistor 333 is preferably 2 times or more the channel width of the transistor 331. More preferably, it is It is preferably the above. More preferably, it is preferably 8 times or more. However, It is not limited to this.

[0272] Note that the gate and the first terminal of the transistor 331 can be connected to various wirings For example, the gate and the first terminal of the transistor 331 can be connected to the wiring 112 or the wiring 11 8. However, it is not limited to this.

[0273] Note that the gate of the transistor 332 and the gate of the transistor 333 can be connected to various wirings For example, the gate of the transistor 332 can be connected to the wiring 114 and the gate of the transistor 333 can be connected to the wiring 111. However it is not limited to this.

[0274] Note that the first terminal of the transistor 332 and the first terminal of the transistor 333 can be connected to different wirings For example, the first terminal of the transistor 332 can be connected to the wiring 11 5_2 and the first terminal of the transistor 333 can be connected to the wiring 115_1 However, it is not limited to this.

[0275] Note that as shown in FIG. 25(B), in addition to the transistor 331, the transistor 3 32, and the transistor 333, the circuit 330 can also have the transistor 334, the transistor 335, and the transistor 336. The first terminal of the transistor 334 is connected to the wiring 113, the second terminal of the transistor 334 is connected to the gates of the transistor 301_1 the gate of the transistor 301_2, and the gate of the transistor 302, and the gate of the transistor 302 The gate of transistor 334 is connected to the second terminal of transistor 331. Transistor The first terminal of 335 is connected to wiring 117, the second terminal of transistor 335 is connected to the second terminal of transistor 334, and the gate of transistor 335 is connected to node n1. The first terminal of transistor 336 is connected to wiring 117, the second terminal of transistor 336 is connected to the second terminal of transistor 334, and the gate of transistor 336 is connected to node n2. Assume that transistors 334, 335, and transistor 336 are N-channel type. However, it is not limited to this, and transistors 334, 335, and transistor 336 can be P-channel type.

[0276] It is possible to connect a capacitive element between the gate and the second terminal of transistor 334.

[0277] The first terminal of transistor 334 can be connected to various wirings. For example, the first terminal of transistor 334 can be connected to wiring 112 or wiring 118. However, it is not limited to this.

[0278] The gates of transistor 335 and transistor 336 can be connected to various wirings. For example, the gate of transistor 335 can be connected to wiring 114, and the gate of transistor 336 can be connected to wiring 111. However, it is not limited to this.

[0279] The first terminal of transistor 335 and the first terminal of transistor 336 are separate wirings. ​​​​It is possible to be connected to a line. For example, the first terminal of transistor 335 is connected to wiring 11 5_2, and the first terminal of transistor 336 can be connected to wiring 115_1 . However, it is not limited to this.

[0280] Here, an example of a semiconductor device in the case of appropriately combining the contents described in Embodiments 1 to 3 is shown in FIG 41. However, it is not limited to this, and it is also possible to combine the contents described in Embodiments 1 to 3 to form semiconductor devices with various configurations.

[0281] The semiconductor device in FIG. 41 has a circuit 100 and a circuit 10. The circuit 10 has a circuit 200 and a circuit 300. The circuit 300 has a circuit 330. In the semiconductor device in FIG. 41, as the circuit 100, the configuration shown in FIG. 4(A) is used. As the circuit 200, the configuration shown in FIG. 11(E) is used . As the circuit 300, the configuration shown in FIG. 19(C) is used. As the circuit 330 , the configuration shown in FIG. 25(B) is used.

[0282] Furthermore, the operation of the semiconductor device shown in FIG. 41 was verified. The verification results are shown in FIG. 42 . FIG. 42 is a diagram showing the verification results of the semiconductor device of this embodiment. The verification was performed using a SPIC E simulator. Also, as a comparative example, the transistors 101_2, 201_2, 203_1, 20 3_2, 301_2, 303_2, 333, and the semiconductor device with a circuit configuration in which transistor 336 is not provided was also verified for its operation. Also , the verification was performed with Vdd = 30V, Vss = 0V, clock frequency = 25 kHz (1 cycle = 20 μs). μsec), mobility of each transistor = 1cm 2 / VS, threshold voltage of each transistor = 5 The test was performed with V and output capacitance set to 50 pF.

[0283] FIG. 42A is a timing chart showing the verification results for the semiconductor device of the comparative example. As shown in FIG. 42(A), in the semiconductor device of the comparative example, the node n The transistor 101_1 is turned on in response to the potential of the line 1, and the wiring 112 and the wiring 111 are connected to each other. The transistor 101_1 is turned on, and the signal CK1 is supplied from the wiring 112 to the transistor The signal is supplied to the wiring 111 via the star 101_1.

[0284] FIG. 42B is a timing chart showing the verification results of the semiconductor device shown in FIG. As shown in FIG. 42B, in the semiconductor device shown in FIG. 41, in the period T1, The transistor 101_1 is turned on in response to the potential of the transistor The transistor 101_1 is turned on, and the signal CK1 is input from the wiring 112 to the transistor is supplied to the wiring 111 through the capacitor 101_1, and in the period T2, The transistor 101_1 is turned on, and the wiring 112 and the wiring 111 are connected to the transistor 10 1_1, the signal CK1 is applied from the wiring 112 to the transistor 101_1. 42, the semiconductor device of this embodiment is In this case, by turning on different transistors in each period, each transistor It can be seen that the number of turns on and the time for which they are turned on can be reduced.

[0285] (Embodiment 4) In this embodiment, an example of a shift register will be described. The shift register of this embodiment can have the semiconductor devices of Embodiments 1 to 3. Note that the shift register can represent a semiconductor device or a gate driver. Note that the content described in Embodiments 1 to 3 will be omitted from its description. Note that the content described in Embodiments 1 to 3 can be appropriately combined with the content described in this embodiment.

[0286] First, an example of the shift register will be described with reference to FIG. 26. The shift register 500 has a plurality of flip-flops such as flip-flops 501_1 to 501_N.

[0287] Note that the flip-flops 501_1 to 501_N respectively correspond to the semiconductor devices described in Embodiments 1 to 3. An example in FIG. 26 shows the case where the semiconductor devices in FIG. 4(A) are used as the flip-flops 501_1 to 501_N, respectively. However, it is not limited thereto, and for example, other semiconductor devices or circuits described in Embodiments 1 to 3 can also be used as the flip-flops 501_1 to 501_N.

[0288] Next, the connection relationship of the shift register will be described. The shift register 500 is connected to wirings 511_1 to 511_N, wiring 512, wiring 513, wiring 514, wirings 515_1 to 515_2, wiring 516, wiring 517, and wiring 518. And in the flip-flop 501_i (where i is any one of 2 to N), wirings 111, 112, 113 , wiring 114, wirings 115_1, 115_2, wiring 116, and wiring 117 are respectively and are connected to wiring 511_i, wiring 512, wiring 514, wiring 511_i-1, wiring 515_1, wiring 515_2, wiring 511_i+1, and wiring 516. Note that in many cases, the connection destination of wiring 112 is different between odd-stage flip-flops and even-stage flip-flops. For example, in the flip-flop at the i-th stage, when wiring 112 is connected to wiring 512, in the flip-flop at the (i + 1)-th stage or the (i - 1)-th stage, wiring 112 is connected to wiring 513.

[0289] Note that in flip-flop 501_1, wiring 114 is often connected to wiring 517. And in flip-flop 501_N, wiring 116 is often connected to wiring 518. However, it is not limited to this.

[0290] Next, an example of the signals or voltages input to or output from each wiring will be described. As an example, signals GOUT_1 to GOUT_N are output from wiring 511_ 1 to 511_N, respectively. Signals GOUT_1 to GOUT_N are the output signals of flip-flops 501_1 to 501_N, respectively. And signals GOUT_1 to GOUT_N correspond to signal OUT and can function as output signals, selection signals, transfer signals, start signals, reset signals, gate signals, or scan signals. It is assumed that signal GCK1 is input to wiring 512. Signal GCK1 corresponds to signal CK1 and can function as a clock signal. As an example, it is assumed that signal GCK2 is input to wiring 513. Signal GCK2 corresponds to signal CK2 and can function as an inverted clock signal. Yes. As an example, assume that voltage V2 is supplied to wiring 514. Wiring 515_1 ~515_2 are assumed to receive signals SEL1~SEL2 respectively, as an example. Assume that voltage V1 is supplied to wiring 516. Assume that signal GSP is input to wiring 517, as an example. Signal GSP corresponds to signal SP and can function as a start signal or a vertical synchronization signal. Assume that signal GRE is input to wiring 518, as an example. Signal GRE corresponds to signal RE and can function as a reset signal. However, it is not limited to this, and various other signals, various voltages, or various currents

[0291] can be input to these wirings. Note that wirings 511_1~511_N can function as signal lines, gate signal lines, or scanning lines. Wiring 512 and wiring 513 can function as signal lines or clock signal lines. Wiring 514 can function as a power supply line. Wirings 515_1~515_2 can function as signal lines. Wiring 516 can function as a power supply line or a ground line. Wiring 517 can function as a signal line. Wiring 518 can function as a signal line. However, it is not limited to this, and these wirings can function as various

[0292] other types of wirings. Note that signals or voltages etc. are input to wirings 512, 513, 514, It does so. Circuit 520 has a function of controlling the shift register by supplying a signal, voltage, etc. to the shift register, and can function as a control circuit, a controller, or the like. It has a function of controlling the shift register by supplying a signal, voltage, etc. to the shift register, and can function as a control circuit, a controller, or the like. It is possible.

[0293] Note that, as an example, circuit 520 is assumed to have circuit 521 and circuit 522. Circuit 521 has a function of generating power supply voltages such as a positive power supply voltage, a negative power supply voltage, a ground voltage, a reference voltage, etc., and can function as a power supply circuit or a regulator. Circuit 522 has a function of generating various signals such as a clock signal, an inverted clock signal, a start signal, a reset signal, and / or a video signal, and can function as a timing generator. However, it is not limited thereto, and circuit 520 can have various circuits or various elements in addition to circuit 521 and circuit 522. For example, circuit 520 can have an oscillator, a level shifter circuit, an inverter circuit, a buffer circuit, a DA conversion circuit, an AD conversion circuit, an operational amplifier, a shift register, a look-up table, a coil, a transistor, a capacitor element, a resistor element, and / or a frequency divider, etc. It has a function of generating power supply voltages such as a positive power supply voltage, a negative power supply voltage, a ground voltage, a reference voltage, etc., and can function as a power supply circuit or a regulator. It has a function of generating power supply voltages such as a positive power supply voltage, a negative power supply voltage, a ground voltage, a reference voltage, etc., and can function as a power supply circuit or a regulator. Circuit 52 2 has a function of generating various signals such as a clock signal, an inverted clock signal, a start signal, a reset signal, and / or a video signal, and can function as a timing generator. It has a function of generating various signals such as a clock signal, an inverted clock signal, a start signal, a reset signal, and / or a video signal, and can function as a timing generator. It is possible. However, it is not limited thereto, and circuit 520 can have various circuits or various elements in addition to circuit 521 and circuit 5 22. For example, circuit 52 0 can have an oscillator, a level shifter circuit, an inverter circuit, a buffer circuit, a DA conversion circuit, an AD conversion circuit, an operational amplifier, a shift register, a look-up table, a coil, a transistor, a capacitor element, a resistor element, and / or a frequency divider, etc.

[0294] Next, the operation of the shift register in FIG. 26 will be described with reference to FIG. 27. FIG. 27 is an example of a timing chart for explaining the operation of the shift register. FIG. 27 shows an example of signals GSP, signal GRE, signal GCK1, signal GCK2, signal SEL1, signal SEL2, signal GOUT_1, signal GOUT_i-1, signal GOUT_i, signal GOUT_i+1, and signal GOUT_N. Note that the description of the common part with the operation of the semiconductor device of Embodiments 1 to 3 will be omitted. signal GOUT_1, signal GOUT_i-1, signal GOUT_i, signal GOUT_i+1, and signal GOUT_N. Note that the description of the common part with the operation of the semiconductor device of Embodiments 1 to 3 will be omitted. It is omitted.

[0295] Describe the operation of flip - flop 501_i at the k - th (k is a natural number) frame. First, signal GOUT_i - 1 becomes high level. Then, flip - flop 501_ i starts operating in period A1, and signal GOUT_i becomes low level. After that, both signal GCK1 and signal GCK2 are inverted. Then, flip - flop 501_ i starts operating in period B1, and signal GOUT_i becomes high level. Signal GOUT _i is input as a reset signal to flip - flop 501_i - 1 and as a start signal to flip - flop 501_i + 1. Thus, flip - flop 501_ i - 1 starts operating in period C1, and flip - flop 501_i + 1 starts operating in period A1. After that, signal GCK1 and signal GCK2 are inverted again. Then, flip - flop 501_i + 1 starts operating in period B1, and signal GOUT_i + 1 becomes high level. Signal GOUT_i + 1 is input as a reset signal to flip - flop 501 _i. Therefore, flip - flop 501_i starts operating in period C1, so signal GOUT_i becomes low level. After that, until signal GOUT_i - 1 becomes high level again, flip - flop 501_i repeats the operations in period D1 and period E1 each time signal GCK1 and signal GCK2 are inverted.

[0296] Describe the operation of flip - flop 501_i at the (k + 1) - th frame. First, signal GOUT_i - 1 becomes high level. Then, flip - flop 501_i starts operating in period The operation in A2 starts and the signal GOUT_i becomes the L level. After that, the signals GCK1 , and GCK2 are inverted. Then, the flip-flop 501_i starts the operation in period B2 , and the signal GOUT_i becomes the H level. The signal GOUT_i is input as a reset signal to the flip-flop 501_i - 1 , and is input as a start signal to the flip-flop 501_i +1. Therefore, the flip-flop 501_i - 1 starts the operation in period C2 , and the flip-flop 501_i + 1 starts the operation in period A2 . After that, the signals GCK1 and GCK2 are inverted again. Then, the flip-flop 501_i + 1 starts the operation in period B1 , and the signal GOUT_i + 1 becomes the H level. The signal GOUT_i + 1 is input as a reset signal to the flip-flop 501_i. Therefore, since the flip-flop 501_i starts the operation in period C2 , the signal GOUT_i becomes the L level. After that, until the signal GOUT_i - 1 becomes the H level again, the flip-flop 501_i repeats the operation in period D2 and the operation in period E2 every time the signals GCK1 and GCK 2 are inverted.

[0297] Note that in the flip-flop 501_1, instead of the output signal of the previous-stage flip-flop , the signal GSP is input from the circuit 520 via the wiring 517. Therefore, when the signal GSP becomes the H level, the flip-flop 501_1 starts the operation in period A1 or period A2 .

[0298] Note that in the flip-flop 501_N, instead of the output signal of the next-stage flip-flop The signal GRE is input from the circuit 520 via the wiring 518. Therefore, when the signal GRE becomes the H level, the flip-flop 501_N starts the operation in the period C1 or the period C2.

[0299] As described above, the shift register of the present embodiment can obtain the same advantages as the semiconductor device by using the semiconductor devices of Embodiments 1 to 3.

[0300] Note that it is possible to make the relationship between the signal GCK1 and the signal GCK2 unbalanced. For example, as shown in the timing chart of FIG. 28(A), in the signals GCK1 and GCK2, it is possible to make the period in which the signal becomes the H level shorter than the period in which the signal becomes the L level. By doing so, even if a delay or rounding occurs in the signals GOUT_1 to GOUT_N, it is possible to prevent the periods in which these signals become the H level. Therefore, when the shift register of the present embodiment is used in a display device, it is possible to prevent a plurality of rows from being selected simultaneously. However, the present invention is not limited to this, and in the signal GCK1 and / or the signal GCK2, it is possible to make the period in which the signal becomes the H level longer than the period in which the signal becomes the L level.

[0301] Note that it is possible to input a multi-phase clock signal to the shift register. For example, as shown in the timing chart of FIG. 2 8(B), it is possible to use an M-phase (where M is a natural number of 3 or more) clock signal. In this case, in the signals GOUT_1 to GOUT_N, the period in which a certain stage becomes the H level can overlap with the periods in which the previous and subsequent stages become the H level. Therefore, when the present embodiment is used in a display device, a plurality of rows will be selected simultaneously. As a result, it becomes possible to use the video signal to other rows of pixels as a precharge voltage.

[0302] In addition, in FIG. 28(B), it is preferable that M≤8. More preferably, it is preferable that M≤6. Even more preferably, it is preferable that M≤4. This is because when the shift register is used in the scanning line drive circuit of the display device, if M is too large, multiple types of video signals will be written to the pixel. And since the period during which an incorrect video signal is input to the pixel becomes long, the display quality may deteriorate.

[0303] Similar to FIG. 28(B), in the timing chart of FIG. 28(A) as well, it is possible to use a multi-phase clock signal.

[0304] In addition, the wiring 518 and other wirings (for example, wiring 512, wiring 513, wiring 515_1, wiring 515_2, wiring 516, or wiring 517) can be configured with a single common wiring, and the wiring 518 can be omitted. In this case, in the flip-flop 501_N, it is preferable that the wiring 116 is connected to the wiring 512, wiring 513, wiring 515_1, wiring 515_2, wiring 516, or wiring 5 17. Also, it is possible to omit the wiring 518 by other configurations. In this case, in the flip-flop 501_N, it is also possible to omit the transistors 303_1~ 303_2 and the transistor 304.

[0305] In addition, as shown in FIG. 29, it is possible to divide the output signal. In an example of FIG. 29, as the flip-flops 501_1~501_N, the semiconductor devices of FIG. 10(E) are used respectively. is possible. And, in flip-flop 501_i (where i is any one of 2 to N), wiring 111, wiring 112, wiring 113, wiring 114, wiring 115_1, wiring 115_2, wiring 116, and wiring 117 are respectively connected to wiring 511_i, wiring 512, wiring 514, wiring 518_i-1, wiring 515_1, wiring 515_2, wiring 511_i+1, and wiring 516 are connected. By doing so, even when loads such as pixel or gate signal lines are connected to wiring 511_1 to 511_N, there will be no distortion or delay in the transfer signal for driving the flip-flop in the next stage. Therefore, the influence of the delay of the shift register can be reduced. However, it is not limited to this. Wiring 114 can be connected to wiring 511_i-1 . Or, wiring 116 can be connected to wiring 517_i+1 .

[0306] (Embodiment 5) In this embodiment, an example of a display device will be described.

[0307] First, referring to FIG. 30(A), an example of the system block of a liquid crystal display device will be described. The liquid crystal display device includes a circuit 5361, a circuit 5362, a circuit 5363_1, a circuit 5363_ 2, a pixel portion 5364 having pixels, a circuit 5365, and an illumination device 5366. In the pixel portion 5364, a plurality of wirings 5371 are arranged extending from the circuit 5362, and a plurality of wirings 5372 are arranged extending from the circuit 5363_1 and the circuit 5363_2. And in the intersection region of the plurality of wirings 5371 and the plurality of wirings 5372, pixels 5367 each having a display element such as a liquid crystal element are arranged in a matrix.

[0308] ​In response to a video signal 5360, a circuit 5361 outputs a signal to a circuit 5362, a circuit 5363_1, a circuit 5363_2 and the circuit 5365 have a function of supplying a signal, a voltage, a current, or the like, Controller, control circuit, timing generator, power supply circuit, regulator, etc. In this embodiment, as an example, the circuit 5361 can function as a circuit 5362, the start signal for the signal line driver circuit (SSP), the clock signal for the signal line driver circuit (SCK), inverted clock signal for signal line driver circuit (SCKB), data for video signal (D ATA) and a latch signal (LAT). Then, a start signal for the scanning line driver circuit (G SP), clock signal for the scanning line driving circuit (GCK), and clock signal for the inversion scanning line driving circuit Alternatively, the circuit 5361 may supply a buffer signal (GCKB) to the circuit 5365. However, the present invention is not limited to this, and may be applied to the circuit 5. 361 also transmits various signals, various voltages, or various currents to a circuit 5362, a circuit It is possible to supply the signal to the circuits 5363_1, 5363_2, and 5365.

[0309] The circuit 5362 receives signals (e.g., SSP, SCK, SCKB , DATA, LAT) to output video signals to a plurality of wirings 5371. The circuit 5363_1 and the circuit 536 3_2 runs according to the signals (GSP, GCK, GCKB) supplied from the circuit 5361. It has a function of outputting scanning signals to a plurality of wirings 5372 and functions as a scanning line driver circuit. is possible. Circuit 5365 controls the amount of power supplied to lighting device 5366, or the time, etc., according to the signal (BLC) supplied from circuit 5361, and has the function of controlling the brightness (or average brightness) of lighting device 5366, and can function as a power supply circuit. is possible.

[0310] When a video signal is input to a plurality of wirings 5371, the plurality of wirings 5371 can function as signal lines, video signal lines, source signal lines, etc. When a scanning signal is input to a plurality of wirings 5372, the plurality of wirings 5372 can function as signal lines, scanning lines, gate signal lines, etc. However, it is not limited to this. is possible.

[0311] When the same signal is input to each of circuit 5363_1 and circuit 5363_2 from circuit 5361, the scanning signal output from circuit 5363_1 to a plurality of wirings 5372 and the scanning signal output from circuit 5363_2 to a plurality of wirings 5372 are often in approximately the same timing. Therefore, the load driven by circuit 5363_1 and circuit 5363_2 can be reduced. Thus, the display device can be enlarged. Or, the display device can be made high-definition. Or, since the channel width of the transistors included in circuit 5363_1 and circuit 5363_2 can be reduced, a display device with a narrow bezel can be obtained. However, it is not limited to this, and circuit 5361 can supply different signals to circuit 5363_1 and circuit 5363_2. obtained. However, it is not limited to this, and circuit 5361 can supply different signals to circuit 5363_1 and circuit 5363_2.

[0312] It is possible to omit either one of circuit 5363_1 and circuit 5363_2. ​​​​​​​

[0313] Note that it is possible to newly arrange wirings such as capacitance lines, power supply lines, and scanning lines in the pixel section 5364. And the circuit 5361 can output signals or voltages or the like to these wirings. Alternatively, a circuit similar to the circuit 5363_1 or the circuit 5363_2 can be newly added. This newly added circuit can output signals such as scanning signals to the newly added wirings.

[0314] Note that the pixel 5367 can have a light-emitting element such as an EL element as a display element. In this case, as shown in FIG. 30(B), since the display element can emit light, the circuit 5 365 and the lighting device 5366 can be omitted. And, in order to supply power to the display element, a plurality of wirings 5373 that can function as power supply lines can be arranged in the pixel section 53 64. The circuit 5361 can supply a power supply voltage (also referred to as voltage ANO) to the wiring 5373. This wiring 5373 can be connected separately for each color element of the pixel or can be commonly connected to all pixels.

[0315] Note that in FIG. 30(B), as an example, the circuit 5361 shows an example of a case where separate signals are supplied to the circuit 5363_1 and the circuit 536 3_2. The circuit 5361 supplies signals such as a start signal (GSP1) for the scanning line driving circuit, a clock signal (GCK1) for the scanning line driving circuit, and a clock signal (GCKB1) for the inverted scanning line driving circuit to the circuit 5363_1. Then, the circuit 5361 supplies signals such as a start signal (GSP2) for the scanning line driving circuit, a clock signal (GCK2) for the scanning line driving circuit, and a clock signal (GCKB2) for the inverted scanning line driving circuit to the circuit 536 3_2. Supply the signal to circuit 5363_2. In this case, circuit 5363_1 scans only the wirings in the odd rows among the plurality of wirings 53 72, and circuit 5363_2 can scan only the wirings in the even rows among the plurality of wirings 5372. Therefore, since the driving frequencies of circuit 5363_1 and circuit 5363_2 can be decreased, power consumption can be reduced. Or, the area where one stage of flip-flops can be laid out can be increased. Therefore, the display device can be made high-definition. Or, the display device can be made larger. However, it is not limited to this. Similar to FIG. 30(A), circuit 5361 can output the same signal to circuit 5363_1 and circuit 5363_2. As shown in FIG. 30(B), in FIG. 30(A) as well, circuit 5361 can supply different signals to circuit 5363_1 and circuit 5363_2. The above is an explanation of an example of the system block of the display device. Next, an example of the configuration of the display device will be described with reference to FIGS. 31(A), (B), (C), (D), and ( E). In FIG. 31(A), circuits having a function of outputting signals to pixel section 5364 (for example, circuit 5

[0316] 362, circuit 5363_1, and circuit 5363_2, etc.) are formed on the same substrate 5380 as pixel section 5364. And circuit 5361 is formed on a substrate different from pixel section 5364. Thus, the number of external components is reduced, so cost reduction can be achieved. Or, since the number of signals or voltages input to substrate 5380 is reduced, the connection between substrate 5380 and external components

[0317] The above is an explanation of an example of the system block of the display device.

[0318] Next, an example of the configuration of the display device will be described with reference to FIGS. 31(A), (B), (C), (D), and ( E).

[0319] In FIG. 31(A), circuits having a function of outputting signals to pixel section 5364 (for example, circuit 5 362, circuit 5363_1, and circuit 5363_2, etc.) are formed on the same substrate 5380 as pixel section 5364. And circuit 5361 is formed on a substrate different from pixel section 5364. Thus, the number of external components is reduced, so cost reduction can be achieved. Or, since the number of signals or voltages input to substrate 5380 is reduced, the connection between substrate 5380 and external components can be simplified, and the reliability of the connection can be improved. can be simplified, and the reliability of the connection can be improved. The number of consecutive counts can be reduced. Therefore, it is possible to improve reliability or yield.

[0320] When the circuit is formed on a substrate different from the pixel portion 5364, the substrate can be mounted on an FPC (Flexible Printed Circuit) by the TAB (Tape Automated Bonding) method. Or, the substrate can be mounted on the same substrate 5380 as the pixel portion 5364 by the COG (Chip on Glass) method. Printed Circuit) by the TAB (Tape Automated Bonding) method. is possible. Or, the substrate can be mounted on the same substrate 5380 as the pixel portion 5364 by the COG (Chip on Glass) method.

[0321] When the circuit is formed on a substrate different from the pixel portion 5364, a transistor using a single crystal semiconductor can be formed on the substrate. Therefore, the circuit formed on the substrate can set a drive frequency over a wide range. For example, by increasing the drive frequency, the number of pixels arranged in the pixel portion 5364 can be increased (the resolution can be increased). By reducing the drive voltage, the power consumption can be reduced. Also, since the circuit formed on the substrate can increase the drive voltage, a display element having a large drive voltage can be used as the display element. Also, the circuit formed on the substrate can reduce the variation in the output signal. a transistor using a single crystal semiconductor can be formed on the substrate. Therefore, the circuit formed on the substrate can set a drive frequency over a wide range. For example, by increasing the drive frequency, the number of pixels arranged in the pixel portion 5364 can be increased (the resolution can be increased). By reducing the drive voltage, the power consumption can be reduced. By doing so, the number of pixels arranged in the pixel portion 5364 can be increased (the resolution can be increased). can be increased). By reducing the drive voltage, the power consumption can be reduced. Also since the circuit formed on the substrate can increase the drive voltage, a display element having a large drive voltage can be used as the display element. Also, the circuit formed on the substrate can increase the drive voltage, a display element having a large drive voltage can be used as the display element. Also, the circuit formed on the substrate can reduce the variation in the output signal.

[0322] In many cases, signals, voltages, currents, etc. are input from an external circuit via the input terminal 5381.

[0323] In FIG. 31(B), the drive frequencies of the circuits 5363_1 and 5363_2 are often lower than the drive frequency of the circuit 536 1 or the circuit 5362, and the transistors formed in the pixel portion​​​ The transistors formed in the same process as the [ta] can be used for circuit 5363_1 and circuit 5363_2. Therefore, circuit 5363_1 and circuit 5363_2 are formed on the same substrate 5380 as the pixel section 5364. And circuit 5361 and circuit 5362 are formed on a substrate different from the pixel section 5 364. In this way, it becomes possible to configure the circuit formed on the substrate 5380 with transistors having a small mobility. Thus, as the semiconductor layer of the transistor, it is possible to use an amorphous semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like. Therefore, it is possible to achieve an increase in the size of the display device, a reduction in the number of processes, a reduction in cost, or an improvement in yield. Note that, as shown in FIG. 31(C), a part of circuit 5362 (circuit 5362a) can be formed on the same substrate 5380 as the pixel section 53 64, and the remaining part of circuit 5362 (circuit 5362b) can be formed on a substrate different from the pixel section 5364. Circuit 5362a is a circuit that can be configured by transistors having a low mobility (for example, a shift register, a selector, a switch, etc.) in many cases. And circuit 5362b is preferably a circuit that can be configured by transistors having a high mobility and small characteristic variations (for example, a shift register, a latch circuit, a buffer circuit, a DA conversion circuit, an AD conversion circuit, etc.)

[0324] in many cases. By doing so, as in FIG. 31(B), as the semiconductor layer of the transistor, for example, an amorphous semiconductor, a microcrystalline semiconductor, an organic semiconductor, or an oxide semiconductor can be used, and further reduction of external components can be achieved.

[0325] In FIG. 31(D), circuits having a function of outputting signals to the pixel section 5364 (for example, circuit 5 362, circuit 5363_1, and circuit 5363_2, etc.), and circuits having a function of controlling these circuits (for example, circuit 5361) are formed on a substrate different from the pixel section 5364 . Thus, since the pixel section and its peripheral circuits can be formed on separate substrates , the yield can be improved.

[0326] Note that, similar to FIG. 31(D), in FIGS. 31(A) to (C) as well, circuit 5363_1 and circuit 5363_2 can be formed on a substrate different from the pixel section 5364.

[0327] In FIG. 31(E), a part of circuit 5361 (circuit 5361a) is formed on the same substrate 5380 as the pixel section 5364, and the remaining circuit 5361 (circuit 5361b) is formed on a substrate different from the pixel section 5364. Circuit 5361a often has circuits (for example, switches, selectors, level shifters, etc.) that can be configured by transistors with low mobility. And circuit 5361b often has circuits (for example, shift registers, timing generators, oscillators, regulators, or analog buffers, etc.) that are preferably configured using transistors with high mobility and small variation.

[0328] Note that, in FIGS. 31(A) to (D) as well, circuit 5361a can be formed on the same substrate as the pixel section 5364 and circuit 5361b can be formed on a substrate different from the pixel section 5364.

[0329] Here, as circuit 5363_1 and circuit 5363_2, in Embodiments 1 to 4 It is possible to use a semiconductor device or a shift register. In this case, by forming circuit 5363_ 1 and circuit 5363_2 and the pixel portion on the same substrate, it is possible to make the polarity of all the transistors formed on the substrate either N-channel type or P-channel type. Therefore, it is possible to reduce the number of processes, improve the yield, improve the reliability, or reduce the cost. In particular, when the polarity of all the transistors is N-channel type, it is possible to use an amorphous semiconductor, a microcrystalline semiconductor, an organic semiconductor, or an oxide semiconductor as the semiconductor layer of the transistor. Thus, it is possible to increase the size of the display device, reduce the cost, or improve the yield.

[0330] Alternatively, the semiconductor device or the shift register according to Embodiments 1 to 4 can reduce the channel width of the transistor. Therefore, the layout area can be reduced, so that the frame can be made smaller. Or, since the layout area can be reduced, the resolution can be increased. Alternatively, the semiconductor device or the shift register according to Embodiments 1 to 4 can reduce the parasitic capacitance.

[0331] Therefore, the power consumption can be reduced. Or, the current capacity of the external circuit can be reduced. Or, the size of the external circuit or the size of the display device having the external circuit can be reduced. Note that a transistor using an amorphous semiconductor, a microcrystalline semiconductor, an organic semiconductor, or an oxide semiconductor as the semiconductor layer may cause characteristic degradation such as an increase in the threshold voltage or a decrease in the mobility.

[0332] ​​There are many combinations. However, the semiconductor devices or shift registers of Embodiments 1 to 4 can suppress the characteristic degradation of the transistors, so the lifespan of the display device can be extended.

[0333] Note that as a part of Circuit 5362, it is possible to use the semiconductor devices or shift registers of Embodiments 1 to 4. For example, Circuit 5362a can have the semiconductor devices or shift registers of Embodiments 1 to 4.

[0334] (Embodiment 6) In this embodiment, an example of a signal line driving circuit will be described. Note that the signal line driving circuit can be shown as a semiconductor device or a signal generation circuit.

[0335] An example of the signal line driving circuit will be described with reference to FIG. 32(A). The signal line driving circuit includes a plurality of circuits such as Circuits 602_1 to 602_N, Circuit 600, and Circuit 601. And each of Circuits 602_1 to 602_N has a plurality of transistors such as Transistors 603_1 to 603_k (k is a natural number of 2 or more). Transistors 603_1 to 603_k are assumed to be N-channel type. However, it is not limited thereto, and Transistors 603_1 to 603_k can be P-channel type or can be CMOS switches.

[0336] The connection relationship of the signal line driving circuit will be described taking Circuit 602_1 as an example. The first terminals of Transistors 603_1 to 603_k are connected to Wiring 605_1. The second terminals of Transistors 603_1 to 603_k are each connected to Wirings S1 to Sk. Transistor 6 The gates of 03_1 to 603_k are each connected to wirings 604_1 to 604_k. For example For example, the first terminal of transistor 603_1 is connected to wiring 605_1, and the second terminal of transistor 603_1 is connected to wiring S1, and the gate of transistor 603_1 is connected to wiring 604_1.

[0337] Circuit 600 has a function of supplying signals to circuits 602_1 to 602_N via wirings 604_1 to 604_k, and can function as a shift register, a decoder, or the like. The signal is often a digital signal and can function as a selection signal. And wirings 604_1 to 604_k can function as signal lines.

[0338] Circuit 601 has a function of outputting signals to circuits 602_1 to 602_N, and can function as a video signal generation circuit or the like. For example, circuit 601 supplies a signal to circuit 602_1 via wiring 605_1. At the same time, it supplies a signal to circuit 602_2 via wiring 605_2. The signal is often an analog signal and can function as a video signal. And wirings 605_1 to 605_N can function as signal lines.

[0339] Circuits 602_1 to 602_N have a function of selecting which wiring to output the output signal of circuit 601 to, and can function as a selector circuit. For example, circuit 602 _1 has a function of selecting which of wirings S1 to Sk to output the signal that circuit 601 outputs to wiring 605_1.

[0340] Transistors 603_1 to 603_N each have a function of controlling the conduction state between wiring 6 05_1 and wiring S1 to Sk according to the output signal of circuit 600, and function as switches.

[0341] Next, the operation of the signal line driving circuit in Fig. 32(A) will be described with reference to the timing chart in Fig. 32(B). In Fig. 32(B), examples of signals 614_1 input to wiring 604_1, signals 614_2 input to wiring 604_2, signals 614 _k input to wiring 604_k, signals 615_1 input to wiring 605_1, and signals 615_2 input to wiring 605_2 are shown. Moreover, one operation period of the signal line driving circuit corresponds to one gate selection period in the display device. The one gate selection period refers to a period during which pixels belonging to a certain row are selected and a video signal can be written to the pixels.

[0342] Note that the one gate selection period is divided into period T0 and periods T1 to Tk. Period T0 is a period for simultaneously applying a precharge voltage to the pixels belonging to the selected row, and can function as a precharge period. Periods T1 to Tk are each a period for writing a video signal to the pixels belonging to the selected row, and can function as write periods.

[0343] For the sake of convenience, the operation of the signal line driving circuit will be described by taking the operation of circuit 602_1 as an example. First, in period T0, circuit 600 outputs H-level signals to wiring 604_1 to 604_k....

Claims

1. A multi-stage circuit, at least one of the multiple-stage circuits includes first to fourth transistors and first to sixth wirings; one of a source electrode and a drain electrode of the first transistor is always electrically connected to the first wiring; the other of the source electrode and the drain electrode of the first transistor is always electrically connected to the second wiring; one of a source electrode and a drain electrode of the second transistor is always electrically connected to the first wiring; the other of the source electrode and the drain electrode of the second transistor is always electrically connected to the third wiring; one of a source electrode and a drain electrode of the third transistor is always electrically connected to a gate electrode of the first transistor; the other of the source electrode and the drain electrode of the third transistor is always electrically connected to the fourth wiring; a gate electrode of the third transistor is always electrically connected to the sixth wiring; one of the source electrode and the drain electrode of the fourth transistor is always electrically connected to the gate electrode of the second transistor; the other of the source electrode and the drain electrode of the fourth transistor is always electrically connected to the fifth wiring; a gate electrode of the fourth transistor is always electrically connected to the sixth wiring; the first wiring has a function of outputting a first signal, the second wiring has a function as a first signal line, the third wiring has a function as a second signal line, the fourth wiring has a function as a third signal line, the fifth wiring has a function as a fourth signal line, a first conductive film functioning as one of a source electrode and a drain electrode of the first transistor and a second conductive film functioning as one of a source electrode and a drain electrode of the second transistor; the first conductive film has a region overlapping with a second conductive film that functions as a gate electrode of the second transistor; Semiconductor device.

2. A multi-stage circuit, at least one of the multiple-stage circuits includes first to fourth transistors and first to sixth wirings; one of a source electrode and a drain electrode of the first transistor is always electrically connected to the first wiring; the other of the source electrode and the drain electrode of the first transistor is always electrically connected to the second wiring; one of a source electrode and a drain electrode of the second transistor is always electrically connected to the first wiring; the other of the source electrode and the drain electrode of the second transistor is always electrically connected to the third wiring; one of a source electrode and a drain electrode of the third transistor is always electrically connected to a gate electrode of the first transistor; the other of the source electrode and the drain electrode of the third transistor is always electrically connected to the fourth wiring; a gate electrode of the third transistor is always electrically connected to the sixth wiring; one of the source electrode and the drain electrode of the fourth transistor is always electrically connected to the gate electrode of the second transistor; the other of the source electrode and the drain electrode of the fourth transistor is always electrically connected to the fifth wiring; a gate electrode of the fourth transistor is always electrically connected to the sixth wiring; the first wiring has a function of outputting a first signal, the second wiring has a function as a first signal line, the third wiring has a function as a second signal line, the fourth wiring has a function as a third signal line, the fifth wiring has a function as a fourth signal line, a signal that is out of phase with the signal input to the fourth wiring is input to the fifth wiring, a first conductive film functioning as one of a source electrode and a drain electrode of the first transistor and a second conductive film functioning as one of a source electrode and a drain electrode of the second transistor; the first conductive film has a region overlapping with a second conductive film that functions as a gate electrode of the second transistor; Semiconductor device.

3. A multi-stage circuit, at least one of the multiple-stage circuits includes first to fourth transistors and first to sixth wirings; one of a source electrode and a drain electrode of the first transistor is always electrically connected to the first wiring; the other of the source electrode and the drain electrode of the first transistor is always electrically connected to the second wiring; one of a source electrode and a drain electrode of the second transistor is always electrically connected to the first wiring; the other of the source electrode and the drain electrode of the second transistor is always electrically connected to the third wiring; one of a source electrode and a drain electrode of the third transistor is always electrically connected to a gate electrode of the first transistor; the other of the source electrode and the drain electrode of the third transistor is always electrically connected to the fourth wiring; a gate electrode of the third transistor is always electrically connected to the sixth wiring; one of the source electrode and the drain electrode of the fourth transistor is always electrically connected to the gate electrode of the second transistor; the other of the source electrode and the drain electrode of the fourth transistor is always electrically connected to the fifth wiring; a gate electrode of the fourth transistor is always electrically connected to the sixth wiring; the first wiring has a function of outputting a first signal, the second wiring has a function as a first signal line, the third wiring has a function as a second signal line, the fourth wiring has a function as a third signal line, the fifth wiring has a function as a fourth signal line, a first conductive film functioning as one of a source electrode and a drain electrode of the first transistor and a second conductive film functioning as one of a source electrode and a drain electrode of the second transistor; the first conductive film has a region overlapping with a second conductive film that functions as a gate electrode of the second transistor; the third conductive film having a function as a gate electrode of the third transistor has a function as a gate electrode of the fourth transistor; Semiconductor device.

4. A multi-stage circuit, at least one of the multiple-stage circuits includes first to fourth transistors and first to sixth wirings; one of a source electrode and a drain electrode of the first transistor is always electrically connected to the first wiring; the other of the source electrode and the drain electrode of the first transistor is always electrically connected to the second wiring; one of a source electrode and a drain electrode of the second transistor is always electrically connected to the first wiring; the other of the source electrode and the drain electrode of the second transistor is always electrically connected to the third wiring; one of a source electrode and a drain electrode of the third transistor is always electrically connected to a gate electrode of the first transistor; the other of the source electrode and the drain electrode of the third transistor is always electrically connected to the fourth wiring; a gate electrode of the third transistor is always electrically connected to the sixth wiring; one of the source electrode and the drain electrode of the fourth transistor is always electrically connected to the gate electrode of the second transistor; the other of the source electrode and the drain electrode of the fourth transistor is always electrically connected to the fifth wiring; a gate electrode of the fourth transistor is always electrically connected to the sixth wiring; the first wiring has a function of outputting a first signal, the second wiring has a function as a first signal line, the third wiring has a function as a second signal line, the fourth wiring has a function as a third signal line, the fifth wiring has a function as a fourth signal line, a signal that is out of phase with the signal input to the fourth wiring is input to the fifth wiring, a first conductive film functioning as one of a source electrode and a drain electrode of the first transistor and a second conductive film functioning as one of a source electrode and a drain electrode of the second transistor; the first conductive film has a region overlapping with a second conductive film that functions as a gate electrode of the second transistor; the third conductive film having a function as a gate electrode of the third transistor has a function as a gate electrode of the fourth transistor; Semiconductor device.

5. A multi-stage circuit, at least one of the multiple-stage circuits includes first to fourth transistors and first to sixth wirings; one of a source electrode and a drain electrode of the first transistor is always electrically connected to the first wiring; the other of the source electrode and the drain electrode of the first transistor is always electrically connected to the second wiring; one of a source electrode and a drain electrode of the second transistor is always electrically connected to the first wiring; the other of the source electrode and the drain electrode of the second transistor is always electrically connected to the third wiring; one of a source electrode and a drain electrode of the third transistor is always electrically connected to a gate electrode of the first transistor; the other of the source electrode and the drain electrode of the third transistor is always electrically connected to the fourth wiring; a gate electrode of the third transistor is always electrically connected to the sixth wiring; one of the source electrode and the drain electrode of the fourth transistor is always electrically connected to the gate electrode of the second transistor; the other of the source electrode and the drain electrode of the fourth transistor is always electrically connected to the fifth wiring; a gate electrode of the fourth transistor is always electrically connected to the sixth wiring; the first wiring has a function of outputting a first signal, the second wiring has a function as a first signal line, the third wiring has a function as a second signal line, the fourth wiring has a function as a third signal line, the fifth wiring has a function as a fourth signal line, a first conductive film functioning as one of a source electrode and a drain electrode of the first transistor has a region overlapping with a second conductive film functioning as a gate electrode of the second transistor; Semiconductor device.

6. A multi-stage circuit, at least one of the multiple-stage circuits includes first to fourth transistors and first to sixth wirings; one of a source electrode and a drain electrode of the first transistor is always electrically connected to the first wiring; the other of the source electrode and the drain electrode of the first transistor is always electrically connected to the second wiring; one of a source electrode and a drain electrode of the second transistor is always electrically connected to the first wiring; the other of the source electrode and the drain electrode of the second transistor is always electrically connected to the third wiring; one of a source electrode and a drain electrode of the third transistor is always electrically connected to a gate electrode of the first transistor; the other of the source electrode and the drain electrode of the third transistor is always electrically connected to the fourth wiring; a gate electrode of the third transistor is always electrically connected to the sixth wiring; one of the source electrode and the drain electrode of the fourth transistor is always electrically connected to the gate electrode of the second transistor; the other of the source electrode and the drain electrode of the fourth transistor is always electrically connected to the fifth wiring; a gate electrode of the fourth transistor is always electrically connected to the sixth wiring; the first wiring has a function of outputting a first signal, the second wiring has a function as a first signal line, the third wiring has a function as a second signal line, the fourth wiring has a function as a third signal line, the fifth wiring has a function as a fourth signal line, a first conductive film functioning as one of a source electrode and a drain electrode of the first transistor has a region overlapping with a second conductive film functioning as a gate electrode of the second transistor; the third conductive film having a function as a gate electrode of the third transistor has a function as a gate electrode of the fourth transistor; Semiconductor device.

7. A multi-stage circuit, at least one of the multiple-stage circuits includes first to fourth transistors and first to sixth wirings; one of a source electrode and a drain electrode of the first transistor is always electrically connected to the first wiring; the other of the source electrode and the drain electrode of the first transistor is always electrically connected to the second wiring; one of a source electrode and a drain electrode of the second transistor is always electrically connected to the first wiring; the other of the source electrode and the drain electrode of the second transistor is always electrically connected to the third wiring; one of a source electrode and a drain electrode of the third transistor is always electrically connected to a gate electrode of the first transistor; the other of the source electrode and the drain electrode of the third transistor is always electrically connected to the fourth wiring; a gate electrode of the third transistor is always electrically connected to the sixth wiring; one of the source electrode and the drain electrode of the fourth transistor is always electrically connected to the gate electrode of the second transistor; the other of the source electrode and the drain electrode of the fourth transistor is always electrically connected to the fifth wiring; a gate electrode of the fourth transistor is always electrically connected to the sixth wiring; the first wiring has a function of outputting a first signal, the second wiring has a function as a first signal line, the third wiring has a function as a second signal line, the fourth wiring has a function as a third signal line, the fifth wiring has a function as a fourth signal line, a signal that is out of phase with the signal input to the fourth wiring is input to the fifth wiring, a first conductive film functioning as one of a source electrode and a drain electrode of the first transistor has a region overlapping with a second conductive film functioning as a gate electrode of the second transistor; Semiconductor device.

8. A multi-stage circuit, at least one of the multiple-stage circuits includes first to fourth transistors and first to sixth wirings; one of a source electrode and a drain electrode of the first transistor is always electrically connected to the first wiring; the other of the source electrode and the drain electrode of the first transistor is always electrically connected to the second wiring; one of a source electrode and a drain electrode of the second transistor is always electrically connected to the first wiring; the other of the source electrode and the drain electrode of the second transistor is always electrically connected to the third wiring; one of a source electrode and a drain electrode of the third transistor is always electrically connected to a gate electrode of the first transistor; the other of the source electrode and the drain electrode of the third transistor is always electrically connected to the fourth wiring; a gate electrode of the third transistor is always electrically connected to the sixth wiring; one of the source electrode and the drain electrode of the fourth transistor is always electrically connected to the gate electrode of the second transistor; the other of the source electrode and the drain electrode of the fourth transistor is always electrically connected to the fifth wiring; a gate electrode of the fourth transistor is always electrically connected to the sixth wiring; the first wiring has a function of outputting a first signal, the second wiring has a function as a first signal line, the third wiring has a function as a second signal line, the fourth wiring has a function as a third signal line, the fifth wiring has a function as a fourth signal line, a signal that is out of phase with the signal input to the fourth wiring is input to the fifth wiring, a first conductive film functioning as one of a source electrode and a drain electrode of the first transistor has a region overlapping with a second conductive film functioning as a gate electrode of the second transistor; the third conductive film having a function as a gate electrode of the third transistor has a function as a gate electrode of the fourth transistor; Semiconductor device.

9. A pixel array device comprising: a pixel; and a gate driver formed on the same substrate as the pixel; the gate driver has a multi-stage circuit, at least one of the multiple-stage circuits includes first to fourth transistors and first to sixth wirings; the pixel has a fifth transistor; one of a source electrode and a drain electrode of the first transistor is always electrically connected to the first wiring; the other of the source electrode and the drain electrode of the first transistor is always electrically connected to the second wiring; one of a source electrode and a drain electrode of the second transistor is always electrically connected to the first wiring; the other of the source electrode and the drain electrode of the second transistor is always electrically connected to the third wiring; one of a source electrode and a drain electrode of the third transistor is always electrically connected to a gate electrode of the first transistor; the other of the source electrode and the drain electrode of the third transistor is always electrically connected to the fourth wiring; a gate electrode of the third transistor is always electrically connected to the sixth wiring; one of the source electrode and the drain electrode of the fourth transistor is always electrically connected to the gate electrode of the second transistor; the other of the source electrode and the drain electrode of the fourth transistor is always electrically connected to the fifth wiring; a gate electrode of the fourth transistor is always electrically connected to the sixth wiring; the first wiring has a function of outputting a first signal, the second wiring has a function as a first signal line, the third wiring has a function as a second signal line, the fourth wiring has a function as a third signal line, the fifth wiring has a function as a fourth signal line, a first conductive film functioning as one of a source electrode and a drain electrode of the first transistor and a second conductive film functioning as one of a source electrode and a drain electrode of the second transistor; the first conductive film has a region overlapping with a second conductive film that functions as a gate electrode of the second transistor; the fifth transistor has an oxide semiconductor film. Display device.

10. A pixel array device comprising: a pixel; and a gate driver formed on the same substrate as the pixel; the gate driver has a multi-stage circuit, at least one of the multiple-stage circuits includes first to fourth transistors and first to sixth wirings; the pixel has a fifth transistor; one of a source electrode and a drain electrode of the first transistor is always electrically connected to the first wiring; the other of the source electrode and the drain electrode of the first transistor is always electrically connected to the second wiring; one of a source electrode and a drain electrode of the second transistor is always electrically connected to the first wiring; the other of the source electrode and the drain electrode of the second transistor is always electrically connected to the third wiring; one of a source electrode and a drain electrode of the third transistor is always electrically connected to a gate electrode of the first transistor; the other of the source electrode and the drain electrode of the third transistor is always electrically connected to the fourth wiring; a gate electrode of the third transistor is always electrically connected to the sixth wiring; one of the source electrode and the drain electrode of the fourth transistor is always electrically connected to the gate electrode of the second transistor; the other of the source electrode and the drain electrode of the fourth transistor is always electrically connected to the fifth wiring; a gate electrode of the fourth transistor is always electrically connected to the sixth wiring; the first wiring has a function of outputting a first signal, the second wiring has a function as a first signal line, the third wiring has a function as a second signal line, the fourth wiring has a function as a third signal line, the fifth wiring has a function as a fourth signal line, a signal that is out of phase with the signal input to the fourth wiring is input to the fifth wiring, a first conductive film functioning as one of a source electrode and a drain electrode of the first transistor and a second conductive film functioning as one of a source electrode and a drain electrode of the second transistor; the first conductive film has a region overlapping with a second conductive film that functions as a gate electrode of the second transistor; the fifth transistor has an oxide semiconductor film. Display device.

11. A pixel array device comprising: a pixel; and a gate driver formed on the same substrate as the pixel; the gate driver has a multi-stage circuit, at least one of the multiple-stage circuits includes first to fourth transistors and first to sixth wirings; the pixel has a fifth transistor; one of a source electrode and a drain electrode of the first transistor is always electrically connected to the first wiring; the other of the source electrode and the drain electrode of the first transistor is always electrically connected to the second wiring; one of a source electrode and a drain electrode of the second transistor is always electrically connected to the first wiring; the other of the source electrode and the drain electrode of the second transistor is always electrically connected to the third wiring; one of a source electrode and a drain electrode of the third transistor is always electrically connected to a gate electrode of the first transistor; the other of the source electrode and the drain electrode of the third transistor is always electrically connected to the fourth wiring; a gate electrode of the third transistor is always electrically connected to the sixth wiring; one of the source electrode and the drain electrode of the fourth transistor is always electrically connected to the gate electrode of the second transistor; the other of the source electrode and the drain electrode of the fourth transistor is always electrically connected to the fifth wiring; a gate electrode of the fourth transistor is always electrically connected to the sixth wiring; the first wiring has a function of outputting a first signal, the second wiring has a function as a first signal line, the third wiring has a function as a second signal line, the fourth wiring has a function as a third signal line, the fifth wiring has a function as a fourth signal line, a first conductive film functioning as one of a source electrode and a drain electrode of the first transistor and a second conductive film functioning as one of a source electrode and a drain electrode of the second transistor; the first conductive film has a region overlapping with a second conductive film that functions as a gate electrode of the second transistor; the third conductive film having a function as a gate electrode of the third transistor has a function as a gate electrode of the fourth transistor; the fifth transistor has an oxide semiconductor film. Display device.

12. A pixel array device comprising: a pixel; and a gate driver formed on the same substrate as the pixel; the gate driver has a multi-stage circuit, at least one of the multiple-stage circuits includes first to fourth transistors and first to sixth wirings; the pixel has a fifth transistor; one of a source electrode and a drain electrode of the first transistor is always electrically connected to the first wiring; the other of the source electrode and the drain electrode of the first transistor is always electrically connected to the second wiring; one of a source electrode and a drain electrode of the second transistor is always electrically connected to the first wiring; the other of the source electrode and the drain electrode of the second transistor is always electrically connected to the third wiring; one of a source electrode and a drain electrode of the third transistor is always electrically connected to a gate electrode of the first transistor; the other of the source electrode and the drain electrode of the third transistor is always electrically connected to the fourth wiring; a gate electrode of the third transistor is always electrically connected to the sixth wiring; one of the source electrode and the drain electrode of the fourth transistor is always electrically connected to the gate electrode of the second transistor; the other of the source electrode and the drain electrode of the fourth transistor is always electrically connected to the fifth wiring; a gate electrode of the fourth transistor is always electrically connected to the sixth wiring; the first wiring has a function of outputting a first signal, the second wiring has a function as a first signal line, the third wiring has a function as a second signal line, the fourth wiring has a function as a third signal line, the fifth wiring has a function as a fourth signal line, a signal that is out of phase with the signal input to the fourth wiring is input to the fifth wiring, a first conductive film functioning as one of a source electrode and a drain electrode of the first transistor and a second conductive film functioning as one of a source electrode and a drain electrode of the second transistor; the first conductive film has a region overlapping with a second conductive film that functions as a gate electrode of the second transistor; the third conductive film having a function as a gate electrode of the third transistor has a function as a gate electrode of the fourth transistor; the fifth transistor has an oxide semiconductor film. Display device.

13. A pixel array device comprising: a pixel; and a gate driver formed on the same substrate as the pixel; the gate driver has a multi-stage circuit, at least one of the multiple-stage circuits includes first to fourth transistors and first to sixth wirings; the pixel has a fifth transistor; one of a source electrode and a drain electrode of the first transistor is always electrically connected to the first wiring; the other of the source electrode and the drain electrode of the first transistor is always electrically connected to the second wiring; one of a source electrode and a drain electrode of the second transistor is always electrically connected to the first wiring; the other of the source electrode and the drain electrode of the second transistor is always electrically connected to the third wiring; one of a source electrode and a drain electrode of the third transistor is always electrically connected to a gate electrode of the first transistor; the other of the source electrode and the drain electrode of the third transistor is always electrically connected to the fourth wiring; a gate electrode of the third transistor is always electrically connected to the sixth wiring; one of the source electrode and the drain electrode of the fourth transistor is always electrically connected to the gate electrode of the second transistor; the other of the source electrode and the drain electrode of the fourth transistor is always electrically connected to the fifth wiring; a gate electrode of the fourth transistor is always electrically connected to the sixth wiring; the first wiring has a function of outputting a first signal, the second wiring has a function as a first signal line, the third wiring has a function as a second signal line, the fourth wiring has a function as a third signal line, the fifth wiring has a function as a fourth signal line, a first conductive film functioning as one of a source electrode and a drain electrode of the first transistor has a region overlapping with a second conductive film functioning as a gate electrode of the second transistor; the fifth transistor has an oxide semiconductor film. Display device.

14. A pixel array device comprising: a pixel; and a gate driver formed on the same substrate as the pixel; the gate driver has a multi-stage circuit, at least one of the multiple-stage circuits includes first to fourth transistors and first to sixth wirings; the pixel has a fifth transistor; one of a source electrode and a drain electrode of the first transistor is always electrically connected to the first wiring; the other of the source electrode and the drain electrode of the first transistor is always electrically connected to the second wiring; one of a source electrode and a drain electrode of the second transistor is always electrically connected to the first wiring; the other of the source electrode and the drain electrode of the second transistor is always electrically connected to the third wiring; one of a source electrode and a drain electrode of the third transistor is always electrically connected to a gate electrode of the first transistor; the other of the source electrode and the drain electrode of the third transistor is always electrically connected to the fourth wiring; a gate electrode of the third transistor is always electrically connected to the sixth wiring; one of the source electrode and the drain electrode of the fourth transistor is always electrically connected to the gate electrode of the second transistor; the other of the source electrode and the drain electrode of the fourth transistor is always electrically connected to the fifth wiring; a gate electrode of the fourth transistor is always electrically connected to the sixth wiring; the first wiring has a function of outputting a first signal, the second wiring has a function as a first signal line, the third wiring has a function as a second signal line, the fourth wiring has a function as a third signal line, the fifth wiring has a function as a fourth signal line, a first conductive film functioning as one of a source electrode and a drain electrode of the first transistor has a region overlapping with a second conductive film functioning as a gate electrode of the second transistor; the third conductive film having a function as a gate electrode of the third transistor has a function as a gate electrode of the fourth transistor; the fifth transistor has an oxide semiconductor film. Display device.

15. A pixel array device comprising: a pixel; and a gate driver formed on the same substrate as the pixel; the gate driver has a multi-stage circuit, at least one of the multiple-stage circuits includes first to fourth transistors and first to sixth wirings; the pixel has a fifth transistor; one of a source electrode and a drain electrode of the first transistor is always electrically connected to the first wiring; the other of the source electrode and the drain electrode of the first transistor is always electrically connected to the second wiring; one of a source electrode and a drain electrode of the second transistor is always electrically connected to the first wiring; the other of the source electrode and the drain electrode of the second transistor is always electrically connected to the third wiring; one of a source electrode and a drain electrode of the third transistor is always electrically connected to a gate electrode of the first transistor; the other of the source electrode and the drain electrode of the third transistor is always electrically connected to the fourth wiring; a gate electrode of the third transistor is always electrically connected to the sixth wiring; one of the source electrode and the drain electrode of the fourth transistor is always electrically connected to the gate electrode of the second transistor; the other of the source electrode and the drain electrode of the fourth transistor is always electrically connected to the fifth wiring; a gate electrode of the fourth transistor is always electrically connected to the sixth wiring; the first wiring has a function of outputting a first signal, the second wiring has a function as a first signal line, the third wiring has a function as a second signal line, the fourth wiring has a function as a third signal line, the fifth wiring has a function as a fourth signal line, a signal that is out of phase with the signal input to the fourth wiring is input to the fifth wiring, a first conductive film functioning as one of a source electrode and a drain electrode of the first transistor has a region overlapping with a second conductive film functioning as a gate electrode of the second transistor; the fifth transistor has an oxide semiconductor film. Display device.

16. A pixel array device comprising: a pixel; and a gate driver formed on the same substrate as the pixel; the gate driver has a multi-stage circuit, at least one of the multiple-stage circuits includes first to fourth transistors and first to sixth wirings; the pixel has a fifth transistor; one of a source electrode and a drain electrode of the first transistor is always electrically connected to the first wiring; the other of the source electrode and the drain electrode of the first transistor is always electrically connected to the second wiring; one of a source electrode and a drain electrode of the second transistor is always electrically connected to the first wiring; the other of the source electrode and the drain electrode of the second transistor is always electrically connected to the third wiring; one of a source electrode and a drain electrode of the third transistor is always electrically connected to a gate electrode of the first transistor; the other of the source electrode and the drain electrode of the third transistor is always electrically connected to the fourth wiring; a gate electrode of the third transistor is always electrically connected to the sixth wiring; one of the source electrode and the drain electrode of the fourth transistor is always electrically connected to the gate electrode of the second transistor; the other of the source electrode and the drain electrode of the fourth transistor is always electrically connected to the fifth wiring; a gate electrode of the fourth transistor is always electrically connected to the sixth wiring; the first wiring has a function of outputting a first signal, the second wiring has a function as a first signal line, the third wiring has a function as a second signal line, the fourth wiring has a function as a third signal line, the fifth wiring has a function as a fourth signal line, a signal that is out of phase with the signal input to the fourth wiring is input to the fifth wiring, a first conductive film functioning as one of a source electrode and a drain electrode of the first transistor has a region overlapping with a second conductive film functioning as a gate electrode of the second transistor; the third conductive film having a function as a gate electrode of the third transistor has a function as a gate electrode of the fourth transistor; the fifth transistor has an oxide semiconductor film. Display device.

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