Liquid discharge device and print head

Abstract

To provide a liquid discharge device capable of acquiring information usable for estimating the operating status of a print head.SOLUTION: A liquid discharge device comprises: a print head which has a discharge unit that discharges liquid on the basis of a discharge control signal and a measurement circuit; and a print head control circuit. The measurement circuit includes: a first oscillation circuit that oscillates for a first predetermined time on the basis of the discharge control signal and oscillates for a second predetermined time on the basis of a measurement start signal; a second oscillation circuit that does not oscillate on the basis of the discharge control signal but oscillates for the second predetermined time on the basis of the measurement start signal; a first counter that outputs a first count value based on a first oscillation signal output from the first oscillation circuit on the basis of the measurement start signal; a second counter that outputs a second count value based on a second oscillation signal output from the second oscillation circuit on the basis of the measurement start signal; and a measurement control circuit that acquires the first count value and the second count value.SELECTED DRAWING: Figure 10

Description

Technical Field

[0001] The present invention relates to a liquid ejection device and a print head.

Background Art

[0002] In recent years, from the perspective of reducing environmental impact, so-called refurbished products that recondition products with initial defective products or used products and finish them to a state equivalent to unused products and then redistribute the products to the market again have attracted attention. Such refurbished products can reduce the amount of waste, and as a result, can reduce the environmental impact. In response to such efforts, in liquid ejection devices such as inkjet printers, for example, efforts have been made to reuse or reproduce print heads and redistribute them to the market again. Whether a print head can be reused or reproduced is determined based on, for example, the operating status of the print head.

[0003] For example, Patent Document 1 discloses a technique for improving the discrimination accuracy of the state of a reused print head by storing information on the usage history of the print head in the print head that ejects liquid.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] Obtaining information that can estimate the operating status of a print head is meaningful not only for the purpose of reusing or reproducing the print head, but in Patent Document 1, obtaining information that can estimate the operating status of the print head other than the information on the usage history of the print head has not been considered.

Means for Solving the Problems

[0006] One aspect of the liquid ejection device according to the present invention is a print head having a discharge unit that discharges liquid based on a discharge control signal and a measurement circuit to which the discharge control signal is input, and a print head control circuit that controls the print head. The measurement circuit includes a first oscillation circuit that oscillates for a first predetermined time based on the discharge control signal and oscillates for a second predetermined time based on a measurement start signal, a second oscillation circuit that does not oscillate based on the discharge control signal and oscillates for the second predetermined time based on the measurement start signal, a first counter that outputs a first count value based on a first oscillation signal output from the first oscillation circuit based on the measurement start signal, a second counter that outputs a second count value based on a second oscillation signal output from the second oscillation circuit based on the measurement start signal, and a measurement control circuit that acquires the first count value and the second count value.

[0007] One aspect of the print head according to the present invention is a discharge unit that discharges liquid based on a discharge control signal, and a measurement circuit to which the discharge control signal is input. The measurement circuit includes a first oscillation circuit that oscillates for a first predetermined time based on the discharge control signal and oscillates for a second predetermined time based on a measurement start signal, a second oscillation circuit that does not oscillate based on the discharge control signal and oscillates for the second predetermined time based on the measurement start signal, a first counter that outputs a first count value based on a first oscillation signal output from the first oscillation circuit based on the measurement start signal, a second counter that outputs a second count value based on a second oscillation signal output from the second oscillation circuit based on the measurement start signal, It has a measurement control circuit that acquires the first count value and the second count value.

Brief Description of the Drawings

[0008]

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Embodiments for Carrying Out the Invention

[0009] Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. The drawings used are for convenience of explanation. Note that the embodiments described below do not unduly limit the content of the present invention described in the claims. Also, not all of the configurations described below are essential constituent elements of the present invention.

[0010] In the following description, an inkjet printer is exemplified as an example of a liquid ejection device according to the present invention. However, the liquid ejection device is not limited to an inkjet printer, and may be, for example, a color material ejection device used for manufacturing a color filter such as a liquid crystal display, an electrode material ejection device used for forming electrodes such as an organic EL display and a surface emission display, a biological organic substance ejection device used for manufacturing a biochip, or the like.

[0011] 1. Embodiment 1-1. Outline of Liquid Ejection Device FIG. 1 is a diagram showing an example of the schematic configuration of the liquid ejection device 1. The liquid ejection device 1 of the present embodiment is a so-called serial printing type inkjet printer in which a carriage 21 equipped with print heads 22-1 to 22-n reciprocates along a scanning axis and ejects ink, which is an example of a liquid, from the print heads 22-1 to 22-n onto a medium P conveyed along a conveyance direction to form a desired image on the medium P. As the medium P used in such a liquid ejection device 1, in addition to printing paper such as plain paper, any printing medium such as a resin film or fabric can be used. Note that the liquid ejection device 1 is not limited to a serial printing type inkjet printer and may be a line printing type inkjet printer.

[0012] As shown in FIG. 1, the liquid ejection device 1 includes a control unit 10, print heads 22-1 to 22-n, a moving unit 30, a conveyance unit 40, and an ink container 90.

[0013] The ink container 90 stores a plurality of types of ink to be ejected onto the medium P. As such an ink container 90, an ink cartridge, a bag-shaped ink pack formed of a flexible film, an ink tank capable of replenishing ink, or the like can be used.

[0014] The control unit 10 includes a processing circuit such as a CPU (Central Processing Unit) or an FPGA (Field Programmable Gate Array), and a storage circuit such as a semiconductor memory, and controls each element of the liquid ejection device 1.

[0015] Print heads 22-1 to 22-n are mounted on the carriage 21. Control signals Ctrl-H and drive signal COM output by the control unit 10 are input to the print heads 22-1 to 22-n. Also, ink stored in the ink container 90 is supplied to the print heads 22-1 to 22-n via a tube or the like (not shown). Each of the print heads 22-1 to 22-n discharges the supplied ink onto the medium P based on the control signal Ctrl-H and the drive signal COM.

[0016] The moving unit 30 includes a carriage motor 31 and an endless belt 32. The carriage motor 31 operates based on the control signal Ctrl-C input from the control unit 10. The carriage 21 on which the print heads 22-1 to 22-n are mounted is fixed to the endless belt 32. Also, the endless belt 32 rotates according to the operation of the carriage motor 31. Then, due to the rotation of the endless belt 32, the carriage 21 fixed to the endless belt 32 moves along the scanning direction. That is, the moving unit 30 controls the movement of the print heads 22-1 to 22-n mounted on the carriage 21.

[0017] The conveying unit 40 includes a conveying motor 41 and conveying rollers 42. The conveying motor 41 operates based on the control signal Ctrl-T input from the control unit 10. The conveying rollers 42 rotate according to the operation of the conveying motor 41 while sandwiching the medium P. Due to the rotation of the conveying rollers 42, the medium P sandwiched by the conveying rollers 42 is conveyed along the conveying direction. That is, the conveying unit 40 controls the conveyance of the medium P.

[0018] In the liquid ejection device 1 configured as described above, the moving unit 30 controls the reciprocating motion along the scanning direction of the carriage 21, and the conveying unit 40 controls the conveyance along the conveyance direction of the medium P. Then, in conjunction with the reciprocating motion of the carriage 21 and the conveyance of the medium P, each of the print heads 22-1 to 22-n mounted on the carriage 21 ejects ink onto the medium P. As a result, the ink ejected from each of the print heads 22-1 to 22-n lands on an arbitrary surface of the medium P, and a desired image is formed on the medium P.

[0019] 1-2. Functional Configuration of Liquid Ejection Device Next, the functional configuration of the liquid ejection device 1 will be described. FIG. 2 is a diagram showing the functional configuration of the liquid ejection device 1. As shown in FIG. 2, the liquid ejection device 1 includes a control unit 10, a head unit 20, and a conveyance unit 40.

[0020] The control unit 10 and the head unit 20 are connected by a cable 15. The cable 15 is a cable having slidability that can follow the movement of the carriage 21, and may be, for example, a flexible flat cable (FFC: Flexible Flat Cable).

[0021] The control unit 10 has a drive circuit 50, a reference voltage circuit 52, and a control circuit 100.

[0022] The control circuit 100 includes a processor such as a microcontroller, and is communicably connected to an external device such as a host computer (not shown) provided outside the liquid ejection device 1. An image information signal including image data to be formed on the medium P is input to the control circuit 100 from the external device. The control circuit 100 performs predetermined image processing on the input image information signal to generate various data for controlling the liquid ejection device 1 and signals corresponding to the data, and outputs them to the corresponding configuration.

[0023] The control circuit 100 generates a control signal Ctrl-T for controlling the conveyance of the medium P and outputs it to the conveyance unit 40. As a result, the conveyance motor 41 included in the conveyance unit 40 is rotationally driven, and the conveyance along the conveyance direction of the medium P is controlled. Here, the control signal Ctrl-T output by the control circuit 100 may be input to the conveyance motor 41 after being signal-converted by a driver circuit (not shown).

[0024] Also, based on the input image information signal, the control circuit 100 generates a latch signal LAT, a change signal CH, a clock signal SCK, and print data signals SI1 to SIn as a control signal Ctrl-H for controlling the head unit 20, and outputs them to the head unit 20 via the cable 15. Details of the latch signal LAT, the change signal CH, the clock signal SCK, and the print data signals SI1 to SIn will be described later.

[0025] Further, the control circuit 100 outputs a base drive signal dA, which is a digital signal, to the drive circuit 50. The drive circuit 50 generates a drive signal COM including one or a plurality of signal waveforms by digitally / analog-converting the input base drive signal dA and then D-class amplifying the converted analog signal. Then, the drive circuit 50 outputs the generated drive signal COM to the head unit 20 via the cable 15. Here, the base drive signal dA is a digital signal for defining the signal waveform of the drive signal COM, and the drive circuit 50 generates the drive signal COM by D-class amplifying the signal waveform defined by the base drive signal dA. Therefore, the base drive signal dA only needs to be able to define the signal waveform of the drive signal COM, and it may be an analog signal. Also, the drive circuit 50 only needs to be able to amplify the signal waveform defined by the base drive signal dA and output it as the drive signal COM. Therefore, the drive circuit 50 may generate the drive signal COM by A-class amplifying, B-class amplifying, or AB-class amplifying the signal waveform defined by the base drive signal dA.

[0026] The reference voltage circuit 52 generates a reference voltage signal VBS that serves as a reference potential for driving a piezoelectric element 60, which will be described later, that the head unit 20 has. Then, the reference voltage circuit 52 outputs the generated reference voltage signal VBS to the head unit 20 via the cable 15. Such a reference voltage signal VBS is a signal with a constant voltage value. For example, it may be a signal with a ground potential of 0 V, or it may be a signal with a DC voltage such as 5.5 V or 6 V.

[0027] The head unit 20 has print heads 22-1 to 22-n. Also, the print head 22-i includes a drive signal selection circuit 200, a measurement circuit 300, and p ejection units 600[1] to 600[p]. Here, i is each integer from 1 to n.

[0028] The drive signal selection circuit 200 is configured to include one or more integrated circuit devices. The drive signal selection circuit 200 receives a latch signal LAT, a change signal CH, a clock signal SCK, a print data signal SIi, and a drive signal COM. Based on the input latch signal LAT, change signal CH, clock signal SCK, and print data signal SIi, the drive signal selection circuit 200 selects or deselects the signal waveform of the drive signal COM, thereby generating and outputting drive voltages VOUT[1] to VOUT[p] that individually correspond to each of the ejection units 600[1] to 600[p]. Note that the details of the configuration and operation of the drive signal selection circuit 200 will be described later.

[0029] The ejection units 600[1] to 600[p] each include a piezoelectric element 60. One end of the piezoelectric element 60 included in the ejection unit 600[j] is supplied with a drive voltage VOUT[j] output from the drive signal selection circuit 200. j is an integer from 1 to p. Also, a reference voltage signal VBS is commonly supplied to the other ends of the p piezoelectric elements 60 included in the ejection units 600[1] to 600[p]. Then, the piezoelectric element 60 included in the ejection unit 600[j] is displaced by the potential difference between the drive voltage VOUT[j] and the reference voltage signal VBS. An amount of ink corresponding to the displacement of this piezoelectric element 60 is ejected from the corresponding ejection unit 600[j]. Then, when the ink ejected from the ejection units 600[1] to 600[p] included in the print heads 22-1 to 22-n lands on the medium P, an image is formed on the medium P.

[0030] In this way, the ejection unit 600[j] included in the print head 22-i has a drive voltage VOUT[j] generated based on the latch signal LAT, the change signal CH, the clock signal SCK, and the print data signal SIi applied thereto, and ejects ink onto the medium P. In other words, the latch signal LAT, the change signal CH, the clock signal SCK, and the print data signals SI1 to SIn are ejection control signals that control the ejection of ink from the ejection unit 600[j] onto the medium P, respectively, and the ejection unit 600[j] ejects ink onto the medium P based on the ejection control signals.

[0031] Here, the print heads 22-1 to 22-n all have the same configuration, and when there is no need to distinguish them, they may be referred to as the print head 22. At this time, the description will be made assuming that a print data signal SI as the print data signals SI1 to SIn is input to the print head 22. Also, the description will be made assuming that a measurement result signal RS as the measurement result signals RS1 to RSn is input from the print head 22. Also, the ejection units 600[1] to 600[p] included in the print head 22 all have the same configuration, and when there is no need to distinguish them, they may simply be referred to as the ejection unit 600. At this time, the description will be made assuming that a drive voltage VOUT as the drive voltages VOUT[1] to VOUT[p] is supplied to the ejection unit 600.

[0032] The measurement circuit 300 included in the print head 22 receives the ejection control signal output by the control circuit 100, and as shown in FIG. 10 described later, includes a first oscillation circuit 310 that oscillates based on the ejection control signal, and a second oscillation circuit 320 that has the same configuration as the first oscillation circuit 310 but does not oscillate based on the ejection control signal. The ejection control signal is a signal for causing each ejection unit 600 included in the print head 22 to eject ink. The greater the number of ink ejections from each ejection unit 600, the greater the difference in the oscillation frequencies between the first oscillation circuit 310 and the second oscillation circuit 320, so the first oscillation circuit 310 deteriorates more over time than the second oscillation circuit 320. As a result, the difference between the oscillation frequency of the first oscillation circuit 310 and the oscillation frequency of the second oscillation circuit 320 increases. On the other hand, the greater the number of ink ejections from each ejection unit 600, the longer the cumulative operation time of the print head 22, so there is a correlation between the oscillation frequency difference between the first oscillation circuit 310 and the second oscillation circuit 320 and the cumulative operation time of the print head 22. In the present embodiment, the latch signal LAT is input to the measurement circuit 300 as the ejection control signal, but a change signal CH or a clock signal SCK may also be input.

[0033] The control circuit 100 outputs a measurement start signal ST to the measurement circuit 300 included in the print head 22-i. i is each integer from 1 to n. The measurement start signal ST may be, for example, a command indicating the start of measurement or a dedicated signal indicating the start of measurement. Further, the control circuit 100 outputs a measurement period designation signal TR to the measurement circuit 300 included in the print head 22-i. The measurement period designation signal TR is a signal for designating the measurement period by the measurement circuit 300. The measurement circuit 300 measures information capable of specifying the oscillation frequency difference between the first oscillation circuit 310 and the second oscillation circuit 320 during the period designated by the measurement period designation signal TR based on the measurement start signal ST, and outputs a measurement result signal RSi to the control circuit 100. The control circuit 100 can estimate the operation status of the print heads 22-1 to 22-n, such as the cumulative operation time, based on the measurement result signals RS1 to RSn.

[0034] 1-3. Structure of the ejection unit Next, the structure of the ejection unit 600 will be described. FIG. 3 is a diagram for explaining the schematic configuration of the ejection unit 600. In addition, FIG. 3 shows a nozzle plate 632, a reservoir 641, and a supply port 661 in addition to the ejection unit 600.

[0035] As shown in FIG. 3, the ejection unit 600 includes a piezoelectric element 60, a diaphragm 621, a cavity 631, and a nozzle 651. The piezoelectric element 60 includes a piezoelectric body 601 and electrodes 611 and 612. The piezoelectric element 60 is configured such that the electrodes 611 and 612 are positioned so as to sandwich the piezoelectric body 601. Such a piezoelectric element 60 is driven so that the central portion is displaced in the vertical direction according to the potential difference between the voltage supplied to the electrode 611 and the voltage supplied to the electrode 612. Specifically, a drive voltage VOUT based on a drive signal COM is supplied to the electrode 611, and a reference voltage signal VBS is supplied to the electrode 612. When the voltage value of the drive voltage VOUT supplied to the electrode 611 changes, the potential difference between the drive voltage VOUT supplied to the electrode 611 and the reference voltage signal VBS supplied to the electrode 612 changes. As a result, the piezoelectric element 60 is driven so that the central portion is displaced in the vertical direction.

[0036] The diaphragm 621 is located below the piezoelectric element 60 in FIG. 3. In other words, the piezoelectric element 60 is formed on the upper surface of the diaphragm 621 in FIG. 3. Such a diaphragm 621 is displaced in the vertical direction as the piezoelectric element 60 is driven in the vertical direction.

[0037] Below the diaphragm 621 in FIG. 3, there is a cavity 631. Ink is supplied to the cavity 631 from a reservoir 641. Further, the ink stored in the ink container 90 is introduced into the reservoir 641 via a supply port 661. That is, the inside of the cavity 631 is filled with the ink stored in the ink container 90. The internal volume of such a cavity 631 expands or contracts as the diaphragm 621 moves up and down. That is, the diaphragm 621 functions as a diaphragm that changes the internal volume of the cavity 631, and the cavity 631 functions as a pressure chamber whose pressure changes as the diaphragm 621 moves up and down.

[0038] The nozzle 651 is an opening provided in the nozzle plate 632 and communicates with the cavity 631. When the internal volume of the cavity 631 changes, the ink filled in the cavity 631 in response to the change is discharged from the nozzle 651.

[0039] In the discharge unit 600 configured as described above, when the piezoelectric element 60 is driven so as to bend upward, the diaphragm 621 is displaced upward. As a result, the internal volume of the cavity 631 expands, and as a result, the ink stored in the reservoir 641 is drawn into the cavity 631. On the other hand, when the piezoelectric element 60 is driven so as to bend downward, the diaphragm 621 is displaced downward. As a result, the internal volume of the cavity 631 contracts, and as a result, an amount of ink corresponding to the degree of contraction of the internal volume of the cavity 631 is discharged from the nozzle 651.

[0040] Note that the piezoelectric element 60 may be driven by supplying a driving voltage VOUT corresponding to a driving signal COM, and any structure may be used as long as ink can be discharged from the nozzle 651 by driving, and it is not limited to the structure shown in FIG. 3.

[0041] 1-4. Functional Configuration of Drive Signal Selection Circuit Next, the configuration and operation of the drive signal selection circuit 200 will be described. In describing the configuration and operation of the drive signal selection circuit 200, an example of the signal waveform of the drive signal COM input to the drive signal selection circuit 200 and an example of the signal waveform of the drive voltage VOUT output from the drive signal selection circuit 200 will be described.

[0042] FIG. 4 is a diagram showing an example of the signal waveform of the drive signal COM. As shown in FIG. 4, the drive signal COM includes a drive signal COMA and a drive signal COMB.

[0043] The drive signal COMA is a signal waveform in which a trapezoidal waveform Adp1 arranged in a period t1 from when the latch signal LAT rises until the change signal CH rises and a trapezoidal waveform Adp2 arranged in a period t2 from when the change signal CH rises until the latch signal LAT rises are continuous. Further, the trapezoidal waveform Adp1 is a signal waveform that causes a predetermined amount of ink to be ejected from the ejection unit 600 when supplied to the piezoelectric element 60 included in the ejection unit 600, and the trapezoidal waveform Adp2 is a signal waveform that causes an amount of ink larger than a predetermined amount to be ejected from the ejection unit 600 when supplied to the piezoelectric element 60 included in the ejection unit 600. Here, in the following description, the amount of ink ejected from the ejection unit 600 when the trapezoidal waveform Adp1 is supplied to the piezoelectric element 60 included in the ejection unit 600 may be referred to as a small amount, and the amount of ink ejected from the ejection unit 600 when the trapezoidal waveform Adp2 is supplied to the piezoelectric element 60 included in the ejection unit 600 may be referred to as a medium amount.

[0044] Also, as shown in FIG. 4, the drive signal COMB is a signal waveform in which a trapezoidal waveform Bdp1 arranged in period t1 and a trapezoidal waveform Bdp2 arranged in period t2 are continuous. Further, the trapezoidal waveform Bdp1 is a signal waveform that does not cause the ejection unit 600 to eject ink when supplied to the piezoelectric element 60 included in the ejection unit 600, and the trapezoidal waveform Bdp2 is a signal waveform that causes the ejection unit 600 to eject a small amount of ink when supplied to the piezoelectric element 60 included in the ejection unit 600. Here, the trapezoidal waveform Bdp1 is a signal waveform for preventing an increase in ink viscosity by vibrating the ink near the nozzle orifice included in the ejection unit 600 to such an extent that the ink is not ejected. In the following description, when the trapezoidal waveform Bdp1 is supplied to the piezoelectric element 60 included in the ejection unit 600, the operation of vibrating the ink near the nozzle orifice may be referred to as micro-vibration.

[0045] Here, as shown in FIG. 4, the voltage values at the start timing and the end timing of each of the trapezoidal waveforms Adp1, Adp2, Bdp1, and Bdp2 are all common at the voltage Vc. That is, each of the trapezoidal waveforms Adp1, Adp2, Bdp1, and Bdp2 starts at the voltage Vc and ends at the voltage Vc. And the cycle tp composed of the period t1 and the period t2 corresponds to the printing cycle for forming a new dot on the medium P.

[0046] Note that FIG. 4 illustrates a case where the trapezoidal waveform Adp1 and the trapezoidal waveform Bdp2 have the same signal waveform, but the trapezoidal waveform Adp1 and the trapezoidal waveform Bdp2 may have different signal waveforms. Also, when the trapezoidal waveform Adp1 is supplied to the piezoelectric element 60 included in the ejection unit 600 and when the trapezoidal waveform Bdp2 is supplied to the piezoelectric element 60 included in the ejection unit 600, although both are described as ejecting a small amount of ink from the ejection unit 600, it is not limited to this. That is, the signal waveforms of the drive signals COMA and COMB are not limited to the signal waveforms shown in FIG. 4, and various combinations of signal waveforms may be used according to the properties of the ink ejected from the ejection unit 600, the material of the medium P on which the ejected ink lands, and the like.

[0047] In addition, in FIG. 4, the case where the timing at which the trapezoidal waveform Adp1 and the trapezoidal waveform Adp2 included in the drive signal COMA are switched, and the timing at which the trapezoidal waveform Bdp1 and the trapezoidal waveform Bdp2 included in the drive signal COMB are switched are defined by one change signal CH is illustrated. However, the change signal CH that defines the timing at which the trapezoidal waveform Adp1 and the trapezoidal waveform Adp2 included in the drive signal COMA are switched and the change signal CH that defines the timing at which the trapezoidal waveform Bdp1 and the trapezoidal waveform Bdp2 included in the drive signal COMB are switched may be different signals.

[0048] FIG. 5 is a diagram showing an example of the signal waveform of the drive voltage VOUT in each case where the size of the dots formed on the medium P is a large dot LD, a medium dot MD, a small dot SD, and a non-recording ND.

[0049] As shown in FIG. 5, when a large dot LD is formed on the medium P, the drive voltage VOUT has a signal waveform in which the trapezoidal waveform Adp1 arranged in the period t1 within the period tp and the trapezoidal waveform Adp2 arranged in the period t2 within the period tp are continuous. When this drive voltage VOUT is supplied to the piezoelectric element 60 included in the ejection unit 600, a small amount of ink and a medium amount of ink are ejected from the corresponding ejection unit 600. Then, each ink lands on and combines with the medium P, and a large dot LD is formed on the medium P in the period tp.

[0050] When a medium dot MD is formed on the medium P, the drive voltage VOUT has a signal waveform in which the trapezoidal waveform Adp1 arranged in the period t1 within the period tp and the trapezoidal waveform Bdp2 arranged in the period t2 within the period tp are continuous. When this drive voltage VOUT is supplied to the piezoelectric element 60 included in the ejection unit 600, a small amount of ink is ejected twice from the corresponding ejection unit 600. Then, each ink lands on and combines with the medium P, and a medium dot MD is formed on the medium P in the period tp.

[0051] When a driving voltage VOUT is applied in a case where small dots SD are formed on a medium P, a trapezoidal waveform Adp1 arranged in a period t1 within a period tp and a constant signal waveform with a voltage Vc arranged in a period t2 within the period tp are continuous signal waveforms. When this driving voltage VOUT is supplied to a piezoelectric element 60 included in a discharge unit 600, a small amount of ink is discharged once from the corresponding discharge unit 600. Then, when this ink lands on the medium P, small dots SD are formed on the medium P in the period tp.

[0052] When a driving voltage VOUT corresponding to a non-recording ND where dots are not formed on a medium P is applied, a trapezoidal waveform Bdp1 arranged in a period t1 within a period tp and a constant signal waveform with a voltage Vc arranged in a period t2 within the period tp are continuous signal waveforms. When this driving voltage VOUT is supplied to a piezoelectric element 60 included in a discharge unit 600, only the ink near the nozzle orifice of the corresponding discharge unit 600 vibrates slightly, and no ink is discharged from the discharge unit 600. Therefore, no dots are formed on the medium P in the period tp.

[0053] Here, the constant signal waveform with the voltage Vc in the driving voltage VOUT means that when none of the trapezoidal waveforms Adp1, Adp2, Bdp1, Bdp2 are selected as the driving voltage VOUT, the voltage Vc immediately before the trapezoidal waveforms Adp1, Adp2, Bdp1, Bdp2 corresponds to the voltage value held by the capacitance component of the piezoelectric element 60 included in the discharge unit 600. That is, when none of the trapezoidal waveforms Adp1, Adp2, Bdp1, Bdp2 are selected as the driving voltage VOUT, the voltage Vc that was supplied immediately before is supplied as the driving voltage VOUT to the piezoelectric element 60 included in the discharge unit 600.

[0054] Here, the drive signal selection circuit 200 generates a driving voltage VOUT corresponding individually to each of a plurality of discharge units 600 as shown in FIG. 5 by selecting or not selecting the trapezoidal waveforms Adp1, Adp2 included in the drive signal COMA and the trapezoidal waveforms Bdp1, Bdp2 included in the drive signal COMB, and outputs it to the piezoelectric element 60 included in the corresponding discharge unit 600.

[0055] FIG. 6 is a diagram showing the functional configuration of the drive signal selection circuit 200. As shown in FIG. 6, the drive signal selection circuit 200 includes a selection control circuit 210 and a plurality of selection circuits 230. Further, FIG. 6 also shows ejection units 600[1] to 600[p] to which drive voltages VOUT[1] to VOUT[p] output from the drive signal selection circuit 200 are supplied.

[0056] A print data signal SI, a clock signal SCK, a latch signal LAT, and a change signal CH are input to the selection control circuit 210. In the selection control circuit 210, a set of a register 212, a latch circuit 214, and a decoder 216 is provided corresponding to each of the ejection units 600[1] to 600[p]. That is, the selection control circuit 210 includes at least the same number of sets of the register 212, the latch circuit 214, and the decoder 216 as the ejection units 600[1] to 600[p].

[0057] The print data signal SI is a signal synchronized with the clock signal SCK, and is a total 2p-bit signal that serially includes 2-bit print data [SIH, SIL] for selecting any one of a large dot LD, a medium dot MD, a small dot SD, and non-recording ND for each of the ejection units 600[1] to 600[p]. The print data signal SI is held in the register 212 for each piece of print data [SIH, SIL] included in the print data signal SI corresponding to the ejection units 600[1] to 600[p].

[0058] Specifically, in the selection control circuit 210, the registers 212 are connected in series with each other to form a p-stage shift register. The print data [SIH, SIL] serially input as the print data signal SI is sequentially transferred to the subsequent-stage register 212 according to the clock signal SCK. Then, by stopping the supply of the clock signal SCK, the print data [SIH, SIL] corresponding to each of the ejection units 600[1] to 600[p] is held in the register 212 corresponding to each of the ejection units 600[1] to 600[p]. In the following description, in order to distinguish the p registers 212 that constitute the shift register, the upstream side to the downstream side through which the print data signal SI propagates may be referred to as the first stage, the second stage, …, the pth stage.

[0059] Each of the p latch circuits 214 is provided corresponding to the p registers 212. Each of the latch circuits 214 latches the print data [SIH, SIL] held in each of the p registers 212 all at once at the rising edge of the latch signal LAT and outputs it to the corresponding decoder 216.

[0060] FIG. 7 is a diagram showing an example of the decoding content in the decoder 216. The decoder 216 generates and outputs the selection signals S1 and S2 by decoding the print data [SIH, SIL] latched by the latch circuit 214 according to the content shown in FIG. 7. For example, when the input print data [SIH, SIL] is [1, 0], the decoder 216 outputs the logic level of the selection signal S1 as H and L levels in the periods t1 and t2 to the selection circuit 230, and outputs the logic level of the selection signal S2 as L and H levels in the periods t1 and t2 to the selection circuit 230.

[0061] The selection circuit 230 is provided corresponding to each of the p ejection units 600. That is, the drive signal selection circuit 200 has p selection circuits 230, which is at least the same number as the p ejection units 600. FIG. 8 is a diagram showing the configuration of the selection circuit 230 corresponding to one ejection unit 600. As shown in FIG. 8, the selection circuit 230 includes inverters 232a and 232b, which are NOT circuits, and transfer gates 234a and 234b.

[0062] The selection signal S1 is input to the non-marked positive control terminal of the transfer gate 234a, while being logically inverted by the inverter 232a and input to the marked negative control terminal of the transfer gate 234a. Also, the drive signal COMA is supplied to the input terminal of the transfer gate 234a. The selection signal S2 is input to the non-marked positive control terminal of the transfer gate 234b, while being logically inverted by the inverter 232b and input to the marked negative control terminal of the transfer gate 234b. Also, the drive signal COMB is supplied to the input terminal of the transfer gate 234b. Then, the output terminal of the transfer gate 234a and the output terminal of the transfer gate 234b are commonly connected. The signal at the connection terminal where the output terminal of the transfer gate 234a and the output terminal of the transfer gate 234b are commonly connected is output as the drive voltage VOUT.

[0063] Specifically, when the selection signal S1 is at the H level, the input terminal and the output terminal of the transfer gate 234a are electrically connected, and when the selection signal S1 is at the L level, the input terminal and the output terminal of the transfer gate 234a are non-conductive. Also, when the selection signal S2 is at the H level, the input terminal and the output terminal of the transfer gate 234b are electrically connected, and when the selection signal S2 is at the L level, the input terminal and the output terminal of the transfer gate 234b are non-conductive. That is, the selection circuit 230 switches the conduction state between the input terminal and the output terminal of the transfer gates 234a and 234b based on the selection signals S1 and S2, thereby selecting or not selecting the signal waveforms of the drive signals COMA and COMB supplied to the input terminals of the transfer gates 234a and 234b, and outputs a drive voltage VOUT to a connection terminal where the output terminal of the transfer gate 234a and the output terminal of the transfer gate 234b are commonly connected.

[0064] The operation of the drive signal selection circuit 200 will be described with reference to FIG. 9. FIG. 9 is a diagram for explaining the operation of the drive signal selection circuit 200. The print data [SIH, SIL] included in the print data signal SI is serially input in synchronization with the clock signal SCK. Then, the print data [SIH, SIL] is sequentially transferred by the register 212 that forms a shift register corresponding to the p ejection units 600 in synchronization with the clock signal SCK. Thereafter, by stopping the supply of the clock signal SCK, each of the registers 212 holds the print data [SIH, SIL] corresponding to each of the p ejection units 600. Note that the print data [SIH, SIL] included in the print data signal SI is input in the order corresponding to the p-th stage, ..., the second stage, and the first stage of the register 212 that forms the shift register and the ejection unit 600.

[0065] Then, when the latch signal LAT rises, each of the latch circuits 214 latches the print data [SIH, SIL] held in the register 212 all at once. In FIG. 9, LS1, LS2, ..., LSp indicate the print data [SIH, SIL] latched by the latch circuits 214 corresponding to the first-stage, second-stage, ..., p-th stage registers 212.

[0066] The decoder 216 outputs the logic levels of the selection signals S1 and S2 in each of the periods t1 and t2 according to the dot size defined by the latched print data [SIH, SIL], as shown in FIG. 7.

[0067] Specifically, when the input print data [SIH, SIL] is [1, 1], the decoder 216 sets the logic level of the selection signal S1 to H, H levels in the periods t1 and t2, and sets the logic level of the selection signal S2 to L, L levels in the periods t1 and t2. In this case, the selection circuit 230 selects the trapezoidal waveform Adp1 in the period t1 and selects the trapezoidal waveform Adp2 in the period t2. As a result, a drive voltage VOUT corresponding to the large dot LD shown in FIG. 5 is generated at the output terminal of the selection circuit 230.

[0068] Also, when the input print data [SIH, SIL] is [1, 0], the decoder 216 sets the logic level of the selection signal S1 to H, L levels in the periods t1 and t2, and sets the logic level of the selection signal S2 to L, H levels in the periods t1 and t2. In this case, the selection circuit 230 selects the trapezoidal waveform Adp1 in the period t1 and selects the trapezoidal waveform Bdp2 in the period t2. As a result, a drive voltage VOUT corresponding to the medium dot MD shown in FIG. 5 is generated at the output terminal of the selection circuit 230.

[0069] Also, when the input print data [SIH, SIL] is [0, 1], the decoder 216 sets the logic level of the selection signal S1 to H, L levels in the periods t1 and t2, and sets the logic level of the selection signal S2 to L, L levels in the periods t1 and t2. In this case, the selection circuit 230 selects the trapezoidal waveform Adp1 in the period t1 and does not select either the trapezoidal waveforms Adp2 or Bdp2 in the period t2. As a result, a drive voltage VOUT corresponding to the small dot SD shown in FIG. 5 is generated at the output terminal of the selection circuit 230.

[0070] Further, when the input print data [SIH, SIL] is [0, 0], the decoder 216 sets the logic levels of the selection signal S1 to L, L levels during periods t1 and t2, and sets the logic levels of the selection signal S2 to H, L levels during periods t1 and t2. In this case, the selection circuit 230 selects the trapezoidal waveform Bdp1 during period t1, and does not select either of the trapezoidal waveforms Adp2 and Bdp2 during period t2. As a result, a drive voltage VOUT corresponding to the non-recording ND shown in FIG. 5 is generated at the output terminal of the selection circuit 230.

[0071] As described above, the drive signal selection circuit 200 generates and outputs the drive voltages VOUT[1] to VOUT[p] by selecting the signal waveforms of the drive signal COMA and the drive signal COMB based on the print data signal SI, the clock signal SCK, the latch signal LAT, and the change signal CH.

[0072] 1-5. Configuration of Measurement Circuit Next, the configuration and operation of the measurement circuit 300 will be described. FIG. 10 is a diagram showing the configuration of the measurement circuit 300. As shown in FIG. 10, the measurement circuit 300 includes a first oscillation circuit 310, a first counter 311, a second oscillation circuit 320, a second counter 321, a measurement control circuit 330, an oscillation control circuit 331, and an OR circuit 332.

[0073] The oscillation control circuit 331 outputs a first oscillation enable signal EN1 that is active for a first predetermined time based on the latch signal LAT, which is a discharge control signal. Hereinafter, it is assumed that the first oscillation enable signal EN1 is active when it is at a high level and inactive when it is at a low level. Specifically, the oscillation control circuit 331 outputs a first oscillation enable signal EN1 that is at a high level for the first predetermined time in synchronization with the falling edge of the latch signal LAT. The first predetermined time is set to be shorter than the minimum interval between two consecutive falling edges of the latch signal LAT. Therefore, after the first oscillation enable signal EN1 transitions from a low level to a high level in synchronization with the falling edge of the latch signal LAT, it transitions from a high level to a low level before the next falling edge of the latch signal LAT arrives. Note that the oscillation control circuit 331 may output a first oscillation enable signal EN1 that is at a high level for the first predetermined time in synchronization with the rising edge of the latch signal LAT.

[0074] When the measurement start signal ST is input from the control circuit 100 to the measurement control circuit 330, the measurement control circuit 330 outputs a second oscillation enable signal EN2 that is active for a second predetermined time. Hereinafter, it is assumed that the second oscillation enable signal EN2 is active when it is at a high level and inactive when it is at a low level.

[0075] The OR circuit 332 receives the first oscillation enable signal EN1 and the second oscillation enable signal EN2 and outputs a signal that is the logical sum of the first oscillation enable signal EN1 and the second oscillation enable signal EN2. In this embodiment, both the first oscillation enable signal EN1 and the second oscillation enable signal EN2 are either at a low level, or one of them is at a low level and the other is at a high level. That is, the first oscillation enable signal EN1 and the second oscillation enable signal EN2 do not both become high levels at the same time. Therefore, the OR circuit 332 outputs a low-level signal when both the first oscillation enable signal EN1 and the second oscillation enable signal EN2 are at a low level, and outputs a high-level signal when either the first oscillation enable signal EN1 or the second oscillation enable signal EN2 is at a high level.

[0076] The first oscillation circuit 310 oscillates for a first predetermined time based on the latch signal LAT which is a discharge control signal, and oscillates for a second predetermined time based on the second oscillation enable signal EN2 output from the measurement control circuit 330. Specifically, the first oscillation circuit 310 receives the output signal of the OR circuit 332 and oscillates when the output signal of the OR circuit 332 is at a high level, outputting the first oscillation signal SO1. Therefore, the first oscillation circuit 310 oscillates during the period when the first oscillation enable signal EN1 output from the oscillation control circuit 331 based on the latch signal LAT is at a high level, and outputs the first oscillation signal SO1. Also, the first oscillation circuit 310 oscillates for a second predetermined time during the period when the second oscillation enable signal EN2 output from the measurement control circuit 330 based on the measurement start signal ST is at a high level, and outputs the first oscillation signal SO1. That is, the first oscillation circuit 310 oscillates during the period when the first oscillation enable signal EN1 or the second oscillation enable signal EN2 is at a high level to output the first oscillation signal SO1, and does not oscillate during the period when both the first oscillation enable signal EN1 and the second oscillation enable signal EN2 are at a low level.

[0077] The first counter 311 outputs a first count value CT1 based on the first oscillation signal SO1 output from the first oscillation circuit 310 based on the second oscillation enable signal EN2. Specifically, the first counter 311 counts the number of pulses of the first oscillation signal SO1 during the period when the measurement period designation signal TR output from the control circuit 100 is active, and outputs the first count value CT1 indicating the count result. Hereinafter, it is assumed that the measurement period designation signal TR is active when it is at a high level and inactive when it is at a low level. The measurement period designation signal TR is a signal that becomes high level for a third predetermined time during the period when the second oscillation enable signal EN2 is at a high level. The third predetermined time is equal to or less than the second predetermined time. That is, the first counter 311 counts the number of pulses of the first oscillation signal SO1 during the period when the second oscillation enable signal EN2 is at a high level and the measurement period designation signal TR is at a high level, and outputs the first count value CT1. Note that the first count value CT1 is reset to 0, for example, at the rising edge of the second oscillation enable signal EN2.

[0078] In this embodiment, the clock signal SCK is also used as the measurement period designation signal TR. That is, the clock signal SCK functions as a signal that defines the timing related to printing with the second oscillation enable signal EN2 being at a low level during the printing period in which the print head 22 discharges ink, and functions as the measurement period designation signal TR during the period when the second oscillation enable signal EN2 is at a high level. Note that the measurement period designation signal TR may be a signal dedicated to the measurement circuit 300. In this case, assuming that the third predetermined time is equal to the second predetermined time, the measurement period designation signal TR may also be used as the second oscillation enable signal EN2. That is, the measurement control circuit 330 may not output the second oscillation enable signal EN2.

[0079] The second oscillation circuit 320 does not oscillate based on the latch signal LAT which is a discharge control signal, and oscillates for a second predetermined time based on the second oscillation enable signal EN2. Specifically, the second oscillation circuit 320 does not oscillate even when the first oscillation enable signal EN1 output from the oscillation control circuit 331 based on the latch signal LAT is at a high level, and oscillates for the second predetermined time during the period when the second oscillation enable signal EN2 output from the measurement control circuit 330 based on the measurement start signal ST is at a high level, and outputs a second oscillation signal SO2. That is, the second oscillation circuit 320 oscillates and outputs the second oscillation signal SO2 during the period when the second oscillation enable signal EN2 is at a high level, and does not oscillate during the period when the second oscillation enable signal EN2 is at a low level. Note that the second oscillation circuit 320 is a circuit having the same configuration as the first oscillation circuit 310.

[0080] The second counter 321 outputs a second count value CT2 based on the second oscillation signal SO2 output from the second oscillation circuit 320 based on the second oscillation enable signal EN2. Specifically, the second counter 321 counts the number of pulses of the second oscillation signal SO2 during the period when the measurement period designation signal TR is at a high level, and outputs a second count value CT2 indicating the count result. That is, the second counter 321 counts the number of pulses of the second oscillation signal SO2 during the period when the second oscillation enable signal EN2 is at a high level and the measurement period designation signal TR is at a high level, and outputs the second count value CT2. Note that the second count value CT2 is reset to 0, for example, at the rising edge of the second oscillation enable signal EN2.

[0081] FIG. 11 shows an example of a timing chart of various signals of the measurement circuit 300 during the printing period. FIG. 12 shows an example of a timing chart of various signals when the measurement circuit 300 performs a measurement operation. As shown in FIG. 11, during the printing period, the first oscillation circuit 310 oscillates for a first predetermined time T1 in synchronization with each pulse of the latch signal LAT, and the logic level of the first oscillation signal SO1 repeats inversion, but the second oscillation circuit 320 does not oscillate and the second oscillation signal SO2 is fixed at a low level. On the other hand, as shown in FIG. 12, when a pulse of the measurement start signal ST is input, both the first oscillation circuit 310 and the second oscillation circuit 320 oscillate for a second predetermined time T2, and during the period in which the measurement period designation signal TR is at a high level for a third predetermined time T3, the first counter 311 performs a counting operation and outputs a first count value CT1, and the second counter 321 performs a counting operation and outputs a second count value CT2. As a measurement result, the first count value CT1 is A and the second count value CT2 is B.

[0082] The measurement control circuit 330 acquires the first count value CT1 output from the first counter 311 and the second count value CT2 output from the second counter 321. Then, the measurement control circuit 330 outputs the first count value CT1 and the second count value CT2 to the control circuit 100 as a measurement result signal RS.

[0083] The first oscillation circuit 310 and the second oscillation circuit 320 have the same configuration. However, the first oscillation circuit 310 oscillates for a first predetermined time based on the latch signal LAT, while the second oscillation circuit 320 does not oscillate based on the latch signal LAT. Therefore, as will be described later, due to the deterioration over time caused by hot carrier injection, the rate at which the oscillation frequency of the first oscillation circuit 310 decreases is greater than the rate at which the oscillation frequency of the second oscillation circuit 320 decreases. As a result, the longer the cumulative operation time of the print head 22, the greater the difference between the first count value CT1 and the second count value CT2. Therefore, the control circuit 100 can estimate the operation status of the print head 22, such as the cumulative operation time, based on the difference between the first count value CT1 and the second count value CT2. The control circuit 100 accurately outputs the measurement period designation signal TR that becomes high level for exactly a third predetermined time T3 based on an oscillation signal output from an oscillator with high frequency accuracy, such as a crystal oscillator. Thus, highly accurate first count value CT1 and second count value CT2 can be obtained, and the operation status of the print head 22 can be estimated with high accuracy.

[0084] The control circuit 100 may output the measurement start signal ST to the measurement circuit 300 periodically, for example, at a cycle of several months, and estimate the operation status of the print head 22 based on the difference between the first count value CT1 and the second count value CT2. For example, the control circuit 100 may display the estimated operation status of the print head 22 on a display unit (not shown) provided in the liquid ejection device 1, or may display a message prompting the user to replace the print head 22 when the cumulative operation time exceeds a threshold value.

[0085] Also, the measurement circuit 300 may include a memory control circuit 340 and a non-volatile memory 350. The non-volatile memory 350 may be, for example, an EEPROM (Electrically Erasable Programmable Read-Only Memory) or a flash memory.

[0086] The memory control circuit 340 stores the first count value CT1 and the second count value CT2 in the non-volatile memory 350. The memory control circuit 340 may store them in the non-volatile memory 350 together with the time information each time the first count value CT1 and the second count value CT2 are output. Then, at a predetermined timing, the memory control circuit 340 reads out a plurality of first count values CT1 and a plurality of second count values CT2 stored in the non-volatile memory 350 in time series and outputs them to the measurement control circuit 330. The measurement control circuit 330 may acquire the plurality of first count values CT1 and the plurality of second count values CT2 and output them to the control circuit 100 as a measurement result signal RS. In this way, the control circuit 100 can accurately estimate the operating status of the print head 22 based on the plurality of first count values CT1 and the plurality of second count values CT2.

[0087] Also, the first count value CT1 and the second count value CT2 at the time of shipment of the print head 22 are stored in the non-volatile memory 350 as initial values. The measurement control circuit 330 may acquire the latest first count value CT1 and the second count value CT2 together with this initial value from the non-volatile memory 350 via the memory control circuit 340 and output them to the control circuit 100 as a measurement result signal RS. In this way, the control circuit 100 can accurately estimate the operating status of the print head 22 by comparing the difference between the latest first count value CT1 and the second count value CT2 with the difference between the initial value of the first count value CT1 and the initial value of the second count value CT2.

[0088] Note that the measurement control circuit 330 may estimate the operating status of the print head 22 based on the difference between the first count value CT1 and the second count value CT2.

[0089] 1-6. Configuration of the First Oscillation Circuit and the Second Oscillation Circuit Next, the configurations of the first oscillation circuit 310 and the second oscillation circuit 320 will be described. As described above, the first oscillation circuit 310 and the second oscillation circuit 320 have the same configuration.

[0090] For example, the first oscillation circuit 310 and the second oscillation circuit 320 may be an INV type ring oscillator shown in FIG. 13. As shown in FIG. 13, in the INV type ring oscillator, a NAND circuit 71 and k - 1 INV circuits 72-2 to 72-k are connected in a ring shape. k is an arbitrary odd number. The NAND circuit 71 receives the output signal of the INV circuit 72-k and the enable signal EN, and outputs a signal obtained by logically inverting the logical product signal of the output signal of the INV circuit 72-k and the enable signal EN. Also, the INV circuit 72-2 receives the output signal of the NAND circuit 71 and outputs a signal obtained by logically inverting the output signal of the NAND circuit 71. The INV circuit 72-i receives the output signal of the INV circuit 72-(i - 1) and outputs a signal obtained by logically inverting the output signal of the INV circuit 72-(i - 1). i is each integer from 3 to k. And, for example, the output signal of the INV circuit 72-k is output from the INV type ring oscillator as the oscillation signal SO. The INV type ring oscillator configured in this way does not oscillate when the enable signal EN is at a low level, and oscillates when the enable signal EN is at a high level.

[0091] Also, for example, the first oscillation circuit 310 and the second oscillation circuit 320 may be the NOR-type ring oscillator shown in FIG. 14. As shown in FIG. 14, in the NOR-type ring oscillator, k NOR circuits 74-1 to 74-k are connected in a ring. k is an arbitrary odd number. The NOR circuit 74-1 receives the output signal of the NOR circuit 74-k and the inverted enable signal ENB obtained by logically inverting the enable signal EN by the INV circuit 73, and outputs a signal obtained by logically inverting the logical sum signal of the output signal of the NOR circuit 74-k and the inverted enable signal ENB. Also, the NOR circuit 74-i receives the output signal of the NOR circuit 74-(i-1) and the inverted enable signal ENB, and outputs a signal obtained by logically inverting the logical sum signal of the output signal of the NOR circuit 74-(i-1) and the inverted enable signal ENB. i is each integer from 2 to k. And, for example, the output signal of the NOR circuit 74-k is output from the NOR-type ring oscillator as the oscillation signal SO. The NOR-type ring oscillator configured in this way does not oscillate when the enable signal EN is at a low level, and oscillates when the enable signal EN is at a high level.

[0092] Also, for example, the first oscillation circuit 310 and the second oscillation circuit 320 may be the NAND-type ring oscillator shown in FIG. 15. As shown in FIG. 15, in the NAND-type ring oscillator, k NAND circuits 75-1 to 75-k are connected in a ring. k is an arbitrary odd number. The NAND circuit 75-1 receives the output signal of the NAND circuit 75-k and the enable signal EN, and outputs a signal obtained by logically inverting the logical product signal of the output signal of the NAND circuit 75-k and the enable signal EN. Also, the NAND circuit 75-i receives the output signal of the NAND circuit 75-(i-1) and the enable signal EN, and outputs a signal obtained by logically inverting the logical product signal of the output signal of the NAND circuit 75-(i-1) and the enable signal EN. i is each integer from 2 to k. And, for example, the output signal of the NAND circuit 75-k is output from the NAND-type ring oscillator as the oscillation signal SO. The NAND-type ring oscillator configured in this way does not oscillate when the enable signal EN is at a low level, and oscillates when the enable signal EN is at a high level.

[0093] In FIGS. 13, 14, and 15, the enable signal EN is the output signal of the OR circuit 332 in the first oscillation circuit 310, and is the second oscillation enable signal EN2 in the second oscillation circuit 320. Further, the oscillation signal SO is the first oscillation signal SO1 in the first oscillation circuit 310, and is the second oscillation signal SO2 in the second oscillation circuit 320.

[0094] 1-7. Mechanism of Aging of Ring Oscillator The INV type ring oscillator shown in FIG. 13, the NOR type ring oscillator shown in FIG. 14, and the NAND type ring oscillator shown in FIG. 15 deteriorate as the number of oscillations increases. Next, the mechanism of this deterioration will be described.

[0095] For example, as shown in FIG. 16, each of the INV circuits 72-2 to 72-k included in the INV type ring oscillator is composed of a PMOS transistor 80 and an NMOS transistor 81. Further, for example, as shown in FIG. 17, each of the NOR circuits 74-1 to 74-k included in the NOR type ring oscillator is composed of two PMOS transistors 82 and 83 and two NMOS transistors 84 and 85. Further, for example, as shown in FIG. 18, each of the NAND circuits 71 included in the INV type ring oscillator and the NAND circuits 75-1 to 75-k included in the NAND type ring oscillator is composed of two PMOS transistors 86 and 87 and two NMOS transistors 88 and 89. In FIGS. 16, 17, and 18, each MOS transistor is marked with a symbol G on the gate, a symbol S on the source, and a symbol D on the drain.

[0096] The INV-type ring oscillator oscillates when the enable signal EN is at a high level. Therefore, as shown in FIG. 18, in the NAND circuit 71, the input signal IN repeatedly transitions between a low level and a high level. Along with this, the output signal OUT repeatedly transitions between a high level and a low level. When the input signal IN transitions from a low level to a high level, a current flows between the drain and source of the NMOS transistor 88 during the period until the output signal OUT transitions from a high level to a low level, and hot carriers are injected into the gate oxide film of the NMOS transistor 88. As a result, the threshold voltage vtn of the NMOS transistor 88 shifts in the direction of increasing. Also, when the input signal IN transitions from a high level to a low level, a current flows between the source and drain of the PMOS transistor 86 during the period until the output signal OUT transitions from a low level to a high level, and hot carriers are injected into the gate oxide film of the PMOS transistor 86. As a result, the absolute value of the threshold voltage vtp of the PMOS transistor 86 shifts in the direction of increasing. Note that hot carrier injection is known to be likely to occur at high voltage and low temperature.

[0097] Also, as shown in FIG. 16, when the enable signal EN is at a high level, in each of the INV circuits 72-2 to 72-k, the input signal IN repeatedly transitions between a low level and a high level. Accordingly, the output signal OUT repeatedly transitions between a high level and a low level. When the input signal IN transitions from a low level to a high level, a current flows between the drain and source of the NMOS transistor 81 during the period until the output signal OUT transitions from a high level to a low level, and hot carriers are injected into the gate oxide film of the NMOS transistor 81. As a result, the threshold voltage vtn of the NMOS transistor 81 shifts in an increasing direction. Also, when the input signal IN transitions from a high level to a low level, a current flows between the source and drain of the PMOS transistor 80 during the period until the output signal OUT transitions from a low level to a high level, and hot carriers are injected into the gate oxide film of the PMOS transistor 80. As a result, the absolute value of the threshold voltage vtp of the PMOS transistor 80 shifts in an increasing direction.

[0098] Therefore, the greater the number of oscillations of the INV type ring oscillator, the greater the amount of change in the threshold voltages of the PMOS transistors 80, 86 and the NMOS transistors 81, 88, and the greater the delay time of each of the NAND circuit 71 and the INV circuits 72-2 to 72-k. Thus, the oscillation frequency of the INV type ring oscillator decreases.

[0099] On the other hand, the INV type ring oscillator does not oscillate when the enable signal EN is at a low level. As shown in FIG. 18, in the NAND circuit 71, both the input signal IN and the output signal OUT are fixed at a high level. At this time, since a potential difference of vtn occurs between the gate and source of the NMOS transistor 88, PBTI (Positive Bias Temperature Instability) occurs in the NMOS transistor 88. vtn is the threshold voltage of the NMOS transistor 88, and vtn > 0V. As a result, the threshold voltage vtn of the NMOS transistor 88 shifts in an increasing direction. Note that PBTI is known to be likely to occur at high voltage and high temperature.

[0100] Also, as shown in FIG. 16, when the enable signal EN is at a low level, in each of the INV circuits 72-3, 72-5, …, 72-k, the input signal IN is fixed at a low level and the output signal OUT is fixed at a high level. At this time, since a potential difference of -VDD occurs between the gate and source of the PMOS transistor 80, NBTI (Negative Bias Temperature Instability) occurs in the PMOS transistor 80. vtp is the threshold voltage of the PMOS transistor 80, and vtp < 0V. As a result, the absolute value of the threshold voltage vtp of the PMOS transistor 80 shifts in the direction of increasing. Note that NBTI is known to be likely to occur at high voltage and high temperature.

[0101] Also, as shown in FIG. 16, when the enable signal EN is at a low level, in each of the INV circuits 72-2, 72-4, …, 72-(k-1), the input signal IN is fixed at a high level and the output signal OUT is fixed at a low level. At this time, since a potential difference of VDD occurs between the gate and source of the NMOS transistor 81, PBTI occurs in the NMOS transistor 81. VDD is the power supply voltage. As a result, the threshold voltage vtn of the NMOS transistor 81 shifts in the direction of increasing.

[0102] Therefore, even if the INV-type ring oscillator does not oscillate, as time passes, the delay time of each of the NAND circuit 71 and the INV circuits 72-2 to 72-k gradually increases, so the oscillation frequency of the INV-type ring oscillator gradually decreases.

[0103] The NOR-type ring oscillator oscillates when the enable signal EN is at a high level. As shown in Fig. 17, in each of the NOR circuits 74-1 to 74-k, the input signal IN repeatedly transitions between a low level and a high level. Accordingly, the output signal OUT repeatedly transitions between a high level and a low level. When the input signal IN transitions from a low level to a high level, a current flows between the drain and source of the NMOS transistor 84 during the period until the output signal OUT transitions from a high level to a low level, and hot carriers are injected into the gate oxide film of the NMOS transistor 84. As a result, the threshold voltage vtn of the NMOS transistor 84 shifts in the direction of increasing. Also, when the input signal IN transitions from a high level to a low level, a current flows between the source and drain of the PMOS transistor 82 during the period until the output signal OUT transitions from a low level to a high level, and hot carriers are injected into the gate oxide film of the PMOS transistor 82. As a result, the absolute value of the threshold voltage vtp of the PMOS transistor 82 shifts in the direction of increasing. Therefore, the greater the number of oscillations of the NOR-type ring oscillator, the greater the amount of change in the threshold voltages of the PMOS transistor 82 and the NMOS transistor 84, and the greater the delay time of each of the NOR circuits 74-1 to 74-k. Thus, the oscillation frequency of the NOR-type ring oscillator decreases.

[0104] On the one hand, when the enable signal EN is at a low level, the NOR-type ring oscillator does not oscillate. As shown in FIG. 17, in each of the NOR circuits 74-1 to 74-k, the inverted enable signal ENB is fixed at a high level, and both the input signal IN and the output signal OUT are fixed at a low level. At this time, since a potential difference of vtp occurs between the gate and source of the PMOS transistor 82, NBTI occurs in the PMOS transistor 82. vtp is the threshold voltage of the PMOS transistor 82, and vtp < 0V. As a result, the absolute value of the threshold voltage vtp of the PMOS transistor 82 shifts in the direction of increasing. Therefore, even if the NOR-type ring oscillator does not oscillate, as time passes, the delay time of each of the NOR circuits 74-1 to 74-k gradually increases, so the oscillation frequency of the NOR-type ring oscillator gradually decreases.

[0105] Since the NAND ring oscillator oscillates when the enable signal EN is at a high level, as shown in Fig. 18, in each of the NAND circuits 75-1 to 75-k, the input signal IN repeatedly transitions between a low level and a high level. Accordingly, the output signal OUT repeatedly transitions between a high level and a low level. When the input signal IN transitions from a low level to a high level, a current flows between the drain and source of the NMOS transistor 88 during the period until the output signal OUT transitions from a high level to a low level, and hot carriers are injected into the gate oxide film of the NMOS transistor 88. As a result, the threshold voltage vtn of the NMOS transistor 88 shifts in the direction of increasing. Also, when the input signal IN transitions from a high level to a low level, a current flows between the source and drain of the PMOS transistor 86 during the period until the output signal OUT transitions from a low level to a high level, and hot carriers are injected into the gate oxide film of the PMOS transistor 86. As a result, the absolute value of the threshold voltage vtp of the PMOS transistor 86 shifts in the direction of increasing. Therefore, the larger the number of oscillations of the NAND ring oscillator, the larger the amount of change in the threshold voltages of each of the PMOS transistor 86 and the NMOS transistor 88, and the larger the delay time of each of the NAND circuits 75-1 to 75-k, so the oscillation frequency of the NAND ring oscillator becomes lower.

[0106] On the one hand, the NAND ring oscillator does not oscillate when the enable signal EN is at a low level. As shown in FIG. 18, in each of the NAND circuits 75-1 to 75-k, both the input signal IN and the output signal OUT are fixed at a high level. At this time, since a potential difference of vtn occurs between the gate and source of the NMOS transistor 88, PBTI occurs in the NMOS transistor 88. vtn is the threshold voltage of the NMOS transistor 88, and vtn > 0V. As a result, the threshold voltage vtn of the NMOS transistor 88 shifts in the direction of increasing. Therefore, even if the NAND ring oscillator does not oscillate, as time passes, the delay time of each of the NAND circuits 75-1 to 75-k gradually increases, so the oscillation frequency of the NAND ring oscillator gradually decreases.

[0107] As described above, the first oscillation circuit 310 and the second oscillation circuit 320 have the same configuration. However, since the first oscillation circuit 310 oscillates for a first predetermined time based on the latch signal LAT, as the cumulative operation time of the print head 22 increases, due to hot carrier injection during oscillation and PBTI and NBTI during non-oscillation, the oscillation frequency F1 of the first oscillation circuit 310 significantly decreases. On the other hand, since the second oscillation circuit 320 does not oscillate based on the latch signal LAT, as the cumulative operation time of the print head 22 increases, due to PBTI and NBTI during non-oscillation, the oscillation frequency F2 of the second oscillation circuit 320 gradually decreases. Therefore, as shown in FIG. 19, the longer the cumulative operation time of the print head 22, the greater the difference between the oscillation frequency F1 of the first oscillation circuit 310 and the oscillation frequency F2 of the second oscillation circuit 320. That is, the longer the cumulative operation time of the print head 22, the greater the difference between the first count value CT1 and the second count value CT2. Thus, the control circuit 100 can estimate the operation status of the print head 22, such as the cumulative operation time, based on the difference between the first count value CT1 and the second count value CT2. In FIG. 19, the oscillation frequencies F1 and F2 decrease linearly with respect to the cumulative operation time of the print head 22, but they may also decrease non-linearly. Therefore, an acceleration degradation test may be performed on the measurement circuit 300 in advance to calculate the relational expression between the difference between the first count value CT1 and the second count value CT2 and the cumulative operation time of the print head 22, and the control circuit 100 may estimate the operation status of the print head 22 using the relational expression.

[0108] As described above, the first oscillation circuit 310 and the second oscillation circuit 320 have the same circuit configuration and may be any one of an INV-type ring oscillator, a NAND-type ring oscillator, and a NOR-type ring oscillator. As described above, since the degradation mechanisms of the INV-type ring oscillator, the NAND-type ring oscillator, and the NOR-type ring oscillator are different, an appropriate ring oscillator is selected in consideration of the manufacturing process and the like. For example, when the degradation caused by NBTI is much larger than the degradation caused by PBTI, the first oscillation circuit 310 and the second oscillation circuit 320 may be configured as a NAND-type ring oscillator. Also, for example, when the degradation caused by PBTI is much larger than the degradation caused by NBTI, the first oscillation circuit 310 and the second oscillation circuit 320 may be configured as a NOR-type ring oscillator. In this way, the decrease in the oscillation frequency F2 of the second oscillation circuit 320 over time becomes gentler. Therefore, the error caused by NBTI or PBTI included in the difference between the first count value CT1 and the second count value CT2 is reduced, and the estimation accuracy of the operating state of the print head 22 by the control circuit 100 is improved. Also, for example, when reduction of the circuit area of the measurement circuit 300 is prioritized, the first oscillation circuit 310 and the second oscillation circuit 320 may be configured as an INV-type ring oscillator.

[0109] Note that since the first oscillation circuit 310 oscillates during the printing period, in the ring oscillator of FIG. 13, FIG. 14, or FIG. 15, in order to reduce the radiation noise generated by the oscillation, it is preferable that the odd number k is a two-digit prime number. On the other hand, by accelerating the degradation of the first oscillation circuit 310, the rate of change of the difference between the first count value CT1 and the second count value CT2 increases, and the estimation accuracy of the operating state of the print head 22 can be improved. Therefore, in order to accelerate the degradation of the first oscillation circuit 310, in the ring oscillator of FIG. 13, FIG. 14, or FIG. 15, it is conceivable to increase the oscillation frequency of the first oscillation circuit 310 by decreasing the odd number k. From the above, for example, 11, 13, 17, etc. can be adopted as the odd number k.

[0110] Also, in the example of FIG. 17, the NOR circuits 74-1 to 74-k have the input signal IN supplied to the gate of the PMOS transistor 82 and the inverted enable signal ENB supplied to the gate of the PMOS transistor 83. However, as shown in FIG. 20, it is also conceivable to configure such that the inverted enable signal ENB is supplied to the gate of the PMOS transistor 82 and the input signal IN is supplied to the gate of the PMOS transistor 83. However, in the configuration of FIG. 20, when the enable signal EN is at a low level, a potential difference of -VDD occurs between the gate and source of the PMOS transistor 83. Therefore, compared with the configuration of FIG. 17 where only a potential difference of vtp occurs between the gate and source of the PMOS transistor 82, the degradation due to NBTI becomes larger. Therefore, for example, when both the first oscillation circuit 310 and the second oscillation circuit 320 are configured as NOR-type ring oscillators, by configuring the NOR circuits 74-1 to 74-k as shown in FIG. 17, compared with the case where the NOR circuits 74-1 to 74-k are configured as shown in FIG. 20, the decrease in the oscillation frequency F2 of the second oscillation circuit 320 over time becomes gentler. Therefore, the error included in the difference between the first count value CT1 and the second count value CT2 due to NBTI is reduced, and the estimation accuracy of the operating state of the print head 22 by the control circuit 100 is improved.

[0111] Similarly, in the example of FIG. 18, the NAND circuits 71, 75-1 to 75-k have the input signal IN supplied to the gate of the NMOS transistor 88 and the enable signal EN supplied to the gate of the NMOS transistor 89. However, as shown in FIG. 21, it is also conceivable to configure the circuit such that the enable signal EN is supplied to the gate of the NMOS transistor 88 and the input signal IN is supplied to the gate of the NMOS transistor 89. However, in the configuration of FIG. 21, when the enable signal EN is at a low level, a potential difference of VDD occurs between the gate and source of the NMOS transistor 89. Therefore, compared with the configuration of FIG. 18 in which only a potential difference of vtn occurs between the gate and source of the NMOS transistor 88, the degradation due to PBTI becomes larger. Therefore, for example, when both the first oscillation circuit 310 and the second oscillation circuit 320 are configured as NAND-type ring oscillators, by configuring the NAND circuits 75-1 to 75-k as shown in FIG. 18, compared with the case where the NAND circuits 75-1 to 75-k are configured as shown in FIG. 21, the decrease in the oscillation frequency F2 of the second oscillation circuit 320 over time becomes gentler. As a result, the error included in the difference between the first count value CT1 and the second count value CT2 due to PBTI is reduced, and the estimation accuracy of the operating state of the print head 22 by the control circuit 100 is improved.

[0112] Note that in the present embodiment, the control circuit 100 is an example of a "print head control circuit".

[0113] 1-8. Operational Effects As described above, in the liquid ejection device 1 of the present embodiment, in the measurement circuit 300 included in the print head 22, the first oscillation circuit 310 oscillates for a first predetermined time based on the LAT signal, and the second oscillation circuit 320 does not oscillate based on the LAT signal. Specifically, the first oscillation circuit 310 oscillates for the first predetermined time during the period in which the first oscillation enable signal EN1 output from the oscillation control circuit 331 based on the LAT signal is at a high level, while the second oscillation circuit 320 does not oscillate. As a result, the longer the operating time of the print head 22, the faster the deterioration of the first oscillation circuit 310 progresses, and the greater the difference between the decrease amount of the oscillation frequency F1 of the first oscillation circuit 310 and the decrease amount of the oscillation frequency F2 of the second oscillation circuit 320 becomes.

[0114] Further, in the liquid ejection device 1 of the present embodiment, based on the measurement start signal ST, both the first oscillation circuit 310 and the second oscillation circuit 320 oscillate, and the first counter 311 outputs a first count value CT1 and a second count value CT2, respectively. Specifically, during the period in which the second oscillation enable signal EN2 output from the measurement control circuit 330 based on the measurement start signal ST is at a high level, both the first oscillation circuit 310 and the second oscillation circuit 320 oscillate for a second predetermined time, and the first counter 311 outputs the first count value CT1 and the second counter 321 outputs the second count value CT2 during the period in which the measurement period designation signal TR is at a high level.

[0115] Since the first count value CT1 reflects the oscillation frequency F1 of the first oscillation circuit 310 and the second count value CT2 reflects the oscillation frequency F2 of the second oscillation circuit 320, the longer the operating time of the print head 22, the greater the difference between the first count value CT1 and the second count value CT2 becomes. Therefore, according to the liquid ejection device 1 of the present embodiment, it is possible to acquire information that can be used to estimate the operating state of the print head 22.

[0116] Further, according to the liquid ejection device 1 of the present embodiment, since the INV type ring oscillator, the NOR type ring oscillator, and the NAND type ring oscillator have different degradation mechanisms from each other, by selecting an appropriate ring oscillator considering the manufacturing process and the like as the first oscillation circuit 310 and the second oscillation circuit 320, the estimation accuracy of the operating state of the print head 22 is improved.

[0117] Further, according to the liquid ejection device 1 of the present embodiment, since the measurement period designation signal TR with high accuracy of the third predetermined time is input from the control circuit 100 to the measurement circuit 300, the accuracy of the first count value CT1 and the second count value CT2 is improved, and the third predetermined time can be arbitrarily set.

[0118] Further, according to the liquid ejection device 1 of the present embodiment, the control circuit 100 or the measurement control circuit 330 can estimate the operating state of the print head 22 based on the difference between the first count value CT1 and the second count value CT2 stored in the non-volatile memory 350. For example, the first count value CT1 and the second count value CT2 stored in the non-volatile memory 350 in the past can be used for estimating the current operating state of the print head 22.

[0119] Also, from the viewpoint of reducing environmental load, when the liquid ejection device 1 distributed in the market is recovered, the print head 22 is removed from the recovered liquid ejection device 1, and the removed print head 22 can be reused or reproduced, it is effective to distribute the liquid ejection device 1 equipped with the reused or reproduced print head 22 to the market again. In the present embodiment, after removing the print head 22, it is possible to estimate the operating state of the print head 22 based on the difference between the first count value CT1 and the second count value CT2 stored in the non-volatile memory 350, and the operating state can be used as one parameter for determining whether the print head 22 can be reused or reproduced.

[0120] 2. Modification The present invention is not limited to this embodiment, and various modifications can be made within the scope of the gist of the present invention.

[0121] 2-1. First Modified Example FIG. 22 is a diagram showing the configuration of the measurement circuit 300A of the first modified example. In FIG. 22, the same components as those in FIG. 10 are denoted by the same reference numerals.

[0122] As shown in FIG. 22, in the measurement circuit 300A of the first modified example, the measurement period designation signal TR is not a signal output from the control circuit 100 outside the measurement circuit 300A, but is output from the measurement control circuit 330 inside the measurement circuit 300A. Specifically, the second oscillation enable signal EN2 output from the measurement control circuit 330 is also used as the measurement period designation signal TR. However, the measurement control circuit 330 may output the measurement period designation signal TR separately from the second oscillation enable signal EN2.

[0123] The first counter 311 counts the number of pulses of the first oscillation signal SO1 during the period when the second oscillation enable signal EN2, which is also used as the measurement period designation signal TR, is at a high level, and outputs the first count value CT1. Similarly, the second counter 321 counts the number of pulses of the second oscillation signal SO2 during the period when the second oscillation enable signal EN2, which is also used as the measurement period designation signal TR, is at a high level, and outputs the second count value CT2. Note that the first count value CT1 and the second count value CT2 are reset to 0, for example, at the rising edge of the second oscillation enable signal EN2.

[0124] The other configurations and functions of the measurement circuit 300A are the same as those of the measurement circuit 300, and thus the description thereof is omitted.

[0125] According to the measurement circuit 300B of the second modified example, the input terminal of the measurement period designation signal TR is unnecessary, and miniaturization and cost reduction are possible.

[0126] 2-2. Second Modified Example FIG. 23 is a diagram showing the configuration of the measurement circuit 300B of the second modified example. In FIG. 23, the same components as those in FIG. 10 are denoted by the same reference numerals. As shown in FIG. 23, the measurement circuit 300B of the second modified example is different from the measurement circuit 300 shown in FIG. 10 in that it has m first oscillation circuits 310-1 to 310-m, m first counters 311-1 to 311-m, m second oscillation circuits 320-1 to 320-m, and m second counters 321-1 to 321-m. m is an arbitrary integer of 2 or more.

[0127] Each of the first oscillation circuits 310-1 to 310-m oscillates for a first predetermined time based on the latch signal LAT which is a discharge control signal, and oscillates for a second predetermined time based on the second oscillation enable signal EN2 output from the measurement control circuit 330. Specifically, the first oscillation circuit 310-i receives the output signal of the OR circuit 332 and oscillates when the output signal of the OR circuit 332 is at a high level, and outputs the first oscillation signal SO1-i. i is each integer from 1 to m. Therefore, the first oscillation circuit 310-i oscillates and outputs the first oscillation signal SO1-i during the period when the first oscillation enable signal EN1 output from the oscillation control circuit 331 is at a high level based on the latch signal LAT. Also, the first oscillation circuit 310-i oscillates for the second predetermined time and outputs the first oscillation signal SO1-i during the period when the second oscillation enable signal EN2 output from the measurement control circuit 330 is at a high level based on the measurement start signal ST. That is, the first oscillation circuit 310-i oscillates and outputs the first oscillation signal SO1-i during the period when the first oscillation enable signal EN1 or the second oscillation enable signal EN2 is at a high level, and does not oscillate during the period when both the first oscillation enable signal EN1 and the second oscillation enable signal EN2 are at a low level.

[0128] The first counter 311-i outputs a first count value CT1-i based on the first oscillation signal SO1-i output from the first oscillation circuit 310-i based on the second oscillation enable signal EN2. Specifically, the first counter 311-i counts the number of pulses of the first oscillation signal SO1-i during the period when the measurement period designation signal TR is at a high level, and outputs the first count value CT1-i indicating the count result. That is, the first counter 311-i counts the number of pulses of the first oscillation signal SO1-i during the period when the second oscillation enable signal EN2 is at a high level and the measurement period designation signal TR is at a high level, and outputs the first count value CT1-i. Note that the first count value CT1-i is reset to 0, for example, at the rising edge of the second oscillation enable signal EN2.

[0129] Each of the second oscillation circuits 320-1 to 320-m does not oscillate based on the latch signal LAT which is a discharge control signal, and oscillates for a second predetermined time based on the second oscillation enable signal EN2. Specifically, the second oscillation circuit 320-i does not oscillate even when the first oscillation enable signal EN1 output from the oscillation control circuit 331 based on the latch signal LAT is at a high level, and oscillates for the second predetermined time and outputs a second oscillation signal SO2-i during the period when the second oscillation enable signal EN2 output from the measurement control circuit 330 based on the measurement start signal ST is at a high level. i is each integer from 1 to m. That is, the second oscillation circuit 320-i oscillates and outputs the second oscillation signal SO2-i during the period when the second oscillation enable signal EN2 is at a high level, and does not oscillate during the period when the second oscillation enable signal EN2 is at a low level.

[0130] The second counter 321-i outputs a second count value CT2-i based on the second oscillation signal SO2-i output from the second oscillation circuit 320-i based on the second oscillation enable signal EN2. Specifically, the second counter 321-i counts the number of pulses of the second oscillation signal SO2-i during the period when the measurement period designation signal TR is at a high level, and outputs the second count value CT2-i indicating the count result. That is, the second counter 321-i counts the number of pulses of the second oscillation signal SO2-i during the period when the second oscillation enable signal EN2 is at a high level and the measurement period designation signal TR is at a high level, and outputs the second count value CT2-i. Note that the second count value CT2-i is reset to 0, for example, at the rising edge of the second oscillation enable signal EN2.

[0131] The measurement control circuit 330 acquires the first count values CT1-1 to CT1-m respectively output from the first counters 311-1 to 311-m and the second count values CT2-1 to CT2-m respectively output from the second counters 321-1 to 321-m. Then, the measurement control circuit 330 outputs the first count values CT1-1 to CT1-m and the second count values CT2-1 to CT2-m to the control circuit 100 as a measurement result signal RS.

[0132] The first oscillation circuits 310-1 to 310-m and the second oscillation circuits 320-1 to 320-m have the same circuit configuration. For example, the first oscillation circuits 310-1 to 310-m and the second oscillation circuits 320-1 to 320-m may be INV-type ring oscillators, NOR-type ring oscillators, or NAND-type ring oscillators. However, the first oscillation circuits 310-1 to 310-m oscillate for a first predetermined time based on the latch signal LAT, while the second oscillation circuits 320-1 to 320-m do not oscillate based on the latch signal LAT. Therefore, due to the deterioration over time caused by hot carrier injection, the rate at which the oscillation frequency of the first oscillation circuits 310-1 to 310-m decreases is greater than the rate at which the oscillation frequency of the second oscillation circuits 320-1 to 320-m decreases. As a result, the longer the cumulative operation time of the print head 22, the greater the difference between the first average value, which is the average value of the first count values CT1-1 to CT1-m, and the second average value, which is the average value of the second count values CT2-1 to CT2-m. Therefore, the control circuit 100 can calculate the first average value and the second average value, and estimate the cumulative operation time of the print head 22 based on the difference between the first average value and the second average value. For example, the control circuit 100 may periodically output a measurement start signal ST to the measurement circuit 300B at a cycle of several months or the like, and estimate the cumulative operation time of the print head 22 based on the difference between the first average value and the second average value.

[0133] The memory control circuit 340 stores the first count values CT1-1 to CT1-m and the second count values CT2-1 to CT2-m in the non-volatile memory 350. The memory control circuit 340 may store them in the non-volatile memory 350 together with time information each time the first count values CT1-1 to CT1-m and the second count values CT2-1 to CT2-m are output. Then, at a predetermined timing, the memory control circuit 340 reads out a plurality of sets of the first count values CT1-1 to CT1-m and the second count values CT2-1 to CT2-m stored in time series in the non-volatile memory 350 and outputs them to the measurement control circuit 330. The measurement control circuit 330 may acquire a plurality of sets of the first count values CT1-1 to CT1-m and the second count values CT2-1 to CT2-m and output them to the control circuit 100 as the measurement result signal RS. In this way, the control circuit 100 can calculate the first average value and the second average value for each set of the first count values CT1-1 to CT1-m and the second count values CT2-1 to CT2-m, and accurately estimate the cumulative operation time of the print head 22 based on the time series of the difference between the first average value and the second average value.

[0134] Also, the first count values CT1-1 to CT1-m and the second count values CT2-1 to CT2-m at the time of shipment of the print head 22 are stored in the non-volatile memory 350 as initial values. The measurement control circuit 330 may acquire the latest first count values CT1-1 to CT1-m and the second count values CT2-1 to CT2-m together with these initial values from the non-volatile memory 350 via the memory control circuit 340 and output them to the control circuit 100 as the measurement result signal RS. In this way, the control circuit 100 can compare the difference between the average value of the latest first count values CT1-1 to CT1-m and the average value of the second count values CT2-1 to CT2-m with the difference between the average value of the initial values of the first count values CT1-1 to CT1-m and the average value of the initial values of the second count values CT2-1 to CT2-m, and accurately estimate the operation status of the print head 22.

[0135] Note that the measurement control circuit 330 may calculate the first average value and the second average value, and estimate the cumulative operation time of the print head 22 based on the difference between the first average value and the second average value.

[0136] Since the other configurations and functions of the measurement circuit 300B are the same as those of the measurement circuit 300, the description thereof will be omitted.

[0137] According to the measurement circuit 300B of the second modification example, even if there are variations in the oscillation frequencies of the first oscillation circuits 310-1 to 310-m and the oscillation frequencies of the second oscillation circuits 320-1 to 320-m, by calculating the average values of the first count values CT1-1 to CT1-m and the average values of the second count values CT2-1 to CT2-m, the influence of the variations in the oscillation frequencies is reduced, so that the estimation accuracy of the cumulative operation time of the print head 22 is improved.

[0138] 2-3. Third Modification Example FIG. 24 is a diagram showing the configuration of the measurement circuit 300C of the third modification example. In FIG. 24, the same reference numerals are given to the same components as those in FIG. 10. As shown in FIG. 24, the measurement circuit 300C of the third modification example is different from the measurement circuit 300 shown in FIG. 10 in that it includes a third oscillation circuit 312, a third counter 313, a fifth oscillation circuit 314, a fifth counter 315, a fourth oscillation circuit 322, a fourth counter 323, a sixth oscillation circuit 324, and a sixth counter 325.

[0139] The first oscillation circuit 310, the third oscillation circuit 312, and the fifth oscillation circuit 314 each oscillate for a first predetermined time based on a latch signal LAT which is a discharge control signal, and oscillate for a second predetermined time based on a second oscillation enable signal EN2 output from the measurement control circuit 330. Specifically, the first oscillation circuit 310, the third oscillation circuit 312, and the fifth oscillation circuit 314 receive the output signal of the OR circuit 332 and oscillate when the output signal of the OR circuit 332 is at a high level. That is, the first oscillation circuit 310, the third oscillation circuit 312, and the fifth oscillation circuit 314 oscillate during the period when the first oscillation enable signal EN1 output from the oscillation control circuit 331 is at a high level based on the latch signal LAT. Also, the first oscillation circuit 310, the third oscillation circuit 312, and the fifth oscillation circuit 314 oscillate for a second predetermined time during the period when the second oscillation enable signal EN2 output from the measurement control circuit 330 is at a high level based on the measurement start signal ST. Then, the first oscillation circuit 310 outputs a first oscillation signal SO1, the third oscillation circuit 312 outputs a third oscillation signal SO3, and the fifth oscillation circuit 314 outputs a fifth oscillation signal SO5. That is, the first oscillation circuit 310, the third oscillation circuit 312, and the fifth oscillation circuit 314 oscillate during the period when the first oscillation enable signal EN1 or the second oscillation enable signal EN2 is at a high level and output the first oscillation signal SO1, the third oscillation signal SO3, and the fifth oscillation signal SO5 respectively, and do not oscillate during the period when both the first oscillation enable signal EN1 and the second oscillation enable signal EN2 are at a low level.

[0140] The first counter 311 outputs a first count value CT1 based on the first oscillation signal SO1 output from the first oscillation circuit 310 based on the second oscillation enable signal EN2. Also, the third counter 313 outputs a third count value CT3 based on the third oscillation signal SO3 output from the third oscillation circuit 312 based on the second oscillation enable signal EN2. Also, the fifth counter 315 outputs a fifth count value CT5 based on the fifth oscillation signal SO5 output from the fifth oscillation circuit 314 based on the second oscillation enable signal EN2. Specifically, the first counter 311 counts the number of pulses of the first oscillation signal SO1 during the period when the measurement period designation signal TR is at the high level, and outputs a first count value CT1 indicating the count result. Also, the third counter 313 counts the number of pulses of the third oscillation signal SO3 during the period when the measurement period designation signal TR is at the high level, and outputs a third count value CT3 indicating the count result. Also, the fifth counter 315 counts the number of pulses of the fifth oscillation signal SO5 during the period when the measurement period designation signal TR is at the high level, and outputs a fifth count value CT5 indicating the count result. That is, the first counter 311, the third counter 313, and the fifth counter 315 count the number of pulses of each of the first oscillation signal SO1, the third oscillation signal SO3, and the fifth oscillation signal SO5 during the period when the second oscillation enable signal EN2 is at the high level and the measurement period designation signal TR is at the high level, and output the first count value CT1, the third count value CT3, and the fifth count value CT5, respectively. Note that the first count value CT1, the third count value CT3, and the fifth count value CT5 are reset to 0, for example, at the rising edge of the second oscillation enable signal EN2.

[0141] The second oscillation circuit 320, the fourth oscillation circuit 322, and the sixth oscillation circuit 324 do not oscillate based on the latch signal LAT which is a discharge control signal, and oscillate for a second predetermined time based on the second oscillation enable signal EN2. Specifically, the second oscillation circuit 320, the fourth oscillation circuit 322, and the sixth oscillation circuit 324 do not oscillate even when the first oscillation enable signal EN1 output from the oscillation control circuit 331 based on the latch signal LAT is at a high level, and oscillate for the second predetermined time during the period when the second oscillation enable signal EN2 output from the measurement control circuit 330 based on the measurement start signal ST is at a high level. Then, the second oscillation circuit 320 outputs a second oscillation signal SO2, the fourth oscillation circuit 322 outputs a fourth oscillation signal SO4, and the sixth oscillation circuit 324 outputs a sixth oscillation signal SO6. That is, the second oscillation circuit 320, the fourth oscillation circuit 322, and the sixth oscillation circuit 324 oscillate during the period when the second oscillation enable signal EN2 is at a high level and output the second oscillation signal SO2, the fourth oscillation signal SO4, and the sixth oscillation signal SO6 respectively, and do not oscillate during the period when the second oscillation enable signal EN2 is at a low level.

[0142] The second counter 321 outputs a second count value CT2 based on the second oscillation signal SO2 output from the second oscillation circuit 320 based on the second oscillation enable signal EN2. Also, the fourth counter 323 outputs a fourth count value CT4 based on the fourth oscillation signal SO4 output from the fourth oscillation circuit 322 based on the second oscillation enable signal EN2. Also, the sixth counter 325 outputs a sixth count value CT6 based on the sixth oscillation signal SO6 output from the sixth oscillation circuit 324 based on the second oscillation enable signal EN2. Specifically, the second counter 321 counts the number of pulses of the second oscillation signal SO2 during the period when the measurement period designation signal TR is at a high level, and outputs a second count value CT2 indicating the count result. Also, the fourth counter 323 counts the number of pulses of the fourth oscillation signal SO4 during the period when the measurement period designation signal TR is at a high level, and outputs a fourth count value CT4 indicating the count result. Also, the sixth counter 325 counts the number of pulses of the sixth oscillation signal SO6 during the period when the measurement period designation signal TR is at a high level, and outputs a sixth count value CT6 indicating the count result. Note that the second count value CT2, the fourth count value CT4, and the sixth count value CT6 are reset to 0, for example, at the rising edge of the second oscillation enable signal EN2.

[0143] The measurement control circuit 330 acquires the first count value CT1, the second count value CT2, the third count value CT3, the fourth count value CT4, the fifth count value CT5, and the sixth count value CT6 output from the first counter 311, the second counter 321, the third counter 313, the fourth counter 323, the fifth counter 315, and the sixth counter 325, respectively. Then, the measurement control circuit 330 outputs the first count value CT1, the second count value CT2, the third count value CT3, the fourth count value CT4, the fifth count value CT5, and the sixth count value CT6 to the control circuit 100 as a measurement result signal RS.

[0144] The first oscillation circuit 310 and the second oscillation circuit 320 have the same circuit configuration. The third oscillation circuit 312 and the fourth oscillation circuit 322 have the same circuit configuration, and their circuit configurations are different from those of the first oscillation circuit 310 and the second oscillation circuit 320. The fifth oscillation circuit 314 and the sixth oscillation circuit 324 have the same circuit configuration, and their circuit configurations are different from those of the first oscillation circuit 310, the second oscillation circuit 320, the third oscillation circuit 312, and the fourth oscillation circuit 322. Specifically, the first oscillation circuit 310 and the second oscillation circuit 320 have the same circuit configuration and are any one of an INV-type ring oscillator, a NOR-type ring oscillator, and a NAND-type ring oscillator. Also, the third oscillation circuit 312 and the fourth oscillation circuit 322 have the same circuit configuration and are any one of the other INV-type ring oscillator, NOR-type ring oscillator, and NAND-type ring oscillator. Further, the fifth oscillation circuit 314 and the sixth oscillation circuit 324 have the same circuit configuration and are any one of the other INV-type ring oscillator, NOR-type ring oscillator, and NAND-type ring oscillator. For example, the first oscillation circuit 310 and the second oscillation circuit 320 may be INV-type ring oscillators, the third oscillation circuit 312 and the fourth oscillation circuit 322 may be NOR-type ring oscillators, and the fifth oscillation circuit 314 and the sixth oscillation circuit 324 may be NAND-type ring oscillators.

[0145] However, the first oscillation circuit 310, the third oscillation circuit 312, and the fifth oscillation circuit 314 oscillate for a first predetermined time based on the latch signal LAT, while the second oscillation circuit 320, the fourth oscillation circuit 322, and the sixth oscillation circuit 324 do not oscillate based on the latch signal LAT. Therefore, due to the deterioration over time caused by hot carrier injection, the rate at which the oscillation frequencies of the first oscillation circuit 310, the third oscillation circuit 312, and the fifth oscillation circuit 314 decrease is greater than the rate at which the oscillation frequencies of the second oscillation circuit 320, the fourth oscillation circuit 322, and the sixth oscillation circuit 324 decrease, respectively. As a result, the longer the cumulative operation time of the print head 22, the greater the first difference, which is the difference between the first count value CT1 and the second count value CT2, the greater the second difference, which is the difference between the third count value CT3 and the fourth count value CT4, and the greater the third difference, which is the difference between the fifth count value CT5 and the sixth count value CT6. Furthermore, since the circuit configurations of the first oscillation circuit 310 and the second oscillation circuit 320, the third oscillation circuit 312 and the fourth oscillation circuit 322, and the fifth oscillation circuit 314 and the sixth oscillation circuit 324 are different from each other, the degradation mechanisms are also different. Therefore, the relationships between each of the first difference, the second difference, and the third difference and the cumulative operation time of the print head 22 are also different. Accordingly, the control circuit 100 can accurately estimate the cumulative operation time of the print head 22 based on the first difference, the second difference, and the third difference. For example, the control circuit 100 may periodically output a measurement start signal ST to the measurement circuit 300C at a cycle of several months or the like, and estimate the cumulative operation time of the print head 22 based on the first difference, the second difference, and the third difference.

[0146] The memory control circuit 340 stores the first count value CT1, the second count value CT2, the third count value CT3, the fourth count value CT4, the fifth count value CT5, and the sixth count value CT6 in the non-volatile memory 350. The memory control circuit 340 may store them in the non-volatile memory 350 together with the time information every time the first count value CT1 to the sixth count value CT6 are output. Then, at a predetermined timing, the memory control circuit 340 reads out a plurality of sets of the first count value CT1 to the sixth count value CT6 stored in time series in the non-volatile memory 350 and outputs them to the measurement control circuit 330. The measurement control circuit 330 may acquire a plurality of sets of the first count value CT1 to the sixth count value CT6 and output them to the control circuit 100 as the measurement result signal RS. In this way, the control circuit 100 can calculate the first difference, the second difference, and the third difference for each set of the first count value CT1 to the sixth count value CT6, and accurately estimate the cumulative operation time of the print head 22 based on the time series of the first difference, the second difference, and the third difference.

[0147] Also, the first count value CT1 to the sixth count value CT6 at the time of shipment of the print head 22 are stored in the non-volatile memory 350 as initial values. The measurement control circuit 330 may acquire the latest first count value CT1 to the sixth count value CT6 together with these initial values from the non-volatile memory 350 via the memory control circuit 340 and output them to the control circuit 100 as the measurement result signal RS. In this way, the control circuit 100 can compare each of the first difference, the second difference, and the third difference based on the latest first count value CT1 to the sixth count value CT6 with each initial value of the first difference, the second difference, and the third difference based on the initial values of the first count value CT1 to the sixth count value CT6, and accurately estimate the operation status of the print head 22.

[0148] Note that the measurement control circuit 330 may calculate the first difference, the second difference, and the third difference, and estimate the cumulative operation time of the print head 22 based on the first difference, the second difference, and the third difference.

[0149] Since the other configurations and functions of the measurement circuit 300C are the same as those of the measurement circuit 300, the description thereof will be omitted.

[0150] In FIG. 24, the oscillation circuits with different circuit configurations that oscillate for a first predetermined time during the period when the first oscillation enable signal EN1 is at a high level and oscillate for a second predetermined time during the period when the second oscillation enable signal EN2 is at a high level are the three oscillation circuits of the first oscillation circuit 310, the third oscillation circuit 312, and the fifth oscillation circuit 314, but there may be two, or there may be four or more. Similarly, the oscillation circuits that oscillate for a second predetermined time during the period when the second oscillation enable signal EN2 is at a high level and do not oscillate even when the first oscillation enable signal EN1 becomes high level are the three oscillation circuits of the second oscillation circuit 320, the fourth oscillation circuit 322, and the sixth oscillation circuit 324, but there may be two, or there may be four or more.

[0151] As described above, according to the measurement circuit 300C of the third modification, since the deterioration mechanisms of the INV type ring oscillator, the NOR type ring oscillator, and the NAND type ring oscillator are different from each other, the first oscillation circuit 310 and the second oscillation circuit 320, the third oscillation circuit 312 and the fourth oscillation circuit 322, and the fifth oscillation circuit 314 and the sixth oscillation circuit 324 are different ring oscillators from each other, and thus the estimation accuracy of the operating state of the print head 22 is improved.

[0152] The present invention includes configurations that are substantially the same as the configurations described in the present embodiment, for example, configurations having the same functions, methods, and results, or configurations having the same objectives and effects. Further, the present invention includes configurations in which non-essential parts of the configurations described in the present embodiment are replaced. Further, the present invention includes configurations that exhibit the same operating effects as the configurations described in the present embodiment or configurations that can achieve the same objectives. Further, the present invention includes configurations in which known technologies are added to the configurations described in the present embodiment.

[0153] The above-described embodiments and modifications are examples and are not limited thereto. For example, it is also possible to appropriately combine each embodiment and each modification.

[0154] The following content is derived from the above-described embodiments and modifications.

[0155] One aspect of the liquid ejection device is a print head having a discharge unit that discharges liquid based on a discharge control signal and a measurement circuit to which the discharge control signal is input, and a print head control circuit that controls the print head. The measurement circuit includes a first oscillation circuit that oscillates for a first predetermined time based on the discharge control signal and oscillates for a second predetermined time based on a measurement start signal, a second oscillation circuit that does not oscillate based on the discharge control signal and oscillates for the second predetermined time based on the measurement start signal, a first counter that outputs a first count value based on a first oscillation signal output from the first oscillation circuit based on the measurement start signal, a second counter that outputs a second count value based on a second oscillation signal output from the second oscillation circuit based on the measurement start signal, and a measurement control circuit that acquires the first count value and the second count value.

[0156] In this liquid ejection device, since the first oscillation circuit oscillates based on the discharge control signal and the second oscillation circuit does not oscillate based on the discharge control signal, the difference between the change amount of the oscillation frequency of the first oscillation circuit and the change amount of the oscillation frequency of the second oscillation circuit increases as the operation time of the print head becomes longer. Also, in this liquid ejection device, based on the measurement start signal, both the first oscillation circuit and the second oscillation circuit oscillate, and the first counter outputs the first count value and the second count value, respectively. Since this first count value reflects the oscillation frequency of the first oscillation circuit and the second count value reflects the oscillation frequency of the second oscillation circuit, the difference between the first count value and the second count value increases as the operation time of the print head becomes longer. Therefore, according to this liquid ejection device, it is possible to acquire information that can be used to estimate the operation status of the print head.

[0157] In one aspect of the liquid ejection device, The measurement circuit further includes an oscillation control circuit that outputs a first oscillation enable signal that is active for a first predetermined time based on the discharge control signal, The first oscillation circuit may oscillate during a period in which the first oscillation enable signal is active.

[0158] According to this liquid discharge device, during a period in which a first oscillation enable signal output from an oscillation control circuit based on a discharge control signal is active, the first oscillation circuit can be caused to oscillate for a first predetermined time and the second oscillation circuit can be prevented from oscillating.

[0159] In one aspect of the liquid discharge device, the measurement control circuit outputs a second oscillation enable signal that is active for a second predetermined time based on the measurement start signal, the first oscillation circuit oscillates during a period in which the first oscillation enable signal or the second oscillation enable signal is active, and does not oscillate during a period in which neither the first oscillation enable signal nor the second oscillation enable signal is active, the second oscillation circuit oscillates during a period in which the second oscillation enable signal is active, and may not oscillate during a period in which the second oscillation enable signal is not active.

[0160] According to this liquid discharge device, during a period in which a first oscillation enable signal output from an oscillation control circuit based on a discharge control signal is active, the first oscillation circuit can be caused to oscillate for a first predetermined time and the second oscillation circuit can be prevented from oscillating, and during a period in which a second oscillation enable signal output from a measurement control circuit based on a measurement start signal is active, both the first oscillation circuit and the second oscillation circuit can be caused to oscillate for a second predetermined time.

[0161] In one aspect of the liquid discharge device, the first counter Output the first count value during the period when the measurement period designation signal is active. The second counter Outputs the second count value during the period when the measurement period designation signal is active. The measurement period designation signal may be a signal that becomes active for a third predetermined time during the period when the second oscillation enable signal is active.

[0162] According to this liquid ejection device, during the period when the second oscillation enable signal becomes active and both the first oscillation circuit and the second oscillation circuit oscillate, the measurement period designation signal becomes active and the first counter outputs the first count value and the second counter outputs the second count value, and the period can be arbitrarily set.

[0163] In one aspect of the liquid ejection device, The measurement period designation signal may be a signal output from the print head control circuit.

[0164] According to this liquid ejection device, since a measurement period designation signal with high accuracy for a third predetermined time is input from the print head control circuit to the measurement circuit, the accuracy of the first count value and the second count value is improved.

[0165] In one aspect of the liquid ejection device, The measurement period designation signal may be a signal output from the measurement control circuit.

[0166] According to this liquid ejection device, an input terminal for the measurement period designation signal TR is not required in the measurement circuit, and miniaturization and cost reduction are possible.

[0167] In one aspect of the liquid ejection device, The measurement circuit A non-volatile memory, And a memory control circuit that stores the first count value and the second count value in the non-volatile memory may be further provided.

[0168] According to this liquid ejection device, it is possible to estimate the operating status of the print head based on the difference between the first count value and the second count value stored in the non-volatile memory. For example, the first count value and the second count value previously stored in the non-volatile memory can be used to estimate the current operating status of the print head. Also, for example, after removing the print head, the operating status of the print head can be estimated based on the difference between the first count value and the second count value stored in the non-volatile memory, and it can be determined whether the print head can be reused or reproduced.

[0169] In one aspect of the liquid ejection device, the measurement circuit, a third oscillation circuit that oscillates for the first predetermined time based on the ejection control signal and oscillates for the second predetermined time based on the measurement start signal; a fourth oscillation circuit that does not oscillate based on the ejection control signal and oscillates for the second predetermined time based on the measurement start signal; a third counter that outputs a third count value based on a third oscillation signal output from the third oscillation circuit based on the measurement start signal; a fourth counter that outputs a fourth count value based on a fourth oscillation signal output from the fourth oscillation circuit based on the measurement start signal, and further includes; the measurement control circuit, further obtains the third count value and the fourth count value, the first oscillation circuit and the second oscillation circuit, have the same circuit configuration and are any one of an INV type ring oscillator, a NOR type ring oscillator, and a NAND type ring oscillator, the third oscillation circuit and the fourth oscillation circuit, may have the same circuit configuration and be any one of the other of an INV type ring oscillator, a NOR type ring oscillator, and a NAND type ring oscillator.

[0170] According to this liquid ejection device, since the INV-type ring oscillator, NOR-type ring oscillator, and NAND-type ring oscillator have different degradation mechanisms from each other, the first and second oscillation circuits and the third and fourth oscillation circuits being different ring oscillators from each other improves the estimation accuracy of the operating state of the print head.

[0171] One aspect of the print head is a discharge unit that discharges liquid based on a discharge control signal, and a measurement circuit to which the discharge control signal is input. The measurement circuit is a first oscillation circuit that oscillates for a first predetermined time based on the discharge control signal and oscillates for a second predetermined time based on a measurement start signal; a second oscillation circuit that does not oscillate based on the discharge control signal and oscillates for the second predetermined time based on the measurement start signal; a first counter that outputs a first count value based on a first oscillation signal output from the first oscillation circuit based on the measurement start signal; a second counter that outputs a second count value based on a second oscillation signal output from the second oscillation circuit based on the measurement start signal; and a measurement control circuit that acquires the first count value and the second count value.

[0172] In this print head, since the first oscillation circuit oscillates based on the ejection control signal and the second oscillation circuit does not oscillate based on the ejection control signal, the difference between the change amount of the oscillation frequency of the first oscillation circuit and the change amount of the oscillation frequency of the second oscillation circuit increases as the operating time of the print head becomes longer. Also, in this print head, based on the measurement start signal, both the first oscillation circuit and the second oscillation circuit oscillate, and the first counter outputs a first count value and a second count value respectively. Since this first count value reflects the oscillation frequency of the first oscillation circuit and the second count value reflects the oscillation frequency of the second oscillation circuit, the difference between the first count value and the second count value increases as the operating time of the print head becomes longer. Therefore, according to this print head, it is possible to acquire information that can be used to estimate the operating state of the print head.

Explanation of Signs

[0173] 1…Liquid ejection device, 10…Control unit, 15…Cable, 20…Head unit, 21…Carriage, 22, 22-1 to 22-n…Print head, 30…Moving unit, 31…Carriage motor, 32…Endless belt, 40…Conveying unit, 41…Conveying motor, 42…Conveying roller, 50…Drive circuit, 52…Reference voltage circuit, 60…Piezoelectric element, 71…NAND circuit, 72-2 to 72-k…INV circuit, 73…INV circuit, 74-1 to 74-k…NOR circuit, 75-1 to 75-k…NAND circuit, 80…PMOS transistor, 81…NMOS transistor, 82, 83…PMOS transistor, 84, 85…NMOS transistor, 86, 87…PMOS transistor, 88, 89…NMOS transistor, 90…Ink container, 100…Control circuit, 200…Drive signal selection circuit, 210…Selection control circuit, 212…Register, 214…Latch circuit, 216…Decoder, 230…Selection circuit, 232a, 232b…Inverter, 234a, 234b…Transfer gate, 300…Measurement circuit, 310, 310-1 to 310-m…First oscillation circuit, 311, 311-1 to 311-m…First counter, 312…Third oscillation circuit, 313…Third counter, 314…Fifth oscillation circuit, 315…Fifth counter, 320, 320-1 to 320-m…Second oscillation circuit, 321, 321-1 to 321-m…Second counter, 322…Fourth oscillation circuit, 323…Fourth counter, 324…Sixth oscillation circuit, 325…Sixth counter, 330…Measurement control circuit, 331…Oscillation control circuit, 332…OR circuit, 340…Memory control circuit, 350…Non-volatile memory, 600, 600-1 to 600-p…Ejection part, 601…Piezoelectric body, 611, 612…Electrode, 621…Diaphragm, 631…Cavity, 632…Nozzle plate, 641…Reservoir, 651…Nozzle, 661…Supply port, P…Medium

Claims

1. A print head having a discharge unit that discharges liquid based on a discharge control signal, and a measurement circuit to which the discharge control signal is input, and a print head control circuit that controls the print head. The measurement circuit includes a first oscillation circuit that oscillates for a first predetermined time based on the discharge control signal and oscillates for a second predetermined time based on a measurement start signal, a second oscillation circuit that does not oscillate based on the discharge control signal and oscillates for the second predetermined time based on the measurement start signal, a first counter that outputs a first count value based on a first oscillation signal output from the first oscillation circuit based on the measurement start signal, a second counter that outputs a second count value based on a second oscillation signal output from the second oscillation circuit based on the measurement start signal, and a measurement control circuit that acquires the first count value and the second count value. A liquid discharge device characterized by the above.

2. The measurement circuit further includes an oscillation control circuit that outputs a first oscillation enable signal that becomes active for the first predetermined time based on the discharge control signal, and the first oscillation circuit oscillates during a period when the first oscillation enable signal is active. The liquid discharge device according to claim 1, characterized by the above.

3. The measurement control circuit outputs a second oscillation enable signal that becomes active for the second predetermined time based on the measurement start signal, The first oscillation circuit oscillates during a period when the first oscillation enable signal or the second oscillation enable signal is active, and does not oscillate during a period when neither the first oscillation enable signal nor the second oscillation enable signal is active, The second oscillation circuit Oscillates during the period when the second oscillation enable signal is active and does not oscillate during the period when the second oscillation enable signal is inactive. The liquid ejection device according to claim 2, characterized in that.

4. The first counter Outputs the first count value during the period when the measurement period designation signal is active. The second counter Outputs the second count value during the period when the measurement period designation signal is active. The measurement period designation signal is a signal that becomes active for a third predetermined time during the period when the second oscillation enable signal is active. The liquid ejection device according to claim 3, characterized in that.

5. The measurement period designation signal is a signal output from the print head control circuit. The liquid ejection device according to claim 4, characterized in that.

6. The measurement period designation signal is a signal output from the measurement control circuit. The liquid ejection device according to claim 4, characterized in that.

7. The measurement circuit A non-volatile memory And a memory control circuit that stores the first count value and the second count value in the non-volatile memory. The liquid ejection device according to claim 1, characterized in that.

8. The measurement circuit A third oscillation circuit that oscillates for the first predetermined time based on the ejection control signal and oscillates for the second predetermined time based on the measurement start signal. A fourth oscillation circuit that does not oscillate based on the ejection control signal and oscillates for the second predetermined time based on the measurement start signal. A third counter that outputs a third count value based on the third oscillation signal output from the third oscillation circuit based on the measurement start signal; A fourth counter that outputs a fourth count value based on the fourth oscillation signal output from the fourth oscillation circuit based on the measurement start signal; and further includes, The measurement control circuit, Further obtains the third count value and the fourth count value, The first oscillation circuit and the second oscillation circuit, Have the same circuit configuration and are any one of an INV type ring oscillator, a NOR type ring oscillator, and a NAND type ring oscillator, The third oscillation circuit and the fourth oscillation circuit, Have the same circuit configuration and are any one of the others of an INV type ring oscillator, a NOR type ring oscillator, and a NAND type ring oscillator, The liquid ejection device according to claim 1, characterized in that.

9. A discharge unit that discharges liquid based on a discharge control signal; A measurement circuit to which the discharge control signal is input; and includes, The measurement circuit, A first oscillation circuit that oscillates for a first predetermined time based on the discharge control signal and oscillates for a second predetermined time based on a measurement start signal; A second oscillation circuit that does not oscillate based on the discharge control signal and oscillates for the second predetermined time based on the measurement start signal; A first counter that outputs a first count value based on the first oscillation signal output from the first oscillation circuit based on the measurement start signal; A second counter that outputs a second count value based on the second oscillation signal output from the second oscillation circuit based on the measurement start signal; And a measurement control circuit that obtains the first count value and the second count value. A print head, characterized in that.

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