Light-emitting device
The light-emitting element addresses the challenge of controlling multiple active layers by employing a semiconductor laminate with a complex wiring structure, allowing for individual light emission control and reducing heat generation and wavelength shift.
Patent Information
- Application Number
- JP2023208830
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2023-12-11
- Publication Date
- 2025-06-23
AI Technical Summary
Existing light-emitting elements lack the capability to individually control the light emission of multiple active layers, leading to inefficiencies and heat generation issues.
A light-emitting element comprising a semiconductor laminate with multiple active layers and a complex wiring structure that allows for individual control of light emission from each active layer through strategically placed electrodes and openings.
Enables independent control of light emission from each active layer, reducing heat generation and allowing for alternating use of active layers to maintain efficiency and prevent wavelength shift.
Smart Images

Figure 2025093220000001_ABST
Abstract
Description
Technical Field
[0001] The embodiment relates to a light-emitting element.
Background Art
[0002] Patent Document 1 discloses a configuration in which a first LED including a first active region that emits green light and a second LED including a second active region that emits blue light are stacked via a tunnel junction.
Prior Art Document
Patent Document
[0003]
Patent Document 1
Summary of the Invention
Problems to be Solved by the Invention
[0004] An object of the embodiment is to provide a light-emitting element capable of individually controlling the light emission of a first active layer and the light emission of a second active layer.
Means for Solving the Problems
[0005] The light-emitting element according to one embodiment of the present invention includes a semiconductor laminate, a first electrode, a second electrode, a third electrode, a first wiring, a second wiring, and a third wiring. The semiconductor laminate has a first p-type semiconductor layer, a first active layer, a first n-type semiconductor layer, an intermediate layer, a second p-type semiconductor layer, a second active layer, and a second n-type semiconductor layer. The first active layer is disposed on the first p-type semiconductor layer. The first n-type semiconductor layer is disposed on the first active layer. The intermediate layer is disposed on the first n-type semiconductor layer. The second p-type semiconductor layer is disposed on the intermediate layer. The second active layer is disposed on the second p-type semiconductor layer. The second n-type semiconductor layer is disposed on the second active layer. The semiconductor laminate has a plurality of first openings and a plurality of second openings. The plurality of first openings are continuously disposed in the first p-type semiconductor layer, the first active layer, and the first n-type semiconductor layer. The plurality of second openings are continuously disposed in the first p-type semiconductor layer, the first active layer, the first n-type semiconductor layer, the intermediate layer, the second p-type semiconductor layer, the second active layer, and the second n-type semiconductor layer. The first electrode is located away from the semiconductor laminate in a plan view. The first electrode is electrically connected to the first p-type semiconductor layer. The second electrode is electrically connected to the second n-type semiconductor layer. The third electrode is electrically connected to the first n-type semiconductor layer. The first wiring is disposed under the semiconductor laminate. The first wiring electrically connects the first electrode and the first p-type semiconductor layer. The second wiring is disposed inside the plurality of second openings. The second wiring electrically connects the second electrode and the second n-type semiconductor layer. The third wiring is disposed inside the plurality of first openings. The third wiring electrically connects the third electrode and the first n-type semiconductor layer.
[0006] The light-emitting element according to one embodiment of the present invention includes a semiconductor laminate, a first electrode, a second electrode, a third electrode, a first wiring, a second wiring, and a third wiring. The semiconductor laminate has a first p-type semiconductor layer, a first active layer, a first n-type semiconductor layer, an intermediate layer, a second p-type semiconductor layer, a second active layer, and a second n-type semiconductor layer. The first active layer is disposed on the first p-type semiconductor layer. The first n-type semiconductor layer is disposed on the first active layer. The intermediate layer is disposed on the first n-type semiconductor layer. The second p-type semiconductor layer is disposed on the intermediate layer. The second active layer is disposed on the second p-type semiconductor layer. The second n-type semiconductor layer is disposed on the second active layer. The semiconductor laminate has a plurality of first openings and a plurality of second openings. The plurality of first openings are continuously disposed in the first p-type semiconductor layer, the first active layer, and the first n-type semiconductor layer. The plurality of second openings are continuously disposed in the first p-type semiconductor layer, the first active layer, the first n-type semiconductor layer, the intermediate layer, the second p-type semiconductor layer, the second active layer, and the second n-type semiconductor layer. The first electrode is located away from the semiconductor laminate in a plan view. The first electrode is electrically connected to the first p-type semiconductor layer. The second electrode is electrically connected to the first n-type semiconductor layer. The third electrode is electrically connected to the second n-type semiconductor layer. The first wiring is disposed under the semiconductor laminate. The first wiring electrically connects the first electrode and the first p-type semiconductor layer. The second wiring is disposed inside the plurality of first openings. The second wiring electrically connects the second electrode and the first n-type semiconductor layer. The third wiring is disposed inside the plurality of second openings. The third wiring electrically connects the third electrode and the second n-type semiconductor layer.
Effect of the Invention
[0007] According to one embodiment of the present invention, it is possible to provide a light-emitting element capable of individually controlling the light emission of the first active layer and the light emission of the second active layer.
Brief Description of the Drawings
[0008]
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Embodiments for Carrying Out the Invention
[0009] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the sizes between parts, etc. are not necessarily the same as the actual ones. Even when representing the same part, the dimensions and ratios may be represented differently in the drawings. In the present specification and each figure, the same elements as those already described are denoted by the same reference numerals, and detailed descriptions thereof are omitted as appropriate.
[0010] Further, in the following, in order to make the description easier to understand, the arrangement and configuration of each part will be described using the XYZ orthogonal coordinate system. The X-axis, Y-axis, and Z-axis are mutually orthogonal. Also, the direction in which the X-axis extends is defined as the "X direction", the direction in which the Y-axis extends is defined as the "Y direction", and the direction in which the Z-axis extends is defined as the "Z direction". Further, in order to make the description easier to understand, among the Z-directions, the direction of the arrow is defined as upward and the opposite direction is defined as downward, but these directions are independent of the direction of gravity. Also, looking along the direction along the Z-axis is defined as "plan view".
[0011] (First Embodiment) FIG. 1 is a plan view showing a light-emitting element according to the first embodiment. FIG. 2 is a cross-sectional view showing a light-emitting element according to the first embodiment. FIG. 2 shows a cross-section taken along line II-II shown in FIG. 1. As shown in FIGS. 1 and 2, the light-emitting element 100 according to the first embodiment includes a semiconductor laminate 10, a first electrode 21, a second electrode 22, a third electrode 23, a first wiring 31, a second wiring 32, and a third wiring 33. As shown in FIG. 1, the shape of the light-emitting element 100 in plan view is rectangular. When the shape of the light-emitting element 100 in plan view is rectangular, the length of one side of the rectangle is, for example, 50 μm or more and 2000 μm or less.
[0012] The semiconductor laminate 10 has a first p-type semiconductor layer 11a, a first active layer 11b, a first n-type semiconductor layer 11c, an intermediate layer 13, a second p-type semiconductor layer 12a, a second active layer 12b, and a second n-type semiconductor layer 12c.
[0013] The first p-type semiconductor layer 11a is disposed at the lowermost part of the semiconductor laminate 10. The first active layer 11b is disposed on the first p-type semiconductor layer 11a. The first n-type semiconductor layer 11c is disposed on the first active layer 11b. The intermediate layer 13 is disposed on the first n-type semiconductor layer 11c. The second p-type semiconductor layer 12a is disposed on the intermediate layer 13. The second active layer 12b is disposed on the second p-type semiconductor layer 12a. The second n-type semiconductor layer 12c is disposed on the second active layer 12b.
[0014] The first p-type semiconductor layer 11a, the first active layer 11b, the first n-type semiconductor layer 11c, the intermediate layer 13, the second p-type semiconductor layer 12a, the second active layer 12b, and the second n-type semiconductor layer 12c are each made of, for example, a nitride semiconductor. In this specification, the "nitride semiconductor" refers to, for example, In x Al y Ga 1-x-y semiconductors of all compositions in which the composition ratios x and y are varied within their respective ranges in the chemical formula N(0≦x≦1, 0≦y≦1, x + y≦1). Also, in the above chemical formula, the Group V elements other than N (nitrogen) are further included, and those further including various elements added to control various physical properties such as conductivity type are also included in the "nitride semiconductor".
[0015] The first n-type semiconductor layer 11c and the second n-type semiconductor layer 12c contain, for example, Si (silicon) as an n-type impurity. The first p-type semiconductor layer 11a and the second p-type semiconductor layer 12a contain, for example, Mg (magnesium) as a p-type impurity. The first active layer 11b and the second active layer 12b are light-emitting layers that emit light and have, for example, a MQW (multiple quantum well) structure including a plurality of barrier layers and a plurality of well layers. The peak wavelength of the light emitted from the first active layer 11b may be the same as or different from the peak wavelength of the light emitted from the second active layer 12b.
[0016] The intermediate layer 13 includes at least one of a p-type semiconductor layer having a higher p-type impurity concentration than the second p-type semiconductor layer 12a and an n-type semiconductor layer having a higher n-type impurity concentration than the first n-type semiconductor layer 11c. The intermediate layer 13 functions as, for example, a tunnel junction layer.
[0017] The semiconductor laminate 10 has a plurality of first openings 16 and a plurality of second openings 17. The plurality of first openings 16 are arranged continuously with the first p-type semiconductor layer 11a, the first active layer 11b, and the first n-type semiconductor layer 11c. The plurality of first openings 16 are holes that penetrate the first p-type semiconductor layer 11a and the first active layer 11b in the Z direction and reach the first n-type semiconductor layer 11c. The plurality of first openings 16 do not penetrate the first n-type semiconductor layer 11c. The plurality of second openings 17 are arranged continuously with the first p-type semiconductor layer 11a, the first active layer 11b, the first n-type semiconductor layer 11c, the intermediate layer 13, the second p-type semiconductor layer 12a, the second active layer 12b, and the second n-type semiconductor layer 12c. The plurality of second openings 17 are holes that penetrate the first p-type semiconductor layer 11a, the first active layer 11b, the first n-type semiconductor layer 11c, the intermediate layer 13, the second p-type semiconductor layer 12a, and the second active layer 12b in the Z direction and reach the second n-type semiconductor layer 12c. The plurality of second openings 17 do not penetrate the second n-type semiconductor layer 12c.
[0018] In the light-emitting element 100, the shape of the plurality of first openings 16 in plan view and the shape of the plurality of second openings 17 in plan view are each a perfect circle. The shape of the plurality of first openings 16 in plan view and the shape of the plurality of second openings 17 in plan view may each be an ellipse, a polygon, or the like.
[0019] The first electrode 21 is electrically connected to the first p-type semiconductor layer 11a. The first electrode 21 is located away from the semiconductor laminate 10 in plan view. The first electrode 21 does not overlap the semiconductor laminate 10 in the Z direction.
[0020] The second electrode 22 is electrically connected to the second n-type semiconductor layer 12c. The second electrode 22 is located away from the semiconductor laminate 10 in plan view. The second electrode 22 does not overlap the semiconductor laminate 10 in the Z direction. The second electrode 22 is arranged, for example, as an electrode opposite to the first electrode 21 in plan view.
[0021] The third electrode 23 is electrically connected to the first n-type semiconductor layer 11c. The third electrode 23 is disposed, for example, under the semiconductor laminate 10. In the light-emitting element 100, the third electrode 23 is disposed at the lowermost part of the light-emitting element 100. In the light-emitting element 100, the third electrode 23 is disposed under the semiconductor laminate 10, the first electrode 21, the second electrode 22, the first wiring 31, the second wiring 32, and the third wiring 33.
[0022] Note that the third electrode 23 does not necessarily have to be disposed under the semiconductor laminate 10. The third electrode 23 may be provided, for example, at the same height as at least one of the first electrode 21 and the second electrode 22, may be provided at the same height as the semiconductor laminate 10, or may be provided at the same height as at least one of the first wiring 31, the second wiring 32, and the third wiring 33.
[0023] The first electrode 21 and the second electrode 22 are each made of, for example, a metal material. As the metal material, for example, at least one of metals such as Ti (titanium), Pt (platinum), Rh (rhodium), Au (gold), Ni (nickel), Ta (tantalum), Zr (zirconium), and alloys containing these metals can be used. The first electrode 21 and the second electrode 22 may each be a single layer or a laminate in which a plurality of layers are laminated. The first electrode 21 and the second electrode 22 can be, for example, laminates in which a Ti layer, a Pt layer, and an Au layer are laminated in this order.
[0024] The third electrode 23 is made of, for example, at least one of a metal material and a semiconductor material. As the metal material, the same materials as those of the metal materials of the first electrode 21 and the second electrode 22 can be used. As the semiconductor material, for example, Si can be used. The third electrode 23 may be, for example, a laminate in which a semiconductor layer is laminated on a metal layer.
[0025] The first wiring 31 electrically connects the first electrode 21 and the first p-type semiconductor layer 11a. The first wiring 31 is disposed under the semiconductor laminate 10 (the first p-type semiconductor layer 11a). In the light-emitting element 100, the first wiring 31 extends from under the first electrode 21 to under the first p-type semiconductor layer 11a. In the light-emitting element 100, the first wiring 31 and the first p-type semiconductor layer 11a are electrically connected via the contact electrode 25 positioned between the first wiring 31 and the first p-type semiconductor layer 11a.
[0026] The second wiring 32 electrically connects the second electrode 22 and the second n-type semiconductor layer 12c. The second wiring 32 is disposed inside the plurality of second openings 17. In the light-emitting element 100, the second wiring 32 extends from under the second electrode 22 to under the second n-type semiconductor layer 12c. In the light-emitting element 100, the second wiring 32 and the second n-type semiconductor layer 12c are electrically connected by the second wiring 32 and the second n-type semiconductor layer 12c being in contact with each other.
[0027] The third wiring 33 electrically connects the third electrode 23 and the first n-type semiconductor layer 11c. The third wiring 33 is disposed inside the plurality of first openings 16. In the light-emitting element 100, the third wiring 33 is disposed under the first n-type semiconductor layer 11c. In the light-emitting element 100, the third wiring 33 and the first n-type semiconductor layer 11c are electrically connected by the third wiring 33 and the first n-type semiconductor layer 11c being in contact with each other.
[0028] The first wiring 31, the second wiring 32, and the third wiring 33 are each made of, for example, a metal material. As the metal material, for example, at least one of metals such as Au (gold), Pt (platinum), Pd (palladium), Rh (rhodium), Ni (nickel), W (tungsten), Mo (molybdenum), Cr (chromium), Ti (titanium), Al (aluminum), Cu (copper), and alloys containing these metals can be used. The first electrode 21 and the second electrode 22 may each be a single layer or a laminate in which a plurality of layers are laminated. The first wiring 31, the second wiring 32, and the third wiring 33 can be, for example, a laminate in which a Ti layer, an Al-Si-Cu alloy layer, a Ti layer, a Pt layer, an Au layer, and a Ti layer are laminated in this order.
[0029] The light-emitting element 100 further includes a conductive member 40. The conductive member 40 is disposed between the third wiring 33 and the third electrode 23. The conductive member 40 electrically connects the third wiring 33 and the third electrode 23. A part 40a of the conductive member 40 is disposed inside the plurality of first openings 16. A part 40a of the conductive member 40 contacts the third wiring 33 inside the plurality of first openings 16. Another part 40b of the conductive member 40 is disposed, for example, inside the plurality of second openings 17. In this case, the light-emitting element 100 further includes a first insulating film 45. The first insulating film 45 is disposed between another part 40b of the conductive member 40 and the second wiring 32. The first insulating film 45 insulates between the conductive member 40 and the second wiring 32. For example, when the third electrode 23 is not disposed under the semiconductor laminate 10, the conductive member 40 may not be disposed.
[0030] The conductive member 40 is made of, for example, a metal material. As the metal material, for example, at least one of metals such as Ni (nickel), Sn (tin), Au (gold), In (indium), Pb (lead), and alloys containing these metals can be used. The conductive member 40 may be a single layer or a laminate in which a plurality of layers are laminated.
[0031] The light-emitting element 100 further includes a second insulating film 50. The second insulating film 50 is disposed between the semiconductor laminate 10 and the first wiring 31, between the semiconductor laminate 10 and the second wiring 32, and between the semiconductor laminate 10 and the third wiring 33. A part of the second insulating film 50 is disposed between the semiconductor laminate 10 and the second wiring 32 inside a plurality of second openings 17. A part of the second insulating film 50 surrounds the second wiring 32 in plan view. Another part of the second insulating film 50 is disposed between the semiconductor laminate 10 and the third wiring 33 inside a plurality of first openings 16. Another part of the second insulating film 50 surrounds the third wiring 33 in plan view. Still another part of the second insulating film 50 is disposed between the first wiring 31 and the third wiring 33 and insulates the first wiring 31 and the third wiring 33. Still another part of the second insulating film 50 is disposed between the second wiring 32 and the third wiring 33 and insulates the second wiring 32 and the third wiring 33.
[0032] The second insulating film 50 is made of, for example, an insulating material. As the insulating material, for example, at least one of silicon oxide and silicon nitride can be used.
[0033] The light-emitting element 100 further includes a surface protection film 55. The surface protection film 55 is disposed on the semiconductor laminate 10. The surface protection film 55 protects the semiconductor laminate 10.
[0034] The surface protection film 55 is made of, for example, an insulating material. As the insulating material, for example, an oxide or a nitride containing at least one selected from the group consisting of Si (silicon), Ti (titanium), Zr (zirconium), Nb (niobium), Ta (tantalum), Al (aluminum), and Hf (hafnium) can be used. As the insulating material, for example, at least one of silicon oxide and silicon nitride can be used.
[0035] As shown in FIG. 1, in the light-emitting element 100, the total area of the plurality of second openings 17 in plan view is larger than the total area of the plurality of first openings 16 in plan view. The total area of the plurality of second openings 17 in plan view is preferably 1.1 times or more and 2 times or less the total area of the plurality of second openings 17 in plan view. The total area of the plurality of second openings 17 in plan view is the sum of the areas of all the first openings 16 in plan view. The total area of the plurality of second openings 17 in plan view is the sum of the areas of all the second openings 17 in plan view.
[0036] In the light-emitting element 100, the areas of the plurality of first openings 16 in plan view are the same as each other. In the light-emitting element 100, the areas of the plurality of second openings 17 in plan view are the same as each other. The areas of the plurality of first openings 16 in plan view may be different from each other. The areas of the plurality of second openings 17 in plan view may be different from each other.
[0037] In the light-emitting element 100, the area of the third wiring 33 in contact with the first n-type semiconductor layer 11c in each of the plurality of first openings 16 is, for example, smaller than the area of the second wiring 32 in contact with the second n-type semiconductor layer 12c in each of the plurality of second openings 17.
[0038] As shown in FIG. 1, in plan view, the semiconductor laminate 10 has a central portion 10a and an outer peripheral portion 10b. The central portion 10a includes, for example, the center of the semiconductor laminate 10 in plan view. The outer peripheral portion 10b surrounds the central portion 10a in plan view. The outer peripheral portion 10b includes, for example, the outer peripheral edge of the semiconductor laminate 10 in plan view. For example, the length from the center of the semiconductor laminate 10 to the boundary between the central portion 10a and the outer peripheral portion 10b is the same as the length from the outer peripheral edge of the semiconductor laminate 10 to the boundary between the central portion 10a and the outer peripheral portion 10b.
[0039] The plurality of second openings 17 are arranged, for example, in a region overlapping with the central portion 10a in a plan view. The plurality of first openings 16 are arranged, for example, in a region overlapping with the outer peripheral portion 10b in a plan view. In the light-emitting element 100, the plurality of first openings 16 are arranged in both a region overlapping with the central portion 10a in a plan view and a region overlapping with the outer peripheral portion 10b in a plan view. In the light-emitting element 100, the plurality of second openings 17 are arranged in both a region overlapping with the central portion 10a in a plan view and a region overlapping with the outer peripheral portion 10b in a plan view. In the light-emitting element 100, the plurality of first openings 16 and the plurality of second openings 17 are alternately arranged in the X direction and the Y direction. In the light-emitting element 100, the plurality of first openings 16 are arranged at the same intervals in the X direction and the Y direction, and the plurality of second openings 17 are arranged at the same intervals in the X direction and the Y direction.
[0040] At least a part of the upper surface of the semiconductor laminate 10 is, for example, roughened. By roughening the upper surface of the semiconductor laminate 10, the light extraction efficiency of the light emitted upward from the semiconductor laminate 10 can be improved. The upper surface of the semiconductor laminate 10 is the upper surface of the second n-type semiconductor layer 12c.
[0041] As shown in FIG. 2, the second n-type semiconductor layer 12c has a first region 12c1 and a second region 12c2. The first region 12c1 overlaps with the plurality of first openings 16 in a plan view. The second region 12c2 overlaps with the plurality of second openings 17 in a plan view. The upper surface of the first region 12c1 is, for example, roughened. The upper surface of the second region 12c2 is, for example, not roughened. The surface roughness of the upper surface of the first region 12c1 is larger than the surface roughness of the upper surface of the second region 12c2.
[0042] FIG. 3 is a cross-sectional view showing a current path in a first light-emitting state of the light-emitting element according to the first embodiment. FIG. 4 is a cross-sectional view showing a current path in a second light-emitting state of the light-emitting element according to the first embodiment. FIG. 5 is a cross-sectional view showing a current path in a third light-emitting state of the light-emitting element according to the first embodiment. As shown in FIGS. 3 to 5, the light-emitting element 100 has three light-emitting states: a first light-emitting state, a second light-emitting state, and a third light-emitting state.
[0043] The first light-emitting state is a state in which both the first active layer 11b and the second active layer 12b are emitting light. FIG. 3 shows the current path in the first light-emitting state. As shown in FIG. 3, in the first light-emitting state, the first electrode 21 functions as the positive electrode and the second electrode 22 functions as the negative electrode. Specifically, the current flows from the first electrode 21, through the first wiring 31, the contact electrode 25, the first p-type semiconductor layer 11a, the first active layer 11b, the first n-type semiconductor layer 11c, the intermediate layer 13, the second p-type semiconductor layer 12a, the second active layer 12b, the second n-type semiconductor layer 12c, and the second wiring 32, and then flows to the second electrode 22. As a result, both the first active layer 11b and the second active layer 12b emit light.
[0044] The second light-emitting state is a state in which the second active layer 12b does not emit light and the first active layer 11b emits light. FIG. 4 shows the current path in the second light-emitting state. As shown in FIG. 4, in the second light-emitting state, the first electrode 21 functions as the positive electrode and the third electrode 23 functions as the negative electrode. Specifically, the current flows from the first electrode 21, through the first wiring 31, the contact electrode 25, the first p-type semiconductor layer 11a, the first active layer 11b, the first n-type semiconductor layer 11c, the third wiring 33, and the conductive member 40 (part 40a), and then flows to the third electrode 23. As a result, the second active layer 12b does not emit light and the first active layer 11b emits light.
[0045] The third light-emitting state is a state in which the first active layer 11b does not emit light and the second active layer 12b emits light. FIG. 5 shows the current path in the third light-emitting state. As shown in FIG. 5, in the third light-emitting state, the third electrode 23 functions as the positive electrode and the second electrode 22 functions as the negative electrode. Specifically, the current flows from the third electrode 23, through the conductive member 40 (part 40a), the third wiring 33, the first n-type semiconductor layer 11c, the intermediate layer 13, the second p-type semiconductor layer 12a, the second active layer 12b, the second n-type semiconductor layer 12c, and the second wiring 32, and then flows to the second electrode 22. As a result, the first active layer 11b does not emit light and the second active layer 12b emits light.
[0046] In this way, in the light-emitting element 100, the light emission of the first active layer 11b and the light emission of the second active layer 12b can be controlled individually. By switching the active layer to be light-emitted, the first active layer 11b and the second active layer 12b can be used alternately. Thereby, the heat generation of the semiconductor laminate 10 can be reduced, and the shift of the emission wavelength due to the heat generation of the semiconductor laminate 10 can be reduced. For example, when the first active layer 11b and the second active layer 12b emit ultraviolet light, since the semiconductor laminate 10 is likely to generate heat, the reduction of heat generation by switching the active layer to be light-emitted is particularly effective. Further, for example, when the peak wavelength of the light emitted from the first active layer 11b is different from the peak wavelength of the light emitted from the second active layer 12b, by switching the active layer to be light-emitted, it becomes a light-emitting element capable of switching the emission wavelength.
[0047] Also, when the second active layer 12b emits light, such as in the first light emission state and the third light emission state, since the intermediate layer 13 is present in the current path, the forward voltage VF tends to be high. Therefore, it is preferable that the total area in plan view of the plurality of second openings 17 is larger than the total area in plan view of the plurality of first openings 16. By doing so, the area of the second wiring 32 in contact with the second n-type semiconductor layer 12c in each of the plurality of second openings 17 can be increased. As a result, in the first light emission state and the third light emission state, the increase in the forward voltage VF can be reduced.
[0048] Also, by setting the total area in plan view of the plurality of second openings 17 to be 1.1 times or more and 2 times or less the total area in plan view of the plurality of first openings 16, while reducing the forward voltage VF in the first light emission state and the second light emission state, it is possible to reduce the situation where the difference between the forward voltage VF in the second light emission state and the forward voltage VF in the third light emission state becomes too large.
[0049] Further, when a part 40a of the conductive member 40 is disposed inside a plurality of first openings 16, even when the third electrode 23 is disposed under the semiconductor laminate 10, the part 40a of the conductive member 40 can electrically connect the third wiring 33 and the third electrode 23. For example, as in the second embodiment described later, in the second opening 17, it is also possible to design to electrically connect the conductive member 40 and the second n-type semiconductor layer 12c. However, it is preferable to dispose a part 40a of the conductive member 40 inside a plurality of first openings 16 and electrically connect the third wiring 33 and the first n-type semiconductor layer 11c via the third electrode 23. More specifically, since the plurality of first openings 16 are shallower than the plurality of second openings 17, the conductive member 40 is easily filled. In other words, even when the conductive member 40 is disposed in the plurality of first openings 16, voids are less likely to occur in the plurality of first openings 16. Therefore, the forward voltage VF can be made less likely to increase.
[0050] Also, as shown in FIG. 2, it is preferable that another part 40b of the conductive member 40 and the first insulating film 45 are disposed inside the plurality of second openings 17. As a result, the heat generated by the semiconductor laminate 10 can be easily dissipated through the conductive member 40. Further, since the first insulating film 45 is disposed between another part 40b of the conductive member 40 and the second wiring 32, even when another part 40b of the conductive member 40 is disposed inside the plurality of second openings 17, the first insulating film 45 can insulate another part 40b of the conductive member 40 and the second wiring 32.
[0051] Further, when emitting light while switching between the first active layer 11b and the second active layer 12b, a plurality of first openings 16 serve as current paths in both the case of emitting light from the first active layer 11b and the case of emitting light from the second active layer 12b. Therefore, as shown in FIG. 1, it is preferable that the plurality of first openings 16 are arranged in a region overlapping with the outer peripheral portion 10b of the semiconductor laminate 10 in plan view. By arranging the plurality of first openings 16 in this way, it is easy to expand the light-emitting region of the light-emitting element 100 to the end of the semiconductor laminate 10. Further, while the plurality of first openings 16 are arranged in a region overlapping with the outer peripheral portion 10b of the semiconductor laminate 10 in plan view, the plurality of second openings 17 are arranged in a region overlapping with the central portion 10a of the semiconductor laminate 10 in plan view, and it is more preferable that the plurality of first openings 16 are arranged in a region overlapping with the outer peripheral portion 10b of the semiconductor laminate 10 in plan view.
[0052] Also, when the upper surface of the semiconductor laminate 10 is roughened, the light extraction efficiency of the light emitted upward from the semiconductor laminate 10 can be improved. On the other hand, when the entire upper surface of the semiconductor laminate 10 is roughened, the thickness of the semiconductor laminate 10 becomes partially thin, and the forward voltage VF tends to increase. Since the upper ends of the plurality of second openings 17 are located above the upper ends of the plurality of first openings 16, the thickness of the portion of the semiconductor laminate 10 overlapping the plurality of second openings 17 in plan view tends to be thinner than the thickness of the portion overlapping the plurality of first openings 16 in plan view. Therefore, as shown in FIG. 2, it is preferable to roughen the upper surface of the first region 12c1 of the second n-type semiconductor layer 12c that overlaps the plurality of first openings 16 in plan view, and not to roughen the upper surface of the second region 12c2 that overlaps the plurality of second openings 17 in plan view. In other words, it is preferable that the surface roughness of the upper surface of the first region 12c1 is made larger than the surface roughness of the upper surface of the second region 12c2. As a result, in the first region 12c1, the light extraction efficiency can be improved, and in the second region 12c2, it is possible to reduce the decrease in thickness due to roughening and reduce the increase in the forward voltage VF.
[0053] (Modification example) FIG. 6 is a plan view showing a light-emitting element according to a modification example of the first embodiment. As shown in FIG. 6, in the light-emitting element 100A according to the modified example of the first embodiment, the arrangement of the plurality of first openings 16 and the plurality of second openings 17 in a plan view is different from that of the light-emitting element 100. In other respects, the light-emitting element 100A is the same as the above-described light-emitting element 100.
[0054] In the light-emitting element 100A, the plurality of second openings 17 are arranged only in a region overlapping the central portion 10a in a plan view. In the light-emitting element 100A, the plurality of first openings 16 are arranged in a region overlapping the outer peripheral portion 10b in a plan view. In the light-emitting element 100A, the plurality of first openings 16 and the plurality of second openings 17 are arranged in a lattice pattern at the same interval. In the light-emitting element 100A, one first opening 16 is arranged at the center of the region overlapping the central portion 10a in a plan view, a plurality of second openings 17 are arranged around this first opening 16, and a plurality of first openings 16 are arranged around these plurality of second openings 17.
[0055] As described above, when emitting light while switching between the first active layer 11b and the second active layer 12b, the plurality of first openings 16 serve as current paths in both the case of emitting light from the first active layer 11b and the case of emitting light from the second active layer 12b. Therefore, as shown in FIG. 6, by arranging the plurality of first openings 16 in a region overlapping the outer peripheral portion 10b of the semiconductor laminate 10 in a plan view and arranging the plurality of second openings 17 only in a region overlapping the central portion 10a in a plan view, it is easy to expand the light-emitting region of the light-emitting element 100A to the end of the semiconductor laminate 10 in both the case of emitting light from the first active layer 11b and the case of emitting light from the second active layer 12b. Further, as shown in FIG. 6, it is preferable to arrange the first opening 16 at a position surrounded by the plurality of second openings 17 in the region overlapping the central portion 10a in a plan view. Thereby, in the light-emitting element 100A, the variation in the light-emitting distribution can be reduced.
[0056] (Second Embodiment) FIG. 7 is a plan view showing a light-emitting element according to the second embodiment. FIG. 8 is a cross-sectional view showing a light-emitting element according to the second embodiment. FIG. 8 shows a cross section taken along line VIII-VIII shown in FIG. 7. As shown in FIGS. 7 and 8, the light-emitting element 200 according to the second embodiment includes a semiconductor laminate 10, a first electrode 21, a second electrode 22, a third electrode 23, a first wiring 31, a second wiring 32, and a third wiring 33.
[0057] In the light-emitting element 200, the second electrode 22 is electrically connected to the first n-type semiconductor layer 11c. In the light-emitting element 200, the third electrode 23 is electrically connected to the second n-type semiconductor layer 12c. In the light-emitting element 200, the second wiring 32 is disposed inside the plurality of first openings 16. In the light-emitting element 200, the second wiring 32 electrically connects the second electrode 22 and the first n-type semiconductor layer 11c. In the light-emitting element 200, the second wiring 32 has a portion connected to the second electrode 22 and a portion connected to the first n-type semiconductor layer 11c. The portion connected to the second electrode 22 bypasses the plurality of second openings 17 (a part 40a of the conductive member 40) and is connected to the portion connected to the first n-type semiconductor layer 11c. In the light-emitting element 200, the third wiring 33 is disposed inside the plurality of second openings 17. In the light-emitting element 200, the third wiring 33 electrically connects the third electrode 23 and the second n-type semiconductor layer 12c. In other respects, the light-emitting element 200 is the same as the above-described light-emitting element 100.
[0058] In the light-emitting element 200, the total area of the plurality of second openings 17 in plan view is, for example, larger than the total area of the plurality of first openings 16 in plan view. The total area of the plurality of second openings 17 in plan view is preferably 1.1 times or more and 2 times or less the total area of the plurality of first openings 16 in plan view.
[0059] The area of the third wiring 33 in contact with the second n-type semiconductor layer 12c in each of the plurality of second openings 17 is, for example, larger than the area of the second wiring 32 in contact with the first n-type semiconductor layer 11c in each of the plurality of first openings 16.
[0060] In the light-emitting element 200, a part 40a of the conductive member 40 is disposed inside a plurality of second openings 17. The part 40a of the conductive member 40 is in contact with the third wiring 33 inside the plurality of second openings 17. In the light-emitting element 200, another part 40b of the conductive member 40 is disposed, for example, inside a plurality of first openings 16. In this case, the first insulating film 45 is disposed between the other part 40b of the conductive member 40 and the second wiring 32. The first insulating film 45 insulates between the other part 40b of the conductive member 40 and the second wiring 32.
[0061] FIG. 9 is a cross-sectional view showing a current path in a first light-emitting state of a light-emitting element according to the second embodiment. FIG. 10 is a cross-sectional view showing a current path in a second light-emitting state of a light-emitting element according to the second embodiment. FIG. 11 is a cross-sectional view showing a current path in a third light-emitting state of a light-emitting element according to the second embodiment. As shown in FIGS. 9 to 11, the light-emitting element 200 has three light-emitting states: a first light-emitting state, a second light-emitting state, and a third light-emitting state.
[0062] The first light-emitting state is a state in which both the first active layer 11b and the second active layer 12b are emitting light. FIG. 9 shows the current path in the first light-emitting state. As shown in FIG. 9, in the first light-emitting state, the first electrode 21 functions as a positive electrode, and the third electrode 23 functions as a negative electrode. More specifically, current flows from the first electrode 21, through the first wiring 31, the contact electrode 25, the first p-type semiconductor layer 11a, the first active layer 11b, the first n-type semiconductor layer 11c, the intermediate layer 13, the second p-type semiconductor layer 12a, the second active layer 12b, the second n-type semiconductor layer 12c, the third wiring 33, and the conductive member 40 (part 40a), and then flows to the third electrode 23. As a result, both the first active layer 11b and the second active layer 12b emit light.
[0063] The second light-emitting state is a state in which the first active layer 11b emits light while the second active layer 12b does not emit light. FIG. 10 shows the current path in the second light-emitting state. As shown in FIG. 10, in the second light-emitting state, the first electrode 21 functions as the positive electrode and the second electrode 22 functions as the negative electrode. Specifically, the current flows from the first electrode 21 through the first wiring 31, the contact electrode 25, the first p-type semiconductor layer 11a, the first active layer 11b, the first n-type semiconductor layer 11c, and the second wiring 32 to the second electrode 22. As a result, the first active layer 11b emits light while the second active layer 12b does not emit light. In FIG. 10, the current path through the second wiring 32, which is not shown in the cross section along the line VIII-VIII, is represented by a dashed line.
[0064] The third light-emitting state is a state in which the second active layer 12b emits light while the first active layer 11b does not emit light. FIG. 11 shows the current path in the third light-emitting state. As shown in FIG. 11, in the third light-emitting state, the second electrode 22 functions as the positive electrode and the third electrode 23 functions as the negative electrode. Specifically, the current flows from the second electrode 22 through the second wiring 32, the first n-type semiconductor layer 11c, the intermediate layer 13, the second p-type semiconductor layer 12a, the second active layer 12b, the second n-type semiconductor layer 12c, the third wiring 33, and the conductive member 40 (part 40a) to the third electrode 23. As a result, the second active layer 12b emits light while the first active layer 11b does not emit light. In FIG. 11, the current path through the second wiring 32, which is not shown in the cross section along the line VIII-VIII, is represented by a dashed line.
[0065] In this way, in the light-emitting element 200, the light emission of the first active layer 11b and the light emission of the second active layer 12b can be controlled individually. By switching the active layer to be light-emitted, the first active layer 11b and the second active layer 12b can be used alternately. Thereby, heat generation of the semiconductor laminate 10 can be reduced, and a shift in the emission wavelength due to heat generation of the semiconductor laminate 10 can be reduced. For example, when the first active layer 11b and the second active layer 12b emit ultraviolet light, since the semiconductor laminate 10 is likely to generate heat, reduction of heat generation by switching the active layer to be light-emitted is particularly effective. Further, for example, when the peak wavelength of the light emitted from the first active layer 11b is different from the peak wavelength of the light emitted from the second active layer 12b, it becomes a light-emitting element capable of switching the emission wavelength by switching the active layer to be light-emitted.
[0066] Furthermore, in the light-emitting element 200, when the peak wavelength of the light emitted from the first active layer 11b and the peak wavelength of the light emitted from the second active layer 12b are in the ultraviolet region and it is desired to make the peak wavelength of the light emitted from the first active layer 11b different from the peak wavelength of the light emitted from the second active layer 12b, it is easy to reduce a decrease in luminous efficiency. Specifically, when the peak wavelength of the light emitted from the first active layer 11b and the peak wavelength of the light emitted from the second active layer 12b are in the ultraviolet region and the peak wavelength of the light emitted from the second active layer 12b is shorter than the peak wavelength of the light emitted from the first active layer 11b, it is easy to reduce a decrease in luminous efficiency. More specifically, light emitted from the active layer tends to be more easily absorbed by the semiconductor layer as the wavelength is shorter. Therefore, in the light-emitting element 200, by making the peak wavelength of the light emitted from the second active layer 12b, which is close to the upper surface of the semiconductor laminate 10 that is the light extraction surface, shorter than the peak wavelength of the light emitted from the first active layer 11b, it is possible to make it difficult for the light emitted from the second active layer 12b to be absorbed by the semiconductor layer. Further, the semiconductor layer tends to generate heat more easily as the wavelength of the light emitted from the active layer is shorter. In the light-emitting element 200, heat generated from the second active layer 12b can be easily dissipated via the third wiring 33, the conductive member 40, and the third electrode 23. This is because in the second opening 17, the third wiring 33 and the conductive member 40, each made of a metal material, are continuously arranged. As a result, a shift in wavelength due to heat generation of the second active layer 12b can be reduced, and the luminous efficiency can be increased.
[0067] Also, when causing the second active layer 12b to emit light, such as in the first light emission state and the third light emission state, since the intermediate layer 13 is present in the current path, the forward voltage VF tends to be high. Therefore, it is preferable that the total area of the plurality of second openings 17 in plan view is larger than the total area of the plurality of first openings 16 in plan view. By doing so, the area of the third wiring 33 in contact with the second n-type semiconductor layer 12c can be increased in each of the plurality of second openings 17. As a result, in the first light emission state and the third light emission state, the forward voltage VF can be reduced.
[0068] Also, by setting the total area of the plurality of second openings 17 in plan view to be 1.1 times or more and 2 times or less the total area of the plurality of first openings 16 in plan view, it is possible to reduce the forward voltage VF while reducing the excessive increase in the difference between the forward voltage VF in the second light emission state and the forward voltage VF in the third light emission state.
[0069] Also, as shown in FIG. 8, since a part 40a of the conductive member 40 is disposed inside the plurality of second openings 17, even when the third electrode 23 is disposed under the semiconductor laminate 10, the part 40a of the conductive member 40 can electrically connect the third wiring 33 and the third electrode 23.
[0070] Also, it is preferable that the other part 40b of the conductive member 40 and the first insulating film 45 are disposed inside the plurality of first openings 16. As a result, heat generated by the semiconductor laminate 10 can be easily dissipated through the conductive member 40. Further, since the first insulating film 45 is disposed between the other part 40b of the conductive member 40 and the second wiring 32, even when the other part 40b of the conductive member 40 is disposed inside the plurality of first openings 16, the first insulating film 45 can insulate the other part 40b of the conductive member 40 and the second wiring 32.
[0071] Also, when causing light emission while switching between the first active layer 11b and the second active layer 12b, a plurality of first openings 16 serve as current paths in both the case of causing the first active layer 11b to emit light and the case of causing the second active layer 12b to emit light. Therefore, as shown in FIG. 7, it is preferable that the plurality of first openings 16 are arranged in a region overlapping with the outer peripheral portion 10b of the semiconductor laminate 10 in a plan view. By arranging the plurality of first openings 16 in this manner, it is easy to expand the light-emitting region of the light-emitting element 100 to the end of the semiconductor laminate 10. Further, it is more preferable that the plurality of first openings 16 are arranged in a region overlapping with the outer peripheral portion 10b of the semiconductor laminate 10 in a plan view, and the plurality of second openings 17 are arranged in a region overlapping with the central portion 10a of the semiconductor laminate 10 in a plan view.
[0072] Also, also in the second embodiment, among the second n-type semiconductor layers 12c, the upper surface of the first region 12c1 overlapping with the plurality of first openings 16 in a plan view is roughened, and the upper surface of the second region 12c2 overlapping with the plurality of second openings 17 in a plan view is not roughened. In other words, it is preferable that the surface roughness of the upper surface of the first region 12c1 is made larger than the surface roughness of the upper surface of the second region 12c2. As a result, in the first region 12c1, while improving the light extraction efficiency, in the second region 12c2, it is possible to reduce the decrease in thickness due to roughening and reduce the increase in the forward voltage VF.
[0073] (Modification example) FIG. 12 is a plan view showing a light-emitting element according to a modification example of the second embodiment. As shown in FIG. 12, in the light-emitting element 200A according to the modification example of the second embodiment, the arrangement of the plurality of first openings 16 and the plurality of second openings 17 in a plan view is different from that of the light-emitting element 200. In other respects, the light-emitting element 200A is the same as the above-described light-emitting element 200.
[0074] In the light-emitting element 200A, the plurality of second openings 17 are arranged only in a region overlapping the central portion 10a in a plan view. In the light-emitting element 200A, the plurality of first openings 16 are arranged in a region overlapping the outer peripheral portion 10b in a plan view. In the light-emitting element 200A, the plurality of first openings 16 and the plurality of second openings 17 are arranged in a grid pattern at the same interval. In the light-emitting element 200A, one first opening 16 is arranged at the center of the region overlapping the central portion 10a in a plan view, a plurality of second openings 17 are arranged around this first opening 16, and a plurality of first openings 16 are arranged around these plurality of second openings 17.
[0075] As described above, when light is emitted while switching between the first active layer 11b and the second active layer 12b, the plurality of first openings 16 serve as current paths in both the case of emitting light from the first active layer 11b and the case of emitting light from the second active layer 12b. Therefore, as shown in FIG. 12, by arranging the plurality of first openings 16 in a region overlapping the outer peripheral portion 10b of the semiconductor laminate 10 in a plan view and arranging the plurality of second openings 17 only in a region overlapping the central portion 10a in a plan view, it is easy to expand the light-emitting region of the light-emitting element 200A to the end of the semiconductor laminate 10 in both the case of emitting light from the first active layer 11b and the case of emitting light from the second active layer 12b. Further, as shown in FIG. 12, in the region overlapping the central portion 10a in a plan view, it is preferable to arrange the first opening 16 at a position surrounded by the plurality of second openings 17. Thereby, in the light-emitting element 200A, the variation in the light-emitting distribution can be reduced.
[0076] The embodiment may include the following configuration.
[0077] (Configuration 1) A semiconductor laminate having a first p-type semiconductor layer, a first active layer disposed on the first p-type semiconductor layer, a first n-type semiconductor layer disposed on the first active layer, an intermediate layer disposed on the first n-type semiconductor layer, a second p-type semiconductor layer disposed on the intermediate layer, a second active layer disposed on the second p-type semiconductor layer, and a second n-type semiconductor layer disposed on the second active layer, the semiconductor laminate having a plurality of first openings disposed continuously in the first p-type semiconductor layer, the first active layer, and the first n-type semiconductor layer, and a plurality of second openings disposed continuously in the first p-type semiconductor layer, the first active layer, the first n-type semiconductor layer, the intermediate layer, the second p-type semiconductor layer, the second active layer, and the second n-type semiconductor layer, A first electrode located away from the semiconductor laminate in a plan view and electrically connected to the first p-type semiconductor layer, A second electrode electrically connected to the second n-type semiconductor layer, A third electrode electrically connected to the first n-type semiconductor layer, A first wiring disposed under the semiconductor laminate and electrically connecting the first electrode and the first p-type semiconductor layer, A second wiring disposed inside the plurality of second openings and electrically connecting the second electrode and the second n-type semiconductor layer, A third wiring disposed inside the plurality of first openings and electrically connecting the third electrode and the first n-type semiconductor layer, A light-emitting element comprising the above.
[0078] (Configuration 2) The light-emitting element according to Configuration 1, wherein a total area in a plan view of the plurality of second openings is larger than a total area in a plan view of the plurality of first openings.
[0079] (Configuration 3) The light-emitting element according to Configuration 2, wherein a total area in a plan view of the plurality of second openings is 1.1 times or more and 2 times or less of a total area in a plan view of the plurality of first openings.
[0080] (Configuration 4) A conductive member is further provided, which is disposed between the third wiring and the third electrode and electrically connects the third wiring and the third electrode. A part of the conductive member is disposed inside the plurality of first openings, and the light-emitting element according to any one of Configurations 1 to 3.
[0081] (Configuration 5) Another part of the conductive member is disposed inside the plurality of second openings. The light-emitting element according to Configuration 4, further comprising an insulating film disposed between another part of the conductive member and the second wiring.
[0082] (Configuration 6) A semiconductor laminate having a first p-type semiconductor layer, a first active layer disposed on the first p-type semiconductor layer, a first n-type semiconductor layer disposed on the first active layer, an intermediate layer disposed on the first n-type semiconductor layer, a second p-type semiconductor layer disposed on the intermediate layer, a second active layer disposed on the second p-type semiconductor layer, and a second n-type semiconductor layer disposed on the second active layer, the semiconductor laminate having a plurality of first openings continuously disposed in the first p-type semiconductor layer, the first active layer, and the first n-type semiconductor layer, and a plurality of second openings continuously disposed in the first p-type semiconductor layer, the first active layer, the first n-type semiconductor layer, the intermediate layer, the second p-type semiconductor layer, the second active layer, and the second n-type semiconductor layer. In a plan view, a first electrode located away from the semiconductor laminate and electrically connected to the first p-type semiconductor layer. A second electrode electrically connected to the first n-type semiconductor layer. A third electrode electrically connected to the second n-type semiconductor layer. A first wiring disposed under the semiconductor laminate and electrically connecting the first electrode and the first p-type semiconductor layer. A second wiring disposed inside the plurality of first openings and electrically connecting the second electrode and the first n-type semiconductor layer. A third wiring disposed inside the plurality of second openings and electrically connecting the third electrode and the second n-type semiconductor layer. A light-emitting element comprising
[0083] (Configuration 7) The light-emitting element according to Configuration 6, wherein a total area of the plurality of second openings in a plan view is larger than a total area of the plurality of first openings in the plan view.
[0084] (Configuration 8) The light-emitting element according to Configuration 7, wherein the total area of the plurality of second openings in the plan view is 1.1 times or more and 2 times or less the total area of the plurality of first openings in the plan view.
[0085] (Configuration 9) Further comprising a conductive member disposed between the third wiring and the third electrode and electrically connecting the third wiring and the third electrode. The light-emitting element according to any one of Configurations 6 to 8, wherein a part of the conductive member is disposed inside the plurality of second openings.
[0086] (Configuration 10) Another part of the conductive member is disposed inside the plurality of first openings. The light-emitting element according to Configuration 9, further comprising an insulating film disposed between the other part of the conductive member and the second wiring.
[0087] (Configuration 11) In a plan view, the semiconductor laminate has a central portion and an outer peripheral portion surrounding the central portion. The plurality of second openings are disposed in a region overlapping the central portion in the plan view. The light-emitting element according to any one of Configurations 1 to 10, wherein the plurality of first openings are disposed in a region overlapping the outer peripheral portion in the plan view.
[0088] (Configuration 12) The light-emitting element according to Configuration 11, wherein the plurality of second openings are disposed only in a region overlapping the central portion in the plan view.
[0089] (Configuration 13) The 2n-type semiconductor layer has a first region overlapping with the plurality of first openings in a plan view and a second region overlapping with the plurality of second openings in a plan view. The light-emitting element according to any one of Configurations 1 to 12, wherein a surface roughness of an upper surface of the first region is larger than a surface roughness of an upper surface of the second region.
[0090] As described above, according to the embodiment, a light-emitting element capable of individually controlling light emission from the first active layer and light emission from the second active layer is provided.
[0091] Each of the above-described embodiments is an example embodying the present invention, and the present invention is not limited to these embodiments. For example, in each of the above-described embodiments, those obtained by adding, deleting, or changing some components or steps are also included in the present invention. Further, each of the above-described embodiments can be implemented in combination with each other.
Description of Reference Numerals
[0092] 10: Semiconductor laminate 10a: Central portion 10b: Peripheral portion 11a: First p-type semiconductor layer 11b: First active layer 11c: First n-type semiconductor layer 12a: Second p-type semiconductor layer 12b: Second active layer 12c: Second n-type semiconductor layer 12c1: First region 12c2: Second region 13: Intermediate layer 16: First opening 17: Second opening 21: First electrode 22: Second electrode 23: Third electrode 25: Contact electrode 31: First wiring 32: Second wiring 33: Third wiring 40: Conductive member 40a: Part 40b: Another part 45: First insulating film 50: Second insulating film 55: Surface protective film 100, 100A, 200, 200A: Light-emitting element
Claims
1. A semiconductor laminate having a first p-type semiconductor layer, a first active layer disposed on the first p-type semiconductor layer, a first n-type semiconductor layer disposed on the first active layer, an intermediate layer disposed on the first n-type semiconductor layer, a second p-type semiconductor layer disposed on the intermediate layer, a second active layer disposed on the second p-type semiconductor layer, and a second n-type semiconductor layer disposed on the second active layer, the semiconductor laminate having a plurality of first openings disposed continuously in the first p-type semiconductor layer, the first active layer, and the first n-type semiconductor layer, and a plurality of second openings disposed continuously in the first p-type semiconductor layer, the first active layer, the first n-type semiconductor layer, the intermediate layer, the second p-type semiconductor layer, the second active layer, and the second n-type semiconductor layer, A first electrode located away from the semiconductor laminate in a plan view and electrically connected to the first p-type semiconductor layer, A second electrode electrically connected to the second n-type semiconductor layer, A third electrode electrically connected to the first n-type semiconductor layer, A first wiring disposed under the semiconductor laminate and electrically connecting the first electrode and the first p-type semiconductor layer, A second wiring disposed inside the plurality of second openings and electrically connecting the second electrode and the second n-type semiconductor layer, A third wiring disposed inside the plurality of first openings and electrically connecting the third electrode and the first n-type semiconductor layer, A light-emitting element comprising the above.
2. The light-emitting element according to claim 1, wherein a total area of the plurality of second openings in a plan view is larger than a total area of the plurality of first openings in a plan view.
3. The light-emitting element according to claim 2, wherein the total area of the plurality of second openings in a plan view is 1.1 times or more and 2 times or less the total area of the plurality of first openings in a plan view.
4. Further comprising a conductive member disposed between the third wiring and the third electrode and electrically connecting the third wiring and the third electrode, The light-emitting element according to claim 1, wherein a part of the conductive member is disposed inside the plurality of first openings.
5. Another part of the conductive member is disposed inside the plurality of second openings, The light-emitting element according to claim 4, further comprising an insulating film disposed between the other part of the conductive member and the second wiring.
6. A semiconductor laminate having a first p-type semiconductor layer, a first active layer disposed on the first p-type semiconductor layer, a first n-type semiconductor layer disposed on the first active layer, an intermediate layer disposed on the first n-type semiconductor layer, a second p-type semiconductor layer disposed on the intermediate layer, a second active layer disposed on the second p-type semiconductor layer, and a second n-type semiconductor layer disposed on the second active layer, the semiconductor laminate having a plurality of first openings continuously disposed in the first p-type semiconductor layer, the first active layer, and the first n-type semiconductor layer, and a plurality of second openings continuously disposed in the first p-type semiconductor layer, the first active layer, the first n-type semiconductor layer, the intermediate layer, the second p-type semiconductor layer, the second active layer, and the second n-type semiconductor layer, A first electrode located away from the semiconductor laminate in a plan view and electrically connected to the first p-type semiconductor layer, A second electrode electrically connected to the first n-type semiconductor layer, A third electrode electrically connected to the second n-type semiconductor layer, A first wiring disposed under the semiconductor laminate and electrically connecting the first electrode and the first p-type semiconductor layer, A second wiring disposed inside the plurality of first openings and electrically connecting the second electrode and the first n-type semiconductor layer, A third wiring disposed inside the plurality of second openings and electrically connecting the third electrode and the second n-type semiconductor layer, A light-emitting element comprising:
7. The light-emitting element according to claim 6, wherein a total area of the plurality of second openings in a plan view is larger than a total area of the plurality of first openings in the plan view.
8. The total area of the plurality of second openings in plan view is 1.1 times or more and 2 times or less the total area of the plurality of first openings in plan view. The light-emitting element according to claim 7.
9. Further provided is a conductive member disposed between the third wiring and the third electrode and electrically connecting the third wiring and the third electrode. The light-emitting element according to claim 6, wherein a part of the conductive member is disposed inside the plurality of second openings.
10. Another part of the conductive member is disposed inside the plurality of first openings. The light-emitting element according to claim 9, further comprising an insulating film disposed between the other part of the conductive member and the second wiring.
11. In plan view, the semiconductor laminate has a central portion and an outer peripheral portion surrounding the central portion. The plurality of second openings are disposed in a region overlapping the central portion in plan view. The plurality of first openings are disposed in a region overlapping the outer peripheral portion in plan view. The light-emitting element according to any one of claims 1 to 10.
12. The plurality of second openings are disposed only in a region overlapping the central portion in plan view. The light-emitting element according to claim 11.
13. The second n-type semiconductor layer has a first region overlapping the plurality of first openings in plan view and a second region overlapping the plurality of second openings in plan view. The surface roughness of the upper surface of the first region is greater than the surface roughness of the upper surface of the second region. The light-emitting element according to any one of claims 1 to 10.
Citation Information
Patent Citations
Hybrid vertical cavity of multiple wavelength leds
US20090001389A1