Element substrate, liquid discharge head, and recording apparatus

Abstract

To solve the following problem that: in a conventional element substrate, in order to fix to either a mode for selecting a recording element or a mode for selecting an antifuse element, signal data of at least 1 bit is required; therefore, every time a recording element or an antifuse element is selected, the signal data amount increases, and particularly in the case of printing using a recording element, an increase in the signal data amount leads to an increase in time for selecting the recording element.SOLUTION: In an element substrate, a control data supply circuit includes: a plurality of stages of shift registers that hold serial data signals; a decoder circuit that outputs a selection signal for selecting either a recording element or a memory element; and a mask circuit connected to the decoder circuit. The mask circuit outputs a high-level or low-level signal to the decoder circuit based on bit data signals for switching memory elements input to the mask circuit.SELECTED DRAWING: Figure 7

Description

Technical Field

[0001] The present invention relates to an element substrate having a recording element and a memory element, a liquid ejection head having the element substrate, and a recording apparatus that performs recording using the liquid ejection head.

Background Art

[0002] In recent years, after a product is completed, an OTP (One Time Programmable) memory for recording various product-specific information such as chip ID, setting parameters, and the state of changes over time during product use is mounted on a semiconductor substrate. There are two types of OTP memories: those using a Poly fuse element and those using an anti-fuse element AF. A memory using an anti-fuse element can reduce the memory module size compared to a conventional Poly fuse memory, which is advantageous for saving space on the semiconductor substrate.

[0003] Also, in the liquid ejection head having a semiconductor substrate described in Patent Document 1, in order to further save space on the semiconductor substrate, it has a single selection circuit including a shift register circuit and a latch circuit. And it is described that the selection circuit can be used for both selection of the recording element and selection of the anti-fuse element.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, in the example described in Patent Document 1, it is necessary to determine either the mode of selecting a recording element or the mode of selecting an anti-fuse element. And at least 1 bit or more of signal data is required for this determination. For this reason, there has been a problem that the amount of signal data increases every time a recording element or an anti-fuse element is selected.

[0006] Particularly in the case of printing using a recording element, if the amount of signal data increases, the time for selecting the recording element increases, and as a result, there has been a problem that the printing speed decreases.

[0007] An object of the present invention is to solve at least one of the problems of the above prior art.

[0008] An object of the present invention is to provide a technique for suppressing an increase in the amount of data supplied to an element substrate for selecting a recording element during a recording operation.

Means for Solving the Problems

[0009] In order to achieve the above object, an element substrate according to an aspect of the present invention has the following configuration. That is, A plurality of recording elements, A driving element for the recording element for driving the recording element, A logical product circuit for selecting the recording element driven by the driving element for the recording element, A plurality of memory elements, A driving element for the memory element for driving the memory element, A logical product circuit for selecting the memory element driven by the driving element for the memory element, A control data supply circuit, In an element substrate having The control data supply circuit A plurality of stages of shift registers for holding serial data signals, A decoder circuit for outputting a selection signal for selecting either the recording element or the memory element a mask circuit connected to the decoder circuit; The mask circuit is configured to: output a high-level or low-level signal to the decoder circuit based on bit data signals for memory element switching input to the mask circuit. The element substrate is characterized by this.

Advantages of the Invention

[0010] According to the present invention, it becomes possible to suppress an increase in the amount of data supplied to the element substrate for selecting a recording element during a recording operation.

[0011] Other features and advantages of the present invention will become apparent from the following description with reference to the accompanying drawings. In the accompanying drawings, the same or similar components are denoted by the same reference numerals.

Brief Description of the Drawings

[0012] The accompanying drawings are included in the specification, form a part thereof, show embodiments of the present invention, and are used to explain the principles of the present invention together with the description.

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Embodiments for Carrying Out the Invention

[0013] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the invention according to the claims. Although a plurality of features are described in the embodiments, not all of these plurality of features are essential to the invention, and the plurality of features may be arbitrarily combined. Further, in the accompanying drawings, the same or similar configurations are denoted by the same reference numerals, and redundant descriptions are omitted.

[0014] Note that "recording" includes not only the case of forming significant information such as characters and figures, but also the case of forming images, patterns, patterns, etc. on a recording medium regardless of whether they are significant or not, or performing processing on the medium, and it does not matter whether or not it is made manifest so that it can be perceived visually by humans. In this embodiment, a sheet-like paper is assumed as the "recording medium", but it may be cloth, plastic film, or the like.

[0015] FIG. 6 is a diagram for explaining the inkjet recording apparatus 1000, the recording head unit 20, and the recording head 10 according to the embodiment of the present invention.

[0016] FIG. 6(a) is a schematic perspective view of an inkjet recording apparatus 1000 according to an embodiment. As shown in FIG. 6(a), the lead screw 5004 rotates via the driving force transmission gears 5008 and 5009 in conjunction with the forward and reverse rotations of the driving motor 5013. The carriage HC can mount the recording head unit 20 and has a pin (not shown in the figure) that engages with the spiral groove 5005 of the lead screw 5004. When the lead screw 5004 rotates, the carriage HC reciprocates in the directions of arrows a and b in the figure.

[0017] FIG. 6(b) is a perspective view showing an example of a recording head unit 20 including a recording head 10 according to an embodiment.

[0018] The recording head unit 20 includes a recording head 10 and a housing portion 24 that houses a recording agent (liquid; ink) to be supplied to the recording head 10, and these constitute a cartridge integrated therewith. Here, the recording head 10 is provided on the surface facing the recording medium P shown in FIG. 6(a). Note that these do not necessarily have to be integrated, and the housing portion 24 can also be in a removable form. The recording head unit 20 also includes a tape member 22. This tape member 22 has terminals for supplying power to the recording head 10, receives power from the main body of the inkjet recording apparatus 1000 via the contact 23, and exchanges various signals.

[0019] FIG. 6(c) is a schematic perspective view of the recording head 10 according to an embodiment.

[0020] The recording head 10 as a liquid ejection head includes a recording element substrate 11 and a flow path forming member 120. A plurality of heat acting portions 117 for applying heat energy generated by electrothermal conversion elements to a recording agent are arranged on the recording element substrate 11. Further, the flow path forming member 120 is also a discharge port member in which a plurality of discharge ports 121 for discharging the recording agent are arranged corresponding to the heat acting portions 117. Power and signals are sent from the main body of the recording apparatus 1000 to the recording element substrate 11 via the tape member 22, the electrothermal conversion elements are driven, and the generated heat energy is applied to the recording agent (liquid) via the heat acting portions 117, and the recording agent is discharged from the discharge ports 121.

[0021] FIG. 9 is a block diagram showing a schematic configuration of the recording apparatus 1000 according to the embodiment.

[0022] The controller 900 controls the operation of this recording apparatus 1000. The controller 900 has a CPU 901, a RAM 902, a ROM 903, and an input / output interface (I / O I / F) 904. The CPU 901 reads out a program stored in the ROM 903 and executes the program to execute the processes shown in the flowchart described later. Also, the CPU 901 controls various operations such as the printing process of this recording apparatus 1000. The input / output interface (I / O I / F) 904 is connected to a motor driver 905 that rotationally drives the aforementioned conveyance motor 5013. Note that the recording apparatus 1000 according to the embodiment includes an operation panel, various sensors, a paper feeding unit, etc. in addition to these, but these are omitted here.

[0023] Next, with reference to FIGS. 1 to 3, the circuit configurations of the ejection module and the memory module mounted on the recording element substrate 11 (hereinafter, also simply referred to as "substrate 11") as a semiconductor substrate according to the embodiment of the present invention will be described.

[0024] FIG. 1 is a diagram showing a part of the circuit configuration of the recording element substrate 11 according to the embodiment.

[0025] The substrate 11 includes a discharge module 204 and a memory module 206. The discharge module 204 includes a recording element Rh (for example, an electro-thermal conversion element that generates heat when energized), a drive element (transistor) MD1 for the recording element to drive the recording element Rh, and a logical product circuit AND1 for recording element selection. When the output of the logical product circuit AND1 becomes high level and the drive element MD1 is turned on, and the recording element Rh is energized and driven, a recording agent such as ink can be discharged from the discharge port 121 to perform recording.

[0026] The memory module 206 further includes an anti-fuse element AF as a memory element, a drive element MD2 for the memory element to write information to the anti-fuse element AF, and a logical product circuit AND2 for memory element selection. The anti-fuse element AF functions as a memory that fixedly holds information when an overvoltage is supplied and is programmable only once.

[0027] Based on the logical data signal transmitted from the control data supply circuit 201 as a signal supply circuit, the driving of the recording element Rh and the anti-fuse element AF is controlled. The control data supply circuit 201 includes a first shift register circuit 501, a second shift register circuit 502, latch circuits 503 and 504, a data mask circuit 505, a decoder circuit 506, etc., which will be described later with reference to FIG. 7 in detail. Logical data signals such as a clock signal CLK, a serial data signal DATA1, a bit data signal DATA2 for anti-fuse switching, a latch signal LT, and a recording element control signal HE (heat enable signal: not shown) can be input to this control data supply circuit 201 via the recording apparatus 1000 main body or a host PC (not shown). Also, a first power supply voltage VDD (for example, 3 to 5V) is supplied as a power supply voltage for logic to the logical product circuit AND1, the logical product circuit AND2, and the control data supply circuit 201.

[0028] Here, the control data supply circuit 201, for example, for m groups each having n ejection modules 204, selects one ejection module 204 included in each group in a determined order and drives the recording element Rh (so-called time-division driving). The control data supply circuit 201 outputs an m-bit group selection signal 210 and an n-bit block selection signal 211. By each ejection module 204 receiving at least one bit of the group selection signal 210 and at least one bit of the block selection signal 211, the recording element Rh is time-division driven.

[0029] Also, the control data supply circuit 201 controls the memory module 206 for each of y groups each having x memory modules 206 to time-division drive and control the anti-fuse element AF. Specifically, by each memory module 206 receiving at least one bit of each of the signals of the group selection signal 210 and the block selection signal 212, the anti-fuse element AF is time-division controlled. At this time, the ejection module 204 and the memory module 206 are driven exclusively, and the logical configuration is such that all the recording elements Rh and all the anti-fuse elements AF are not driven at the same time (details will be described later).

[0030] The AND circuit AND1 for recording element selection receives the corresponding group selection signal 210, block selection signal 211, and recording element control signal HE. When the output of the AND circuit AND1 turns on in response to the input signals, the corresponding recording element driving element MD1 becomes conductive, and the recording element Rh connected in series with the recording element driving element MD1 is driven.

[0031] Here, as the driving element MD1 for the recording element, for example, a DMOS transistor (Double-diffused MOSFET), which is a high-voltage-resistant MOS transistor, is used. In the case of an anti-fuse memory, generally, the driving current of the memory element is smaller than that of the recording element, and thus the current driving ability of the DMOS transistor can also be smaller. Therefore, the area of the driving element MD2 for the memory element may be made smaller than the area of the driving element MD1 for the recording element.

[0032] Also, as the AND circuit AND1 for recording element selection, for example, a MOS transistor is used. Here, the second power supply voltage VH (for example, 24V) is supplied to the ejection module 204 as the power supply voltage for driving the recording element, and the ground potential is set to GNDH.

[0033] Further, the corresponding group selection signal 210, block selection signal 212, and memory element control signal ME (not shown) are input to the AND circuit AND2 for memory selection. A signal corresponding to the input signals is output to the driving element MD2 for the memory element, and the conduction state / non-conduction state of the driving element MD2 is switched. As with the driving element MD1 of the recording element, a DMOS transistor is used for the driving element MD2 of the memory element. Also, as the AND circuit AND2 for memory element selection, a MOS transistor is used. The third power supply voltage VID (for example, 24V) for writing information to the anti-fuse element AF is supplied to the memory module 206, and the ground potential is set to GNDH. As shown in FIG. 1, the driving element MD1 of the recording element and the driving element MD2 of the memory element may be configured to be connected to a common GNDH pad via a common ground wiring.

[0034] Note that although the power supply voltage VID and the power supply voltage VH are independent power supply lines, when the minimum value of the voltage required for writing to the anti-fuse element AF is equal to or lower than the power supply voltage VH, for example, in combination with a step-down circuit, the power supply voltage VH may be used.

[0035] FIG. 2 is a circuit diagram for explaining the configuration of the memory module 206 used for the substrate 11 according to the embodiment.

[0036] Here, the AND2 logic circuit for memory selection is composed of a NAND circuit 306 and an inverter INV. The inverter INV has a PMOS transistor MP1 and an NMOS transistor MN1, and MOSFETs are used for the transistors MP1 and MN1. The output signal Sig of the NAND circuit 306 is input to the inverter INV, and the output signal Vg of the AND2 logic circuit is output to the gate of the memory driving element MD2. Note that FIG. 2 shows the arrangement of the driving element MD2 and the AND2 logic circuit shown in FIG. 1 with the left and right reversed.

[0037] Before information is written, the anti-fuse element AF functions as, for example, a capacitive element Ca. FIG. 2 shows the state before information is written to the anti-fuse element AF, and the anti-fuse element AF is represented by the capacitive element Ca. Similarly, in other figures, the anti-fuse element AF may be shown as the capacitive element Ca.

[0038] In this way, the capacitive element Ca as the anti-fuse element AF is connected in series with the memory driving element MD2 at one end thereof. And a power supply voltage VID is supplied to the other end of the capacitive element Ca when reading and writing information.

[0039] Furthermore, a resistive element (with a resistance value of Rp, hereinafter simply referred to as "resistive element Rp") connected in parallel with the anti-fuse element AF is provided. Thereby, even when the driving element MD2 for the memory element is in a non-conductive state, it is possible to prevent a situation where an overvoltage is applied across the anti-fuse element AF and information is erroneously written to the anti-fuse element AF.

[0040] FIG. 3 is a diagram schematically showing an example of a cross-sectional structure of a part of the substrate 11 corresponding to the capacitive element Ca and the driving element MD2 for the memory element according to the embodiment.

[0041] For example, a P-type well region 101, and N-type well regions 102a and 102b are formed on a P-type silicon substrate 100. The P-type well region 101 may be formed simultaneously in the process of forming the P-type well of the NMOS transistor MN1, and this P-type well and the P-type well region 101 have the same impurity concentration distribution. The same applies to the relationship between the N-type well regions 102a and 102b and the N-type well of the PMOS transistor MP1. When the breakdown voltage VB at the PN junction between the N-type well regions 102a and 102b and the P-type silicon substrate 100 is considered, VB > VID is set so that breakdown does not occur at the PN junction when writing information. Therefore, the N-type well regions 102a and 102b may be formed in consideration of their respective impurity concentrations.

[0042] Reference numeral 103 indicates a field oxide film having a LOCOS structure. The gate oxide film 104 is formed simultaneously with the formation of the gate insulating films of the transistors MP1 and MN1. The gate electrode 105a of the memory driving element MD2 and the electrode 105b of the capacitive element Ca used as the anti-fuse element AF are each formed of poly-silicon. These are formed simultaneously with the formation of the gate electrodes of the transistors MP1 and MN1. Similarly, the high-concentration N-type diffusion regions 106a to 106c and the high-concentration P-type diffusion region 107 are formed simultaneously with the formation of the high-concentration diffusion regions for the drains, sources, and bulks of the transistors MP1 and MN1. Reference numeral 108 indicates a contact portion, and reference numerals 109a to 109d indicate metal wirings. Note that the manufacturing method and structure of the metal wirings 109a to 109d and each electrode are not limited as long as they are electrically connected.

[0043] Next, the configuration of the high-voltage-resistant NMOS transistor will be described.

[0044] The gate electrode 105a is disposed over the adjacent P-well region 101 and N-well region 102a via the gate oxide film 104. The region where the P-well region 101 overlaps with the gate electrode 105a becomes the channel region. The high-concentration N-type diffusion region 106a is the source electrode, and the high-concentration P-type diffusion region 107 is the back gate electrode. As the drain electric field relaxation region, an N-well region 102a extending to the lower part of the gate electrode 105 is disposed. The high-concentration N-type diffusion region 106b formed in the N-well region 102a becomes the drain electrode. Further, the drain side of the gate electrode 105a has a structure that rides on the field oxide film 103 formed in the N-well region 102a, that is, a so-called LOCOS offset structure.

[0045] Thereby, even when the high-voltage withstand NMOS transistor is in the off state, that is, the voltage of the gate electrode is GND and the voltage of the drain electrode rises to the high voltage VID, the gate-drain breakdown voltage can be ensured.

[0046] Next, the structure of the anti-fuse element AF will be described.

[0047] An electrode 105b is used as the upper electrode of the anti-fuse element AF via the gate oxide film 104 over the N-well region 102b, and the high-concentration N-type diffusion region 106c is used as the lower electrode.

[0048] In FIG. 2, the high-concentration N-type diffusion region 106c is formed only in the opening of the upper electrode, but the high-concentration N-type diffusion region may be formed over the entire lower part of the upper electrode. Further, in FIG. 2, the lower electrode of the anti-fuse element AF is connected to the drain of the high-voltage withstand NMOS transistor, but the upper electrode may be connected to the drain of the high-voltage withstand NMOS transistor and the lower electrode may be connected to the high voltage VID.

[0049] Note that in FIG. 2, a capacitor formed of an N-well region and polysilicon is shown, but a capacitor using a PMOS transistor may be used.

[0050] Next, the connection state of each electrode will be described.

[0051] The metal wiring 109a is connected to the source electrode and the back gate electrode of the high breakdown voltage NMOS transistor via the contact portion 108, and a GND potential is applied. The metal wiring 109b is connected to the gate electrode of the high breakdown voltage NMOS transistor via the contact portion 108, and the output signal Vg of the inverter circuit INV shown in FIG. 1 is input. The metal wiring 109c is connected to the drain electrode of the high breakdown voltage NMOS transistor MD1 and the lower electrode of the anti-fuse element AF via the contact portion 108. The metal wiring layer 109d is connected to the upper electrode of the anti-fuse element AF via the contact portion 108, and a high voltage VID at the time of writing is applied.

[0052] Next, the operation when writing to the anti-fuse element AF will be described.

[0053] When information is to be written to the anti-fuse element AF, the output signal Sig of the NAND circuit 306 is set to the low level, thereby turning on the memory driving element MD2. As a result, a high voltage VID is applied to the gate oxide film constituting the anti-fuse element AF. Thereby, the gate oxide film is destroyed and information is written to the anti-fuse element AF. That is, before writing, the anti-fuse element AF was a capacitive element Ca, whereas after writing, it becomes a resistive element.

[0054] Methods for reading the information written in the anti-fuse element AF include measuring a change in the impedance of the anti-fuse element AF.

[0055] The information recorded in the anti-fuse element AF is product-specific information such as a chip ID and setting parameters, and these are written at the factory using an inspection machine or the like at the time of product shipment. Alternatively, when the product is mounted on the product main body and the user writes information after starting use of the product, a voltage corresponding to the high voltage VID is supplied from the product main body.

[0056] [Embodiment 1] Based on the above premises, Embodiments 1 and 2 of the present invention will be described.

[0057] FIG. 7 is a diagram showing an example of the circuit configuration of the control data supply circuit 201 according to Embodiment 1.

[0058] The control data supply circuit 201 includes the first shift register circuit 501, the second shift register circuit 502, the latch circuits 503 and 504, the data mask circuit 505, the decoder circuit 506, etc., which have been described above. On the input side of the control data supply circuit 201, logical data signals such as a clock signal CLK for transferring the data of the shift register circuits 501 and 502, a signal DATA1, a signal DATA2, a latch signal LT for inputting, and a control signal (not shown) of the recording element are input. On the output side of the control data circuit 201, signals such as a group selection signal 210, a block selection signal 211 for selecting a recording element, and a block selection signal 212 for selecting a memory element are output.

[0059] The first shift register circuit 501 is composed of a plurality of stages of registers, and the second shift register circuit 502 is composed of one register. The first shift register circuit 501 is serially connected to the second shift register circuit 502, and the signal DATA1 for inputting serial data is first input to the first shift register circuit 501 and is output from the first shift register circuit 501 and input to the second shift register circuit 502.

[0060] In addition, the output of each register of the first shift register circuit 501 is connected to each corresponding first latch circuit 503, and the first latch circuit 503 receives the outputs of the registers of the first shift register circuit 501 in parallel. Similarly, the output of the second shift register circuit 502 of the most significant bit is connected to the second latch circuit 504 via the data mask circuit 505.

[0061] Further, the decoder circuit 506 receives the outputs of some of the latch circuits of the first latch circuit 503 and the output from the second latch circuit 504. The data mask circuit 505 sends the output of the second shift register circuit 502 to the second latch circuit 504 only when the signal DATA2 is a high-level signal. Then, when the output is latched in the second latch circuit 504, the output of the second latch circuit 504 is output as the output selection signal of the decoder circuit 506. And when the output of the second latch circuit 504, that is, the output selection signal is high level, the block selection signal 212 for memory element selection is output from the decoder circuit 506.

[0062] On the other hand, when the signal DATA2 is a low-level signal, the output of the second shift register circuit 502 is not sent to the second latch circuit 504 via the data mask circuit 505. Therefore, in this case, since the output selection signal is not output to the decoder circuit 506 at a high level from the second latch circuit 504, the block selection signal 211 for recording element selection is output from the decoder circuit 506.

[0063] That is, when using the recording element for printing, regardless of whether the second shift register circuit 502 receives a signal or not, by setting the signal DATA2 to a low level, the output of the second shift register circuit 502 is masked by the data mask circuit 505. Therefore, the block selection signal 211 of the recording element is automatically output and the recording element is selected. Thus, at the time of printing, only the first shift register circuit 501 can select the recording element. Therefore, compared with the conventional example, it is possible to suppress an increase in the amount of data associated with the selection of the recording element.

[0064] In FIG. 7, one second shift register circuit 502, one data mask circuit 505, and one second latch circuit 504 are provided respectively. However, for proper use of modes such as reading and writing of memory elements, a plurality of second shift register circuits 502, data mask circuits 505, and second latch circuits 504 may be provided and used.

[0065] Figure 4 is a plan view of the recording element substrate 11 according to Embodiment 1 of the present invention.

[0066] This substrate 11 has a terminal for inputting a latch signal (LT) as an input terminal, a clock input terminal for inputting a shift clock signal (CLK), data input terminals for inputting serial data signals (DATA1, DATA3), and an input terminal for inputting a bit data signal (DATA2).

[0067] This substrate 11 includes a plurality of groups of recording element modules and a plurality of groups of memory element modules. The recording element module includes a recording element Rh, a driving element MD1 for energizing and driving the recording element, and a logical product circuit AND1 for recording element selection. The memory element module includes an anti-fuse element AF as a memory element (also shown as "capacitor element Ca" in FIG. 4), a driving element MD2 for the memory element, and a logical product circuit AND2 for memory element selection.

[0068] Furthermore, a common logic bus wiring 402 (common wiring) capable of supplying signals from the control data supply circuit 201a to the logical product circuit AND1 and the logical product circuit AND2 is mounted. The control data supply circuit 201a is the same circuit as the circuit shown in FIG. 7. In Embodiment 1, the common logic bus wiring 402 includes a group selection signal 210 output from the control data supply circuit 201 described with reference to FIG. 1, a block selection signal 211 for recording element selection, and a block selection signal 212 for memory element selection.

[0069] First, the arrangement of elements and circuits on the substrate 11 will be described.

[0070] The substrate 11 is provided with a supply port 408 for supplying ink as a recording agent that extends in the longitudinal direction of the substrate 11. Along the extending direction of the supply port 408, a recording element row 4041 configured by arranging a plurality of recording elements Rh in at least one row is provided. Further, a driving element row 4042 for recording elements configured by arranging driving elements MD1 for the recording elements corresponding to the respective recording elements Rh is provided adjacent to the recording element row 4041 on the side opposite to the side where the supply port 408 of the recording element row 4041 is provided. Furthermore, a logical product circuit row 4043 for recording element selection configured by arranging logical product circuits AND1 for recording element selection corresponding to the respective recording elements Rh is provided adjacent to the driving element row 4042. In the first embodiment, the recording element row 4041, the driving element row 4042, and the logical product circuit row 4043 extend along the Y direction shown in FIG. 4.

[0071] Similarly, the substrate 11 is provided with an anti-fuse element row 4061 (memory element row) configured by arranging a plurality of anti-fuse elements AF (capacitor elements Ca) along the direction of the recording element row 4041. This anti-fuse element row 4061 is provided near the edge of the substrate 11. Further, a resistor element row 4064 configured by arranging resistor elements Rp corresponding to the respective anti-fuse elements AF is provided adjacent to the anti-fuse element row 4061. Furthermore, a driving element row 4062 for memory elements configured by arranging driving elements MD2 for the memory elements corresponding to the respective anti-fuse elements AF is provided adjacent to the resistor element row 4064. Further, a logic circuit row 4063 configured by arranging logic circuits AND2 for memory element selection corresponding to the respective anti-fuse elements AF is provided adjacent to the driving element row 4062.

[0072] Also, the above-described common logic bus wiring 402 is provided between a discharge module row 704 including a recording element row 4041 and rows of elements and circuits for recording elements, and a memory module row 706 including a memory element row and rows of elements and circuits for memory elements. In Embodiment 1, the common logic bus wiring 402 extends along the direction of the recording element row 4041. Also, the logic circuit row 4043 for recording elements and the logic circuit row 4063 for memory elements extend along the extending direction of the common logic bus wiring 402. In other words, the common logic bus wiring 402, the logic circuit row 4043 for recording elements, and the logic circuit row 4063 for memory element rows extend along the Y direction in FIG. 4. Also, the logic circuit row 4063 for memory element rows, the common logic bus wiring 402, and the logic circuit row 4043 for recording element rows are arranged side by side in the X direction from the left side in FIG. 4 in this order. Further, the control data supply circuit 201(201a) is arranged at an end portion of the substrate 11 in the Y direction.

[0073] Also, on each of both sides (X direction) of the supply port 408 on the substrate 11, a recording element row 4041, a driving element row 4042, and a logic circuit row 4043 are provided. The anti-fuse element row 4061 is provided in one row on one side of the supply port 408. Therefore, one of the two provided recording element rows 4041 (the left side in FIG. 4) also serves as the anti-fuse element row 4061 and the common logic bus wiring 402.

[0074] On the other hand, the other recording element row 4041 (the right side in FIG. 4) is connected to the control data supply circuit 201b via a logic bus wiring 403 dedicated to the recording element row. This logic bus wiring 403 dedicated to the recording element row includes a group selection signal 210 and a block selection signal 211 for recording element selection. Note that a configuration in which the recording element row 4041, the driving element row 4042, and the logic circuit row 4043 are provided only on one side of the supply port 408 may be employed.

[0075] FIG. 8 is a diagram showing an example of the circuit configuration of the control data supply circuit 201b according to Embodiment 1.

[0076] In the control data supply circuit 201b, the signal DATA2 and the mask circuit 505 in FIG. 7 are omitted, and the decoder circuit 506 outputs only the block selection signal 211 for recording element selection.

[0077] The configurations of the control data supply circuits 201a and 201b according to the first embodiment are as described above with reference to FIGS. 7 and 8. Here, the operation of the circuits will be mainly described.

[0078] In the example of FIG. 7, the decoder circuit 506 operates as a multiplexer that inputs and decodes a multi-bit signal, here a 4-bit signal, and outputs 16 selection signals. When the output of the second latch circuit 504 is at a low level, the selection signal 211 for selecting a group of recording elements is output, and when the output of the second latch circuit 504 is at a high level, the selection signal 212 for selecting a group of memory elements is output. In the example of FIG. 7, there are 5 blocks each for the recording elements and the memory elements, and each block contains 16 elements.

[0079] Also, in FIG. 8, the second latch circuit 504, the data mask circuit 505, the second shift register circuit 502, the block selection signal 212 for memory element selection, and the signal DATA2 in FIG. 7 do not exist.

[0080] FIG. 10(A) is a flowchart for explaining the process of controlling the control data supply circuit 201a when the recording apparatus 1000 according to the first embodiment performs a recording process for one line. The process shown in this flowchart is achieved by the CPU 901 reading and executing a program stored in the ROM 903. Since the process of controlling the control data supply circuit 201b is the same as the conventional process, its description is omitted.

[0081] First, at S1001, the CPU 901 sets DATA2 to a low level. Next, it proceeds to S1002 where the CPU 901 outputs a 10-bit serial signal to DATA1 in synchronization with the CLK signal. Then, at S1003, it outputs a latch signal LT to latch the 10-bit data set in the first shift register circuit 501 into the first latch circuit 503. However, at this time, since DATA2 is at a low level, the data of the second shift register circuit 502 is not latched into the second latch circuit 504. At this time, one group of recording elements is selected with the upper 2 to 6 bits, and a block of recording elements included in the group selected by the upper bits is selected with the lower 7 to 10 bits. As a result, the recording elements to be driven in the recording operation are determined. Then, at S1004, it outputs the image data to be printed at that time. Then, it proceeds to S1005 where the CPU 901 outputs a recording element control (heat enable (HE)) signal for driving the recording elements to the recording head 20. As a result, in one drive of the recording elements, the number of recording elements corresponding to the maximum number of groups is driven simultaneously. Then, it proceeds to S1006 where it determines, for example, whether the output of the image data for one line has ended. If not, it returns to S1002 to execute the above-described processing.

[0082] FIG. 10(B) is a flowchart for explaining the process of controlling the control data supply circuit 201a when the recording apparatus 1000 according to Embodiment 1 performs access processing to the memory module. Note that the process shown in this flowchart is achieved by the CPU 901 reading and executing a program stored in the ROM 903. Note that in the case of access processing to the memory module, the control data supply circuit 201b is not used.

[0083] First, at S1011, the CPU 901 sets DATA2 to a high level. Next, proceeding to S1011, the CPU 901 outputs a 10-bit serial signal to DATA1 in synchronization with the CLK signal. However, in this case, the leading bit of the 10-bit serial signal is set to a high level. Then, at S1012, the latch signal LT is output to latch the 10-bit data set in the first shift register circuit 501 into the first latch circuit 503. However, at this time, since DATA2 is at a high level, the high-level data ("1") of the second shift register circuit 502 is latched into the second latch circuit 504. At this time, one group of memory elements is selected by the upper 2 to 6 bits, and a block of memory elements included in the group selected by the upper bits is selected by the lower 7 to 10 bits. As a result, the memory elements to be read or written to are determined. Then, at S1013, by outputting a memory control signal, data can be written to or read from the memory element. Then, proceeding to S1005, the CPU 901 determines whether the writing or reading of data to / from the memory element has ended. If it is determined that the process has ended, this process is terminated. If it is determined that the process has not ended, the process returns to S1011 to execute the above-described process.

[0084] In Embodiment 1, for example, there are 5 blocks of memory elements, and each block contains 16 memory elements. Therefore, when accessing the memory element, the CPU 901 of the recording apparatus 1000 sets DATA2 to a high level and outputs a 10-bit serial signal with the leading bit being "1" to DATA1 in synchronization with the CLK signal. Then, the latch signal LT is output to latch the 10-bit data set in the first shift register circuit 501 into the first latch circuit 503. However, at this time, since DATA2 is at a high level, the data of the second shift register circuit 502 is latched into the second latch circuit 504. At this time, one group of memory elements is selected by the upper 2 to 6 bits, and a block of memory elements included in the group selected by the upper bits is selected by the lower 7 to 10 bits.

[0085] As described above, according to Embodiment 1, when using a recording element for printing, the output of the second shift register circuit 502 is masked by the signal DATA2 and not sent to the decoder circuit. Therefore, when the signal DATA2 is at a low level, the decoder circuit always outputs a selection signal for selecting the block of the recording element. Accordingly, compared with the conventional example, there is an effect that the number of bits of the signal for selecting the recording element can be reduced.

[0086] [Embodiment 2] FIG. 5 is a plan view of a recording element substrate 11 according to Embodiment 2 of the present invention.

[0087] In the recording element substrate of FIG. 4 according to the above-described Embodiment 1, the signal DATA2 for image data was used in the control data supply circuit 201a.

[0088] In contrast, in Embodiment 2, the signal DATA4 for image data used in the control data supply circuit 201b is supplied to the control data supply circuit 201a as the aforementioned DATA2. As a result, in the substrate 11 according to this Embodiment 2, the output of the selection signal of the block of the recording element is prohibited (masked) from the control data supply circuit 201a by only one signal DATA4.

[0089] As described above, according to Embodiment 2, by changing the number of signal lines input to the element substrate from two to one, that is, using only the signal DATA4 instead of the signal DATA3 and the signal DATA2 in FIG. 4, the number of electrode pads on the substrate can be reduced. Alternatively, the remaining electrode pads can be used for other purposes.

[0090] (Other Embodiments) The present invention can also be realized by supplying a program that realizes one or more functions of the above-described embodiments to a system or device via a network or a storage medium, and causing one or more processors in a computer of the system or device to read and execute the program. Further, it can also be realized by a circuit (for example, ASIC) that realizes one or more functions.

[0091] The present invention is not limited to the above-described embodiments, and various changes and modifications can be made without departing from the spirit and scope of the present invention. Therefore, in order to publicize the scope of the present invention, the following claims are appended.

Explanation of Signs

[0092] 201... Control data supply circuit, 210... Group selection signal, 211... Block selection signal for recording element selection, 212... Block selection signal for memory element selection, 501... First shift register circuit, 502... Second shift register circuit

Claims

1. A plurality of recording elements; a recording element driving element for driving the recording element; a logical AND circuit for selecting the recording element to be driven by the recording element drive element; A plurality of memory elements; A memory element driving element for driving the memory element; a memory element selection AND circuit for selecting the memory element to be driven by the memory element drive element; A control data supply circuit; In an element substrate having The control data supply circuit includes: A multi-stage shift register for holding a serial data signal; a decoder circuit for outputting a selection signal for selecting either the recording element or the memory element; a mask circuit connected to the decoder circuit; The mask circuit includes: The element substrate outputs a high-level or low-level signal to the decoder circuit based on a bit data signal for switching memory elements input to the mask circuit.

2. 2. The element substrate according to claim 1, further comprising a latch circuit that latches the serial data held in the shift register.

3. 3. The element substrate according to claim 2, characterized in that the group of recording elements or memory elements is selected by a portion of the output of the latch circuit, and a selection signal for selecting a block of the recording elements or memory elements is a 1-bit signal obtained by decoded a portion of the remaining output of the latch circuit by the decoder circuit.

4. 3. The element substrate according to claim 1, wherein the bit data signal is a 1-bit data signal inputted via a data input terminal.

5. 5. The element substrate according to claim 1, further comprising a clock input terminal for inputting a shift clock signal which inputs the serial data signal to the shift register.

6. 3. The element substrate according to claim 2, further comprising a latch signal input terminal for inputting a latch signal for latching the serial data in the latch circuit.

7. 2. The element substrate according to claim 1, wherein when the mask circuit masks the leading bit data of the shift register, the decoder circuit outputs a selection signal for selecting a block of the recording elements.

8. 8. The element substrate according to claim 1, wherein the decoder circuit includes a multiplexer that receives a multi-bit data signal, decodes the multi-bit data signal, and outputs a 1-bit selection signal for each of the multiple-bit data signals.

9. The element substrate according to any one of claims 1 to 8, characterized in that the recording element includes an electro-thermal conversion element that generates heat when current is applied thereto, a first transistor that energizes the electro-thermal conversion element, and a logic circuit that receives a block selection signal for the recording element, a group selection signal for the recording element, and a control signal for the recording element to control the driving of the first transistor.

10. 10. The element substrate according to claim 1, wherein the memory element includes an anti-fuse element that writes or reads information by passing current through it, a second transistor that passes current through the anti-fuse element, and a logic circuit that inputs a block selection signal for the memory element, a group selection signal for the memory element, and a control signal for the memory element to control the driving of the second transistor.

11. A liquid ejection head comprising the element substrate according to claim 1 .

12. A recording apparatus for performing recording using the liquid ejection head according to claim 11.

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