Plasma processing apparatus and plasma processing method

Abstract

To provide a plasma processing apparatus and a plasma processing method that are capable of controlling the impedance of a counter electrode so as to be capable of following the frequency of a high frequency wave.SOLUTION: A plasma processing apparatus includes a processing vessel, an application electrode, a counter electrode, and a phase control circuit. The processing vessel is configured to form a processing space. The application electrode is configured to be provided on one side of the processing space, and is connected to a high-frequency power source. The counter electrode is configured to be provided on the other side of the processing space. The phase control circuit is configured to include a semiconductor switch, and is connected to the counter electrode. The semiconductor switch receives, as a control signal, an on-signal shorter than one cycle of the high-frequency wave in synchronization with a frequency of high frequency output from the high-frequency power source.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a plasma processing apparatus and a plasma processing method.

Background Art

[0002] The plasma processing apparatus disclosed in Patent Document 1 includes a chamber, an upper electrode, a gas supply unit, a high-frequency power source, a first measuring instrument, a second measuring instrument, a detector, an impedance adjusting device, and a control device. The lower electrode may be included in a substrate support portion configured to be provided in the chamber and on which a substrate is placed. The upper electrode may be provided in the chamber and arranged to face the lower electrode. The gas supply unit may be configured to supply a processing gas between the upper electrode and the lower electrode. The high-frequency power source may be electrically connected to the upper electrode and configured to generate plasma of the processing gas by applying a high-frequency voltage to the upper electrode. The first measuring instrument may be configured to measure the potential waveform of the upper electrode. The second measuring instrument may be configured to measure the potential waveform of the lower electrode. The detector may be configured to detect a voltage waveform obtained by subtracting the second potential measured by the second measuring instrument from the first potential waveform measured by the first measuring instrument. The impedance adjusting device may be configured to adjust the impedance of the lower electrode. The control device may be configured to control the impedance adjusting device to adjust the impedance of the lower electrode based on the voltage waveform detected by the detector.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The present disclosure provides a plasma processing apparatus and a plasma processing method capable of controlling the impedance of a counter electrode so as to follow a high-frequency.

Means for Solving the Problems

[0005] The plasma processing apparatus according to one aspect of the present disclosure includes a processing container, an application electrode, a counter electrode, and a phase control circuit. The processing container is configured to form a processing space. The application electrode is configured to be provided on one side of the processing space and is connected to a high-frequency power source. The counter electrode is configured to be provided on the other side of the processing space. The phase control circuit is configured to include a semiconductor switch and is connected to the counter electrode. The semiconductor switch receives, as a control signal, a turn-on signal that is synchronized with the frequency of the high-frequency output from the high-frequency power source and is shorter than one cycle of the high-frequency.

Effects of the Invention

[0006] According to the present disclosure, the impedance of the counter electrode can be controlled so as to follow the high-frequency.

Brief Description of the Drawings

[0007]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

[0008] Hereinafter, embodiments of the disclosed plasma processing apparatus and plasma processing method will be described in detail with reference to the drawings. Note that the disclosed technology is not limited by the following embodiments.

[0009] In a plasma processing apparatus that generates capacitively coupled plasma (CCP), for example, it is known to provide a phase controller on the lower electrode and control the plasma distribution by varying the impedance seen from the upper electrode. In such a phase controller, for example, a vacuum varactor is varied by a mechanical drive system to vary the impedance in about less than 1 second to about several seconds. On the other hand, in atomic layer process (ALP), plasma ignition may be performed by switching the gas species or stepwise switching the high-frequency power at intervals of about several seconds during the process recipe. Therefore, it is difficult for a mechanical phase controller to perform impedance control following the process recipe. Thus, it is expected to control the impedance of the counter electrode to follow the high-frequency frequency.

[0010] [Configuration of Plasma Processing Apparatus] FIG. 1 is a schematic cross-sectional view showing an example of the configuration of a plasma processing apparatus according to an embodiment of the present disclosure. The plasma processing apparatus 1 shown in FIG. 1 includes a control unit 2 and a chamber 10. The chamber 10 provides an internal space therein. The chamber 10 may include a chamber body 12. The chamber body 12 has a substantially cylindrical shape. The internal space (processing space 10s) of the chamber 10 is provided inside the chamber body 12. The chamber body 12 is formed of a metal such as aluminum. The chamber body 12 is electrically grounded. Note that the side wall of the chamber body 12 may provide a passage through which the substrate W passes when being transported. Further, a gate valve may be provided along the side wall of the chamber body 12 to open and close this passage.

[0011] The plasma processing apparatus 1 further includes a substrate support unit 14. The substrate support unit 14 is installed inside the chamber 10. The substrate support unit 14 is configured to support the substrate W placed thereon. The substrate support unit 14 has a main body. The main body of the substrate support unit 14 is formed of, for example, aluminum nitride and may have a disk shape. The substrate support unit 14 may be supported by a support member 16. The support member 16 extends upward from the bottom of the chamber 10. The substrate support unit 14 includes a lower electrode 18. The lower electrode 18 is included in the substrate support unit 14 and is embedded in the main body of the substrate support unit 14. Note that the lower electrode 18 is an example of a counter electrode.

[0012] The plasma processing apparatus 1 further includes an upper electrode 20. The upper electrode 20 is provided in the chamber 10 and above the substrate support unit 14. The upper electrode 20 is arranged to face the lower electrode 18. The upper electrode 20 constitutes the top portion of the chamber 10. The upper electrode 20 is electrically separated from the chamber body 12. In one embodiment, the upper electrode 20 is fixed to the upper portion of the chamber body 12 via an insulating member 21. Note that the upper electrode 20 is an example of an application electrode.

[0013] In one embodiment, the upper electrode 20 is configured as a showerhead. The upper electrode 20 provides a gas diffusion space 20d inside thereof. Further, the upper electrode 20 further provides a plurality of gas holes 20h. The plurality of gas holes 20h extend downward from the gas diffusion space 20d and open toward the internal space of the chamber 10. That is, the plurality of gas holes 20h connect the gas diffusion space 20d and the internal space (processing space 10s) of the chamber 10.

[0014] The plasma processing apparatus 1 further includes a gas supply unit 22. The gas supply unit 22 is configured to supply gas into the chamber 10. The gas supply unit 22 is configured to supply a processing gas between the upper electrode 20 and the lower electrode 18. The gas supply unit 22 is connected to the gas diffusion space 20d via a pipe 23. The gas supply unit 22 may have one or more gas sources, one or more flow controllers, and one or more on-off valves. Each of the one or more gas sources is connected to the pipe 23 via a corresponding flow controller and a corresponding on-off valve.

[0015] In one embodiment, the gas supply unit 22 may supply a film-forming gas. That is, the plasma processing apparatus 1 may be a film-forming apparatus. The film formed on the substrate W using the film-forming gas may be an insulating film. In another embodiment, the gas supply unit 22 may supply an etching gas. That is, the plasma processing apparatus 1 may be a plasma etching apparatus.

[0016] The plasma processing apparatus 1 further includes an exhaust device 24. The exhaust device 24 includes a pressure controller such as an automatic pressure control valve and a vacuum pump such as a turbo molecular pump or a dry pump. The exhaust device 24 is connected to the internal space of the chamber 10 via an exhaust pipe from an exhaust port 12e provided at the bottom of the chamber body 12.

[0017] The plasma processing apparatus 1 further includes a high-frequency power supply 26. The high-frequency power supply 26 is electrically connected to the upper electrode 20 via a matcher 28. The high-frequency power supply 26 may be configured to include the matcher 28. The high-frequency power supply 26 is configured to generate plasma of a processing gas supplied between the upper electrode 20 and the lower electrode 18 from the gas supply unit 22 by applying a high-frequency voltage to the upper electrode 20. In one embodiment, the high-frequency power supply 26 generates high-frequency power. The frequency of the high-frequency power may be any frequency. The frequency of the high-frequency power may be, for example, 13.56 MHz or less. The frequency of the high-frequency power may be, for example, 2 MHz or less. The frequency of the high-frequency power may be, for example, 20 kHz or more. Note that when the high-frequency power is a high-frequency signal for generating plasma, it can also be referred to as a source RF (Radio Frequency) signal or source RF power.

[0018] The high-frequency power supply 26 is connected to the upper electrode 20 via the matcher 28. The high-frequency power from the high-frequency power supply 26 is supplied to the upper electrode 20 via the matcher 28. The matcher 28 has a matching circuit that matches the impedance of the load of the high-frequency power supply 26 to the output impedance of the high-frequency power supply 26. In addition to the high-frequency power, a bias signal for generating a bias potential on the substrate W may be supplied to the upper electrode 20. The bias signal may be a high-frequency signal, a pulse of a DC voltage, or a DC voltage (DC). When a DC voltage is supplied to the upper electrode 20, a DC power supply may be included. Note that when the bias signal is a high-frequency signal, it can also be referred to as a bias RF signal or bias RF power.

[0019] In another embodiment, it may be configured to periodically apply a pulse of a DC voltage to the upper electrode 20. The frequency defining the period during which the pulse of the DC voltage is applied to the upper electrode 20 is, for example, 10 kHz or more and 10 MHz or less.

[0020] When plasma processing is performed on the substrate W in the plasma processing apparatus 1, the processing gas is supplied from the gas supply unit 22 into the chamber 10. Then, high-frequency power and DC voltage pulses from the high-frequency power supply 26 are applied to the upper electrode 20. As a result, plasma is generated from the processing gas in the chamber 10. The substrate W on the substrate support unit 14 is processed by chemical species from the generated plasma. For example, chemical species from the plasma form a film on the substrate W. Alternatively, chemical species from the plasma etch the substrate W.

[0021] The plasma processing apparatus 1 further includes a phase control circuit 40. The phase control circuit 40 includes a semiconductor switch and is connected to the lower electrode 18. The phase control circuit 40 is configured to adjust the impedance of the lower electrode 18.

[0022] Here, with reference to FIGS. 2 and 3, the details of the phase control circuit 40 will be described. FIG. 2 is a diagram showing an example of the phase control circuit in the present embodiment. FIG. 3 is a diagram showing an example of the phase control circuit including a signal source. As shown in FIGS. 2 and 3, the phase control circuit 40 includes a FET (Field Effect Transistor) 41, a detector 42, and a generator 43. In the circuit of FIG. 3, a capacitor C1 connected between the lower electrode 18 and the drain of the FET 41 for DC cut, and a capacitor C2 connected in parallel with the FET 41 are also shown. That is, the phase control circuit 40 may include the capacitors C1 and C2. The capacitors C1 and C2 are examples of capacitive elements. Note that the capacitor C2 may be omitted. Also, in FIGS. 2 and 3, the high-frequency current I flowing from the lower electrode 18 side to the FET 41 in , the voltage V between the drain and source of the FET 41 d , and the combined capacitance C of the FET 41 and the capacitor C2 EFF are illustrated. Also, in FIG. 2, the gate voltage V of the FET 41 g is illustrated, and in FIG. 3, the voltage V of the signal source corresponding to the voltage measured at the lower electrode 18 in is illustrated. In the present embodiment, the combined capacitance C EFF becomes the variable target capacitance.

[0023] FET41 is an example of a semiconductor switch and is connected between the lower electrode 18 and the ground. As a variable reactance capable of high-speed response, FET41 is used in place of a conventional mechanically driven vacuum tube. When an on signal 44 is input as a control signal from the generation unit 43 to the gate of FET41, the drain-source becomes conductive. That is, when FET41 is conductive, the voltage V d between the drain and the source becomes 0 [V]. Note that FET41 is, for example, an N-channel type FET, with the drain connected to the lower electrode 18 side and the source connected to the ground side. Also, a P-channel type FET may be used for FET41. In that case, the direction of the parasitic diode in the equivalent circuit described later is reversed, and the direction of the current flowing into the FET is also reversed.

[0024] The detector 42 is provided between the lower electrode 18 on the high-frequency power supply 26 side and FET41. In the circuit of FIG. 3, the detector 42 will be provided between the capacitor C1 and the drain of FET41. The detector 42 detects the high-frequency current I in flowing from the lower electrode 18 side to FET41. Note that the high-frequency current I in is the high-frequency current flowing from the high-frequency power supply 26 through the matcher 28, the processing space 10s, the lower electrode 18, and the capacitor C1 to FET41. The detector 42 can use, for example, a directional coupler, a VI probe, etc. The detector 42 outputs the information on the detected current to the generation unit 43. The information on the detected current is, for example, the waveform information of the high-frequency current I in . Note that instead of the high-frequency current I in , the high-frequency voltage at the drain terminal of FET41 may be detected by a detector and used as the information detected instead of the current.

[0025] The generation unit 43 generates an on-signal 44, which is a control signal for the FET 41, based on the current information input from the detector 42. Note that the on-signal 44 is an example of the gate signal of the FET 41. Further, process timing information 45 is input from the control unit 2 to the generation unit 43. The process timing information 45 includes, as processing conditions, for example, the gas type and flow rate of the processing gas supplied to the processing space 10s, the high-frequency signal supplied by the high-frequency power supply 26, and the pressure and temperature in the chamber 10. The generation unit 43 may generate the on-signal 44, which is a control signal for the FET 41, based on the current information input from the detector 42 and the process timing information 45. That is, the generation unit 43 may change the period of the on-signal 44 in one cycle of the current input from the detector 42 according to the processing conditions.

[0026] That is, the generation unit 43 may generate the on-signal 44 based on the current information input from the detector 42 and the switching of the gas type of the processing gas supplied to the processing space 10s. Note that the generation unit 43 may change the period of the on-signal 44 in one cycle of the current input from the detector 42 according to the gas type of the processing gas. Further, the generation unit 43 may generate the on-signal 44 based on the current information input from the detector 42 and the switching of the flow rate of the processing gas supplied to the processing space 10s. Note that the generation unit 43 may change the period of the on-signal 44 in one cycle of the current input from the detector 42 according to the flow rate of the processing gas. Further, when the current information input from the detector 42 is a pulse waveform having a specific pulse width, the generation unit 43 may generate the on-signal 44 based on the pulse waveform. Note that the generation unit 43 may change the period of the on-signal 44 in one cycle of the current input from the detector 42 according to the pulse waveform. Further, the generation unit 43 may generate the on-signal 44 based on the current information input from the detector 42 and the bias signal supplied to the upper electrode 20. Note that the generation unit 43 may change the period of the on-signal 44 in one cycle of the current input from the detector 42 according to the bias signal.

[0027] The on-signal 44 is, for example, a high frequency output from the high-frequency power supply 26, that is, the high-frequency current I detected by the detector 42 in synchronized with the frequency of the high-frequency current I in and is generated as a signal shorter than one cycle of the high-frequency current I in . For example, when the high-frequency current I

[0028] is a sine wave, the on-signal 44 outputs a signal shorter than one cycle of the sine wave for each cycle of the sine wave. Also, the phase control circuit 40 may include an inductive element such as a coil at one or more positions between the lower electrode 18 and the detector 42 and between the source and ground of the FET 41. That is, the phase control circuit 40 may include an inductive element such as a coil at one or more positions on the high-frequency power supply 26 side from the detector 42 and on the ground side from the FET 41. That is, since the phase control circuit 40 does not include an inductive element between the detector 42 and the source of the FET 41, the influence of the inductive element can be excluded in the generation of the on-signal 44. In addition, in the case of the inductive element in this case, the parasitic inductance such as wiring between the detector 42 and the source of the FET 41 is not included because the influence is minor.

[0029] [Conduction angle α of FET] Next, with reference to FIGS. 4 to 7, the conduction between the drain and source of the FET 41 will be described in terms of the conduction angle α represented by the angle in one cycle of the high-frequency current I in . FIG. 4 is a diagram showing an example of an equivalent circuit of the FET. The equivalent circuit 41a of the FET 41 shown in FIG. 4 is represented as a parallel circuit of a switch SW, a capacitor C3, and a diode D (parasitic diode). In the equivalent circuit 41a, when the high-frequency current I in is applied from the sine-wave current source 46, the voltage across both ends of the equivalent circuit 41a becomes the drain-source voltage V d .

[0030] In the FET 41, to reduce switching losses, the drain-source voltage V dWhen there is no diode D, it is desired to perform zero-voltage switching that switches on / off at the timing of 0 [V]. For this reason, in the present embodiment, the use of either the positive or negative half-wave region within one cycle of the sine wave waveform of the voltage V d is considered. In the equivalent circuit 41a, when using the positive half-wave region of the sine wave, since the switch SW conducts in the negative half-wave region, the positive half-wave region of the sine wave of the current source 46 appears as the voltage V d . However, when using the negative half-wave region of the sine wave, the switch SW conducts in the positive half-wave region, and also the drain-source becomes conductive due to the diode D in the negative half-wave region, so the negative half-wave region of the sine wave of the current source 46 does not appear as the voltage V d . Therefore, in the equivalent circuit 41a, the positive half-wave can be generated as the voltage V d , but it is difficult to generate the negative half-wave. For this reason, in the present embodiment, the positive region within one cycle of the sine wave waveform of the voltage V d is used.

[0031] FIG. 5 is a diagram showing an example of the relationship between the conduction angle of the on-signal and the voltage waveform between the drain and source of the FET. As shown in FIG. 5, when taking the graph 50 of the high-frequency current I in as a reference, the voltage V d is delayed by 90 degrees in phase. In FIG. 5, as the voltage corresponding to the voltage V d , when the switch SW is off, the graph 51 of the voltage V EFF charged with respect to the combined capacitor C dx is shown. That is, the voltage V dx becomes a positive value obtained by integrating the high-frequency current I in . Also, the corresponding conduction angle α is shown on the right vertical axis of the graph 51. In FIG. 5, the zero-crossing point when the waveform of the graph 50 of the high-frequency current I in changes from the negative side to the positive side, that is, the peak on the 0 [V] side of the graph 51 of the voltage V dx is taken as the reference point for the period of the on-signal 44.

[0032] Gate voltage V gAs shown in the graph 52, during the period of the on signal 44, the high-frequency current I in In other words, when the conduction angle α is 0 degrees, the switch SW is off for one period, and when the conduction angle is 180 degrees, the switch SW is on for one period. In the example of FIG. 5, the gate voltage V g Graph 52 switches on / off at the timing when the conduction angle α=90 degrees, which corresponds to the half wave on the 0 [V] side of graph 51.

[0033] Voltage V d Graph 53 shows the voltage V dx Of the graphs in the figure, the gate voltage V g In the section where the gate voltage V is on, that is, the section corresponding to twice the conduction angle α, the drain-source is conductive, so the gate voltage V is 0 [V]. g During the off period, the voltage V dx The voltage corresponding to the graph 51 of the voltage V d Graph 53 shows the voltage V dx The waveform corresponds to the positive half wave of

[0034] FIG. 6 is a diagram showing an example of a change in the drain-source voltage waveform of an FET when the conduction angle of an ON signal is changed. In FIG. 6, the high-frequency current I in Graph 60 and voltage V dx For the graph 61, the gate voltage V g and voltage V d Graphs 62 to 67 are shown.

[0035] In the graphs 62 and 63, the conduction angle α is 90 degrees, so like the graphs 52 and 53 in FIG. 5, the high-frequency current I in The voltage V corresponding to half a period of d In graphs 64 and 65, the conduction angle α is 135 degrees, so the high frequency current I in In one period, the gate voltage V gThe on-period becomes longer than the off-period, and the period during which the drain-source is conducting becomes longer. Therefore, when the conduction angle α is 135 degrees, as shown in graph 65, the period during which voltage V d appears is shorter than when the conduction angle α is 90 degrees, and the peak of voltage V d also becomes lower. Graphs 66 and 67 show that since the conduction angle α is 45 degrees, in one cycle of the high-frequency current I in , the on-period of the gate voltage V g becomes shorter than the off-period, and the period during which the drain-source is conducting becomes shorter. Therefore, when the conduction angle α is 45 degrees, as shown in graph 67, the period during which voltage V d appears is longer than when the conduction angle α is 90 degrees, and the peak of voltage V d also becomes higher. Note that as shown in graphs 63, 65, and 67, voltage V d becomes 0 [V] at the on / off switching, so zero voltage switching is achieved.

[0036] Figure 7 is a graph showing an example of the relationship between the conduction angle of the on-signal and the capacitance component of the lower electrode. Graph 70 shown in Figure 7 shows the conduction angle α [degrees] on the horizontal axis and the ratio of the combined capacitance C EFF to the combined capacitance C0 of the parasitic capacitance (capacitor C3) of FET41 and capacitor C2 when FET41 is off on the vertical axis. Here, in graph 70, the triangle marks indicate the measured values, and graph 71 indicates the values of the theoretical formula. Here, the theoretical formula for the ratio of the combined capacitance C EFF to the combined capacitance C0 is given by the following formula (1). The measured values are obtained from the following formula (2).

[0037]

Equation

Equation

[0038] In formula (1), when the conduction angle α is 0 degrees, the combined capacitance C EFF = the combined capacitance C0. By increasing the conduction angle α from 0 degrees, the combined capacitance CEFF The value increases. That is, in this embodiment, by controlling the conduction angle α, the capacitance component between the drain and source of the FET 41 can be continuously (smoothly) controlled. That is, the phase control circuit 40 controls the gate voltage V in by the on-signal 44 having a predetermined conduction angle α generated based on the information of the high-frequency current I detected by the detector 42, g so that the impedance of the lower electrode 18 can be controlled to follow the high-frequency frequency.

[0039] Returning to the description of FIG. 1. The control unit 2 processes computer-executable instructions for causing the plasma processing apparatus 1 to execute various processes described in the present disclosure. The control unit 2 may be configured to control each element of the plasma processing apparatus 1 so as to execute the various processes described herein. In one embodiment, part or all of the control unit 2 may be included in the plasma processing apparatus 1. The control unit 2 may include a processing unit 2a1, a storage unit 2a2, and a communication interface 2a3. The control unit 2 is realized by, for example, a computer 2a. The processing unit 2a1 may be configured to read a program from the storage unit 2a2 and perform various control operations by executing the read program. This program may be stored in the storage unit 2a2 in advance, or may be acquired via a medium when necessary. The acquired program is stored in the storage unit 2a2 and read from the storage unit 2a2 by the processing unit 2a1 and executed. The medium may be various storage media readable by the computer 2a, or may be a communication line connected to the communication interface 2a3. The processing unit 2a1 may be a CPU (Central Processing Unit). The storage unit 2a2 may include a RAM (Random Access Memory), a ROM (Read Only Memory), an HDD (Hard Disk Drive), an SSD (Solid State Drive), or a combination thereof. The communication interface 2a3 may communicate with the plasma processing apparatus 1 via a communication line such as a LAN (Local Area Network).

[0040] The control unit 2 is capable of performing predetermined control according to the selected process recipe. For example, the control unit 2 controls each part of the plasma processing apparatus 1 so as to perform the plasma processing method described later. To give a detailed example, the control unit 2 executes a process of loading and preparing the substrate W into the chamber 10. The control unit 2 supplies a processing gas into the chamber 10 to generate plasma, and executes a process of plasma-processing the substrate W using the generated plasma. Here, the plasma processing may be, for example, a film formation process, an etching process, or other processes. Further, when plasma processing is performed on the substrate W to be processed in the processing space 10s in the chamber 10, the control unit 2 outputs process timing information to the phase control circuit 40 according to the process recipe in the plasma processing. Note that the control unit 2 may output other control information to the phase control circuit 40.

[0041] [Plasma Processing Method] Next, the plasma processing according to the present embodiment will be described as a plasma processing method. FIG. 8 is a flowchart showing an example of the plasma processing in the present embodiment.

[0042] The control unit 2 controls a gate valve (not shown) to open a loading / unloading port (not shown). When the loading / unloading port is open, the substrate W is loaded into the processing space 10s of the chamber 10 through the loading / unloading port and placed on the substrate support portion 14. That is, the control unit 2 controls the plasma processing apparatus 1 to load the substrate W into the chamber 10 (step S1). Note that the control unit 2 may be a control device for the entire substrate processing system (not shown) including the plasma processing apparatus 1 and a transfer device in a transfer chamber (not shown) adjacent to the chamber 10. The control unit 2 controls the gate valve to close the loading / unloading port.

[0043] The control unit 2 controls the exhaust device 24 connected to the exhaust port 12e to reduce the pressure in the chamber 10 to a predetermined pressure. The control unit 2 controls the gas supply unit 22 to supply a plasma generation gas from the plurality of gas holes 20h to the chamber 10. The control unit 2 controls the high-frequency power supply 26 to ignite plasma with a predetermined power. The control unit 2 executes a plasma processing step of performing plasma processing on the substrate W using the plasma of the plasma generation gas for a predetermined time (step S2).

[0044] During the plasma processing step, when plasma processing is performed on the substrate W, the control unit 2 outputs process timing information to the phase control circuit 40 according to the process recipe in the plasma processing. That is, the control unit 2 outputs control information to adjust the period of the on-signal 44 of the FET 41 with respect to the phase control circuit 40 according to the processing conditions of the plasma processing.

[0045] For example, the control unit 2 controls the phase control circuit 40 so that the impedance of the lower electrode 18 draws in the high-frequency current I in Thus, the overall plasma density can be increased on the substrate W. Also, for example, the control unit 2 controls the phase control circuit 40 so that the impedance of the lower electrode 18 does not draw in the high-frequency current I in Thereby, the plasma density in the peripheral portion of the substrate W can be increased on the substrate W. Further, for example, the control unit 2 controls the phase control circuit 40 so that the impedance of the lower electrode 18 draws in the harmonic current generated in the processing space 10s of the chamber 10. Thereby, the plasma density at the center of the substrate W can be increased on the substrate W. That is, the control unit 2 can control the in-plane distribution of the plasma by adjusting the reactance with the phase control circuit 40 to control the impedance of the lower electrode 18.

[0046] When the plasma processing step is completed, the control unit 2 stops the high-frequency signal to stop the generation of plasma. Further, the control unit 2 controls the gate valve to open the carry-in / outlet. The control unit 2 controls the plasma processing apparatus 1 so that the substrate support pins (not shown) protrude from the upper surface of the substrate support unit 14 to lift the substrate W. When the carry-in / outlet is open, the substrate W is carried out of the chamber 10 by an arm (not shown) in a transfer chamber via the carry-in / outlet. That is, the control unit 2 controls the plasma processing apparatus 1 to carry out the substrate W from the chamber 10 (step S3). In this way, the control unit 2 can control the impedance of the lower electrode 18 by adjusting the reactance with the phase control circuit 40 even during plasma processing.

[0047] [Application Example] Subsequently, with reference to FIG. 9, an application example of the present embodiment will be described. FIG. 9 is a graph showing an example in the case where the conduction angle of the on-signal is changed according to the gas species and the high-frequency power. The graph 72 shown in FIG. 9 is a case where, for example, when switching the gas species such as ALP and the high-frequency power, the conduction angle α of the on-signal 44 is synchronously changed to perform impedance control of the lower electrode 18. In the graph 72, for example, in the sections 73 to 76, one or more of the gas species and the high-frequency power are switched, for example, in a stepwise manner. In the section 73, the gas species is gas species A and the high-frequency power is 200 W, and it is assumed that the conduction angle α is 90 degrees. In the section 74, the gas species is switched to gas species B, the high-frequency power is maintained at 200 W, and the conduction angle α is switched to, for example, 75 degrees. In the section 75, the gas species is switched to gas species A, the high-frequency power is switched to 500 W, and the conduction angle α is switched to, for example, 160 degrees. In the section 76, the gas species is switched to gas species B, the high-frequency power is maintained at 500 W, and the conduction angle α is switched to, for example, 135 degrees. Thereby, the plasma processing apparatus 1 can perform impedance control of the lower electrode 18 synchronized with the process recipe with respect to plasma fluctuations according to the process recipe.

[0048] Also, as another example, for the high frequency supplied from the high frequency power supply 26, it may be a high frequency with a pulse waveform having a specific pulse width, and the on signal 44 may be generated based on the pulse waveform. In this case, examples of the specific pulse width include pulse widths in the unit of microseconds (μs) to milliseconds (ms). For example, the specific pulse width is from 1 μs to 1000 ms. In this case, in the plasma processing apparatus 1, impedance control of the lower electrode 18 synchronized with the pulse timing can be performed for extremely short-time plasma ignition (so-called pulse plasma) or plasma fluctuations.

[0049] Also, as another example, the on signal 44 may be generated based on the bias signal supplied to the upper electrode 20. The bias signal is supplied to the upper electrode 20, for example. Note that the bias signal may include a DC power supply. Also, the bias signal is, for example, a high frequency signal (high frequency power) of 400 kHz, a single pulse of DC voltage or a continuous pulse which is a periodic pulse, and a DC voltage (DC), etc. The pulse width of the single pulse or continuous pulse of DC voltage may be a pulse in the range of, for example, 1 [μs] to 10 [s]. In this case, in the plasma processing apparatus 1, impedance control of the lower electrode 18 can be performed based on the on / off timing of the bias signal and the current value of the lower electrode 18 (corresponding to the above-mentioned high frequency current I in ). That is, the plasma processing apparatus 1 can optimize the plasma distribution according to the processing conditions.

[0050] As another example, the on-signal 44 may be controlled to respond to sudden plasma fluctuations due to abnormal discharges, pressure value disturbances, etc. based on various monitor values. The various monitor values include, for example, the flow rate of the processing gas supplied to the processing space 10s, the plasma density and electron temperature in the processing space 10s, the voltage and current of the high-frequency power, and the pressure and temperature in the chamber 10. In this case, in the plasma processing apparatus 1, impedance control of the lower electrode 18 can be performed based on various monitor values. That is, the plasma processing apparatus 1 can suppress sudden plasma fluctuations due to external disturbances.

[0051] As described above, according to the present embodiment, the plasma processing apparatus 1 includes a processing container (chamber 10), an applied electrode (upper electrode 20), a counter electrode (lower electrode 18), and a phase control circuit 40. The processing container is configured to form a processing space 10s. The applied electrode is configured to be provided on one side of the processing space 10s and is connected to the high-frequency power source 26. The counter electrode is configured to be provided on the other side of the processing space 10s. The phase control circuit 40 is configured to include a semiconductor switch (for example, FET 41) and is connected to the counter electrode. The semiconductor switch receives, as a control signal, an on-signal 44 that is shorter than one cycle of the high frequency and is synchronized with the frequency of the high frequency output from the high-frequency power source 26. As a result, the impedance of the counter electrode can be controlled to follow the frequency of the high frequency.

[0052] Further, according to the present embodiment, the phase control circuit 40 is further configured to include a detector 42 that detects a high-frequency current between the high-frequency power source 26 and the semiconductor switch. Also, the on-signal 44 is generated based on the current detected by the detector 42. As a result, the impedance of the counter electrode can be controlled to follow the frequency of the high frequency.

[0053] Further, according to the present embodiment, the phase control circuit 40 includes capacitive elements (capacitor C1 and / or capacitor C2). As a result, the DC component can be cut. Also, the capacitance component between the drain and source of the FET 41 can be adjusted.

[0054] Also, according to the present embodiment, the phase control circuit 40 includes inductive elements at one or more positions on the high-frequency power supply 26 side relative to the detector 42 and on the ground side relative to the semiconductor switch. As a result, in the generation of the on-signal 44, the influence of the inductive elements can be excluded.

[0055] Also, according to the present embodiment, the on-signal 44 is generated based on the switching of the gas species of the process gas supplied to the processing space 10s. As a result, impedance control of the counter electrode can be performed in synchronization with the process recipe.

[0056] Also, according to the present embodiment, the on-signal 44 is generated based on the switching of the flow rate of the process gas supplied to the processing space 10s. As a result, impedance control of the counter electrode can be performed in synchronization with the process recipe.

[0057] Also, according to the present embodiment, the high-frequency is a high-frequency with a pulse waveform having a specific pulse width. Also, the on-signal 44 is generated based on the pulse waveform. As a result, impedance control of the counter electrode can be performed in synchronization with the pulse timing.

[0058] Also, according to the present embodiment, the on-signal 44 is generated based on the bias signal supplied to the applied electrode. As a result, impedance control of the counter electrode can be performed based on the on / off timing of the bias signal.

[0059] Also, according to the present embodiment, the on-signal 44 is generated with the zero-crossing point when the waveform of the high-frequency current changes from the minus side to the plus side as the reference point for the period of the on-signal 44. As a result, the switching loss of the FET 41 can be reduced.

[0060] Also, according to the present embodiment, the period of the on-signal 44 has sections corresponding to the phases of the current for the same angle centered on the reference point in the advancing direction and the delaying direction of the phase. As a result, the switching loss of the FET 41 can be reduced.

[0061] Also, according to the present embodiment, the semiconductor switch is the FET 41. Also, the on-signal 44 is a signal for which conduction occurs between the drain and source of the FET 41. As a result, the capacitive component between the drain and source of the FET 41 can be controlled.

[0062] Also, according to the present embodiment, the plasma processing method is a plasma processing method in the plasma processing apparatus 1, and among an application electrode connected to the high-frequency power supply 26 disposed in the processing space 10s within the processing container and a counter electrode facing the application electrode, an on-signal 44 shorter than one cycle of the high-frequency is input to the semiconductor switch of the phase control circuit 40 connected to the counter electrode in synchronization with the frequency of the high-frequency output from the high-frequency power supply 26. Also, the period of the on-signal 44 is changed according to the processing conditions. As a result, impedance control of the counter electrode synchronized with the process recipe can be performed.

[0063] The embodiments disclosed this time should be considered to be illustrative in all respects and not restrictive. The above embodiments may be omitted, replaced, or changed in various forms without departing from the scope and gist of the appended claims.

[0064] Also, in the above-described embodiment, the form in which a high-frequency signal is supplied to the upper electrode 20 and the lower electrode 18 is grounded via the phase control circuit 40 has been described, but the present invention is not limited to this. For example, a form in which a high-frequency signal is supplied to the lower electrode 18 and the upper electrode 20 is grounded via the phase control circuit 40 may also be used.

[0065] Note that the present disclosure can also adopt the following configuration. (1) A processing container configured to form a processing space, configured to be provided on one side of the processing space and an application electrode connected to a high-frequency power supply, a counter electrode configured to be provided on the other side of the processing space, and a phase control circuit configured to include a semiconductor switch and connected to the counter electrode, wherein the semiconductor switch receives, as a control signal, a turn-on signal that is synchronized with the frequency of the high-frequency output from the high-frequency power supply and is shorter than one cycle of the high-frequency, a plasma processing apparatus. (2) The phase control circuit is further configured to include a detector for detecting the high-frequency current between the high-frequency power supply and the semiconductor switch, and the turn-on signal is generated based on the current detected by the detector. The plasma processing apparatus according to (1). (3) The phase control circuit includes a capacitive element. The plasma processing apparatus according to (1) or (2). (4) The phase control circuit includes an inductive element at one or more positions on the high-frequency power supply side of the detector and on the ground side of the semiconductor switch. The plasma processing apparatus according to (2) or (3). (5) The turn-on signal is generated based on a change in the gas species of the processing gas supplied to the processing space. The plasma processing apparatus according to any one of (1) to (4). (6) The turn-on signal is generated based on a change in the flow rate of the processing gas supplied to the processing space. The plasma processing apparatus according to any one of (1) to (4). (7) The high-frequency is a high-frequency of a pulse waveform having a specific pulse width, and the turn-on signal is generated based on the pulse waveform. The plasma processing apparatus according to any one of (1) to (4) above. (8) The on-signal is generated based on a bias signal supplied to the application electrode. The plasma processing apparatus according to any one of (1) to (4) above. (9) The on-signal is generated with a zero-crossing point when the waveform of the high-frequency current changes from the negative side to the positive side as a reference point for the period of the on-signal. The plasma processing apparatus according to any one of (2) to (8) above. (10) The period of the on-signal has sections corresponding to the phase of the current for the same angle centered on the reference point in the direction of phase advance and the direction of phase delay. The plasma processing apparatus according to (9) above. (11) The semiconductor switch is a FET (Field Effect Transistor). The on-signal is a signal for which conduction occurs between the drain and source of the FET. The plasma processing apparatus according to any one of (1) to (10) above. (12) A plasma processing method in a plasma processing apparatus, Among an application electrode connected to a high-frequency power source and an opposing electrode opposing the application electrode, which are arranged in a processing space within a processing container, an on-signal shorter than one cycle of the high-frequency is input to a semiconductor switch of a phase control circuit connected to the opposing electrode in synchronization with the frequency of the high-frequency output from the high-frequency power source. The period of the on-signal is changed according to processing conditions. Plasma processing method. (13) The processing conditions are the gas species of the processing gas supplied to the processing space. The plasma processing method according to (12) above. (14) The processing conditions are the flow rate of the processing gas supplied to the processing space. The plasma processing method according to (12) above. (15) The high-frequency wave is a high-frequency wave having a specific pulse width, The processing conditions are the pulse waveform, The plasma processing method according to (12) above. (16) The processing conditions are the bias signal supplied to the application electrode, The plasma processing method according to (12) above.

Explanation of symbols

[0066] 1 Plasma processing apparatus 10 Chamber 10s Processing space 18 Lower electrode 20 Upper electrode 26 High-frequency power supply 40 Phase control circuit 41 FET 42 Detector 43 Generation unit 44 On signal W Substrate

Claims

1. A processing container configured to form a processing space, An application electrode configured to be provided on one side of the processing space and connected to a high-frequency power supply, A counter electrode configured to be provided on the other side of the processing space, A phase control circuit configured to include a semiconductor switch and connected to the counter electrode, The semiconductor switch receives, as a control signal, an on-signal that is shorter than one cycle of the high-frequency signal and synchronized with the frequency of the high-frequency signal output from the high-frequency power supply. A plasma processing apparatus.

2. The phase control circuit is further configured to include a detector for detecting the high-frequency current between the high-frequency power supply and the semiconductor switch. The on-signal is generated based on the current detected by the detector. The plasma processing apparatus according to claim 1.

3. The phase control circuit includes a capacitive element. The plasma processing apparatus according to claim 2.

4. The phase control circuit includes an inductive element at one or more positions on the high-frequency power supply side of the detector and on the ground side of the semiconductor switch. The plasma processing apparatus according to claim 2.

5. The on-signal is generated based on a change in the gas species of the processing gas supplied to the processing space. The plasma processing apparatus according to claim 2.

6. The on-signal is generated based on a change in the flow rate of the processing gas supplied to the processing space. The plasma processing apparatus according to claim 2.

7. The high-frequency signal is a high-frequency signal having a specific pulse width and a pulse waveform. The on-signal is generated based on the pulse waveform. The plasma processing apparatus according to claim 2.

8. The on-signal is generated based on a bias signal supplied to the application electrode. The plasma processing apparatus according to claim 2.

9. The on-signal is generated using the zero-crossing point when the waveform of the high-frequency current changes from the negative side to the positive side as a reference point for the period of the on-signal. The plasma processing apparatus according to claim 2.

10. The period of the on-signal has intervals corresponding to the phase of the current for the same angular portion in the advancing and retarding directions of the phase, centered on the reference point. The plasma processing apparatus according to claim 9.

11. The semiconductor switch is an FET (Field Effect Transistor). The on-signal is a signal that conducts between the drain and source of the FET. The plasma processing apparatus according to claim 2.

12. A plasma processing method in a plasma processing apparatus, Among an application electrode connected to a high-frequency power source and a counter electrode disposed in a processing space within a processing container and opposed to the application electrode, an on-signal shorter than one cycle of the high-frequency is input to a semiconductor switch of a phase control circuit connected to the counter electrode in synchronization with the frequency of the high-frequency output from the high-frequency power source. The period of the on-signal is changed according to processing conditions. Plasma processing method.

13. The processing condition is the type of processing gas supplied to the processing space. The plasma processing method according to claim 12.

14. The processing condition is the flow rate of the processing gas supplied to the processing space. The plasma processing method according to claim 12.

15. The high-frequency is a high-frequency having a specific pulse width and having a pulse waveform, The processing condition is the pulse waveform. The plasma processing method according to claim 12.

16. The processing condition is a bias signal supplied to the application electrode. The plasma processing method according to claim 12.

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