Semiconductor integrated circuit classifying engine learning method, semiconductor integrated circuit classifying method and semiconductor integrated circuit designing method

Abstract

To facilitate, in an automation of a layout design for a semiconductor integrated circuit, an appropriate selection of layout data as an initial value utilized in Warm Start.SOLUTION: A semiconductor integrated circuit classifying engine learning method includes: a base design data obtaining step of obtaining base designing data corresponding to each of one or more pieces of hardware configuration information; a generating step of generating multiple additional design data; and a learning step of causing a neural network to learn with each of the multiple additional design data being as an input. Each of the multiple additional design data includes partial base design data that is a portion of the base design data. One major ID value is allocated to each of the one or more pieces of hardware configuration information. The neural network is caused to, in the learning step, learn in such a way that each of the multiple additional design data is taken as an input so as to estimate the one major ID value corresponding to the additional design data.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] The present disclosure relates to a classification engine learning method for semiconductor integrated circuits, a semiconductor integrated circuit classification method, and a semiconductor integrated circuit design method.

Background Art

[0002] Conventionally, methods for designing semiconductor integrated circuits have been studied. The process of generating information necessary for the design and manufacture of semiconductor integrated circuits includes many stages, from the initial stage such as determining the operation specifications represented by hardware structure information described in a hardware description language to the final stage such as the layout of each component and wiring of the semiconductor integrated circuit.

[0003] Among these stages, there are EDA (Electronic Design Automation) tools for automating the layout stage. By using such tools, the layout stage can be automated.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Non-Patent Documents

[0005]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] To design a layout using such tools, usually a large amount of computing resources and time are required.

[0007] To reduce computing resources and time, when designing a layout by an EDA tool, there is a so-called Warm Start method that uses the base layout data as an initial value. However, if it is hardware structure information derived from already designed layout hardware structure information, etc., the designed layout data can be used as an initial value, but if it is not such hardware structure information, it is generally difficult to select layout data as an initial value. Also, if the layout data used as an initial value is not appropriate, the design quality may deteriorate. In such a technical field, for example, Patent Document 1 discloses a layout classification method, but does not disclose a method for selecting layout data suitable for the initial value of Warm Start.

[0008] Therefore, an object of the present disclosure is to facilitate the selection of appropriate layout data as an initial value used in Warm Start in the automation of semiconductor integrated circuit layout design.

Means for Solving the Problems

[0009] In order to achieve the above object, a classification engine learning method for a semiconductor integrated circuit according to an aspect of the present disclosure includes: a base design data acquisition step of acquiring base design data corresponding to each of one or more different hardware structure information describing the semiconductor integrated circuit; a generation step of generating a learning design data group including a plurality of additional design data based on the base design data; and a learning step of causing a neural network to learn using each of the plurality of additional design data as an input. Each of the plurality of additional design data is different from each other and includes partial base design data that is a part of the base design data and different from the base design data. One major ID value out of one or more different major ID values is assigned to each of the one or more hardware structure information. In the learning step, the neural network is caused to learn using each of the plurality of additional design data as an input so as to infer one major ID value corresponding to the additional design data out of the one or more major ID values.

[0010] In order to achieve the above object, a semiconductor integrated circuit classification method according to an aspect of the present disclosure includes: an assignment step of assigning one major ID value out of a plurality of different major ID values to each of a plurality of different hardware structure information and layout data of a semiconductor integrated circuit created based on each of the plurality of hardware structure information; an unclassified base design data acquisition step of acquiring unclassified base design data corresponding to unclassified hardware structure information different from the plurality of hardware structure information; and an inference step of inferring one major ID value corresponding to the unclassified base design data out of the plurality of major ID values by inputting the unclassified base design data to a learned neural network.

[0011] To achieve the above object, a semiconductor integrated circuit design method according to an aspect of the present disclosure includes a classification step of classifying the unclassified hardware structure information by inferring the one major ID value by the semiconductor integrated circuit classification method, and one of the plurality of hardware structure information to which the one major ID value is assigned, and layout data creation step of creating layout data based on the unclassified hardware structure information, based on the one hardware structure information and design data related to the layout data created based on the one hardware structure information.

Effect of the Invention

[0012] According to the present disclosure, in the automation of the layout design of a semiconductor integrated circuit, it is possible to facilitate the selection of appropriate layout data as an initial value used in Warm Start.

Brief Description of the Drawings

[0013]

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Embodiments for Carrying Out the Invention

[0014] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. Note that all the embodiments described below are specific examples of the present disclosure. The numerical values, shapes, materials, standards, components, arrangement positions and connection forms of the components, steps, order of steps, etc. shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Among the components in the following embodiments, components not described in the independent claims indicating the top-level concept of the present disclosure are described as optional components. Also, each drawing is not necessarily drawn precisely. In each drawing, substantially the same configuration is denoted by the same reference numeral, and redundant descriptions may be omitted or simplified.

[0015] (Embodiment 1) A classification engine learning method, a semiconductor integrated circuit classification method, a semiconductor integrated circuit design method, and a semiconductor integrated circuit design system according to Embodiment 1 will be described.

[0016] [1-1. Semiconductor integrated circuit design system] The configuration of the semiconductor integrated circuit design system according to this embodiment will be described with reference to FIG. 1. FIG. 1 is a block diagram showing the overall configuration of a semiconductor integrated circuit design system 10 according to this embodiment.

[0017] The semiconductor integrated circuit design system 10 is a system that designs the (physical) layout of a semiconductor integrated circuit based on hardware structure information that describes the semiconductor integrated circuit. The hardware structure information is the structure information in which the semiconductor integrated circuit is described by a hardware description language, and is also referred to as a hardware structure statement. The hardware structure information describes specifications such as the configuration and operation of the semiconductor integrated circuit. For example, the hardware structure information may be a gate-level netlist. The hardware description language in which the hardware structure information is described is not particularly limited. The hardware structure information may be described, for example, in RTL (Register Transfer Level), at the behavioral level, or in the Unified Modeling Language (UML).

[0018] As shown in FIG. 1, the semiconductor integrated circuit design system 10 according to the present embodiment includes a classification engine learning device 20, a classification engine 40, a semiconductor integrated circuit design device 60, and a database 80.

[0019] In the semiconductor integrated circuit design system 10, the layout of unclassified hardware structure information, which is hardware structure information for which design information such as layout data has not been obtained, is designed using the semiconductor integrated circuit design device 60, which is a layout automatic design device. In the semiconductor integrated circuit design device 60, a layout is designed using a method called Warm Start. In the method called Warm Start, the base layout data is input as the initial value of the layout design. Hereinafter, the layout data input to the semiconductor integrated circuit design device 60 as the initial value is also referred to as initial layout data. By using appropriate initial layout data in the layout design, the calculation resources and time in the layout design can be reduced.

[0020] In this embodiment, one or more layout data corresponding to one or more hardware structure information are stored in the database 80. The classification engine 40 is a neural network that has been learned to select initial layout data corresponding to the unclassified hardware structure information, and selects the layout data corresponding to the unclassified hardware structure information from among the one or more layout data. The learning of the classification engine 40 is performed by the classification engine learning device 20. Hereinafter, each component of the semiconductor integrated circuit design system 10 will be described.

[0021] The database 80 is a storage circuit that stores data used in each component of the semiconductor integrated circuit design system 10 according to this embodiment. In this embodiment, the database 80 stores one or more hardware structure information, one or more major ID values, one or more layout data, and the like.

[0022] The classification engine learning device 20 is a device that causes the classification engine 40 to learn using a classification engine learning method described later. The classification engine learning device 20 will be described with reference to FIG. 2. FIG. 2 is a block diagram showing the functional configuration of the classification engine learning device 20 according to this embodiment. The database 80 is also shown in FIG. 2. As shown in FIG. 2, the classification engine learning device 20 includes an acquisition unit 22, a generation unit 24, and a learning unit 26.

[0023] The acquisition unit 22 is an example of a first acquisition unit that acquires base design data, which is design data corresponding to each of one or more different hardware structure information that describes a semiconductor integrated circuit. Here, the design data is data used for the layout design corresponding to the hardware structure information. As the design data, for example, data in the form of a graph object can be used. In this embodiment, the acquisition unit 22 acquires a base graph object in the form of a graph object as the base design data.

[0024] The base graph object is a graph object obtained by converting hardware structure information. The acquisition unit 22 may acquire the base graph object from a database 80 or the like, or may acquire the base graph object by converting one or more pieces of hardware structure information. In the present embodiment, one or more pieces of hardware structure information are stored in the database 80, and the acquisition unit 22 converts each of the one or more pieces of hardware structure information into a base graph object.

[0025] The base graph object may be, for example, a graph object in CDFG (Control Data Flow Graph) format. The base graph object includes a plurality of base nodes and one or more base edges obtained by converting each description in the hardware structure information. Each of the plurality of base nodes is a node corresponding to a hardware instance that realizes a function represented by the hardware structure information corresponding to the base graph object among one or more pieces of hardware structure information. Each of the one or more base edges is an edge corresponding to a connection part connected to the hardware instance.

[0026] In the present embodiment, the one or more pieces of hardware structure information include a plurality of pieces of hardware structure information. Each of the one or more pieces of hardware structure information is already designed hardware structure information, and layout data for each of the one or more pieces of hardware structure information has been obtained. One of the one or more different major ID values is assigned to each of the one or more pieces of hardware structure information. Each of the one or more major ID (Identification Data) values is identification information for identifying each piece of hardware structure information.

[0027] In the present embodiment, based on a plurality of different hardware structure information for describing a semiconductor integrated circuit and layout data of the semiconductor integrated circuit created based on each of the plurality of hardware structure information, one major ID value out of a plurality of different major ID values is assigned to each of the plurality of hardware structure information. The assignment of the plurality of major ID values may be performed, for example, in the classification engine learning device 20, or may be stored in the database 80 in a state where the plurality of major ID values are assigned to the plurality of hardware structure information in advance.

[0028] Note that in the present embodiment, one or more pieces of hardware structure information, one or more major ID values respectively associated with the one or more pieces of hardware structure information, and one or more layout metadata are acquired from the database 80, but may be input to the classification engine learning device 20 from an input device other than the database 80. The hardware instance includes, for example, a gate, a register, and the like. Further, when the hardware structure information is described in the unified modeling language, the hardware instance includes units such as a CPU (Central Processing Unit).

[0029] The base graph object according to the present embodiment will be described with reference to FIG. 3. FIG. 3 is a diagram showing an example of the base graph object according to the present embodiment. In the example shown in FIG. 3, the base graph object includes base nodes N11, N21, N22, N23, N24, N31, N32, N33, N41, N42 and base edges E11, E21, E22, E23, E24, E31, E32, E33, E41, E42.

[0030] The plurality of base nodes include base nodes corresponding to operators, base nodes performing sequential operations, and the like. The plurality of base nodes include one or more first base nodes, and each of the one or more first base nodes may have, as a feature quantity, the degree of complexity of operations in the hardware instance corresponding to the first base node. Here, as the complexity of operations, for example, the amount of calculation (order) representing the performance of operations using a certain algorithm is used. As the amount of calculation, there are concepts such as time complexity (processing time) and space complexity (memory usage). As a method of expressing time complexity, the O notation is typical. As the O notation, in ascending order of short processing time, there are O(1): constant time, O(logN): logarithmic time, O(N): linear time, O(NlogN): quasi-linear · linear logarithmic time, O(N^2): quadratic time, O(N^3): polynomial time, O(k^N): exponential time, and O(N!): factorial time.

[0031] In addition, one or more base nodes include one or more second base nodes, and each of the one or more second base nodes may have, as a feature quantity, the number of inputs to the second base node. For example, the number of inputs to base node N11 is 4, and the number of inputs to base node N22 is 2.

[0032] In addition, the plurality of base nodes include one or more third base nodes, and each of the one or more third base nodes may have, as a feature quantity, the number of base nodes through which the input to the third base node passes among the plurality of base nodes. For example, the base nodes through which the input to base node N23 passes (that is, the serially connected nodes through which the input to base node N23 passes) are two, namely base node N33 and base node N41 (or base node N42).

[0033] In addition, one or more base nodes may have, as feature quantities, the calculation efficiency, power efficiency, etc. of the operator.

[0034] One or more base edges include one or more first base edges, and each of the one or more first base edges may have, as a feature amount, the amount of information transmitted by a connection corresponding to the first base edge.

[0035] Also, the hardware structure information is described in RTL, and the connection corresponding to each of the one or more base edges may be a wiring connected to a hardware instance. The wiring has a bus structure, and the amount of information transmitted by the connection corresponding to the base edge includes the bus width of the bus structure. For example, in the example shown in FIG. 3, the bus width of the base edge E21 may be 4 bits. The bus width of the base edge E22 may be 32 bits. The bus widths of the base edges E23, E31, E32, and E33 may be 16 bits. The bus width of the base edge E24 may be 2 bits. The bus widths of the base edges E41 and E42 may be 8 bits.

[0036] When the hardware structure information is a gate-level netlist closer to layout data than the RTL description, generally, technology information, constraint information, etc. that are not described in the hardware structure information are set as premises.

[0037] Here, the technology information is information that varies for each semiconductor manufacturing process. The gate-level netlist (for a specific manufacturing process) is closer to the layout data (for a specific manufacturing process) than the combination of the RTL description and the technology information (for a specific manufacturing process).

[0038] This technology information may be included in the feature amount of the base node. Thereby, in the classification engine 40, it becomes possible to make an inference considering information related to the manufacturing process (for example, library information). Also, by controlling the weight of this feature amount, it is possible to control the degree of consideration of the manufacturing process in the inference (inference considering the information of the manufacturing process or inference not based on the manufacturing process (that is, considering the circuit structure as the center)).

[0039] The constraint information includes, for example, constraints on the operating frequency of the semiconductor integrated circuit, constraint information on the area, etc. This constraint information may be included in the feature amount of the base node. Thereby, in the classification engine 40, inference considering the constraint information becomes possible. Also, by controlling the weight of this feature amount, it is possible to control the degree of consideration of the constraint information in the inference (whether to perform inference considering the constraint information or inference not based on the constraint information (considering the circuit structure as the center)).

[0040] By embedding the index related to the physical metrics of the semiconductor integrated circuit as a feature amount into the neural network included in the classification engine 40 in this way, learning of the neural network based on more information becomes possible. As described above, the neural network according to the present embodiment is a graph neural network. In the graph neural network, convolution calculation considering the connection relationship between nodes is performed. However, by adding additional information other than the connection relationship as a feature amount to the graph neural network, it is possible to learn about the features of the graph object to be learned using more information. Therefore, the accuracy of inference by the neural network can be improved.

[0041] Also, each of the plurality of base nodes may have, as a feature amount, the disadvantage of the operation such as the calculation cost of the node corresponding to the operator and the complexity of the operation. Also, each of the plurality of first nodes may have, as a feature amount, the advantage of the operation such as the calculation efficiency and power efficiency of the node corresponding to the operator. Thereby, by embedding the index related to the physical metrics of the semiconductor integrated circuit as a feature amount into the neural network, learning based on more information becomes possible. Therefore, the accuracy of inference by the neural network can be improved. Also, by having the disadvantage of the operation as a feature amount, it becomes possible to treat the disadvantage of the operation as the importance of the design issue. Also, by having the advantage of the operation as a feature amount, it becomes possible to treat the advantage of the operation as the importance that is a trade-off with the disadvantage of the operation.

[0042] The generation unit 24 shown in FIG. 2 is a processing unit that generates a learning design data group including a plurality of additional design data based on the base design data. The plurality of additional design data may be stored in the generation unit 24, for example, or may be stored in the database 80. Each of the plurality of additional design data is different from each other and is a part of the base design data, and includes a partial base graph object different from the base design data. Note that the base design data may be included in the plurality of additional design data.

[0043] In the present embodiment, the generation unit 24 generates a learning design data group including a plurality of additional graph objects in graph object form as the plurality of additional design data based on the base graph object. Each of the plurality of additional graph objects is different from each other and is a part of the base graph object, and includes a partial base graph object different from the base graph object as partial base design data. Note that the base graph object may be included in the plurality of additional graph objects.

[0044] The partial base graph object includes a plurality of partial nodes, and the number of the plurality of partial nodes may be more than half of the number of the plurality of base nodes. For example, among the base graph objects shown in FIG. 3, a graph object including the base nodes N11, N23, N24, N33, N41, N42 and the base edges E11, E23, E24, E33, E41, E42 may be a partial base graph object. In this case, the base nodes N11, N23, N24, N33, N41, N42 correspond to the plurality of partial nodes included in the partial base graph object, and the base edges E11, E23, E24, E33, E41, E42 correspond to one or more partial edges included in the partial base graph object. By generating the partial base graph object in this way, it is possible to generate a partial base graph object similar to the base graph object and different from the base graph object.

[0045] The plurality of additional graph objects may include a combined graph object of a partial base graph object and a noise graph object. The configuration of the noise graph object is not particularly limited, but the number of nodes of the noise graph object may be less than the number of partial nodes of the partial base graph object. By generating a plurality of additional graph objects in this way, it becomes possible to generate a large number of graph objects that are similar to the base graph object and different from the base graph object.

[0046] The generation unit 24 shown in FIG. 2 may generate a partial base graph object based on the feature amounts of the plurality of base nodes included in the base graph object. For example, the generation unit 24 may classify the plurality of base nodes into a plurality of groups including a first group and a second group based on the first feature amount of the plurality of base nodes. The plurality of partial nodes included in the partial base graph object generated by the generation unit 24 may include the base nodes included in the first group and the base nodes included in the second group among the plurality of base nodes included in the base graph object. Here, the range of the first feature amount corresponding to the first group may include a representative value of the first feature amount. The representative value of the first feature amount may be, for example, the median value, the average value, or the mode value of the first feature amount.

[0047] For example, in the example shown in FIG. 3, a case where the number of inputs to the base node is used as the first feature amount and the most frequent value is used as the representative value will be described. As shown in FIG. 3, the number of inputs is 1 at the base nodes N21, N23, N24, N31, N32, N41, N42, the number of inputs is 2 at the base nodes N22, N33, and the number of inputs is 4 at the base node N11. Therefore, the most frequent value of the number of inputs, which is the first feature amount, is 1. Thus, the value of the first feature amount corresponding to the first group is determined to be 1, and the value of the first feature amount corresponding to the second group is determined to be, for example, 2. In this case, the partial nodes included in the partial base graph object may include at least one of the base nodes N21, N23, N24, N31, N32, N41, N42 included in the first group and at least one of the base nodes N22, N33 included in the second group. By generating the partial base graph object in this way, it is possible to suppress the bias of the feature amounts in the partial base graph object. Therefore, a partial base graph object similar to the base graph object can be generated.

[0048] Further, the partial base graph object may be generated by sampling a part of the base graph object using a known sampling method such as that disclosed in Non-Patent Document 1.

[0049] The learning unit 26 shown in FIG. 2 is a processing unit that causes a neural network to learn using each of a plurality of additional design data generated by the generation unit 24 as an input. The learned neural network learned by the learning unit 26 is used in the classification engine 40. The neural network classifies the unclassified hardware structure information in the classification engine 40. In the present embodiment, the neural network is a graph neural network.

[0050] The learning unit 26 causes the neural network to learn so as to infer one major ID value corresponding to the additional design data from among one or more major ID values, using each of the plurality of additional design data as an input.

[0051] In this embodiment, the learning unit 26 causes a neural network to learn by using, as a plurality of additional data, each of a plurality of additional graph objects as an input. The learning unit 26 causes the neural network to learn so as to infer, from among one or more major ID values, one major ID value corresponding to the additional graph object by using each of the plurality of additional graph objects as an input. That is, in the learning unit 26, when a plurality of additional graph objects generated based on one piece of hardware structure information are inputs to the neural network, the neural network is caused to learn so as to infer one major ID value corresponding to the one piece of hardware structure information. That is, the learning unit 26 causes the neural network to learn so as to classify a plurality of additional graph objects into one group represented by one corresponding base graph object. Being classified in this way means that when the semiconductor integrated circuit design apparatus 60 performs layout design of the plurality of additional graph objects classified into the one group, layout data corresponding to the one base graph object can be used as initial layout data.

[0052] In this embodiment, in learning of the neural network, since a plurality of additional design data are used as inputs, the accuracy of inference by the neural network can be improved as compared with the case where only base design data are used as an input.

[0053] Further, since each of the plurality of additional design data includes partial base design data that is a part of the base design data, they are similar to the base design data. Therefore, when the semiconductor integrated circuit design apparatus 60 designs the layout of each of the plurality of additional design data, by using the layout data corresponding to the base design data as initial layout data, the computational resources and time required for the design can be reduced.

[0054] The classification engine 40 shown in FIG. 1 is an engine that classifies unclassified hardware structure information using a neural network that has been learned by the classification engine learning device 20. The classification engine 40 according to the present embodiment will be described with reference to FIG. 4. FIG. 4 is a block diagram showing the functional configuration of the classification engine 40 according to the present embodiment. FIG. 4 also shows a database 80. As shown in FIG. 4, the classification engine 40 includes an acquisition unit 42 and an inference unit 44.

[0055] The acquisition unit 42 is an example of a second acquisition unit that acquires unclassified base design data corresponding to one or more hardware structure information (in the present embodiment, a plurality of hardware structure information) and different unclassified hardware structure information. In the present embodiment, the acquisition unit 42 acquires an unclassified base graph object in the graph object format as the unclassified base design data. The unclassified base graph object is a graph object obtained by converting unclassified hardware structure information. The acquisition unit 42 may acquire the unclassified base graph object from the database 80 or the like, or may acquire the unclassified base graph object by converting the unclassified hardware structure information. In the present embodiment, the unclassified hardware structure information is input to the classification engine 40, and the acquisition unit 42 converts the unclassified hardware structure information into an unclassified base graph object. The unclassified base graph object may be, for example, a graph object in the CDFG format.

[0056] The inference unit 44 has a neural network that has been learned by the classification engine learning device 20. The inference unit 44 infers one major ID value corresponding to the unclassified base design data among one or more major ID values by inputting the unclassified base design data into the learned neural network. In the present embodiment, the one or more hardware structure information includes a plurality of hardware structure information. As a result, the unclassified base design data is classified into a group corresponding to the inferred major ID value. That is, when the layout design of the unclassified hardware structure information is performed by the semiconductor integrated circuit design device 60, it is inferred that the layout data corresponding to the hardware structure information to which the major ID value is assigned can be used as the initial layout data. In the present embodiment, the inference unit 44 infers one major ID value corresponding to the unclassified base graph object among one or more major ID values by inputting the unclassified base graph object into the learned neural network.

[0057] The semiconductor integrated circuit design device 60 shown in FIG. 1 creates layout data based on the unclassified hardware structure information based on one hardware structure information to which one major ID value inferred by the classification engine 40 among the plurality of hardware structure information is assigned and design data related to the layout data created based on the one hardware structure information.

[0058] In the present embodiment, unclassified hardware structure information is input to the semiconductor integrated circuit design device 60, and layout data based on the unclassified hardware structure information is created.

[0059] As the semiconductor integrated circuit design device 60, an EDA tool for automating the design of the layout corresponding to the hardware structure information can be used, and any EDA tool that can support Warm Start can be used.

[0060] The semiconductor integrated circuit design device 60 acquires initial layout data from the database 80 based on one inferred major ID value. The initial layout data includes design data related to layout data corresponding to the hardware structure information to which one inferred major ID value is assigned. The initial layout data may include layout metadata in which metadata corresponding to the major ID value is synthesized into the design data. The layout metadata may include, for example, layout constraints, layout scripts, and the like.

[0061] As described above, by appropriately classifying the unclassified hardware structure information by the classification engine 40 having the neural network learned by the classification engine learning device 20, it is possible to select initial layout data suitable for the unclassified hardware structure information. Therefore, by performing layout design by the semiconductor integrated circuit design device 60 using the selected initial layout data, calculation resources and time can be reduced.

[0062] [1-2. Hardware Configuration] Next, the hardware configuration of the semiconductor integrated circuit design system 10 according to the present embodiment will be described with reference to FIG. 5. FIG. 5 is a diagram showing an example of the hardware configuration of a computer 1000 that realizes the functions of the semiconductor integrated circuit design system 10 according to the present embodiment by software.

[0063] As shown in FIG. 5, the computer 1000 includes an input device 1001, an output device 1002, a CPU 1003, a built-in storage 1004, a RAM 1005, a reading device 1007, a transmission / reception device 1008, and a bus 1009. The input device 1001, the output device 1002, the CPU 1003, the built-in storage 1004, the RAM 1005, the reading device 1007, and the transmission / reception device 1008 are connected by the bus 1009.

[0064] The input device 1001 is a device serving as a user interface such as an input button, a touch pad, a touch panel display, etc., and accepts user operations. Note that the input device 1001 may be configured to accept not only contact operations by the user but also operations by voice and remote operations using a remote control or the like.

[0065] The output device 1002 is a device that outputs signals from the computer 1000, and may be a device serving as a user interface such as a display, a speaker, etc. in addition to signal output terminals.

[0066] The built-in storage 1004 is a flash memory or the like. Also, the built-in storage 1004 may store in advance at least one of the data stored in the database 80 of the semiconductor integrated circuit design system 10, a program for realizing the functions of the semiconductor integrated circuit design system 10, and an application using the functional configuration of the semiconductor integrated circuit design system 10.

[0067] The RAM 1005 is a random access memory (Random Access Memory), and is used for storing data and the like when executing a program or an application.

[0068] The reading device 1007 reads information from a recording medium such as a USB (Universal Serial Bus) memory. The reading device 1007 reads the program or application recorded on the recording medium having the program or application as described above and stores it in the built-in storage 1004.

[0069] The transceiver device 1008 is a communication circuit for performing communication wirelessly or by wire. The transceiver device 1008 may communicate with a server device connected to a network, for example, and download the program or application as described above from the server device and store it in the built-in storage 1004.

[0070] The CPU 1003 is a central processing unit that copies programs, applications, etc. stored in the built-in storage 1004 to the RAM 1005 and sequentially reads and executes instructions included in the copied programs, applications, etc. from the RAM 1005.

[0071] [1-3. Classification Engine Learning Method for Semiconductor Integrated Circuits] The classification engine learning method for the semiconductor integrated circuit according to this embodiment will be described with reference to FIG. 6. FIG. 6 is a flowchart showing the flow of the classification engine learning method for the semiconductor integrated circuit according to this embodiment. The classification engine learning method for the semiconductor integrated circuit according to this embodiment is executed by the classification engine learning device 20.

[0072] As shown in FIG. 6, first, based on one or more different hardware structure information describing the semiconductor integrated circuit and the layout data of the semiconductor integrated circuit created based on each of the one or more hardware structure information, one of the one or more different major ID values is assigned to each of the one or more hardware structure information (first assignment step S21). In this embodiment, the one or more hardware structure information includes a plurality of hardware structure information. Each of the one or more hardware structure information may be a gate-level netlist.

[0073] Subsequently, the acquisition unit 22 of the classification engine learning device 20 acquires base design data corresponding to each of the one or more pieces of hardware structure information (base design data acquisition step S22). In the present embodiment, in the base design data acquisition step S22, the acquisition unit 22 acquires a base graph object in graph object format as the base design data. The base graph object includes a plurality of base nodes and one or more base edges obtained by converting each description in the hardware structure information. The plurality of base nodes include base nodes corresponding to operators, base nodes that perform sequential operations, and the like. The plurality of base nodes include one or more first base nodes, and each of the one or more first base nodes may have, as a feature amount, the degree of complexity of the operation in the hardware instance corresponding to the first base node.

[0074] Further, the one or more base nodes include one or more second base nodes, and each of the one or more second base nodes may have, as a feature amount, the number of inputs to the second base node.

[0075] Also, the plurality of base nodes include one or more third base nodes, and each of the one or more third base nodes may have, as a feature amount, the number of base nodes through which the input to the third base node passes among the plurality of base nodes.

[0076] The one or more base edges include one or more first base edges, and each of the one or more first base edges may have, as a feature amount, the amount of information transmitted by the connection part corresponding to the first base edge.

[0077] Subsequently, the generation unit 24 of the classification engine learning device 20 generates a learning design data group including a plurality of additional design data based on the base design data acquired in the base design data acquisition step S22 (generation step S24). Each of the plurality of additional design data is different from each other and is a part of the base design data and includes partial base design data different from the base design data.

[0078] In the present embodiment, in generation step S24, the generation unit 24 generates a learning design data group including a plurality of additional graph objects in graph object form as the plurality of additional design data. Each of the plurality of additional graph objects is different from each other and is a part of the base graph object, and includes a partial base graph object different from the base graph object as partial base design data. The partial base graph object includes a plurality of partial nodes, and the number of the plurality of partial nodes may be more than half of the number of the plurality of base nodes.

[0079] The plurality of additional graph objects may include a combined graph object of a partial base graph object and a noise graph object. The number of nodes of the noise graph object may be less than the number of partial nodes of the partial base graph object.

[0080] In generation step S24, the generation unit 24 may generate a partial base graph object based on the feature amounts of the plurality of base nodes included in the base graph object. In generation step S24, the generation unit 24 may classify the plurality of base nodes into a plurality of groups including a first group and a second group based on the first feature amount of the plurality of base nodes. The plurality of partial nodes included in the partial base graph object generated by the generation unit 24 may include the base nodes included in the first group and the base nodes included in the second group among the plurality of base nodes included in the base graph object. Here, the range of the first feature amount corresponding to the first group may include a representative value of the first feature amount. The representative value of the first feature amount may be, for example, the median, average value, or mode value of the first feature amount.

[0081] Subsequently, the learning unit 26 of the classification engine learning device 20 causes the neural network to learn using each of a plurality of additional design data (learning step S26). In learning step S26, the learning unit 26 causes the neural network to learn using each of the plurality of additional design data as input and infer one major ID value corresponding to the additional design data from among one or more major ID values. In the present embodiment, in learning step S26, the learning unit 26 causes the neural network to learn using each of a plurality of additional graph objects as the plurality of additional design data. In learning step S26, the learning unit 26 causes the neural network to learn using each of the plurality of additional graph objects as input and infer one major ID value corresponding to the additional graph object from among one or more major ID values.

[0082] As described above, by causing the neural network to learn using a plurality of additional design data, it is possible to perform inference with higher accuracy by the neural network than in the case of learning using only the base design data.

[0083] [1-4. Semiconductor Integrated Circuit Classification Method] The semiconductor integrated circuit classification method according to the present embodiment will be described with reference to FIG. 7. FIG. 7 is a flowchart showing the flow of the semiconductor integrated circuit classification method according to the present embodiment. The semiconductor integrated circuit classification method according to the present embodiment is executed by the classification engine 40.

[0084] As shown in FIG. 7, first, similar to the classification engine learning method, based on a plurality of different hardware structure information describing the semiconductor integrated circuit and layout data of the semiconductor integrated circuit created based on each of the plurality of hardware structure information, one major ID value is assigned to each of the plurality of hardware structure information from among a plurality of different major ID values (first assignment step S40).

[0085] Subsequently, a neural network that has been learned by the classification engine learning method of the semiconductor integrated circuit described above is prepared (preparation step S41). In the present embodiment, the neural network is learned in the classification engine learning device 20.

[0086] Subsequently, the acquisition unit 42 of the classification engine 40 acquires unclassified base design data corresponding to a plurality of hardware structure information and different unclassified hardware structure information (unclassified base design data acquisition step S42). In the present embodiment, in the unclassified base design data acquisition step S42, the acquisition unit 42 acquires an unclassified base graph object in the form of a graph object as the unclassified base design data.

[0087] In the unclassified base design data acquisition step S42, the acquisition unit 42 may acquire the unclassified base design data from a database 80 or the like, or may acquire the unclassified base design data by converting the unclassified hardware structure information. In the present embodiment, the unclassified hardware structure information is input to the classification engine 40, and in the unclassified base design data acquisition step S42, the acquisition unit 42 converts the unclassified hardware structure information into an unclassified base graph object as the unclassified base design data.

[0088] Subsequently, the inference unit 44 of the classification engine 40 infers one major ID value corresponding to the unclassified base design data among a plurality of major ID values by inputting the unclassified base design data to the learned neural network (inference step S44). In the present embodiment, in the inference step S44, one major ID value corresponding to the unclassified base graph object among a plurality of major ID values is inferred by inputting the unclassified base graph object as the unclassified base design data to the learned neural network.

[0089] As a result, the unclassified base design data is classified into groups corresponding to the inferred major ID values. That is, when the semiconductor integrated circuit design apparatus 60 performs the layout design of the unclassified hardware structure information, it is inferred that layout data corresponding to the hardware structure information to which the major ID value is assigned can be used as the initial layout data.

[0090] The results of verifying the semiconductor integrated circuit classification method according to this embodiment will be described. In this verification, a neural network trained by a classification engine learning method was prepared using eight different base graph objects A to H. The unclassified base graph object was generated by adding a noise graph object in an amount of about 40% of the entire base graph object A to the base graph object A. The results of classifying such an unclassified base graph object by the semiconductor integrated circuit classification method according to this embodiment will be described with reference to FIG. 8. FIG. 8 is a diagram showing the results of classification by the semiconductor integrated circuit classification method according to this embodiment. In FIG. 8, base graph objects A to H are shown in order of the reliability of the base graph objects. The reliability shown in FIG. 8 is a value indicating the degree to which it can be trusted that the base graph object is classified. The reliability is represented by a value between 0 and 1, and the larger the value, the higher the degree of trust.

[0091] The unclassified base graph object obtained by modifying the base graph object A is similar to the base graph object A but different from the base graph object A. Such an unclassified base graph object is classified into the base graph object A based on the reliability shown in FIG. 8. Thus, according to the semiconductor integrated circuit classification method according to this embodiment, the unclassified base graph object can be appropriately classified.

[0092] [1-5. Semiconductor Integrated Circuit Design Method] The semiconductor integrated circuit design method according to this embodiment will be described with reference to FIG. 9. FIG. 9 is a flowchart showing the flow of the semiconductor integrated circuit design method according to this embodiment. The semiconductor integrated circuit design method according to this embodiment is executed by the classification engine 40 and the semiconductor integrated circuit design apparatus 60.

[0093] As shown in FIG. 9, first, unclassified hardware structure information is classified by inferring one major ID value by the above-described semiconductor integrated circuit classification method (classification step S61).

[0094] Subsequently, based on one piece of hardware structure information to which one major ID value is assigned among a plurality of pieces of hardware structure information and design data related to layout data created based on the one piece of hardware structure information, layout data based on the unclassified hardware structure information is created (layout data creation step S62). In the layout data creation step S62, for example, using the layout data created based on the hardware structure information to which one major ID value inferred in the classification step S61 is assigned as the initial layout data, layout design is performed by the semiconductor integrated circuit design apparatus 60. The initial layout data may include layout metadata in which metadata corresponding to the major ID value is synthesized into the design data. The layout metadata may include, for example, layout constraints, layout scripts, and the like.

[0095] As described above, by appropriately classifying the unclassified hardware structure information by the classification engine 40 having the neural network learned by the classification engine learning apparatus 20, it is possible to select initial layout data suitable for the unclassified hardware structure information. Therefore, by performing layout design by the semiconductor integrated circuit design apparatus 60 using the selected initial layout data, calculation resources and time can be reduced.

[0096] (Embodiment 2) A classification engine learning method, a semiconductor integrated circuit classification method, a semiconductor integrated circuit design method, and a semiconductor integrated circuit design system according to Embodiment 2 will be described. In the classification engine learning method of the semiconductor integrated circuit according to this embodiment, etc., not only the major ID value but also the minor ID value based on the classification result from a predetermined perspective is used, which is different from the classification engine learning method of the semiconductor integrated circuit according to Embodiment 1, etc. Hereinafter, the classification engine learning method of the semiconductor integrated circuit according to this embodiment, etc., will be described centering on the differences from the classification engine learning method of the semiconductor integrated circuit according to Embodiment 1, etc.

[0097] [2-1. Semiconductor Integrated Circuit Design System] The configuration of the semiconductor integrated circuit design system according to this embodiment will be described with reference to FIG. 10. FIG. 10 is a block diagram showing the overall configuration of the semiconductor integrated circuit design system 110 according to this embodiment.

[0098] As shown in FIG. 10, the semiconductor integrated circuit design system 110 according to this embodiment includes a classification engine learning device 120, a classification engine 140, a semiconductor integrated circuit design device 60, and a database 80.

[0099] The classification engine learning device 120 according to this embodiment will be described with reference to FIG. 11. FIG. 11 is a block diagram showing the functional configuration of the classification engine learning device 120 according to this embodiment. The database 80 is also shown in FIG. 11. As shown in FIG. 11, the classification engine learning device 120 includes an acquisition unit 22, a generation unit 24, and a learning unit 126.

[0100] The learning unit 126 according to this embodiment is a processing unit that causes a neural network to learn using each of a plurality of additional design data generated by the generation unit 24 as an input, similar to the learning unit 26 according to Embodiment 1. In this embodiment, similar to the learning unit 26 according to Embodiment 1, the learning unit 126 causes a neural network to learn using each of a plurality of additional graph objects generated by the generation unit 24 as a plurality of additional design data as an input.

[0101] In this embodiment, for each of a plurality of additional design data corresponding to each of a plurality of hardware structure information, a first minor ID value based on the classification result from the first perspective is assigned. Also, in this embodiment, for each of a plurality of additional graph objects corresponding to each of a plurality of hardware structure information, a first minor ID value based on the classification result from the first perspective is assigned. A first minor ID value based on the classification result from the first perspective may be assigned to each of a plurality of hardware structure information. In this embodiment, the learning unit 126 assigns a first minor ID value to each of a plurality of additional graph objects.

[0102] The learning unit 126 causes the neural network to learn so as to infer a first minor ID value corresponding to the additional design data that is input to the neural network among a plurality of additional design data, in addition to the major ID value. Note that the learning unit 126 may cause the neural network to learn so as to infer a first minor ID value corresponding to the hardware structure information that is input to the neural network among a plurality of hardware structure information, in addition to the major ID value. In this embodiment, the learning unit 126 causes the neural network to learn so as to infer a first minor ID value corresponding to the additional graph object that is input to the neural network among a plurality of additional graph objects, in addition to the major ID value.

[0103] For example, each of the plurality of additional graph objects includes a plurality of additional nodes and one or more additional edges, and the first perspective may be related to the features of the plurality of additional nodes and one or more additional edges. Note that the first perspective is not limited to this. For example, the first perspective may be related to the circuit scale, the number of flip-flops, or the critical path length of the additional graph object or the base graph object.

[0104] Here, the major ID value and the first minor ID value will be described with reference to FIG. 12. FIG. 12 is a diagram showing an example of the assignment of the major ID value and the first minor ID value according to the present embodiment.

[0105] Among the ID values shown in FIG. 12, A001, A002, and A003 are major ID values, and B001, B002, and B003 are first minor ID values. In FIG. 12, additional graph objects 1-1, 1-2, and 1-3 generated based on the base graph object to which A001 is assigned as the major ID value, additional graph objects 2-1, 2-2, and 2-3 generated based on the base graph object to which A002 is assigned as the major ID value, and additional graph objects 3-1, 3-2, and 3-3 generated based on the base graph object to which A003 is assigned as the major ID value have first minor ID values assigned thereto. The first minor ID value B001 is assigned to the additional graph objects 1-1, 2-1, and 3-1, the first minor ID value B002 is assigned to the additional graph objects 1-2, 2-2, and 3-2, and the first minor ID value B003 is assigned to the additional graph objects 1-3, 2-3, and 3-3. In this way, not only the major ID value but also the minor ID value based on other perspectives is assigned to each additional graph object. Thereby, in addition to the classification focusing on the features of the base graph object based on the major ID value, it becomes possible to perform classification focusing on the features common to the additional graph objects based on a plurality of base graph objects.

[0106] Furthermore, for each of the plurality of additional design data corresponding to each of the plurality of hardware structure information, a second minor ID value based on the classification result from a second perspective different from the first perspective may be assigned. The learning unit 126 may assign a second minor ID value to each of the plurality of additional design data.

[0107] The learning unit 126 may cause the neural network to learn so as to infer a second minor ID value corresponding to the additional design data that is input to the neural network among the plurality of additional design data. Thereby, classification focusing on further different features becomes possible.

[0108] Note that, in the present embodiment, three or more minor ID values based on the classification results from three or more perspectives may be assigned, and the neural network may be caused to learn so as to infer three or more minor ID values.

[0109] The classification engine 140 according to the present embodiment shown in FIG. 10 will be described with reference to FIG. 13. FIG. 13 is a block diagram showing the functional configuration of the classification engine 140 according to the present embodiment. As shown in FIG. 13, the classification engine 140 includes an acquisition unit 42 and an inference unit 144. The database 80 is also shown in FIG. 13.

[0110] The inference unit 144 according to this embodiment has a neural network that has been trained by a classification engine learning method, similar to the inference unit 44 according to Embodiment 1. In this embodiment, the inference unit 144 inputs unclassified base design data into the trained neural network to infer one major ID value corresponding to the unclassified base design data among one or more major ID values, and to infer a first minor ID value corresponding to the unclassified base design data. The inference unit 144 may infer a major ID value and a first minor ID value corresponding to the unclassified hardware structure information. In this embodiment, the inference unit 144 inputs an unclassified base graph object into the trained neural network to infer one major ID value corresponding to the unclassified base graph object among one or more major ID values, and to infer a first minor ID value corresponding to the unclassified base graph object.

[0111] According to the classification engine 140 including such an inference unit 144, in addition to the classification focusing on the features of the base design data based on the major ID value, classification focusing on the features common to the additional design data based on a plurality of base design data becomes possible.

[0112] The inference unit 144 may infer a second minor ID value corresponding to the unclassified base design data. For example, the inference unit 144 may infer a second minor ID value corresponding to the unclassified base graph object. Thereby, classification focusing on further different features also becomes possible. Note that the inference unit 144 may infer three or more minor ID values based on the classification results from three or more viewpoints.

[0113] According to the semiconductor integrated circuit design system 110 including the classification engine learning device 120 and the classification engine 140 as described above, the initial layout data used in the semiconductor integrated circuit design device 60 can include layout metadata including the first minor ID value inferred by the classification engine 140. Thereby, the semiconductor integrated circuit design device 60 can perform layout design based on more detailed layout constraints and layout scripts. Therefore, computing resources and time can be further reduced, and the layout quality can be improved.

[0114] [2-2. Classification Engine Learning Method for Semiconductor Integrated Circuits] The classification engine learning method for a semiconductor integrated circuit according to the present embodiment will be described with reference to FIG. 14. FIG. 14 is a flowchart showing the flow of the classification engine learning method for a semiconductor integrated circuit according to the present embodiment. The classification engine learning method for a semiconductor integrated circuit according to the present embodiment is executed by the classification engine learning device 120.

[0115] First, similar to the classification engine learning method for a semiconductor integrated circuit according to Embodiment 1, a first allocation step S21, a base design data acquisition step S22, and a generation step S24 are executed.

[0116] Subsequently, for each of the plurality of additional design data corresponding to each of the plurality of hardware structure information, a first minor ID value based on the classification result from the first perspective is assigned (second assignment step S125). In the present embodiment, in the second assignment step S125, the learning unit 126 of the classification engine learning device 120 assigns a first minor ID value based on the classification result from the first perspective to each of the plurality of additional graph objects corresponding to each of the plurality of hardware structure information.

[0117] Subsequently, the learning unit 126 causes the neural network to learn using each of a plurality of additional design data as an input, in the same manner as the learning unit 26 of the classification engine learning device 20 according to the first embodiment (learning step S126). In the learning step S126, the learning unit 126 causes the neural network to learn using each of the plurality of additional design data as an input so as to infer one major ID value corresponding to the additional design data among one or more major ID values. In the learning step S126, the learning unit 126 further causes the neural network to learn so as to infer a first minor ID value corresponding to the additional design data that is input to the neural network among the plurality of additional design data.

[0118] In the present embodiment, in the learning step S126, the learning unit 126 causes the neural network to learn using each of a plurality of additional graph objects as an input. In the learning step S126, the learning unit 126 further causes the neural network to learn so as to infer a first minor ID value corresponding to the additional graph object that is input to the neural network among the plurality of additional graph objects.

[0119] In addition to the major ID value, the learning unit 126 may cause the neural network to learn so as to infer a first minor ID value corresponding to the hardware structure information that is input to the neural network among the plurality of hardware structure information.

[0120] In the learning step S126, the learning unit 126 may cause the neural network to learn so as to infer a second minor ID value corresponding to the additional design data that is input to the neural network among the plurality of additional graph objects. Thereby, classification focusing on further different features becomes possible.

[0121] Note that in the present embodiment, three or more minor ID values may be assigned based on the classification results from three or more viewpoints, and the neural network may be caused to learn so as to infer three or more minor ID values.

[0122] According to the classification engine learning method of the semiconductor integrated circuit according to the present embodiment, in addition to the classification focusing on the characteristics of the base design data based on the major ID value, it is also possible to perform classification focusing on the characteristics common to the additional graph objects based on a plurality of base design data.

[0123] [2-3. Semiconductor integrated circuit classification method] The semiconductor integrated circuit classification method according to the present embodiment will be described with reference to FIG. 15. FIG. 15 is a flowchart showing the flow of the semiconductor integrated circuit classification method according to the present embodiment. The semiconductor integrated circuit classification method according to the present embodiment is executed by the classification engine 140.

[0124] As shown in FIG. 15, first, the first allocation step S40 is executed in the same manner as the semiconductor integrated circuit classification method according to Embodiment 1.

[0125] Subsequently, a neural network that has been learned by the classification engine learning method of the semiconductor integrated circuit according to the present embodiment described above is prepared (preparation step S141). In the present embodiment, the neural network is learned in the classification engine learning device 120.

[0126] Subsequently, the unclassified base design data acquisition step S42 is executed in the same manner as the semiconductor integrated circuit classification method according to Embodiment 1.

[0127] Subsequently, the inference unit 144 of the classification engine 140 inputs the unclassified base design data into the learned neural network, infers one major ID value corresponding to the unclassified base design data among one or more major ID values, and infers the first minor ID value corresponding to the unclassified base design data (inference step S144). In the present embodiment, in inference step S144, the inference unit 144 inputs the unclassified base graph object into the learned neural network, infers one major ID value corresponding to the unclassified base graph object among one or more major ID values, and infers the first minor ID value corresponding to the unclassified base graph object. Note that in inference step S144, the first minor ID value corresponding to the unclassified hardware structure information may be inferred.

[0128] According to the semiconductor integrated circuit classification method according to the present embodiment, in the semiconductor integrated circuit design apparatus 60, the initial layout data can include layout metadata including the first minor ID value inferred by the classification engine 140 and the like. Thereby, the semiconductor integrated circuit design apparatus 60 can perform layout design based on more detailed layout constraints and layout scripts. Therefore, calculation resources and time can be further reduced, and the layout quality can be improved.

[0129] [2-4. Semiconductor Integrated Circuit Design Method] The semiconductor integrated circuit design method according to the present embodiment will be described with reference to FIG. 16. FIG. 16 is a flowchart showing the flow of the semiconductor integrated circuit design method according to the present embodiment. The semiconductor integrated circuit design method according to the present embodiment is executed by the semiconductor integrated circuit design apparatus 60.

[0130] In the present embodiment, first, the unclassified hardware structure information is classified by inferring one major ID value and the first minor ID value corresponding to the unclassified hardware structure information by the semiconductor integrated circuit classification method described above (classification step S161).

[0131] Subsequently, the semiconductor integrated circuit design apparatus 60 creates layout data based on unclassified hardware structure information based on one piece of hardware structure information among a plurality of pieces of hardware structure information corresponding to a combination of one major ID value and a first minor ID value, and design data related to the layout data created based on the one piece of hardware structure information (layout data creation step S162).

[0132] As a result, the same effects as those of the semiconductor integrated circuit design method according to the first embodiment are achieved. Further, in the present embodiment, the initial layout data used in the semiconductor integrated circuit design apparatus 60 can include layout metadata including the first minor ID value inferred by the classification engine 140 and the like. Thereby, the semiconductor integrated circuit design apparatus 60 can perform layout design based on more detailed layout constraints and a layout script. Therefore, calculation resources and time can be further reduced, and the layout quality can be improved.

[0133] (Modifications, etc.) As described above, the classification engine learning method of the semiconductor integrated circuit according to the present disclosure and the like have been described based on each embodiment. However, the present disclosure is not limited to these embodiments. As long as the gist of the present disclosure is not deviated from, various modifications conceived by those skilled in the art applied to each embodiment, and other forms constructed by combining some components in each embodiment are also included in the scope of the present disclosure.

[0134] For example, in the second embodiment, the configuration using the first minor ID value and the second minor ID value has been described. However, a combination of a plurality of minor ID values based on the classification results from these multiple viewpoints may be assigned to each graph object as one minor ID value.

[0135] In each of the above-described embodiments, the example using a graph object as the object of learning and inference has been mainly described. However, the object of learning and inference is not limited to the graph object. For example, the object of learning and inference may be design data that can infer a graph object, or design data corresponding to each of the hardware structure information.

[0136] Regarding the design data in this case, it will be described with reference to FIGS. 17 to 21. Each of FIGS. 17 and 18 is a diagram showing an example of design data. FIG. 19 is a diagram showing an example of base design data. Each of FIGS. 20 and 21 is a diagram showing an example of partial design data.

[0137] The design data that is the object of learning and inference may be, for example, a list of components of an LSI based on a certain architecture as shown in FIG. 17. And as the input during learning, as shown in FIG. 18, each component is encoded, and for example, as shown in FIG. 19, the number of components as a feature amount can be used as base design data as a feature amount. For example, in FIG. 19, the code of the component ALU-typeA is shown as 0000, and the number thereof is shown as 0001.

[0138] Examples of partial design data generated based on the base design data as shown in FIG. 19 are those shown in FIGS. 20 and 21. In the example shown in FIG. 20, some of the components shown in FIG. 19 (such as the components ALU-typeA and ALU-typeC) are deleted. Also, in the example shown in FIG. 21, the number of components is further reduced from the example shown in FIG. 20. For example, the number of the component ALU-typeB shown in FIG. 20 was 0010, whereas the number of the component ALU-typeB shown in FIG. 21 is reduced to 0001.

[0139] Even when using these base design data and partial base design data, learning and inference are possible in the same manner as in each of the above-described embodiments.

[0140] In this case, the neural networks used in the learning units 26, 126, the inference units 44, 144, and the learning steps S26, S126, and the inference steps S44, S144 in each of the above embodiments may not be graph neural networks, but may be general convolutional networks, multi-layer perceptrons, or the like.

[0141] Also, the following forms may also be included within the scope of one or more aspects of the present disclosure.

[0142] (1) Some of the components constituting the semiconductor integrated circuit design system 10 described above may be a computer system composed of a microprocessor, ROM, RAM, hard disk unit, display unit, keyboard, mouse, etc. A computer program is stored in the RAM or the hard disk unit. The microprocessor operates according to the computer program to achieve its functions. Here, the computer program is composed of a combination of a plurality of instruction codes indicating instructions for the computer to achieve a predetermined function.

[0143] (2) Some of the components constituting the semiconductor integrated circuit design system 10 described above may be assumed to be composed of one system LSI (Large Scale Integration). A system LSI is a super multi-functional LSI manufactured by integrating a plurality of components on one chip, and specifically, is a computer system including a microprocessor, ROM, RAM, etc. A computer program is stored in the RAM. The microprocessor operates according to the computer program, and thus the system LSI achieves its functions.

[0144] (3) Some of the components constituting the semiconductor integrated circuit design system 10 described above may be composed of IC cards or single modules that are detachable from each device. The IC card or the module is a computer system composed of a microprocessor, ROM, RAM, etc. The IC card or the module may include the above-mentioned ultra-multi-functional LSI. When the microprocessor operates according to a computer program, the IC card or the module achieves its function. This IC card or this module may have tamper resistance.

[0145] (4) Also, some of the components constituting the semiconductor integrated circuit design system 10 described above may be recorded on a computer-readable recording medium for the computer program or the digital signal, such as a flexible disk, a hard disk, a CD-ROM, an MO, a DVD, a DVD-ROM, a DVD-RAM, a BD (Blu-ray (registered trademark) Disc), a semiconductor memory, etc. It may also be the digital signal recorded on these recording media.

[0146] Also, some of the components constituting the semiconductor integrated circuit design system 10 described above may transmit the computer program or the digital signal via a telecommunication line, a wireless or wired communication line, a network represented by the Internet, data broadcasting, etc.

[0147] (5) The present disclosure may be the method shown above. It may also be a computer program for realizing these methods by a computer, or a digital signal composed of the computer program. Furthermore, the present disclosure may be realized as a non-temporary computer-readable recording medium such as a CD-ROM on which the computer program is recorded.

[0148] (6) Further, the present disclosure may be a computer system including a microprocessor and a memory, where the memory stores the computer program, and the microprocessor operates according to the computer program.

[0149] (7) Further, it may be implemented by another independent computer system by recording and transferring the program or the digital signal to the recording medium, or by transferring the program or the digital signal via the network or the like.

[0150] (8) The above embodiments and the above modifications may be combined respectively.

[0151] (Supplementary Note) Also, the following technology is disclosed by the above description.

[0152] (Technology 1) A method for learning a classification engine of a semiconductor integrated circuit, including a base design data acquisition step of acquiring base design data corresponding to each of one or more pieces of different hardware structure information describing the semiconductor integrated circuit, a generation step of generating a learning design data group including a plurality of additional design data based on the base design data, and a learning step of causing a neural network to learn with each of the plurality of additional design data as an input. Each of the plurality of additional design data is different from each other and is a part of the base design data and includes partial base design data different from the base design data. One major ID value among one or more different major ID values is assigned to each of the one or more pieces of hardware structure information. In the learning step, the neural network is caused to learn with each of the plurality of additional design data as an input so as to infer one major ID value corresponding to the additional design data among the one or more major ID values. A method for learning a classification engine of a semiconductor integrated circuit.

[0153] (Technique 2) In the base design data acquisition step, as the base design data, a base graph object in graph object format is acquired. In the generation step, the learning design data group including a plurality of additional graph objects in graph object format is generated as the plurality of additional design data. Each of the plurality of additional graph objects is different from each other and is a part of the base graph object, and includes a partial base graph object different from the base graph object as the partial base design data. The classification engine learning method for a semiconductor integrated circuit according to Technique 1.

[0154] (Technique 3) The base graph object includes a plurality of base nodes and one or more base edges. Each of the plurality of base nodes corresponds to a hardware instance that realizes a function represented by hardware structure information corresponding to the base graph object among the one or more hardware structure information. Each of the one or more base edges corresponds to a connection part connected to the hardware instance. The classification engine learning method for a semiconductor integrated circuit according to Technique 2.

[0155] (Technique 4) The partial base graph object includes a plurality of partial nodes, and the number of the plurality of partial nodes is more than half of the number of the plurality of base nodes. The classification engine learning method for a semiconductor integrated circuit according to Technique 3.

[0156] (Technique 5) The plurality of additional graph objects include a combined graph object of the partial base graph object and a noise graph object, and the number of nodes of the noise graph object is less than the number of the partial nodes of the partial base graph object. The classification engine learning method for a semiconductor integrated circuit according to Technique 4.

[0157] (Technique 6) The one or more hardware structure information includes a plurality of hardware structure information. The classification engine learning method for a semiconductor integrated circuit according to any one of Techniques 1 to 5.

[0158] (Technique 7) For each of the plurality of additional design data corresponding to each of the plurality of hardware structure information, a first minor ID value based on the classification result from a first perspective is assigned. In the learning step, further, the neural network is trained to infer the first minor ID value corresponding to the additional design data that is input to the neural network among the plurality of additional design data. The method for learning a classification engine of a semiconductor integrated circuit according to Technique 6

[0159] (Technique 8) In the generation step, a learning design data group including a plurality of additional graph objects in the form of graph objects is generated as the plurality of additional design data. Each of the plurality of additional graph objects includes a plurality of additional nodes and one or more additional edges. The first perspective is related to the features of the plurality of additional nodes and one or more additional edges. The method for learning a classification engine of a semiconductor integrated circuit according to Technique 7

[0160] (Technique 9) In the generation step, a learning design data group including a plurality of additional graph objects in the form of graph objects is generated as the plurality of additional design data. For each of the plurality of additional graph objects corresponding to each of the plurality of hardware structure information, a second minor ID value based on the classification result from a second perspective different from the first perspective is assigned. In the learning step, the neural network is trained to infer the second minor ID value corresponding to the additional graph object that is input to the neural network among the plurality of additional graph objects. The method for learning a classification engine of a semiconductor integrated circuit according to Technique 7

[0161] (Technique 10) In the generation step, the plurality of base nodes of the base graph object are classified into a plurality of groups including a first group and a second group based on a first feature amount of the plurality of base nodes, the partial base graph object includes a plurality of partial nodes, and the plurality of partial nodes included in the partial base graph object include base nodes included in the first group and base nodes included in the second group among the plurality of base nodes included in the base graph object, and a representative value of the first feature amount is included in a range of the first feature amount corresponding to the first group. The semiconductor integrated circuit classification engine learning method according to any one of Techniques 3 to 5.

[0162] (Technique 11) The representative value is the median value, average value, or mode value of the first feature amount. The semiconductor integrated circuit classification engine learning method according to Technique 10.

[0163] (Technique 12) The plurality of base nodes include one or more first base nodes, and each of the one or more first base nodes has, as a feature amount, a degree of complexity of an operation in the hardware instance corresponding to the first base node. The semiconductor integrated circuit classification engine learning method according to any one of Techniques 3 to 5.

[0164] (Technique 13) The plurality of base nodes include one or more second base nodes, and each of the one or more second base nodes has, as a feature amount, the number of inputs to the second base node. The semiconductor integrated circuit classification engine learning method according to any one of Techniques 3 to 5.

[0165] (Technique 14) The one or more base edges include one or more first base edges, and each of the one or more first base edges has, as a feature amount, the amount of information transmitted by the connection portion corresponding to the first base edge. The semiconductor integrated circuit classification engine learning method according to any one of Techniques 3 to 5.

[0166] (Technique 15) Each of the one or more pieces of hardware structure information is a semiconductor integrated circuit classification engine learning method described in any one of Techniques 1 to 14, which is a gate-level netlist.

[0167] (Technique 16) The plurality of base nodes include one or more third base nodes, and each of the one or more third base nodes has, as a feature amount, the number of base nodes through which the input to the third base node passes among the plurality of base nodes, which is a semiconductor integrated circuit classification engine learning method described in any one of Techniques 3 to 5.

[0168] (Technique 17) A semiconductor integrated circuit classification method, including: a preparation step of preparing the neural network learned by the semiconductor integrated circuit classification engine learning method described in any one of Techniques 1 to 16; an unclassified base design data acquisition step of acquiring unclassified base design data corresponding to unclassified hardware structure information different from the one or more pieces of hardware structure information; and an inference step of inferring, by inputting the unclassified base design data into the learned neural network, one major ID value corresponding to the unclassified base design data among the one or more major ID values, wherein the one or more pieces of hardware structure information include a plurality of pieces of hardware structure information, which is a semiconductor integrated circuit classification method.

[0169] (Technique 18) A semiconductor integrated circuit classification method using the neural network learned by the semiconductor integrated circuit classification engine learning method described in Technique 7, including: an unclassified base design data acquisition step of acquiring unclassified base design data corresponding to unclassified hardware structure information different from the one or more pieces of hardware structure information; and an inference step of inferring, by inputting the unclassified base design data into the learned neural network, one major ID value corresponding to the unclassified base design data among the one or more major ID values, and inferring the first minor ID value corresponding to the unclassified base design data, which is a semiconductor integrated circuit classification method.

[0170] (Technique 19) A semiconductor integrated circuit classification method, comprising: an assignment step of assigning, to each of the plurality of hardware structure information that describes a semiconductor integrated circuit and layout data of the semiconductor integrated circuit created based on each of the plurality of hardware structure information, one major ID value out of a plurality of different major ID values; an unclassified base design data acquisition step of acquiring unclassified base design data corresponding to unclassified hardware structure information different from the plurality of hardware structure information; and an inference step of inputting the unclassified base design data to a learned neural network to infer one major ID value corresponding to the unclassified base design data out of the plurality of major ID values.

[0171] (Technique 20) The semiconductor integrated circuit classification method according to Technique 19, wherein, in the unclassified base design data acquisition step, an unclassified base graph object in graph object form is acquired as the unclassified base design data.

[0172] (Technique 21) The neural network is learned by a classification engine learning method, and the classification engine learning method includes: a base design data acquisition step of acquiring base design data corresponding to each of the plurality of hardware structure information; a generation step of generating a learning design data group including a plurality of additional design data based on the base design data; and a learning step of causing the neural network to learn with each of the plurality of additional design data as an input. Each of the plurality of additional design data is different from each other and includes partial base design data that is a part of the base design data and different from the base design data. In the learning step, the neural network is caused to learn with each of the plurality of additional design data as an input so as to infer one major ID value corresponding to the additional design data out of the plurality of major ID values. The semiconductor integrated circuit classification method according to Technique 19.

[0173] A semiconductor integrated circuit design method including: a classification step of classifying the unclassified hardware structure information by inferring the one major ID value by the semiconductor integrated circuit classification method described in Technique 19; and a layout data creation step of creating layout data based on the unclassified hardware structure information based on one piece of hardware structure information to which the one major ID value is assigned among the plurality of pieces of hardware structure information and design data related to the layout data created based on the one piece of hardware structure information.

[0174] (Technique 23) For each of the plurality of pieces of hardware structure information, a first minor ID value based on the classification result from the first perspective is assigned, and in the inference step, further, the semiconductor integrated circuit classification method described in Technique 19 for inferring the first minor ID value corresponding to the unclassified hardware structure information.

[0175] (Technique 24) A semiconductor integrated circuit design method including: a classification step of classifying the unclassified hardware structure information by inferring the one major ID value and the first minor ID value corresponding to the unclassified hardware structure information by the semiconductor integrated circuit classification method described in Technique 23; and a layout data creation step of creating layout data based on the unclassified hardware structure information based on one piece of hardware structure information among the plurality of pieces of hardware structure information corresponding to the combination of the one major ID value and the first minor ID value and design data related to the layout data created based on the one piece of hardware structure information.

Industrial Applicability

[0176] The present disclosure can be used when designing a layout of a semiconductor integrated circuit based on hardware structure information describing the semiconductor integrated circuit.

Explanation of Signs

[0177] 10, 110 Semiconductor integrated circuit design system 20. 120 Classification Engine Learning Device 22. 42 Acquisition Unit 24 Generation Unit 26. 126 Learning Unit 40. 140 Classification Engine 44. 144 Inference Unit 60 Semiconductor Integrated Circuit Design Device 80 Database 1000 Computer 1001 Input Device 1002 Output Device 1003 CPU 1004 Built-in Storage 1005 RAM 1007 Reading Device 1008 Transceiver 1009 Bus E11, E21, E22, E23, E24, E31, E32, E33, E41, E42 Base Edge N11, N21, N22, N23, N24, N31, N32, N33, N41, N42 Base Node

Claims

1. A classification engine training method for a semiconductor integrated circuit, comprising: a base design data acquisition step of acquiring base design data corresponding to each of one or more pieces of different hardware structure information describing the semiconductor integrated circuit; A generating step of generating a learning design data group including a plurality of additional design data based on the base design data; a learning step of causing a neural network to learn using each of the plurality of additive design data as an input; each of the plurality of additional design data is different from each other, and includes partial base design data that is a part of the base design data and is different from the base design data; each of the one or more pieces of hardware configuration information is assigned one major ID value among one or more major ID values ​​different from each other; In the learning step, each of the plurality of additive design data is input, and the neural network is trained to infer one measure ID value corresponding to the additive design data among the one or more measure ID values. A method for training a classification engine for semiconductor integrated circuits.

2. In the base design data acquisition step, a base graph object in a graph object format is acquired as the base design data; In the generating step, the learning design data group is generated, the learning design data group including a plurality of additional graph objects in a graph object format as the plurality of additional design data; Each of the plurality of additional graph objects is different from the others, and includes a partial base graph object, which is a part of the base graph object and is different from the base graph object, as the partial base design data.

2. The classification engine learning method for a semiconductor integrated circuit according to claim 1.

3. the base graph object includes a plurality of base nodes and one or more base edges; each of the plurality of base nodes corresponds to a hardware instance that realizes a function represented by hardware structure information corresponding to the base graph object among the one or more pieces of hardware structure information; Each of the one or more base edges corresponds to a connection that is connected to the hardware instance.

3. The classification engine learning method for a semiconductor integrated circuit according to claim 2.

4. the partial base graph object includes a plurality of partial nodes; The number of the partial nodes is greater than half the number of the base nodes.

4. The classification engine learning method for a semiconductor integrated circuit according to claim 3.

5. the plurality of additional graph objects include a combined graph object of the partial base graph object and a noise graph object; The number of nodes of the noise graph object is less than the number of the partial nodes of the partial base graph object.

5. The classification engine learning method for a semiconductor integrated circuit according to claim 4.

6. The one or more pieces of hardware configuration information include a plurality of pieces of hardware configuration information.

2. The classification engine learning method for a semiconductor integrated circuit according to claim 1.

7. A first minor ID value based on a classification result from a first viewpoint is assigned to each of the plurality of additive design data corresponding to each of the plurality of hardware structure information; The learning step further includes training the neural network to infer the first minor ID value corresponding to additive design data among the plurality of additive design data that is input to the neural network.

7. The classification engine learning method for a semiconductor integrated circuit according to claim 6.

8. In the generating step, the learning design data group is generated, the learning design data group including a plurality of additional graph objects in a graph object format as the plurality of additional design data; each of the plurality of additional graph objects includes a plurality of additional nodes and one or more additional edges; The first viewpoint is related to features of the plurality of additional nodes and one or more additional edges.

8. The classification engine learning method for a semiconductor integrated circuit according to claim 7.

9. In the generating step, the learning design data group is generated, the learning design data group including a plurality of additional graph objects in a graph object format as the plurality of additional design data; A second minor ID value is assigned to each of the plurality of additional graph objects corresponding to each of the plurality of pieces of hardware configuration information based on a classification result from a second perspective different from the first perspective; In the learning step, the neural network is trained to infer the second minor ID value corresponding to an additional graph object among the plurality of additional graph objects that is an input to the neural network.

8. The classification engine learning method for a semiconductor integrated circuit according to claim 7.

10. In the generating step, classifying the plurality of base nodes of the base graph object into a plurality of groups including a first group and a second group based on first feature amounts of the plurality of base nodes; the partial base graph object includes a plurality of partial nodes; the plurality of partial nodes included in the partial base graph object include, among the plurality of base nodes included in the base graph object, a base node included in the first group and a base node included in the second group; The range of the first feature amount corresponding to the first group includes a representative value of the first feature amount.

4. The classification engine learning method for a semiconductor integrated circuit according to claim 3.

11. The representative value is a median, an average, or a mode of the first feature amount. The classification engine learning method for a semiconductor integrated circuit according to claim 10.

12. the plurality of base nodes includes one or more first base nodes; Each of the one or more first base nodes has a characteristic representing a degree of complexity of a calculation in the hardware instance corresponding to the first base node.

4. The classification engine learning method for a semiconductor integrated circuit according to claim 3.

13. the plurality of base nodes includes one or more second base nodes; Each of the one or more second base nodes has a number of inputs to the second base node as a feature.

4. The classification engine learning method for a semiconductor integrated circuit according to claim 3.

14. The one or more base edges include one or more first base edges, and each of the one or more first base edges has an amount of information transmitted by the connection portion corresponding to the first base edge as a feature.

4. The classification engine learning method for a semiconductor integrated circuit according to claim 3.

15. Each of the one or more pieces of hardware structure information is a gate level netlist.

2. The classification engine learning method for a semiconductor integrated circuit according to claim 1.

16. the plurality of base nodes includes one or more third base nodes; Each of the one or more third base nodes has, as a feature, the number of base nodes through which an input to the third base node passes among the plurality of base nodes.

4. The classification engine learning method for a semiconductor integrated circuit according to claim 3.

17. A method for classifying semiconductor integrated circuits, comprising the steps of: A preparation step of preparing the neural network that has been trained by the classification engine training method for a semiconductor integrated circuit according to claim 1; an unclassified base design data acquisition step of acquiring unclassified base design data corresponding to unclassified hardware structure information different from the one or more pieces of hardware structure information; an inference step of inferring one measure ID value corresponding to the unclassified base design data from among the one or more measure ID values ​​by inputting the unclassified base design data to the trained neural network; The one or more pieces of hardware configuration information include a plurality of pieces of hardware configuration information. Classification method for semiconductor integrated circuits.

18. A semiconductor integrated circuit classification method using the neural network trained by the semiconductor integrated circuit classification engine training method according to claim 7, an unclassified base design data acquisition step of acquiring unclassified base design data corresponding to unclassified hardware structure information different from the one or more pieces of hardware structure information; and an inference step of inferring one major ID value corresponding to the unclassified base design data among the one or more major ID values ​​by inputting the unclassified base design data to the trained neural network, and inferring the first minor ID value corresponding to the unclassified base design data. Classification method for semiconductor integrated circuits.

19. A method for classifying semiconductor integrated circuits, comprising the steps of: an assignment step of assigning one major ID value among a plurality of mutually different major ID values ​​to each of the plurality of pieces of hardware structure information based on a plurality of mutually different pieces of hardware structure information describing a semiconductor integrated circuit and layout data of the semiconductor integrated circuit created based on each of the plurality of pieces of hardware structure information; an unclassified base design data acquisition step of acquiring unclassified base design data corresponding to unclassified hardware structure information different from the plurality of pieces of hardware structure information; and an inference step of inferring one measure ID value corresponding to the unclassified base design data from among the plurality of measure ID values ​​by inputting the unclassified base design data to a trained neural network. Semiconductor integrated circuit classification method.

20. In the unclassified base design data acquisition step, an unclassified base graph object in a graph object format is acquired as the unclassified base design data.

20. The method for classifying semiconductor integrated circuits according to claim 19.

21. the neural network has been trained using a classification engine training method; The classification engine training method includes: a base design data acquisition step of acquiring base design data corresponding to each of the plurality of pieces of hardware structure information; A generating step of generating a learning design data group including a plurality of additional design data based on the base design data; a learning step of causing the neural network to learn using each of the plurality of additive design data as an input; each of the plurality of additional design data is different from each other, and includes partial base design data that is a part of the base design data and is different from the base design data; In the learning step, each of the plurality of additive design data is input, and the neural network is trained to infer one measure ID value corresponding to the additive design data among the plurality of measure ID values.

20. The method for classifying semiconductor integrated circuits according to claim 19.

22. A classification step of classifying the unclassified hardware structure information by inferring the one major ID value by the semiconductor integrated circuit classification method according to claim 19; and a layout data creating step of creating layout data based on the unclassified hardware structure information, based on one piece of hardware structure information to which the one major ID value is assigned among the plurality of pieces of hardware structure information, and on design data related to layout data created based on the one piece of hardware structure information. A semiconductor integrated circuit design method.

23. a first minor ID value based on a classification result from a first perspective is assigned to each of the plurality of pieces of hardware configuration information; The inferring step further comprises inferring the first minor ID value corresponding to the unclassified hardware configuration information.

20. The method for classifying semiconductor integrated circuits according to claim 19.

24. A classification step of classifying the unclassified hardware structure information by inferring the one major ID value and the first minor ID value corresponding to the unclassified hardware structure information according to the semiconductor integrated circuit classification method of claim 23; and a layout data creating step of creating layout data based on the unclassified hardware structure information based on one piece of hardware structure information among the plurality of pieces of hardware structure information corresponding to the combination of the one major ID value and the first minor ID value and on design data related to layout data created based on the one piece of hardware structure information. A semiconductor integrated circuit design method.

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