Display substrate and display device

Abstract

To provide a display substrate and a display device.SOLUTION: A base substrate of a display substrate includes a display area, a plurality of pixel units is located in the display area, the pixel unit includes a pixel circuit (1121) having a first pixel circuit (1121a) and a second pixel circuit (1121b) which are adjacent along a first direction, an initialization signal line (113) extends in the first direction and provides an initialization signal for the first pixel circuit and the second pixel circuit, a first control signal line (114A) extends in the first direction and provides a gate signal for the first pixel circuit and the second pixel circuit (1121b), a light emission control signal line (115) extends in the first direction and provides a light emission control signal for the first pixel circuit (1121a) and the second pixel circuit (1121b), and the initialization signal line (113) is located on a side of the light emission control signal line (115) away from the first control signal line (114A), extends in the first direction, and is provided in a spaced and segmented manner.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and more specifically to display substrates and display devices.

Background Art

[0002] In related technologies, the requirements of users for portable terminal devices are becoming increasingly high. Being lighter, thinner, brighter, and more energy-efficient still remains the requirements of most users. However, due to the self-luminous feature of the Organic light-emitting diode (OLED) display panel, it can realize the display function without a backlight and has become a well-received display panel that is lighter and thinner. Also, the requirements for display panels in the current market are not only for flat surfaces but also for irregular shapes, curved surfaces, transparent displays, etc. The OLED display panel will become the most widely used display technology in the future. In particular, the Active-matrix organic light-emitting diode (AMOLED) display panel requires a relatively complex pixel compensation circuit in order to prevent the problem of display unevenness caused by the difference in the drive transistor Vth during the process. How to realize the performance of the entire circuit within the limited space is an issue waiting to be solved.

Summary of the Invention

Problems to be Solved by the Invention

[0003] Embodiments of the present disclosure provide a display substrate and a display device. Embodiments of the present disclosure provide a display substrate including a base substrate, a plurality of pixel units, an initialization signal line, a first control signal line, and a light emission control signal line. The base substrate includes a display area, and the plurality of pixel units are located in the display area and include pixel circuits having a first pixel circuit and a second pixel circuit adjacent to each other along a first direction. The initialization signal line extends in the first direction and is configured to provide an initialization signal to the first pixel circuit and the second pixel circuit. The first control signal line extends in the first direction and is configured to provide a gate signal to the first pixel circuit and the second pixel circuit. The light emission control signal line extends in the first direction and is configured to provide a light emission control signal to the first pixel circuit and the second pixel circuit. The initialization signal line is located on a side away from the first control signal line of the light emission control signal line, extends in the first direction, and is provided in a segmented manner with an interval therebetween.

Means for Solving the Problems

[0004] In some embodiments, the display substrate further includes an initialization bus line located on a side away from the base substrate of the initialization signal line, and the initialization bus line and the initialization signal line are electrically connected.

[0005] In some embodiments, the initialization bus includes a plurality of main body portions, a plurality of connection portions, and a plurality of branch portions. The plurality of main body portions extend in the first direction and are provided at intervals along the second direction. The plurality of main body portions are configured to provide the initialization signal to corresponding plurality of the initialization signal lines that extend in the first direction and are provided in a segmented manner with an interval therebetween. The plurality of connection portions extend in the second direction and connect two adjacent main body portions. The plurality of branch portions are connected to at least one of two adjacent main body portions. The plurality of connection portions and the plurality of branch portions are provided at intervals alternately along the first direction. The plurality of branch portions are located between two adjacent main body portions and are configured to provide the initialization signal to corresponding plurality of the initialization signal lines that extend in the first direction and are provided in a segmented manner with an interval therebetween.

[0006] In some embodiments, the display substrate further includes a second control signal line located on a side away from the emission control signal line of the initialization signal line, the second control signal line extends in the first direction, and is configured to provide a reset control signal to the first pixel circuit and the second pixel circuit.

[0007] In some embodiments, the display substrate includes a plurality of first power supply lines, the first power supply lines extend in the second direction, are provided at intervals along the first direction, and are configured to provide a first power supply signal to the pixel circuit.

[0008] In some embodiments, the pixel circuit includes an emission control transistor, a gate of the emission control transistor is connected to the emission control signal line, the emission control transistor includes a first pole and a second pole, and the second pole and the first pole of the emission control transistor are respectively located on a first side and a second side across the emission control signal line.

[0009] In some embodiments, the pixel circuit includes a driving transistor located on the second side of the emission control signal line, the driving transistor includes a first pole and a second pole, the first pole of the driving transistor is connected to the first power supply line, and the second pole of the driving transistor is connected to the first pole of the emission control transistor.

[0010] In some embodiments, the pixel circuit includes a first reset transistor located between the second control signal line and the emission control signal line, the second control signal line is connected to a gate of the first reset transistor, the first reset transistor includes a first pole and a second pole, the first pole of the first reset transistor is connected to a gate of the driving transistor, and the second pole of the first reset transistor is connected to the initialization signal line.

[0011] In some embodiments, the display substrate includes a plurality of data lines, the plurality of data lines extend in the second direction and are provided at intervals along the first direction, and are configured to provide data signals to the pixel circuit.

[0012] In some embodiments, the pixel circuit includes a storage capacitor, a data writing transistor, and a first compensation transistor. The first control signal line is connected to the gate of the data writing transistor and the gate of the first compensation transistor respectively. The data writing transistor includes a first pole and a second pole. The first pole of the data writing transistor is connected to the data line. The storage capacitor includes a first pole and a second pole. The first pole of the storage capacitor is connected to the second pole of the data writing transistor. The second pole of the storage capacitor is connected to the gate of the driving transistor. The first compensation transistor includes a first pole and a second pole. The first pole of the first compensation transistor is connected to the gate of the driving transistor. The second pole of the first compensation transistor is connected to the second pole of the driving transistor.

[0013] In some embodiments, the initialization signal line is provided at intervals in the same layer as the first pole of the storage capacitor.

[0014] In some embodiments, the data writing transistor and the first compensation transistor are located on the side closer to the emission control signal line of the first control signal line.

[0015] In some embodiments, the pixel circuit includes a second compensation transistor. The emission control signal line is connected to the gate of the second compensation transistor. The second compensation transistor includes a first pole located on the first side of the emission control signal line. The first pole of the second compensation transistor is connected to the second pole of the first reset transistor.

[0016] In some embodiments, the display substrate includes a first connection electrode extending in the second direction, and the first connection electrode connects the gate of the driving transistor, the first pole of the first compensation transistor, and the first pole of the second compensation transistor.

[0017] In some embodiments, the pixel circuit includes a second reset transistor and a third reset transistor located between the second control signal line and the light emission control signal line. The second control signal line is connected to the gate of the second reset transistor, the light emission control signal line is connected to the gate of the third reset transistor. The second reset transistor includes a first pole and a second pole. The first pole of the second reset transistor is connected to the second pole of the data writing transistor, and the second pole of the second reset transistor is connected to the initialization signal line. The third reset transistor includes a first pole and a second pole. The first pole of the third reset transistor is connected to the second pole of the data writing transistor, and the second pole of the third reset transistor is connected to the initialization signal line.

[0018] In some embodiments, the display substrate includes a second connection electrode extending in the second direction, and the second connection electrode connects the first pole of the third reset transistor and the second pole of the data writing transistor.

[0019] In some embodiments, the first connection electrode, the second connection electrode, the data line, and the first power supply line are provided in the same layer.

[0020] In some embodiments, the display substrate further includes a light emitting element. The second pole of the light emission control transistor is connected to the first pole of the light emitting element, and the light emission control bus line is provided at an interval in the same layer as the first pole of the light emitting element.

[0021] In some embodiments, the pixel circuit includes a fourth reset transistor located between the second control signal line and the light emission control signal line. The second control signal line is connected to the gate of the fourth reset transistor. The fourth reset transistor includes a first pole and a second pole. The first pole of the fourth reset transistor is connected to the first pole of the light emitting element, and the second pole of the fourth reset transistor is connected to the initialization signal line.

[0022] Embodiments of the present disclosure further provide a display device including the display substrate described in any of the above embodiments.

[0023] Additional aspects and advantages of embodiments of the present disclosure will be shown in part in the following description, will become apparent in part from the following description, or will be understood by the practice of the embodiments of the present disclosure.

[0024] The above and / or additional aspects and advantages of the present disclosure will be apparent and will be easily understood from the description of the embodiments made in conjunction with the following drawings.

Brief Description of the Drawings

[0025]

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Embodiments for Carrying Out the Invention

[0026] Hereinafter, embodiments of the present disclosure will be described in detail. Examples of the embodiments are shown in the drawings, and throughout the drawings, the same or similar reference numerals denote the same or similar elements, or elements having the same or similar functions. The embodiments described below with reference to the drawings are exemplary only and are merely for explaining the present disclosure, and should not be construed as limiting the present disclosure.

[0027] In the description of the present disclosure, the orientation or positional relationship indicated by terms such as "upper", "lower", "left", "right", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for facilitating the description of the present disclosure and simplifying the explanation, and does not indicate or imply that the shown device or element must have a specific orientation and be configured and operated in a specific orientation. Therefore, it should not be construed as limiting the present disclosure. Also, the terms "first" and "second" are merely for the purpose of explanation and should not be construed as indicating or implying relative importance or implicitly indicating the number of the shown technical features. Therefore, the features limited by "first" and "second" may explicitly or implicitly include one or more of the above features. In the description of the present disclosure, "a plurality" means two or more unless otherwise specified.

[0028] The following disclosure provides many different embodiments or examples for implementing different structures of the present disclosure. To simplify the present disclosure, the members and arrangements of specific examples are described below. Of course, these are merely examples and are not intended to limit the present disclosure. Also, for the sake of brevity and clarity, reference numerals and / or reference letters may be repeated in different examples, and they do not themselves indicate the relationships between the various embodiments and / or arrangements being discussed. Furthermore, although the present disclosure provides examples of various specific processes and materials, those skilled in the art can recognize that other processes may be applied and / or other materials may be used.

[0029] The resolution of an organic light-emitting diode (OLED) display device is being increased to a high resolution such that as the pixel density (Pixels Per Inch, PPI) of the screen increases, the pixel size of the backplane circuit of the display device gradually becomes smaller. The design space for each individual pixel unit is becoming smaller and smaller. For example, the pixel circuit structure of one pixel unit in an organic light-emitting diode display panel may include a plurality of transistors, for example, seven or more transistors, and may include, for example, a 9T1C pixel circuit structure, but is not limited thereto. Since the width of the circuit wiring and the wiring pitch in the substrate circuit become smaller, the difficulty of the wiring layout increases accordingly. Embodiments of the present disclosure will be described by taking the 9T1C pixel circuit structure as an example.

[0030] Referring to FIGS. 1 to 5, a display substrate 110 according to an embodiment of the present disclosure includes a base substrate 111, a plurality of pixel units 112, an initialization signal line 113, a first control signal line 114A, and a light emission control signal line 115. The base substrate 111 includes a display area 1111, and the plurality of pixel units 112 are located in the display area 1111 and arranged in a matrix. Each pixel unit 112 includes a pixel circuit 1121 having a first pixel circuit 1121a and a second pixel circuit 1121b adjacent to each other along a first direction. The initialization signal line 113 extends in the first direction and is configured to provide an initialization signal Vinit to the first pixel circuit 1121a and the second pixel circuit 1121b. The first control signal line 114A extends in the first direction and is configured to provide a gate signal Sn to the first pixel circuit 1121a and the second pixel circuit 1121b. The light emission control signal line 115 extends in the first direction and is configured to provide a light emission control signal EM to the first pixel circuit 1121a and the second pixel circuit 1121b. Here, the initialization signal line 113 is located on a side away from the first control signal line 114A of the light emission control signal line 115, extends in the first direction, and is provided in a segmented manner with a space therebetween.

[0031] The display substrate 110 according to an embodiment of the present disclosure can be applied to the display device 100 according to an embodiment of the present disclosure, that is, the display device 100 according to an embodiment of the present disclosure can perform image display by the display substrate 110 according to an embodiment of the present disclosure.

[0032] In the display substrate 110 and the display device 100 of the present disclosure, by designing the initialization signal line 113 to be provided in a segmented manner with a space therebetween along the first direction, the space occupied by the initialization signal line 113 in the substrate is reduced, and it becomes easy to optimize the wiring layout of the display substrate 110 within the limited space to meet more performance requirements.

[0033] In some embodiments, the display device 100 may be a display device capable of image display such as a smartphone, a tablet, a smart band, a virtual reality device, a personal data terminal, a notebook computer, etc., but is not limited thereto. In the embodiment shown in FIG. 1, the display device 100 is a smartphone.

[0034] In some embodiments, the display substrate 110 includes a plurality of first power lines 116A. The first power lines 116A extend in the second direction and are provided at intervals along the first direction. The plurality of first power lines 116A are configured to provide a first power signal ELVDD to the pixel circuit 1121. Specifically, the first power signal ELVDD is a voltage signal at a constant high level.

[0035] In some embodiments, the display substrate 110 includes a plurality of data lines 117. The plurality of data lines 117 extend in the second direction and are provided at intervals along the first direction. The data lines 117 are configured to provide data signals to the pixel circuit 1121.

[0036] When the display substrate 110 performs display, one pixel may include a plurality of pixel units 112. Also, one pixel may include a plurality of pixel units 112 that emit light of different colors. For example, one pixel includes a pixel unit 112 that emits red light, a pixel unit 112 that emits green light, and a pixel unit 112 that emits blue light, but is not limited thereto. The number of pixel units 112 included in one pixel and the light emission status of each pixel unit 112 can be set as needed. The display device 100 can generate a corresponding data signal based on each pixel value in the image and provide the data signal to the corresponding pixel circuit 1121 via the data line 117.

[0037] In some embodiments, the display substrate 110 further includes a second control signal line 114B located on a side away from the light emission control signal line 115 of the initialization signal line 113. The second control signal line extends in the first direction and is configured to provide a reset control signal RESET to the first pixel circuit 1121a and the second pixel circuit 1121b.

[0038] Furthermore, the display substrate 110 includes a third pixel circuit 1121c and a fourth pixel circuit 1121d. The third pixel circuit 1121c is adjacent to the fourth pixel circuit 1121d along the first direction, the first pixel circuit 1121a is adjacent to the third pixel circuit 1121c along the second direction, and the second pixel circuit 1121b is adjacent to the fourth pixel circuit 1121d along the second direction. The second control signal line 114B may be configured to provide a gate signal Sn to the third pixel circuit 1121c and the fourth pixel circuit 1121d. Specifically, the second control signal line 114B can provide the reset control signal RESET to the first pixel circuit 1121a and the second pixel circuit 1121b while providing the gate signal Sn to the third pixel circuit 1121c and the fourth pixel circuit 1121d.

[0039] In some embodiments, the display substrate 110 includes a light emitting element 118, and the pixel circuit 1121 is connected to the light emitting element 118 to drive the light emitting element 118 to emit light. The display substrate 110 may include a second power supply line 119 configured to provide a second power supply signal ELVSS to the light emitting element 118.

[0040] Specifically, the second power supply signal ELVSS is a voltage signal at a certain low level. The first power supply signal ELVDD is greater than the second power supply signal ELVSS. The initialization signal Vinit is a voltage signal at a certain level, and its magnitude may be, for example, between the first power supply signal ELVDD and the second power supply signal ELVSS, but is not limited thereto. For example, the initialization signal Vinit may be less than or equal to the second power supply signal ELVSS.

[0041] In some embodiments, the display substrate 110 may include a plurality of third power lines 116B extending in a first direction, and the plurality of third power lines 116B are provided at intervals along a second direction. The third power line 116B may be connected to the first power line 116A and configured to provide the first power signal ELVDD to the pixel circuit 1121.

[0042] In this way, by alternately providing the first power line 116A and the third power line 116B extending in different directions, it is advantageous for maintaining the stability of the first power signal ELVDD provided by the entire display substrate 110 to the pixel circuit 1121.

[0043] In some embodiments, the pixel circuit 1121 includes a data writing transistor T1, a first compensation transistor T2, a driving transistor T3, a first reset transistor T4, a second reset transistor T5, a third reset transistor T6, a light emission control transistor T7, a fourth reset transistor T8, a second compensation transistor T9, and a storage capacitor C1.

[0044] During the reset stage, the pixel circuit 1121 can realize the initialization of the driving transistor T3, the storage capacitor C1, and the light emitting element 118 under the action of the reset control signal RESET by the initialization signal Vinit. Thereby, when the display screen is refreshed frame by frame, the state of the pixel circuit 1121 is kept the same, ensuring that the display device 100 can display normally. When writing data, the pixel circuit 1121 can write the data signal provided from the data signal line into the storage capacitor C1 and store it under the action of the gate signal Sn, and realize the compensation for the threshold voltage of the third transistor T3. During the light emission control stage, the pixel circuit 1121 can convert the data signal into a current signal under the action of the light emission control signal EM to drive the light emitting element 118 to emit light, realizing image display.

[0045] The display device 100 according to an embodiment of the present disclosure further includes a data driving circuit 120 and a scanning driving circuit 130. The data driving circuit 120 is configured to provide a data signal to the pixel unit 112 according to a command of the control circuit, and the scanning driving circuit 130 is configured to provide signals such as a light emission control signal EM, a gate signal Sn, a reset control signal RESET, and an initialization signal Vinit to the pixel unit 112 according to a command of the control circuit.

[0046] In the embodiment shown in FIG. 2, the display substrate 110 includes a non-display area 1112, and the data driving circuit 120 and the scanning driving circuit 130 may be provided in the non-display area of the display substrate 110, but are not limited thereto. For example, the data driving circuit 120 and the scanning driving circuit 130 may be provided on a circuit board that connects the electronic device 100 and the display substrate 110, such as a printed circuit board and / or a flexible circuit board.

[0047] In some embodiments, the control circuit of the display substrate 110 includes, but is not limited to, an external integrated circuit (IC). In some embodiments, the scanning driving circuit 130 has a GOA (Gate On Array) structure mounted on the display panel, or a driving chip (IC) structure bonded to the display panel. For example, it is also possible to provide the light emission control signal EM and the gate signal Sn using different driving circuits. In some embodiments, the display device 100 further includes a power supply (not shown) for providing the above-described power supply signal, which may be a voltage source or a current source as required, and the power supply is configured to provide a first power supply signal ELVDD, a second power supply signal ELVSS, an initialization signal Vinit, etc. to the pixel unit 112 through the first power supply line 116A, the second power supply line 119, and the initialization signal line 113, respectively.

[0048] In some embodiments, the light emission control signal line 115 is connected to the gate T70 of the light emission control transistor T7. Note that a part of the light emission control signal line 115 serves as the gate T70 of the light emission control transistor T7.

[0049] Furthermore, the emission control transistor T7 includes a first pole T71 and a second pole T72, and the second pole T72 and the first pole T71 of the emission control transistor T7 are respectively located on the first side and the second side with the emission control signal line 115 interposed therebetween.

[0050] In some embodiments, the driving transistor T3 is located on the second side of the emission control signal line 115, includes a first pole T31 and a second pole T32, the first pole T31 is connected to the first power supply line 116A, and the second pole T32 is connected to the first pole T71 of the emission control transistor T7.

[0051] In some embodiments, the first reset transistor T4 is located between the second control signal line 114B and the emission control signal line 115, and the second control signal line 114B is connected to the gate T40 of the first reset transistor T4. The first reset transistor T4 includes a first pole T41 and a second pole T42, the first pole T41 is connected to the gate T30 of the driving transistor T3, and the second pole T42 is connected to the initialization signal line 113.

[0052] Specifically, a part of the second control signal line 114B serves as the gate T40 of the first reset transistor T4. The first control signal line 114A can provide a reset control signal RESET to the first reset transistor T4, and the first reset transistor T4 provides an initialization signal Vinit to the gate T30 of the driving transistor T3 for initialization under the action of the reset control signal RESET.

[0053] In some embodiments, the first control signal line 114A is respectively connected to the gate T10 of the data writing transistor T1 and the gate T20 of the first compensation transistor T2.

[0054] Specifically, a part of the first control signal line 114A may be used as the gate T10 of the data writing transistor T1, and another part of the first control signal line 114A may be used as the gate T20 of the first compensation transistor T2.

[0055] Furthermore, in some examples, the data writing transistor T1 includes a first pole T11 and a second pole T12. The first pole T11 of the data writing transistor T1 is connected to the data line 117. The storage capacitor C1 includes a first pole C11 and a second pole C12. The first pole C11 of the storage capacitor C1 is connected to the second pole T12 of the data writing transistor T1. The second pole C12 of the storage capacitor C1 is connected to the gate T30 of the driving transistor T3.

[0056] Specifically, the second pole C12 of the storage capacitor C1 may be used as the gate T30 of the driving transistor T3. The first control signal line 114A can provide a gate signal Sn to the data writing transistor T1. The data writing transistor T1 writes the data signal provided from the data line 117 into the storage capacitor C1 under the action of the gate signal Sn.

[0057] In one example, the storage capacitor C1 is located between the first control signal line 114A and the light emission control signal line 115.

[0058] Furthermore, the first compensation transistor T2 includes a first pole T21 and a second pole T22. The first pole T21 of the first compensation transistor T2 is connected to the gate T30 of the driving transistor T3. The second pole T22 of the first compensation transistor T2 is connected to the second pole T32 of the driving transistor T3.

[0059] In this way, the first control signal line 114A provides a gate signal Sn to the first compensation transistor T2. The first compensation transistor T2 can communicate the gate T30 and the second pole T32 of the driving transistor T3 under the action of the gate signal Sn, thereby compensating the threshold voltage of the driving transistor T3 when writing the data signal.

[0060] In some embodiments, the data writing transistor T1 and the first compensation transistor T2 are located on the side closer to the light emission control signal line 115 of the first control signal line 114A.

[0061] That is, the first control signal line 114A is configured to provide the gate signal Sn to the first pixel circuit 1121a and the second pixel circuit 1121b on the side of the first control signal line 114A. Note that the first control signal line 114A may be configured to provide the reset control signal RESET to other pixel circuits 1121 on the other side of the first control signal line 114A facing the first pixel circuit 1121a and the second pixel circuit 1121b, and is not specifically limited here.

[0062] In some embodiments, the emission control signal line 115 is connected to the gate T90 of the second compensation transistor T9. The second compensation transistor T9 includes a first pole T91 located on the first side of the emission control signal line 115, and the first pole T91 of the second compensation transistor T9 is connected to the first pole T41 of the first reset transistor T4.

[0063] Specifically, a part of the emission control signal line 115 may be used as the gate T90 of the second compensation transistor T9. The first pole T91 of the second compensation transistor T9 located on the first side of the emission control signal line 115 is connected to the first pole T41 of the first reset transistor T4 located on the first side of the emission control signal line 115.

[0064] In the data writing process, the pixel circuit 1121 short - circuits the first compensation transistor T2 in diode connection to compensate the threshold voltage of the driving transistor T3. There is an equivalent capacitance between the gate and the drain that short - circuits the first compensation transistor T2. When the charging of the storage capacitance C1 is completed, the potential of the connection terminal with the gate of the driving transistor T3 is the threshold voltage of the driving transistor T1. In the process of the short - circuited first compensation transistor T2 turning off, due to the bias voltage and capacitance change, the charge stored in the equivalent capacitance of the first compensation transistor T2 is injected into the storage capacitance C1, and an error is likely to occur in the threshold voltage signal held in the storage capacitance C1. Thus, by providing the second compensation transistor T9, after the data writing stage is completed, since the second compensation transistor T9 has an equivalent capacitance, when the first compensation transistor T2 turns off, part or all of the charge released from the equivalent capacitance between the gate and the drain of the first compensation transistor T2 is absorbed by the equivalent capacitance of the second compensation transistor T9, and the threshold voltage can be accurately and stably maintained.

[0065] Note that the second compensation transistor T9 is located at the second pole (not shown) on the second side of the light - emission control signal line 115 and may be floating.

[0066] In some embodiments, the display substrate 110 includes a first connection electrode 11211 extending in the second direction. The first connection electrode 11211 connects the gate T30 of the driving transistor T3 (the second pole C12 of the storage capacitance C1), the first pole T21 of the first compensation transistor T2, and the first pole T91 of the second compensation transistor T9.

[0067] Specifically, the display substrate 110 has a multilayer structure, and each wiring in the pixel circuit 1121 may be provided in a different layer, and the electrodes of different elements may also be provided at different positions in the same layer or different layers. In this way, by providing the first connection electrode 11211 on any one layer of the substrate, the electrical connection between the gate T30 of the driving transistor T3 located in a different layer or at a different position, the first pole T21 of the first compensation transistor T2, and the first pole T91 of the second compensation transistor T9 can be realized. Here, the first connection electrode 11211 can be connected to the corresponding element through the via holes formed in each layer of the substrate.

[0068] In one example, a plate via hole is formed in the first pole C11 of the storage capacitor C1, and the first connection electrode 11211 is connected to the second pole C12 of the storage capacitor C1, that is, the gate T30 of the driving transistor T3, through the plate via hole.

[0069] In some embodiments, the second reset transistor T5 and the third reset transistor T6 are located between the second control signal line 114B and the light emission control signal line 115. The second control signal line 114B is connected to the gate T50 of the second reset transistor T5, and the light emission control signal line 115 is connected to the gate T60 of the third reset transistor T6.

[0070] Specifically, a part of the second control signal line 114B may be used as the gate T50 of the second reset transistor T5, and the light emission control signal line 115 may be used as the gate T60 of the third reset transistor T6.

[0071] Furthermore, in some embodiments, the second reset transistor T5 includes a first pole T51 and a second pole T52. The first pole T51 is connected to the second pole T12 of the data writing transistor T1, and the second pole T52 is connected to the initialization signal line 113.

[0072] Thus, the second control signal line 114B can provide the reset control signal RESET to the second reset transistor T5, and the second reset transistor T5 can provide the initialization signal Vinit to the second pole T12 of the data writing transistor T1 and the first pole C11 of the storage capacitor C1 under the action of the reset control signal RESET for initialization.

[0073] In some embodiments, the third reset transistor T6 includes a first pole T61 and a second pole T62, the first pole T61 is connected to the second pole T12 of the data writing transistor T1, and the second pole T62 is connected to the initialization signal line 113.

[0074] Thus, the emission control signal EM provides the emission control signal EM to the third reset transistor T6, and the third reset transistor T6 can provide the initialization signal Vinit to the second pole T12 of the data writing transistor T1 and the first pole C11 of the storage capacitor C1 under the action of the emission control signal EM for initialization.

[0075] In some embodiments, the display substrate 110 includes a second connection electrode 11212 extending in the second direction, and the second connection electrode 11212 connects the first pole T51 of the second reset transistor T5, the first pole T61 of the third reset transistor T6, the first pole C11 of the storage capacitor C1, and the second pole T12 of the data writing transistor T1.

[0076] Similarly, by providing the second connection electrode 11212, the electrical connection between the first pole T51 of the second reset transistor T5, the first pole T61 of the third reset transistor T6, the first pole C11 of the storage capacitor C1, and the second pole T12 of the data writing transistor T1 located in different layers or different positions is realized. Here, the second connection electrode 11212 can be connected to the corresponding element through the via holes opened in each layer of the substrate.

[0077] In some embodiments, the first connection electrode 11211, the second connection electrode 11212, the data line 117, and the first power supply line 116A are provided in the same layer.

[0078] In some embodiments, the second pole T72 of the light emission control transistor T7 is connected to the first pole 1181 of the light emitting element 118.

[0079] Specifically, the light emission control transistor T7 is turned on under the action of the light emission control signal EM, the driving transistor T3 generates a driving current under the action of the first power supply signal ELVDD, and the light emission control transistor T7 transmits the driving current to the first pole 1181 of the light emitting element 118 to drive the light emitting element 118 to emit light.

[0080] In some embodiments, the fourth reset transistor T8 is located between the second control signal line 114B and the light emission control signal line 115, and the second control signal line 114B is connected to the gate T80 of the fourth reset transistor T8.

[0081] Specifically, a part of the second control signal line 114B may be used as the gate T80 of the fourth reset transistor T8.

[0082] Furthermore, in some embodiments, the fourth reset transistor T8 includes a first pole T81 and a second pole T82, the first pole T81 is connected to the first pole 1181 of the light emitting element 118, and the second pole T82 is connected to the initialization signal line 113.

[0083] In this way, the second control signal line 114B can provide the reset control signal RESET to the fourth reset transistor T8, and the fourth reset transistor T8 can provide the initialization signal Vinit to the first pole 1181 of the light emitting element 118 under the action of the reset control signal RESET to initialize it.

[0084] In some embodiments, the display substrate 110 includes a buffer layer 120 on a base substrate 111, and the pixel circuit 1121 includes an active layer 121 located on the buffer layer 120, a first insulating layer 122 located on a side of the active layer 121 away from the base substrate 111, a gate layer 123 located on the first insulating layer 122, a second insulating layer 124 located on a side of the gate layer 123 away from the base substrate 111, a third insulating layer 125 located on the second insulating layer 124, and a source-drain layer 126 located on the third insulating layer 125.

[0085] In some embodiments, the material of the buffer layer 120 may include an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. The material of one or more of the third insulating layer 125, the second insulating layer 124, and the first insulating layer 122 may include an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. The materials of the third insulating layer 125, the second insulating layer 124, and the first insulating layer 122 may be the same or different.

[0086] In some embodiments, as shown in FIG. 4, in some examples of the above-described embodiments of the present disclosure, the active layer 121 may include a source region 1211, a drain region 1212, and a channel region 1213 located between the source region 1211 and the drain region 1212. The third insulating layer 125, the second insulating layer 124, and the first insulating layer 122 have via holes for exposing the source region 1211 and the drain region 1212. The first pole 1261 and the second pole 1262 of the transistor are electrically connected to the source region 1211 and the drain region 1212 through the via holes, respectively. The gate layer 123 overlaps the channel region 1213 located between the source region 1211 and the drain region 1212 in the active layer 121 in a direction perpendicular to the base substrate 111.

[0087] In some embodiments, the display substrate 110 further includes a planarization layer 127 on a side of the base substrate 111 away from the source-drain layer 126. The planarization layer 127 is located above the first pole 1261 and the second pole 1262 of the transistor, and planarizes the surface of the pixel circuit 1121 on a side away from the base substrate 111. Via holes are formed in the planarization layer 127 to expose the first pole 1261 and the second pole 1262 (in the illustrated case) of the transistor. A passivation layer 128 including passivation layer vias may be further formed between the pixel circuit 1121 and the planarization layer 127. The passivation layer 128 can protect the first pole 1261 and the second pole 1262 of the transistor in the pixel circuit 1121 from corrosion by water vapor.

[0088] The transistor shown in FIG. 4 may be the fourth reset transistor T8 or the light emission control transistor T7, but other transistors in the circuit may be formed at other positions on the substrate, and correspondingly, the connection method of other transistors may also be designed as required and is not usually specifically limited.

[0089] For example, the material of the active layer 121 may include polycrystalline silicon or an oxide semiconductor (for example, zinc indium gallium oxide). The material of the gate electrode may include a metal material or an alloy material. For example, it is a single-layer or multi-layer structure of a metal composed of molybdenum, aluminum, titanium, etc. For example, the multi-layer structure is a stack of a plurality of metal layers (for example, a three-layer metal stack of titanium, aluminum, and titanium (Ti / Al / Ti)). The material of the source electrode and the drain electrode may include a metal material or an alloy material. For example, it is a single-layer or multi-layer structure of a metal composed of molybdenum, aluminum, titanium, etc. For example, the multi-layer structure is a stack of a plurality of metal layers (for example, a three-layer metal stack of titanium, aluminum, and titanium (Ti / Al / Ti)). In the embodiments of the present disclosure, the materials of each functional layer are not specifically limited.

[0090] In some embodiments, the material of the passivation layer 128 may include an organic insulating material or an inorganic insulating material, such as a silicon nitride material, which has a high dielectric constant and excellent hydrophobicity and can well protect the pixel driving circuit from corrosion by water vapor.

[0091] In some embodiments, the light-emitting element 118 may be formed on the planarization layer 127, that is, the light-emitting element 118 is provided on the side away from the base substrate 111 of the planarization layer 127. The light-emitting element 118 includes a first electrode 1181, a light-emitting layer 1182, and a second electrode 1183. The first electrode 1181 of the light-emitting element 118 is electrically connected to the first electrode 1261 and / or the second electrode 1262 of the corresponding transistor through the via hole of the planarization layer 127. On the first electrode 1181 of the light-emitting element 118, a pixel definition layer 130 including a plurality of openings defining a plurality of pixel units 112 is formed. Each of the plurality of openings exposes the first electrode 1181 of the corresponding light-emitting element 118. Then, the light-emitting layer 1182 is provided in the plurality of openings of the pixel definition layer 130, and the second electrode 1183 of the light-emitting element 118 is provided on the pixel definition layer 130 and the light-emitting layer 1182. For example, the second electrode 1183 may be provided in a part or all of the display area 1111 and may be formed entirely during the manufacturing process.

[0092] In some embodiments, the pixel circuit 1121 may include an adapter electrode 11213, and the display substrate 110 connects the first electrode 1181 of the light-emitting element 118 and the first electrode 1261 and / or the second electrode 1262 of the corresponding transistor through the adapter electrode 11213. In this way, the adapter electrode 11213 can make the arrangement of the relative positions of the pixel circuit 1121 and the light-emitting element 118 in the display panel 110 more flexible.

[0093] For example, the first electrode 1181 of the light-emitting element 118 may include a reflective layer (not shown), and the second electrode 1182 of the light-emitting element 118 may include a transparent layer or a translucent layer. Thereby, the first electrode 1181 of the light-emitting element 118 can reflect the light emitted from the light-emitting layer 1182, and the light in this part is radiated to the external environment through the second electrode 1183 of the light-emitting element 118, thereby providing a light emission rate. When the second electrode 1183 of the light-emitting element 118 includes a semi-transmissive layer, some of the light reflected by the first electrode 1181 of the light-emitting element 118 is reflected again by the second electrode 1183 of the light-emitting element 118. Therefore, the first electrode 1181 of the light-emitting element 118 and the second electrode 1183 of the light-emitting element 118 form a resonance structure, and the light emission efficiency can be improved.

[0094] For example, the material of the first electrode 1181 of the light-emitting element 118 may include at least one transparent conductive oxide material including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), etc. Further, the first electrode 1181 of the light-emitting element 118 may include a metal with a high reflectivity such as silver (Ag) as a reflective layer.

[0095] For example, in the case of an OLED, the light-emitting layer 1182 may include a small molecule or a polymer molecule organic material, and may be a fluorescent or phosphorescent light-emitting material, and can emit red light, green light, blue light, or white light. Further, the light-emitting layer 1182 may further include functional layers such as an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer as required.

[0096] For example, the second electrode 1182 of the light-emitting element 118 may include various conductive materials. For example, the second electrode 1183 of the light-emitting element 118 may include a metal material such as lithium (Li), aluminum (Al), magnesium (Mg), silver (Ag), etc.

[0097] For example, the material of the pixel definition layer 130 may include organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, and phenolic resin, or may include inorganic insulating materials such as silicon oxide and silicon nitride. The embodiments of the present disclosure are not limited thereto.

[0098] Also, the first electrode C11 of the storage capacitor C1 is provided between the second insulating layer 124 and the third insulating layer 125, and the second electrode C12 is provided between the first insulating layer 122 and the second insulating layer 124. The first electrode C11 and the second electrode C12 of the storage capacitor C1 are laminated so that at least a part thereof overlaps in a direction perpendicular to the base substrate 111. The first electrode C11 and the second electrode C12 of the storage capacitor C1 form the storage capacitor C1 using the second insulating layer 124 as a dielectric material. The second electrode C12 of the storage capacitor C1 is provided in the same layer as the gate layer 123 in the pixel circuit 1121. Thus, also in the above-described modification example, it is also possible to obtain sub-pixels having different structures in which the first electrode C11 and the second electrode C12 of the storage capacitor C1 are located in other layers.

[0099] In some embodiments, as shown in FIG. 4, the display substrate 110 may further include a sealing layer 131 provided on the light-emitting element 118. By sealing the light-emitting element 118, the sealing layer 131 can reduce or prevent the deterioration of the light-emitting element 118 due to moisture and / or oxygen contained in the environment. The sealing layer 131 may have a single-layer structure or a composite layer structure in which an inorganic layer and an organic layer are laminated. For example, it may include a first inorganic sealing layer 1311, a first organic sealing layer 1312, and a second inorganic sealing layer 1313 provided in sequence.

[0100] For example, the material of the encapsulation layer 131 may include insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, and polymer resins. Inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride have high density and can prevent the intrusion of water, oxygen, etc. The material of the organic encapsulation layer 131 may be a polymer resin that can planarize the surface of the display substrate 110 and relieve the stress of the first inorganic encapsulation layer 1311 and the second inorganic encapsulation layer 1313, such as a polymer material containing a desiccant or a polymer material capable of blocking water vapor, and may also contain a water-absorbing material such as a desiccant to absorb substances such as water and oxygen that have intruded inside.

[0101] Referring to FIGS. 6 to 8, FIG. 6 is a schematic diagram of the semiconductor pattern layer L1 of the display substrate 110, and a first insulating layer 122 may be formed on the semiconductor pattern layer L1. FIG. 7 is a schematic diagram of the first conductive pattern layer L2 formed on the first insulating layer 122 of the display substrate 110, and FIG. 8 is a schematic structural diagram of the display substrate 110 after the semiconductor pattern layer is subjected to a conductor formation process using a self-alignment process. In some embodiments, in the manufacturing process of the display substrate 110, using a self-alignment process, the semiconductor pattern layer L1 is subjected to a conductor formation process using the first conductive pattern layer L2 as a mask, for example, high-concentration doping is performed on the semiconductor pattern layer L1 using ion implantation, and the semiconductor pattern layer L1 in the portion not covered by the first conductive pattern layer L2 is made conductive, and the source region (the first pole T11) and the drain region (the second pole T12) of the data writing transistor T1, the source region (the first pole T21) and the drain region (the second pole T22) of the first compensation transistor T2, the source region (the first pole T31) and the drain region (the second pole T32) of the driving transistor T3, the source region (the first pole T41) and the drain region (the second pole T42) of the first reset transistor T4, the source region (the first pole T51) and the drain region (the second pole T52) of the second reset transistor T5, the source region (the first pole T61) and the drain region (the second pole T62) of the third reset transistor T6, the source region (the first pole T71) and the drain region (the second pole T72) of the light emission control transistor T7, the source region (the first pole T81) and the drain region (the second pole T82) of the fourth reset transistor T8, and the source region (the first pole T91) and the drain region (the second pole T92) of the second compensation transistor T9 are formed.The semiconductor pattern layer L1 in the portion covered by the first conductive pattern layer L2 retains semiconductor characteristics and forms the channel regions T14 of the data writing transistor T1, T24 of the first compensation transistor T2, T34 of the driving transistor T3, T44 of the first reset transistor T4, T54 of the second reset transistor T5, T64 of the third reset transistor T6, T74 of the light emission control transistor T7, T84 of the fourth reset transistor T8, and T94 of the second compensation transistor T9.

[0102] As shown in FIG. 8, the second pole T82 of the fourth reset transistor T8 and the second pole T42 of the first reset transistor T4 are integrally formed. The first pole T91 of the second compensation transistor T9 and the first pole T41 of the first reset transistor T4 are integrally formed. The first pole T81 of the fourth reset transistor T8 and the second pole T72 of the light emission control transistor T7 are integrally formed. The first pole T71 of the light emission control transistor T7, the second pole T32 of the driving transistor T3, and the second pole T22 of the first compensation transistor T2 are integrally formed. The first poles T51 of the second reset transistor T5 and T61 of the third reset transistor T6 are integrally formed. The second poles T52 of the second reset transistor T5 and T62 of the third reset transistor T6 are integrally formed. In particular, the second pole C12 of the storage capacitor C1 may be used as the gate T30 of the driving transistor T3.

[0103] For example, the channel region 1213 (active layer 121) of the transistor used in the embodiments of the present disclosure may be single-crystalline silicon, polycrystalline silicon (e.g., low-temperature polycrystalline silicon), or a metal-oxide semiconductor material (e.g., IGZO, AZO, etc.). In one embodiment, all of the transistors are P-type low-temperature polycrystalline silicon (LTPS) thin-film transistors. In other embodiments, the first compensation transistor T2 and the first reset transistor T4 directly connected to the gate T30 of the driving transistor T3 are metal-oxide semiconductor thin-film transistors, that is, the channel material of the transistor is a metal-oxide semiconductor material (e.g., IGZO, AZO, etc.). Since the metal-oxide semiconductor thin-film transistor has a small leakage current, it can contribute to reducing the leakage current of the gate of the driving transistor T3.

[0104] For example, the transistors used in the embodiments of the present disclosure may include various structures such as a top-gate type, a bottom-gate type, or a double-gate type. In one embodiment, the first compensation transistor T2 and the first reset transistor T4 directly connected to the gate of the driving transistor T3 are double-gate type thin-film transistors, which can contribute to reducing the leakage current of the gate T30 of the driving transistor T3.

[0105] Note that the semiconductor pattern layer L1 may be the above-described active layer 121, and the first conductive pattern layer L2 may be the above-described gate layer 123.

[0106] In some embodiments, the correspondence between the semiconductor pattern layer L1 and the via holes VH1, VH2, VH3, VH4, VH5, VH6, VH7, and VH8 formed on the display substrate 110 is shown in FIG. 6, and the semiconductor pattern layer L1 can be connected to other layers of the display substrate 110 through the via holes.

[0107] Referring to FIG. 9, in some embodiments, a second insulating layer 124 is formed on the structure after the conductor formation process, and a second conductive pattern layer L3 is formed on the second insulating layer 124. The second conductive pattern layer L3 includes a first pole C11 of the storage capacitor C1 and an initialization signal line 113. The first pole C11 of the storage capacitor C1 is provided in the same layer as the initialization signal line 113. The first pole C11 of the storage capacitor C1 has an electrode via hole C111, which facilitates the electrical connection of the first connection electrode 11211 to the second pole C12 of the storage capacitor C1 (the gate T30 of the driving transistor T3) through the electrode via hole C111. The first connection electrode 11211 and the first pole C11 of the storage capacitor C1 are insulated from each other.

[0108] In some embodiments, the via hole VH3 may penetrate through the first insulating layer 122 and the second insulating layer 124, whereby the initialization signal line 113 can be connected to the second poles T42 of the first reset transistor T4, the second poles T52 of the second reset transistor T5, the second poles T62 of the third reset transistor T6, and the second poles T82 of the fourth reset transistor T8 through the via hole VH3.

[0109] Note that the second conductive pattern layer L3 may be located between the second insulating layer 124 and the third insulating layer 125.

[0110] In some embodiments, the second conductive pattern layer L3 further includes a third power supply line 116B, that is, the third power supply line 116B is provided in the same layer as the first pole C11 of the storage capacitor C1 and the initialization signal line 113. Specifically, the third power supply line 116B is located between the first pole C11 of the storage capacitor C1 and the initialization signal line 113.

[0111] As shown in FIG. 10, after further forming a third insulating layer 125 on the side of the second conductive pattern layer L3 of the display substrate 110 away from the first conductive pattern layer L2, a third conductive pattern layer L4 may be further formed on the side of the third insulating layer 125 away from the second conductive pattern layer L3. The third conductive pattern layer L4 is formed with a first connection electrode 11211, a second connection electrode 11212, a first adapter electrode 11213, a data line 117, and a first power line 116A. The first connection electrode 11211, the second connection electrode 11212, the adapter electrode 11213, the data line 117, and the first power line 116A are located in the same layer.

[0112] For example, the first conductive pattern layer L2, the second conductive pattern layer L3, and the third conductive pattern layer L4 are all made of a metal material. For example, the first conductive pattern layer L2 is formed by the same patterning process from the same metal material, the second conductive pattern layer L3 is formed by the same patterning process from the same metal material, and the third conductive pattern layer L4 is formed by the same patterning process from the same metal material. For example, examples of the metal material include, but are not limited to, molybdenum (Mo) metal, aluminum metal, and titanium metal. For example, the first conductive pattern layer L2, the second conductive pattern layer L3, and the third conductive pattern layer L4 may be formed of molybdenum metal, but are not limited thereto.

[0113] Note that the third conductive pattern layer L4 may be the source-drain layer 123 described above. The display substrate 110 further includes via holes VH9, VH10, and VH11. Here, via holes VH1, VH2, VH4, VH5, VH6, VH7, and VH8 may penetrate the first insulating layer 122, the second insulating layer 124, and the third insulating layer 125, via hole VH9 may penetrate the second insulating layer 124 and the third insulating layer 125, and via holes VH10 and VH11 may penetrate the third insulating layer 125.

[0114] In this way, the adapter electrode 11213 can be connected to the first pole T81 of the fourth reset transistor T8 and the second pole T72 of the light emission control transistor T7 via the via hole VH1. The first connection electrode 11211 is connected to the first pole T91 of the second compensation transistor T9 and the first pole T41 of the first reset transistor T4 via the via hole VH2, connected to the second pole C12 of the storage capacitor C1 via the via hole VH9, and can be connected to the first pole T21 of the first compensation transistor T2 via the via hole VH7, where the via hole VH9 corresponds to the electrode via hole C111. The second connection electrode 11212 is connected to the first pole T51 of the second reset transistor T5 and the second pole T62 of the third reset transistor T6 via the via hole VH4, connected to the first pole C11 of the storage capacitor C1 via the via hole VH11, and can be connected to the second pole T12 of the data writing transistor T1 via the via hole VH6. The data line 117 can be connected to the first pole T11 of the data writing transistor T1 via the via hole VH8. The first power supply line 116A can be connected to the third power supply line 116B via the via hole VH10.

[0115] In some embodiments, the second conductive layer L3 further includes a capacitor plate C21, and the capacitor plate C21 is provided corresponding to the data line 117 and can shield the interference between the data line 117 and other signal lines.

[0116] Referring to FIG. 11, in some embodiments, the display substrate 110 includes an initialization bus 132 located on a side of the initialization signal line 113 away from the base substrate 111, and the initialization bus 132 and the initialization signal line 113 are electrically connected. Specifically, a passivation layer 128 is formed on a side of the second conductive pattern layer L3 away from the third conductive pattern layer L4, a planarization layer 127 is formed on a side of the passivation layer 128 away from the third conductive pattern layer L4, and then an anode circuit pattern L5 can be formed on a side of the planarization layer 127 away from the third conductive pattern layer L4. The anode circuit pattern L5 includes the first electrode 1181 of the light-emitting element 118 and the initialization bus 132. The initialization bus 132 is provided in the same layer as the first electrode 1181 of the light-emitting element 118. In an example, the light-emitting element 118 is an OLED, and the first electrode 1181 of the light-emitting element 118 is the anode of the OLED. The initialization bus 132 can be connected to the initialization signal line 113 of the second conductive pattern layer L3 through via holes of the passivation layer 128 and the planarization layer 127.

[0117] In this way, the initialization bus 132 can make full use of the wiring space of the anode conductive layer, and the initialization signal Vinit can be further provided to the adjacent first pixel circuit 1121a and second pixel circuit 1121b by the segmented initialization signal line 113.

[0118] In some embodiments, the display substrate 110 may further include via holes VH12 and VH13. The via hole VH12 penetrates the passivation layer 128 and the planarization layer 127, and the via hole VH13 penetrates the passivation layer 128 and the planarization layer 127.

[0119] In this way, the adapter electrode 11213 can be connected to the first electrode 1181 of the light-emitting element 118 through the via hole VH12, and the initialization signal line 113 can be connected to the initialization bus 132 through the via hole VH13.

[0120] In some embodiments, the initialization bus 132 includes a plurality of main body portions 1321, a plurality of connection portions 1322, and a plurality of branch portions 1323. The plurality of main body portions 1321 extend in a first direction and are provided at intervals along a second direction. They are configured to provide an initialization signal Vinit to corresponding ones of the plurality of initialization signal lines 113 that extend in the first direction and are segmented at intervals. The plurality of connection portions 1322 extend in the second direction and connect two adjacent main body portions 1321. The plurality of branch portions 1323 are connected to at least one of two adjacent main body portions 1321. The plurality of connection portions 1322 and the plurality of branch portions 1323 are alternately spaced along the first direction. The plurality of branch portions 1322 are located between two adjacent main body portions 1321 and are configured to provide an initialization signal Vinit to corresponding ones of the plurality of initialization signal lines 113 that extend in the first direction and are segmented at intervals.

[0121] Referring to FIG. 12, in some embodiments, a pixel opening layer L6 may be formed on a side of the display substrate 110 away from the substrate of the anode circuit pattern L5, and a pixel opening 1301 corresponding to the anode circuit pattern L5 is provided in the pixel opening layer L6. Note that the pixel opening layer L6 may be the above-described pixel definition layer 130.

[0122] In the description of this specification, descriptions related to terms such as "one embodiment", "some embodiments", "exemplary embodiments", "examples", "specific examples", or "some examples" mean that specific features, structures, materials, or characteristics described in combination with the embodiments or examples are included in at least one embodiment or example of the present disclosure. In this specification, exemplary expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any appropriate manner in one or more embodiments or examples.

[0123] Although embodiments of the present disclosure have been illustrated and described, those skilled in the art can make various changes, modifications, substitutions, and variations to these embodiments without departing from the principles and spirit of the present disclosure. It will be understood that the scope of the present disclosure is limited by the claims and their equivalents.

Explanation of Reference Numerals

[0124] 100 Display device 110 Display substrate 111 Base substrate 112 Pixel unit 113 Initialization signal line 114A First control signal line 114B Second control signal line 115 Light emission control signal line 116A First power supply line 116B Third power supply line 117 Data line 118 Light emitting element 119 Second power supply line 120 Data driving circuit 120 Buffer layer 121 Active layer 122 First insulating layer 123 Gate layer 124 Second insulating layer 125 Third insulating layer 126 Source-drain layer 127 Flattening layer 128 Passivation layer 130 Scanning driving circuit 130 Pixel definition layer

Claims

1. a base substrate including a display area; a plurality of pixel units each including a pixel circuit, the pixel circuit including a first pixel circuit and a second pixel circuit adjacent to each other along a first direction, the pixel circuit being located in the display area; an initialization signal line extending in the first direction and configured to provide an initialization signal to the first pixel circuit and the second pixel circuit; a first control signal line extending in the first direction and configured to provide a gate signal to the first pixel circuit and the second pixel circuit; a light emission control signal line extending in the first direction and configured to provide a light emission control signal to the first pixel circuit and the second pixel circuit; Equipped with the initialization signal line is located on a side of the light emission control signal line that is distant from the first control signal line, extends in the first direction, and is provided in a segmented manner at intervals; an initialization bus line located on a side of the initialization signal line away from the base substrate, the initialization bus line and the initialization signal line being electrically connected; the initialization bus line includes a plurality of main body portions, a plurality of connection portions, and a plurality of branch portions; the plurality of body portions extend in the first direction and are spaced apart along a second direction, and are configured to provide the initialization signal to a corresponding plurality of initialization signal lines extending in the first direction and spaced apart in segments; The plurality of connection portions extend in the second direction and connect two adjacent ones of the main body portions, A display substrate, wherein the plurality of branch portions are connected to at least one of two adjacent body portions, and the plurality of branch portions are located between the two adjacent body portions, extend in the first direction, and are configured to provide the initialization signal to a corresponding plurality of initialization signal lines that are segmented and spaced apart.

2. 2. The display substrate of claim 1, further comprising a second control signal line located on a side of the initialization signal line away from the emission control signal line, the second control signal line extending in the first direction and configured to provide a reset control signal to the first pixel circuit and the second pixel circuit.

3. 3. The display substrate of claim 2, further comprising a plurality of first power lines extending in the second direction and spaced apart along the first direction, the first power lines configured to provide a first power signal to the pixel circuits.

4. 4. The display substrate of claim 3, further comprising a plurality of third power lines, the plurality of third power lines being spaced apart along the second direction, the third power lines being connected to the first power lines and configured to provide the first power signal to the pixel circuits.

5. the pixel circuit includes a light emission control transistor; a gate of the light emission control transistor is connected to the light emission control signal line, the light emission control transistor includes a first pole and a second pole, and the pixel circuit includes a driving transistor; the driving transistor includes a first pole and a second pole, the first pole of the driving transistor is connected to the first power supply line; 4. The display substrate according to claim 3, wherein the second electrode of the driving transistor is connected to the first electrode of the light-emitting control transistor.

6. the pixel circuit includes a first reset transistor and a storage capacitor, the second control signal line is connected to a gate of the first reset transistor, the storage capacitance includes a first pole and a second pole, the second pole of the storage capacitance being connected to the gate of the drive transistor; 6. The display substrate of claim 5, wherein the first reset transistor includes a first pole and a second pole, the second pole of the first reset transistor is connected to the gate of the driving transistor, and the first reset transistor is configured to realize initialization of the driving transistor and the storage capacitor by the initialization signal in a reset stage.

7. 7. The display substrate according to claim 6, wherein the initialization signal line is provided in the same layer as the first pole of the storage capacitor, with a gap therebetween.

8. 7. The display substrate of claim 6, further comprising a plurality of data lines, the plurality of data lines extending in the second direction and spaced apart along the first direction, the plurality of data lines configured to provide data signals to the pixel circuits.

9. the pixel circuit includes a data writing transistor and a first compensation transistor; the data write transistor includes a first pole and a second pole, the first pole of the data write transistor is connected to the data line; a first electrode of the storage capacitor is connected to a second electrode of the data write transistor; 9. The display substrate of claim 8, wherein the first compensation transistor includes a first pole and a second pole, the first pole of the first compensation transistor is connected to the gate of the driving transistor, and the second pole of the first compensation transistor is connected to the second pole of the driving transistor.

10. The display substrate of claim 9, wherein the data write transistor and the first compensation transistor are located on a side of the first control signal line that is closer to the light emission control signal line.

11. the pixel circuit includes a second reset transistor and a third reset transistor located between the second control signal line and the light emission control signal line, the second control signal line is connected to a gate of the second reset transistor, and the light emission control signal line is connected to a gate of the third reset transistor; the second reset transistor includes a first pole and a second pole, the first pole of the second reset transistor is connected to the second pole of the data write transistor, and the second pole of the second reset transistor is connected to the initialization signal line; 11. The display substrate of claim 10, wherein the third reset transistor includes a first pole and a second pole, the first pole of the third reset transistor is connected to the second pole of the data write transistor, and the second pole of the third reset transistor is connected to the initialization signal line.

12. a second electrode of the light-emitting control transistor is connected to a first electrode of the light-emitting element, and the pixel circuit includes a fourth reset transistor located between the second control signal line and the light-emitting control signal line; 6. The display substrate according to claim 5, wherein the fourth reset transistor includes a first pole and a second pole, the first pole of the fourth reset transistor is connected to the first pole of the light-emitting element, and the second pole of the fourth reset transistor is connected to the initialization signal line.

13. The display substrate of claim 12 , further comprising a second power line configured to provide a second power signal to the light emitting element.

14. 14. The display substrate of claim 13, wherein the initialization signal is a constant voltage signal, and the magnitude of the initialization signal is between the first power signal and the second power signal.

15. The display substrate according to claim 1 , wherein one pixel of the display substrate includes a pixel unit emitting red light, a pixel unit emitting green light, and a pixel unit emitting blue light.

16. 2. The display substrate of claim 1, wherein the first control signal line is further configured to provide a reset control signal to a pixel circuit on another side of the first control signal line opposite the first pixel circuit and the second pixel circuit.

17. A display device comprising the display substrate according to any one of claims 1 to 16.

18. 18. The display device of claim 17, further comprising a data driving circuit and a scan driving circuit, the data driving circuit configured to provide data signals to the pixel units according to commands from a control circuit, and the scan driving circuit configured to provide reset control signals, the emission control signals, the gate signals and the initialization signals to the pixel units according to commands from a control circuit.

19. 20. The display device of claim 18, wherein the display substrate includes a non-display area, and the data driving circuit and the scan driving circuit are provided in the non-display area.

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