Semiconductor device

Abstract

To provide a light-emitting device capable of preventing afterimage from being displayed.SOLUTION: A plurality of pixels arranged in n rows and m columns (n and m are each an integer of 2 or more) is supplied with a first signal containing image information and a second signal for initializing the pixels. Each pixel includes a first transistor for controlling input of the first signal and a second transistor for controlling input of the second signal. The first transistor in pixels in a k-th row (k is an integer of 1 or more and n or less) and the second transistor in pixels in a (k+1)th row are turned on at the same time, so that the pixels are initialized and images are displayed effectively.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to an article, a method, or a manufacturing method. Alternatively, the present invention relates to a process, a machine, a manu facture, or a composition of matter. Further, one aspect of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, a driving method thereof, or a manufacturing method thereof. In particular, one aspect of the present invention relates to a semiconductor device, a display device, or a light-emitting device including an oxide semiconductor.

[0002] Note that in this specification and the like, the semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. A display device, an electro-optical device, a semiconductor circuit, and an electronic device may include a semiconductor device.

Background Art

[0003] A light-emitting device using a light-emitting element has high visibility, is optimal for thinning, and has no viewing angle limitation. Therefore, it has attracted attention as a display device to replace a CRT (cathode ray tube) or a liquid crystal display device. An active matrix type display device using a light-emitting element has a configuration that varies depending on the manufacturer, but usually includes at least a light-emitting element, a transistor (switching transistor) that controls the input of an image signal to a pixel, and a transistor (driving transistor) that controls the current value supplied to the light-emitting element, and these are provided for each pixel.

[0004] In recent years, as a new semiconductor having both high mobility obtained by polysilicon or microcrystalline silicon and uniform element characteristics obtained by amorphous silicon, an oxide Semiconductors are attracting attention. Oxide semiconductors can be formed on substrates with low strain points such as glass substrates, and can also be applied to large substrates of the fifth generation (one side exceeding 1000 mm) or larger. And, instead of conventional semiconductors such as silicon and germanium that have been used,[[]] a light-emitting device in which the above oxide semiconductor is used for the transistors of the pixels is being put into practical use.

[0005] Patent Document 1 below describes an example in which a TFT containing an oxide semiconductor in the active layer is used for a TFT that drives an organic EL element. Also, Patent Document 2 below describes an organic electroluminescence display device in which the active layer of a thin-film transistor is formed of an oxide semiconductor. Further, Patent Document 2 below describes an organic electroluminescence display device in which the active layer of a thin-film transistor is formed of an oxide semiconductor. Regarding the organic electroluminescence display device in which the active layer of a thin-film transistor is formed of an oxide semiconductor. is described.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0007] By the way, a transistor using an oxide semiconductor has the characteristic that the off-current is extremely small. By using a transistor having the above characteristic for the pixels of a light-emitting device, the image information once input can be continuously held in the pixels, and as long as a still image is continuously displayed, the frequency of rewriting the image information can be reduced, and power saving of the display device can be achieved. However, in the above light-emitting device, if the image information is continuously held for a long time, then different image information can be continuously held in the pixels, and as long as a still image is continuously displayed, the frequency of rewriting the image information can be reduced, and power saving of the display device can be achieved. However, in the above light-emitting device, if the image information is continuously held for a long time, then different image information can be continuously held in the pixels, and as long as a still image is continuously displayed, the frequency of rewriting the image information can be reduced, and power saving of the display device can be achieved. However, in the above light-emitting device, if the image information is continuously held for a long time, then different image information is continuously held in the pixels, and as long as a still image is continuously displayed, the frequency of rewriting the image information can be reduced, and power saving of the display device can be achieved. However, in the above light-emitting device, if the image information is continuously held for a long time, then different image information Even if input to the pixel, the image information cannot be completely rewritten, and the image information before rewriting remains in the pixel and may be displayed as an afterimage.

[0008] Under the technical background as described above, one aspect of the present invention provides a novel semiconductor device or the like or provides a light-emitting device capable of preventing the display of an afterimage, or provides a driving method for a light-emitting device capable of preventing the display of an afterimage, which is one of the problems.

[0009] Also, one aspect of the present invention provides a light-emitting device capable of displaying image information even at a high scanning frequency or provides a driving method for a light-emitting device capable of displaying image information even at a high scanning frequency, which is one of the problems.

[0010] Note that the description of a plurality of problems does not prevent the existence of each other's problems. Note that one aspect of the present invention does not need to solve all of these problems. Also, problems other than those listed will naturally become apparent from the descriptions in the specification, drawings, claims, etc., and these problems can also be problems of one form of the present invention.

Means for Solving the Problems

[0011] One aspect of the present invention is a light-emitting device having a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first light-emitting element, a second light-emitting element, a first wiring, a second wiring, a third wiring, a fourth wiring, and a fifth wiring, wherein the gate of the first transistor is connected to the second wiring, and one of the source and drain of the first transistor is connected to the fourth wiring, and the source and drain of the first transistor 4 transistors, a fifth transistor, a sixth transistor, a first light-emitting element, a second light-emitting element, a first wiring, a second wiring, a third wiring, a fourth wiring, and a fifth wiring, and the gate of the first transistor is connected to the second wiring, and one of the source and drain of the first transistor is connected to the fourth wiring, and the source and drain of the first transistor element, a second light-emitting element, a first wiring, a second wiring, a third wiring, a fourth wiring, and a fifth wiring, and the gate of the first transistor is connected to the second wiring, and one of the source and drain of the first transistor is connected to the fourth wiring, and the source and drain of the first transistor is connected to the fourth wiring, and the source and drain of the first transistor and one of the drain and source are connected to the fourth wiring, and the source and drain of the first transistor​​​​ One side of the rain is connected to the gate of the third transistor, and the gate of the second transistor is connected to the first wiring. One of the source and drain of the second transistor is connected to the fifth wiring and the other of the source and drain of the second transistor is connected to the gate of the third transistor. One of the source and drain of the third transistor is connected to the first terminal of the first light-emitting element. The other of the source and drain of the third transistor is supplied with the first potential, the second terminal of the first light-emitting element is supplied with the second potential, the gate of the fourth transistor is connected to the third wiring, one of the source and drain of the fourth transistor is connected to the fourth wiring, and the other of the source and drain of the fourth transistor is connected to the gate of the sixth transistor. The gate of the fifth transistor is connected to the second wiring. One of the source and drain of the fifth transistor is connected to the fifth wiring, and the other of the source and drain of the fifth transistor is connected to the gate of the sixth transistor. One of the source and drain of the sixth transistor is connected to the first terminal of the second light-emitting element, and the other of the source and drain of the sixth transistor is supplied with the first potential. The second terminal of the second light-emitting element is supplied with the second potential. The fourth wiring is supplied with a signal including image information, and the fifth wiring is supplied with the third potential.

[0012] One aspect of the present invention is a light-emitting device having a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first light-emitting element, a second light-emitting element, a first wiring, a second wiring, a third wiring, a fourth wiring, and a fifth wiring, wherein the gate of the first transistor is connected to the second wiring, and the first transistor One of the source and drain of the [device] is connected to the fourth wiring, and the other of the source and drain of the first transistor is connected to the gate of the third transistor. The gate of the second transistor is connected to the first wiring. One of the source and drain of the second transistor is connected to the fifth wiring, and the other of the source and drain of the second transistor is connected to the gate of the third transistor. One of the source and drain of the third transistor is connected to the first terminal of the first light-emitting element, and the other of the source and drain of the third transistor is supplied with a first potential. The second terminal of the first light-emitting element is supplied with a second potential. The gate of the fourth transistor is connected to the third wiring. One of the source and drain of the fourth transistor is connected to the fourth wiring, and the other of the source and drain of the fourth transistor is connected to the gate of the sixth transistor. The gate of the fifth transistor is connected to the second wiring. One of the source and drain of the fifth transistor is connected to the fifth wiring, and the other of the source and drain of the fifth transistor is connected to the gate of the sixth transistor. One of the source and drain of the sixth transistor is connected to the first terminal of the second light-emitting element, and the other of the source and drain of the sixth transistor is supplied with a first potential. The second terminal of the second light-emitting element is supplied with a second potential. The fourth wiring is supplied with a signal including image information, and the fifth wiring is supplied with a second potential. The other of the source and drain is connected to the gate of the third transistor. The gate of the second transistor is connected to the first wiring. One of the source and drain of the second transistor is connected to the fifth wiring. The other of the source and drain of the second transistor is connected to the gate of the third transistor. One of the source and drain of the third transistor is connected to the first terminal of the first light-emitting element. The other of the source and drain of the third transistor is supplied with a first potential. The second terminal of the first light-emitting element is supplied with a second potential. The gate of the fourth transistor is connected to the third wiring. One of the source and drain of the fourth transistor is connected to the fourth wiring. The other of the source and drain of the fourth transistor is connected to the gate of the sixth transistor. The gate of the fifth transistor is connected to the second wiring. One of the source and drain of the fifth transistor is connected to the fifth wiring. The other of the source and drain of the fifth transistor is connected to the gate of the sixth transistor. One of the source and drain of the sixth transistor is connected to the first terminal of the second light-emitting element. The other of the source and drain of the sixth transistor is supplied with a first potential. The second terminal of the second light-emitting element is supplied with a second potential. The fourth wiring is supplied with a signal including image information, and the fifth wiring is supplied with a second potential. One aspect of the present invention includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first capacitor, a second capacitor, a first light-emitting element, a second light-emitting element, a first wiring, a second wiring, a third wiring, and a fourth wiring. The fourth wiring is supplied with a signal including image information, and the fifth wiring is supplied with a second potential.

[0013] One aspect of the present invention is a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first capacitor, a second capacitor, a first light-emitting element, a second light-emitting element, a first wiring, a second wiring, a third wiring, and a fourth wiring. A fourth transistor, a fifth transistor, a sixth transistor, a first capacitor, a second capacitor, a first light-emitting element, a second light-emitting element, a first wiring, a second wiring, a third wiring, and a fourth wiring. A first light-emitting element, a second light-emitting element, a first wiring, a second wiring, a third wiring, and a fourth wiring. It should be noted that the term "[device]" in the translation of is used as a placeholder as the specific device is not clearly defined in the original text. Also, the numbers within the < > tags are preserved as they are according to the requirements.A light emitting device having a first transistor and a second wiring, One of the source and drain of the first transistor is connected to the fourth wiring. The other of the source and drain of the second transistor is connected to the gate of the third transistor. The gate of the second transistor is connected to the first wiring, and one of the source and drain of the second transistor is connected to the first wiring. The other is connected to one of the source and drain of the third transistor, and the other is connected to the source and drain of the second transistor. The other of the source and drain is connected to the gate of a third transistor. One of the source and the drain is connected to the first terminal of the first light-emitting element, and the third transistor The other of the source and the drain is given a first potential, and the first terminal of the first capacitance element is connected to a third transistor. the second terminal of the first capacitance element is connected to the gate of the third transistor; and a drain of the first light-emitting element, a second terminal of the first light-emitting element is applied with a second potential, and a fourth The gate of the transistor is connected to the third wiring, and the source and drain of the fourth transistor are One of the source and drain of the fourth transistor is connected to the fourth wiring, and the other of the source and drain of the fourth transistor is connected to the sixth wiring. the gate of the fifth transistor is connected to the second wiring; the gate of the fifth transistor is connected to the second wiring; One of the source and drain of the fifth transistor is the source and drain of the sixth transistor. The other of the source and drain of the fifth transistor is connected to one of the source and drain of the sixth transistor. The sixth transistor is connected to the gate of the second light-emitting element. The other of the source and drain of the sixth transistor is connected to the first terminal, and a first potential is applied to the other of the source and drain of the sixth transistor. a first terminal of the second capacitance element is connected to the gate of the sixth transistor, and the second capacitance element a second terminal of the sixth transistor connected to one of the source and drain of the sixth transistor; The second terminal of is supplied with a second potential, and the fourth wiring is supplied with a signal including image information.

[0014] One aspect of the present invention is a light-emitting device including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first light-emitting element, a second light-emitting element, a first wiring, a second wiring, a third wiring, a fourth wiring, and a fifth wiring, wherein the gate of the first transistor is connected to the second wiring, one of the source and the drain of the first transistor is connected to the fourth wiring, the other of the source and the drain of the first transistor is connected to the gate of the third transistor, the gate of the second transistor is connected to the first wiring, one of the source and the drain of the second transistor is connected to the fifth wiring, the other of the source and the drain of the second transistor is connected to the gate of the third transistor, one of the source and the drain of the third transistor is connected to the first terminal of the first light-emitting element, the other of the source and the drain of the third transistor is supplied with a first potential, the second terminal of the first light-emitting element is supplied with a second potential, the gate of the fourth transistor is connected to the third wiring, one of the source and the drain of the fourth transistor is connected to the fourth wiring, the other of the source and the drain of the fourth transistor is connected to the gate of the sixth transistor, the gate of the fifth transistor is connected to the second wiring, one of the source and the drain of the fifth transistor is connected to the fifth wiring, the other of the source and the drain of the fifth transistor is connected to the gate of the sixth transistor, one of the source and the drain of the sixth transistor is connected to the first terminal of the second light-emitting element, and the other of the source and the drain of the sixth transistor is supplied with a first potential. 4 transistor, a fifth transistor, a sixth transistor, a first light-emitting element, and a second light-emitting element, a first wiring, a second wiring, a third wiring, a fourth wiring, and a fifth wiring, A light-emitting device having a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first light-emitting element, a second light-emitting element, a first wiring, a second wiring, a third wiring, a fourth wiring, and a fifth wiring, wherein the gate of the first transistor is connected to the second wiring, one of the source and the drain of the first transistor is connected to the fourth wiring, the other of the source and the drain of the first transistor is connected to the gate of the third transistor, the gate of the second transistor is connected to the first wiring, one of the source and the drain of the second transistor is connected to the fifth wiring, the other of the source and the drain of the second transistor is connected to the gate of the third transistor, one of the source and the drain of the third transistor is connected to the first terminal of the first light-emitting element, the other of the source and the drain of the third transistor is supplied with a first potential, the second terminal of the first light-emitting element is supplied with a second potential, the gate of the fourth transistor is connected to the third wiring, one of the source and the drain of the fourth transistor is connected to the fourth wiring, the other of the source and the drain of the fourth transistor is connected to the gate of the sixth transistor, the gate of the fifth transistor is connected to the second wiring, one of the source and the drain of the fifth transistor is connected to the fifth wiring, the other of the source and the drain of the fifth transistor is connected to the gate of the sixth transistor, one of the source and the drain of the sixth transistor is connected to the first terminal of the second light-emitting element, and the other of the source and the drain of the sixth transistor is supplied with a first potential. One of the source and the drain of the first transistor is connected to the fourth wiring, and the other of the source and the drain of the first transistor is connected to the gate of the third transistor. The other of the source and the drain of the first transistor is connected to the gate of the third transistor. The gate of the second transistor is connected to the first wiring, and one of the source and the drain of the second transistor is connected to the fifth wiring. The other of the source and the drain of the second transistor is connected to the gate of the third transistor. One of the source and the drain of the third transistor is connected to the first terminal of the first light-emitting element. The other of the source and the drain of the third transistor is supplied with a first potential, and the second terminal of the first light-emitting element is supplied with a second potential. The gate of the fourth transistor is connected to the third wiring, and one of the source and the drain of the fourth transistor is connected to the fourth wiring. The other of the source and the drain of the fourth transistor is connected to the gate of the sixth transistor. The gate of the fifth transistor is connected to the second wiring, and one of the source and the drain of the fifth transistor is connected to the fifth wiring. The other of the source and the drain of the fifth transistor is connected to the gate of the sixth transistor. One of the source and the drain of the fifth transistor is connected to the fifth wiring, and the other of the source and the drain of the fifth transistor is connected to the gate of the sixth transistor. One of the source and the drain of the sixth transistor is connected to the first terminal of the second light-emitting element. The other of the source and the drain of the sixth transistor is connected to the first terminal of the second light-emitting element. A potential is applied to the second terminal of the second light-emitting element, a second potential is applied to the second terminal of the second light-emitting element, and the fourth wiring transmits image information. A first signal including the first wiring is applied, and the first wiring is selected rather than the first signal being applied to the fourth wiring. The first signal is provided to the fifth wiring at a timing that is earlier than the period during which the first signal is applied.

[0015] In the above embodiment, the first to sixth transistors each contain an oxide semiconductor in a channel formation region. It is preferred.

[0016] In the above embodiment, the oxide semiconductor is indium, zinc, M (M is Ga, Sn, Hf, A It is preferred that the alloy contains at least one of these elements.

[0017] One aspect of the present invention is a display device including the light-emitting device according to the above aspect, a microphone, and an operation key. It is an electronic device.

[0018] In this specification, the term "connection" means electrical connection, and the term "connection" means a state in which a current, a voltage, or a potential is This corresponds to a circuit configuration that can make the signal available for supply or transmission. In addition, a connected circuit configuration does not necessarily refer to a directly connected circuit configuration. , resistors, diodes, etc., so that a current, voltage, or potential can be supplied or transmitted. , indirectly connected through circuit elements such as transistors, inductors, and capacitance elements. Therefore, the pixel 101 may include a transistor, a die, etc., as necessary. It may further include other circuit elements such as electrodes, resistors, capacitors, and inductors. good.

[0019] In addition, even if components that are independent on the circuit diagram are connected, In the case where a conductive film is connected to a plurality of components, for example, when a part of the wiring also functions as an electrode, may also have such functions. In this specification, connection means that even when one conductive film has the functions of a plurality of components, it is included in that category.

[0020] Also, the source terminal of a transistor means a source region that is part of the active layer, or a source electrode connected to the active layer. Similarly, the drain terminal of a transistor means a drain region that is part of the active layer, or a drain electrode connected to the active layer.

[0021] Also, the source terminal and the drain terminal of a transistor change their names depending on the channel type of the transistor and the levels of the potentials applied to the source terminal and the drain terminal. Generally, in an n-channel type transistor, of the source terminal and the drain terminal, the one to which a lower potential is applied is called the source terminal, and the one to which a higher potential is applied is called the drain terminal. Also, in a p-channel type transistor, of the source terminal and the drain terminal, the one to which a lower potential is applied is called the drain terminal, and the one to which a higher potential is applied is called the source terminal. In this specification, for the sake of convenience, when explaining the connection relationship of a transistor, it is assumed that the source terminal and the drain terminal are fixed, but actually, depending on the above potential relationship, the names of the source terminal and the drain terminal are interchanged.

Advantages of the Invention

[0022] According to one aspect of the present invention, it is possible to provide a novel semiconductor device or the like, or to provide a light-emitting device capable of preventing the display of afterimages, or to provide a driving method for a light-emitting device capable of preventing the display of afterimages.

[0023] Alternatively, according to one aspect of the present invention, a light-emitting device capable of displaying image information even at a high scanning frequency is provided, or driving of a light-emitting device capable of displaying image information even at a high scanning frequency can be provided.

[0024] Note that the description of these effects does not prevent the existence of other effects. Note that one aspect of the present invention does not necessarily have all of these effects. Note that other effects will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other effects from the description in the specification, drawings, claims, or any description.

Brief Description of the Drawings

[0025]

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Embodiments for Carrying Out the Invention

[0026] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art can easily understand that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not to be construed as limited to the description of the embodiments shown below.

[0027] Also, in the embodiments described below, the same parts or parts having the same functions are denoted by the same reference numerals are commonly used among different drawings, and the repeated description thereof will be omitted.

[0028] Also, when the same reference numerals are used, especially when it is necessary to distinguish them, identification signs such as ” (n)”, ”(m, n)” may be appended to the reference numerals for description.

[0029] (Embodiment 1) The configuration of a light-emitting device according to an aspect of the present invention is shown as a block diagram in FIG. 1(A) as an example. Note that in the block diagram, the components are classified according to functions and shown as independent blocks from each other. However, in actual components, it is difficult to completely separate them according to functions, and one component may be related to a plurality of functions.

[0030] The light-emitting device 100 shown in FIG. 1(A) includes a pixel portion 102 having a plurality of pixels 101, a signal line driving circuit (source driver) 124, a scanning line driving circuit (gate driver) 125, a panel 103 having, a controller 104, and a power supply circuit 105, and at least includes Pixel 101 includes a light-emitting element and a transistor that controls the operation of the light-emitting element, respectively. Each has it.

[0031] When a signal Sig0 having image information is input, the controller 104 performs signal processing on the signal Sig0 according to the specifications of the panel 103, and has a function of supplying it to the panel 103 as a signal Sig1. Further, the controller 104 has a function of generating a signal Sig2 having no image information and supplying it to the panel 103. When a signal Sig0 having image information is input, the controller 104 performs signal processing on the signal Sig0 according to the specifications of the panel 103, and has a function of supplying it to the panel 103 as a signal Sig1. Further, the controller 104 has a function of generating a signal Sig2 having no image information and supplying it to the panel 103. When a signal Sig0 having image information is input, the controller 104 performs signal processing on the signal Sig0 according to the specifications of the panel 103, and has a function of supplying it to the panel 103 as a signal Sig1. Further, the controller 104 has a function of generating a signal Sig2 having no image information and supplying it to the panel 103. When a signal Sig0 having image information is input, the controller 104 performs signal processing on the signal Sig0 according to the specifications of the panel 103, and has a function of supplying it to the panel 103 as a signal Sig1. Further, the controller 104 has a function of generating a signal Sig2 having no image information and supplying it to the panel 103.

[0032] The power supply circuit 105 has a function of generating a voltage to be supplied to the panel 103, the controller 104, and other various circuits in the light-emitting device 100 from the voltage Vp input to the light-emitting device 100. Further, the power supply circuit 105 has a function of supplying the voltage VDD to each of the plurality of pixels 101 included in the pixel portion 102. Specifically, in FIG. 1(A), the voltage VDD is supplied to each of the plurality of pixels 101 as the potential difference between a fixed potential Vcom such as the ground potential and the potential Vel. The controller 104 has a function of selecting whether or not the power supply circuit 105 supplies the voltage VDD to the plurality of pixels 101. The power supply circuit 105 has a function of generating a voltage to be supplied to the panel 103, the controller 104, and other various circuits in the light-emitting device 100 from the voltage Vp input to the light-emitting device 100. Further, the power supply circuit 105 has a function of supplying the voltage VDD to each of the plurality of pixels 101 included in the pixel portion 102. Specifically, in FIG. 1(A), the voltage VDD is supplied to each of the plurality of pixels 101 as the potential difference between a fixed potential Vcom such as the ground potential and the potential Vel. The controller 104 has a function of selecting whether or not the power supply circuit 105 supplies the voltage VDD to the plurality of pixels 101. The power supply circuit 105 has a function of generating a voltage to be supplied to the panel 103, the controller 104, and other various circuits in the light-emitting device 100 from the voltage Vp input to the light-emitting device 100. Further, the power supply circuit 105 has a function of supplying the voltage VDD to each of the plurality of pixels 101 included in the pixel portion 102. Specifically, in FIG. 1(A), the voltage VDD is supplied to each of the plurality of pixels 101 as the potential difference between a fixed potential Vcom such as the ground potential and the potential Vel. The controller 104 has a function of selecting whether or not the power supply circuit 105 supplies the voltage VDD to the plurality of pixels 101. The power supply circuit 105 has a function of generating a voltage to be supplied to the panel 103, the controller 104, and other various circuits in the light-emitting device 100 from the voltage Vp input to the light-emitting device 100. Further, the power supply circuit 105 has a function of supplying the voltage VDD to each of the plurality of pixels 101 included in the pixel portion 102. Specifically, in FIG. 1(A), the voltage VDD is supplied to each of the plurality of pixels 101 as the potential difference between a fixed potential Vcom such as the ground potential and the potential Vel. The controller 104 has a function of selecting whether or not the power supply circuit 105 supplies the voltage VDD to the plurality of pixels 101. The power supply circuit 105 has a function of generating a voltage to be supplied to the panel 103, the controller 104, and other various circuits in the light-emitting device 100 from the voltage Vp input to the light-emitting device 100. Further, the power supply circuit 105 has a function of supplying the voltage VDD to each of the plurality of pixels 101 included in the pixel portion 102. Specifically, in FIG. 1(A), the voltage VDD is supplied to each of the plurality of pixels 101 as the potential difference between a fixed potential Vcom such as the ground potential and the potential Vel. The controller 104 has a function of selecting whether or not the power supply circuit 105 supplies the voltage VDD to the plurality of pixels 101. The power supply circuit 105 has a function of generating a voltage to be supplied to the panel 103, the controller 104, and other various circuits in the light-emitting device 100 from the voltage Vp input to the light-emitting device 100. Further, the power supply circuit 105 has a function of supplying the voltage VDD to each of the plurality of pixels 101 included in the pixel portion 102. Specifically, in FIG. 1(A), the voltage VDD is supplied to each of the plurality of pixels 101 as the potential difference between a fixed potential Vcom such as the ground potential and the potential Vel. The controller 104 has a function of selecting whether or not the power supply circuit 105 supplies the voltage VDD to the plurality of pixels 101. The power supply circuit 105 has a function of generating a voltage to be supplied to the panel 103, the controller 104, and other various circuits in the light-emitting device 100 from the voltage Vp input to the light-emitting device 100. Further, the power supply circuit 105 has a function of supplying the voltage VDD to each of the plurality of pixels 101 included in the pixel portion 102. Specifically, in FIG. 1(A), the voltage VDD is supplied to each of the plurality of pixels 101 as the potential difference between a fixed potential Vcom such as the ground potential and the potential Vel. The controller 104 has a function of selecting whether or not the power supply circuit 105 supplies the voltage VDD to the plurality of pixels 101.

[0033] Note that the power supply circuit 105 may have a function of controlling the supply of voltage to various circuits included in the panel 103. Note that the power supply circuit 105 may have a function of controlling the supply of voltage to various circuits included in the panel 103.

[0034] The scanning line driving circuit 125 has a function of selecting a plurality of pixels 101 included in the pixel portion 102 row by row. The scanning line driving circuit 125 has a function of selecting a plurality of pixels 101 included in the pixel portion 102 row by row.

[0035] The signal line driving circuit 124 has a function of supplying the signal Sig1 or the signal Sig2 given from the controller 104 to the pixels 101 in the row selected by the scanning line driving circuit 125. The signal line driving circuit 124 has a function of supplying the signal Sig1 or the signal Sig2 given from the controller 104 to the pixels 101 in the row selected by the scanning line driving circuit 125. Do it.

[0036] Here, the signal Sig2 is set to a constant potential that does not include image information. In this case, this potential may be generated by the signal line driving circuit 124 or may be generated by the power supply circuit 105. Also the signal Sig2 may be given the potential Vcom or the potential Vel.

[0037] Next, FIG. 1(B) shows an example of the specific configuration of the pixel 101. The pixel shown in FIG. 1(B) 101 has at least a light emitting element EL1, a transistor M1, a transistor M2, and a transistor M3.

[0038] The light emitting element EL1 includes, within its scope, an element whose luminance is controlled by current or voltage For example, an OLED (organic light emitting diode) or the like can be used as the light emitting element EL1. The OLED has at least an EL layer, an anode, and a cathode. The EL layer is composed of a single layer or a plurality of layers provided between the anode and the cathode, and among these layers, at least a light emitting layer containing a light emitting substance is included. The EL layer is supplied with current when the potential difference between the cathode and the anode, with the cathode as a reference, becomes equal to or higher than the threshold voltage Vthe of the light emitting element EL1. The electroluminescence obtained includes light emission (fluorescence) when returning from the singlet excited state to the ground state and light emission (phosphorescence) when returning from the triplet excited state to the ground state. When the potential difference between the cathode and the anode, with the cathode as a reference, becomes equal to or higher than the threshold voltage Vthe of the light emitting element EL1, electroluminescence is obtained by the current supplied. The electroluminescence includes light emission (fluorescence) when returning from the singlet excited state to the ground state and light emission (phosphorescence) when returning from the triplet excited state to the ground state. Electroluminescence includes light emission (fluorescence) when returning from the singlet excited state to the ground state and light emission (phosphorescence) when returning from the triplet excited state to the ground state. Electroluminescence includes light emission (fluorescence) when returning from the singlet excited state to the ground state and light emission (phosphorescence) when returning from the triplet excited state to the ground state. Electroluminescence includes light emission (fluorescence) when returning from the singlet excited state to the ground state and light emission (phosphorescence) when returning from the triplet excited state to the ground state.

[0039] The transistor M3 has a function of controlling the supply of the power supply voltage corresponding to the potential difference between the potential Vcom and the potential Vel to the light emitting element EL1. That is, the above power supply voltage is supplied to the light emitting element EL1 via the transistor M 3.

[0040] Transistor M1 has a function of controlling the input to the gate electrode of transistor M3 of the signal Sig1 given to panel 103 by controller 104. to the gate electrode of transistor M3.

[0041] Transistor M2 has a function of controlling the input to the gate electrode of transistor M3 of the signal Sig2 given to panel 103 by controller 104. to the gate electrode of transistor M3.

[0042] Specifically, in pixel 101, one of the source terminal and the drain terminal of transistor M3 is connected to wiring ANL to which potential Vel is applied, and the other is connected to either the anode or the cathode of light-emitting element EL1. Also, either the anode or the cathode of light-emitting element EL1 is connected to terminal CTL to which potential Vcom is applied. And one of the source terminal and the drain terminal of transistor M1 is connected to wiring SL1 to which the potential of signal Sig1 is applied, and the other is connected to the gate electrode of transistor M3. A signal for selecting on or off of transistor M1 is input to the gate electrode of transistor M1. Further, one of the source terminal and the drain terminal of transistor M2 is connected to wiring SL2 to which the potential of signal Sig2 is applied, and the other is connected to the gate electrode of transistor M3. A signal for selecting on or off of transistor M2 is input to the gate electrode of transistor M2. to the gate electrode of transistor M3. to the gate electrode of transistor M3. A signal for selecting on or off of transistor M1 is input to the gate electrode of transistor M1. Further, one of the source terminal and the drain terminal of transistor M2 is connected to wiring SL2 to which the potential of signal Sig2 is applied, and the other is connected to the gate electrode of transistor M3. A signal for selecting on or off of transistor M2 is input to the gate electrode of transistor M2. connected to wiring SL2 to which the potential of signal Sig2 is applied, and the other is connected to the gate electrode of transistor M3. A signal for selecting on or off of transistor M2 is input to the gate electrode of transistor M2. to the gate electrode of transistor M3. A signal for selecting on or off of transistor M2 is input to the gate electrode of transistor M2. to the gate electrode of transistor M2. is input.

[0043] And in one aspect of the present invention, in the normal operation state where the pixel portion 102 displays an image , a signal Sig1 having image information is applied to the wiring SL1. Also, a signal Sig2 having no image information is applied to the wiring SL2. The signal Sig2 having no image information is applied to the wiring SL2.

[0044] Using FIG. 2, an example of the operation of the pixel 101 shown in FIG. 1(B) will be described. FIGS. 2(A) to 2(D) schematically show the operation of the pixel 101. In FIGS. 2(A) to 2(D ), a case is illustrated where a capacitor element C1 for holding the gate voltage of the transistor M3 is provided in the pixel 101. However, when the gate capacitance formed between the gate electrode (G) of the transistor M3 and the active layer or the parasitic capacitance of the gate electrode is sufficiently large, it is not always necessary to provide the capacitor element C1 in the pixel 101. Also, in FIGS. 2(A) to 2(D), the transistors M1 and M2 are illustrated as switches. Further, in FIGS. 2(A) to 2(D), an example is shown where the drain terminal (D) of the transistor M3 is connected to the wiring ANL and the source terminal (S) is connected to the light emitting element EL1. In FIGS. 2(A) to 2(D), the transistors M1 and M2 are illustrated as switches. Also, in FIGS. 2(A) to 2(D), an example is shown where the drain terminal (D) of the transistor M3 is connected to the wiring ANL and the source terminal (S) is connected to the light emitting element EL1. The drain terminal (D) of the transistor M3 is connected to the wiring ANL and the source terminal (S) is connected to the light emitting element EL1.

[0045] FIG. 2(A) schematically shows the operation of the pixel 101 when a signal Sig1 having image information is input to the pixel 101. In FIG. 2(A), the potential of the signal Sig1 is applied from the wiring SL1 to the gate electrode of the transistor M3 through the on-transistor M1. Charge is accumulated in the capacitor element C1 according to the above potential. When a power supply voltage is applied between the terminal CTL and the wiring ANL, the value of the drain current of the transistor M3 is determined according to the potential of the signal Sig1, and the luminance of the light emitting element EL1 is determined according to the value of the drain current. In FIG. 2(A), the potential of the signal Sig1 is applied from the wiring SL1 to the gate electrode of the transistor M3 through the on-transistor M1. Charge is accumulated in the capacitor element C1 according to the above potential. When a power supply voltage is applied between the terminal CTL and the wiring ANL, the value of the drain current of the transistor M3 is determined according to the potential of the signal Sig1, and the luminance of the light emitting element EL1 is determined according to the value of the drain current. Charge is accumulated in the capacitor element C1 according to the above potential. When a power supply voltage is applied between the terminal CTL and the wiring ANL, the value of the drain current of the transistor M3 is determined according to the potential of the signal Sig1, and the luminance of the light emitting element EL1 is determined according to the value of the drain current. When a power supply voltage is applied between the terminal CTL and the wiring ANL, the value of the drain current of the transistor M3 is determined according to the potential of the signal Sig1, and the luminance of the light emitting element EL1 is determined according to the value of the drain current. The value of the drain current of the transistor M3 is determined according to the potential of the signal Sig1, and the luminance of the light emitting element EL1 is determined according to the value of the drain current.

[0046] FIG. 2(B) schematically shows the operation of the pixel 101 when the signal Sig1 is held in the pixel 101. as shown. In FIG. 2(B), when the transistor M1 is turned off, the wiring SL1 and the gate electrode of the transistor M3 are electrically disconnected. Therefore, in the capacitor element C1, the stored charge is retained, and the potential of the gate electrode of the transistor M3 is also retained. When a power supply voltage is applied between the terminal CT L and the wiring ANL, the value of the drain current of the transistor M3 and the

[0047] luminance of the light-emitting element EL1 determined according to the potential of the signal Sig1 are maintained even after the transistor M1 is turned off. When the off-current of the transistor M1 is extremely small, it is possible to prevent the charge held in the capacitor element C1 through the transistor M1 from leaking. In this case, after the input of the signal Sig1 to the pixel 101 is completed

[0048] by turning off the transistor M1, the potential of the gate electrode of the transistor M3 is less likely to fluctuate, and therefore, it is possible to prevent the luminance of the light-emitting element EL1 from changing. However, when the off-current of the transistor M1 is extremely small, the charge stored in the capacitor element C1 continues to be held, and then, even if a signal Sig1 having image information different from that in FIG. 2(A) is input, the charge held in the capacitor element C1 cannot be completely replaced, and the previous image information may be displayed as an afterimage in the pixel portion will end up.

[0049] Therefore, in one aspect of the present invention, immediately before the signal Sig1 is supplied to the pixel 101, a signal Sig2 having no image information is input to the pixel 101, and the potential of the gate electrode of the transistor M3 is initialized.

[0050] FIG. 2(D) schematically shows the operation of the pixel 101 when a signal Sig2 having no image information is input to the pixel 101. In FIG. 2(D), the potential of the signal S ig2 is applied from the wiring SL2 to the gate electrode of the transistor M3 via the on transistor M2. When the transistor M3 is an n-channel type, the potential of the signal Sig2 is set to a height such that the gate voltage of the transistor M3 is equal to or lower than the threshold voltage. When the transistor M3 is a p channel type, the potential of the signal Sig2 is set to a height such that the gate voltage of the transistor M3 is equal to or higher than the threshold voltage. Thus, when charges are accumulated in the capacitive element C1 according to the potential of the signal Sig1, the charges are discharged when the potential of the signal Sig2 is input to the pixel 101. Then, the transistor M3 turns off, and the light-emitting element EL1 does not emit light. After that, the signal Sig1 is input to the pixel 101 again, and the luminance of the light-emitting element EL1 is determined according to the potential of the signal Sig1. At this time, since the pixel 101 has been previously initialized by the signal Sig2, no afterimage is displayed on the pixel portion 102. Note that in FIG. 1(B), the case where the transistors M1 to M3 have a single-gate structure is taken as an example.

[0051] Sig1. Sig2 is input to the pixel 101, the charge is released. Then, the transistor M3 turns off, and the light-emitting element EL1 does not emit light. Subsequently, the signal Sig1 is input to the pixel 101 again, and the luminance of the light-emitting element EL1 is determined according to the potential of the signal Sig1. At this time, since the pixel 101 has been previously initialized by the signal Sig2, no afterimage is displayed on the pixel portion 102.

[0052] After that, the signal Sig1 is input to the pixel 101 again, and the luminance of the light-emitting element EL1 is determined according to the potential of the signal Sig1. At this time, since the pixel 101 has been previously initialized by the signal Sig2, no afterimage is displayed on the pixel portion 102. Note that in FIG. 1(B), the case where the transistors M1 to M3 have a single-gate structure is taken as an example. Therefore, the afterimage is not displayed on the pixel portion 102.

[0053] Note that in FIG. 1(B), the case where the transistors M1 to M3 have a single-gate structure is taken as an example. Although shown, these transistors may have a multi-gate structure having a plurality of channel formation regions with a plurality of electrically connected gate electrodes.

[0054] Next, an example of the configuration of the pixel portion 102 will be described. FIG. 3 shows an example of a specific circuit diagram of the pixel portion 102.

[0055] As shown in FIG. 3, the pixel portion 102 includes a plurality of wirings GL, a plurality of wirings SL1, a plurality of wirings SL2, a wiring ANL, and a plurality of pixels 101. As an example, the pixel portion 102 has a configuration in which the pixels 101 are arranged in n rows vertically and m columns horizontally (n and m are integers of 2 or more). Note that the pixel portion 102 is numbered as the first row, the second row to the nth row in order from the pixel 101 at the top of FIG. 3, and the first column, the second column to the mth column in order from the pixel on the left of FIG. 3. The wiring GL is assigned symbols GL(0), GL(1), GL(2) to GL(n) in order from the top. The wiring SL1 is assigned symbols SL1(1), SL1(2) to SL1(m) in order from the left, and similarly, the wiring SL2 is assigned symbols SL2(1), SL2(2) to SL2(m) in order from the left. Each pixel 101 is electrically connected to the terminal CTL.

[0056] In the case of the light-emitting device 100 shown in FIG. 1(A), the plurality of wirings SL1 are connected to the signal line driving circuit 124, the plurality of wirings GL are connected to the scanning line driving circuit 125, and the wiring ANL and the terminal CTL are connected to the power supply circuit 105. Each pixel 101 is connected to one of the plurality of wirings SL1, two of the plurality of wirings GL, one of the plurality of wirings SL2, and the wiring ANL. ​In NL, it is connected. All pixels 101 are connected to terminal CTL.

[0057] In the pixel 101 of the k-th row (k is an integer of 1 or more), the gate electrode of transistor M1 is arranged connected to wiring GL(k). That is, when wiring GL(k) is selected, transistor M1 turns on, and signal Sig1 is input from wiring SL1 to the pixel 101 of the k-th row through transistor M1.

[0058] Also, in the pixel 101 of the (k + 1)-th row, the gate electrode of transistor M2 is connected to the wiring GL(k) existing in the row above. That is, when wiring GL(k) is selected, transistor M2 turns on, and signal Sig2 is input from wiring SL2 to the pixel 101 of the (k + 1)-th row through transistor M2, and the pixel 101 is initialized.

[0059] When the signal Sig1 having image information is input to the pixel 101, the light emission state of the light emitting element EL1 is determined according to the potential of the signal Sig1. Specifically, when transistor M3 is on according to the potential of the signal Sig1, the light emitting element EL1 is supplied with current and enters the light emission state. Also, when transistor M3 is off according to the potential of the signal Sig1 or the signal Sig2, the supply of current to the light emitting element EL1 is not performed, and the light emitting element EL1 enters the non-light emission state.

[0060] The operation of the pixel portion 102 will be described using the timing chart shown in FIG. 4. FIG. 4 shows the potential supplied to the plurality of wirings GL (GL(0) to GL(n)) shown in FIG. 3, the signal Sig1 supplied to the wiring SL1 shown in FIG. 3, and the signal supplied to the wiring SL2 shown in FIG. 3. is the potential supplied to the plurality of wirings GL (GL(0) to GL(n)) shown in FIG. 3, the signal Sig1 supplied to the wiring SL1 shown in FIG. 3, and the signal supplied to the wiring SL2 shown in FIG. 3. ​​​​​​​​​​​FIG. 4 shows an example of a timing chart for Sig2. The figure shows a timing chart in which one frame period is divided into n+1 periods from period p0 to period pn. The timing chart shown in FIG. 4 is based on the timing chart shown in FIG. This is an example in which the transistor is an n-channel type.

[0061] The signal Sig2 is maintained at a constant potential from the period p0 through the period pn.

[0062] First, in a period p0, the line GL(0) is selected, so that a signal is applied to the pixel 101 in the first row. A signal Sig2 is input and the pixel is initialized.

[0063] Next, during a period p1, the wiring GL(0) is deselected (a low-level potential is applied). ), the line GL(1) is selected. When the line GL(1) is selected, the pixel 101 in the first row At the same time, a signal Sig2 is applied to the pixels 101 in the second row. Then, the pixel is initialized.

[0064] Next, in a period p2, the line GL(1) is deselected, and the pixel 101 in the first row The state of period p1 is maintained until a signal is input. When the wiring GL(2) is selected, A signal Sig1 is input to the pixels 101 in the second row. At the same time, a signal Sig2 is given and the pixel is initialized.

[0065] By repeating the above operation until the wiring GL(n) is selected, the initialization by the signal Sig2 is performed. The signal Sig1 is input in order from the pixel 101 in the first row to the pixel 101 in the nth row. An image can be displayed on the element 102 .

[0066] As described above, by synchronizing the timing at which the signal Sig2 is input to the pixel with the selection of the wiring GL, even when the scanning frequency of the light-emitting device 100 is set to a high frequency, the input of the signal Sig2 to the pixel 101 can be performed without delay. As described above, by synchronizing the timing at which the signal Sig2 is input to the pixel with the selection of the wiring GL, even when the scanning frequency of the light-emitting device 100 is set to a high frequency, the input of the signal Sig2 to the pixel 101 can be performed without delay. As described above, by synchronizing the timing at which the signal Sig2 is input to the pixel with the selection of the wiring GL, even when the scanning frequency of the light-emitting device 100 is set to a high frequency, the input of the signal Sig2 to the pixel 101 can be performed without delay.

[0067] FIG. 5 is a circuit diagram in the circuit diagram of FIG. 3 when the wiring ANL is arranged in the horizontal direction of the pixel portion 102 without changing the connection relationship between each element and the wiring. FIG. 5 is a circuit diagram in the circuit diagram of FIG. 3 when the wiring ANL is arranged in the horizontal direction of the pixel portion 102 without changing the connection relationship between each element and the wiring.

[0068] In the circuit diagram of FIG. 3 or FIG. 5, the wiring SL2 may be connected to the terminal CTL, for example (see FIG. 6). In the circuit diagram of FIG. 3 or FIG. 5, the wiring SL2 may be connected to the terminal CTL, for example (see FIG. 6).

[0069] Alternatively, in the circuit diagram of FIG. 3 or FIG. 5, for example, without providing the wiring SL2, either the source terminal or the drain terminal of the transistor M2 may be connected to the terminal CTL, and the other may be connected to the gate electrode of the transistor M3 (see FIG. 7). Alternatively, in the circuit diagram of FIG. 3 or FIG. 5, for example, without providing the wiring SL2, either the source terminal or the drain terminal of the transistor M2 may be connected to the terminal CTL, and the other may be connected to the gate electrode of the transistor M3 (see FIG. 7). Alternatively, in the circuit diagram of FIG. 3 or FIG. 5, for example, without providing the wiring SL2, either the source terminal or the drain terminal of the transistor M2 may be connected to the terminal CTL, and the other may be connected to the gate electrode of the transistor M3 (see FIG. 7).

[0070] Alternatively, in the circuit diagram of FIG. 3 or FIG. 5, for example, without providing the wiring SL2, either the source terminal or the drain terminal of the transistor M2 may be connected to the source of the transistor M3, and the other may be connected to the gate electrode of the transistor M3 (see FIG. 8). Alternatively, in the circuit diagram of FIG. 3 or FIG. 5, for example, without providing the wiring SL2, either the source terminal or the drain terminal of the transistor M2 may be connected to the source of the transistor M3, and the other may be connected to the gate electrode of the transistor M3 (see FIG. 8). Alternatively, in the circuit diagram of FIG. 3 or FIG. 5, for example, without providing the wiring SL2, either the source terminal or the drain terminal of the transistor M2 may be connected to the source of the transistor M3, and the other may be connected to the gate electrode of the transistor M3 (see FIG. 8). By doing so, when the transistor M2 is turned on, the capacitive element C1 is short-circuited, and the pixel 101 is initialized. By doing so, when the transistor M2 is turned on, the capacitive element C1 is short-circuited, and the pixel 101 is initialized.

[0071] Note that this embodiment can be implemented in appropriate combination with other embodiments.

[0072] (Embodiment 2) In this embodiment, one aspect of the present invention will be described with reference to FIG. 9. One aspect of the present invention is effective when the signal Sig1 is input at a high scanning frequency, such as double-speed driving. As the scanning frequency increases, the period during which the signal Sig1 is input becomes shorter, and there may be a case where the potential for Sig1 cannot be sufficiently written into the pixel. However, one aspect of the present invention can solve the above problem.

[0073] A timing chart showing one aspect of the present invention is shown in FIG. 9. FIG. 9 shows the timing when, in Embodiment 1, a signal identical to the signal Sig1 is input as the signal Sig2 to the wiring SL2 at a timing earlier than the period during which the wiring GL is selected, rather than the signal Sig1 being applied to the wiring SL1. The data of the signal Sig1 and the signal Sig2 will be referred to as signals S1, S2, S3, and Sn for each divided period.

[0074] In the period p0 of FIG. 9, when the wiring GL(0) is selected and the signal S1 is applied as the signal Sig2 to the wiring SL2, the signal S1 is input to the pixel 101 in the first row. In the period p0, the gate electrode of the transistor M3 of the pixel 101 in the first row is pre-charged by the signal S1.

[0075] Next, in the period p1, when the wiring GL(1) is selected and the signal S1 is input again as the signal Sig1 to the pixel 101 in the first row via the transistor M1. That is, the signal S1 is input to the pixel 101 in the first row over two periods from the period p0 to the period p1. Also, in the period p1, the pre-charge of the gate electrode of the transistor M3 of the pixel 101 in the second row by the signal Sig2 is performed simultaneously. ​​​​​​​​​​

[0076] For example, even if the period given to the input of signal Sig1 is halved by double-speed driving , since the input from signal Sig2 is supplemented, the total input period of signal S1 does not become half , and the input of signal S1 is performed without problems.

[0077] By performing the above operation until wiring GL(n) is selected, even in double-speed driving, data from signal S1 to signal Sn can be input to pixel section 102 without problems.

[0078] Note that this embodiment can be implemented in appropriate combination with other embodiments.

[0079] (Embodiment 3) In this embodiment, an example of a more detailed configuration of the light-emitting device 100 shown in FIG. 1(A) will be described.

[0080] FIG. 10 shows, as an example, a block diagram of the configuration of a light-emitting device according to an aspect of the present invention. The light-emitting device 100 shown in FIG. 10 has a pixel section 102 having a plurality of pixels 101, a signal line driving circuit (source driver) 124, a scanning line driving circuit (gate driver) 125, a panel 103 having these, a controller 104, and a power supply circuit 105, similar to the case of FIG. 1(A). Further, the light-emitting device 100 shown in FIG. 10 has an input device 120, a CPU 121, an image processing circuit 122, and an image memory 123.

[0081] The input device 120 has a function of giving information and commands to the CPU 121 included in the light-emitting device 100. For example, from the input device 120, a command for shifting the pixel section 102 from an operating state to a non-operating state, or a command for shifting the pixel section 102 from a non-operating state to an operating state is given to the CPU 121 included in the light-emitting device 100. Commands can be given to the CPU 121. As the input device 120, a keyboard, a pointing device, a touch panel, or the like can be used.

[0082] The CPU 121 decodes the commands input from the input device 120 and has the function of executing the commands by comprehensively controlling the operations of various circuits

[0083] possessed by the light emitting device 100. For example, when a command to shift the pixel unit 102 from the operating state to the non-operating state is sent from the input device 120, the CPU 121 issues a command to

[0084] the controller 104 to stop the supply of the power voltage from the power supply circuit 105 to the pixel unit 102. Or, when a command to shift the pixel unit 102 from the non-operating state to the

[0085] operating state is sent from the input device 120, the CPU 121 issues a command to the controller 104 to resume the supply of the power voltage from the power supply circuit 105 to the pixel unit 102. The image memory 123 has the function of storing the image data 126 input to the light emitting device 100. In FIG. 10, the case where only one image memory 123 is provided in the light emitting device 100 is illustrated, but a plurality of image

[0086] memories 123 may be provided in the light emitting device 100. For example, when a Memory), SRAM (Static Random Access Memor y), etc. can be used. Alternatively, VRAM (Vi deo RAM) may be used for the image memory 123.

[0087] The image processing circuit 122, in accordance with instructions from the controller 104, writes the image data 126 to the image memory 123 and reads the image data 126 from the image memory 123, and has a function of generating a signal Sig1 from the image data 126.

[0088] Note that the controller 104 has a function of supplying various drive signals used for driving, such as the signal line drive circuit 124 and the scan line drive circuit 125, to the panel 103. The drive signals include a start pulse signal SSP for controlling the operation of the signal line drive circuit 124, a clock signal SCK , a latch signal LP, a start pulse signal GSP for controlling the operation of the scan line drive circuit 125, , a clock signal GCK, and the like.

[0089] Note that this embodiment can be implemented in appropriate combination with other embodiments.

[0090] (Embodiment 4) In this embodiment, the light-emitting device, the cross-sectional structure, and the layout of the transistor shown in the above embodiment will be described with reference to the drawings.

[0091] <Cross-sectional Structure of Light-Emitting Device> FIG. 11 shows, as an example, the cross-sectional structure of a pixel portion of a light-emitting device according to one aspect of the present invention. Note that , in FIG. 11, the cross-sectional structures of the transistor M3, the capacitor element C1, and the light-emitting element EL1 included in the pixel 101 shown in FIG. 3 are illustrated.

[0092] Specifically, the light-emitting device shown in FIG. 11 includes a transistor M3 and a capacitor element C1 on a substrate 400. The transistor M3 includes a conductive film 401 that functions as a gate, an insulating film 402 on the conductive film 401, a semiconductor film 403 that overlaps the conductive film 401 with the insulating film 402 interposed therebetween, and a conductive film 404 and a conductive film 405 that function as a source or a drain electrically connected to the semiconductor film 403.

[0093] The capacitor element C1 includes a conductive film 401 that functions as an electrode, an insulating film 402 on the conductive film 401, and a conductive film 404 that overlaps the conductive film 401 with the insulating film 402 interposed therebetween and functions as an electrode.

[0094] As the insulating film 402, an insulating film containing at least one of aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, oxynitride silicon, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide may be used singly or in a stacked manner. In this specification, oxynitride refers to a material having a higher oxygen content than nitrogen in its composition, and oxynitride refers to a material having a higher nitrogen content than oxygen in its composition.

[0095] An insulating film 411 is provided on the semiconductor film 403, the conductive film 404, and the conductive film 405. When an oxide semiconductor is used as the semiconductor film 403, it is desirable to use a material that can supply oxygen to the semiconductor film 403 for the insulating film 411. By using the above material for the insulating film 411, it is possible to move the oxygen contained in the insulating film 411 to the semiconductor film 403. It is possible to reduce the oxygen deficiency amount of the semiconductor film 403. The transfer of oxygen contained in the insulating film 411 to the semiconductor film 403 can be efficiently performed by performing a heat treatment after forming the insulating film 411. An insulating film 420 is provided on the insulating film 411, and a conductive film 424 is provided on the insulating film 420. The conductive film 424 is connected to the conductive film 404 at the opening provided in the insulating film 411 and the insulating film 420.

[0096] An insulating film 425 is provided on the insulating film 420 and the conductive film 424. The insulating film 425 has an opening at a position overlapping the conductive film 424. Also, on the insulating film 425, an insulating film 426 is provided at a position different from the opening of the insulating film 425. Then, on the insulating film 425 and the insulating film 426, an EL layer 427 and a conductive film 428 are provided so as to be laminated in order. The portion where the EL layer 427 contacts the upper surface of the conductive film 424 and the lower surface of the conductive film 428 functions as a light-emitting element EL1. And one of the conductive film 424 and the conductive film 428 functions as an anode, and the other functions as a cathode.

[0097]

[0098] The light-emitting device also has a substrate 430 that faces the substrate 400 with the light-emitting element EL1 interposed therebetween. On the substrate 430, that is, on the surface of the substrate 430 closer to the light-emitting element EL1, a shielding film 431 having a function of shielding light is provided. And the shielding film 431 has an opening in the region overlapping the light-emitting element EL1. In the opening overlapping the light-emitting element EL1, a coloring layer 432 that transmits visible light in a specific wavelength range is provided on the substrate 430.

[0099] Note that the insulating film 426 adjusts the distance between the light-emitting element EL1 and the substrate 430, and may be omitted depending on the situation.

[0100] In addition, in this embodiment, a top emission structure is shown in which the light of the light-emitting element EL1 is extracted from the side opposite to the element substrate, but a bottom emission structure in which the light of the light-emitting element EL1 is extracted from the element substrate side, or a dual emission structure in which the light of the light-emitting element EL1 is extracted from both the element substrate side and the side opposite to the element substrate can also be an aspect of the present invention.

[0101] 〈Pixel layout〉 Next, an example of the layout of the pixel 101 shown in FIG. 5 will be described. FIG. 12 shows a top view of the pixel 101 shown in FIG. 5 as an example. In FIG. 12, various insulating films and the light-emitting element EL1 (including the conductive film 424, the EL layer 427, and the conductive film 428) are omitted in order to clarify the layout of the pixel 101.

[0102] FIG. 12 shows the layout of the pixels 101a and 101b arranged vertically.

[0103] In the pixel 101a, the transistor M1 has a conductive film 501 having a function as a gate, a semiconductor film 511, and conductive films 521 and 524 that are electrically connected to the semiconductor film 511 and have a function as a source or a drain. The conductive film 501 has a function as a wiring GL.

[0104] In the pixel 101a, the transistor M2 has a conductive film 502 having a function as a gate, a semiconductor film 512, and conductive films 522 and 525 that are electrically connected to the semiconductor film 512 and have a function as a source or a drain. ​​​​​​​​​​​It has a conductive film 522 and a conductive film 524 having such functions. The conductive film 502 is the conductive film 52 3 is electrically connected to a wiring GL (not shown) of the pixel above through it.

[0105] In pixel 101a, transistor M3 has a conductive film 503 having a function as a gate a semiconductor film 513, and conductive films 525 and 526 that are electrically connected to the semiconductor film 513 and have functions as a source or a drain. The conductive film 526 is electrically connected to the conductive film 50 4. It is electrically connected.

[0106] In pixel 101a, the capacitor element C1 has a conductive film 503, a conductive film 525, and an insulating film (not shown) provided between the conductive film 50 3 and the conductive film 525. The conductive film 503 is electrically connected to the conductive film 524.

[0107] In pixel 101a, the conductive film 504 has a function as a wiring ANL.

[0108] In pixel 101a, the conductive film 501 is electrically connected to the conductive film 527.

[0109] In pixel 101b, transistor M1 has a conductive film 505 having a function as a gate a semiconductor film 514, and conductive films 521 and 528 that are electrically connected to the semiconductor film 514 and have functions as a source or a drain. The conductive film 505 has a function as a wiring GL and. It has a function.

[0110] In pixel 101b, transistor M2 has a conductive film 506 having a function as a gate a semiconductor film 515, and conductive films 521 and 528 that are electrically connected to the semiconductor film 515 and have functions as a source or a drain. The conductive film 505 has a function as a wiring GL It has a conductive film 522 and a conductive film 528 having such functions. The conductive film 506 is electrically connected to the conductive film 501 of the pixel 101a via the conductive film 52 7.

[0111] In pixel 101b, transistor M3 has a conductive film 507 having a function as a gate, a semiconductor film 516, and conductive films 529 and 530 that are electrically connected to the semiconductor film 516 and have functions as a source or a drain. The conductive film 530 is electrically connected to the conductive film 50 8. It has a conductive film 529 and a conductive film 530 having such functions. The conductive film 530 is electrically connected to the conductive film 50 8.

[0112] In pixel 101b, capacitor C1 has a conductive film 507, a conductive film 529, and an insulating film (not shown) provided between the conductive film 50 7 and the conductive film 529. The conductive film 507 is electrically connected to the conductive film 52 8.

[0113] In pixel 101b, the conductive film 508 has a function as wiring ANL.

[0114] In pixel 101b, the conductive film 505 is electrically connected to the gate of transistor M2 included in the pixel one below via the conductive film 531.

[0115] The conductive films 501 to 508 can be fabricated in the same process.

[0116] The semiconductor films 511 to 516 can be fabricated in the same process.

[0117] The conductive films 521 to 531 can be fabricated in the same process.

[0118] The conductive film 521 has a function as wiring SL1.

[0119] The conductive film 522 has a function as wiring SL2. ​

[0120] In FIG. 12, pixels located above and below are electrically connected to each other via conductive films 523, 527, and 531. 11. However, instead of the conductive films 523, 527, and 531, for example, the conductive film 42 in FIG. The pixels may be electrically connected to each other via a conductive film fabricated in the same process as in 4.

[0121] <Transistor structure> Next, a structure of a transistor 70 having a channel formation region in an oxide semiconductor film will be described as an example. Shown below.

[0122] The transistor 70 shown in FIG. 13A includes a conductive film 80 functioning as a gate and a conductive film 8 0, and an oxide semiconductor film 82 overlapping the conductive film 80 with the insulating film 81 sandwiched therebetween. A conductive film 83 serving as a source and a drain connected to the oxide semiconductor film 82 and 13A includes an oxide semiconductor film and a conductive film 84. 82, insulating films 85 to 87 are stacked in order on the conductive film 83 and the conductive film 84. do.

[0123] 13A, a conductive film is formed on the oxide semiconductor film 82, the conductive film 83, and the conductive film 84 in this order. In the example shown, the insulating films 85 to 87 are formed on the oxide semiconductor layer. The insulating film provided on the conductive film 82, the conductive film 83, and the conductive film 84 may be a single layer or a double layer. Alternatively, it may be a multi-layer structure having three or more layers.

[0124] The insulating film 86 contains oxygen in a stoichiometric amount or more, and a part of the oxygen is removed by heating. It is preferable that the insulating film has a function of supplying the insulating film to the oxide semiconductor film 82. 86 is preferably one having few defects, typically due to dangling bonds of silicon. The density of the peaks of the ESR spectrum (an asymmetric ESR spectrum with a g value appearing in the vicinity of 2.01) is preferably 1 × 10 18 spins / cm 3 or less. However, when the insulating film 86 is provided directly on the oxide semiconductor film 82, the oxide semiconductor film 8 2 may be damaged during the formation of the insulating film 86. As shown in FIG. 13(A), it is preferable to provide the insulating film 85 between the oxide semiconductor film 82 and the insulating film 86. The insulating film 85 causes less damage to the oxide semiconductor film 8 2 during its formation than the insulating film 86, and is desirably an insulating film having a function of permeating oxygen. However, since the insulating film 86 can be directly formed on the oxide semiconductor film 82 while suppressing the damage to the oxide semiconductor film 82 to a small level if possible, the insulating film 85 does not necessarily have to be provided.

[0125] The insulating film 85 preferably has few defects. Typically, the density of spins in the vicinity of g = 2.001 derived from silicon dangling bonds obtained by ESR measurement is 3 × 10 17 spins / cm 3 or less. This is because if the density of defects contained in the insulating film 85 is high, oxygen binds to the defects, resulting in a decrease in the oxygen permeation amount in the insulating film 85

[0126] In addition, it is preferable that there are few defects at the interface between the insulating film 85 and the oxide semiconductor film 82. Typically, by ESR measurement with the magnetic field applied parallel to the film surface, the density of spins having a g value derived from oxygen deficiency in the oxide semiconductor used for the oxide semiconductor film 82 is 1.89 or more and 1.96 or less is preferably 1 × 10 17 spins / cm3 Furthermore, it is preferably below the detection lower limit. This is preferable.

[0127] In addition, it is desirable that the insulating film 87 has a blocking effect of preventing the diffusion of oxygen, hydrogen, and water. Alternatively, it is desirable that the insulating film 87 has a blocking effect of preventing the diffusion of hydrogen and water. This is desirable.

[0128] The higher the density and compactness of the insulating film, and the fewer the unbonded hands and the more chemically stable it is, the higher the blocking effect it exhibits. An insulating film that exhibits a blocking effect of preventing the diffusion of oxygen, hydrogen, and water can be formed, for example, using aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, etc. An insulating film that exhibits a blocking effect of preventing the diffusion of hydrogen and water can be formed, for example, using silicon nitride, silicon oxynitride, etc. When the insulating film 87 has a blocking effect of preventing the diffusion of water, hydrogen, etc., impurities such as resin inside the panel and water and hydrogen existing outside the panel can be prevented from entering the oxide semiconductor film 82. When an oxide semiconductor is used for the oxide semiconductor film 82, a part of the water or hydrogen that has entered the oxide semiconductor becomes an electron donor (donor). Therefore, by using the insulating film 87 having the above blocking effect, the threshold voltage of the transistor 70 can be prevented from shifting due to the generation of donors. For example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, etc. can be used for the insulating film that exhibits a blocking effect of preventing the diffusion of oxygen, hydrogen, and water. For example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, etc. can be used for the insulating film that exhibits a blocking effect of preventing the diffusion of oxygen, hydrogen, and water. For example, silicon nitride, silicon oxynitride, etc. can be used for the insulating film that exhibits a blocking effect of preventing the diffusion of hydrogen and water. For example, silicon nitride, silicon oxynitride, etc. can be used for the insulating film that exhibits a blocking effect of preventing the diffusion of hydrogen and water.

[0129] When the insulating film 87 has a blocking effect of preventing the diffusion of water, hydrogen, etc., impurities such as resin inside the panel and water and hydrogen existing outside the panel can be prevented from entering the oxide semiconductor film 82. When an oxide semiconductor is used for the oxide semiconductor film 82, a part of the water or hydrogen that has entered the oxide semiconductor becomes an electron donor (donor). Therefore, by using the insulating film 87 having the above blocking effect, the threshold voltage of the transistor 70 can be prevented from shifting due to the generation of donors. When an oxide semiconductor is used for the oxide semiconductor film 82, a part of the water or hydrogen that has entered the oxide semiconductor becomes an electron donor (donor). Therefore, by using the insulating film 87 having the above blocking effect, the threshold voltage of the transistor 70 can be prevented from shifting due to the generation of donors. When an oxide semiconductor is used for the oxide semiconductor film 82, a part of the water or hydrogen that has entered the oxide semiconductor becomes an electron donor (donor). Therefore, by using the insulating film 87 having the above blocking effect, the threshold voltage of the transistor 70 can be prevented from shifting due to the generation of donors. When an oxide semiconductor is used for the oxide semiconductor film 82, a part of the water or hydrogen that has entered the oxide semiconductor becomes an electron donor (donor). Therefore, by using the insulating film 87 having the above blocking effect, the threshold voltage of the transistor 70 can be prevented from shifting due to the generation of donors. This can be prevented.

[0130] In addition, when an oxide semiconductor is used for the oxide semiconductor film 82, since the insulating film 87 has a blocking effect of preventing the diffusion of oxygen, the diffusion of oxygen from the oxide semiconductor to the outside can be prevented. In addition, when an oxide semiconductor is used for the oxide semiconductor film 82, since the insulating film 87 has a blocking effect of preventing the diffusion of oxygen, the diffusion of oxygen from the oxide semiconductor to the outside can be prevented. This makes it possible. Therefore, in the oxide semiconductor, since oxygen deficiencies serving as donors are reduced, it is possible to prevent the threshold voltage of the transistor 70 from shifting due to the generation of donors.

[0131] Note that in FIG. 13(A), a case where the oxide semiconductor film 82 is composed of a three-layer stacked oxide semiconductor film is illustrated. Specifically, in the transistor 70 shown in FIG. 13(A), as the oxide semiconductor film 82, an oxide semiconductor film 82a to an oxide semiconductor film 82c are stacked in order from the side of the insulating film 81. The oxide semiconductor film 82 of the transistor 70 is not necessarily composed of a plurality of stacked oxide semiconductor films, and may be composed of a single-layer oxide semiconductor film.

[0132] And the oxide semiconductor film 82a and the oxide semiconductor film 82c contain at least one of the metal elements constituting the oxide semiconductor film 82b, and the energy of the lower end of the conduction band is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0 .15 eV or more, and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less, and is an oxide film close to the vacuum level. Further, when the oxide semiconductor film 82b contains at least indium, it is preferable because the carrier mobility increases.

[0133] Also, as shown in FIG. 13(B), the transistor 70 may have a configuration in which the oxide semiconductor film 82c is provided so as to overlap with the insulating film 85 on the upper layers of the conductive films 83 and 84.

[0134] Note that impurities such as moisture or hydrogen serving as electron donors (donors) are reduced, and in addition, an acid ​​​​​​​​​An oxide semiconductor (purified Oxide Semiconductor) purified by reducing elemental deficiencies has few carrier generation sources, so it can be of type i (intrinsic semiconductor) or extremely close to type i. Therefore, a transistor having a channel formation region in a purified oxide semiconductor film has an extremely small off-current and high reliability. And a transistor in which a channel formation region is formed in the oxide semiconductor film tends to have electrical characteristics (also referred to as normally-off characteristics) in which the threshold voltage is positive. Specifically, the small off-current of a transistor having a channel formation region in a purified oxide semiconductor film can be proven by various experiments. For example, even in an element with a channel width of 1×10 μm and a channel length of 10 μm, when the voltage between the source electrode and the drain electrode (drain voltage) is in the range of 1 V to 10 V, the off-current is below the measurement limit of a semiconductor parameter analyzer, that is, 1×10 A or less. In this case, it can be seen that the off-current normalized by the channel width of the transistor is 100 zA / μm or less. Also, a circuit that connects a capacitor element and a transistor and controls the charge flowing into or out of the capacitor element with the transistor is used to measure the off-current. In this measurement, a purified oxide semiconductor film is used for the channel formation region of the transistor, and the off-current of the transistor is measured from the change in the charge amount per unit time of the capacitor element. As a result, it was found that when the voltage between the source electrode and the drain electrode of the transistor is 3 V, an even smaller off-current of several tens yA / μm can be obtained. And a transistor in which a channel formation region is formed in the oxide semiconductor film tends to have electrical characteristics (also referred to as normally-off characteristics) in which the threshold voltage is positive. Specifically, the small off-current of a transistor having a channel formation region in a purified oxide semiconductor film can be proven by various experiments. For example, even in an element with a channel width of 1×10 μm and a channel length of 10 μm, when the voltage between the source electrode and the drain electrode (drain voltage) is in the range of 1 V to 10 V, the off-current is below the measurement limit of a semiconductor parameter analyzer, that is, 1×10 A or less.

[0135] In this case, it can be seen that the off-current normalized by the channel width of the transistor is 100 zA / μm or less. Also, a circuit that connects a capacitor element and a transistor and controls the charge flowing into or out of the capacitor element with the transistor is used to measure the off-current. In this measurement, a purified oxide semiconductor film is used for the channel formation region of the transistor, and the off-current of the transistor is measured from the change in the charge amount per unit time of the capacitor element. As a result, it was found that when the voltage between the source electrode and the drain electrode of the transistor is 3 V, an even smaller off-current of several tens yA / μm can be obtained. For example, even in an element with a channel width of 1×10 μm and a channel length of 10 μm, when the voltage between the source electrode and the drain electrode (drain voltage) is in the range of 1 V to 10 V, the off-current is below the measurement limit of a semiconductor parameter analyzer, that is, 1×10 A or less. 0 6 μm and the channel length is 10 μm, the off-current can be made to have the characteristic of being below the measurement limit of a semiconductor parameter analyzer, that is, 1×10 A or less, even when the voltage between the source electrode and the drain electrode (drain voltage) is in the range of 1 V to 10 V. In this case, it can be seen that the off-current normalized by the channel width of the transistor is 100 zA / μm or less. Also, a circuit that connects a capacitor element and a transistor and controls the charge flowing into or out of the capacitor element with the transistor is used to measure the off-current. In this measurement, a purified oxide semiconductor film is used for the channel formation region of the transistor, and the off-current of the transistor is measured from the change in the charge amount per unit time of the capacitor element. As a result, it was found that when the voltage between the source electrode and the drain electrode of the transistor is 3 V, an even smaller off-current of several tens yA / μm can be obtained. A or less. -13 In this case, it can be seen that the off-current normalized by the channel width of the transistor is 100 zA / μm or less. Also, a circuit that connects a capacitor element and a transistor and controls the charge flowing into or out of the capacitor element with the transistor is used to measure the off-current. In this measurement, a purified oxide semiconductor film is used for the channel formation region of the transistor, and the off-current of the transistor is measured from the change in the charge amount per unit time of the capacitor element. As a result, it was found that when the voltage between the source electrode and the drain electrode of the transistor is 3 V, an even smaller off-current of several tens yA / μm can be obtained. In this case, it can be seen that the off-current normalized by the channel width of the transistor is 100 zA / μm or less. Also, a circuit that connects a capacitor element and a transistor and controls the charge flowing into or out of the capacitor element with the transistor is used to measure the off-current. In this measurement, a purified oxide semiconductor film is used for the channel formation region of the transistor, and the off-current of the transistor is measured from the change in the charge amount per unit time of the capacitor element. As a result, it was found that when the voltage between the source electrode and the drain electrode of the transistor is 3 V, an even smaller off-current of several tens yA / μm can be obtained. In this case, it can be seen that the off-current normalized by the channel width of the transistor is 100 zA / μm or less. Also, a circuit that connects a capacitor element and a transistor and controls the charge flowing into or out of the capacitor element with the transistor is used to measure the off-current. In this measurement, a purified oxide semiconductor film is used for the channel formation region of the transistor, and the off-current of the transistor is measured from the change in the charge amount per unit time of the capacitor element. As a result, it was found that when the voltage between the source electrode and the drain electrode of the transistor is 3 V, an even smaller off-current of several tens yA / μm can be obtained. Also, a circuit that connects a capacitor element and a transistor and controls the charge flowing into or out of the capacitor element with the transistor is used to measure the off-current. In this measurement, a purified oxide semiconductor film is used for the channel formation region of the transistor, and the off-current of the transistor is measured from the change in the charge amount per unit time of the capacitor element. As a result, it was found that when the voltage between the source electrode and the drain electrode of the transistor is 3 V, an even smaller off-current of several tens yA / μm can be obtained. In this measurement, a purified oxide semiconductor film is used for the channel formation region of the transistor, and the off-current of the transistor is measured from the change in the charge amount per unit time of the capacitor element. As a result, it was found that when the voltage between the source electrode and the drain electrode of the transistor is 3 V, an even smaller off-current of several tens yA / μm can be obtained. In this measurement, a purified oxide semiconductor film is used for the channel formation region of the transistor, and the off-current of the transistor is measured from the change in the charge amount per unit time of the capacitor element. As a result, it was found that when the voltage between the source electrode and the drain electrode of the transistor is 3 V, an even smaller off-current of several tens yA / μm can be obtained. As a result, it was found that when the voltage between the source electrode and the drain electrode of the transistor is 3 V, an even smaller off-current of several tens yA / μm can be obtained. As a result, it was found that when the voltage between the source electrode and the drain electrode of the transistor is 3 V, an even smaller off-current of several tens yA / μm can be obtained. And, a transistor using a highly purified oxide semiconductor film for the channel formation region has an off-current that is significantly smaller than that of a transistor using crystalline silicon.

[0136] When an oxide semiconductor film is used as the semiconductor film, the oxide semiconductor preferably contains at least indium (In) or zinc (Zn). Further, as a stabilizer for reducing the variation in the electrical characteristics of a transistor using the oxide semiconductor film, it preferably has gallium (Ga) in addition to them. Further, it preferably has tin (Sn) as a stabilizer. Further, it preferably has hafnium (Hf) as a stabilizer. Further, it preferably has aluminum (Al) as a stabilizer. Further, it preferably contains zirconium (Zr) as a stabilizer.

[0137] Among oxide semiconductors, In-Ga-Zn-based oxides, In-Sn-Zn-based oxides, etc. are different from silicon carbide, gallium nitride, or gallium oxide, and transistors with excellent electrical characteristics can be fabricated by sputtering or wet methods, and have advantages such as excellent mass productivity. Also, different from silicon carbide, gallium nitride, or gallium oxide, the above In-Ga-Zn-based oxide can fabricate transistors with excellent electrical characteristics on a glass substrate. Also, it can cope with the enlargement of the substrate size.

[0138] Also, as other stabilizers, lanthanoids such as lanthanum (La), cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol mium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lut etium (Lu) may contain any one or more of them.

[0139] For example, as the oxide semiconductor, indium oxide, gallium oxide, tin oxide, zinc oxide, I n-Zn-based oxide, Sn-Zn-based oxide, Al-Zn-based oxide, Zn-Mg-based oxide, S n-Mg-based oxide, In-Mg-based oxide, In-Ga-based oxide, In-Ga-Zn-based oxid e (also denoted as IGZO), In-Al-Zn-based oxide, In-Sn-Zn-based oxide, Sn-Ga-Zn-based oxide, Al-Ga-Zn-based oxide, Sn-Al-Zn-based oxide, I n-Hf-Zn-based oxide, In-La-Zn-based oxide, In-Pr-Zn-based oxide, In -Nd-Zn-based oxide, In-Ce-Zn-based oxide, In-Sm-Zn-based oxide, In- Eu-Zn-based oxide, In-Gd-Zn-based oxide, In-Tb-Zn-based oxide, In-D y-Zn-based oxide, In-Ho-Zn-based oxide, In-Er-Zn-based oxide, In-Tm -Zn-based oxide, In-Yb-Zn-based oxide, In-Lu-Zn-based oxide, In-Sn- Ga-Zn-based oxide, In-Hf-Ga-Zn-based oxide, In-Al-Ga-Zn-based oxid e, In-Sn-Al-Zn-based oxide, In-Sn-Hf-Zn-based oxide, In-Hf- Al-Zn-based oxide can be used.

[0140] Note that, for example, the In-Ga-Zn-based oxide means an oxide containing In, Ga, and Zn, and the ratio of In, Ga, and Zn is not limited. Also, metal elements other than In, Ga, and Zn It may contain. The In-Ga-Zn oxide has a sufficiently high resistance in the absence of an electric field and can sufficiently reduce the off-current, and also has a high mobility. The off-current can be made sufficiently small, and the mobility is also high.

[0141] For example, a relatively high mobility can be obtained relatively easily with an In-Sn-Zn oxide. However, even with an In-Ga-Zn oxide, the mobility can be increased by reducing the defect density in the bulk.

[0142] The oxide semiconductor can be formed by a CVD (Chemical Vapor Deposition) method ( MOCVD (Metal Organic Chemical Vapor Deposition) method, ALD (Atomic Layer Deposition) method, thermal CVD method or PECVD (Plasma Enhanced Chemical Vapor Deposition) method, including but not limited to these), MBE (Molecular Beam Epitaxy) method or PLD (Pulsed Laser Deposition) method. In particular, when using the MOCVD method, ALD method or thermal CVD method, since no plasma is used, it is difficult to damage the oxide semiconductor, and the leakage current in the off state of the transistor can be suppressed low.

[0143] When forming an In-Ga-Zn oxide film using a thermal CVD method such as the MOVCD method or the ALD method, trimethylindium, trimethylgallium, and dimethylzinc are used. The chemical formula of trimethylindium is In(CH3)3. Also, the chemical formula of trimethylgallium is Ga(CH3)3. Also, the chemical formula of dimethylzinc is Zn(CH3)2. It is (H3)2. Also, it is not limited to these combinations, and instead of trimethylgallium triethylgallium (chemical formula Ga(C2H5)3) can also be used, and instead of dimethylzinc diethylzinc (chemical formula Zn(C2H5)2) can also be used.

[0144] Hereinafter, the structure of the oxide semiconductor film will be described.

[0145] The oxide semiconductor film is roughly classified into a single crystal oxide semiconductor film and a non-single crystal oxide semiconductor film. The non- single crystal oxide semiconductor film refers to an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, a polycrystalline oxide semiconductor film, a CAAC-OS film, and the like.

[0146] The amorphous oxide semiconductor film is an oxide semiconductor film in which the atomic arrangement in the film is irregular and has no crystal component. It is typical of an oxide semiconductor film that has no crystal part even in a minute region and the whole film has a complete amorphous structure. Even in a minute region, it has no crystal part, and the whole film has a complete amorphous structure. The oxide semiconductor film is typical.

[0147] The microcrystalline oxide semiconductor film contains, for example, microcrystals (also called nanocrystals) having a size of 1 nm or more and less than 10 nm. Therefore, the microcrystalline oxide semiconductor film has a higher regularity of atomic arrangement than the amorphous oxide semiconductor film. Therefore, the microcrystalline oxide semiconductor film is characterized by having a lower density of defect levels than the amorphous oxide semiconductor film. ... is also called.) Therefore, the microcrystalline oxide semiconductor film has a higher regularity of atomic arrangement than the amorphous oxide semiconductor film. Therefore, the microcrystalline oxide semiconductor film is characterized by having a lower density of defect levels than the amorphous oxide semiconductor film.

[0148] The CAAC-OS film is one of the oxide semiconductor films having a plurality of crystal parts, and most of the crystal parts have a size that can be accommodated in a cube having a side length of less than 100 nm. Therefore, the crystal parts included in the CAAC-OS film include cases where the side length is less than 10 nm, less than 5 nm, or less than 3 nm and can be accommodated in a cube. The CAAC-OS film has fewer defects than the microcrystalline oxide semiconductor film. ... is less than 100 nm. Therefore, the CAAC-O S film contains crystal parts that can be accommodated in a cube with a side length of less than 10 nm, less than 5 nm, or less than 3 nm. ... is less than 100 nm. Therefore, the crystal parts included in the CAAC-OS film include cases where the side length is less than 10 nm, less than 5 nm, or less than 3 nm and can be accommodated in a cube. The CAAC-OS film has fewer defects than the microcrystalline oxide semiconductor film. It is characterized by a low trap level density. When the CAAC-OS film is observed by a transmission electron microscope (TEM: transmission Electron Microscope), a clear boundary between crystal parts, that is, a grain boundary (also referred to as a grain boundary), cannot be confirmed. Therefore, it can be said that in the CAAC-OS film, a decrease in electron mobility due to grain boundaries is unlikely to occur.

[0149] When the CAAC-OS film is observed by TEM from a direction substantially parallel to the sample surface (cross-sectional TEM observation ), it can be confirmed that in the crystal part, metal atoms are arranged in layers. Each layer of metal atoms has a shape that reflects the unevenness of the surface (also referred to as the formed surface) or the upper surface of the CAAC-OS film, and is arranged parallel to the formed surface or the upper surface of the CAAC-OS film.

[0150] In this specification, "parallel" means a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. Also, "perpendicular" means a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included.

[0151] On the other hand, when the CAAC-OS film is observed by TEM from a direction substantially perpendicular to the sample surface (planar TEM observation), it can be confirmed that in the crystal part, metal atoms are arranged in a triangular or hexagonal shape. However, no regularity is seen in the arrangement of metal atoms between different crystal parts.

[0152] From the cross-sectional TEM observation and the planar TEM observation, it can be seen that the crystal part of the CAAC-OS film has orientation. ​​​​​​​​​

[0153] X-ray diffraction (XRD) was performed on the CAAC-OS film. For example, a CAAC-OS film with InGaZnO4 crystals was In the out-of-plane analysis, a peak was observed at a diffraction angle (2θ) of approximately 31°. This peak is attributed to the (009) plane of the InGaZnO4 crystal. This indicates that the crystals in the CAAC-OS film have a c-axis orientation, and the c-axis is generally aligned on the surface on which the film is formed or on the upper surface. It can be seen that it is oriented in a substantially vertical direction.

[0154] On the other hand, in-plane X-ray irradiation is performed on the CAAC-OS film in a direction perpendicular to the c-axis. In the analysis by the ane method, a peak may appear at 2θ around 56°. This peak is This is attributed to the (110) plane of the InGaZnO4 crystal. In the case of a semiconductor film, 2θ is fixed at around 56°, and the normal vector of the sample surface is set as the axis (φ axis). When the sample is rotated and analyzed (φ scan), the crystal plane equivalent to the (110) plane is In contrast, in the case of the CAAC-OS film, the 2θ is set to 5 Even when the φ is fixed at around 6° and scanned, no clear peak appears.

[0155] From the above, it is considered that the a-axis and b-axis orientations are inconsistent between different crystal regions in the CAAC-OS film. The crystal is regular, but has a c-axis orientation, and the c-axis is parallel to the normal vector of the surface on which the crystal is formed or the upper surface. Therefore, the layered arrangement confirmed by the cross-sectional TEM observation mentioned above is consistent with the above. Each layer of aligned metal atoms is a plane parallel to the ab plane of the crystal.

[0156] The crystalline portion is formed when the CAAC-OS film is formed or when a crystallization process such as a heat treatment is performed. As described above, the c-axis of the crystal is aligned along the surface on which the CAAC-OS film is formed or along the surface on which the CAAC-OS film is formed. The orientation of the CAAC-OS film is parallel to the normal vector of the top surface. When the shape of the CAAC-OS film is changed by etching, the c-axis of the crystal is aligned with the surface on which the CAAC-OS film is formed. Or it may not be parallel to the normal vector of the upper surface.

[0157] In addition, the degree of crystallinity in the CAAC-OS film may not be uniform. When the crystal part of the CAAC-OS film is formed by crystal growth from the vicinity of the top surface, The adjacent regions may have a higher degree of crystallinity than the regions adjacent the surface to be formed. When impurities are added to a C-OS film, the crystallinity of the region to which the impurities are added changes, resulting in partial In some cases, regions of differing crystallinity may be formed.

[0158] In addition, the out-of-plane method of CAAC-OS film with InGaZnO4 crystals In the analysis by , in addition to the peak at 2θ near 31°, a peak also appeared at 2θ near 36°. The peak at 2θ of around 36° may be due to the c-axis orientation in some parts of the CAAC-OS film. The CAAC-OS film contains crystals that do not have a 2θ of around 31°. It is preferred that the spectrum exhibits a peak and does not exhibit a peak at 2θ of around 36°.

[0159] The electrical characteristics of transistors using CAAC-OS films change when irradiated with visible or ultraviolet light. Therefore, the transistor has high reliability.

[0160] In addition, transistors using CAAC-OS films are resistant to external forces such as deformation caused by bending of the substrate. The resistance is stronger than that of a Poly-Si transistor or a single-crystalline Si transistor. For example, it is suitable for a highly flexible substrate such as plastic.

[0161] Note that the oxide semiconductor film may be, for example, a laminated film having two or more of an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, and a CA AC-OS film.

[0162] In addition, in order to form a CAAC-OS film by a sputtering method, the following conditions are preferably applied.

[0163] By reducing the incorporation of impurities during film formation, it is possible to suppress the breakdown of the crystal state due to impurities. For example, the impurity concentration (such as hydrogen, water, carbon dioxide, and nitrogen) present in the processing chamber may be reduced. Also, the impurity concentration in the film-forming gas may be reduced. Specifically, a film-forming gas having a dew point of -80°C or lower, preferably -100°C or lower, is used.

[0164] In addition, by increasing the substrate heating temperature during film formation, migration of sputtering particles occurs after reaching the substrate. Specifically, the substrate heating temperature is set to 100°C or higher and 740°C or lower, preferably 200°C or higher and 500°C or lower for film formation. By increasing the substrate heating temperature during film formation, when flat or pellet-shaped sputtering particles reach the substrate, migration occurs on the substrate, and the flat surface of the sputtering particles adheres to the substrate.

[0165] In addition, it is preferable to reduce plasma damage during film formation by increasing the oxygen ratio in the film-forming gas and optimizing the power. The oxygen ratio in the film-forming gas is 30 vol% or more, preferably 100 vol %.

[0166] As an example of a target, an In-Ga-Zn-based oxide target is shown below.

[0167] InO X powder, GaO Y powder, and ZnO Z powders are mixed in a predetermined molar ratio, and after pressure treatment , heat treatment is performed at a temperature of 1000 °C or higher and 1500 °C or lower to obtain a polycrystalline In-Ga -Zn-based oxide target. Here, X, Y, and Z are arbitrary positive numbers. Here, the predetermined molar ratio is, for example, InO X powder, GaO Y powder, and ZnO Z powders are 2:2: 1, 8:4:3, 3:1:1, 1:1:1, 4:2:3, 1:4:4, or 3:1:2 . Note that the type of powder and the molar ratio for mixing may be appropriately changed according to the target to be produced.

[0168] Note that since alkali metals are not elements constituting the oxide semiconductor, they are impurities. Alkaline earth metals also become impurities when they are not elements constituting the oxide semiconductor. In particular , among alkali metals, Na diffuses into the insulating film when the insulating film in contact with the oxide semiconductor film is an oxide, and becomes Na + . Further, Na breaks or interrupts the bond between the metal and oxygen constituting the oxide semiconductor within the oxide semiconductor film. As a result , for example, abnormal ionization occurs due to a shift in the threshold voltage in the negative direction, and the mobility decreases . As a result, deterioration of the electrical characteristics of the transistor, such as a decrease in mobility, occurs, and in addition, variations in characteristics also occur. Specifically, the measured value of the Na concentration by secondary ion mass spectrometry is 5×10 / cm 16 or less 3 , preferably 1×10 ​16 / cm 3 More preferably, 1×10 15 / cm 3 The following Similarly, the measured Li concentration is 5×10 15 / cm 3 Below, preferably 1×1 0 15 / cm 3 Similarly, the measured value of K concentration should be 5×10 15 / cm 3 Below Lower, preferably 1×10 15 / cm 3 The following should be used.

[0169] In addition, when a metal oxide containing indium is used, the bond energy with oxygen is Silicon and carbon, which are larger than indium, break the bond between indium and oxygen, creating an oxygen vacancy. Therefore, when silicon or carbon is mixed into the oxide semiconductor film, As with alkali and alkaline earth metals, degradation of the electrical characteristics of transistors occurs. Therefore, it is preferable that the concentrations of silicon and carbon in the oxide semiconductor film be low. Specifically, the measured values ​​of C concentration or Si concentration by secondary ion mass spectrometry is 1 x 10 18 / cm 3 With the above configuration, the electrical characteristics of the transistor are preferably as follows. This makes it possible to prevent deterioration of the electrical conductivity of the semiconductor device, thereby improving the reliability of the semiconductor device.

[0170] In addition, depending on the conductive material used for the source electrode and the drain electrode, The metal in the drain electrode may extract oxygen from the oxide semiconductor film. The region of the nitride semiconductor film in contact with the source electrode and the drain electrode is depleted due to the formation of oxygen vacancies. It is made n-type.

[0171] Since the n-type region functions as a source region or a drain region, the contact resistance between the oxide semiconductor film and the source and drain electrodes can be reduced. Therefore, by forming the n-type region, the mobility and on-current of the transistor can be increased thereby enabling high-speed operation of the semiconductor device using the transistor.

[0172] Note that the extraction of oxygen by the metal in the source and drain electrodes may occur when the source and drain electrodes are formed by a sputtering method or the like, or may also occur by a heat treatment performed after the source and drain electrodes are formed.

[0173] In addition, the region to be n-type becomes easier to form by using a conductive material that easily binds to oxygen for the source and drain electrodes. Examples of the conductive material include Al, Cr, Cu, Ta, Ti, Mo, W, and the like.

[0174] In addition, the oxide semiconductor film is not necessarily composed of a single metal oxide film and may be composed of a plurality of stacked metal oxide films. For example, in the case of a semiconductor film in which the first to third metal oxide films are stacked in order, the first metal oxide film and the third metal oxide film contain at least one of the metal elements constituting the second metal oxide film in its components, and the energy at the bottom of the conduction band is 0.05 eV or more, 0.07 eV or more, 0. 1 eV or more or 0.15 eV or more, and 2 eV or less, 1 eV or less, 0.5 eV or less or 0.4 eV or less, and is an oxide film close to the vacuum level. Further, the second metal oxide film has at least ​It is preferable that indium is included because it increases the carrier mobility.

[0175] When the semiconductor film having the above configuration is included in a transistor, by applying a voltage to the gate electrode, when an electric field is applied to the semiconductor film, in the semiconductor film, a channel formation region is formed in the second metal oxide film having a small energy at the lower end of the conduction band. That is, since the third metal oxide film is provided between the second metal oxide film and the gate insulating film, a channel formation region can be formed in the second metal oxide film separated from the gate insulating film. That is, since the third metal oxide film includes at least one of the metal elements constituting the second metal oxide film, interface scattering hardly occurs at the interface between the second metal oxide film and the third metal oxide film. Therefore, since the movement of carriers is hardly inhibited at the interface, the field-effect mobility of the transistor is increased. That is, since the third metal oxide film includes at least one of the metal elements constituting the second metal oxide film, a channel formation region can be formed in the second metal oxide film separated from the gate insulating film.

[0176] In addition, since the third metal oxide film includes at least one of the metal elements constituting the second metal oxide film as its component, interface scattering hardly occurs at the interface between the second metal oxide film and the third metal oxide film. Therefore, since the movement of carriers is hardly inhibited at the interface, the field-effect mobility of the transistor is increased. In addition, when interface levels are formed at the interface between the second metal oxide film and the first metal oxide film, channel formation regions are also formed in the regions near the interface, so that the threshold voltage of the transistor fluctuates. However, since the first metal oxide film includes at least one of the metal elements constituting the second metal oxide film as its component, interface levels are hardly formed at the interface between the second metal oxide film and the first metal oxide film. Therefore, with the above configuration, variations in electrical characteristics such as the threshold voltage of the transistor can be reduced.

[0177] In addition, when interface levels are formed at the interface between the second metal oxide film and the first metal oxide film, channel formation regions are also formed in the regions near the interface, so that the threshold voltage of the transistor fluctuates. However, since the first metal oxide film includes at least one of the metal elements constituting the second metal oxide film as its component, interface levels are hardly formed at the interface between the second metal oxide film and the first metal oxide film. Therefore, with the above configuration, variations in electrical characteristics such as the threshold voltage of the transistor can be reduced. Moreover, in order not to form interface levels that inhibit the flow of carriers at the interfaces of the respective films due to the presence of impurities between the metal oxide films, a plurality of oxide semiconductor films are stacked. Therefore, with the above configuration, variations in electrical characteristics such as the threshold voltage of the transistor can be reduced. Moreover, in order not to form interface levels that inhibit the flow of carriers at the interfaces of the respective films due to the presence of impurities between the metal oxide films, a plurality of oxide semiconductor films are stacked.

[0178] In addition, in order not to form interface levels that inhibit the flow of carriers at the interfaces of the respective films due to the presence of impurities between the metal oxide films, a plurality of oxide semiconductor films are stacked. Moreover, in order not to form interface levels that inhibit the flow of carriers at the interfaces of the respective films due to the presence of impurities between the metal oxide films, a plurality of oxide semiconductor films are stacked. is desirable. If impurities are present between the stacked metal oxide films, the continuity of the energy at the lower end of the conduction band between the metal oxide films is lost, and near the interface, carriers are trapped or disappear due to recombination. By reducing the impurities between the films, a plurality of metal oxide films having at least one common metal as the main component are more likely to form a continuous junction (here, particularly a U-shaped well structure in which the energy at the lower end of the conduction band changes continuously between the films) than simply stacking them. To form a continuous junction, it is necessary to continuously stack each film without exposing it to the atmosphere using a multi-chamber film forming apparatus equipped with a load lock chamber (sputtering apparatus). Each chamber in the sputtering apparatus should be evacuated to a high vacuum (5×10

[0179] Pa or higher, 1×10 Pa or lower) using an adsorption type vacuum exhaust pump such as a cryopump to remove water and other impurities as much as possible for the oxide semiconductor. Alternatively, it is preferable to combine a turbo molecular pump and a cold trap to prevent gas from flowing back into the chamber from the exhaust system. To obtain a high-purity intrinsic oxide semiconductor, it is not only necessary to evacuate each chamber to a high vacuum, but also to highly purify the gas used for sputtering. The dew point of the oxygen gas -7 and argon gas used as the above gas should be -40°C or lower, preferably -80°C or lower, more preferably - -4 100°C or lower. By highly purifying the gas used, moisture and other substances are prevented from being incorporated into the oxide semiconductor film.

[0180] It can be prevented from being recessed as much as possible. Specifically, when the second metal oxide film is In- M-Zn oxide (M is Ga, Y, Zr, La, Ce, or Nd), in the target used to form the second metal oxide film, if the atomic ratio of metal elements is In:M: Zn = x1:y1:z1, then 、 x1 / y1 is 1 / 3 or more and 6 or less, further 1 or more and 6 or less, and z1 / y1 is preferably 1 / 3 or more and 6 or less, further 1 or more and 6 or less. By setting z1 / y1 to 1 or more and 6 or less, it becomes easier to form a CA AC-OS film as the second metal oxide film. Representative examples of the atomic ratio of metal elements in the target include , In:M:Zn = 1:1:1, In:M:Zn = 3:1:2, etc.

[0181] Specifically, when the first metal oxide film and the third metal oxide film are In-M-Zn oxide (M is G a, Y, Zr, La, Ce, or Nd), in the target used to form the first metal oxide film and the third metal oxide film, if the atomic ratio of metal elements is In:M:Zn = x2:y2:z2, then 、 x2 / y2 < x1 / y1, and z2 / y2 is preferably 1 / 3 or more and 6 or less, further 1 or more and 6 or less. By setting z2 / y2 to 1 or more and 6 or less, it becomes easier to form a CAAC-OS film as the first metal oxide film and the third metal oxide film. Representative examples of the atomic ratio of metal elements in the target include In:M:Z n = 1:3:2, In:M:Zn = 1:3:4, In:M:Zn = 1:3:6, In:M :Zn = 1:3:8, etc.

[0182] In addition, the thickness of the first metal oxide film and the third metal oxide film is 3 nm or more and 100 nm or less. ​​, preferably 3 nm or more and 50 nm or less. Further, the thickness of the second metal oxide film is 3 n m or more and 200 nm or less, preferably 3 nm or more and 100 nm or less, and more preferably 3 nm or more and 50 nm or less.

[0183] In the three-layer semiconductor film, the first to third metal oxide films can take both amorphous and crystalline forms. However, since the second metal oxide film in which the channel formation region is formed being crystalline can impart stable electrical characteristics to the transistor, the second metal oxide film is preferably crystalline.

[0184] Note that the channel formation region means the region of the semiconductor film of the transistor that overlaps with the gate electrode and is sandwiched between the source electrode and the drain electrode. Also, the channel region refers to the region where current mainly flows in the channel formation region.

[0185] For example, when an In-Ga-Zn-based oxide film formed by sputtering is used as the first and third metal oxide films, a target of In-Ga-Zn-based oxide (In:Ga:Zn = 1:3:2 [atomic number ratio]) can be used for forming the first and third metal oxide films. The film formation conditions may be, for example, using argon gas at 30 sccm and oxygen gas at 15 sccm as the film formation gas, a pressure of 0.4 Pa, a substrate temperature of 200°C, and a DC power of 0.5 kW.

[0186]

[0186] It is preferable to use a target containing polycrystalline In-Ga-Zn-based oxide. Film formation conditions are, for example, using 30 sccm of argon gas and 15 sccm of oxygen gas as the film formation gas , setting the pressure to 0.4 Pa, the temperature of the substrate to 300 °C, and the DC power to 0.5 kW is possible.

[0187] Note that the transistor may have a structure in which the end of the semiconductor film is inclined, or may have a structure in which the end of the semiconductor film is rounded.

[0188] Also, when using a semiconductor film having a plurality of stacked metal oxide films for a transistor , the regions in contact with the source electrode and the drain electrode may be n-type. With the above configuration , the mobility and on-current of the transistor can be increased, and high-speed operation of a semiconductor device using the transistor can be realized. Further, when using a semiconductor film having a plurality of stacked metal oxide films for a transistor, the region to be n-type reaches the second metal oxide film that becomes the channel formation region, which is more preferable for increasing the mobility and on-current of the transistor and realizing further high-speed operation of the semiconductor device.

[0189] This embodiment can be implemented in appropriate combination with other embodiments.

[0190] (Embodiment 5) FIG. 14 is an example of a perspective view of a light-emitting device according to an aspect of the present invention.

[0191] The light-emitting device shown in FIG. 14 includes a panel 1601, a circuit board 1602 provided with a controller, a power supply circuit, an image processing circuit, an image memory, a CPU, etc., and a connection part 1603. ​​​​The panel 1601 includes a pixel portion 1604 provided with a plurality of pixels, and a scanning line driving circuit 1605 that selects a plurality of pixels row by row, and a signal line driving circuit 1606 that controls the input of signal Sig1 or signal Sig2 to the pixels within the selected row. Various signals and the potential of the power supply are input to the panel 1601 from the circuit board 1602 via the connection portion 1603. The connection portion 1603 can use an FPC (Flexible Printed Circuit), etc. Also, when using a COF tape for the connection portion 1603, a part of the circuits within the circuit board 1602, or a part of the scanning line driving circuit 1605 or the signal line driving circuit 1606 included in the panel 1601, etc. are formed on a separately prepared chip, and the chip is connected to the COF tape using the COF (Chip On Film) method. This embodiment can be implemented in appropriate combination with other embodiments.

[0192] (Embodiment 6) A light-emitting device according to an aspect of the present invention can be used in a display device, a notebook personal computer, an image reproduction device equipped with a recording medium (typically a device having a display capable of reproducing an image from a recording medium such as a DVD: Digital Versatile Disc). In addition, as electronic devices in which a light-emitting device according to an aspect of the present invention can be used, there are mobile phones, portable game machines, portable information terminals, electronic book terminals, video cameras, cameras such as digital still cameras, goggle-type displays (head-mounted displays), navigation systems, audio reproduction devices (car audio, digital audio players), etc.

[0193]

[0194] (Embodiment 6) A light-emitting device according to an aspect of the present invention can be used in a display device, a notebook personal computer, an image reproduction device equipped with a recording medium (typically a device having a display capable of reproducing an image from a recording medium such as a DVD: Digital Versatile Disc). In addition, as electronic devices in which a light-emitting device according to an aspect of the present invention can be used, there are mobile phones, portable game machines, portable information terminals, electronic book terminals, video cameras, cameras such as digital still cameras, goggle-type displays (head-mounted displays), navigation systems, audio reproduction devices (car audio, digital audio players), etc. ​​​​​​​​​​​​ layers, etc.), copiers, facsimiles, printers, printer multifunction devices, automated teller machines (ATMs), vending machines, and the like. Specific examples of these electronic devices are shown in FIG. 15. are listed. Specific examples of these electronic devices are shown in FIG. 15. shown.

[0195] FIG. 15(A) is a display device and includes a housing 5001, a display unit 5002, a support base 5003, etc. The light-emitting device according to one aspect of the present invention can be used for the display unit 5002. Note that the display device includes all information display devices for personal computers, TV broadcast reception, advertisement display, and the like. shown. The light-emitting device according to one aspect of the present invention can be used for the display unit 5002. Note that the display device includes all information display devices for personal computers, TV broadcast reception, advertisement display, and the like. display devices for personal computers, TV broadcast reception, advertisement display, and the like. are included.

[0196] FIG. 15(B) is a portable information terminal and includes a housing 5101, a display unit 5102, operation keys 5103, etc. The light-emitting device according to one aspect of the present invention can be used for the display unit 5102. shown. The light-emitting device according to one aspect of the present invention can be used for the display unit 5102.

[0197] FIG. 15(C) is a display device and includes a housing 5701 having a curved surface, a display unit 5702, etc. By using a flexible substrate for the light-emitting device according to one aspect of the present invention, the light-emitting device can be used for the display unit 5702 supported by the housing 5701 having a curved surface, and a flexible, lightweight, and user-friendly display device can be provided. shown. By using a flexible substrate for the light-emitting device according to one aspect of the present invention, the light-emitting device can be used for the display unit 5702 supported by the housing 5701 having a curved surface, and a flexible, lightweight, and user-friendly display device can be provided. supported by the housing 5701 having a curved surface, and a flexible, lightweight, and user-friendly display device can be provided. can be provided.

[0198] FIG. 15(D) is a portable game machine and includes a housing 5301, a housing 5302, display units 5303, display units 5304, a microphone 5305, a speaker 5306, operation keys 5307, a sticker 5308, etc. The light-emitting device according to one aspect of the present invention can be used for the display unit 5303 or the display unit 5304. By using the light-emitting device according to one aspect of the present invention for the display unit 5303 or the display unit 5304, the user experience is excellent and quality degradation is less likely to occur. using the light-emitting device according to one aspect of the present invention for the display unit 5303 or the display unit 5304, the user experience is excellent and quality degradation is less likely to occur. A portable game machine can be provided. Note that the portable game machine shown in FIG. 15(D) has two display units 5303 and 5304, but the number of display units owned by the portable game machine is not limited to this.

[0199] FIG. 15(E) is an electronic book terminal, which has a housing 5601, a display unit 5602, etc. The light-emitting device according to one aspect of the present invention can be used for the display unit 5602. By using a flexible substrate, the light-emitting device can be made flexible, so that a flexible, lightweight, and easy-to-use electronic book terminal can be provided.

[0200] FIG. 15(F) is a mobile phone, and a display unit 5902, a microphone 5907, a speaker 5904, a camera 5903, an external connection unit 5906, and operation buttons 5905 are provided on a housing 5901. The light-emitting device according to one aspect of the present invention can be used for the display unit 5902. In addition, when the light-emitting device according to one aspect of the present invention is formed on a flexible substrate, the light-emitting device can be applied to the display unit 5902 having a curved surface as shown in FIG. 15(F).

[0201] This embodiment can be implemented in appropriate combination with other embodiments.

[0202] (Embodiment 7) In this embodiment, an example of a transistor that can be used for the transistors M1 to M3 shown in Embodiment 1 and Embodiment 2 will be described with reference to FIG. 16.

[0203] FIG. 16(A) is a top view of a transistor 300, and FIG. 16(B) is a cross-sectional view taken along line A-A' in FIG. 16(A). It is a cross-sectional view between the dotted lines X1 - X2. Fig. 16(C) is a cross-sectional view between the dashed-dotted lines Y1 - Y 2 in Fig. 16(A). Fig. 16(B) is a cross-sectional view in the channel length direction of the transistor 300, and Fig. 16(C) is a cross-sectional view in the channel width direction of the transistor 300. Note that, in Fig. 16(A), for clarity, some of the components are shown with omissions.

[0204] The transistor 300 has a conductive film 361 formed on a substrate 362, an insulating film 364 on the substrate 362 and the conductive film 361, an oxide semiconductor film 366 on the insulating film 364, conductive films 370a, 370b and an insulating film 372 in contact with the oxide semiconductor film 366, and a conductive film 374 overlapping the oxide semiconductor film 366 through the insulating film 372. Note that an insulating film 376 is provided on the transistor 30 0. In the transistor 300, the conductive film 374 functions as a first gate electrode, and the conductive

[0205] film 361 functions as a second gate electrode. Also, the insulating film 372 functions as a first gate insulating film, and the insulating film 364 functions as a second gate insulating film. .

[0206] In the transistor 300, the conductive film 370a functions as one of the source electrode and the drain electrode, and the conductive film 370b functions as the other of the source electrode and the drain electrode.

[0207] As shown in Fig. 16(C), the conductive film 374 is connected to the conductive film 361 through an opening 389 provided in the insulating film 372 and the insulating film 364. Since the same potential is applied to the first gate electrode and the second gate electrode of the transistor 300, the increase in the on-current and the initial characteristics ​​​ Reduction of property variations, -GBT (minus Gate Bias Temperature) e) Suppression of degradation in stress tests and rise of on-current at different drain voltages It is possible to suppress voltage fluctuations.

[0208] Further, the transistor 300 may be given different potentials without connecting the conductive film 374 and the conductive film 361. By doing so, the threshold voltage of the transistor 300 can be controlled. Note that, depending on the case, the conductive film 361 may be omitted.

[0209] In the oxide semiconductor film 366, regions that do not overlap with the conductive film 370a, the conductive film 370b, and the conductive film 374 have elements that form oxygen deficiencies. Hereinafter, the elements that form oxygen deficiencies will be described as impurity elements. Representative examples of impurity elements include hydrogen, noble gas elements, etc. Representative examples of noble gas elements include helium, neon, argon, krypton, and xenon. Further, boron, carbon, nitrogen, fluorine, aluminum, silicon, phosphorus, chlorine, etc. may be included in the oxide semiconductor film 366 as impurity elements.

[0210] Further, the insulating film 376 is a film containing hydrogen, typically a nitride insulating film. When the insulating film 376 is in contact with the oxide semiconductor film 366, the hydrogen contained in the insulating film 376 diffuses into the oxide semiconductor film 366. As a result, a large amount of hydrogen is contained in the region where the oxide semiconductor film 366 is in contact with the insulating film 376.

[0211] When a noble gas element is added to the oxide semiconductor film as an impurity element, the bonds between metal elements and oxygen in the oxide semiconductor film are broken, and oxygen deficiencies are formed. The oxygen contained in the oxide semiconductor film ​​​​​​​​​​​Due to the interaction between oxygen vacancies and hydrogen, the conductivity of the oxide semiconductor film increases. Specifically, when hydrogen enters the oxygen vacancies contained in the oxide semiconductor film, carriers (electrons) are generated. As a result, the conductivity increases.

[0212] Examples of substrates applicable to the substrate 362 include, for example, glass substrates, quartz substrates, plastic substrates, metal substrates, stainless steel substrates, substrates having a stainless steel foil, tantalum substrates, substrates having a tungsten foil, flexible substrates, laminated films papers containing fibrous materials, or base films. An example of a glass substrate is barium borosilicate glass, aluminoborosilicate glass, or soda lime glass. Examples of flexible substrates include plastics typified by polyethylene terephthalate (PET), poly ethylene naphthalate (PEN), and polyethersulfone (PES), or flexible synthetic resins such as acrylic. For laminated films, films made of polypropylene, polyester, polyvinyl fluoride, polyvinyl chloride, etc., or inorganic vapor deposition films can also be used. An example of a base film is polyester, polyamide, polyimide, aramid, epoxy, inorganic vapor deposition film, or papers.

[0213] Furthermore, the substrate 362 is not limited to a mere support, and may be a substrate on which other elements such as transistors and capacitors are formed.

[0214] Materials used for the conductive film 361 and the conductive film 374 include metal elements selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten, or the above-described metal elements ​The alloy may be made of an alloy containing the above-mentioned metal elements or a combination of the above-mentioned metal elements. The conductive film 361 and the conductive film 374 may have a single-layer structure or a two-layer structure or more. For example, a two-layer structure in which a titanium film is laminated on an aluminum film, or a nitride film may be laminated on an aluminum film. A two-layer structure in which a titanium film is laminated on a titanium nitride film, and a tungsten film is laminated on a titanium nitride film a two-layer structure in which a tungsten film is laminated on a tantalum nitride film or a tungsten nitride film; Layer structure: titanium film, aluminum film laminated on titanium film, titanium on top of aluminum film There are also three-layer structures that form a film. A combination of one or more selected from the group consisting of chromium, molybdenum, chromium, neodymium, and scandium. Alternatively, an alloy film or a nitride film may be used for the conductive film 361 and the conductive film 374. The material can be formed by using a sputtering method, for example.

[0215] In addition, examples of a conductive film that can be used for the conductive film 361 and the conductive film 374 include indium For example, an oxide containing tungsten oxide, indium oxide, Indium zinc oxide containing tungsten, indium oxide containing titanium oxide, titanium oxide Indium tin oxide (ITO) containing tin, in ... Conductive materials with light-transmitting properties such as indium zinc oxide and indium tin oxide doped with silicon oxide Materials can be used.

[0216] Examples of materials that can be used for the conductive film 370a and the conductive film 370b include aluminum, Titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum A single metal composed of ruthenium, or tungsten, or an alloy having this as a main component can be used as a single layer structure or a laminated structure. In particular, it is preferable to contain one or more elements selected from aluminum, chromium, copper, tantalum , titanium, molybdenum, and tungsten. For example, a two-layer structure in which a titanium film is laminated on an aluminum film, a titanium film is laminated on a tungsten film, a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film , a three-layer structure in which a titanium film or a titanium nitride film and an aluminum film or a copper film are laminated on the titanium film or the titanium nitride film, and a titanium film or a titanium nitride film is further formed thereon , a three-layer structure in which a molybdenum film or a molybdenum nitride film and an aluminum film or a copper film are laminated on the molybdenum film or the molybdenum nitride film , and a molybdenum film or a molybdenum nitride film is further formed thereon . There are also three-layer structures and the like. In addition, a transparent conductive material containing indium oxide, tin oxide or zinc oxide may be used. The conductive film can be formed, for example, by a sputtering method. For details of the oxide semiconductor film 366, refer to the description of the oxide semiconductor film 82 in FIG. 13.

[0217] For details of the oxide semiconductor film 366, refer to the description of the oxide semiconductor film 82 in FIG. 13.

[0218] The insulating film 364 can be formed by laminating a single layer or multiple layers of an oxide insulating film or a nitride insulating film. In order to improve the interface characteristics with the oxide semiconductor film 366, in the insulating film 364 at least the region in contact with the oxide semiconductor film 366 is preferably formed of an oxide insulating film. Also, by using an oxide insulating film that releases oxygen by heating as the insulating film 364, the oxygen contained in the insulating film 364 can be moved to the oxide semiconductor film 366 by heat treatment. This is possible.

[0219] The thickness of the insulating film 364 can be 50 nm or more, or 100 nm or more and 3000 nm or less, or 20 0 nm or more and 1000 nm or less. By increasing the thickness of the insulating film 364, the oxygen release amount of the insulating film 364 can be increased, and the interface levels at the interface between the insulating film 364 and the oxide semiconductor film 366, as well as the oxygen vacancies contained in the channel formation region of the oxide semiconductor film 366, can be reduced.

[0220] As the insulating film 364, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, nitride silicon, aluminum oxide, hafnium oxide, or gallium oxide can be used, and it can be provided as a single layer or a laminate.

[0221] The insulating film 372 can be formed by laminating a single layer or a laminate of an oxide insulating film or a nitride insulating film. In order to improve the interface characteristics with the oxide semiconductor film 366, in the insulating film 372 it is preferable to form at least the region in contact with the oxide semiconductor film 366 using an oxide insulating film. As the insulating film 372, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, nitride silicon, aluminum oxide, hafnium oxide, or gallium oxide can be used, and it can be provided as a single layer or a laminate.

[0222] In addition, by providing an insulating film having a blocking effect on oxygen, hydrogen, water, etc. as the insulating film 372, diffusion of oxygen from the oxide semiconductor film 366 to the outside and intrusion of hydrogen, water, etc. from the outside into the oxide semiconductor film 366 can be prevented. As the insulating film having a blocking effect on oxygen, hydrogen, water, etc., aluminum oxide, aluminum oxynitride, gallium oxide, acid Gallium nitride, yttrium oxide, yttrium oxynitride, hafnium oxide, oxynitride hafnium, etc. are available.

[0223] Also, as the insulating film 372, hafnium silicate (HfSiO x ), hafnium silicate (HfSi with nitrogen added x O y N z ), hafnium aluminate (HfAl with nitrogen added x O y N z ), high-k materials such as hafnium oxide and yttrium oxide can be used to reduce the gate leakage of the transistor.

[0224] Also, by using an oxide insulating film that releases oxygen upon heating as the insulating film 372, it is possible to move the oxygen contained in the insulating film 372 to the oxide semiconductor film 366 by heat treatment.

[0225] The thickness of the insulating film 372 can be 5 nm or more and 400 nm or less, or 5 nm or more and 300 nm or less, or 10 nm or more and 250 nm or less.

[0226] This embodiment can be implemented in appropriate combination with other embodiments.

Description of Reference Numerals

[0227] C1 Capacitor element M1 Transistor M2 Transistor M3 Transistor p0 Period p1 Period p2 Period S1 Signal Sig0 Signal Sig1 Signal Sig2 Signal SL1 Wiring SL2 Wiring 70 Transistor 80 Conductive Film 81 Insulating Film 82 Oxide Semiconductor Film 82a Oxide Semiconductor Film 82b Oxide Semiconductor Film 82c Oxide Semiconductor Film 83 Conductive Film 84 Conductive Film 85 Insulating Film 86 Insulating Film 87 Insulating Film 100 Light-Emitting Device 101 Pixel 101a Pixel 101b Pixel 102 Pixel Section 103 Panel 104 Controller 105 Power Supply Circuit 120 Input Device 121 CPU 122 Image Processing Circuit 123 Image Memory 124 Signal Line Driving Circuit 125 Scanning Line Driving Circuit 126 Image Data 300 Transistor 361 Conductive Film 362 Substrate 364 Insulating Film 366 Oxide Semiconductor Film 370a Conductive Film 370b Conductive Film 372 Insulating Film 374 Conductive Film 376 Insulating Film 389 Opening 400 Substrate 401 Conductive Film 402 Insulating Film 403 Semiconductor Film 404 Conductive Film 405 Conductive Film 411 Insulating Film 420 Insulating Film 424 Conductive film 425 Insulating film 426 Insulating film 427 EL layer 428 Conductive film 430 Substrate 431 Masking film 432 Coloring layer 501 Conductive film 502 Conductive film 503 Conductive film 504 Conductive film 505 Conductive film 506 Conductive film 507 Conductive film 508 Conductive film 511 Semiconductor film 512 Semiconductor film 513 Semiconductor film 514 Semiconductor film 515 Semiconductor film 516 Semiconductor film 521 Conductive film 522 Conductive film 523 Conductive film 524 Conductive film 525 Conductive film 526 Conductive film 527 Conductive film 528 Conductive film 529 Conductive film 530 Conductive film 531 Conductive film 1601 Panel 1602 Circuit board 1603 Connection part 1604 Pixel part 1605 Scanning line drive circuit 1606 Signal line drive circuit 5001 Housing 5002 Display unit 5003 Support stand 5101 Housing 5102 Display unit 5103 Operation key 5301 Housing 5302 Housing 5303 Display unit 5304 Display unit 5305 Microphone 5306 Speaker 5307 Operation Key 5308 Stylus 5601 Housing 5602 Display Unit 5701 Housing 5702 Display Unit 5901 Housing 5902 Display Unit 5903 Camera 5904 Speaker 5905 Button 5906 External Connection Port 5907 Microphone

Claims

[Claim 1] a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first light-emitting element, a second light-emitting element, a first wiring, a second wiring, a third wiring, a fourth wiring, and a fifth wiring; a gate of the first transistor is connected to the second wiring; one of a source and a drain of the first transistor is connected to the fourth wiring, the other of the source and the drain of the first transistor is connected to the gate of the third transistor; a gate of the second transistor is connected to the first wiring; one of a source and a drain of the second transistor is connected to the fifth wiring, the other of the source and the drain of the second transistor is connected to the gate of the third transistor; one of a source and a drain of the third transistor is connected to a first terminal of the first light emitting element; the other of the source and the drain of the third transistor is given a first potential; a second terminal of the first light emitting element is given a second potential; a gate of the fourth transistor is connected to the third wiring; one of a source and a drain of the fourth transistor is connected to the fourth wiring, the other of the source and the drain of the fourth transistor is connected to the gate of the sixth transistor; a gate of the fifth transistor is connected to the second wiring; one of a source and a drain of the fifth transistor is connected to the fifth wiring, the other of the source and the drain of the fifth transistor is connected to the gate of the sixth transistor; one of a source and a drain of the sixth transistor is connected to a first terminal of the second light emitting element; the other of the source and the drain of the sixth transistor is given the first potential; the second terminal of the second light-emitting element is given the second potential; A signal including image information is applied to the fourth wiring, The light emitting device is characterized in that a third potential is applied to the fifth wiring.

Images