Display device

Abstract

To provide a display device capable of suppressing a decrease in display quality.SOLUTION: A display device according to an embodiment includes a base material, a plurality of pixels disposed in a display region on the base material, and a data signal line that supplies a data signal to each of the pixels. Each of the pixels includes a pixel circuit that has a first transistor and a holding capacitor, and a light-emitting element that is driven by the pixel circuit. The holding capacitor is configured so that the voltage that controls the current supplied to the light-emitting element is written therein. The first transistor is configured to supply the current to the light-emitting element on the basis of the voltage written in the holding capacitor. A first frame period to display one frame in the display region includes a second period to turn on the first transistor disposed before the first period in which the voltage according to the data signal is written in the holding capacitor.SELECTED DRAWING: Figure 14

Description

Technical Field

[0001] Embodiments of the present invention relate to a display device.

Background Art

[0002] In recent years, display devices applying organic light-emitting diodes (OLEDs), which are light-emitting elements functioning as display elements, have been put into practical use.

[0003] In such a display device, a light-emitting element is driven by a pixel circuit. However, depending on the driving method of the light-emitting element, the display quality of the display device may deteriorate.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] An object of the present invention is to provide a display device capable of suppressing a decrease in display quality.

Means for Solving the Problems

[0006] The display device according to the embodiment includes a base material, a plurality of pixels arranged in a display area on the base material, and a data signal line that supplies a data signal to each of the plurality of pixels. Each of the plurality of pixels includes a pixel circuit having a first transistor and a holding capacitor, and a light-emitting element driven by the pixel circuit. The holding capacitor is configured to write a voltage for controlling a current supplied to the light-emitting element. The first transistor is configured to supply a current to the light-emitting element based on the voltage written in the holding capacitor. One frame period for displaying one frame in the display area includes a second period for turning on the first transistor, which is arranged before a first period in which a voltage corresponding to the data signal is written in the holding capacitor.

Brief Description of the Drawings

[0007]

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Embodiments for Carrying Out the Invention

[0008] One embodiment will be described with reference to the drawings. The disclosure is merely an example, and for those that can be easily conceived by a person skilled in the art for appropriate modifications while maintaining the gist of the invention, they are naturally included in the scope of the present invention. In addition, for the purpose of making the description clearer, the drawings may schematically represent the width, thickness, shape, etc. of each part compared to the actual embodiment, but it is merely an example and does not limit the interpretation of the present invention. Also, in this specification and each drawing, components that exhibit the same or similar functions as those described above with respect to the previously shown drawings may be given the same reference numerals, and detailed descriptions that are repeated may be omitted as appropriate.

[0009] In addition, in the drawings, for the purpose of facilitating understanding as necessary, the X-axis, Y-axis, and Z-axis that are perpendicular to each other are described. The direction along the X-axis is referred to as the first direction X, the direction along the Y-axis is referred to as the second direction Y, and the direction along the Z-axis is referred to as the third direction Z. Looking at various elements parallel to the third direction Z is referred to as a plan view.

[0010] The display device according to this embodiment is an organic electroluminescence display device including an organic light-emitting diode (OLED) as a display element (light-emitting element), and is mounted on a television, a personal computer, a portable terminal, a mobile phone, etc.

[0011] (First Embodiment) First, the first embodiment will be described. FIG. 1 is a diagram showing a configuration example of a display device DSP according to this embodiment. The display device DSP has a display area DA for displaying an image and a non-display area NDA around the display area DA on an insulating base material 10. The base material 10 may be glass or a resin film having flexibility.

[0012] In this embodiment, the shape of the base material 10 in a plan view is rectangular. However, the shape of the base material 10 in a plan view is not limited to a rectangle, and may be other shapes such as a square, a circle, or an ellipse.

[0013] The display area DA includes a plurality of pixels PX arranged in a matrix in a first direction X and a second direction Y that intersect each other. The pixel PX includes a plurality of sub-pixels SP. In one example, the plurality of sub-pixels SP include a red sub-pixel SP1, a green sub-pixel SP2, and a blue sub-pixel SP3. Note that the plurality of sub-pixels SP may include sub-pixels of other colors such as white together with the sub-pixels SP1, SP2, and SP3. Further, the plurality of sub-pixels SP may include sub-pixels of other colors instead of any one of the sub-pixels SP1, SP2, and SP3.

[0014] Note that, although details will be described later, each of the plurality of sub-pixels SP includes a pixel circuit and a light-emitting element driven by the pixel circuit. The pixel circuit is composed of, for example, a plurality of transistors (switching elements constituted by thin-film transistors). The light-emitting element is the organic light-emitting diode described above. For example, the sub-pixel SP1 includes a light-emitting element that emits light so as to emit light in the red wavelength range, the sub-pixel SP2 includes a light-emitting element that emits light so as to emit light in the green wavelength range, and the sub-pixel SP3 includes a light-emitting element that emits light so as to emit light in the blue wavelength range.

[0015] FIG. 2 shows an example of the layout of the plurality of sub-pixels SP (SP1, SP2, and SP3) included in the pixel PX. Here, the description will be made by focusing on four pixels PX.

[0016] The sub-pixels SP1, SP2, and SP3 constituting one pixel PX are each formed in a substantially rectangular shape extending in the second direction Y and are arranged in the first direction X. Looking at two pixels PX arranged in the first direction X, the colors displayed in the sub-pixels SP adjacent in the first direction X are different from each other. Further, looking at two pixels PX arranged in the second direction Y, the colors displayed in the sub-pixels SP adjacent in the second direction Y are the same. Note that the areas of the sub-pixels SP1, SP2, and SP3 may be the same or different from each other.

[0017] FIG. 3 shows another example of the layout of the plurality of sub-pixels SP (SP1, SP2, and SP3) included in the pixel PX.

[0018] The sub-pixels SP1 and SP2 that constitute one pixel PX are arranged in the second direction Y, the sub-pixels SP1 and SP3 are arranged in the first direction X, and the sub-pixels SP2 and SP3 are arranged in the first direction X. The sub-pixel SP1 is formed in a substantially rectangular shape extending in the first direction X, and the sub-pixels SP2 and SP3 are formed in a substantially rectangular shape extending in the second direction Y. The area of the sub-pixel SP2 is larger than the area of the sub-pixel SP1, and the area of the sub-pixel SP3 is larger than the area of the sub-pixel SP2. Note that the shape and area of the sub-pixel SP1 may be the same as those of the sub-pixel SP2.

[0019] Focusing on two pixels PX arranged in the first direction X, in the region where the sub-pixels SP1 and SP3 are alternately arranged and the region where the sub-pixels SP2 and SP3 are alternately arranged, the colors displayed in the sub-pixels SP adjacent in the first direction X are different from each other. On the other hand, focusing on two pixels PX arranged in the second direction Y, in the region where the sub-pixels SP1 and SP2 are alternately arranged, the colors displayed in the sub-pixels SP adjacent in the second direction Y are different from each other. Also, in the region where a plurality of sub-pixels SP3 are arranged, the colors displayed in the sub-pixels SP adjacent in the second direction are the same.

[0020] Note that the outer shapes of the sub-pixels SP1, SP2, and SP3 shown in FIGS. 2 and 3 correspond to the outer shapes of the regions (i.e., light-emitting regions) where colors are displayed in the sub-pixels SP, but are shown in a simplified manner and do not necessarily reflect the actual shapes.

[0021] Here, although details will be described later, ribs and partition walls are arranged in the display area DA in the present embodiment. The ribs each have an opening in the sub-pixels SP1, SP2, and SP3. The partition walls are arranged at the boundaries between adjacent sub-pixels SP and overlap the ribs in a plan view. Specifically, the partition walls are arranged between the openings (sub-pixels SP) adjacent in the first direction X and between the openings (sub-pixels SP) adjacent in the second direction Y. Thereby, the partition walls are formed in a lattice shape so as to partition the sub-pixels SP1, SP2, and SP3 as a whole. In other words, it can also be said that the partition walls have openings in the sub-pixels SP1, SP2, and SP3, similar to the ribs.

[0022] Figure 4 is a schematic cross-sectional view of the display device DSP along the line A-A in Figure 2. In the display device DSP, an insulating layer 11 called an undercoat layer is disposed on the substrate 10 having light transmissivity such as the glass described above (on the surface on which light-emitting elements and the like are disposed).

[0023] The insulating layer 11 has, for example, a three-layer laminated structure having a silicon oxide film (SiO), a silicon nitride film (SiN), and a silicon oxide film (SiO). Note that the insulating layer 11 is not limited to the three-layer laminated structure. The insulating layer 11 may have a laminated structure with more than three layers, or may have a single-layer structure or a two-layer laminated structure.

[0024] A circuit layer 12 is disposed on the insulating layer 11. The circuit layer 12 has pixel circuits (various circuits and wirings) for driving the light-emitting elements included in each of the sub-pixels SP1, SP2, and SP3 as described above. The circuit layer 12 is covered with an insulating layer 13.

[0025] The insulating layer 13 functions as a planarization film that planarizes the unevenness caused by the circuit layer 12. Although not shown in Figure 4, the insulating layer 13 is provided with contact holes for connecting the lower electrodes LE to the pixel circuits.

[0026] The lower electrodes LE (LE1, LE2, and LE3) are disposed on the insulating layer 13. The rib 5 is disposed on the insulating layer 13 and the lower electrodes LE. An end portion (a part) of the lower electrode LE is covered with the rib 5.

[0027] The partition wall 6 has a lower portion 61 disposed on the rib 5 and an upper portion 62 covering the upper surface of the lower portion 61. The upper portion 62 has a width larger than that of the lower portion 61 in the first direction X and the second direction Y. Thereby, the partition wall 6 has a shape in which both end portions of the upper portion 62 protrude from the side surfaces of the lower portion 61. Such a shape of the partition wall 6 can be referred to as an overhang shape.

[0028] The organic layer OR (OR1, OR2, and OR3) and the upper electrode UE (UE1, UE2, and UE3) together with the above-described lower electrode LE (LE1, LE2, and LE3) constitute a light-emitting element included in the sub-pixel SP.

[0029] As shown in FIG. 4, the organic layer OR1 includes a first organic layer OR1a and a second organic layer OR1b spaced apart from each other. The upper electrode UE1 includes a first upper electrode UE1a and a second upper electrode UE1b spaced apart from each other. The first organic layer OR1a contacts the lower electrode LE1 through an opening AP1 (an opening that the rib 5 has in the sub-pixel SP1) and covers a part of the rib 5. The second organic layer OR1b is located above the upper portion 62. The first upper electrode UE1a faces the lower electrode LE1 and covers the first organic layer OR1a. Further, the first upper electrode UE1a contacts the side surface of the lower portion 61. The second upper electrode UE1b is located above the partition wall 6 and covers the second organic layer OR1b.

[0030] Also, as shown in FIG. 4, the organic layer OR2 includes a first organic layer OR2a and a second organic layer OR2b spaced apart from each other. The upper electrode UE2 includes a first upper electrode UE2a and a second upper electrode UE2b spaced apart from each other. The first organic layer OR2a contacts the lower electrode LE2 through an opening AP2 (an opening that the rib 5 has in the sub-pixel SP2) and covers a part of the rib 5. The second organic layer OR2b is located above the upper portion 62. The first upper electrode UE2a faces the lower electrode LE2 and covers the first organic layer OR2a. Further, the first upper electrode UE2a contacts the side surface of the lower portion 61. The second upper electrode UE2b is located above the partition wall 6 and covers the second organic layer OR2b.

[0031] Also, as shown in FIG. 4, the organic layer OR3 includes a first organic layer OR3a and a second organic layer OR3b spaced apart from each other. The upper electrode UE3 includes a first upper electrode UE3a and a second upper electrode UE3b spaced apart from each other. The first organic layer OR3a contacts the lower electrode LE3 through the opening AP3 (the opening of the rib 5 in the sub-pixel SP3) and covers a part of the rib 5. The second organic layer OR3b is located on the upper portion 62. The first upper electrode UE3a faces the lower electrode LE3 and covers the first organic layer OR3a. Further, the first upper electrode UE3a contacts the side surface of the lower portion 61. The second upper electrode UE3b is located above the partition wall 6 and covers the second organic layer OR3b.

[0032] In the example shown in FIG. 4, the sub-pixels SP1, SP2, and SP3 include cap layers CP1, CP2, and CP3 (optical path adjustment layers) for adjusting the optical characteristics of the light emitted from the light-emitting layers of the organic layers OR1, OR2, and OR3.

[0033] The cap layer CP1 includes a first cap layer CP1a and a second cap layer CP1b spaced apart from each other. The first cap layer CP1a is located in the opening AP1 and disposed on the first upper electrode UE1a. The second cap layer CP1b is located above the partition wall 6 and disposed on the second upper electrode UE1b.

[0034] The cap layer CP2 includes a first cap layer CP2a and a second cap layer CP2b spaced apart from each other. The first cap layer CP2a is located in the opening AP2 and disposed on the first upper electrode UE2a. The second cap layer CP2b is located above the partition wall 6 and disposed on the second upper electrode UE2b.

[0035] The cap layer CP3 includes a first cap layer CP3a and a second cap layer CP3b spaced apart from each other. The first cap layer CP3a is located in the opening AP3 and disposed on the first upper electrode UE3a. The second cap layer CP3b is located above the partition wall 6 and disposed on the second upper electrode UE3b.

[0036] Sealing layers SE1, SE2, and SE3 are respectively disposed on sub-pixels SP1, SP2, and SP3. The sealing layer SE1 continuously covers each member of the sub-pixel SP1 including the first cap layer CP1a, the partition wall 6, and the second cap layer CP1b. The sealing layer SE2 continuously covers each member of the sub-pixel SP2 including the first cap layer CP2a, the partition wall 6, and the second cap layer CP2b. The sealing layer SE3 continuously covers each member of the sub-pixel SP3 including the first cap layer CP3a, the partition wall 6, and the second cap layer CP3b.

[0037] In the example shown in FIG. 4, the second organic layer OR1b, the second upper electrode UE1b, the second cap layer CP1b, and the sealing layer SE1 on the partition wall 6 between the sub-pixels SP1 and SP2 are separated from the second organic layer OR2b, the second upper electrode UE2b, the second cap layer CP2b, and the sealing layer SE2 on the partition wall 6. Also, the second organic layer OR2b, the second upper electrode UE2b, the second cap layer CP2b, and the sealing layer SE2 on the partition wall 6 between the sub-pixels SP2 and SP3 are separated from the second organic layer OR3b, the second upper electrode UE3b, the second cap layer CP3b, and the sealing layer SE3 on the partition wall 6.

[0038] The sealing layers SE1, SE2, and SE3 are covered by a resin layer 14 (planarization film). The resin layer 14 is covered by a sealing layer 15. Further, the sealing layer 15 is covered by a resin layer 16.

[0039] The insulating layer 13 and the resin layers 14 and 16 are formed of an organic material. The rib 5 and the sealing layers 15 and SE (SE1, SE2, and SE3) are formed of an inorganic material such as silicon nitride (SiNx).

[0040] The lower portion 61 of the partition wall 6 has conductivity. The upper portion 62 of the partition wall 6 may also have conductivity. The lower electrode LE may be formed of a transparent conductive oxide such as ITO (Indium Tin Oxide), or may have a laminated structure of a metal material such as silver (Ag) and a conductive oxide. The upper electrode UE may be formed of a conductive oxide such as ITO.

[0041] When the potential of the lower electrode LE is relatively higher than that of the upper electrode UE, the lower electrode LE corresponds to the anode and the upper electrode UE corresponds to the cathode. Also, when the potential of the upper electrode UE is relatively higher than that of the lower electrode LE, the upper electrode UE corresponds to the anode and the lower electrode LE corresponds to the cathode.

[0042] The organic layer OR includes a pair of functional layers and a light-emitting layer disposed between these functional layers. As an example, the organic layer OR has a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, a light-emitting layer, a hole blocking layer, an electron transport layer, and an electron injection layer are laminated in this order.

[0043] The cap layer CP (CP1, CP2, and CP3) is formed, for example, by a multilayer body of a plurality of transparent thin films. The multilayer body may include, as the plurality of thin films, a thin film formed of an inorganic material and a thin film formed of an organic material. Also, these plurality of thin films have different refractive indexes from each other. The material of the thin film constituting the multilayer body is different from the material of the upper electrode UE and also different from the material of the sealing layer SE. Note that the cap layer CP may be omitted.

[0044] A common voltage is supplied to the partition wall 6. This common voltage is supplied to the upper electrodes UE (first upper electrodes UE1a, UE2a, and UE3a) in contact with the side surface of the lower portion 61, respectively. Pixel voltages are supplied to the lower electrodes LE (LE1, LE2, and LE3) through the pixel circuits respectively included in the sub-pixels SP (SP1, SP2, and SP3).

[0045] When a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of the first organic layer OR1a emits light in the red wavelength range. When a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of the first organic layer OR2a emits light in the green wavelength range. When a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of the first organic layer OR3a emits light in the blue wavelength range.

[0046] As another example, the light-emitting layers of the organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include a color filter that converts the light emitted by the light-emitting layer into light of a color corresponding to the sub-pixels SP1, SP2, and SP3. Further, the display device DSP may include a layer containing quantum dots that are excited by the light emitted by the light-emitting layer to generate light of a color corresponding to the sub-pixels SP1, SP2, and SP3.

[0047] FIG. 5 is a schematic enlarged cross-sectional view of the partition wall 6. In FIG. 5, elements other than the rib 5, the partition wall 6, the insulating layer 13, and the pair of lower electrodes LE are omitted. The pair of lower electrodes LE corresponds to any one of the lower electrodes LE1, LE2, and LE3 described above.

[0048] In the example shown in FIG. 5, the lower portion 61 of the partition wall 6 includes a barrier layer (bottom portion) 611 disposed on the rib 5 and a metal layer (axial portion) 612 disposed on the barrier layer 611. The barrier layer 611 is formed of a material different from that of the metal layer 612 and is formed of a metal material such as molybdenum (Mo), titanium (Ti), and titanium nitride (TiN), for example. The metal layer 612 is formed thicker than the barrier layer 611. The metal layer 612 may have a single-layer structure or may be a simple laminated structure of a metal material. As an example, the metal layer 612 is formed of aluminum (Al), for example.

[0049] The upper portion (top portion) 62 is thinner than the lower portion 61. In the example shown in FIG. 5, the upper portion 62 includes a first layer 621 disposed on the metal layer 612 and a second layer 622 disposed on the first layer 621. As an example, the first layer 621 is formed of titanium (Ti), for example, and the second layer 622 is formed of ITO, for example.

[0050] In the example shown in FIG. 5, the width of the lower portion 61 decreases as it approaches the upper portion 62. That is, the side surfaces 61a and 61b of the lower portion 61 are inclined with respect to the third direction Z. The upper portion 62 has an end portion 62a protruding from the side surface 61a and an end portion 62b protruding from the side surface 61b.

[0051] The protruding amounts D of the end portions 62a and 62b from the side surfaces 61a and 61b (hereinafter referred to as the protruding amount D of the partition wall 6) are, for example, 2.0 μm or less. The protruding amount D of the partition wall 6 in the present embodiment corresponds to the distance in the width direction (the first direction X or the second direction Y) orthogonal to the third direction Z of the partition wall 6 between the lower ends (barrier layer 611) of the side surfaces 61a and 61b and the end portions 62a and 62b.

[0052] In the example shown in FIG. 5, the side surfaces of the barrier layer 611 and the side surfaces of the metal layer 612 are aligned to form a flat surface without a step. However, for example, the side surface of the barrier layer 611 may slightly recede from the side surface of the metal layer 612 or may protrude from the side surface of the metal layer 612. Further, in FIG. 5, the side surfaces of the barrier layer 611 and the metal layer 612 (that is, the side surfaces 61a and 61b of the lower portion 61) are inclined with respect to the third direction Z, but the side surfaces may be parallel to the third direction Z.

[0053] The structure of the partition wall 6 and the materials of each part of the partition wall 6 can be appropriately selected in consideration of, for example, the method of forming the partition wall 6.

[0054] Here, in the present embodiment, the partition wall 6 is formed so as to partition the sub-pixels SP in a plan view. The above-described organic layer OR is formed, for example, by an anisotropic or directional vacuum deposition method. However, when the organic material for forming the organic layer OR is deposited on the entire substrate 10 with the partition wall 6 disposed, since the partition wall 6 has the shape shown in FIGS. 4 and 5, almost no organic layer OR is formed on the side surfaces of the partition wall 6. According to this, an organic layer OR (light-emitting element) divided for each sub-pixel SP by the partition wall 6 can be formed.

[0055] FIGS. 6 to 8 are schematic cross-sectional views for explaining a light-emitting element formed using the partition wall 6. In FIGS. 6 to 8, the substrate 10, the insulating layer 11, and the circuit layer 12 are omitted. Further, the sub-pixels SPα, SPβ, and SPγ shown in FIGS. 6 to 8 correspond to any one of the sub-pixels SP1, SP2, and SP3.

[0056] First, with the partition wall 6 arranged as described above, as shown in FIG. 6, an organic layer OR, an upper electrode UE, a cap layer CP, and a sealing layer SE are sequentially formed by vapor deposition on the entire substrate 10. The organic layer OR includes a light-emitting layer that emits light of a color corresponding to the sub-pixel SPα. Due to the overhanging partition wall 6, the organic layer OR is divided into a first organic layer ORa that contacts the lower electrode LE through the opening AP and a second organic layer ORb on the partition wall 6. The upper electrode UE is divided into a first upper electrode UEa that covers the first organic layer ORa and a second upper electrode UEb that covers the second organic layer ORb. The cap layer CP is divided into a first cap layer CPa that covers the first upper electrode UEa and a second cap layer CPb that covers the second upper electrode UEb. The first upper electrode UEa is in contact with the lower portion 61 of the partition wall 6. The sealing layer SE continuously covers the first cap layer CPa, the partition wall 6, and the second cap layer CPb.

[0057] Next, as shown in FIG. 7, a resist R is formed on the sealing layer SE. The resist R covers the sub-pixel SPα. That is, the resist R is disposed directly above the first organic layer ORa, the first upper electrode UEa, and the first cap layer CPa located in the sub-pixel SPα. The resist R is also located directly above the portion of the second organic layer ORb, the second upper electrode UEb, and the second cap layer CPb on the partition wall 6 between the sub-pixel SPα and the sub-pixel SPβ, closer to the sub-pixel SPα. That is, at least a part of the partition wall 6 is exposed from the resist R.

[0058] Furthermore, by etching using the resist R as a mask, as shown in FIG. 8, the portions of the organic layer OR, the upper electrode UE, the cap layer CP, and the sealing layer SE that are exposed from the resist R are removed. As a result, a light-emitting element including the lower electrode LE, the first organic layer ORa, the first upper electrode UEa, and the first cap layer CPa is formed in the sub-pixel SPα. On the other hand, the lower electrode LE is exposed in the sub-pixels SPβ and SPγ. The above-described etching includes, for example, dry etching of the sealing layer SE, wet etching and dry etching of the cap layer CP, wet etching of the upper electrode UE, and dry etching of the organic layer OR.

[0059] As described above, when the light-emitting element of the sub-pixel SPα is formed, the resist R is removed, and the light-emitting elements of the sub-pixels SPβ and SPγ are formed in order, similarly to the sub-pixel SPα.

[0060] As exemplified for the above sub-pixels SPα, SPβ, and SPγ, the light-emitting elements of the sub-pixels SP1, SP2, and SP3 are formed, and further, the resin layer 14, the sealing layer 15, and the resin layer 16 are formed, whereby the structure of the display device DSP shown in FIG. 4 is realized.

[0061] Here, as described above, each of the plurality of sub-pixels SP includes a pixel circuit for driving the light-emitting element. Hereinafter, with reference to FIG. 9, an example of the circuit configuration of the pixel circuit will be described. Note that the pixel circuit 100 shown in FIG. 9 is a 7Tr1C pixel circuit having seven transistors Tr1 to Tr7 and one holding capacitor Cst.

[0062] In the following description, one of the source terminals and drain terminals of each of the transistors Tr1 to Tr7 shown in FIG. 9 is defined as the first terminal, and the other is defined as the second terminal. Also, one terminal of the holding capacitor Cst (the capacitive element that realizes it) shown in FIG. 9 is defined as the first terminal, and the other terminal is defined as the second terminal.

[0063] The first terminal of the transistor Tr1 is connected to the first terminal of the transistor Tr2 and the second terminal of the transistor Tr5 via the node n3. The second terminal of the transistor Tr1 is connected to a data signal line that supplies the data signal Data. The data signal Data corresponds to a signal (pixel signal) written to the pixel. Note that the transistor Tr1 is, for example, an n-channel type transistor.

[0064] Transistor Tr2 corresponds to a driving transistor (DRT) that supplies current to the light-emitting element 20 included in the sub-pixel SP (that is, the light-emitting element 20 driven by the pixel circuit 100). The first terminal of transistor Tr2 is connected to the first terminal of transistor Tr1 and the second terminal of transistor Tr5 via node n3. The second terminal of transistor Tr2 is connected to the second terminal of transistor Tr3, the first terminal of transistor Tr4, and the first terminal of transistor Tr7 via node n1. Note that transistor Tr2 is, for example, an n-channel transistor.

[0065] The first terminal of transistor Tr3 is connected to the gate terminal of transistor Tr2 and the second terminal of the holding capacitor Cst via node n2. The second terminal of transistor Tr3 is connected to the second terminal of transistor Tr2, the first terminal of transistor Tr4, and the first terminal of transistor Tr7 via node n1. Note that transistor Tr3 is, for example, an n-channel transistor.

[0066] The first terminal of transistor Tr4 is connected to the second terminal of transistor Tr2, the second terminal of transistor Tr3, and the first terminal of transistor Tr7 via node n1. The second terminal of transistor Tr4 is connected to a power supply line that supplies the power supply voltage VDDEL. Note that transistor Tr4 is, for example, a p-channel transistor.

[0067] The first terminal of transistor Tr5 is connected to the first terminal of transistor Tr6, the first terminal of the holding capacitor Cst, and the anode terminal of the light-emitting element 20 via node n4. The second terminal of transistor Tr5 is connected to the first terminal of transistor Tr1 and the first terminal of transistor Tr2 via node n3. Note that transistor Tr5 is, for example, a p-channel transistor.

[0068] The first terminal of transistor Tr6 is connected, via node n4, to the first terminal of transistor Tr5, the first terminal of holding capacitor Cst, and the anode terminal of light-emitting element 20. The second terminal of transistor Tr6 is connected to a power supply line that supplies initialization voltage Vini. Note that transistor Tr6 is, for example, an n-channel type transistor.

[0069] The first terminal of transistor Tr7 is connected, via node n1, to the second terminal of transistor Tr2, the second terminal of transistor Tr3, and the first terminal of transistor Tr4. The second terminal of transistor Tr7 is connected to a power supply line that supplies power supply voltage VSH. Note that transistor Tr7 is, for example, an n-channel type transistor.

[0070] Also, as shown in FIG. 9, the gate terminal of transistor Tr1 is connected to a gate signal line that supplies gate signal Scan2. The gate terminal of transistor Tr3 is connected to a gate signal line that supplies gate signal Scan1. The gate terminals of transistors Tr4 to Tr6 are connected to a control signal line that supplies control signal EM. The gate terminal of transistor Tr7 is connected to a gate signal line that supplies gate signal Scan3.

[0071] The first terminal of holding capacitor Cst is connected, via node n4, to the first terminal of transistor Tr5, the first terminal of transistor Tr6, and the anode terminal of light-emitting element 20. The second terminal of holding capacitor Cst is connected, via node n2, to the gate terminal of transistor Tr2 and the first terminal of transistor Tr3.

[0072] The anode terminal of light-emitting element 20 is connected, via node n4, to the first terminal of transistor Tr5, the first terminal of transistor Tr6, and the first terminal of holding capacitor Cst. The cathode terminal of light-emitting element 20 is connected to a power supply line that supplies power supply voltage VSSEL. The above-described power supply voltage VDDEL corresponds to the anode voltage supplied to light-emitting element 20, and power supply voltage VSSEL corresponds to the cathode voltage supplied to light-emitting element 20.

[0073] Hereinafter, with reference to FIG. 10, an example of the operation of the pixel circuit 100 (7Tr1C pixel circuit) in the comparative example of the present embodiment will be described. FIG. 10 is a timing chart showing output examples of the gate signals Scan1 to Scan3 and the control signal EM for the pixel circuit 100 (including the sub-pixel SP).

[0074] Note that the plurality of transistors constituting the pixel circuit 100 include n-channel transistors and p-channel transistors. The n-channel transistor is a switching element that becomes an off state (non-conducting state) when a low (level) signal is supplied to the gate terminal, and becomes an on state (conducting state) when a high (level) signal is supplied to the gate terminal. On the other hand, the p-channel transistor is a switching element that becomes an off state (non-conducting state) when a high (level) signal is supplied to the gate terminal, and becomes an on state (conducting state) when a low (level) signal is supplied to the gate terminal.

[0075] In the period t0 shown in FIG. 10, since the control signal EM is low, the transistors Tr4 and Tr5 among the seven transistors included in the pixel circuit 100 are in the on state, and the transistor Tr6 is in the off state.

[0076] Also, in the period t0, since the gate signals Scan1 to Scan3 are low, the transistors Tr1, Tr3, and Tr7 are in the off state.

[0077] Accordingly, a current controlled by the gate voltage of the transistor Tr2 (the voltage supplied to the gate terminal of the transistor Tr2 based on the data signal Data of the previous frame) flows through the light-emitting element 20 (OLED), and the state in which the light-emitting element 20 emits light is maintained.

[0078] Note that at the timing when the period t0 ends, the control signal EM is switched from low to high.

[0079] Next, the period t1 shown in FIG. 10 corresponds to a reset period for resetting the voltage written in the holding capacitor Cst based on the power supply voltage VSH and the initialization voltage Vini. In the period t1, since the control signal EM is high, the transistors Tr4 and Tr5 are in the off state, and the transistor Tr6 is in the on state. In this case, the initialization voltage Vini is supplied to the node n4 via the transistor Tr6, but since the initialization voltage Vini is set to a value at which no current flows through the light-emitting element 20, no current flows through the light-emitting element 20 in the period t1.

[0080] Also, at the timing when the period t1 starts, the gate signal Scan1 is switched from low to high. For this reason, in the period t1, the transistor Tr3 becomes in the on state. Further, after the period t0 ends and before the period t1 starts, the gate signal Scan3 is switched from low to high. For this reason, in the period t1, the transistor Tr7 is in the on state. According to this, the power supply voltage VSH is supplied to the gate terminal of the transistor Tr2 via the transistors Tr7 and Tr3. In this case, a voltage of VSH - Vini is applied across the holding capacitor Cst (between the first and second terminals), and the information of the previous frame is reset.

[0081] Note that at the timing when the period t1 ends, the gate signal Scan3 is switched from high to low.

[0082] Next, the period t2 shown in FIG. 10 corresponds to a sampling period in which a voltage corresponding to the data signal Data is written into the holding capacitor Cst. At the timing when the period t2 starts, the gate signal Scan2 is switched from low to high. For this reason, in the period t2, the transistor Tr1 becomes in the on state. Also, in the period t2, since the gate signal Scan3 is low, the transistor Tr7 is in the off state.

[0083] In this case, the gate terminal (node n2) of transistor Tr2 is supplied with the data signal Data (voltage Vdata corresponding thereto) and the threshold voltage Vth of transistor Tr2 (i.e., a voltage corresponding to Vdata + Vth) via transistors Tr1 to Tr3. According to this, a voltage of Vdata + Vth - Vini is applied to the holding capacitor Cst, and information regarding Vdata and Vth is written into the holding capacitor Cst (i.e., a voltage for controlling the current supplied from transistor Tr2 to the light-emitting element 20 is written into the holding capacitor Cst).

[0084] Note that at the timing when the period t2 ends, the gate signal Scan1 is switched from high to low.

[0085] Next, the period t3 shown in FIG. 10 corresponds to a light-emitting period in which current is supplied to the light-emitting element 20 (i.e., the light-emitting element 20 emits light). In the period t3, since the gate signal Scan1 is low, transistor Tr3 is in the off state. Also, since the gate signal Scan2 has been switched from high to low before the period t3 starts, transistor Tr1 is in the off state. Further, the control signal EM is switched from high to low at the timing when the period t3 starts. For this reason, transistors Tr4 and Tr5 turn on, and transistor Tr6 turns off.

[0086] Here, assuming that the first terminal of transistor Tr2 is the source terminal, the voltage Vgs between the gate terminal and the source terminal (node n2 to node n3) of transistor Tr2 is the voltage of the holding capacitor Cst (Vdata + Vth - Vini). In this case, transistor Tr2 turns on, and a current flows from the power supply line (the power supply line supplying the power supply voltage VDDEL) connected to the second terminal of transistor Tr4 toward node n4. Along with this, the potential of node n4 starts to rise. When the potential exceeds the threshold value of the light-emitting element 20 (OLED), a current starts to flow through the light-emitting element 20, and light emission of the light-emitting element 20 starts. Finally, when the current Ioled flowing through the light-emitting element 20 reaches the output current (the output current in the saturation region of transistor Tr2) Idrt supplied from transistor Tr2, the potential rise of node n4 stops, and the light-emitting element 20 enters a steady light-emitting state.

[0087] Note that substituting the voltage Vgs = Vdata + Vth - Vini between the gate terminal and the source terminal of transistor Tr2 into the TFT saturation formula Idrt = 1 / 2Cox * μ * W / L * (Vgs - Vth) 2 yields Idrt (= Ioled) = 1 / 2Cox * μ * W / L * (Vdata - Vini) 2 where Cox is the gate capacitance per unit area, μ is the carrier mobility, W is the channel width of transistor Tr2, and L is the channel length of transistor Tr2.

[0088] Accordingly, it can be seen that Idrt becomes a value independent of the threshold voltage Vth of transistor Tr2 (that is, a current independent of the threshold voltage Vth of transistor Tr2 flows through the light-emitting element 20), and the influence of the variation in the threshold voltage Vth on Idrt can be eliminated.

[0089] That is, it can be said that the above-described pixel circuit 100 (7Tr1C pixel circuit) has a function (Vth correction function) of correcting the variation in the threshold voltage Vth of transistor Tr2.

[0090] Incidentally, the display device DSP operates to sequentially display frames (images) in the display area DA. However, in the comparative example of the present embodiment, during the period for displaying one frame in the display area DA (hereinafter referred to as the one-frame period), the above-described reset period (period t1 shown in FIG. 10), sampling period (period t2 shown in FIG. 10), and light emission period (period t3 shown in FIG. 10) are included.

[0091] Here, referring to FIG. 11, the case where the frame displayed in each one-frame period is a black image (hereinafter referred to as black display) will be described. As described above, in the light emission period included in the one-frame period, current is supplied from the transistor Tr2 to the light emitting element 20 based on the voltage written in the holding capacitor Cst. However, in the light emission period during black display, in order to realize the luminance 201 shown in FIG. 11, the voltage Vgs applied to the transistor Tr2 is reduced (that is, the transistor Tr2 is turned off so as not to supply current to the light emitting element 20). In this case, at the timing when the light emission period during black display ends, the transistor Tr2 is in a state where carriers are not trapped in the defect in the channel region of the semiconductor layer constituting the transistor Tr2 (hereinafter referred to as the non-trapped state).

[0092] Next, referring to FIG. 12, the case where the frame displayed in each one-frame period is a white image (hereinafter referred to as white display) will be described. In the light emission period during this white display, in order to realize the luminance 202 shown in FIG. 12, the voltage Vgs applied to the transistor Tr2 is increased (that is, the transistor Tr2 is turned on so as to supply current to the light emitting element 20). In this case, at the timing when the light emission period during white display ends, the transistor Tr2 is in a state where carriers are trapped in the defect in the channel region of the semiconductor layer constituting the transistor Tr2 (hereinafter referred to as the trapped state). Thus, the transistor Tr2 in the trapped state has a smaller flowing current compared to the case where it is in the non-trapped state.

[0093] In FIGS. 11 and 12 described above, the arrangements of the reset period, sampling period, and light emission period included in one frame period are schematically shown. "Reset" represents the reset period, and "Samp" represents the sampling period. Also, "Black" shown in FIG. 11 represents the light emission period during black display, and "White" shown in FIG. 12 represents the light emission period during white display. The same applies to FIGS. 13 and 14 below.

[0094] Here, referring to FIG. 13, the case of switching from black display to white display will be described. In FIG. 13, it is assumed that the frame displayed in the (n - 1)-th one-frame period is a black image, and the frames displayed in the n-th to (n + 2)-th one-frame periods are white images.

[0095] First, since the transistor Tr2 is in the off state during the light emission period included in the (n - 1)-th one-frame period, the transistor Tr2 is in the non-trapped state at the timing when the light emission period ends.

[0096] Next, when the pixel circuit 100 operates during the reset period and sampling period included in the n-th one-frame period, a voltage of Vdata + Vth - Vini is written (applied) to the holding capacitor Cst. As a result, during the light emission period included in the n-th one-frame period, the light emitting element 20 emits light according to the current Idrt (= 1 / 2Cox*μ*W / L*(Vdata - Vini) 2 ) supplied from the transistor Tr2 based on the voltage (Vdata + Vth - Vini) written in the holding capacitor Cst.

[0097] Note that since the transistor Tr2 is in the on state during the light emission period included in the n-th one-frame period, the transistor Tr2 is in the trapped state at the timing when the light emission period ends.

[0098] Next, when the pixel circuit 100 operates during the reset period and the sampling period included in the (n + 1)-th one-frame period, since the transistor Tr2 is in the trap state, the current flowing through the transistor Tr2 during the sampling period is smaller than the current flowing through the transistor Tr2 during the sampling period included in the above-described n-th one-frame period.

[0099] In this case, a voltage corresponding to Vdata + Vth is supplied to the node n2 during the sampling period included in the n-th one-frame period, whereas the potential of the node n2 does not reach Vdata + Vth during the sampling period included in the (n + 1)-th one-frame period (that is, writing up to Vdata + Vth cannot be performed, and a voltage corresponding to Vdata + Vth + α is supplied to the node n2). According to this, a voltage of Vdata + Vth - Vini + α is written into the holding capacitor Cst, and the voltage written into the holding capacitor Cst during the (n + 1)-th one-frame period is higher than the voltage written into Cst during the n-th one-frame period.

[0100] During the light emission period included in the (n + 1)-th one-frame period, the light emitting element 20 emits light according to the current Idrt (= 1 / 2Cox*μ*W / L*(Vdata - Vini + α) 2 ) supplied from the transistor Tr2 based on the voltage (Vdata + Vth - Vini + α) written into the holding capacitor Cst in this way.

[0101] Although the (n + 1)-th one-frame period has been described here, the same applies to the (n + 2)-th one-frame period, and thus a detailed description of the (n + 2)-th one-frame period is omitted.

[0102] When switching from black display to white display as described above, as shown by the luminance 203 in FIG. 13, during the n-th one-frame period, in the frame (the first frame of white display), the current Idrt (= 1 / 2Cox*μ*W / L*(Vdata - Vini) 2) In contrast, the frames after the (n + 1)-th frame period (the second frame and subsequent frames of white display) are displayed at the luminance realized by the light-emitting element 20 emitting light according to the current Idrt (= 1 / 2Cox * μ * W / L * (Vdata - Vini + α) 2 ) are displayed at the luminance realized by the light-emitting element 20 emitting light according to this.

[0103] That is, in the comparative example of the present embodiment described above, in the sampling period included in the one-frame period for displaying the first frame of white display, the sampling progresses quickly (that is, a large current flows through the transistor Tr2 in the sampling period), so the luminance of the first frame of white display is lower than the luminance of the second and subsequent frames of white display, and the display quality of the display device DSP deteriorates based on the luminance difference.

[0104] Therefore, in the present embodiment, as shown in FIG. 14, a Pre-Activate period is arranged between the reset period and the sampling period included in each one-frame period. The Pre-Activate period is a period in which a voltage Vgs is applied to the transistor Tr2 to turn on the transistor Tr2.

[0105] In the present embodiment, by turning on the transistor Tr2 during the above-described Pre-Activate period, for example, even in the first frame of white display, since the transistor Tr2 is in a trapped state, the current flowing through the transistor Tr2 in the sampling period becomes approximately the same as that in the second and subsequent frames of white display. As a result, in the present embodiment, as shown by the luminance 204 in FIG. 14, the luminance difference between the first frame and the second and subsequent frames of white display can be reduced, and a decrease in the display quality of the display device DSP can be suppressed.

[0106] Hereinafter, with reference to FIG. 15, an example of the operation of the pixel circuit 100 in the present embodiment will be described. Here, mainly the parts different from FIG. 10 described above will be described.

[0107] As shown in FIG. 15, in the present embodiment, a period t4 (Pre-Activate period) is arranged between a period t1 (reset period) and a period t2 (sampling period).

[0108] At the timing when the period t4 starts, the gate signal Scan1 is switched from high to low. Therefore, in the period t4, the transistor Tr3 is turned off.

[0109] According to such a period t4, by the coupling of the gate signal line (transistor Tr3) supplying the gate signal Scan1 and the node n1, the voltages of the source terminal and the drain terminal of the transistor Tr2 (node n1 and node n3) can be pulled down below the gate voltage.

[0110] Specifically, no current flows through the transistor Tr3 in the period t4, but the voltage of the node n1 decreases due to the influence of the coupling of the gate signal line supplying the gate signal Scan1. According to this, the transistor Tr2 is turned on by the voltage Vgd between the gate terminal and the drain terminal of the transistor Tr2, and the voltage of the node n3 decreases. Therefore, compared with the period between the periods t1 and t2 in the comparative example of the present embodiment, a higher voltage Vgs can be applied to the transistor Tr2.

[0111] In the present embodiment, by operating the pixel circuit 100 as described above in the period t4 arranged before the period t1, a Pre-Activate period for turning on the transistor Tr2 can be realized. According to such a Pre-Activate period, even when the previous frame is a black image, the state (non-trap state) of the transistor Tr2 based on the frame can be eliminated, and a current similar to that in the second and subsequent frames can be made to flow through the transistor Tr2 at the time of the first frame of white display (that is, the decrease in luminance in the first frame of white display can be suppressed).

[0112] Here, referring to FIG. 16, the Scan circuit and the EM circuit for realizing the gate signals Scan1 to Scan3 and the control signal EM in the comparative example of the present embodiment will be briefly described.

[0113] The Scan circuit is a circuit for outputting the gate signals Scan1 to Scan3, and includes a shift register (hereinafter referred to as the Scan circuit shift register) composed of a plurality of registers (circuits). The Scan circuit operates such that the start signal G1VST and the clock signals G1CLK1 to G1CLK3 supplied according to the horizontal period (H) shown in FIG. 16 are input to the Scan circuit shift register, and the gate signals Scan1 to Scan3 are output from the registers arranged in each stage of the Scan circuit shift register. Note that the gate signals Scan1 to Scan3 can be output according to the timing when the start signal G1VST and the clock signals G1CLK1 to G1CLK3 input to the Scan circuit shift register are switched from low to high.

[0114] Also, the EM circuit is a circuit for outputting the control signal EM, and includes a shift register (hereinafter referred to as the EM circuit shift register) composed of a plurality of registers (circuits). The EM circuit operates such that the start signal E1VST and the clock signal E1CLK supplied according to the horizontal period (H) shown in FIG. 16 are input to the EM circuit shift register, and the control signal EM is output from the registers arranged in each stage of the EM shift register. Note that the control signal EM can be output according to the timing when the start signal E1VST and the clock signal E1CLK1 input to the EM circuit shift register are switched from low to high.

[0115] Also, FIG. 17 shows an example of the configuration of a gate driver composed of the above-described Scan circuit and EM circuit.

[0116] In the example shown in FIG. 17, the shift register 301 for the Scan circuit is composed of a plurality of registers including registers SR1 to SR4. Each of the registers SR1 to SR4 is connected to a gate signal line connected to a plurality of sub-pixels SP (pixel circuits 100 included therein) constituting each row of the display area DA, and the shift register 301 for the Scan circuit operates to sequentially output the gate signal Scan3 from each of the registers SR1 to SR4.

[0117] Specifically, for example, when the register SR1 outputs the gate signal Scan3 to a plurality of sub-pixels SP constituting the m+1-th row of the display area DA, the register SR2 outputs the gate signal Scan3 to a plurality of sub-pixels SP constituting the m+2-th row of the display area DA after the gate signal Scan3 is output from the register SR1. Note that the gate signal Scan3 output from the register SR2 is used as the gate signal Scan1 output to a plurality of sub-pixels SP constituting the m+1-th row of the display area DA.

[0118] Furthermore, for example, when the register SR2 outputs the gate signal Scan3 to a plurality of sub-pixels SP constituting the m+2-th row of the display area DA, the register SR3 outputs the gate signal Scan3 to a plurality of sub-pixels SP constituting the m+3-th row of the display area DA after the gate signal Scan3 is output from the register SR2. Note that the gate signal Scan3 output from the register SR3 is used as the gate signal Scan2 output to a plurality of sub-pixels SP constituting the m+1-th row of the display area DA and the gate signal Scan1 output to a plurality of sub-pixels SP constituting the m+2-th row of the display area DA.

[0119] Also, in the example shown in FIG. 17, the shift register 302 for the EM circuit is composed of a plurality of registers including registers ER1 to ER3. The registers ER1 to ER3 are each connected to a NOT circuit (inverter) 302a, and each of the NOT circuits 302a is connected to a control signal line connected to a plurality of sub-pixels SP (pixel circuits 100 included therein) constituting each row of the display area DA. The shift register 302 for the EM circuit operates to sequentially output the control signal EM from the NOT circuits 302a connected to each of the registers ER1 to ER4.

[0120] According to the configuration of the gate driver shown in FIG. 17, it is possible to sequentially output the gate signals Scan1 to Scan3 and the control signal EM for each row (a plurality of sub-pixels SP constituting the row) of the display area DA.

[0121] By the way, in the comparative example of the present embodiment, it has been described that the gate signals Scan1 to Scan3 and the control signal EM are output from the Scan circuit and the EM circuit based on the start signal VST and the clock signals G1CLK1 to G1CLK3 shown in FIG. 16 and the start signal E1VST and the clock signal E1CLK1 described above. However, in the present embodiment, the gate signals Scan1 to Scan3 and the control signal EM are output from the Scan circuit and the EM circuit based on the start signal VST and the clock signals G1CLK1 to G1CLK3 shown in FIG. 18 and the start signal E1VST and the clock signal E1CLK1.

[0122] Note that the gate signals Scan1 and Scan2 in the comparative example of the present embodiment are signals whose timings are formed by shifting the phase of the gate signal Scan3. As shown in FIG. 15, the gate signals Scan1 and Scan2 in the present embodiment are also signals whose timings are formed by shifting the phase of Scan3 in the same manner. Also, the control signal EM in the present embodiment is the same as the control signal EM in the comparative example of the present embodiment.

[0123] According to this, the gate signals Scan1 to Scan3 and the control signal EM in the present embodiment can be realized by using the shift register 301 for the Scan circuit and the shift register 302 for the EM circuit (that is, one set of shift registers) in the comparative example of the present embodiment. Therefore, compared with the comparative example of the present embodiment, the present embodiment does not increase the peripheral circuit width.

[0124] As described above, the display device DSP according to the present embodiment includes a base material 10, a plurality of sub-pixels SP arranged in the display area DA on the base material 10, and data signal lines for supplying a data signal Data to each of the plurality of sub-pixels SP. Each of the plurality of sub-pixels SP includes a pixel circuit 100 having a transistor Tr2 (first transistor) and a holding capacitor Cst, and a light-emitting element 20 driven by the pixel circuit 100. The holding capacitor Cst is configured to write a voltage for controlling the current supplied to the light-emitting element 20. The transistor Tr2 is configured to supply a current to the light-emitting element 20 based on the voltage written in the holding capacitor Cst. One frame period for displaying one frame (image) in the display area DA includes a Pre-Activate period (second period) in which the transistor Tr2 arranged before the sampling period (first period) in which a voltage corresponding to the data signal Data is written in the holding capacitor Cst is turned on.

[0125] In this embodiment, with the above-described configuration, it is possible to suppress a decrease in the display quality of the display device DSP. Specifically, in the comparative example of this embodiment, when switching from black display to white display, the sampling in the first frame of the white display progresses faster than in the subsequent second frame and later (that is, the sampling at the time of the first white writing is faster than other white writings), resulting in a decrease in the luminance of the first frame. In contrast, in this embodiment, the transistor Tr2 is turned on in the Pre-Activate period before the sampling period included in the one-frame period for displaying the first frame of the white display (that is, a current is passed through the transistor Tr2 in advance to put the transistor Tr2 in a trapped state). As a result, the magnitude of the current flowing through the transistor Tr2 in the sampling period can be made comparable to that in the second frame, so that the difference in luminance between the first frame and the second frame and later of the white display can be reduced (that is, the black-and-white response is improved and a decrease in display quality is suppressed).

[0126] In other words, in the comparative example of this embodiment, the current flowing through the transistor Tr2 increases in the first frame at the time of switching from black display to white display, resulting in a decrease in the luminance of the first frame as a result. In contrast, in this embodiment, since the Pre-Activate period is arranged before the sampling period in each one-frame period, the magnitude of the current flowing through the transistor Tr2 (that is, the progress of sampling) can be made uniform whether the previous frame is a black image or a white image in each one-frame period.

[0127] Note that in this embodiment, one frame period includes a reset period (fourth period) for resetting the voltage written in the holding capacitor Cst based on the power supply voltage VSH (first voltage) and the initialization voltage Vini (second voltage). Although the Pre-Activate period has been described as being arranged between the reset period and the sampling period, for example, the Pre-Activate period may be arranged between the light emission period (third period) included in one frame period before the one frame period and the sampling period included in the one frame period including the Pre-Activate period (that is, after the light emission period and before the sampling period).

[0128] Also, the pixel circuit 100 in this embodiment further includes a transistor Tr3 (second transistor). The second terminal (one of the source terminal and the drain terminal) of the transistor Tr3 is connected to the second terminal (one of the source terminal and the drain terminal) of the transistor Tr2. The first terminal (the other of the source terminal and the drain terminal) of the transistor Tr3 is connected to the gate terminal of the transistor Tr2 and the second terminal (one terminal) of the holding capacitor Cst. The power supply voltage VSH is supplied to the second terminal of the holding capacitor Cst, and the initialization voltage Vini is supplied to the first terminal (the other terminal) of the holding capacitor Cst. The transistor Tr3 is turned on during the reset period and the sampling period and turned off during the Pre-Activate period. In this embodiment, with such a configuration, the Pre-Activate period can be inserted into one frame period.

[0129] (Second Embodiment) Next, the second embodiment will be described. In the first embodiment described above, it has been described that by turning off the transistor Tr3 during the Pre-Activate period, the voltage of the source terminal and the drain terminal of the transistor Tr2 is pulled down below the gate voltage. However, if the magnitude of Vgs applied during the Pre-Activate period is not sufficient, the degree of improving the black-and-white response may be small.

[0130] Therefore, in this embodiment, a configuration for further increasing the voltage Vgs applied to the transistor Tr2 during the Pre-Activate period described in the above-described first embodiment will be described.

[0131] FIG. 19 shows an example of the circuit configuration of the pixel circuit in this embodiment. In FIG. 19, the same parts as those in FIG. 9 are denoted by the same reference numerals and the detailed description thereof is omitted, and the parts different from FIG. 9 will be mainly described.

[0132] In the above-described first embodiment, it has been described that the gate terminals of the transistors Tr4 to Tr6 are connected to one control signal line (the control signal line for supplying the control signal EM), but in this embodiment, the control signal line is separated. Specifically, as shown in FIG. 19, the gate terminal of the transistor Tr4 is connected to the control signal line for supplying the control signal EM1. Further, the gate terminals of the transistors Tr5 and Tr6 are connected to the control signal line for supplying the control signal EM2.

[0133] Next, with reference to FIG. 20, an example of the operation of the pixel circuit 100 in this embodiment will be described. Here, the parts different from FIG. 15 described above will be mainly described.

[0134] As shown in FIG. 20, since the control signal EM2 is switched from low to high before the period t1 starts, in the period t1, the transistor Tr5 is in the off state and the transistor Tr6 is in the on state. According to this, as described above, a voltage of VSH - Vini is applied to the holding capacitor Cst.

[0135] Further, since the control signal EM2 is switched from high to low after the period t1 ends, in the period t4, the transistor Tr5 is in the on state and the transistor Tr6 is in the off state.

[0136] Here, according to the above-described control signal EM2, transistors Tr6 and Tr5 are turned on in order from period t1 to period t4. Therefore, in this embodiment, the initialization voltage Vini is supplied to node n3 during period t4 via transistors Tr6 and Tr5. According to this, the voltages of the source terminal and the drain terminal of transistor Tr2 can be pulled down below the gate voltage by the supplied initialization voltage Vini.

[0137] In the above-described first embodiment, it has been described that the gate voltage Vgs is applied to transistor Tr2 by the gate signal line for supplying the gate signal Scan1 and the coupling of node n1. However, in this embodiment, as described above, the gate voltage Vgs is applied to transistor Tr2 by the initialization voltage Vini. Thus, the gate voltage Vgs applied to transistor Tr2 in this embodiment is larger than the gate voltage Vgs applied to transistor Tr2 in the above-described first embodiment.

[0138] Note that the control signal EM1 in this embodiment is the same as the control signal EM in this embodiment except that it is supplied only to transistor Tr4.

[0139] Incidentally, although detailed description is omitted, the Scan circuit in this embodiment operates to output gate signals Scan1 to Scan3 based on the start signal G1VST and the clock signals G1CLK1 to G1CLK3 shown in FIG. 21, similarly to the Scan circuit in the above-described first embodiment.

[0140] On the other hand, different from the EM circuit in the above-described first embodiment, the EM circuit in this embodiment operates to output control signals EM1 and EM2 based on the start signal E1VST, and the clock signals E1CLK1 and E1CLK2 shown in FIG. 21.

[0141] Also, as shown in FIG. 22, the shift register 302 for the EM circuit in the present embodiment outputs a control signal EM1 from a NOT circuit 302a connected to each of the registers ER1 to ER3, and outputs a control signal EM2 from a NOR circuit 302b connected to each of the registers ER1 to ER3 and a signal line for supplying the clock signal E1CLK2.

[0142] That is, in the present embodiment, it is possible to realize the control signals EM1 and EM2 by adding a simple circuit element of one signal line for supplying a clock signal and one NOR circuit (terminal) to the EM circuit (shift register 302 for the EM circuit) in the first embodiment described above.

[0143] As shown in FIG. 22, the shift register 301 for the Scan circuit in the present embodiment is the same as the shift register 301 for the Scan circuit shown in FIG. 17 and does not need to be changed.

[0144] As described above, in the present embodiment, an initialization voltage Vini is supplied to the first terminal of the transistor Tr2 during the Pre-Activate period.

[0145] In order to supply the initialization voltage Vini to the first terminal of the transistor Tr2 during the Pre-Activate period in the present embodiment, the on state and off state of the transistor Tr4 (third transistor) disposed between the power supply line for supplying the power supply voltage VDDEL (third voltage) and the node n1 are controlled based on the control signal EM1 (first control signal), and the transistor Tr5 (fourth transistor) disposed between the node n3 and the node n4 and the transistor Tr6 (fifth transistor) disposed between the power supply line for supplying the initialization voltage Vini and the node n4 are controlled based on the control signal EM2 (second control signal).

[0146] In this case, the transistor Tr4 is controlled to be in an off state during the reset period, the Pre-Activate period, and the sampling period, and in an on state during the light emission period. The transistor Tr5 is controlled to be in an off state during the reset period and the sampling period, and in an on state during the Pre-Activate period and the light emission period. The transistor Tr6 is controlled to be in an off state during the Pre-Activate period and the light emission period, and in an on state during the reset period and the sampling period.

[0147] In this embodiment, due to the above-described configuration, the voltage Vgs applied to the transistor Tr2 can be increased compared to the configuration of the first embodiment described above, so that the black-and-white response can be further improved.

[0148] As described above, based on the display device described as an embodiment of the present invention, all display devices that can be appropriately designed and modified by those skilled in the art also belong to the scope of the present invention as long as they include the gist of the present invention.

[0149] Within the scope of the idea of the present invention, those skilled in the art can conceive of various modifications, and those modifications are also understood to belong to the scope of the present invention. For example, for the above-described embodiment, those obtained by appropriately adding, deleting, or modifying the components, or adding, omitting, or changing the conditions of the process by those skilled in the art also belong to the scope of the present invention as long as they have the gist of the present invention.

[0150] Also, regarding other operational effects brought about by the aspects described in the above-described embodiment, those that are obvious from the description of this specification or that can be appropriately conceived by those skilled in the art are naturally understood to be brought about by the present invention.

Explanation of Reference Numerals

[0151] DSP... display device, DA... display area, NDA... non-display area, PX... pixel, SP, SP1, SP2, SP3... sub-pixels, AP, AP1, AP2, AP3... apertures, LE, LE1, LE2, LE3... lower electrodes, UE, UE1, UE2, UE3... upper electrodes, OR, OR1, OR2, OR3... organic layers, SE, SE1, SE2, SE3... sealing layers, Tr1~Tr7... transistors, Cst... holding capacitance, SR1~SR4... registers, ER1~ER3... registers, 5... rib, 6... partition wall, 10... substrate, 11... insulating layer, 12... circuit layer, 13... insulating layer, 14... resin layer, 15... sealing layer, 16... resin layer, 20... light-emitting element, 61... lower part, 62... upper part, 100... pixel circuit, 301... shift register for Scan circuit, 302... shift register for EM circuit, 302a... NOT circuit, 302b... NOR circuit.

Claims

1. A base material, a plurality of pixels arranged in a display area on the base material, and data signal lines for supplying data signals to each of the plurality of pixels are provided, each of the plurality of pixels includes a pixel circuit having a first transistor and a holding capacitor, and a light-emitting element driven by the pixel circuit, the holding capacitor is configured to have a voltage written therein for controlling a current supplied to the light-emitting element, the first transistor is configured to supply a current to the light-emitting element based on the voltage written in the holding capacitor, a one-frame period for displaying one frame in the display area includes a second period for turning on the first transistor disposed before a first period in which a voltage corresponding to the data signal is written in the holding capacitor display device.

2. the one-frame period includes a third period for supplying a current to the light-emitting element disposed after the first period, the second period is disposed between a third period included in a previous one-frame period before the one-frame period including the second period and a first period included in the one-frame period including the second period The display device according to claim 1.

3. a first power supply line for supplying a first voltage to each of the plurality of pixels, and a second power supply line for supplying a second voltage to each of the plurality of pixels are further provided, the one-frame period includes a fourth period for resetting a voltage written in the holding capacitor based on the first and second voltages supplied from the first and second power supply lines, the second period is disposed between the fourth period and the first period The display device according to claim 2.

4. the pixel circuit further has a second transistor, one of a source terminal and a drain terminal of the second transistor is connected to one of a source terminal and a drain terminal of the first transistor, the other of the source terminal and the drain terminal of the second transistor is connected to a gate terminal of the first transistor and one terminal of the holding capacitor, a first voltage is supplied from the first power supply line to one terminal of the holding capacitor, a second voltage is supplied from the second power supply line to the other terminal of the holding capacitor, the second transistor is turned on in the fourth period and the first period and turned off in the second period The display device according to claim 3.

5. The display device according to claim 3, wherein the second voltage is supplied to one of the source terminal and the drain terminal of the first transistor in the second period.

6. The display device further includes a third power line that supplies a third voltage to each of the plurality of pixels, The pixel circuit has third to fifth transistors, One of the source terminal and the drain terminal of the third transistor is connected to the third power line, The other of the source terminal and the drain terminal of the third transistor is connected to one of the source terminal and the drain terminal of the first transistor, One of the source terminal and the drain terminal of the fourth transistor is connected to the other of the source terminal and the drain terminal of the first transistor, The other of the source terminal and the drain terminal of the fourth transistor is connected to one of the source terminal and the drain terminal of the light-emitting element and the fifth transistor, One of the source terminal and the drain terminal of the fifth transistor is further connected to the other terminal of the holding capacitor, The other of the source terminal and the drain terminal of the fifth transistor is connected to the second power line, The third transistor is in an off state in the fourth period, the second period, and the first period, and is in an on state in the third period, The fourth transistor is in an off state in the fourth period and the first period, and is in an on state in the second period and the third period, The fifth transistor is in an off state in the second period and the third period, and is in an on state in the fourth period and the first period The display device according to claim 5.

7. A first control signal line that supplies a first control signal to each of the plurality of pixels, and A second control signal line that supplies a second control signal to each of the plurality of pixels The display device further includes: The off state and the on state of the third transistor are controlled based on the first control signal, The off state and the on state of the fourth and fifth transistors are controlled based on the second control signal The display device according to claim 6.

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