Method of packaging semiconductor dies

Abstract

To provide a method of packaging semiconductor dies.SOLUTION: The method includes a first step of providing a substrate 7 and a plurality of semiconductor dies 3 arranged with spaces on the substrate 7, where an exposed surface of the substrate 7 is between the dies 3, 5. Thereafter, a film is applied to the substrate 7 to cover the plurality of semiconductor dies 3, 5 and the exposed substrate surface with a film layer 19, each die 3, 5 includes a top surface 10 and at least one side surface 23, and the film layer 19 extends across the top surfaces 10 and along the side surfaces 23 of the dies 3, 5. Subsequently, the film is removed from the top surfaces 10 of the dies 3, 5, while leaving the film intact on the side surfaces 23 of the dies 3, 5. Thereafter, the top surfaces of the dies 3, 5 are plasma-etched and the film is removed from the side surfaces 23 of the dies 3, 5. The semiconductor dies 3, 5 are thinned for use in a variety of end applications.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a method of packaging a semiconductor die, for example a method of preparing a die assembly for packaging. The present invention further relates to a method of thinning a semiconductor die, such a method following, for example, a die-to-wafer bonding process. The present invention further relates to a semiconductor die assembly, for example a hybrid-bonded semiconductor die assembly, and a plasma etching system for packaging a semiconductor die, for example for preparing a semiconductor die for packaging and / or for performing thinning of a semiconductor die.

Background Art

[0002] Thermal compression bonding, fusion, and hybrid bonding techniques are used in the manufacture of CMOS image sensors and in advanced packaging applications, for example for preparing semiconductor dies for 3D stacking. In hybrid bonding applications, different types of or the same type of semiconductor dies from different wafers are bonded (i.e., joined) through dielectric-to-dielectric and metal-to-metal connections to a substrate such as a target wafer, and thus multiple semiconductor dies can be assembled together into one package.

[0003] Die-to-wafer bonding is a preferred method of hybrid bonding because it achieves a relatively high placement accuracy of semiconductor dies compared to wafer-to-wafer bonding and other similar techniques. Die-to-wafer bonding is further a process that achieves a good level of control over the yield of the bonded wafers because only known good dies are selected for bonding. The dies are typically separated by plasma dicing the wafer through a mask before being transferred as individual dies (which can be of the same or different types) supported on a ring or frame-shaped carrier tape or on a carrier wafer to a target wafer that already contains dies.

[0004] The limitations of available pick-and-place tools impose restrictions on the size and shape of the semiconductor dies to be transferred. In particular, the die to be transferred must have sufficient thickness (i.e., height above the plane of the substrate) to be gripped and moved. In many cases, the final product defines a thinner semiconductor die package, and thus, excess semiconductor die material must be removed to thin (i.e., reduce the thickness) the die before etching.

[0005] One solution to this problem is to generate a reconfigured wafer, where the gaps between individual dies are filled with a thick dielectric film. Current plasma-enhanced chemical vapor deposition (PECVD) SiO2 films can fill gaps up to approximately 40 μm deep, and at least an equivalent amount of SiO2 further covers the surface of the die. Grinding of SiO2 and silicon and subsequent chemical mechanical polishing are required to provide a smooth, flat upper surface of the die. In many cases, the thickness of the die must be significantly reduced, and as a result, the process uses a large amount of dielectric fill material and is extremely expensive.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0007] For example, there is a need for a method of thinning a semiconductor die during or after a die-to-wafer bonding process that retains the integrity of the semiconductor die and is cost-effective in the process.

Means for Solving the Problems

[0008] In a first aspect of the present invention, a method of packaging a semiconductor die is provided. The method includes providing a substrate and a plurality of semiconductor dies spaced apart from the substrate, with an exposed surface of the substrate existing between the dies. The method further includes adding a film to the substrate to cover the plurality of semiconductor dies and the exposed surface of the substrate with a film layer, each die having an upper surface and at least one side surface, and the film layer extending across the upper surface of the die and along the side surfaces. The method further includes removing the film from the upper surface of the die while leaving the film intact on the side surfaces of the die. The method further includes plasma etching the upper surface of the die. The method includes a further step of removing the film from the side surfaces of the die.

[0009] The method advantageously provides a method of packaging a semiconductor die in which the die is thinned with high precision. The method described in the claims can be, for example, a particular use after the step of die-to-wafer bonding on a target wafer where a thicker die is required for placement on the target wafer.

[0010] Compared to certain prior art methods, the method described in the claims prevents the use of excessive materials required, for example, for depositing a dielectric layer for grinding. Under the method described in the claims, the etching of the semiconductor die is substantially completely anisotropic in the vertical direction due to the use of a film layer that provides selective passivation of the sidewalls of the die during the main etching. The sidewalls of the semiconductor die are maintained with high integrity. When applying the method described in the claims, a very smooth (i.e., having a minimum surface roughness of about 1 nm) horizontal semiconductor upper surface is provided. In addition, the method enables the silicon etching thinning step to be carried out at a relatively high etching rate of about 1 μm / min to 10 μm / min, which is relatively fast compared to methods such as chemical mechanical polishing.

[0011] The packaging method described in the claims may include a 3D integration or 2.5D integration method. The packaging method may include a method of thinning semiconductor dies in a vertical stack of dies. The method may be repeated for each die added to the stack. Alternatively, the packaging method may include a method of thinning semiconductor dies in a horizontal stack of dies.

[0012] The semiconductor die may typically be substantially cube-shaped in terms of shape. The side surfaces of the semiconductor die may be substantially perpendicular to the central horizontal plane of the substrate. The upper surface of the die may be substantially horizontal, i.e., parallel to the central horizontal plane of the substrate. The exposed surface may be substantially horizontal, i.e., parallel to the central horizontal plane of the substrate.

[0013] The film may include a polymer. Alternatively, the film may include another material having a high etching selectivity with respect to the thinning etching process. In other words, the film may be etched much more slowly than Si and the film may be removed without etching Si.

[0014] The semiconductor die may comprise an unmasked silicon die.

[0015] The film layer may directly cover the upper surface of the die without any intervening layer.

[0016] The film may be added by plasma enhanced chemical vapor deposition.

[0017] The plasma deposition process may result in conformal deposition over the die and the substrate.

[0018] The film may be added using a plasma formed from a fluorocarbon gas.

[0019] The fluorocarbon gas may form a large amount of fluorine and carbon and may be easily polymerized, so it may be particularly suitable as a process gas for plasma deposition of polymers.

[0020] The fluorocarbon gas may include C4F8. Alternatively, the fluorocarbon gas may include C5F8 or C4F6 or a mixture of the above gases.

[0021] The film can be conformally deposited, that is, having substantially the same thickness everywhere. The film can be deposited at least in the vertical and horizontal directions with respect to the horizontal plane at the center of the substrate so as to cover the upper surface and the side surfaces of the die.

[0022] The method may further include removing the film from the exposed surface of the substrate simultaneously with removing the film from the upper surface of the die.

[0023] The film can be removed from the upper surface of the die by anisotropic plasma etching.

[0024] "Anisotropic" etching is understood to mean etching in a direction perpendicular to the exposed surface of the substrate. The film can be removed from the upper surface of the die by anisotropic plasma etching in a direction perpendicular to the horizontal plane at the center of the substrate. Thus, the film is removed only where the plasma ions contact the semiconductor die assembly in the vertical direction. The high level of directionality ensures that the film remains on the side surfaces of the die while being etched from the upper surface.

[0025] The high level of directionality of the etching can be provided by the generation of a charge bias (i.e., potential difference) between (i) the semiconductor die assembly together with its peripheral components and (ii) the plasma. Such a charge bias can be generated by supplying RF power to at least one support component (e.g., an electrostatic chuck) of the semiconductor die assembly. The alternating current can result in a negative potential being generated on the semiconductor die assembly and the support component, and then the negative potential attracts positive ions towards the semiconductor die assembly. To generate an appropriate charge bias, the RF power, i.e., the "RF bias power", may need to be supplied at higher than 200W, for example higher than 300W.

[0026] The film can be removed from the top surface of the die using plasma formed from SF6 gas.

[0027] Since SF6 gas can be selectively used to etch both silicon and the polymer film, it can be particularly suitable as a process gas for plasma etching of the polymer film. As described above, the use of RF bias power supplied to one or more components that support a semiconductor die assembly (e.g., an electrostatic chuck) can result in a high level of directionality for plasma etching the polymer film. Additionally, the use of a relatively low pressure can minimize ion collisions to enable substantially vertical ion implantation into the semiconductor die assembly.

[0028] Alternatively, the plasma can be formed from another gas such as, for example, NF3 or CF4 gas.

[0029] The film can be removed from the side surfaces of the die by isotropic plasma ashing. "Isotropic" plasma ashing is understood to mean that it is not completely directional. Plasma ashing without any specific directionality can be a particularly effective technique for removing all remaining polymer from the semiconductor die assembly.

[0030] The film can be removed from the side surfaces of the die using an oxygen-based ashing chemistry such as, for example, O2 or O2 / Ar.

[0031] Since CO and CO2 can be formed, oxygen-containing gases are particularly suitable for removing the polymer film from the side surfaces of the die.

[0032] The film layer can be added substantially over the entire substrate.

[0033] The film layer can be added such that there is no uncovered portion of the substrate or die.

[0034] The film layer can spread along each side surface of the die.

[0035] Thus, while the top surface of the die is etched, the film can remain intact on each side of the die.

[0036] The film layer can have a maximum thickness of less than 5 μm.

[0037] The film layer can have a maximum thickness of less than 2 μm, for example less than 1 μm.

[0038] The film layer can have a substantially constant average thickness with a maximum thickness variation from the average thickness of less than 20%.

[0039] The maximum thickness variation can be less than 10%, for example less than 5%.

[0040] The film can be applied to the substrate in a single deposition step.

[0041] The top surface of the die can be etched until the thickness of each die between the exposed surface of the substrate and the top surface of the die is less than a threshold thickness defined by the user.

[0042] The threshold thickness can be 20 μm.

[0043] The threshold thickness can be 10 μm.

[0044] The threshold thickness can be application-specific and can be preset by the user using a control device before the method is implemented.

[0045] The top surface of the die can be etched using, for example, a cyclic etching process similar to that described in U.S. Patent No. 9,842,772, which is the applicant's patent. The cyclic process can help to maintain a smooth surface when exposed through silicon vias and can further provide high selectivity to SiO2. Alternatively, if there is no need to protect features of buried SiO2, for example, the top surface of the die can be etched using a one-step process.

[0046] The upper surface of the die can be etched using a plasma formed from SF6 gas.

[0047] The plurality of semiconductor dies can include at least one die of a first type and at least one die of a second type, and the method can include a preceding step of bonding at least one die of the first type to a substrate to provide a plurality of semiconductor dies spaced apart on the substrate, wherein at least one die of the second type is pre-bonded to the substrate. Alternatively, the dies can be of the same type and are selected from different wafers and bonded to a target substrate that has been removed.

[0048] The plurality of semiconductor dies can include at least one die transferred from a first wafer to a substrate and a plurality of further dies supported on the substrate, and the method can include a preceding step of bonding at least one die to the substrate, wherein the plurality of further dies are pre-bonded to the substrate. The dies can be bonded in a stacked manner. The dies can be stacked in a suitable configuration, for example, in a vertical stack or a horizontal stack. A plurality of dynamic random access memory (DRAM) dies can be stacked.

[0049] The method can include a step of die-to-wafer bonding to provide a substrate and a plurality of semiconductor dies spaced apart on the substrate.

[0050] The substrate can include a semiconductor material.

[0051] The substrate can include a dielectric material.

[0052] The substrate can include a tape or be supported on a tape.

[0053] The method can further include a subsequent step of adding a packaging material to the substrate to embed the substrate and the die.

[0054] A plurality of semiconductor dies may be included in an upper layer of a plurality of vertical stacks of dies. Alternatively, the plurality of semiconductor dies may be included in a plurality of horizontal stacks of dies, and the film layer extends across the upper surface of the dies and along a plurality of outward-facing sides (i.e., exposed outer sides) of the dies.

[0055] In a second aspect, a method for thinning semiconductor dies is provided. The method includes adding a continuous film layer over a plurality of unmasked dies supported on a substrate to cover the upper surface and each side surface of the dies. The method includes plasma etching the film layer to expose the upper surface of each die among the plurality of unmasked dies while leaving the film layer covering the side surfaces. The method includes plasma etching the exposed upper surface of the dies. The method includes plasma ashing the film layer remaining on the side surfaces of the dies so that the film layer is completely removed.

[0056] The plurality of unmasked dies may be included in an upper layer of a plurality of vertical stacks of dies, with two or more dies present in each stack, and the continuous film layer covers the upper surfaces of the plurality of unmasked dies in the upper layer and the side surfaces of each die in each stack.

[0057] The method may further include transferring additional unmasked dies to each stack to form a new plurality of unmasked dies included in a new upper layer, and then adding a new continuous film layer over the new plurality of unmasked dies, wherein the new continuous film layer covers the upper surface of the dies in the new upper layer and the side surfaces of each die in each stack, plasma etching the new film layer to expose the upper surface of each die in the new upper layer while leaving the new film layer covering the side surfaces, plasma etching the exposed upper surface of the dies, and plasma ashing the new film layer remaining on the side surfaces of the dies so that the new film layer is completely removed.

[0058] In a third aspect of the present invention, there is provided a semiconductor die assembly including a substrate processed by the method of the first aspect or the second aspect and a plurality of semiconductor dies, and the plurality of semiconductor dies include at least two different types of dies bonded to the substrate.

[0059] In a fourth aspect of the present invention, there is provided a semiconductor die assembly including a substrate processed by the method of the first aspect or the second aspect and a plurality of semiconductor dies, and each of the plurality of semiconductor dies has a thickness of less than 15 μm.

[0060] In a fifth aspect of the present invention, there is provided a plasma etching apparatus configured to perform the method according to the first aspect or the second aspect. The plasma etching apparatus includes a chamber. The plasma etching apparatus further includes a plasma generator associated with the chamber and configured to generate plasma from at least one gas accommodated in the chamber. The plasma etching apparatus further includes a substrate support configured to support a substrate assembly including a substrate and a plurality of semiconductor dies spaced apart from the substrate, and the substrate support is disposed with respect to the chamber such that plasma contacts the substrate assembly during use. The plasma etching apparatus further includes a control device configured to cause the apparatus to perform plasma deposition to cover the substrate assembly with a film layer, then perform plasma etching to partially remove the film layer so that the upper surfaces of the semiconductor dies are exposed, then perform plasma etching to thin the plurality of semiconductor dies, and then perform plasma ashing to completely remove the film layer.

Brief Description of the Drawings

[0061] Embodiments of the present invention will be described below by way of example only with reference to the accompanying schematic diagrams.

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

DETAILED DESCRIPTION OF THE INVENTION

[0062] In an exemplary embodiment of the present invention, a semiconductor die assembly 1 is provided that includes two semiconductor dies 3, 5 arranged side - by - side and bonded to a substrate 7 (FIG. 1). For purposes of illustration, assembly 1 includes two dies, but in other embodiments, there may be a plurality of dies, for example, more than 50 or more than 100 dies, bonded to the substrate. The dies are arranged on the substrate 7 with a gap 6 between the dies such that a portion 8 (the "exposed portion 8") of the upper surface 10 of the substrate 7 is exposed. In embodiments where there are more than two dies, the dies may be arranged uniformly across the substrate. In this embodiment, the substrate 7 is not supported. In an alternative embodiment, the substrate 7 may be supported on a support structure such as a film on a frame or a base wafer.

[0063] In an exemplary embodiment, the substrate 7 comprises a 300 mm wafer. In an alternative embodiment, the substrate may alternatively comprise a tape (i.e., the die is present on the tape). In an exemplary embodiment, the die is square when viewed in plan view and has four sides 23. Each die 3, 5 comprises a semiconductor layer 9 formed from silicon in an exemplary embodiment, above the dielectric layer 11. The dielectric layer 11 of each die 3, 5 is in contact with the interface layer 13 on the wafer 7. In an exemplary embodiment of the present invention, the dielectric layer 11 of each die has a lower dielectric surface 15 including a bonding pad opening (not shown) for hybrid bonding the die 3, 5 to the upper interface surface 17 of the interface layer 13 of the wafer 7.

[0064] The dies 3, 5 of the semiconductor die assembly 1 are mounted on the wafer 7 according to a die-to-wafer bonding process using a pick-and-place robot (not shown). Each of the dies 3, 5 has a thickness t of about 40 μm between the upper surface 12 of the die and the upper interface surface 17 of the interface layer 13 of the wafer 7. The pick-and-place process and machine are known in the art and will not be described in detail herein. A die thickness of about 30 μm or more is required for accurate placement by the pick-and-place robot. However, for practical reasons, such as to enable integration into various end products with different spatial constraints and for economic reasons, a significantly thinner thickness is desired in many applications. Depending on the intended end use, a minor or significant thickness reduction may be required.

[0065] To thin the dies 3, 5, a method of thinning the dies is carried out as described herein.

[0066] In an initial step 103, dies 3, 5 and wafer 7 are covered with a film layer 19 (FIG. 2). The film layer provides a passivation layer, i.e., a protective layer covering the surfaces of each silicon die 3, 5. In an exemplary embodiment, the film layer 19 includes a polymer formed from fluorine and carbon, although other passivation materials such as other polymer materials may be suitable as alternatives. In an exemplary embodiment, the film layer 19 is deposited by plasma deposition using an inductively coupled plasma (ICP) etching apparatus known in the art. Another etching apparatus such as a PECVD chamber or an RIE chamber may be suitable as an alternative. (As will be described in more detail below) the apparatus generates plasma from a carbon fluoride gas such as C4F8. Plasma deposition is performed in the secondary / principal chamber of the apparatus at a relatively high pressure of about 80 - 120 mTorr over a period of about 40 seconds to 80 seconds (the apparatus is described in more detail below). The apparatus of the exemplary embodiment receives two C4F8 gas streams (i.e., a primary and a secondary gas stream) in the chamber via two separate inlets. The gas is supplied at a flow rate of about 100 sccm to 300 sccm. In an alternative embodiment, one chamber of a similar apparatus may be supplied using one gas source. In an exemplary embodiment, two plasma generators in the form of ICP sources generate two plasmas from two respective gas supplies (which will mix later) by electromagnetic induction at an ICP power of about 500 W to 2000 W.

[0067] As will be described in more detail below with reference to FIG. 7, an AC voltage of 13.56 MHz (i.e., high-frequency "RF bias power") is applied to the support component of the semiconductor die assembly 1. In the positive cycle, electrons are attracted to the support component, and in the negative cycle, cations are attracted to the support component. Since electrons move faster, a negative DC potential is generated in the support component. This generates a charge bias (i.e., charge difference / potential difference) between the semiconductor die assembly 1 and the plasma. Next, the negative DC potential attracts cations to the semiconductor die assembly 1 on the support component, which are deposited as a polymer layer 19 containing carbon and fluorine. The use of a relatively high pressure results in scattering that helps to make the deposition more uniform.

[0068] The charge difference can be controlled by applying RF bias power to the support component, which in turn controls the rate of polymer deposition. An RF bias power of about 450 W to 550 W has been found to be suitable for polymer deposition.

[0069] The polymer layer 19 is deposited to a thickness of about 1 μm (not shown to scale) and is added as a substantially uniform layer, i.e., having a substantially constant thickness across the semiconductor die assembly 1. The high-pressure deposition step is isotropic, and positively charged plasma ions flow towards all outer surfaces of the semiconductor die assembly 1 as part of the plasma flow in the chamber. The polymer layer 19 is deposited in a single addition. A thickness between 0.5 μm and 1.5 μm has been found to be optimal to provide a film layer thick enough to successfully passivate the sides of the semiconductor layer during plasma etching while being thin enough so that the film layer can be added in a single addition.

[0070] The polymer layer 19 completely covers each die and further completely covers the exposed portion 8 of the upper surface 10 of the substrate 7. Thus, the polymer layer provides a continuous passivation layer covering the die assembly. In embodiments where there are a plurality of dies bonded to the substrate, the exposed portion may include some smaller exposed portions of the upper surface of the substrate between and around the dies.

[0071] In an exemplary embodiment, the polymer layer 19 extends across the entire upper surface 12 of each die and along each side surface 23 of each die 3, 5. The thickness of the polymer layer 19 across the upper surface 12 of the dies 3, 5 is substantially the same as the thickness of the polymer layer 19 along the side surfaces 23 of the dies 3, 5 and is substantially the same as the thickness of the polymer layer 19 across the exposed portion 8 of the upper surface 10 of the substrate 7. In an alternative embodiment, the thickness of the polymer layer 19 along the side surfaces 23 may be slightly thinner than the thickness of the polymer layer 19 across the upper surface 12 of the dies 3, 5 and / or across the exposed portion 8 of the upper surface 10 of the substrate 7. Nevertheless, as long as the polymer layer provides a continuous barrier (i.e., does not include gaps), a passivation effect is still provided.

[0072] In a subsequent step, while keeping the polymer layer 19 intact on the side surface 23 of the die, the polymer layer 19 is removed from the upper surfaces 12 of each of the dies 3, 5 and the exposed portion 8 between the dies 3, 5 (FIG. 3). Thus, while the side surfaces of the dies remain passivated, the upper surfaces 12 of the dies are exposed. In an exemplary embodiment, the polymer layer 19 is removed by plasma etching using the same plasma etching apparatus. The apparatus generates plasma from SF6 gas (as will be described in more detail below). The polymer plasma etching is carried out in the chamber of the apparatus at a relatively low pressure of about 5 mTorr to 20 mTorr for a period of about 120 seconds to 160 seconds. A binary input SF6 gas flow (i.e., a primary and a secondary gas flow) is supplied into the chamber at a low flow rate of about 150 sccm to 250 sccm. The binary ICP plasma source generates two plasmas that will mix later by electromagnetic induction with an ICP power of about 500 W to 2000 W. An RF bias power of about 250 W to 350 W has been found to be suitable for polymer etching.

[0073] In an exemplary embodiment, the etching of the polymer from the die upper surfaces 12 and the exposed portion 8 between the dies 3, 5 is simultaneous, and the etching is directional along a vertical axis, i.e., an axis orthogonal to the horizontal plane at the center of the substrate 7. Since the etching is directional / anisotropic, the polymer on the side surfaces 23 of the dies is not affected and remains in place. The directionality is achieved by using SF6 gas at a low pressure with RF bias power during etching. In contrast, the deposition of the film uses C4F8 gas at a high pressure with RF bias power.

[0074] The removal of the polymer layer from the die upper surface is monitored spectroscopically, and the spectral line at 300 nm continues to decrease suddenly and rapidly until it flattens out, indicating (by prediction that the horizontal upper surface of the die has had the polymer removed and thus the layer has been removed from the exposed portion 8).

[0075] In a subsequent step, the upper surfaces 12 of the silicon dies 3, 5 are plasma etched to thin the dies (Figure 4). In an exemplary embodiment, the dies are thinned by plasma etching using the same plasma etching apparatus as that used for polymer deposition and polymer etching (although in principle the polymer layer can be deposited in a separate tool after dicing). Similar to the polymer etching of the die upper surface, the apparatus chamber is fed with SF6 gas in a binary manner. The etching rate of the Si die is faster than that of the polymer layer, which means that the die can be thinned while the polymer layer remains intact on the sidewalls of the die. The Si etching step uses a larger SF6 flow rate, on the order of about 500 sccm to 1000 sccm, and a slightly higher pressure to increase the etching rate.

[0076] In an exemplary embodiment of the present invention, there are buried features in the form of through-silicon vias (TSVs - not shown in the figure) within the semiconductor layer 9 of the die. The TSVs comprise Cu pillars covered by a dielectric layer of SiO2. The Si plasma etching is carried out to circulate (to enhance the selectivity of SiO2) at a low to medium pressure of about 20 mTorr to 40 mTorr. The etching is carried out through an alternating sequence where the RF bias power is applied for 1 second and then not applied for 2 seconds (i.e., the RF bias power is turned off). The process continues until the target silicon thickness t’ is achieved and the etching ends on a smooth Si surface (however, alternatively, the etching can end when the TSVs are exposed). During the etching, the film layer 19 remaining on the side surfaces 23 of the dies 3, 5 protects the sides of the dies 3, 5 from unwanted etching. Thus, thanks to the protective passivation layer, the plasma etching of silicon is anisotropic. In other words, the etching is directional in the vertical direction. The thickness reduction achieved can vary depending on the requirements, from a reduction of a few micrometers to a reduction of tens or hundreds of micrometers. In an alternative embodiment without TSVs and other buried features, since the selectivity of SiO2 is not particularly a concern, the circulating etching process may be omitted by selecting a one-step process.

[0077] In a subsequent step, while keeping the thinned dies 3, 5 bonded to the wafer 7, the polymer layer 19 is removed from the side surfaces 23 of each die 3, 5 such that the polymer is completely removed from the semiconductor die assembly 1 (FIG. 5). In an exemplary embodiment, the polymer layer 19 is removed from the side surfaces 23 by plasma ashing using the same plasma etching apparatus. (As will be described in more detail below) the apparatus generates a plasma from an oxygen-containing gas. The plasma ashing is performed in the chamber of the apparatus at a relatively low pressure of about 5 mTorr to 15 mTorr. A binary input oxygen-containing gas flow (i.e., a primary and a secondary gas flow) is supplied into the chamber at a flow rate of about 100 sccm to 400 sccm. The binary ICP plasma source generates a plasma that will later mix by electromagnetic induction at an ICP power of about 2 kW to 5 kW. A low RF bias power of about 0 W to 50 W has been found to be suitable for polymer ashing. Anisotropic ashing is performed and all remaining polymer is removed.

[0078] The final polymer strip is controlled by timing, but in another embodiment, it can be monitored using an optical endpoint signal.

[0079] In an exemplary embodiment, the semiconductor die assembly is maintained at a constant temperature, for example, about 1 °C to 10 °C for the deposition and etching steps and slightly higher but less than 50 °C for the ashing step (due to the higher ICP power).

[0080] The described method of thinning the die provides a smaller semiconductor die assembly and provides dies 3, 5 for packaging, for example, using advanced packaging techniques. In summary (FIG. 6), the method includes a first step 103 of providing a semiconductor die assembly and a second step 105 of adding a film to a substrate 7 to cover the semiconductor die and the exposed portion 8 with a film layer, the film layer spreading across the top surface of the die and along the side surfaces, the second step 105, a third step 107 of removing the film from the top surface of the die while leaving the film intact on the side surfaces of the die, a fourth step 109 of plasma etching the top surface of the die, and a fifth step 111 of removing the film from the side surfaces of the die. Thus, a processed die assembly is provided that includes dies thinned from an original thickness of the die, which is about 40 μm, to a height suitable for packaging for various end uses, for example, to less than half of the original height, for example, to less than a quarter of the original height.

[0081] The process can be adjusted as needed. In some situations, the film layer 19 on the side surfaces of the die can become partially collapsed during Si etching (FIG. 7). When the film layer collapses across the semiconductor layer 9, the semiconductor layer is partially obscured when viewed in plan view, and the Si etching rate decreases in the vicinity of the obscured region 25. As a result, the thickness of the Si adjacent to the film layer becomes thicker than the thickness of the open area of the die. To avoid this from occurring, the film deposition and the parameters of the semiconductor layer and film etching can be changed. Alternatively, or additionally, the method can include, as an intermediate step, a further step of removing the film layer and redepositing it.

[0082] In an exemplary embodiment, all method steps are performed using a plasma etching apparatus 301, such as Rapier XE (trademark) (FIG. 8). In an alternative embodiment, the method steps can be performed using separate modules in a cluster tool or using a series of separate tools or other apparatuses.

[0083] The plasma etching apparatus 301 includes a first chamber 303 located above a second, larger chamber 305. A first plasma generator 308 in the form of a cylindrical ICP source 309 connected to a first RF (13.56 MHz) power supply 311 is disposed at the peripheral portion of the first chamber and configured to generate a variable magnetic field to induce an electric field to excite electrons in the gas within the first chamber. A first gas inlet 307 supplies a first process gas into the first chamber 303, and after primary plasma is generated by electromagnetic induction, ion generation continues.

[0084] A DC coil 313 is used to control the shape of the plasma exiting the first chamber 303. A Faraday shield 315 reduces capacitive coupling from the ICP source, i.e., makes the ICP source primarily inductive.

[0085] The plasma flows into the second chamber 305, where the plasma contacts the semiconductor die assembly 1 supported by an electrostatic chuck 317. The semiconductor die assembly 1 is supported on a tape 321 held by a frame 323. In an exemplary embodiment, the edges of the semiconductor die assembly 1 are protected by a wafer edge protection (WEP) device 319. A baffle 325 above the electrostatic chuck 317 is configured to control the gas flow in the vicinity of the semiconductor die assembly.

[0086] The second gas inlet 327 is arranged in an annular configuration at the upper part of the second chamber 305 and is configured to supply a second processing gas into the second chamber. A second plasma generator 329 connected to a second RF (13.56 MHz) power supply 331 provides a second cylindrical ICP source. The coaxial source helps to increase the etching rate towards the edge of the semiconductor die assembly. The second plasma generator 329 is arranged at the peripheral part of the second chamber and is configured to generate a secondary plasma from the second processing gas at the peripheral part 305 of the second chamber. The two plasmas mix within the chamber to provide a more uniformly distributed plasma across the semiconductor die assembly. The gas flow through the chamber is assisted by a pump 333 and a valve 335. An independent power supply 337 (similarly 13.56 MHz, but frequencies from 2 MHz to 20 MHz can be used) provides RF bias power to the electrodes associated with the semiconductor die assembly, i.e., the support.

Claims

1. 1. A method of packaging a semiconductor die, comprising: providing a substrate and a plurality of semiconductor dies spaced apart on the substrate, with an exposed surface of the substrate between the dies; applying a film to the substrate to cover the plurality of semiconductor dies and the exposed surface of the substrate with a film layer, each die having a top surface and at least one side surface, the film layer extending across the top surfaces and along the side surfaces of the die; removing the film from the top side of the die while leaving the film intact on the side of the die; plasma etching the top surface of the die; removing the film from the side of the die; The method according to claim 1, further comprising:

2. The method of claim 1 , wherein the membrane comprises a polymer.

3. 3. The method of claim 1 or 2, wherein the semiconductor die comprises an unmasked silicon die.

4. 4. The method of any one of claims 1 to 3, wherein the film is applied by plasma enhanced chemical vapor deposition.

5. 5. The method of claim 1, wherein the film is applied using a plasma formed from a fluorocarbon gas.

6. 6. The method according to any one of claims 1 to 5, characterized in that the film is applied at least vertically and laterally to a central horizontal plane of the substrate.

7. 7. The method of claim 1, further comprising removing the film from the exposed surface of the substrate simultaneously with the step of removing the film from the top surface of the die.

8. 8. The method of claim 1, wherein the membrane is removed from the top surface of the die by anisotropic plasma etching.

9. 9. The method according to claim 1, wherein the membrane is made of SF ６ the top surface of the die is removed using a plasma formed from a gas.

10. 10. The method of claim 1, wherein the film is removed from the side of the die by isotropic plasma ashing.

11. 11. The method of any one of claims 1 to 10, wherein the film is removed from the side of the die using an oxygen-based ashing chemistry.

12. 12. The method of any one of claims 1 to 11, wherein the membrane layer is applied over substantially the entire substrate.

13. 13. The method of any one of claims 1 to 12, wherein the membrane layer extends along all said sides of the die.

14. 14. The method according to any one of claims 1 to 13, characterized in that the membrane layer has a maximum thickness of less than 5 μm.

15. 15. The method of any one of claims 1 to 14, wherein the membrane layer has a substantially constant average thickness with a maximum thickness variation from the average thickness of less than 20%.

16. 16. The method of any one of claims 1 to 15, wherein the film is applied to the substrate in a single deposition step.

17. 17. The method according to any one of claims 1 to 16, comprising: the intermediate steps of removing the film to completely remove the film layer and re-applying the film to the substrate to cover the plurality of semiconductor dies and the exposed surface of the substrate with a replacement film layer.

18. 18. The method of any one of claims 1 to 17, wherein the top surface of the die is etched until a thickness of each die between the exposed surface of the substrate and the top surface of the die is less than a user-defined threshold thickness.

19. 20. The method of claim 18, wherein the threshold thickness is 20 μm.

20. 20. The method of claim 18, wherein the threshold thickness is 10 μm.

21. 21. The method of any one of claims 1 to 20, wherein the plurality of semiconductor dies comprises at least one die of a first type and at least one die of a second type, the method comprising a preceding step of bonding at least one die of the first type to the substrate to provide the plurality of semiconductor dies spaced apart on the substrate, the at least one die of the second type being pre-bonded to the substrate.

22. 22. The method of any one of claims 1 to 21, wherein the substrate comprises a semiconductor material.

23. 23. The method of any one of claims 1 to 22, wherein the substrate comprises a dielectric material.

24. 24. The method of any one of claims 1 to 23, wherein the substrate is a tape or is supported on a tape.

25. 25. The method of any one of claims 1 to 24, further comprising the subsequent step of applying a packaging material to the substrate to embed the substrate and the die. A method comprising:

26. 26. The method of any one of claims 1 to 25, wherein the plurality of semiconductor dies are provided in an upper layer of a plurality of vertical stacks of dies.

27. 27. The method of claim 1, wherein the semiconductor dies are arranged in a horizontal stack of dies, and the film layer extends across the top surfaces of the dies and along the outwardly facing side surfaces of the dies.

28. 1. A method of thinning a semiconductor die, comprising: applying a continuous film layer over a plurality of unmasked dies supported on a substrate to cover a top surface and each side surface of the dies; plasma etching the membrane layer to expose the top surface of each die of the plurality of unmasked dies while the membrane layer remains covering the side surfaces; plasma etching the exposed top surface of the die; plasma ashing the film layer remaining on the side of the die such that the film layer is completely removed; The method according to claim 1, further comprising:

29. 30. The method of claim 28, wherein the unmasked dies are provided in an upper layer of a plurality of vertical stacks of dies, with two or more dies in each stack, and wherein the continuous film layer covers the top surfaces of the unmasked dies in the upper layer and the side surfaces of each die in each stack.

30. 30. The method of claim 29, transferring a further unmasked die to each of said stacks to form a new plurality of unmasked dies included in a new upper layer; next, adding a new continuous film layer over the new plurality of unmasked dies, the new continuous film layer covering the top surfaces of the dies in the new upper layer and the side surfaces of each of the dies in each of the stacks; plasma etching the new film layer to expose the top surface of each of the dies in the new upper layer while the new film layer remains covering the side surfaces; plasma etching the exposed top surface of the die; plasma ashing the new film layer remaining on the side of the die such that the new film layer is completely removed; The method further comprising:

31. 31. A semiconductor die assembly processed by the method of any one of claims 1 to 30, comprising a substrate and a plurality of semiconductor dies, the plurality of semiconductor dies comprising at least two different types of dies bonded to the substrate.

32. 31. A semiconductor die assembly comprising a substrate and a plurality of semiconductor dies processed by the method of any one of claims 1 to 30, wherein each of the plurality of semiconductor dies has a thickness of less than 15 μm.

33. 31. A plasma etching apparatus configured to carry out the method of any one of claims 1 to 30, the plasma etching apparatus comprising: A chamber; a plasma generator associated with the chamber and configured to generate a plasma from at least one gas contained in the chamber; a substrate support configured to support a substrate assembly comprising a substrate and a plurality of semiconductor dies spaced apart from the substrate, the substrate support being positioned relative to the chamber such that, in use, the plasma contacts the substrate assembly; a controller configured to cause the apparatus to perform plasma deposition to cover the substrate assembly with a film layer, then perform plasma etching to partially remove the film layer so that top surfaces of the semiconductor dies are exposed, then perform plasma etching to reduce a thickness of the semiconductor dies, and then perform plasma ashing to completely remove the film layer; A plasma etching apparatus comprising:

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