Pixel, method of driving pixel, and display device including pixel

Abstract

To provide a pixel in which the number of switching transistors is reduced, a method of driving the pixel, and a display device including the pixel.SOLUTION: A pixel comprises: a driving transistor DR that has a gate electrode at a first node N1, a first electrode connected to a high potential driving voltage VDD, and a second electrode connected to a light-emitting element LD, and controls an amount of driving current to the light-emitting element LD; a first transistor T1 that transmits reference voltage Vref to the gate electrode of the driving transistor DR in response to a first gate signal SCAN1; a second transistor T2 that transmits data voltage Vdata to the gate electrode of the driving transistor DR in response to a second gate signal SCAN2; a third transistor T3 that electrically connects the gate electrode of the driving transistor DR to the second electrode of the driving transistor DR in response to the first gate signal SCAN1; and a fourth transistor T4 that electrically connects the driving transistor DR with the light-emitting element LD in response to a light-emitting signal EM.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a pixel, a method for driving the pixel, and a display device including the pixel.

Background Art

[0002] Recently, in a display device, in order to reduce power consumption when the change in an input video is small, a technique for driving a pixel at a low speed has been developed.

[0003] When a display panel is driven at a low speed for a long time, during a skip period, the voltage of a specific node in a gate driving unit may increase due to current leakage, noise, etc. Such an increase in the node voltage may reduce the driving force of the gate driving unit and cause image quality degradation.

Summary of the Invention

Problems to be Solved by the Invention

[0004] An embodiment aims to provide a pixel in which the number of switching transistors connected to a driving transistor is reduced, a method for driving the pixel, and a display device including the pixel.

[0005] Also, an object of the present invention is to provide a pixel in which the number of light emission signals required for driving the pixel is reduced by removing a switching transistor, a method for driving the pixel, and a display device including the pixel.

Means for Solving the Problems

[0006] A pixel according to an embodiment includes a light-emitting element, a first electrode connected to a high-potential drive voltage, a second electrode connected to the light-emitting element, a drive transistor that controls a drive current amount supplied to the light-emitting element in response to a voltage of a gate electrode, a first transistor that transmits a reference voltage to the gate electrode of the drive transistor in response to a first gate signal, a second transistor that transmits a data voltage to the gate electrode of the drive transistor in response to a second gate signal, a third transistor that connects the gate electrode of the drive transistor and the second electrode in response to the first gate signal, and a fourth transistor that connects the drive transistor and the light-emitting element in response to a light-emitting signal.

[0007] The first transistor is connected between the reference voltage and a first node, and its gate electrode receives the first gate signal. The second transistor is connected to a data line and a third node, and its gate electrode receives the second gate signal. The third transistor is connected between the third node and a second node, and its gate electrode receives the first gate signal. The fourth transistor is connected between the third node and the light-emitting element, and its gate electrode receives the light-emitting signal. The gate electrode of the drive transistor may be connected to the first node, and the second electrode may be connected to the second node.

[0008] The pixel may further include a first capacitor connected between the first node and the third node.

[0009] The pixel may further include a second capacitor connected between the third node and a fourth node, a fifth transistor connected between the fourth node and a base voltage and having a gate electrode that receives a third gate signal, and a sixth transistor connected between the fourth node and the light-emitting element and having a gate electrode that receives the light-emitting signal.

[0010] When the second transistor is switched to the on state, the data voltage is transmitted to the gate electrode of the driving transistor via the first capacitor, thereby preventing voltage loss due to the switching of the second transistor.

[0011] When the second transistor is turned on or when the light-emitting element emits light, the third transistor is turned off, and by separating the second node and the third node, the influence of mutual voltage fluctuations between the second node and the third node can be prevented.

[0012] During the initialization period of one frame, the first gate signal, the light-emitting signal, and the third gate signal are applied at the on level, so that the first node is initialized to the reference voltage via the first transistor, and the second node, the third node, and the fourth node may be initialized to the base voltage via the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor.

[0013] During the sensing period of one frame, the first gate signal and the third gate signal are applied at the on level, so that the gate electrode of the driving transistor and the second electrode are connected by the third transistor, and the differential voltage between the reference voltage and the threshold voltage of the driving transistor may be stored in the second capacitor.

[0014] During the programming period of one frame, the second gate signal and the third gate signal are applied at the on level, so that the third node is set to the data voltage by the second transistor, the fourth node is set to the base voltage by the fifth transistor, the data voltage is stored in the second capacitor, and the sum voltage of the data voltage and the threshold voltage of the driving transistor is stored in the first capacitor.

[0015] During the light emission period of one frame, when the light emission signal is applied at the turn-on level, a drive current may be applied to the light emitting element via the fourth transistor, and the light emitting element may emit light corresponding to the drive current.

[0016] A method for driving a pixel according to an embodiment may include an initialization step of applying the first gate signal and the light emission signal at the turn-on level, a sensing step of applying the first gate signal at the turn-on level after the initialization step, a programming step of applying the second gate signal at the turn-on level after the sensing step, and a light emission step of applying the light emission signal at the turn-on level after the programming step.

[0017] In the initialization step and the programming step, the third gate signal may be further applied at the turn-on level.

[0018] During the programming period, the data voltage applied to the data line is transmitted to the gate electrode of the drive transistor via the first capacitor, thereby preventing voltage loss due to the switching of the second transistor.

[0019] During the programming period and the light emission period, the third transistor may be turned off to separate the second node and the third node, thereby preventing the influence of mutual voltage fluctuations between the second node and the third node.

[0020] A display device according to an embodiment may include a display panel on which pixels are arranged, a gate driving unit that applies first to third gate signals to the pixels, a light emission driving unit that applies a light emission signal to the pixels, a data driving unit that applies a data voltage to the pixels, and a timing control unit that controls the operation timings of the gate driving unit, the light emission driving unit, and the data driving unit.

[0021] The pixel, pixel driving method, and display device including the pixel according to the embodiment can reduce the voltage loss of the gate node of the driving transistor due to switching by minimizing the number of switching transistors connected to the driving transistor.

[0022] Also, the pixel, pixel driving method, and display device including the pixel according to the embodiment can reduce the wiring of the driving unit and achieve a narrow bezel by minimizing the number of light emission signals required for pixel driving.

[0023] Also, the pixel, pixel driving method, and display device including the pixel according to the embodiment enable stable image output without luminance change by preventing voltage fluctuation of the driving transistor during pixel light emission.

Brief Description of the Drawings

[0024]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Mode for Carrying Out the Invention

[0025] Hereinafter, embodiments will be described with reference to the drawings. In this specification, when a certain component (or region, layer, part, etc.) is referred to as being "on", "connected to", or "coupled to" another component, it means that it may be directly connected / coupled to the other component, or a third component may be disposed therebetween.

[0026] The same reference numerals refer to the same components. Also, in the drawings, the thickness, ratio, and dimensions of the components are exaggerated for the purpose of an effective explanation of the technical content. "And / or" includes all combinations of one or more of the associated components that can define the relationship.

[0027] Terms such as first and second can be used to describe various components, but the above components are not limited by the above terms. The above terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the rights of this embodiment, the first component may be called the second component, and similarly the second component may be called the first component. Singular expressions include plural expressions unless otherwise clearly specified in the context.

[0028] Terms such as "below", "beneath", "above", "on top" are used to explain the association relationship of the structures shown in the drawings. The above terms are relative concepts and are explained based on the directions shown in the drawings.

[0029] Terms such as "comprising" or "having" are intended to specify that there are the features, numbers, steps, operations, components, parts, or combinations thereof described in the specification, and should be understood not to preclude the possibility of the existence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0030] FIG. 1 is a block diagram schematically showing the structure of a display device according to an embodiment.

[0031] Referring to FIG. 1, the display device 1 includes a timing control unit 10, a gate driving unit 20, a data driving unit 30, a light emission driving unit 40, a power supply unit 50, and a display panel 60.

[0032] The timing control unit 10 (for example, a timing controller circuit) can receive a video signal RGB and a control signal CS from an external host system or the like. The video signal RGB may include a plurality of gradation data. The control signal CS may include, for example, a horizontal synchronization signal, a vertical synchronization signal, and a main clock signal.

[0033] The timing control unit 10 processes the video signal RGB and the control signal CS to conform to the operating conditions of the display panel 60, and can generate and output video data DATA, a gate driving control signal CONT1, a data driving control signal CONT2, a light emission driving control signal CONT3, and a power supply control signal CONT4. Such a timing control unit 10 can control the operating timings of the gate driving unit 20, the data driving unit 30, and the light emission driving unit 40 by control signals.

[0034] The gate driving unit 20 (for example, a gate driver circuit) can generate a gate signal based on the gate driving control signal CONT1 output from the timing control unit 10. The gate driving unit 20 can provide the generated gate signal to the pixels PX via a plurality of gate lines GL. In one embodiment, the gate driving unit 20 can generate one or more gate signals having turn-on levels at different timings.

[0035] The data driving unit 30 (for example, a data driver circuit) can generate a data signal based on the video data DATA and the data driving control signal CONT2 output from the timing control unit 10. The data driving unit 30 can provide the generated data signal to the pixels PX via a plurality of data lines DL.

[0036] The light emission driving unit 40 (for example, a light emission driver circuit) can generate a light emission control signal based on the light emission driving control signal CONT3 output from the timing control unit 10. The light emission driving unit 40 can provide the generated gate signal to the pixel PX via a plurality of light emission lines EL.

[0037] The power supply unit 50 (for example, a power supply circuit) can generate a high potential driving voltage VDD and a low potential driving voltage VSS provided to the display panel 60 based on the power supply control signal CONT4. The power supply unit 50 can provide the generated driving voltages VDD and VSS to the pixel PX via the corresponding power supply lines PL1 and PL2.

[0038] A plurality of pixels PX (also called sub-pixels) are arranged on the display panel 60. The pixel PX may include one or more transistors and a light emitting element connected to the gate line GL and the data line DL. The pixel PX can charge the data voltage supplied via the data line DL in response to the gate signal applied via the gate line GL, and can emit light with a luminance corresponding to the charged data voltage in response to the light emission control signal applied via the light emission line EL.

[0039] In one embodiment, each pixel PX can display any one of red, green, and blue colors. In other embodiments, each pixel PX can display any one of cyan, magenta, and yellow colors. In various embodiments, each pixel PX can also display any one of red, green, blue, and white colors.

[0040] The timing control unit 10, the gate driving unit 20, the data driving unit 30, the light emitting driving unit 40, and the power supply unit 50 may each be constituted by a separate integrated circuit (IC), or may be constituted by an integrated circuit in which at least a part is integrated. Further, the gate driving unit 20 and the light emitting driving unit 40 may be configured in an in-panel method that is formed integrally with the display panel 60. In such an embodiment, the gate driving unit 20 and the light emitting driving unit 40 can constitute a gate in-panel unit (hereinafter, GIP).

[0041] FIG. 2 is a circuit diagram of a pixel according to an embodiment.

[0042] Referring to FIG. 2, a pixel PX according to an embodiment may include a driving transistor DR, a light emitting element LD connected to the driving transistor DR, and a control circuit for controlling the amount of driving current applied to the light emitting element LD via the driving transistor DR. For example, the control circuit may include first to sixth transistors T1 to T6 and first and second capacitors C1, C2.

[0043] The first electrode (for example, drain electrode) of the driving transistor DR is configured to receive a high potential driving voltage VDD via a high potential driving power line PL1 connected to the first electrode, and the second electrode (for example, source electrode) is electrically connected to the light emitting element LD at the second node N2. The gate electrode of the driving transistor DR is connected to the first node N1. The driving transistor DR can be turned on according to the voltage applied to the first node N1, and can control the amount of driving current flowing through the light emitting element LD.

[0044] The first electrode (e.g., drain electrode) of the first transistor T1 is configured to receive a reference voltage Vref from a reference voltage line, and the second electrode (e.g., source electrode) is connected to the gate electrode of the driving transistor DR of the first node N1. The gate electrode of the first transistor T1 is connected to the first gate line GL1 and can receive a first gate signal SCAN1 from the first gate line GL1. The first transistor T1 turns on in response to the first gate signal SCAN1 applied to the first gate line GL1 and can transmit the reference voltage Vref to the gate electrode of the driving transistor DR of the first node N1. The first transistor T1 may be referred to as the "first switching transistor".

[0045] The first electrode (e.g., drain electrode) of the second transistor T2 is connected to the data line DL, and the second electrode (e.g., source electrode) of the second transistor T2 is electrically connected to the gate electrode of the driving transistor DR at the third node N3. The gate electrode of the second transistor T2 is connected to the second gate line GL2 and receives a second gate signal SCAN2 from the second gate line GL2. The second transistor T2 turns on in response to the second gate signal SCAN2 applied to the second gate line GL2 and transmits the data voltage Vdata applied to the data line DL to the gate electrode of the driving transistor DR. The second transistor T2 may be referred to as the "second switching transistor".

[0046] The first capacitor C1 may be connected between the second electrode of the second transistor T2 of the third node N3 and the gate electrode of the driving transistor DR of the first node N1. That is, the first capacitor electrode of the first capacitor C1 is connected to the first node N1, and the second capacitor electrode of the first capacitor C1 is connected to the third node N3. The first capacitor C1 may store a voltage corresponding to the voltage difference between the first node N1 and the third node N3.

[0047] The third transistor T3 is connected between the second node N2 and the third node N3. The first electrode (e.g., drain electrode) of the third transistor T3 is connected to the second electrode of the second transistor T2 and the second electrode of the first capacitor C1 at the third node N3, and the second electrode (e.g., source electrode) of the third transistor T3 is connected to the second electrode of the driving transistor DR at the second node N2. The gate electrode of the third transistor T3 is connected to the first gate line GL1 and receives the first gate signal SCAN1 from the first gate line GL1. The third transistor T3 turns on in response to the first gate signal SCAN1 applied to the first gate line GL1, and can electrically connect the gate electrode (third node N3) and the second electrode (second node N2) of the driving transistor DR. The third transistor T3 may be called the "third switching transistor".

[0048] The first electrode (e.g., drain electrode) of the fourth transistor T4 is connected to the second electrodes of the driving transistor DR and the third transistor T3 at the second node N2, and the second electrode (e.g., source electrode) of the fourth transistor T4 is connected to the anode electrode of the light-emitting element LD. The gate electrode of the fourth transistor T4 is connected to the emission line EL and can receive the emission signal EM. The fourth transistor T4 turns on in response to the emission signal EM applied to the emission line EL, and can electrically connect the driving transistor DR and the light-emitting element LD (fourth node N4). The fourth transistor T4 may be called the "emission transistor".

[0049] The first electrode (e.g., drain electrode) of the fifth transistor T5 is connected to the fourth node N4, and the second electrode (e.g., source electrode) of the fifth transistor T5 is connected to a power supply line that supplies the base voltage GND. The gate electrode of the fifth transistor T5 is connected to the third gate line GL3 and receives a third gate signal SCAN3 via the third gate line GL3. The fifth transistor T5 turns on in response to the third gate signal SCAN3 applied to the third gate line GL3 and can connect the fourth node N4 to the base voltage GND. The fifth transistor is also called the "fourth switching transistor".

[0050] The second capacitor C2 may be connected between the first electrode of the fifth transistor T5 and the fourth node N4. That is, the second capacitor C2 includes a first capacitor electrode connected to the second electrode of the second transistor T2 and the first electrode of the third transistor T3 at the third node N3, and a second capacitor electrode connected to the first electrode of the fifth transistor T5 at the fourth node N4. The second capacitor C2 may store a voltage corresponding to the voltage difference between the third node N3 and the fourth node N4.

[0051] The first electrode (e.g., drain electrode) of the sixth transistor T6 is connected to the second electrode of the second capacitor C2 and the first electrode of the fifth transistor T5 at the fourth node N4, and the second electrode of the sixth transistor T6 is connected to the anode electrode of the light-emitting element LD and the second electrode of the fourth transistor T4. The gate electrode of the sixth transistor T6 is connected to the emission line EL and receives an emission signal EM. The sixth transistor T6 turns on in response to the emission signal EM applied to the emission line EL and connects the fourth node N4 and the anode electrode of the light-emitting element LD. The sixth transistor T6 is also called the "fifth switching transistor".

[0052] The anode electrode of the light-emitting element LD is connected to the fourth transistor T4, and the cathode electrode is connected to the low-potential driving voltage VSS. When the driving transistor DR and the fourth transistor T4 are turned on, a current path is formed between the high-potential driving voltage VDD and the low-potential driving voltage VSS, and a driving current can flow through the light-emitting element LD. The light-emitting element LD can emit light with a luminance corresponding to the amount of the driving current applied.

[0053] In the embodiment shown in FIG. 2, the pixel PX may be composed of an oxide semiconductor thin-film transistor.

[0054] The oxide semiconductor thin-film transistor includes a gate electrode, a source electrode, and a drain electrode. The oxide semiconductor thin-film transistor includes an active layer formed of an oxide semiconductor. Here, the oxide semiconductor can be set as an amorphous or crystalline oxide semiconductor. The oxide semiconductor thin-film transistor may be composed of an N-type transistor. The oxide semiconductor thin-film transistor enables a low-temperature process and has a lower charge mobility than an LTPS thin-film transistor. Such an oxide semiconductor thin-film transistor has excellent off-current characteristics.

[0055] However, this embodiment is not limited thereto. In other embodiments, at least one of the transistors DR, T1 to T6 may be composed of an LTPS (Low Temperature Poly-Silicon) thin-film transistor.

[0056] The LTPS thin-film transistor includes a gate electrode, a source electrode, and a drain electrode. The LTPS thin-film transistor includes an active layer formed of polysilicon. Such an LTPS thin-film transistor may be composed of a P-type thin-film transistor. The LTPS thin-film transistor has a high electron mobility and thus has high-speed driving characteristics.

[0057] FIG. 3 is a waveform diagram for explaining the signals applied to the pixels shown in FIG. 2, and the changes in the node voltage and driving current thereby. FIGS. 4 to 7 are diagrams for explaining the driving method of the pixels shown in FIG. 2.

[0058] Referring to FIG. 3, in a driving method according to an embodiment, one frame (1 Frame) may include an initialization period t1 (initialization step), a sensing period t2 (sensing step), a programming period t3 (programming step), and a light emitting period t4 (light emitting step).

[0059] During the initialization period t1, each node voltage of the pixel PX may be initialized to a predetermined voltage. Referring to FIGS. 3 and 4 together, during the initialization period t1, the first gate signal SCAN1, the third gate signal SCAN3, and the light emitting signal EM are applied at the turn-on level. Thereby, the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned on.

[0060] When the first transistor T1 is turned on, the reference voltage Vref is applied to the first node N1. Thereby, the voltage of the first node N1, that is, the gate electrode of the driving transistor DR, is initialized to the reference voltage Vref.

[0061] When the fourth to sixth transistors T4 to T6 are turned on, the base voltage GND is transmitted to the second node N2 through the fifth transistor T5, the sixth transistor T6, and the fourth transistor T4. Thereby, the voltages of the source electrode of the driving transistor DR and the anode electrode of the light emitting element LD are initialized to the base voltage GND.

[0062] When the third transistor T3 is turned on, the base voltage GND is further transmitted to the third node N3. As a result, a voltage corresponding to the voltage difference between the first node N1 and the third node N3, that is, the reference voltage Vref, is stored in the first capacitor C1, and a voltage corresponding to the voltage difference between the third node N3 and the fourth node N4, that is, 0V, is stored in the second capacitor C2.

[0063] On the other hand, the reference voltage Vref may be set to a voltage higher than the threshold voltage Vth of the driving transistor DR. The reference voltage Vref may be set to, for example, about 2V, but is not limited thereto. At this time, the gate-source voltage Vgs of the driving transistor DR is set to the reference voltage Vref higher than the threshold voltage Vth of the driving transistor DR, and the driving transistor DR can be turned on.

[0064] During the sensing period t2, the characteristic value of the driving transistor DR may be sensed. The characteristic value may be, for example, the threshold voltage Vth of the driving transistor DR.

[0065] Referring to FIGS. 3 and 5 together, during the sensing period t2, the first gate signal SCAN1 and the third gate signal SCAN3 are applied at the turn-on level. Thereby, the first transistor T1, the third transistor T3, and the fifth transistor T5 are turned on.

[0066] When the first transistor T1 is turned on, the voltage of the first node N1 is maintained at the reference voltage Vref, and when the fifth transistor T5 is turned on, the voltage of the fourth node N4 is maintained at the base voltage GND. Also, when the third transistor T3 is turned on, the second node N2 and the third node N3 are connected.

[0067] During the sensing period t2, current can flow through the drive transistor DR in the on state. The drain-source current of the drive transistor DR can be determined by the reference voltage Vref and the threshold voltage Vth of the drive transistor DR.

[0068] The drive transistor DR can supply the source-drain current to the second node N2 until the gate-source voltage Vgs reaches the threshold voltage (i.e., until "reference voltage Vref - voltage of the second node N2 = threshold voltage Vth" is satisfied). Also, the third transistor T3 can supply the voltage of the second node N2 to the third node N3.

[0069] In such a manner, while the drive transistor DR is turned on, the voltage of the second node N2 and the drain-source current of the drive transistor DR are gradually changed, and the voltage of the second node N2 and the voltage of the third node N3 can finally converge to the differential voltage between the reference voltage Vref and the threshold voltage Vth of the drive transistor DR.

[0070] The first capacitor C1 stores the voltage corresponding to the voltage difference between the first node N1 and the third node N3, that is, the threshold voltage Vth of the drive transistor DR, and the second capacitor C2 stores the voltage corresponding to the voltage difference between the third node N3 and the fourth node N4, that is, the differential voltage between the reference voltage Vref and the threshold voltage Vth of the drive transistor DR.

[0071] On the other hand, during the sensing period t2, the light emission signal EM is applied at the turn-off level, and the fourth transistor T4 and the sixth transistor T6 are turned off. Thereby, during the sensing operation, the light emitting element LD can be separated from the sensing circuit to prevent abnormal light emission of the light emitting element LD.

[0072] During the programming period t3, the data voltage Vdata may be programmed at the pixel PX. Referring to FIGS. 3 and 6 together, during the programming period t3, the second gate signal SCAN2 and the third gate signal SCAN3 are applied at the turn-on level. Thereby, the second transistor T2 and the fifth transistor T5 are turned on. On the other hand, during the programming period t3, the data voltage Vdata is applied to the data line DL.

[0073] When the second transistor T2 is turned on, the data voltage Vdata applied to the data line DL is transmitted to the third node N3. Also, when the fifth transistor T5 is turned on, the voltage of the fourth node N4 is maintained at the base voltage GND.

[0074] During the previous period, the threshold voltage Vth of the driving transistor DR is charged in the first capacitor C1, so that the voltage of the first node N1 during the programming period t3 is set to the sum voltage of the data voltage Vdata and the threshold voltage Vth of the driving transistor DR. The second capacitor C2 can store a voltage corresponding to the voltage difference between the third node N3 and the fourth node N4, that is, the data voltage Vdata.

[0075] During the programming period t3, the third transistor T3 is turned off, and the second node N2 and the third node N3 are separated, thereby preventing the influence of the mutual voltage fluctuation between the second node N2 and the third node N3. That is, the source electrode of the driving transistor DR is floated. Thereby, it is possible to prevent the voltage of the source electrode of the driving transistor DR from changing due to the data voltage Vdata applied to the third node N3, and to prevent the level of the data voltage Vdata applied to the third node N3 from changing due to the voltage of the source electrode of the driving transistor DR.

[0076] Further, the second transistor T2 is configured to transmit the data voltage Vdata to the gate electrode of the driving transistor DR via the first capacitor C1. That is, the gate electrode of the driving transistor DR is not directly connected to the second transistor T2, but is configured to be applied with the data voltage Vdata via the first capacitor C1. Therefore, it is possible to prevent a voltage loss that may occur at the gate electrode of the driving transistor DR due to the switching operation of the second transistor T2.

[0077] On the other hand, also during the programming period t3, the light emission signal EM is applied at the turn-off level, and the fourth transistor T4 and the sixth transistor T6 are turned off. Thereby, it is possible to prevent abnormal light emission of the light emitting element LD even if the voltage of the second node N2 changes during the programming period t3.

[0078] During the light emission period t4, the light emitting element LD can emit light corresponding to the data voltage Vdata charged during the programming period t3. Referring to FIGS. 3 and 7 together, during the light emission period t4, the light emission signal EM is applied at the turn-on level. Thereby, the fourth transistor T4 and the sixth transistor T6 are turned on.

[0079] When the fourth transistor T4 is turned on, a current path is formed from the high-potential drive voltage VDD to the light emitting element LD via the driving transistor DR. Thereby, a drive current Ioled corresponding to the gate-source voltage Vgs flows through the driving transistor DR.

[0080] Due to such a drive current Ioled, the potential of the anode electrode of the light emitting element LD rises to the operating point voltage Voled of the light emitting element LD, and the light emitting element LD can be turned on. The turned-on light emitting element LD can emit light with a luminance corresponding to the drive current Ioled.

[0081] While the light-emitting element LD is emitting light, the operating point voltage Voled of the light-emitting element LD may be applied to the fourth node N4 via the sixth transistor T6. During the previous period, by charging the data voltage Vdata to the second capacitor C2, the voltage of the third node N3 during the light-emitting period t4 is set to the sum voltage of the data voltage Vdata and the operating point voltage Voled of the light-emitting element LD. Also, during the previous period, by charging the threshold voltage Vth of the driving transistor DR to the first capacitor C1, the voltage of the first node N1 during the light-emitting period t4 is set to the sum voltage of the data voltage Vdata, the threshold voltage Vth of the driving transistor DR, and the operating point voltage Voled of the light-emitting element LD.

[0082] As a result, during the light-emitting period t4, the gate-source voltage Vgs of the driving transistor DR is "(data voltage Vdata + threshold voltage Vth + operating point voltage Voled) - operating point voltage Voled", that is, the sum voltage of the data voltage Vdata and the threshold voltage Vth.

[0083] At this time, the drain-source current Ids of the driving transistor DR, that is, the driving current Ioled, can be determined by Equation (1) below.

[0084] [Equation (1)] Ids = 0.5k(Vdata + Vth) 2 = Ioled Here, k is a constant determined by the mobility, channel ratio, parasitic capacitance, etc. of the driving transistor DR.

[0085] In this way, the driving current Ioled applied to the light-emitting element LD during the light-emitting period t4 includes a compensation value for the threshold voltage Vth of the driving transistor DR. Therefore, it is possible to compensate for changes in the characteristic values of the driving transistor DR due to deterioration of the pixel PX.

[0086] On the other hand, during the light emission period t4, the third transistor T3 is controlled to be in the off state. As a result, the voltage level of the third node N3 is prevented from changing due to the voltage of the source electrode of the driving transistor DR, and the voltage of the gate electrode of the driving transistor DR is stably maintained during the light emission period t4, so that an image can be stably displayed without a change in luminance.

[0087] Considering the driving method described above, while the pixel PX is being driven, only the first transistor T1 is directly connected to the gate electrode of the driving transistor DR, and the third transistor T3 and the fourth transistor T4 are alternately connected to the source electrode of the driving transistor DR, so that only one transistor is connected. Generally, when a transistor is switched, the voltage of the connected node may fluctuate and cause a loss. In the pixel PX according to the present disclosure, by minimizing the number of transistors connected to control each node voltage of the driving transistor DR, the voltage loss of the gate electrode and the source electrode of the driving transistor DR can be reduced.

[0088] Also, the pixel PX according to the present disclosure is driven using one light emission signal EM. That is, the pixel PX does not require a plurality of light emission signals EM. Thereby, the number of wirings required for the driving unit of the display device 1 can be reduced, and narrow bezelization can be realized.

[0089] As described above, the embodiments of the present invention have been described with reference to the accompanying drawings. However, it can be understood that the above-described technical configuration of the present invention can be realized in other specific forms without changing the technical idea and essential features of the present invention by those skilled in the technical field to which the present invention belongs. Therefore, it should be understood that the above embodiments are exemplary in all respects and not restrictive. Furthermore, the scope of the present invention is indicated by the claims described below rather than the above detailed description. Also, all changes or modified forms derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the scope of the present invention.

Claims

1. A light-emitting element; a driving transistor having a first electrode connected to a high potential driving voltage and a second electrode electrically connected to the light emitting element, the driving transistor controlling an amount of driving current supplied to the light emitting element in response to a voltage of a gate electrode; a first transistor for transmitting a reference voltage to the gate electrode of the driving transistor in response to a first gate signal; a second transistor for transmitting a data voltage to the gate electrode of the driving transistor in response to a second gate signal different from the first gate signal; a third transistor that electrically connects the gate electrode of the driving transistor and the second electrode of the driving transistor in response to the first gate signal; a fourth transistor electrically connecting the second electrode of the driving transistor and the light emitting element in response to a light emitting signal.

2. The driving transistor is the gate electrode of a first node; a first electrode of the driving transistor connected to a first power supply line that supplies the high potential driving voltage to the first electrode of the driving transistor; The pixel of claim 1 , further comprising: the second electrode electrically connected to the light emitting element of a second node.

3. the first transistor is connected to the gate electrode of the drive transistor at the first node and to a reference voltage line that supplies the reference voltage to the first transistor, the first transistor having a gate electrode that receives the first gate signal; the second transistor is connected to the third node of the third transistor and to a data line that supplies the data voltage to the second transistor, the second transistor having a gate electrode that receives the second gate signal; the third transistor is connected to the second transistor at the third node and to the drive transistor at the second node, the third transistor having a gate electrode receiving the first gate signal; 3. The pixel of claim 2, wherein the fourth transistor is electrically connected to the second node and the light-emitting element while the third transistor is on, the fourth transistor having a gate electrode receiving the light-emitting signal.

4. The pixel of claim 3 , further comprising a first capacitor connected between the first node and the third node.

5. a second capacitor connected between the third node and a fourth node; a fifth transistor, the fifth transistor having a gate electrode connected to the second capacitor at the fourth node and to a second power supply line that provides a base voltage to the fifth transistor, the fifth transistor receiving a third gate signal; 5. The pixel of claim 4, further comprising: a sixth transistor having a gate electrode connected to the second capacitor and the fifth transistor at the fourth node, the sixth transistor being connected to the light emitting element and the fourth transistor to receive the light emitting signal.

6. The pixel of claim 5 , wherein while the second transistor is in an on state, the data voltage is transferred to the gate electrode of the drive transistor through the first capacitor.

7. 6. The pixel of claim 5, wherein the third transistor is configured to be off while the second transistor is on or while the light emitting element is emitting light, thereby electrically isolating the second node from the third node.

8. 6. The pixel of claim 5, wherein during an initialization period of one frame, the first gate signal, the light emission signal, and the third gate signal are applied at a turn-on level, the first node is initialized to the reference voltage via the first transistor that is turned on during the initialization period, and the second node, the third node, and the fourth node are initialized to the base voltage via the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor that are turned on during the initialization period.

9. 6. The pixel of claim 5, wherein during a sensing period of one frame, while the first gate signal and the third gate signal are applied at a turn-on level, the gate electrode and the second electrode of the driving transistor are electrically connected to each other by the first capacitor and the third transistor that are turned on during the sensing period, and a voltage corresponding to a voltage difference between the reference voltage and a threshold voltage of the driving transistor is stored in the second capacitor.

10. 6. The pixel of claim 5, wherein during a programming period of one frame, the second gate signal and the third gate signal are applied at a turn-on level, the third node is set to the data voltage via the second transistor that is turned on during the programming period, the fourth node is set to the base voltage via the fifth transistor that is turned on during the programming period, the data voltage is stored in the second capacitor, and a sum of the data voltage and a threshold voltage of the driving transistor is stored in the first capacitor.

11. 6. The pixel according to claim 5, wherein during a light emission period of one frame, the light emission signal is applied at a turn-on level, a driving current is applied to the light emitting element via a fourth transistor that is turned on during the light emission period, and the light emitting element emits light in response to the driving current.

12. A light-emitting element; a drive transistor having a gate electrode at the first node; a first electrode connected to a high potential driving voltage line that supplies a high potential driving voltage to the first electrode; a second electrode connected to a second node; a first transistor having a gate electrode connected to the gate electrode of the drive transistor at the first node and to a reference voltage line providing a reference voltage to the first transistor, the first transistor receiving a first gate signal; a second transistor, the second transistor having a gate electrode connected to a data line supplying a data voltage to the second transistor and to a third node and receiving a second gate signal; a third transistor connected between the third node and the second node and having a gate electrode for receiving the first gate signal; a fourth transistor connected between the third node and the light emitting element and having a gate electrode for receiving a light emitting signal; a first capacitor connected between the first node and the third node; A method of driving a pixel comprising: applying the first gate signal and the light emission signal at a turn-on level during an initialization period, the first transistor and the third transistor being turned on during the initialization period in response to the first gate signal, and the fourth transistor being turned on during the initialization period in response to the light emission signal; applying the first gate signal at a turn-on level during a sensing period after the initialization period, the first transistor and the third transistor being turned on during the sensing period in response to the first gate signal; applying the second gate signal at a turn-on level during a programming period after the sensing period, the second transistor being turned on during the programming period in response to the second gate signal; applying the light emission signal at a turn-on level during an emission period after the programming period, the fourth transistor being responsive to the light emission signal to turn on during the emission period.

13. The pixel is a second capacitor connected between the third node and a fourth node; a fifth transistor connected to the second capacitor at the fourth node and to a second power supply line that supplies a base voltage, the fifth transistor having a gate electrode that receives a third gate signal; 13. The method of claim 12, further comprising: a sixth transistor connected to the second capacitor and the fifth transistor at the fourth node, and to the light emitting element and the fourth transistor, the sixth transistor having a gate electrode receiving the light emitting signal.

14. 14. The method of claim 13, wherein the third gate signal is further applied at a turn-on level during the initialization period and the programming period, and the fifth transistor is turned on in response to the third gate signal during the initialization period and the programming period.

15. 15. The method of claim 14, wherein during the programming period, the data voltage applied to the data line is transferred to the gate electrode of the drive transistor through the first capacitor.

16. 15. The method of claim 14, wherein the second node and the third node are electrically isolated from each other by turning off the third transistor during the programming period and the light emission period.

17. A display device, comprising: A display panel including a plurality of pixels, each of which includes the pixel according to claim 1; a gate driver configured to apply the first gate signal, the second gate signal, and a third gate signal to the plurality of pixels; an emission driver configured to apply the emission signal to the plurality of pixels; a data driver configured to output the data voltages to the plurality of pixels; a timing controller configured to control operation timings of the gate driver, the light emitting driver, and the data driver.

18. A light-emitting element; a drive transistor including a first electrode connected to a high potential voltage line supplying a high potential drive voltage to the drive transistor, a second electrode connected to a second node, and a gate electrode connected to the first node; a first transistor including a first electrode connected to a reference line providing a reference voltage to the first transistor, a second electrode connected to the gate electrode of the drive transistor at the first node, and a gate electrode receiving a first gate signal; a second transistor including a first electrode connected to a data line providing a data voltage to the second transistor, a second electrode connected to a third node, and a gate electrode receiving a second gate signal different from the first gate signal; a third transistor including a first electrode connected to the second electrode of the second transistor at the third node, a second electrode connected to the second electrode of the drive transistor at the second node, and a gate electrode receiving the first gate signal; a fourth transistor including a first electrode connected to the second electrode of the driving transistor and the second electrode of the third transistor at the second node, a second electrode connected to the light emitting element, and a gate electrode receiving a light emitting signal; a first capacitor including a first capacitor electrode connected to the second electrode of the first transistor and the gate electrode of the driving transistor at the first node, and a second capacitor electrode connected to the second electrode of the second transistor and the first electrode of the third transistor at the third node.

19. a second capacitor including a first capacitor electrode connected to the second electrode of the second transistor, the second capacitor electrode of the first capacitor, and the first electrode of the third transistor at the third node, and a second capacitor electrode connected to a fourth node; a fifth transistor including a first electrode connected to the second capacitor electrode of the second capacitor at the fourth node, a second electrode connected to a second power supply line providing a base voltage to the fifth transistor, and a gate electrode receiving a third gate signal; 20. The pixel of claim 18, further comprising: a sixth transistor including a first electrode connected to the second capacitor electrode of the second capacitor at the fourth node and the first electrode of the fifth transistor, a second electrode connected to the second electrode of the fourth transistor and a light emitting element, and a gate electrode receiving the light emitting signal.

20. 20. The pixel of claim 19, wherein during an initialization period of one frame, the first gate signal, the light emission signal, and the third gate signal are applied at a turn-on level, the first node is initialized to the reference voltage via the first transistor that is turned on during the initialization period, and the second node, the third node, and the fourth node are initialized to the base voltage via the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor that are turned on during the initialization period.

21. During a sensing period after the initialization period of one frame, a first gate signal and a third gate signal are applied at a turn-on level to turn on the first transistor, the third transistor, and the fifth transistor during the sensing period, while the gate electrode and the second electrode of the driving transistor are electrically connected by the third transistor and the first capacitor, and a voltage corresponding to a voltage difference between the reference voltage and a threshold voltage of the driving transistor is stored in the second capacitor; The pixel of claim 20 , wherein during the sensing period, the second transistor, the fourth transistor and the sixth transistor are turned off.

22. During a programming period of one frame after the sensing period, the second gate signal and the third gate signal are applied at a turn-on level, the second transistor and the fifth transistor are turned on during the programming period, the third node is set to the data voltage by the second transistor, the fourth node is set to the base voltage by the fifth transistor, the data voltage is stored in the second capacitor, and a sum of the data voltage and a threshold voltage of the driving transistor is stored in the first capacitor; The pixel of claim 21 , wherein the third transistor, the fourth transistor, and the sixth transistor are turned off during the programming period.

23. 23. The pixel of claim 22, wherein the data voltage is transferred to the gate electrode of the drive transistor through the first capacitor while the second transistor is on during the programming period.

24. during a light emission period of one frame, the light emission signal is applied at a turn-on level, the fourth transistor and the sixth transistor are turned on during the light emission period, a drive current is applied to the light emitting element via the fourth transistor, and the light emitting element emits light in response to the drive current; 23. The pixel of claim 22, wherein the first transistor, the second transistor, the third transistor and the fifth transistor are turned off during the light emitting period.

25. 25. The pixel of claim 24, wherein the second transistor is configured to be on during the programming period or the third transistor is configured to be off while the light emitting element is emitting light during the light emitting period, thereby isolating the second node and the third node.

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