Differential amplifier, digital-analog conversion circuit, and display driver

Abstract

PURPOSE: To provide a differential amplifier in which grayscale inversion is suppressed, and a digital-analog conversion circuit and a display driver using the differential amplifier.CONSTITUTION: A differential amplifier pertaining to the present invention comprises: a first differential pair for differentially inputting a first voltage and an output voltage; a second differential pair for differentially inputting a second voltage and an output voltage; a control circuit for supplying a drive current to one or both of the first and second differential pairs on the basis of a digital data signal; an amplification stage for receiving the voltage of an output pair of each of the first and second differential pairs and converting it to an output voltage; an auxiliary circuit for supplying a prescribed auxiliary current to the other differential pair when the drive current is supplied to only one differential pair; and a coupling circuit for coupling the output pairs of both differential pairs when supplying the drive current to both of the first and second differential pairs, and severing the coupling of the output pairs when supplying the drive current to only one differential pair.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a differential amplifier, a digital - to - analog conversion circuit including the differential amplifier, and a display driver including the digital - to - analog conversion circuit.

Background Art

[0002] Currently, as display devices, active - matrix liquid - crystal display devices, organic EL display devices, etc. are mainstream. Such display devices are equipped with a display panel in which display cells connected to a plurality of data lines are arranged in a matrix, and a data driver for driving the plurality of data lines of the display panel. The data driver is provided with a digital - to - analog conversion circuit including a differential amplifier that converts a video digital signal into an analog voltage corresponding to a luminance level and amplifies the voltage signal to supply it to each data line of the display panel.

[0003] The schematic configuration of the data driver will be described below.

[0004] The data driver includes, for example, a shift register, a data register latch, a level shifter, and a DA (digital to analog) conversion section. The shift register generates a plurality of latch timing signals for selecting a latch in synchronization with a clock signal in response to a start pulse supplied from a display controller, and supplies them to the data register latch. The data register latch takes in video digital data supplied from the display controller in a predetermined number (for example, n) based on each of the latch timing signals supplied from the shift register, and supplies n video digital data signals representing each video digital data to the level shifter. The level shifter performs a level - shift process to increase the signal amplitude for each of the n video digital data signals supplied from the data register latch, and supplies the n level - shifted video digital data signals to the DA conversion section.

[0005] The DA conversion section includes a reference voltage generation circuit, a decoder section, and an amplification section.

[0006] The reference voltage generation circuit generates a plurality of reference voltages with different voltage values and supplies them to the decoder section. For example, the reference voltage generation circuit supplies a plurality of divided voltages obtained by dividing the voltage between the power supply voltage and the reference voltage by a ladder resistor to the decoder section as a reference voltage group. Note that digital-to-analog conversion using a plurality of reference voltages generated by such a ladder resistor is called the RDAC method.

[0007] The decoder section has n decoder circuits provided corresponding to each output of the data driver. Each of the decoder circuits receives the video digital data signal supplied from the level shifter, selects two different reference voltages corresponding to this video digital data signal from among the plurality of reference voltages, and supplies the selected two reference voltages to the amplifier section.

[0008] The amplifier section has n differential amplifiers each of which amplifies and outputs the two reference voltages supplied from the decoder section.

[0009] By the way, in the DA conversion section described above, the larger the number of reference voltages generated by the reference voltage generation circuit, the more the number of gradations (number of colors) of the luminance levels that can be expressed can be increased. However, increasing the number of reference voltages generated by the reference voltage generation circuit increases the chip size of the data driver and increases the manufacturing cost accordingly.

[0010] Therefore, as the differential amplifier described above, a differential amplifier that performs so-called interpolation operation, which is capable of generating a voltage having a voltage value between two input voltages as an output voltage by weighting and averaging two different input voltages, has been proposed (see, for example, Patent Documents 1 and 2).

[0011] According to a differential amplifier (also referred to as an interpolation amplifier) that performs such an interpolation operation, by the interpolation operation based on a plurality of input voltages, it is possible to obtain voltage values with a gradation number larger than the number of voltage values that can be represented by the plurality of input voltages. Therefore, even if the total number of reference voltages generated by the reference voltage generation circuit is reduced, it is possible to generate voltages corresponding to the desired gradation number.

[0012] Hereinafter, the configuration of the interpolation amplifier will be described by extracting the differential amplifier described in FIGS. 5 and 6 of Patent Document 2.

[0013] The differential amplifier includes first and second differential pairs that receive two different input voltages V1 and V2 at the non-inverting input terminal and receive the output voltage V3 at the inverting input terminal. In such a differential amplifier, by controlling the current ratio of the total current of the drive currents flowing through the first and second differential pairs respectively, it is possible to output a voltage that interpolates the input voltages V1 and V2 at a predetermined ratio. That is, this differential amplifier is a differential amplifier in which the interpolation ratio of the input voltages V1 and V2 is determined by the weighting ratio of the drive currents of the first and second differential pairs that receive the input voltages V1 and V2.

[0014] Here, in the differential amplifier, when outputting the same voltage as the input voltage V1 or V2, all of the drive current is supplied to one of the first and second differential pairs, and the supply of the drive current to the other differential pair is cut off. The drive currents supplied to the first and second differential pairs are controlled to be turned on and off by the lower bits of the video digital signal indicating the luminance level for the switches connected to the current source.

[0015] Thereby, the digital-to-analog conversion circuit including the differential amplifier can significantly reduce the number of reference voltages generated by the reference voltage generation circuit and the number of switch transistors for selecting the reference voltage in the decoder. Particularly when the number of bits of the video digital signal is large, it is an effective means to suppress an increase in the circuit scale of the digital-to-analog conversion circuit and an increase in the chip area.

Prior Art Documents

Patent Documents

[0016] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-174180 [Patent Document 2] Japanese Patent Application Laid-Open No. 2011-135158 [Summary of the Invention] [Problems to be Solved by the Invention]

[0017] Recently, with the increase in the size and resolution of display panels, the load capacitance of the data lines of the display panel that the above-described data driver has to drive has increased, and the driving period per pixel (also referred to as one data period) for the data driver to drive the data lines has a tendency to become shorter.

[0018] When the load capacitance of the data line is large and the driving period is short, it becomes difficult to fully charge the data line within one data period, and display may be performed with a gradation voltage in a transition state (during voltage change) before reaching 100%.

[0019] Therefore, in order to ensure display quality, it is essential that, as the gradation voltage output to the data line, a gradation reversal does not occur in which the voltage value of one gradation voltage is higher (or lower) than the voltage value of a gradation voltage that is higher (or lower) than the voltage value of that one gradation voltage even when the voltage value transitions.

[0020] However, in a conventional differential amplifier as described in Patent Document 2, when an output voltage having the same voltage value as one of two input voltages is output, the drive current supplied to the differential pair that receives the other input voltage becomes zero, and the tail potential of the differential pair becomes an indeterminate state.

[0021] At this time, the tail potential is significantly different from the tail potential obtained when outputting the interpolated voltage between the two input voltages. Therefore, this difference in tail potential becomes a factor increasing the output delay (transition time of voltage change until reaching the target voltage) for the current input voltage or the next input voltage. As a result, a time difference corresponding to the difference in the value of the tail current occurs in the output delay for each of the successive voltage levels, and there was a possibility that the above-described gradation inversion occurred. This effect becomes particularly significant in a high-speed driven differential amplifier.

[0022] Hereinafter, such gradation inversion will be described with reference to FIGS. 1A, 1B, and 1C.

[0023] FIGS. 1A and 1B are configuration diagrams schematically showing the differential amplifier described in Patent Document 1 or 2 above. In FIGS. 1A and 1B, input voltages IN0 and IN1 having different voltage values from each other are received at the non-inverting input terminals of differential pair Df1 (first differential pair) and differential pair Df2 (second differential pair), respectively, and the output voltage Vout is received at the inverting input terminals of differential pairs Df1 and Df2, respectively. Also, in FIGS. 1A and 1B, the supply or cut-off of the tail current i1 to differential pairs Df1 and 2 by two current sources is controlled by a switch group that is turned on and off by the bit signal D0. For the sake of convenience, FIGS. 1A and 1B show only a differential pair formed by a pair of NMOS transistors, a current source that drives it, and an amplification stage that receives the output of the differential pair and produces an amplification effect.

[0024] Here, FIG. 1A is a circuit diagram briefly showing the state of the circuit of the differential amplifier when the bit signal D0 = 0 (logical value 0), and the current i1 generated by two current sources is supplied to differential pairs Df1 and Df2, respectively. When differential pairs Df1 and Df2 are configured to have the same size, the output voltage Vout becomes Vout = (IN0 + IN1) / 2, which interpolates the input voltages IN0 and IN1 one-to-one.

[0025] Figure 1B is a circuit diagram that briefly shows the state of the circuit of the differential amplifier when the bit signal D0 = 1 (logical value 1). The current i1 generated by two current sources is supplied only to the differential pair Df2. At this time, the current supply to the differential pair Df1 is cut off (current zero), and the differential amplifier generates an output voltage Vout having the same voltage value as the input voltage IN1 of the differential pair Df2.

[0026] Figure 1C is a waveform diagram showing the waveforms of the input voltages IN0 and IN1, the output voltage Vout, the tail voltage TL1 of the differential pair Df1, and the tail voltage TL2 of the differential pair Df2 when the voltage value of the input voltage IN0 transitions between 1V and 8.5V and the voltage value of the input voltage IN1 transitions between 1.2V and 8.7V.

[0027] Note that in Figure 1C, waveforms for four data periods corresponding to four consecutive data pieces are shown. For the output voltage Vout, it is assumed that the load is a data line, and the voltage waveform at the near end of the data line is shown. At this time, the voltage waveform at the far end of the data line has a delay corresponding to the impedance (resistance and capacitance) of the data line with respect to the voltage waveform at the near end of the data line. Also, the bit signal D0 represents a logical value 0 in the first and second data periods of the first half and a logical value 1 in the third and fourth data periods of the second half.

[0028] As shown in Figure 1C, the output voltage Vout changes at a predetermined slew rate with respect to the voltage changes of the input voltages IN0 and IN1, and after the input voltages IN0 and IN1 become stable, it becomes the output voltage according to the bit signal D0.

[0029] That is, in the first and second data periods when the bit signal D0 is at the logical value 0, the output voltage Vout stabilizes at 1.1V or 8.6V respectively. On the other hand, in the third and fourth data periods when the bit signal D0 is at the logical value 1, the output voltage Vout stabilizes at 1.2V or 8.7V respectively.

[0030] Also, the voltages of the tails TL1 and TL2 of the differential pairs Df1 and Df2 change according to the voltage signal on the high-potential side among the voltage signals supplied to the non-inverting input and the inverting input of the differential pair during the first and second data periods when the bit signal D0 has a logical value of 0, and stabilize at a voltage (about 5.8V, about 0.2V) that is lower than the threshold voltage by about the threshold voltage from the high-potential side voltage signal.

[0031] On the other hand, during the third and fourth data periods when the bit signal D0 has a logical value of 1, the voltage of the tail TL2 of the differential pair Df2 changes in substantially the same manner as during the first and second data periods. However, during the third and fourth data periods, since the current supply to the differential pair Df1 is cut off, the voltage change of the tail TL1 of the differential pair Df1 is significantly different from the voltage change during the first and second data periods. At this time, the voltage change of the tail TL1 during the third and fourth data periods is also significantly different from the voltage change of the tail TL2 of the differential pair Df2 during the third and fourth data periods.

[0032] That is, the voltage of the tail TL1 of the differential pair Df1 first changes to about 5.8V in response to the change in the input voltage IN0 at the non-inverting input terminal during the third data period, and then changes to about 7.6V due to capacitive coupling by the parasitic capacitance of the transistor in response to the change in the voltage Vout at the inverting input terminal.

[0033] Also, the voltage of the tail TL1 of the differential pair Df1 first changes to about 4.8V due to capacitive coupling by the parasitic capacitance of the transistor in response to the change in the input voltage IN0 at the non-inverting input terminal during the fourth data period, and then changes to about 3.8V due to capacitive coupling by the parasitic capacitance of the transistor in response to the change in the voltage Vout at the inverting input terminal.

[0034] As described above, in a conventional interpolation operation type differential amplifier, when outputting an output voltage (Vout) having the same voltage value as one of two input voltages (IN0, IIN1) (for example, IN1) (D0 = 1), the drive current of the differential pair receiving the other input voltage (IN0) is set to zero. As a result, the potential of the tail of the differential pair (for example, tail TL1) becomes an indeterminate state and greatly fluctuates under the influence of capacitive coupling due to parasitic capacitance. The tail potential at this time is a value significantly different from the tail potential obtained when performing interpolation output (D0 = 0).

[0035] Therefore, such a difference in tail potential affects the output delay of the output voltage immediately after switching from the data period of performing interpolation output (the second data period) to the data period of outputting a voltage having the same voltage value as the input voltage (the third data period), or the output delay of the output voltage immediately after switching from the data period of outputting a voltage having the same voltage value as the input voltage to the next data period.

[0036] As a result, a difference occurs in the output delay between consecutive voltage levels, and there is a possibility of gray scale inversion occurring.

[0037] Therefore, an object of the present invention is to provide an interpolation operation type differential amplifier that suppresses gray scale inversion, a digital - analog conversion circuit using the same, and a display driver.

Means for Solving the Problem

[0038] The differential amplifier according to the present invention receives an N (N is an integer of 1 or more)-bit digital data signal together with first and second voltages having different voltage values, and inserts the first and second voltages into 2 to the power of N pieces, and outputs, as an output voltage, one voltage based on the digital data signal among the 2 to the power of N voltages thus interpolated, and amplifies and outputs the voltage. The differential amplifier includes: a first differential pair that differentially inputs the first voltage and the output voltage; a second differential pair that differentially inputs the second voltage and the output voltage; a control circuit that supplies a drive current to one of the first differential pair and the second differential pair, or both the first differential pair and the second differential pair, based on the digital data signal; an amplification stage that receives the voltage of each output pair of the first differential pair and the second differential pair, or one of the output pairs, and converts the received voltage into the output voltage; an auxiliary circuit that supplies a predetermined auxiliary current to the other differential pair of the first differential pair and the second differential pair when the control circuit supplies the drive current only to the one differential pair based on the digital data signal; and a coupling circuit that couples the output pairs of the first differential pair and the second differential pair when the control circuit supplies the drive current to both the first differential pair and the second differential pair based on the digital data signal, and disconnects the coupling of the output pairs when the drive current is supplied only to the one differential pair.

[0039] The digital - to - analog conversion circuit according to the present invention is a digital - to - analog conversion circuit that converts an M - bit (M is an integer of 2 or more) digital data signal into an output voltage having an analog voltage value, and includes a voltage generation circuit that generates a plurality of voltages having different voltage values, and a decoder that receives a higher - order digital data signal composed of higher - order bits excluding the lower N (N is an integer of 1 or more) bits in the M - bit digital data signal, and based on the higher - order digital data signal, selects first and second voltages having different voltage values from among the plurality of voltages, and the differential amplifier described above. The differential amplifier receives the first and second voltages selected by the decoder and a digital data signal composed of the lower N bits in the M - bit digital data signal, and amplifies and outputs the output voltage having an analog voltage value corresponding to the M - bit digital data signal.

[0040] The display driver according to the present invention is a display driver having a plurality of output channels that output a plurality of gradation voltage signals based on a video signal, and is characterized in that the differential amplifier described above or the digital - to - analog conversion circuit described above is provided for each of the plurality of output channels.

Effect of the Invention

[0041] The differential amplifier according to the present invention receives first and second voltages having different voltage values from each other, and based on a digital data signal, supplies a drive current to one or both of a first differential pair that differentially inputs the first voltage and the output voltage, and a second differential pair that differentially inputs the second voltage and the output voltage. At this time, the amplification stage receives the voltages applied to the output pair of the first differential pair and the output pair of the second differential pair and amplifies and outputs the output voltage.

[0042] At this time, in the invention of the present application, when drive currents are supplied to both of the first and second differential pairs, the output of one of the differential pairs is combined with the output of the other differential pair. On the other hand, when drive current is supplied to only one of the first and second differential pairs, a predetermined auxiliary current is supplied to the other differential pair described above in a state where the connection between the outputs of the first and second differential pairs is cut off. Therefore, even when drive current is supplied to only one of the first and second differential pairs, an auxiliary current is supplied to the other differential pair and the other differential pair operates, so that the tail voltage of the other differential pair is stabilized. As a result, it becomes possible to eliminate the difference in output delay between adjacent gradation voltages in a data period subsequent to a data period in which an output voltage having one of the first and second voltage values is output.

[0043] Therefore, according to the present invention, it is possible to realize driving that prevents gradation inversion at the time of transition of the voltage value when the input voltage changes.

Brief Description of Drawings

[0044]

Figure 1A

Figure 1B

Figure 1C

Figure 2

Figure 3

Figure 4A

Figure 4B

Figure 5A

Figure 5B

Figure 6

Figure 7A

Figure 7B

Figure 8A

Figure 8B

Figure 8C

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15A

Figure 15B

Mode for Carrying Out the Invention

[0045] Hereinafter, embodiments of the present invention will be described in detail.

[0046] FIG. 2 is a circuit diagram showing the configuration of a differential amplifier 100 showing an overview of the differential amplifier according to the present invention.

[0047] The differential amplifier 100 receives a first level voltage IN0 and a second level voltage IN1 having different voltage values via input terminals T1 and T2. The differential amplifier 100 amplifies and outputs, as an output voltage Vout, one of 2 to the Nth power of level voltages interpolated at a predetermined ratio based on an N-bit (N is an integer of 1 or more) digital data signal DX from these level voltages IN0 and IN1. Note that the first and second level voltages IN0 and IN1 have a voltage difference sufficiently small with respect to the output voltage range of the differential amplifier 100.

[0048] The differential amplifier 100 in FIG. 2 includes a differential pair Df1 that differentially inputs the first level voltage IN0 and the output voltage Vout, and a differential pair Df2 that differentially inputs the second level voltage IN1 and the output voltage Vout.

[0049] The differential pair Df1 includes an N-channel transistor 11 that receives the first level voltage IN0 at its gate, and an N-channel transistor 12 that receives the output voltage Vout at its gate. The sources of the transistors 11 and 12 are connected to each other, and the connection point serves as the tail of the differential pair Df1. On the other hand, the drains of the transistors 21 and 22 each serve as an output pair of the differential pair Df1.

[0050] The differential pair Df2 includes an N-channel transistor 21 that receives the second-level voltage IN1 at its gate, and an N-channel transistor 22 that receives the output voltage Vout at its gate. The sources of transistors 21 and 22 are connected to each other, and the connection point serves as the tail of the differential pair Df2. On the other hand, the drains of transistors 21 and 22 respectively form the output pair of the differential pair Df2.

[0051] Here, each transistor constituting the differential pairs Df1 and Df2 has the same conductivity type and the same size. Therefore, even if the differential pairs Df1 and Df2 are interchanged, an equivalent circuit configuration is obtained.

[0052] Furthermore, the differential amplifier 100 includes the following first and second load circuits 10 and 20, control circuit 30, auxiliary circuit 40, coupling circuit 50, and amplification stage 60.

[0053] The load circuit 10 receives the high-level power supply voltage VDD and is connected to the output pair in the differential pair Df1. The load circuit 20 receives the high-level power supply voltage VDD and is connected to the output pair in the differential pair Df2. The load circuits 10 and 20 are composed of, for example, a current mirror circuit connected between the respective output pairs of the differential pairs Df1 and Df2 and the high-level power supply voltage VDD, a pair of resistor elements, or a constant current source. Note that the load circuit 10 may include a switch that receives the N-bit digital data signal DX and is turned on and off based on the N-bit digital data signal DX, and may be configured such that its activation and inactivation are controlled by the on-off control of the switch.

[0054] The control circuit 30 is connected between the tail nodes n10 and n20, which are the respective tail nodes of the differential pairs Df1 and Df2, and the low-level power supply voltage VSS.

[0055] The control circuit 30 includes (N + 1) current sources 30_1 to 30_(N + 1) consisting of a current source with a current ratio of 1 and N current sources with a current ratio of 2 to the power of k (k is an integer from 0 to N - 1), and a switch group 31 that supplies the respective currents of the current sources 30_1 to 30_(N + 1) to one of the tails of the differential pairs Df1 and Df2. The switch group 31 receives an N-bit digital data signal DX, and based on the digital data signal DX, selects one of the 2 to the power of N combinations by the current sources 30_1 to 30_(N + 1), and supplies the total current by the selected combination of current sources to both of the respective tails n10 and n20 of the differential pairs Df1 and Df2, or to only the tail n20. Note that the (N + 1) current sources 30_1 to 30_(N + 1) consisting of a current source with a current ratio of 1 and N current sources with a current ratio of 2 to the power of k (k is an integer from 0 to N - 1) are the case when configured with the minimum number of current sources, and the actual number of current sources is not limited to N. The control circuit 30 has a plurality of current sources each having a predetermined current ratio, and based on the digital data signal DX, selects one of the 2 to the power of N combinations of current ratios by the plurality of current sources, and may be configured to supply the combined current of each of the selected combination of current sources as a drive current to one or both of the tail nodes of the differential pairs Df1 and Df2. For example, a combination of 2 to the power of N current ratios may be configured by 2 to the power of N current sources with equal current ratios.

[0056] With such a configuration, the control circuit 30 sets one of the 2 to the power of N combinations based on the N-bit digital data signal DX for each current ratio of the total of the drive currents I1 and I2 of the differential pairs Df1 and Df2 that contribute to the amplification action. Then, the control circuit 30 supplies the currents of the set current ratio to the differential pairs Df1 and Df2 respectively.

[0057] The auxiliary circuit 40 has an auxiliary current source 40_1 and a switch 41 connected in series between the tail n10 of the differential pair Df1 and the low power supply voltage VSS. The auxiliary circuit 40 receives an N-bit digital data signal DX, and based on the N-bit digital data signal DX, controls whether to supply an auxiliary current ia that does not contribute to the amplification effect to the differential pair Df1.

[0058] The coupling circuit 50 is composed of switches 51 and 52 that control the connection between the output pairs of the differential pairs Df1 and Df2, for example. By controlling the on / off states of the switches 51 and 52 based on the N-bit digital data signal DX, the coupling between the output pair of the differential pair Df1 and the output pair of the differential pair Df2 is controlled.

[0059] The amplification stage 60 receives the output of the differential pair Df2, or the outputs of both the differential pairs Df1 and Df2, and converts them into an output voltage Vout. The output voltage Vout is output via the output terminal T3 and is also fed back to the differential pairs Df1 and Df2.

[0060] With the above-described configuration, the differential amplifier 100 amplifies and outputs, as the output voltage Vout, one of the voltage levels obtained by interpolating (dividing) the first and second level voltages IN0 and IN1 into 2 to the power of N combinations corresponding to the ratio of the drive currents of the differential pairs Df1 and Df2.

[0061] When the differential amplifier 100 outputs the same voltage value as the second level voltage IN1 as the output voltage Vout, the currents of each of the current sources 30_1 to 30_(N + 1) are all supplied to the tail n20 of the differential pair Df2.

[0062] Next, the operation of this embodiment will be described with reference to FIG. 3. FIG. 3 shows the operating states of the load circuit 10, the control circuit 30, the auxiliary circuit 40, and the coupling circuit 50 with respect to the output voltage Vout.

[0063] First, when it is shown that the digital data signal DX outputs an interpolation voltage between IN0 and IN1 having voltage values different from the first and second level voltages IN0 and IN1 as the output voltage Vout, the control circuit 30 controls each switch of the switch group 31 to be in the on or off state based on the digital data signal DX. That is, by such control, the control circuit 30 distributes and supplies the currents of the current sources 30_1 to 30_(N + 1) to the respective tails n10 and n20 of the differential pairs Df1 and Df2. At this time, the switch 41 of the auxiliary circuit 40 is turned off, and the supply of the auxiliary current ia generated by the auxiliary current source 40_1 to the tail n10 is blocked. Further, at this time, the coupling circuit 50 connects the output pairs of the differential pairs Df1 and Df2 to each other, and the amplification stage 60 operates based on the combined output of the respective output pairs of the differential pairs Df1 and Df2. Also, the load circuit 10 is controlled to be inactive or active. When the load circuit 10 is controlled to be inactive, all the drive currents I1 and I2 distributed by the control circuit 30 to the differential pairs Df1 and Df2 flow to the load circuit 20. When the load circuit 10 is controlled to be active, the drive currents I1 and I2 distributed by the control circuit 30 to the differential pairs Df1 and Df2 flow to the load circuits 10 and 20, respectively. In both cases, since the output pairs of the differential pairs Df1 and Df2 are coupled to each other via the coupling circuit 50, the amplification effects of the differential amplifier 100 are substantially the same. Note that the coupling circuit 50 and the load circuit 10 are also controlled to operate by on / off control of the internal switches based on the digital data signal DX, similar to the control circuit 30 and the auxiliary circuit 40.

[0064] Therefore, one of the voltage levels obtained by interpolating the level voltages IN0 and IN1 into 2 to the power of N is determined by the ratio of the drive currents flowing through the differential pairs Df1 and Df2, respectively, and the differential amplifier 100 amplifies and outputs a voltage having that one voltage level as the output voltage Vout.

[0065] Also, when the digital data signal DX indicates that an output voltage Vout having the same voltage value as the second level voltage IN1 is to be output, the control circuit 30 controls each switch of the switch group 31 to be in an on or off state based on the digital data signal DX. That is, by such control, the control circuit 30 supplies all the currents of the current sources 30_1 to 30_(N + 1) to the tail n20 of the differential pair Df2. At this time, the switch 41 of the auxiliary circuit 40 is turned on, and the auxiliary current ia generated by the auxiliary current source 40_1 is supplied to the tail n10. Also, at this time, the coupling circuit 50 cuts off the connection between the output pairs of the differential pairs Df1 and Df2, and operates the amplification stage 60 only by the output of the output pair of the differential pair Df2. Also, the load circuit 10 is actively controlled, and the auxiliary current ia flows through the differential pair Df1 to the load circuit 10.

[0066] Therefore, the differential amplifier 100 amplifies and outputs, as the output voltage Vout, a voltage having the same voltage value as the second level voltage IN1. At this time, the differential pair Df1 does not contribute to the amplification action, receives the first level voltage IN0 input to the differential pair Df1 and the output voltage Vout, and the first load circuit 10 operates. For this reason, the tail n10 of the differential pair Df1 becomes a voltage corresponding to the first level voltage IN0 and the output voltage Vout. Since the first and second level voltages IN0 and IN1 have a sufficiently small voltage difference with respect to the output voltage range of the differential amplifier 100, the voltage fluctuation at the tail n10 becomes almost the same voltage fluctuation as that of the tail n20 of the differential pair Df2 that receives the second level voltage IN1 and the output voltage Vout and contributes to the amplification action.

[0067] Hereinafter, a configuration example of the load circuit 10 will be described with reference to FIGS. 4A, 4B, 5A, and 5B.

[0068] FIG. 4A is a diagram showing a load circuit 10_1 as a configuration example of the load circuit 10 that can be controlled to be active or inactive, and FIG. 4B is a diagram showing the relationship between the active and inactive control of the load circuit 10_1 and the on / off control of the switch.

[0069] As shown in FIG. 4A, the load circuit 10_1 includes a current mirror (13, 14) and a switch 54 connected in series between the power supply voltage VDD and the output pair (n11, n12) of the differential pair Df1.

[0070] As shown in FIG. 4B, the load circuit 10_1 becomes active when the switch 54 is on and the current mirror (13, 14) functions, and becomes inactive when the switch 54 is off and the current mirror (13, 14) does not function.

[0071] In addition, in the example shown in FIG. 4A, a switch for conducting or interrupting current is added to control the activation and inactivation of the load circuit 10, but configurations other than FIG. 4A are also possible. For example, the transistors 13 and 14 constituting the current mirror (13, 14) may be replaced with resistive elements.

[0072] FIG. 5A is a diagram showing a load circuit 10_2 as another configuration example of the load circuit 10 that can be controlled to be active or inactive, and FIG. 5B is a diagram showing the relationship between the activation and inactivation control of the load circuit 10_2 and the on / off control of the switch.

[0073] As shown in FIG. 5A, the load circuit 10_2 includes a current mirror (13, 14), switches 55 and 56 connected between the power supply voltage VDD and the output pair (n11, n12) of the differential pair Df1.

[0074] As shown in FIG. 5B, the load circuit 10_2 becomes active when the switch 55 is off and the switch 56 is on, and the current mirror (13, 14) functions, and becomes inactive when the switch 55 is on and the switch 56 is off, and the current mirror (13, 14) does not function.

[0075] In addition, in the example shown in FIG. 5A, a switch for turning off the transistors constituting the load is added to control the activation and inactivation of the load circuit 10, but configurations other than FIG. 5A are also possible. For example, the transistors 13 and 14 constituting the current mirror (13, 14) may be replaced with current source transistors.

[0076] As described above, the load circuits 10 (10_1, 10_2) have their activation or inactivation controlled by the on / off control of the internal switches.

[0077] In FIG. 2, the digital data signal DX that controls the on / off of the internal switches of the load circuit 10, the control circuit 30, the auxiliary circuit 40, and the coupling circuit 50 is a single-bit or multi-bit signal, and the on / off of each internal switch is controlled based on the logical values of the signal group including the complementary signal of each bit signal.

[0078] When the digital data signal DX is a multi-bit signal, one switch function shown in FIG. 2 and the circuit diagrams of the following embodiments may be realized by the combination of a plurality of switches controlled by a multi-bit signal, or may be controlled by a signal obtained by logically synthesizing the multi-bit signal.

[0079] As described above, according to the differential amplifier 100 shown in FIG. 2, when outputting the output voltage Vout having the same voltage value as the second level voltage IN1, even if the supply of the drive current to the differential pair Df1 is stopped, the auxiliary current ia that does not contribute to the amplification operation is supplied to the differential pair Df1 and the differential pair Df1 operates, so that the voltage of the tail n10 of the differential pair Df1 is stabilized. Thereby, it is possible to realize a drive that prevents the gradation inversion at the time of the voltage value transition when the input voltage changes.

[0080] Note that the differential amplifier 100 shown in FIG. 2 shows a configuration having N-channel type differential pairs as the differential pairs Df1 and Df2, but of course, a configuration having P-channel type differential pairs may also be used. Also, a differential amplifier having both N-channel type differential pairs and P-channel type differential pairs can be configured.

[0081] In short, as the differential amplifier according to the present invention, when receiving first and second voltages (IN0, IN1) having different voltage values and amplifying and outputting, as an output voltage (Vout), one voltage based on an N-bit digital data signal (DX) among 2 to the power of N voltages obtained by interpolating the first and second voltages into 2 to the power of N, it may include at least the following first and second differential pairs, control circuit, amplification stage, auxiliary circuit, and coupling circuit.

[0082] That is, the first differential pair (Df1) receives the first voltage (IN0) and the output voltage (Vout) as differential inputs, and the second differential pair (Df2) receives the second voltage (IN1) and the output voltage as differential inputs. The control circuit (30) supplies drive currents (I1, I2) to one of the first and second differential pairs (Df1, Df2) or both of the first and second differential pairs based on the digital data signal (DX). The amplification stage (60) receives the voltages of the output pairs of each of the first and second differential pairs or one of the voltages of the output pairs and converts this into the output voltage. The auxiliary circuit (40) supplies a predetermined auxiliary current (ia) to the other differential pair of the first and second differential pairs when the control circuit supplies drive current only to the one differential pair based on the digital data signal (DX). The coupling circuit (50) couples the output pairs of each of the first and second differential pairs based on the digital data signal (DX) when the control circuit supplies drive currents to both of the first and second differential pairs, and blocks the coupling of the output pairs when supplying drive current only to one differential pair.

Example

[0083] FIG. 6 is a circuit diagram showing the configuration of a differential amplifier 100_1 as a specific example when N, which is the number of bits of the digital data signal DX in the differential amplifier 100 shown in FIG. 2, is set to 1.

[0084] In the differential amplifier 100_1 shown in FIG. 6, the digital data signal DX input to the differential amplifier 100 shown in FIG. 2 becomes a 1-bit digital data signal D0 (XD0). Here, if D0 is a positive signal, XD0 represents its complementary signal.

[0085] Based on the digital data signal D0 (XD0), the differential amplifier 100_1 amplifies and outputs, as the output voltage Vout, one of the voltage levels that interpolates (divides) the first and second level voltages IN0 and IN1 to be amplified into two.

[0086] The control circuit 30 includes two current sources 30_1 and 30_2 with one end connected to the low power supply voltage VSS, and switches 31_1, 31_2, 32_1, and 32_2 connected between the other ends of the two current sources 30_1 and 30_2 and the tails n10 and n20 of the differential pairs Df1 and Df2. The currents i1 and i2 of the two current sources 30_1 and 30_2 are the same current. Each switch is controlled to be turned on or off based on the logical value of the digital data signal D0 (XD0).

[0087] The first load circuit 10 is composed of the load circuit 10_1 in FIG. 4A and is controlled to be active or inactive based on the digital data signal D0 (XD0). The second load circuit 20 is composed of a single-stage P-channel current mirror.

[0088] Note that the load circuit 10_1 can be replaced with the load circuit 10_2 in FIG. 4B, and it may also be composed of a single-stage P-channel current mirror similar to the load circuit 20. When the first load circuit 10 has the same configuration as the load circuit 20, the digital data signal D0 (XD0) is not input.

[0089] Also, in each of the embodiments after FIG. 6, for the figures representing the first load circuit 10 as the load circuit 10_1, they are the same as those shown in FIG. 4A.

[0090] Both the load circuits 10_1 and 20 have the input ends of their current mirrors connected to the terminals (drains) of the output pairs of the transistors 12 and 22 to which the output voltage Vout is fed back, among the differential pairs Df1 and Df2 respectively. Further, the output ends of the current mirrors are connected to the terminals (drains) of the output pairs of the transistors 11 and 21 to which the first and second level voltages IN0 and IN1 are input.

[0091] Note that the configurations of the differential pairs Df1 and Df2, the auxiliary circuit 40, the coupling circuit 50, and the amplification stage 60 are the same as those shown in FIG. 2.

[0092] The auxiliary current ia of the auxiliary current source 40_1 of the auxiliary circuit 40 is set to a current equal to or less than the currents i1 and i2 of the current sources 30_1 and 30_2 of the control circuit 30.

[0093] Next, the operation of the differential amplifier 100_1 will be described with reference to the control examples shown in FIGS. 7A and 7B.

[0094] FIGS. 7A and 7B show the on / off control modes of each switch for two voltage levels j and (j + 1) (where j is an arbitrary integer equal to or greater than 0) corresponding to the logical values 0 and 1 of the digital data signal D0, respectively, the currents supplied to the differential pairs Df1 and Df2, and the relationship with the output voltage.

[0095] FIG. 7A shows a control example (control example 1) in which, when the differential amplifier 100_1 outputs voltage levels j and (j + 1) obtained by interpolating the level voltages IN0 and IN1 into two, the voltage level j is set as the voltage obtained by interpolating the level voltages IN0 and IN1 one-to-one, and the voltage level (j + 1) is set as the voltage equal to the level voltage IN1. The complementary signal XD0 of the digital data signal D0 is omitted from the description.

[0096] That is, in FIG. 7A, first, when the digital data signal D0 = 0, the switches 31_1, 32_2, 51, and 52 are turned on, and the switches 31_2, 32_1, 41, and 54 are turned off. At this time, to the tails n10 and n20 of the differential pairs Df1 and Df2, the drive current I1 = i1 the drive current I2 = i2 is supplied as the same drive current. Note that the auxiliary current ia of the auxiliary circuit 40 is not supplied.

[0097] Furthermore, by such switch control, the output pairs of the differential pairs Df1 and Df2 are connected via the coupling circuit 50. At this time, the load circuit 10_1 is controlled to be inactive, and the drive current I1 supplied to the differential pair Df1 is combined with the drive current I2 supplied to the differential pair Df2 via the coupling circuit 50 and flows to the load circuit 20. Thereby, the differential amplifier 100_1 produces an amplification effect based on the level voltages IN0, IN1 differentially input to the differential pairs Df1 and Df2 and the output voltage Vout.

[0098] On the other hand, when the digital data signal D0 = 1, as shown in FIG. 7A, the switches 31_1, 32_1, 51, and 52 are turned off, and the switches 31_2, 32_2, 41, and 54 are controlled to be in the on state. At this time, the drive current I1 = ia and the drive current I2 = (i1 + i2) are supplied to the tails n10, n20 of the differential pairs Df1 and Df2.

[0099] Furthermore, at this time, all the currents i1, i2 of the current sources 30_1, 30_2 of the control circuit 30 are supplied to the tail n20 of the differential pair Df2 and flow to the load circuit 20 via the differential pair Df2. Also, the auxiliary current ia of the auxiliary current source 40_1 of the auxiliary circuit 40 is supplied to the tail n10 of the differential pair Df1 and flows to the actively controlled load circuit 10_1 via the differential pair Df1.

[0100] Also, by the switch control shown in FIG. 7A, the output pairs of the differential pairs Df1 and Df2 are disconnected by the coupling circuit 50, so the differential pair Df1 does not contribute to the amplification effect, and only the amplification effect corresponding to the level voltage IN1 differentially input to the differential pair Df2 and the output voltage Vout occurs.

[0101] Note that the auxiliary current ia of the auxiliary current source 40_1 of the auxiliary circuit 40 only needs to be able to control the voltage fluctuation of the tail n10 of the differential pair Df1 to be substantially equal to that of the tail n20 of the differential pair Df2, and the minimum current required for that is sufficient.

[0102] ​FIG. 7B shows a control example (control example 2) in which the differential amplifier 100_1 outputs voltage levels j and (j + 1) obtained by interpolating two level voltages IN0 and IN1, where the voltage level j is set to the same voltage as the level voltage IN1, and the voltage level (j + 1) is set to the voltage obtained by interpolating the level voltages IN0 and IN1 one-to-one. Note that the description of the complementary signal XD0 of the digital data signal D0 is omitted. FIG. 7B shows the control in which the order of the levels j and (j + 1) in FIG. 7A is reversed and the logical value of the digital data signal D0 is inverted.

[0103] That is, in FIG. 7B, first, when the digital data signal D0 = 0, the switches 31_1, 32_1, 51, and 52 are controlled to be off, and the switches 31_2, 32_2, 41, and 54 are controlled to be on. At this time, the following identical drive currents are supplied to the tails n10 and n20 of the differential pairs Df1 and Df2: Drive current I1 = ia Drive current I2 = (i1 + i2) At this time, all of the currents i1 and i2 of the current sources 30_1 and 30_2 of the control circuit 30 are supplied to the tail n20 of the differential pair Df2, and the auxiliary current ia of the auxiliary current source 40_1 of the auxiliary circuit 40 is supplied to the tail n10 of the differential pair Df1.

[0104] Furthermore, by such switch control, the differential pairs Df1 and Df2 are blocked from each other's output pairs by the coupling circuit 50, and the load circuit 10_1 is controlled to be active. As a result, the differential amplifier 100_1 produces an amplification effect according to the level voltage IN1 differentially input to the differential pair Df2 and the output voltage Vout. At this time, the differential pair Df1 does not contribute to the amplification effect.

[0105] On the other hand, when the digital data signal D0 = 1, as shown in FIG. 4B, the switches 31_1, 32_2, 51, and 52 are controlled to be on, and the switches 31_2, 32_1, 41, and 53 are controlled to be off. At this time, the following drive currents are supplied to the tails n10 and n20 of the differential pairs Df1 and Df2: Drive current I1 = i1 Drive current I2 = i2 is supplied. At this time, the auxiliary current ia of the auxiliary circuit 40 is not supplied.

[0106] Also, by the switch control shown in FIG. 7B, the output pairs of the differential pairs Df1 and Df2 are connected via the coupling circuit 50, and the load circuit 10_1 is controlled to be inactive. As a result, the differential amplifier 100_1 produces an amplification effect according to the level voltages IN0, IN1 differentially input to the differential pairs Df1 and Df2 and the output voltage Vout.

[0107] Note that the switches 32_1 and 32_2 of the control circuit 30 are in the off and on states, respectively, regardless of the logical value of the digital data signal D0. Here, the switches 32_1 and 32_2 are provided for the purpose of equalizing the parasitic capacitances to the tails of the differential pairs Df1 and Df2, and the switches 32_1 and 32_2 can be omitted when the influence of the parasitic capacitances can be ignored.

[0108] FIGS. 8A and 8B are a circuit diagram of the differential amplifier 100_1 showing the on / off states of the respective switches when the differential amplifier 100_1 is controlled according to the control example 1 shown in FIG. 7A, and a diagram showing the simulation results of its operation.

[0109] Incidentally, FIG. 8A shows the on / off states of the respective switches when the digital data signal D0 = 0, and FIG. 8B shows the on / off states of the respective switches when the digital data signal D0 = 1.

[0110] First, when the digital data signal D0 = 0, as shown in FIG. 8A, the switches 31_1 and 32_2 are in the on state, so the current i1 flows through the differential pair Df1 and the current i2 (i2 = i1) flows through the differential pair Df2. At this time, as shown in FIG. 8A, the load circuit 10_1 is inactive (the switch 54 is off), and the switches 51 and 52 are in the on state, so the following output voltage Vout that interpolates the level voltages IN0 and IN1 one-to-one is output.

[0111] Vout=(IN0 + IN1) / 2 Next, when the digital data signal D0 = 1, as shown in FIG. 8B, switches 31_2 and 32_2 are turned on, so that both currents i1 and i2 are supplied only to differential pair Df2 and not to differential pair Df1. However, during this time, since switch 41 is turned on as shown in FIG. 8B, the auxiliary current ia flows through differential pair Df1. At this time, as shown in FIG. 8B, the load circuit 10_1 is active (switch 54 is on) and switches 51 and 52 are off, so that the output voltage Vout having a voltage value equal to the level voltage IN1 is output.

[0112] FIG. 8C is a waveform diagram showing an example of waveforms of the level voltages IN0 and IN1, the output voltage Vout, the tail voltage TL1 of differential pair Df1, and the tail voltage TL2 of differential pair Df2.

[0113] In FIG. 8C, the waveforms of the respective voltages are shown by taking as an example the case where the level voltage IN0 is a voltage whose voltage value transitions between 1 V (volt) and 8.5 V, and the level voltage IN1 is a voltage whose voltage value transitions between 1.2 V and 8.7 V. Here, the pair of level voltages IN0 and IN1 corresponds to digital data pieces indicating the luminance level represented by, for example, a video signal for each pixel. In FIG. 8C, an example of waveforms of the level voltages IN0 and IN1 in each of four data periods corresponding to four consecutive digital data pieces is shown. Also, the above-described 1-bit digital data signal D0 is, for example, the least significant bit of the above-described digital data piece.

[0114] At this time, when the load is the data line of the display panel, the output voltage Vout represents the level of the voltage signal at the proximal end of the data line. Note that the voltage signal at the distal end of the data line has a larger impedance (resistance and capacitance) of the data line than the voltage signal at the proximal end of the data line, so that the delay of the voltage signal also becomes larger accordingly. Also, in FIG. 8C, the digital data signal D0 is 0 in the first two consecutive data periods and 1 in the last two data periods.

[0115] As shown in FIG. 8C, the output voltage Vout changes at a predetermined slew rate with respect to the voltage changes of the input level voltages IN0 and IN1, and after the level voltages IN0 and IN1 become stable, it becomes a voltage value according to the digital data signal D0. That is, in the first and second data periods when the digital data signal D0 is 0, the output voltage Vout = 1.1V and 8.6V that interpolate the level voltages IN0 and IN1 one-to-one are respectively stabilized. On the other hand, in the third and fourth data periods when the digital data signal D0 is 1, the output voltages Vout = 1.2V and 8.7V equal to the level voltage IN1 are respectively stabilized.

[0116] Also, the tail voltages TL1 and TL2 of the differential pairs Df1 and Df2 change according to the high-potential-side voltage signal among the voltage signals supplied to the non-inverting input terminal and the inverting input terminal of each differential pair while the digital data signal D0 = 0, and are stabilized at a voltage (about 5.8V, about 0.2V) lower than the threshold voltage by about the threshold voltage from the high-potential-side voltage signal.

[0117] On the other hand, even while the digital data signal D0 = 1, the tail voltages TL1 and TL2 of the differential pairs Df1 and Df2 change in substantially the same voltage manner as in the case where the digital data signal D0 = 1.

[0118] As described above, in the differential amplifier 100_1, unlike the operations shown in FIGS. 1A to 1C that explain the operation of the conventional differential amplifier, even while outputting the output voltage Vout having the same voltage value as the input level voltage IN1 (D0 = 1), an auxiliary current ia that does not contribute to the amplification operation is supplied to the differential pair Df1 that receives the level voltage IN0.

[0119] As a result, the tail voltage TL1 of the differential pair Df1 is controlled to change in the same voltage manner as the tail voltage TL2 of the differential pair Df2. As a result, the output delay difference between adjacent gradation voltages in the data period in which the same voltage as the level voltage IN1 is output and the subsequent data period is eliminated, and it becomes possible to prevent gradation inversion when the voltage value of the output voltage Vout transitions.

Example

[0120] FIG. 9 is a circuit diagram showing the configuration of a differential amplifier 100_2 as a second embodiment when N, which is the number of bits of the digital data signal DX in the differential amplifier 100 shown in FIG. 2, is 2.

[0121] In the differential amplifier 100_2 shown in FIG. 9, the digital data signal DX input to the differential amplifier 100 shown in FIG. 2 becomes a 2-bit digital data signal D0, D1 (XD0, XD1). Note that the digital data signals D0, D1 (XD0, XD1) are the lower 2 bits of the digital data pieces corresponding to a pair of level voltages IN0 and IN1 input to the differential amplifier 100_2.

[0122] The differential amplifier 100_2 amplifies and outputs, as an output voltage Vout, one of the voltage levels obtained by interpolating four levels of the first and second level voltages IN0 and IN1 according to the 2-bit digital data signals D0 and D1 (XD0, XD1).

[0123] The control circuit 30 shown in FIG. 9 includes three current sources 30_1, 30_2, 30_3 having one end connected to the low-level power supply voltage VSS, and switches 31_1, 31_2, 32_1, 32_2, 33_1, 33_2. As shown in FIG. 9, these switches 31_1, 31_2, 32_1, 32_2, 33_1, 33_2 are connected between the other ends of the current sources 30_1, 30_2, and 30_3 and the differential pairs Df1 and Df2. Each switch is controlled to be turned on or off based on the logical values of the digital data signals D1, D0 (XD1, XD0).

[0124] The current ratios of the currents i1, i2, and i3 respectively generated by the current sources 30_1, 30_2, and 30_3 are i1:i2:i3 = 1:1:2 That is.

[0125] Note that the differential pairs Df1 and Df2, the first and second load circuits (10_1, 20), the auxiliary circuit 40, the coupling circuit 50, and the amplification stage 60 shown in FIG. 9 are the same as those shown in FIG. 6. At this time, the auxiliary current ia generated by the auxiliary current source 40_1 of the auxiliary circuit 40 is set to be equal to or less than the currents i1 and i2 generated by the current sources 30_1 and 30_2 of the control circuit 30.

[0126] Next, the operation of the differential amplifier 100_2 in FIG. 9 will be described with reference to the control example shown in FIG. 10.

[0127] FIG. 10 is a diagram showing the on / off control modes of each switch for each of the four voltage levels j, (j + 1), (j + 2), (j + 3) corresponding to the logical values of the 2-bit digital data signals D1 and D0, the currents supplied to the differential pairs Df1 and Df2, and the output voltage.

[0128] FIG. 10 is a diagram showing a control example when the differential amplifier 100_2 outputs the voltage levels j to (j + 3) obtained by interpolating the level voltages IN0 and IN1 into four levels.

[0129] That is, in FIG. 10, the voltage level j is the voltage obtained by interpolating the level voltages IN0 and IN1 at a ratio of 1:3, the voltage level (j + 1) is the voltage obtained by interpolating IN0 and IN1 at a ratio of 1:1, the voltage level (j + 2) is the voltage obtained by interpolating IN0 and IN1 at a ratio of 3:1, and the voltage level (j + 3) is the voltage equal to IN1. A control example in this case is shown.

[0130] The voltage levels j, (j + 1), (j + 2), and (j + 3) respectively correspond to (0, 0), (0, 1), (1, 0), and (1, 1) as the digital data signals (D1, D0). Note that the complementary signals of each digital data signal are not described.

[0131] As shown in Fig. 10, when the digital data signals (D1, D0) are (0, 0), switches 31_1, 32_2, 33_1, 51 and 52 are controlled to be in the on state, and switches 31_2, 32_1, 33_2, 41 and 54 are controlled to be in the off state. At this time, currents with a current ratio of 3 to 1, such as drive currents I1 = (i1 + i3) and I2 = i2, are respectively supplied to the tails n10, n20 of differential pairs Df1 and Df2. At this time, the auxiliary current ia of the auxiliary circuit 40 is not supplied, the output pairs of the differential pairs Df1 and Df2 are connected via the coupling circuit 50, and the load circuit 10_1 is made inactive. As a result, the differential amplifier 100_2 exhibits an amplification effect corresponding to the level voltages IN0, IN1 input to the differential pairs Df1 and Df2, the output voltage Vout, and the ratio of the drive currents I1, I2 driving the differential pairs Df1 and Df2.

[0132] Therefore, the differential amplifier 100_2 outputs an output voltage Vout corresponding to the voltages generated in the differential pairs Df1 and Df2 by the drive currents I1 = (i1 + i3) and I2 = i2 flowing through the differential pairs Df1 and Df2, Vout = (3·IN0 + IN1) / 4 as output.

[0133] When the digital data signals (D1, D0) are (0, 1), switches 31_1, 32_1, 33_2, 51 and 52 are controlled to be in the on state, and switches 31_2, 32_2, 33_1, 41 and 54 are controlled to be in the off state. At this time, currents with a current ratio of 1 to 1, such as drive currents I1 = (i1 + i2) and I2 = i3, are respectively supplied to the tails n10, n20 of the differential pairs Df1 and Df2. At this time, the auxiliary current ia of the auxiliary circuit 40 is not supplied, the differential pairs Df1 and Df2 are connected via the coupling circuit 50 at their output pairs, and the load circuit 10_1 is made inactive. As a result, the differential amplifier 100_2 exhibits an amplification effect corresponding to the level voltages IN0, IN1 differentially input to the differential pairs Df1 and Df2, the output voltage Vout, and the ratio of the drive currents I1, I2 driving the differential pairs Df1 and Df2.

[0134] Therefore, differential amplifier 100_2 outputs an output voltage Vout corresponding to the voltages generated in differential pairs Df1 and Df2 by drive currents I1 = (i1 + i2) and I2 = i3 flowing through differential pairs Df1 and Df2, Vout = (IN0 + IN1) / 2 as follows.

[0135] When the digital data signals (D1, D0) are (1, 0), switches 31_1, 32_2, 33_2, 51, and 52 are controlled to be in the ON state, and switches 31_2, 32_1, 33_1, 41, and 53 are controlled to be in the OFF state. At this time, currents with a current ratio of 1 to 3, such as drive currents I1 = i1 and I2 = (i2 + i3), are supplied to tails n10 and n20 of differential pairs Df1 and Df2, respectively. At this time, the auxiliary current ia of the auxiliary circuit 40 is not supplied, the output pairs of differential pairs Df1 and Df2 are connected via the coupling circuit 50, and the load circuit 10_1 is deactivated. As a result, an amplification effect corresponding to the level voltages IN0 and IN1 differentially input to differential pairs Df1 and Df2, the output voltage Vout, and the ratio of the drive currents I1 and I2 driving differential pairs Df1 and Df2 occurs in differential amplifier 100_2.

[0136] Therefore, differential amplifier 100_2 outputs an output voltage Vout corresponding to the voltages generated in differential pairs Df1 and Df2 by drive currents I1 = i1 and I2 = (i2 + i3) flowing through differential pairs Df1 and Df2, Vout = (IN0 + 3·IN1) / 4 as follows.

[0137] When the digital data signals (D1, D0) are (1, 1), switches 31_2, 32_2, 33_2, 41 and 54 are controlled to be in the on state, and switches 31_1, 32_1, 33_1, 51 and 52 are controlled to be in the off state. At this time, drive currents I1 = ia and I2 = (i1 + i2 + i3) are supplied to the tails n10 and n20 of differential pairs Df1 and Df2. Also, all of the currents i1, i2, and i3 generated by current sources 30_1, 30_2, and 30_3 of control circuit 30 are supplied to the tail n20 of differential pair Df2, and the auxiliary current ia of auxiliary current source 40_1 of auxiliary circuit 40 is supplied to the tail n10 of differential pair Df1 and flows into the activated load circuit 10_1. Furthermore, according to such switch control, since the output pairs of differential pairs Df1 and Df2 are blocked by coupling circuit 50, the amplification action by differential pair Df1 is removed from differential amplifier 100_2, and only the amplification action corresponding to the level voltage IN1 input to differential pair Df2 and the output voltage Vout occurs.

[0138] Therefore, differential amplifier 100_2 outputs the output voltage Vout corresponding to the voltage generated in differential pair Df2 by the drive current I2 = (i1 + i2 + i3) flowing through differential pair Df2, Vout = IN1 as the output.

[0139] Note that the auxiliary current ia generated by auxiliary current source 40_1 may be, for example, equal to or less than the current i1 (or i2) of current source 30_1 (or 30_2). That is, as the auxiliary current ia, it may be the minimum current that can make the voltage fluctuation of the tail n10 of differential pair Df1 approximately equal to the voltage fluctuation generated at the tail n20 of differential pair Df2.

[0140] As described above, even in the differential amplifier 100_2 shown in FIG. 9, when outputting an output voltage Vout having the same voltage value as the first level voltage IN1, an auxiliary current ia that does not contribute to the amplification action is supplied to the differential pair Df1 to which the second level voltage IN0 is input. Thereby, control is performed so that voltage changes between the tail voltage TL1 of the differential pair Df1 and the tail voltage TL2 of the differential pair Df2 become equal. As a result, generation of an output delay difference between adjacent gradation voltages in a data period in which an output voltage Vout having the same voltage value as the level voltage IN1 is output and a data period subsequent thereto is prevented. As a result, it is possible to realize driving in which gradation inversion does not occur even when the voltage value transitions when the input voltage changes.

[0141] Needless to say, the control similar to that of FIG. 10 is also applicable to the control in which the voltage level j corresponding to the digital data signals (D1, D0) = (0, 0) is set to the same voltage value as the level voltage IN1. Specifically, it is control in which the order of levels j to (j + 3) in FIG. 10 is reversed and the logical values of the digital data signals D1 and D0 are inverted.

Embodiment

[0142] FIG. 11 is a circuit diagram showing a configuration of a differential amplifier 100_3 as a third embodiment in which the first and second load circuits 10 and 20 included in the differential amplifier 100 shown in FIG. 2 are replaced with a low-voltage cascode current mirror.

[0143] In FIG. 11, since the configurations other than the load circuits 10A_1, 20A and the circuit 27A constituting the low-voltage cascode current mirror are the same as those in FIG. 2, the load circuits 10A_1, 20A and the circuit 27A will be described below.

[0144] In FIG. 11, the load circuit 10A_1 includes a P-channel transistor pair (13, 14) in which a first terminal (source) is connected to a high-level power supply voltage VDD via a switch 54, a second terminal (drain) is connected to the tails n11 and n12 of the output pair of the differential pair Df1, respectively, and control terminals (gates) are commonly connected.

[0145] The load circuit 20A includes a P-channel transistor pair (23, 24) in which the first terminal (source) is connected to the high-level power supply voltage VDD, the second terminal (drain) is connected to the nodes n21 and n22 of the output pair of the differential pair Df2, respectively, and the control terminals (gates) are commonly connected.

[0146] Furthermore, the circuit 27A includes a P-channel transistor pair (25, 26) connected between the nodes n21 and n22 of the output pair of the differential pair Df2 and the amplification stage 60. Each of the first terminals (sources) of the transistor pair (25, 26) is connected to the nodes n21 and n22, respectively, and each of the second terminals (drains) is connected to the amplification stage 60 via the nodes nn1 and nn2. And the second terminal (drain) of the transistor 26 among the transistor pair (25, 26) is connected to the common control terminal (gate) of the transistor pair (13, 14) of the load circuit 10A_1, and is also connected to the common control terminal (gate) of the transistor pair (23, 24) of the load circuit 20A. A bias voltage BP is commonly applied to the control terminals (gates) of each transistor of the transistor pair (25, 26).

[0147] The transistor pair (25, 26) of these circuits 27A and the transistor pair (23, 24) of the load circuit 20A constitute a two-stage vertical stacked P-channel low-voltage cascode current mirror. Also, the transistor pair (25, 26) and the transistor pair (13, 14) of the load circuit 10A_1 also constitute a two-stage vertical stacked P-channel low-voltage cascode current mirror, which operates when the switches 51 and 52 of the coupling circuit 50 are in the on state.

[0148] Note that in FIG. 11, the transistor pair (25, 26) shows a configuration shared by the load circuits 10A_1 and 20A in response to device reduction.

[0149] As described above, in the differential amplifier 100_3 shown in FIG. 11, the load circuits 10A_1 and 20A form the first stage of a P-channel low-voltage cascode current mirror connected to the amplification stage 60.

[0150] Note that when the load circuit 10A_1 controls the switch 54 in the same manner as in FIGS. 7A, 7B, and 10, since it is not involved in the amplification operation, it may be replaced with the load circuit 10_1. In this case, at least the load circuit 20A and the circuit 27A may form a low-voltage cascode current mirror. On the other hand, when the output voltage Vout outputs the interpolation voltage, if the switch 54 is turned on and the load circuit 10A_1 is activated and used, the load circuit 10A_1 is involved in the amplification operation together with the load circuit 20A. Therefore, both the load circuit 10A_1 and the load circuit 20A are configured as the first stage of the low-voltage cascode current mirror.

Embodiment

[0151] FIG. 12 is a circuit diagram showing the configuration of a differential amplifier 100_4 as a fourth embodiment.

[0152] Note that the differential amplifier 100_4 is a Rail-to-Rail type differential amplifier capable of outputting an output voltage Vout in an output voltage range substantially close to the power supply voltage range VDD~VSS, and is an extension of the differential amplifier 100 shown in FIG. 2 to a configuration including an N-channel type differential pair and a P-channel type differential pair.

[0153] That is, as shown in FIG. 12, the differential amplifier 100_4 includes an N-type differential stage NDF, a P-type differential stage PDF, floating current sources 61 and 62, P-channel type output transistors 63 and N-channel type output transistors 64.

[0154] The N-type differential stage NDF is a circuit within the region surrounded by the dashed line in FIG. 11, that is, the amplification stage 60 is omitted from the differential amplifier 100_3. Similarly, as the N-type differential stage NDF, a configuration in which the amplification stage 60 is omitted from each of the differential amplifiers in FIGS. 2, 6, and 9 can also be applied. In that case, the output nodes n21 and n22 of the differential pair Df2 are connected to the nodes nn1 and nn2 in FIG. 12.

[0155] The P-type differential stage PDF is in a form of opposite conductivity type to the N-type differential stage NDF, and realizes the functions by the load circuits 10A_1, 20A, differential pairs Df1 and Df2, circuit 27A, control circuit 30, auxiliary circuit 40 and coupling circuit 50 shown in FIG. 11.

[0156] FIG. 13 is a circuit diagram showing the configuration of the P-type differential stage PDF.

[0157] As shown in FIG. 13, the P-type differential stage PDF includes load circuits 110A, 120A, differential pairs Df1a and Df2a, circuit 127A, control circuit 130, auxiliary circuit 140 and coupling circuit 150, which respectively correspond to the load circuits 10A_1, 20A, differential pairs Df1 and Df2, circuit 27A, control circuit 30, auxiliary circuit 40 and coupling circuit 50 shown in FIG. 11.

[0158] That is, the load circuit 110A is composed of N-channel transistors 113 and 114 whose control terminals (gates) are commonly connected to each other, and a switch 154 connected between the common source of the transistors 113 and 114 and the low-level power supply voltage VSS. The load circuit 120A is composed of N-channel transistors 123 and 124 whose control terminals (gates) are commonly connected to each other. The switch 154 of the load circuit 110A is controlled to be turned on and off based on the digital data signal DX, and is inactive when off and active when on. The first differential pair Df1a and the second differential pair Df2a are each composed of a P-channel transistor pair, and the transistor pair (125, 126) constituting the circuit 127A is composed of an N-channel transistor pair to which a bias voltage BN is applied to their control terminals (gates).

[0159] Here, the output pair of the differential pair Df2a, that is, the second terminals (drains) of the transistors 121 and 122, are connected to the second terminals (drains) of the transistors 123 and 124 of the load circuit 120A, respectively, together with the first terminals (sources) of the transistor pairs (125, 126) as shown in FIG. 13. Further, the second terminal (drain) of the transistor 126 among the transistor pair (125, 126) is connected to the control terminals (gates) of the transistors 113, 114, 123, and 124 of the load circuits 110A and 120A. At this time, the transistor pair (125, 126) and the transistor pair (123, 124) of the load circuit 120A constitute an N-channel low-voltage cascode current mirror in a two-stage vertical stacking configuration. The transistor pair (125, 126) and the transistor pair (113, 114) of the load circuit 110 also constitute an N-channel low-voltage cascode current mirror in a two-stage vertical stacking configuration, and operate when the switches 151 and 152 of the coupling circuit 150 are in the on state.

[0160] The control circuit 130 includes (N + 1) current sources 130_1 to 130_(N + 1) consisting of a current source with a current ratio of 1 and N current sources with a current ratio of 2 to the power of k (k is an integer from 0 to N - 1), similar to the control circuit 30, and a switch group 131 that supplies the current of each of the current sources 130_1 to 130_(N + 1) to either one of the tails of the differential pairs Df1a and Df2a. The switch group 131 selects any one of 2 to the power of N combinations by the current sources 130_1 to 130_(N + 1) based on the N-bit digital data signal DX, and supplies the total current of each of the current sources in the selected combination as a drive current to each of the tails of the differential pairs Df1a and Df2a.

[0161] The auxiliary circuit 140 has an auxiliary current source 140_1 and a switch 141 connected in series between the tail of the differential pair Df1a and the high-level power supply voltage VDD. The auxiliary circuit 140 receives the N-bit digital data signal DX, and based on the N-bit digital data signal DX, controls to supply the auxiliary current ia that does not contribute to the amplification effect to the differential pair Df1a, or to cut off the supply of the auxiliary current ia to the differential pair Df1a.

[0162] The coupling circuit 150 is composed of switches 151 and 152 that control the connection between the output pairs of differential pairs Df1a and Df2a respectively, and controls the coupling between the output pair of differential pair Df1a and the output pair of differential pair Df2a based on the N-bit digital data signal DX.

[0163] Incidentally, the load circuit 110A, the control circuit 130, the auxiliary circuit 140, and the coupling circuit 150 perform the same operations as the load circuit 10A_1, the control circuit 30, the auxiliary circuit 40, and the coupling circuit 50 of the differential amplifier 100_3 in FIG. 11 described above within the P-type differential stage PDF.

[0164] Here, in the differential amplifier 100_4 shown in FIG. 12, the second terminal (drain) of transistor 25 of the transistor pair (25, 26) that constitutes the second stage of the P-channel low-voltage cascode current mirror included in the N-type differential stage NDF is connected to one end of the floating current source 61 and the gate of the output transistor 63 via the node nn1. Also, the second terminal (drain) of transistor 26 of the transistor pair (25, 26) is connected to one end of the floating current source 62 via the node nn2.

[0165] Also, in the differential amplifier 100_4, the second terminal (drain) of transistor 125 of the transistor pair (125, 126) that constitutes the second stage of the N-channel low-voltage cascode current mirror included in the P-type differential stage PDF is connected to the other end of the floating current source 61 and the gate of the output transistor 64 via the node pn1. Also, the second terminal (drain) of transistor 126 of the transistor pair (125, 126) is connected to the other end of the floating current source 62 via the node pn2.

[0166] The floating current source 61 is connected between the second terminal (drain) of transistor 25 of the N-type differential stage NDF, which serves as the output end of the low-voltage cascode current mirror respectively, and the second terminal (drain) of transistor 125 of the P-type differential stage PDF, and transfers the current between these transistors 25 and 125.

[0167] The floating current source 62 is connected between the second terminals (drains) of the transistors 26 of the N-type differential stage NDF and the transistors 126 of the P-type differential stage PDF, each of which serves as the input terminal of the low-voltage cascode current mirror, and transfers the current between these transistors 26 and 126.

[0168] The high-level power supply voltage VDDH is applied to the first terminal (source) of the output transistor 63, and the second terminal (drain) is connected to the output terminal T3. The low-level power supply voltage VSSH is applied to the first terminal (source) of the output transistor 64, and the second terminal (drain) is connected to the output terminal T3. In the differential amplifier 100_4, similar to the differential amplifiers 100_1 to 100_3 described above, the voltage generated at the output terminal T3 is output as the output voltage Vout. Also, in the differential amplifier 100_4, this output voltage Vout is supplied to each of the N-type differential stage NDF and the P-type differential stage PDF as the feedback voltage.

[0169] With the configuration shown in FIG. 12, the differential amplifier 100_4 constitutes a Rail-to-Rail type differential amplifier capable of outputting an output voltage Vout in an output voltage range that is approximately close to the power supply voltage range VDD to VSS.

Example

[0170] FIG. 14 is a block diagram showing the configuration of a display device 500 including a display driver (data driver) as a fifth example, including the differential amplifier according to the present invention.

[0171] The display device 500 includes a display panel 510, a scanning driver 520, and a data driver 530.

[0172] The display panel 510 is composed of, for example, a liquid crystal or an organic EL panel, and includes m (m is a natural number of 2 or more) horizontal scanning lines GL1 to GLm extending in the horizontal direction of the two-dimensional screen and n (n is a natural number of 2 or more) data lines DL1 to DLn extending in the vertical direction of the two-dimensional screen. Display cells responsible for pixels are formed at each intersection of the horizontal scanning lines and the data lines.

[0173] Based on the scanning timing signal supplied from a display controller (not shown), the scanning driver 520 sequentially applies horizontal scanning pulses to each of the horizontal scanning lines GL1 to GLm of the display panel 510. In recent years, the scanning driver 520 has mainly adopted a thin film transistor circuit configuration formed integrally with the display panel 510. In addition, in small display devices such as tablets and smartphones, the display controller and the power supply circuit are also built into the data driver 530. Here, the description of the display controller and the power supply circuit is omitted.

[0174] The data driver 530 receives a clock signal CLK, a start pulse signal STA, a video digital signal DVS, and various control signals CNT from the display controller. Thereby, the data driver 530 generates gradation voltage signals G1 to Gn having voltage values corresponding to the luminance levels indicated by the video digital signal DVS, and supplies each of them to the data lines DL1 to DLn of the display panel 510.

[0175] The data driver 530 is formed on a semiconductor IC chip, and includes a shift register 91, a data register latch 92, n level shifters (SHF) 93, a reference voltage generation circuit 94, n decoders 95, a bias voltage generation circuit 96, and n differential amplifiers 100.

[0176] In response to the start pulse signal STA, the shift register 91 generates a plurality of latch timing signals for selecting latches in synchronization with the clock signal CLK, and supplies them to the data register latch 92.

[0177] At the timing of the latch timing signal supplied from the shift register 91, the data register latch 92 takes in digital data pieces representing the luminance levels of each pixel included in the video digital signal in units of n, and supplies n digital data signals representing them to the n level shifters 93 respectively.

[0178] Each level shifter 93 performs a level shift process to increase the signal amplitude on the digital data signal it receives, and generates a high-voltage M-bit (where M is an integer of 2 or more) digital data signal. This signal is supplied to the decoder 95 of the level shifter 93.

[0179] Each level shifter 93 supplies the differential amplifier 100 with the digital data signal DX of the lower N bits among the M bits it generates, and supplies the decoder 95 with the digital data signals of the remaining upper bit groups among the M bits. That is, the n level shifters 93 supply the n differential amplifiers 100 with n digital data signals each consisting of the lower 2 bits of the n high-voltage digital data signals, and supply the n decoders 95 with n upper digital data signals each consisting of the upper bit groups of the n high-voltage digital data signals. When the digital data signal DX of the lower N bits is a signal group of multiple bits, arithmetic processing may be performed at the stage of the low-voltage digital data signal before the level shifter 93, and a signal subjected to level conversion as necessary may be supplied to the differential amplifier 100.

[0180] The reference voltage generation circuit 94 receives the high-level power supply voltage VGH and the low-level power supply voltage VGL, generates a group of reference voltages (V0 to Vx) with different voltage values from each other by, for example, dividing the voltage between the two voltages by resistance division, and supplies each of the n decoders 95.

[0181] Each decoder 95 selects two reference voltages from the above-described group of reference voltages based on the upper digital data signal supplied from the level shifter 93, and supplies them to the differential amplifier 100 as reference voltages IN0 and IN1, respectively.

[0182] The differential amplifier 100 is provided corresponding to each of the n outputs of the data driver 530. Each of the differential amplifiers 100 generates an amplified output voltage Vout based on two reference voltages IN0 and IN1 selected by each decoder 95 and a separately supplied lower N-bit digital data signal. At this time, the n output voltages Vout generated by each differential amplifier 100 are supplied as n gradation voltage signals S1 to Sn to the data lines DL1 to DLn of the display panel 510.

[0183] The bias voltage generation circuit 96 generates a plurality of bias voltages for setting the operating current of the current source that operates each of the differential amplifiers 100 and supplies them to each of the differential amplifiers 100.

[0184] Here, each of the differential amplifiers 100 shown in FIG. 11 is composed of, for example, the circuits shown in FIGS. 2, 6, 9, 11, or 12. At this time, the bias voltage BP used in the P-channel low-voltage cascode current mirror (23 to 26) shown in FIG. 11 and the bias voltage BN used in the N-channel low-voltage cascode current mirror (123 to 126) shown in FIG. 10 are also generated by the bias voltage generation circuit 96.

[0185] Therefore, by adopting the circuits shown in FIGS. 2, 6, 9, 11, or 12 as the differential amplifiers 100 provided for each output channel of the data driver 530, a data driver that does not cause gradation inversion during voltage transition of the gradation voltage signal can be realized.

Example

[0186] FIGS. 15A and 15B are diagrams showing a specification example as a sixth example in the differential amplifier 100 included in the data driver 530 shown in FIG. 14.

[0187] FIG. 15A is a specification example when N = 1.

[0188] According to the specification shown in FIG. 15A, the digital data signal D0 for the least significant 1 bit in the above-described M-bit digital data signal (the complementary signal is omitted) is supplied to the differential amplifier 100. At this time, two level voltages selected by the decoder 95 based on the other upper bit group are supplied to the differential amplifier 100 as (IN0, IN1).

[0189] FIG. 15A shows eight gradation levels from an arbitrary gradation level j to (j + 8). These eight gradation levels correspond to the logical values of the lower 3 bits (D2, D1, D0) of the digital data signal. Vref is a reference voltage generated by the reference voltage generation circuit 94 and supplied to each decoder 95.

[0190] Also, in FIG. 15A, V0, V2, V4, V6, V8 are supplied as the reference voltage Vref at every two gradation levels. Note that the two level voltages (IN0, IN1) selected by the decoder 95 by the upper bit group of the digital data signal D1 or higher are the same in every two consecutive gradation levels, and (IN0, IN1) are (V0, V2), (V2, V4), (V4, V6), (V6, V8) at every two gradation levels, and each is supplied to the differential amplifier 100 according to the digital data signal.

[0191] Also, in FIG. 15A, (pI1, pI2) is the drive current ratio of the first and second differential pairs controlled by the control circuit 30 of the differential amplifier 100 by the digital data signal D0 (N = 1) of the least significant 1 bit of the digital data signal.

[0192] For example, when the gradation level is j, D0 is set to 0, and the drive current ratio (pI1, pI2) of the first and second differential pairs is controlled to (1, 1). As a result, the differential amplifier 100 outputs an output voltage Vout = V1 that interpolates one-to-one with respect to the two level voltages (IN0, IN1) = (V0, V2). Also, when the gradation level is (j + 1), D0 is set to 1, and the drive current ratio (pI1, pI2) of the first and second differential pairs is controlled to (0, 2). As a result, the differential amplifier 100 outputs an output voltage Vout = V2 that is the same as the level voltage IN1 with respect to the two level voltages (IN0, IN1) = (V0, V2). These two gradation levels j and (j + 1) can be realized by the control of FIG. 7A.

[0193] By repeating such two gradation levels j and (j + 1) every two levels, gradation voltages V1 to V8 corresponding to gradation levels j to (j + 8) are output from the differential amplifier 100 as the output voltage Vout. Needless to say, it is possible to expand to multiple gradations by sequentially assigning the specifications of FIG. 15A every eight gradations.

[0194] In the specification of FIG. 15A, the selection state where the output voltage Vout is equal to the level voltage IN1 occurs every two gradations. At this time, no current is supplied from the control circuit 30 to the first differential pair of the differential amplifier 100, but in the differential amplifier 100 of the present invention, an auxiliary current that does not contribute to the amplification action is supplied from the auxiliary circuit 40 to the first differential pair. Thereby, the tail potential of the first differential pair is controlled to the same voltage fluctuation as the tail potential of the second differential pair that causes the amplification action. As a result, no difference occurs in the output delay of each of the continuous voltage levels, and a voltage output that suppresses gradation inversion becomes possible.

[0195] FIG. 15B is an example of a specification when N = 2.

[0196] According to the specifications shown in Fig. 15B, the digital data signals D1 and D0 for the lower 2 bits in the above-mentioned M-bit digital data signal (complementary signals are omitted) are supplied to the differential amplifier 100. At this time, two level voltages selected by the decoder 95 based on the other upper bit group are supplied to the differential amplifier 100 as (IN0, IN1).

[0197] Fig. 15B shows 8 gradation levels from an arbitrary gradation level j to (j + 8). These 8 gradation levels correspond to the logical values of the lower 3 bits (D2, D1, D0) of the digital data signal. Vref is a reference voltage generated by the reference voltage generation circuit 94 and supplied to each decoder 95.

[0198] Also, in Fig. 15B, V0, V4, and V8 every 4 gradation levels are supplied as the reference voltage Vref. Note that the two level voltages (IN0, IN1) selected by the decoder 95 by the upper bit group of the digital data signal D2 and above are the same in 4 consecutive gradation levels, and (IN0, IN1) = (V0, V4), (V4, V8) every 4 gradation levels, and each is supplied to the differential amplifier 100.

[0199] Also, in Fig. 15B, (pI1, pI2) is the drive current ratio of the first and second differential pairs controlled by the control circuit 30 of the differential amplifier 100 by the digital data signals D1 and D0 (N = 2) of the lower 2 bits of the digital data signal.

[0200] For example, when the gradation level is j, (D1, D0) = (0, 0), and the drive current ratios (pI1, pI2) of the first and second differential pairs are controlled to (3, 1). Thereby, the differential amplifier 100 outputs an output voltage Vout = V1 that interpolates at a ratio of 1 to 3 with respect to the two level voltages (IN0, IN1) = (V0, V4). Also, when the gradation level is (j + 1), (D1, D0) = (0, 1), and the drive current ratios (pI1, pI2) of the first and second differential pairs are controlled to (2, 2). Thereby, the differential amplifier 100 outputs an output voltage Vout = V2 that interpolates at a ratio of 1 to 1 with respect to the two level voltages (IN0, IN1) = (V0, V4). Also, when the gradation level is (j + 2), (D1, D0) = (1, 0), and the drive current ratios (pI1, pI2) of the first and second differential pairs are controlled to (1, 3). Thereby, the differential amplifier 100 outputs an output voltage Vout = V3 that interpolates at a ratio of 3 to 1 with respect to the two level voltages (IN0, IN1) = (V0, V4). Also, when the gradation level is (j + 3), (D1, D0) = (1, 1), and the drive current ratios (pI1, pI2) of the first and second differential pairs are controlled to (0, 4). Thereby, the differential amplifier 100 outputs an output voltage Vout = V4 having the same voltage value as the level voltage IN1 with respect to the two level voltages (IN0, IN1) = (V0, V4). These four gradation levels j to (j + 3) can be realized by the control of FIG. 10.

[0201] By repeating the operations of such four gradation levels j to (j + 3) every four levels, the gradation voltages V1 to V8 corresponding to the gradation levels j to (j + 8) are output from the differential amplifier 100 as the output voltage Vout. Furthermore, it goes without saying that it is possible to expand to multi-gradation by sequentially assigning the specifications of FIG. 15B every eight gradations.

[0202] In the specification of FIG. 15B, the selection state where the output voltage Vout is equal to IN1 occurs every four gradations. At this time, no current is supplied from the control circuit 30 to the first differential pair of the differential amplifier 100, but in the differential amplifier 100 of the present invention, an auxiliary current that does not contribute to the amplification action is supplied from the auxiliary circuit 40 to the first differential pair. As a result, the tail potential of the first differential pair is controlled to have the same voltage fluctuation as the tail potential of the second differential pair that causes the amplification action. As a result, there is no difference in the output delay for each of the continuous voltage levels, and a voltage output that suppresses gradation inversion is possible.

Explanation of Reference Numerals

[0203] 10, 20 Load circuit 30 Control circuit 40 Auxiliary circuit 50 Coupling circuit 60 Amplification stage 100, 100_1 to 100_4 Differential amplifier Df1, Df1a, Df2, Df2a Differential pair

Claims

1. A differential amplifier that receives a digital data signal of N (where N is an integer of 1 or more) bits together with first and second voltages having different voltage values, and amplifies and outputs, as an output voltage, one voltage based on the digital data signal among 2 to the power of N voltages obtained by interpolating the first and second voltages into 2 to the power of N voltages, comprising: a first differential pair that differentially inputs the first voltage and the output voltage; a second differential pair that differentially inputs the second voltage and the output voltage; a control circuit that supplies a drive current to one of the first differential pair and the second differential pair, or both the first differential pair and the second differential pair, based on the digital data signal; an amplification stage that receives the voltage of each output pair of the first differential pair and the second differential pair, or one of the output pairs, and converts this into the output voltage; an auxiliary circuit that supplies a predetermined auxiliary current to the other differential pair of the first differential pair and the second differential pair when the control circuit supplies the drive current only to the one differential pair based on the digital data signal; a coupling circuit that couples the output pairs of the first differential pair and the second differential pair to each other when the control circuit supplies the drive current to both the first differential pair and the second differential pair based on the digital data signal, and disconnects the coupling of the output pairs when the drive current is supplied only to the one differential pair. A differential amplifier characterized by comprising:

2. When the digital data signal indicates that the output voltage having a voltage value different from the first and second voltages is to be output, the auxiliary circuit cuts off the supply of the auxiliary current to the other differential pair, and the coupling circuit connects the output pairs of the first differential pair and the second differential pair to each other. When the digital data signal indicates that the output voltage having a voltage value equal to the first or second voltage is to be output, the control circuit supplies the drive current only to the one differential pair, the auxiliary circuit supplies the auxiliary current to the other differential pair, and the coupling circuit disconnects the connection between the output pairs of the first differential pair and the second differential pair. The differential amplifier according to Claim 1, characterized in that:

3. The differential amplifier according to Claim 1, further comprising first and second load circuits individually connected to the output pairs of the first and second differential pairs, respectively.

4. comprising first and second load circuits connected to output pairs of the first and second differential pairs; when the control circuit supplies the drive current to both the first differential pair and the second differential pair, the first load circuit is deactivated so that the drive current flows to the second load circuit connected to the output pair of each of the first differential pair and the second differential pair coupled via the coupling circuit; when the control circuit supplies the drive current to only one of the differential pairs, the drive current flows to the second load circuit connected to the one differential pair, the first load circuit is activated, and the predetermined auxiliary current flows to the second load circuit connected to the other differential pair, the differential amplifier according to claim 1, characterized in that.

5. The control circuit has a plurality of current sources each having a predetermined current ratio, and based on the digital data signal, selects any one of combinations of 2 to the Nth power of current ratios by the plurality of current sources, and the combined current of each of the selected combination of current sources is used as the drive current and supplied to a tail node of one or both of the first differential pair and the second differential pair. The differential amplifier according to any one of claims 1 to 4, characterized in that.

6. The control circuit has (N + 1) current sources including a current source having a current ratio of 1 and N current sources having a current ratio of 2 to the kth power (k is an integer from 0 to N - 1), and based on the digital data signal, selects any one of 2 to the Nth power of combinations by the (N + 1) current sources, and the combined current of each of the selected combination of current sources is used as the drive current and supplied to a tail node of one or both of the first differential pair and the second differential pair. The differential amplifier according to any one of claims 1 to 4, characterized in that.

7. The 2 to the Nth power of combinations of the current ratios of the drive currents supplied to each of the first differential pair and the second differential pair correspond to 2 to the Nth power of voltages obtained by interpolating the first and second voltages into 2 to the Nth power and adding 1 to each of the 2 to the Nth power of voltages, and consecutive 2 to the Nth power of voltages; The differential amplifier according to claim 5, characterized in that, based on the digital data signal, the output voltage having one of the 2 to the Nth power of voltages is amplified and output from the amplification stage.

8. The differential amplifier according to claim 6, characterized in that N is 1.

9. The differential amplifier according to claim 6, wherein N is 2. **Claim 10** A digital-to-analog conversion circuit that converts an M-bit (M is an integer of 2 or more) digital data signal into an output voltage having an analog voltage value, a voltage generation circuit that generates a plurality of voltages having different voltage values; receives a higher-order digital data signal composed of higher-order bits excluding the lower N (N is an integer of 1 or more) bits in the M-bit digital data signal, and based on the higher-order digital data signal, selects first and second voltages having different voltage values from the plurality of voltages a decoder; a differential amplifier according to any one of claims 1 to 4, and wherein the differential amplifier receives the first and second voltages selected by the decoder and a digital data signal composed of the lower N bits in the M-bit digital data signal, and amplifies and outputs the output voltage having an analog voltage value corresponding to the M-bit digital data signal. A digital-to-analog conversion circuit characterized by that. **Claim 11** A display driver having a plurality of output channels that output a plurality of gradation voltage signals based on a video signal, A display driver characterized in that the differential amplifier according to claims 1 to 4 or the digital-to-analog conversion circuit according to claim 10 is provided for each of the plurality of output channels.

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