Circuit arrangement and display system

Abstract

To provide a circuit arrangement that can maintain the continuity of synchronization in switching of images.SOLUTION: In a vertical blanking period of first image data IMA, a control circuit 140 controls a first selection circuit 150 to switch from the first image data IMA to image data for switching IMX. In a switching period TIMX during which the image data for switching IMX is selected by the first selection circuit 150, the control circuit 140 controls an output circuit 130 to output output image data IMQ at a frame rate different from that of second image data IMB. In an overlapping period of a vertical blanking period of the image data for switching IMX and a vertical blanking period of the second image data IMB, the control circuit 140 controls the first selection circuit 150 to switch from the image data for switching IMX to the second image data IMB.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a circuit device, a display system, and the like.

Background Art

[0002] Patent Document 1 discloses a display system including a switching circuit that switches asynchronous video signals. The switching circuit outputs a video signal synchronized with a vertical synchronization signal VS3 for a certain period after power-on, and outputs a composite video signal synchronized with a vertical synchronization signal VS4 after the switching signal is switched.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In Patent Document 1, since the vertical synchronization signal VS3 and the vertical synchronization signal VS4 are asynchronous, there is a problem that the continuity of synchronization is impaired when switching the video signal. That is, there is no continuity of synchronization between the last synchronization timing of the vertical synchronization signal VS3 before switching and the first synchronization timing of the vertical synchronization signal VS4 after switching. In a display device that receives image data without continuity of synchronization, synchronization becomes unstable and the image is disturbed, or measures such as performing black display during a period without continuity of synchronization are taken, which may result in poor appearance of the display.

Means for Solving the Problems

[0005] One aspect of the present disclosure relates to a circuit device including a first input circuit that receives first image data, a second input circuit that receives second image data, a frame memory that stores the second image data as switching image data, a first selection circuit that selects any one of the first image data, the second image data, and the switching image data and outputs it as first selected image data, an output circuit that outputs output image data based on the first selected image data, and a control circuit. The control circuit controls the first selection circuit to switch from the first image data to the switching image data during a vertical blanking period of the first image data, and controls the output circuit to output the output image data at a frame rate different from that of the second image data during a switching period in which the switching image data is selected by the first selection circuit. The circuit device is related to controlling the first selection circuit to switch from the switching image data to the second image data during an overlapping period between a vertical blanking period of the switching image data and a vertical blanking period of the second image data.

[0006] Another aspect of the present disclosure relates to a display system including the above-described circuit device and a display device that displays an image based on the output image data.

Brief Description of the Drawings

[0007]

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Mode for Carrying Out the Invention

[0008] Hereinafter, preferred embodiments of the present disclosure will be described in detail. It should be noted that the embodiments described below do not unduly limit the content described in the claims, and not all of the configurations described in the embodiments are essential constituent elements.

[0009] 1. Electronic device, display system FIG. 1 is a configuration example of an electronic device and a display system. The electronic device 400 includes a first device 10, a second device 20, and a display system 300. The display system 300 includes a circuit device 100 and a display device 200.

[0010] Each of the first device 10 and the second device 20 is a device that transmits image data to the circuit device 100. Examples of such devices include a camera, a repeater, a splitter, or a microprocessor. The camera captures an image and transmits the image data. The repeater is a device that performs buffering of the input image data. The splitter is a device that divides and transmits the input image data. The microprocessor transmits, for example, image data read from a memory, or performs image processing on the image data read from a memory or input from the outside and then transmits it.

[0011] The first device 10 transmits the first image data IMA. The second device 20 transmits the second image data IMB asynchronously with the first image data IMA. Asynchronous means that the display timings of the first image data IMA and the second image data IMB are not synchronized. Specifically, the timing control signals such as the dot clock, vertical synchronization signal, or horizontal synchronization signal of the first image data IMA and the timing control signal of the second image data IMB are generated independently of each other.

[0012] The circuit device 100 receives the first image data IMA from the first device 10, receives the second image data IMB from the second device 20, switches between the first image data IMA and the second image data IMB, and outputs them as output image data IMQ. The circuit device 100 is, for example, an integrated circuit device in which a plurality of circuit elements are integrated on a semiconductor substrate. The circuit device 100 is, for example, a dedicated IC for video switching, or an IC that performs image processing such as overlay or distortion correction in addition to video switching, or an IC that incorporates the function of a display controller in addition to video switching.

[0013] The display device 200 receives the output image data IMQ and displays an image corresponding to the output image data IMQ. The display device 200 is, for example, an in-vehicle display device such as a head-up display, a center information display, a cluster panel, a navigation system, or an electronic mirror. Alternatively, the display device 200 may be a television device or a monitor of an information processing terminal. The display device 200 includes a display panel and a display driver that drives the display panel. When the display device 200 is a head-up display, the display device 200 may include a projection optical system that projects the image displayed on the display panel and a light source for projection.

[0014] As an example, the electronic device 400 is an in-vehicle device, the first device 10 is a SoC that outputs a navigation image or the like, the second device 20 is an in-vehicle camera such as a rear camera, and the display device 200 is a head-up display or a center information display that displays information to the passenger. At this time, when the shift lever is switched to the reverse gear, the circuit device 100 may switch the output image data IMQ from a navigation image or the like to an image of a rear camera or the like based on the operation information of the shift lever.

[0015] 2. Circuit device FIG. 2 shows a first configuration example of the circuit device. The circuit device 100 includes a first input circuit 110, a second input circuit 120, an output circuit 130, a control circuit 140, a first selection circuit 150, a frame memory 160, and a register 180.

[0016] The first input circuit 110 is an image interface circuit that receives the first image data IMA and converts the received first image data IMA into a format used inside the circuit device 100. The specifications of the image interface may be various, such as those in which the image data and the timing control signal are transmitted and received as individual signals, those in which all or part of the timing control signal is embedded in the image data, those in which the timing control signal is demodulated from the image data, or those in which the image data and the timing control signal are transmitted and received by packet communication. The specifications of the image interface are, for example, Open LVDS Display Interface, DisplayPort, or Display Serial Interface 2 of Mobile Industry Processor Interface. The image data format used inside the circuit device 100 may also be various as described above. As an example, it is a format in which RGB image data and a timing control signal are transmitted as individual signals. The timing control signal includes, for example, a dot clock, a horizontal synchronization signal, and a vertical synchronization signal. Hereinafter, including the timing control signal, it will simply be referred to as the first image data IMA. The same applies to the second image data IMB and the output image data IMQ.

[0017] The second input circuit 120 is an image interface circuit that receives the second image data IMB and converts the received second image data IMB into a format used inside the circuit device 100. The first image data IMA and the second image data IMB are asynchronous. Asynchronous means that the timing control signals are not synchronized. For example, the synchronization timings of the vertical synchronization signals are independent of each other, or the frame rates are different. The image interface standard and the image data format used inside the circuit device 100 are the same as those described for the first input circuit 110. However, the image interface standard of the second input circuit 120 may be different from that of the first input circuit 110.

[0018] The frame memory 160 buffers the second image data IMB received by the second input circuit 120 and outputs the buffered second image data IMB as the switching-use image data IMX. As an example, the frame memory 160 has a double-buffer configuration, each including a first buffer and a second buffer for one frame. However, when the writing and reading of the frames do not interfere with each other, the frame memory 160 may be a single buffer. The embodiments described with reference to FIG. 4 and the like are described in a double-buffer configuration, but the frame memory 160 may have a triple-buffer configuration with three screens.

[0019] The first selection circuit 150 selects any one of the first image data IMA, the second image data IMB, and the switching-use image data IMX, and outputs the selected image data as the first selected image data IMS1. When switching from the first image data IMA to the second image data IMB, the first selection circuit 150 selects in the order of the first image data IMA, the switching-use image data IMX, and the second image data IMB.

[0020] The output circuit 130 outputs output image data IMQ based on the first selected image data IMS1. Also, the output circuit 130 adjusts the frame rate of the switching image data IMX so that the first image data IMA, the switching image data IMX, and the second image data IMB are switched during the vertical blanking period.

[0021] The register 180 stores adjustment data 181 for adjusting the frame rate of the switching image data IMX. For example, an external processing device of the circuit device 100 writes the adjustment data 181 into the register 180 via an interface circuit (not shown). Alternatively, the circuit device 100 may include a non-volatile memory (not shown) that stores the adjustment data 181, and the adjustment data 181 may be loaded from the non-volatile memory into the register 180.

[0022] The control circuit 140 controls the first selection circuit 150 and the output circuit 130 based on the adjustment data 181 stored in the register 180. Specifically, the control circuit 140 controls the selection timing of the image data by the first selection circuit 150 and the frame rate adjustment by the output circuit 130 based on the frame rate indicated by the adjustment data 181.

[0023] FIG. 3 is a detailed configuration example of the output circuit. The output circuit 130 includes a buffer memory 131, an image processing circuit 132, a synchronization signal generation circuit 133, and an output interface circuit 134. Note that the configuration of the output circuit 130 is not limited to FIG. 3, and for example, the image processing circuit 132 may be omitted.

[0024] The buffer memory 131 buffers the first selected image data IMS1. The buffer memory 131 absorbs, for example, the rate difference that occurs when the synchronization signal generation circuit 133 adjusts the frame rate.

[0025] The image processing circuit 132 performs image processing on the image data from the buffer memory 131. The image processing circuit 132 performs image processing on some or all of the first image data IMA, the switching image data IMX, and the second image data IMB. An example of the image processing is a process of overlaying a predetermined image such as an icon on the image data from the buffer memory 131. However, the image processing may be various, for example, gamma correction or color adjustment. Hereinafter, the image data after the image processing will also be referred to as the first image data IMA, the switching image data IMX, and the second image data IMB.

[0026] The synchronization signal generation circuit 133 generates a synchronization signal for the output image data IMQ. Specifically, it generates a synchronization signal for the output image data IMQ based on the dot clock used inside the circuit device 100. At this time, when the switching image data IMX is input from the image processing circuit 132, the synchronization signal generation circuit 133 adjusts the frame rate of the switching image data IMX. Specifically, the synchronization signal generation circuit 133 generates a synchronization signal so that the frame rate of the switching image data IMX is slower than the frame rate of the second image data IMB. When the first image data IMA or the second image data IMB is input from the image processing circuit 132, the synchronization signal generation circuit 133 generates a synchronization signal so as not to change the frame rate of those image data.

[0027] The output interface circuit 134 outputs the first image data IMA, the switching image data IMX, or the second image data IMB as output image data IMQ using the synchronization signal generated by the synchronization signal generation circuit 133. The output interface circuit 134 is an image interface circuit that converts the image data format used inside the circuit device 100 into the transmission standard of the output image data IMQ. The standards of the image interface and the image data format used inside the circuit device 100 are as described in the first input circuit 110. However, the image interface standard of the output interface circuit 134 may be different from the image interface standards of the first input circuit 110 and the second input circuit 120.

[0028] The control circuit 140 controls the frame rate adjustment by the synchronization signal generation circuit 133 based on the adjustment data 181. The adjustment data 181 is data indicating at least one of the vertical blanking period and the horizontal blanking period. The synchronization signal generation circuit 133 generates the horizontal synchronization signal and the vertical synchronization signal of the switching image data IMX so as to be the blanking period indicated by the adjustment data 181 based on the control from the control circuit 140. Since the total number of pixels in a frame is changed by changing the blanking period, the frame rate of the switching image data IMX is changed. The adjustment data 181 may be data indicating the blanking period itself, or may be data indicating the additional amount for the blanking period of the switching image data IMX input to the synchronization signal generation circuit 133. Specific examples of how to change the blanking period will be described after FIG. 7.

[0029] Note that the first selection circuit 150, the control circuit 140 in FIG. 2, and the image processing circuit 132 and the synchronization signal generation circuit 133 in FIG. 3 are constituted by logic circuits. Each of the first selection circuit 150, the control circuit 140, the image processing circuit 132, and the synchronization signal generation circuit 133 may be configured as an individual logic circuit. Alternatively, the logic circuit may be a processor. The circuit device 100 may include a memory (not shown) that stores a program describing the processing of each part of the first selection circuit 150, the control circuit 140, the image processing circuit 132, and the synchronization signal generation circuit 133. The processor may realize the processing of each part by executing the program. The processor may include, for example, one or more of a CPU, a GPU, a microcomputer, a DSP, an ASIC, or an FPGA. CPU is the abbreviation of Central Processing Unit. GPU is the abbreviation of Graphics Processing Unit. DSP is the abbreviation of Digital Signal Processor. ASIC is the abbreviation of Application Specific Integrated Circuit. FPGA is the abbreviation of Field Programmable Gate Array.

[0030] FIG. 4 is a timing chart for explaining the operation of the circuit device. FIG. 4 shows an example in which the frame rates of the first image data IMA and the second image data IMB are the same or substantially the same, and the vertical synchronization timings are different. Further, FIG. 4 shows an example in which the frame memory 160 has a double buffer configuration.

[0031] Let the image data in each frame of the first image data IMA be IMA1, IMA2, ···. The image data is transmitted like the active period of IMA1, the vertical blanking period, the active period of IMA2, the vertical blanking period, ···. Similarly, let the image data in each frame of the second image data IMB be IMB1, IMB2, ···. The image data is transmitted like the active period of IMB1, the vertical blanking period, the active period of IMB2, the vertical blanking period, ···.

[0032] The frame memory 160 updates the first buffer in IMB1 during the active period of IMB1, updates the second buffer in IMB2 during the active period of IMB2, updates the first buffer in IMB3 during the active period of IMB3, and updates the second buffer in IMB4 during the active period of IMB4. "Updating the buffer with image data" can also be rephrased as "writing the image data into the buffer". The first buffer and the second buffer hold the data written in the most recent update during the period when they are not updated. Hereinafter, the frame memory 160 repeats the same operation.

[0033] The first selection circuit 150 selects the first image data IMA, and the output circuit 130 outputs IMA1 as the output image data IMQ. The output circuit 130 does not change the frame period TFA of IMA1 in the output image data IMQ from the frame period of the first image data IMA received by the first input circuit 110.

[0034] During the vertical blanking period between IMA1 and IMA2, the first selection circuit 150 switches the first selected image data IMS1 from the first image data IMA to the switching image data IMX. The period during which the first selection circuit 150 selects the switching image data IMX shall be referred to as the switching period TIMX. During the switching period TIMX, the output circuit 130 reads IMB2 from the second buffer and outputs it as the output image data IMQ, then reads IMB3 from the first buffer and outputs it as the output image data IMQ, and then reads IMB4 from the second buffer and outputs it as the output image data IMQ. At this time, the output circuit 130 makes the frame periods TFX of IMB2, IMB3, and IMB4 in the output image data IMQ longer than the frame period TFB of the second image data IMB received by the second input circuit 120. This corresponds to frame rate adjustment, and the frame rate is adjusted by adjusting the blanking period as described above.

[0035] Taking the case where IMB2 is read from the second buffer as an example, it suffices that the active period of IMB2 in the output image data IMQ falls within the period from the start of the update by IMB2 in the second buffer to the end of the update by IMB4. In this way, IMB2 can be read from the second buffer without interference between the update and the read of the second buffer. The output circuit 130 reads from the buffer of the first buffer and the second buffer where such interference does not occur.

[0036] Since the frame periods TFX of IMB2, IMB3, and IMB4 in the output image data IMQ are longer than the frame period TFB of the second image data IMB received by the second input circuit 120, the time difference between the vertical synchronization timing of the output image data IMQ and the vertical synchronization timing of the second image data IMB becomes smaller. When the vertical blanking period of the output image data IMQ overlaps with the vertical blanking period of the second image data IMB, the first selection circuit 150 switches from the switching image data IMX to the second image data IMB during the overlapping period. In the example of FIG. 4, the switching is performed during the overlapping period between the vertical blanking period of IMB4 in the output image data IMQ and the vertical blanking period between IMB5 and IMB6 of the second image data IMB.

[0037] After the first selection circuit 150 selects the second image data IMB, the output circuit 130 outputs IMB6 and IMB7 as the output image data IMQ. The output circuit 130 does not change the frame periods TFB of IMB6 and IMB7 in the output image data IMQ from the frame period of the second image data IMB received by the second input circuit 120.

[0038] As described above, in the output image data IMQ, the first image data IMA, the switching image data IMX, and the second image data IMB are switched during the vertical blanking period. This can avoid image distortion or non-display periods during the switching of asynchronous images and provide a good-looking image to the user.

[0039] FIG. 5 shows a second configuration example of the circuit device. Hereinafter, the parts different from the first configuration example will be mainly described, and the description of the parts similar to the first configuration example will be omitted as appropriate. The circuit device 100 further includes a compression circuit 161 and a decompression circuit 162.

[0040] The compression circuit 161 compresses the second image data IMB and stores the compressed second image data IMB as the switching image data IMX in the frame memory 160. The decompression circuit 162 decompresses the switching image data IMX read from the frame memory 160 and outputs it to the first selection circuit 150. The compression method may be any method as long as a certain degree of image quality is maintained. As an example, the compression circuit 161 and the decompression circuit 162 may perform compression and decompression of image data using an image compression technology such as MPEG. Alternatively, the compression circuit 161 may reduce the number of pixels of the image data by thinning or binning, etc., and the decompression circuit 162 may restore the number of pixels of the image data to the original by upsampling or the like. By compressing the image data stored in the frame memory 160, the capacity of the frame memory 160 can be saved.

[0041] FIG. 6 shows a third configuration example of the circuit device. Hereinafter, the parts different from the first configuration example or the second configuration example will be mainly described, and the description of the parts similar to the first configuration example or the second configuration example will be omitted as appropriate. The circuit device 100 further includes a second selection circuit 170. Here, an example in which the second selection circuit 170 is combined with the second configuration example is shown, but the second selection circuit 170 may be combined with the first configuration example.

[0042] The second selection circuit 170 selects either the first image data IMA or the second image data IMB and outputs the selected image data as the second selected image data IMS2 to the compression circuit 161. The compression circuit 161 compresses the second selected image data IMS2, and the frame memory 160 stores the compressed second selected image data IMS2 as the switching image data IMX.

[0043] When the first selection circuit 150 selects the first image data IMA, the second selection circuit 170 selects the second image data IMB. When the first selection circuit 150 selects the second image data IMB, the second selection circuit 170 selects the first image data IMA. That is, when the output image data IMQ switches from the first image data IMA to the second image data IMB, the second image data IMB becomes the switching image data IMX. When the output image data IMQ switches from the second image data IMB to the first image data IMA, the first image data IMA becomes the switching image data IMX.

[0044] When the output image data IMQ switches from the second image data IMB to the first image data IMA, the operation is the same as the timing chart in FIG. 4. As an example, if "IMA" and "IMB" are interchanged in FIG. 4, it becomes the timing chart when the output image data IMQ switches from the second image data IMB to the first image data IMA.

[0045] In this embodiment, the circuit device 100 includes a first input circuit 110 that receives first image data IMA, a second input circuit 120 that receives second image data IMB, and a frame memory 160 that stores the second image data IMB as switching image data IMX. The circuit device 100 includes a first selection circuit 150 that selects any one of the first image data IMA, the second image data IMB, and the switching image data IMX and outputs it as first selected image data IMS1, an output circuit 130 that outputs output image data IMQ based on the first selected image data IMS1, and a control circuit 140. As described with reference to FIG. 4, the control circuit 140 controls the first selection circuit 150 to switch from the first image data IMA to the switching image data IMX during the vertical blanking period of the first image data IMA. The control circuit 140 controls the output circuit 130 to output the output image data IMQ at a frame rate different from that of the second image data IMB during a switching period TIMX in which the switching image data IMX is selected by the first selection circuit 150. The control circuit 140 controls the first selection circuit 150 to switch from the switching image data IMX to the second image data IMB during an overlapping period between the vertical blanking period of the switching image data IMX and the vertical blanking period of the second image data IMB.

[0046] According to this embodiment, during the switching period TIMX, the output image data IMQ is output at a frame rate different from that of the second image data IMB, so that the time difference between the vertical synchronization timing of the second image data IMB and the vertical synchronization timing of the output image data IMQ is reduced. Then, as the time difference decreases, an overlapping period occurs between the vertical blanking period of the switching image data IMX and the vertical blanking period of the second image data IMB. During this overlapping period, by switching from the switching image data IMX to the second image data IMB, the switching among the first image data IMA, the switching image data IMX, and the second image data IMB is performed during the vertical blanking period. Thereby, image distortion or a non-display period during the switching of asynchronous images can be avoided, and a good-looking image can be provided to the user.

[0047] As described with reference to FIG. 5, the circuit device 100 may include a compression circuit 161 that compresses the second image data IMB. The frame memory 160 may store the second image data IMB compressed by the compression circuit 161 as the switching image data IMX.

[0048] Further, the circuit device 100 may include a decompression circuit 162 that decompresses the switching image data IMX stored in the frame memory 160 and outputs it to the first selection circuit 150.

[0049] According to the present embodiment, by storing the compressed second image data IMB in the frame memory 160, the capacity of the frame memory 160 can be saved.

[0050] Also in the present embodiment, the control circuit 140 may set the frame rate of the switching image data IMX to a frame rate slower than the frame rate of the second image data IMB.

[0051] According to the present embodiment, as the vertical synchronization timing of the switching image data IMX gradually lags behind the vertical synchronization timing of the first image data IMA, it approaches the vertical synchronization timing of the second image data IMB. Then, when the time difference in the vertical synchronization timing becomes small, an overlapping period occurs between the vertical blanking period of the switching image data IMX and the vertical blanking period of the second image data IMB.

[0052] As described with reference to FIG. 6, the circuit device 100 may include a second selection circuit 170 that selects either the first image data IMA or the second image data IMB and outputs it as the second selected image data IMS2. The frame memory 160 may store the second selected image data IMS2 as the switching image data IMX.

[0053] Also, when the first selection circuit 150 switches from the second image data IMB to the first image data IMA, the second selection circuit 170 may select the first image data IMA as the second selected image data IMS2. The control circuit 140 may control the first selection circuit 150 to switch from the second image data IMB to the switching image data IMX during the vertical blanking period of the second image data IMB. The control circuit 140 may set the frame rate of the switching image data IMX to a frame rate different from that of the first image data IMA during the switching period. The control circuit 140 may control the first selection circuit 150 to switch from the switching image data IMX to the first image data IMA during the overlapping period between the vertical blanking period of the switching image data IMX and the vertical blanking period of the first image data IMA.

[0054] According to the present embodiment, in both the switching from the first image data IMA to the second image data IMB and the switching from the second image data IMB to the first image data IMA, the image switching is performed during the vertical blanking period. Thereby, it is possible to avoid image distortion or non-display periods in the bidirectional switching of asynchronous images and provide a user with a good-looking image.

[0055] Also, as will be described later with reference to FIGS. 7 to 12, the control circuit 140 may set the frame rate of the switching image data IMX by adjusting the length of the vertical blanking period, the length of the horizontal blanking period, or the lengths of the vertical blanking period and the horizontal blanking period of the switching image data IMX during the switching period TIMX.

[0056] Further, the circuit device 100 may include a register 180 that stores adjustment data 181 for the frame rate of the switching image data IMX. The control circuit 140 may set the length of the vertical blanking period, the length of the horizontal blanking period, or the lengths of the vertical blanking period and the horizontal blanking period of the switching image data IMX based on the adjustment data 181 during the switching period TIMX.

[0057] The frame rate is determined by the total number of pixels in the frame including the blanking area. That is, (total number of horizontal pixels) × (total number of vertical pixels) is the total number of pixels in the frame. According to this embodiment, by adjusting the length of the horizontal blanking period, the total number of horizontal pixels is changed, and by adjusting the length of the vertical blanking period, the total number of vertical pixels is changed. Thereby, the total number of pixels in the frame is changed and the frame rate is adjusted.

[0058] Note that in FIG. 8, the length of the vertical blanking period is adjusted, in FIGS. 9 and 10, the length of the horizontal blanking period is adjusted, and in FIGS. 11 and 12, the lengths of the vertical blanking period and the horizontal blanking period are adjusted.

[0059] Also, in this embodiment, the output circuit 130 may output the output image data IMQ based on the dot clock signal of the same frequency regardless of whether the first selection circuit 150 selects the first image data IMA, the switching image data IMX, or the second image data IMB. "Outputting the output image data IMQ based on the dot clock signal of the same frequency" means, for example, outputting the output image data IMQ based on the common same dot clock signal regardless of which image data is selected.

[0060] According to this embodiment, in the switching between the first image data IMA, the switching image data IMX, and the second image data IMB, the output circuit 130 controls the display timing based on the dot clock signal of the same frequency. Thereby, even if the first image data IMA and the second image data IMB are asynchronous, in the output image data IMQ, the image switching is performed during the vertical blanking period by the display timing control managed by the dot clock signal of the same frequency.

[0061] 3. Frame Rate Adjustment Hereinafter, an example of frame rate adjustment performed by the synchronization signal generation circuit 133 will be described.

[0062] FIG. 7 is an example of image data without frame rate adjustment. HSYNC indicates a horizontal synchronization signal, and VSYNC indicates a vertical synchronization signal. Here, the image data is illustrated as two-dimensional data corresponding to the display state, HSYNC is illustrated in association with the horizontal scanning direction in the display state, and VSYNC is illustrated in association with the vertical scanning direction. The area and period in the two-dimensional data can be associated with each other by the period of the dot clock. In the following, there may be cases where the area and period are not distinguished in the description.

[0063] The active area ACAR shown in FIG. 7 is the area displayed on the display device 200. The horizontal active pixel number HAC is the number of pixels in the active area ACAR in the horizontal scanning direction. The vertical active pixel number VAC is the number of pixels in the active area ACAR in the vertical scanning direction.

[0064] The blanking area BLAR is the area other than the active area ACAR among all the areas corresponding to the frame, and includes a horizontal blanking period and a vertical blanking period. The horizontal blanking period is the period other than the active period in the horizontal scanning period where the active area ACAR exists. The vertical blanking period is the period where the active area ACAR does not exist in the vertical scanning period. The horizontal total pixel number HTT is the number of pixels in the horizontal scanning direction of all the areas including the blanking area BLAR and the active area ACAR. The vertical total pixel number VTT is the number of pixels in the vertical scanning direction of all the areas including the blanking area BLAR and the active area ACAR.

[0065] FIG. 8 is a first example of frame rate adjustment. The synchronization signal generation circuit 133 slows down the frame rate of the switching image data IMX by increasing the vertical total pixel number VTT.

[0066] AD_BLAR indicates the increase in the blanking area BLAR. The number of pixels of the increase AD_BLAR in the horizontal scanning direction is the total number of horizontal pixels HTT. If the number of pixels of the increase AD_BLAR in the vertical scanning direction is ADy, the vertical scanning period becomes longer by HTT×ADy×(dot clock period). As a result, the frame rate becomes slower.

[0067] The adjustment data 181 may be data indicating, for example, the total number of vertical pixels VTT, or may be data indicating the number of pixels ADy of the increase AD_BLAR in the vertical scanning direction.

[0068] Figure 9 is a second example of frame rate adjustment. The synchronization signal generation circuit 133 slows down the frame rate of the switching image data IMX by increasing the total number of horizontal pixels HTT.

[0069] The number of pixels of the increase AD_BLAR in the vertical scanning direction is the total number of vertical pixels VTT. If the number of pixels of the increase AD_BLAR in the horizontal scanning direction is ADx, the vertical scanning period becomes longer by ADx×VTT×(dot clock period). As a result, the frame rate becomes slower.

[0070] The adjustment data 181 may be data indicating, for example, the total number of horizontal pixels HTT, or may be data indicating the number of pixels ADx of the increase AD_BLAR in the horizontal scanning direction.

[0071] Figure 10 is a third example of frame rate adjustment. The synchronization signal generation circuit 133 increases the total number of horizontal pixels HTT and combines a plurality of total numbers of horizontal pixels HTT to slow down the frame rate of the switching image data IMX.

[0072] The number of pixels of the increase AD_BLAR in the vertical scanning direction is the total number of vertical pixels VTT. The number of pixels of the increase AD_BLAR in the horizontal scanning direction varies for each horizontal scanning period. In the example of FIG. 10, the number of pixels of the increase AD_BLAR in each horizontal scanning period is either ADx1 or ADx2. ADx1 and ADx2 are different. However, the number of pixels of the increase AD_BLAR in each horizontal scanning period may be any of three or more types of pixel numbers. Since the vertical scanning period becomes longer by (the total number of pixels of AD_BLAR) × (the period of the dot clock), the frame rate becomes slower. By combining a plurality of total horizontal pixel numbers HTT, the frame rate can be finely adjusted compared to FIG. 8 or FIG. 9.

[0073] The adjustment data 181 may be data indicating, for example, the total number of horizontal pixels HTT in each horizontal scanning period, or may be data indicating the number of pixels of the increase AD_BLAR in the horizontal scanning direction in each horizontal scanning period.

[0074] FIG. 11 is a fourth example of frame rate adjustment. The synchronization signal generation circuit 133 slows down the frame rate of the switching image data IMX by increasing the total number of horizontal pixels HTT and the total number of vertical pixels VTT.

[0075] Let the number of pixels of the increase AD_BLAR in the horizontal scanning direction be ADx, and the number of pixels of the increase AD_BLAR in the vertical scanning direction be ADy. Since the vertical scanning period becomes longer by HTT×VTT - {(HTT - ADx)×(VTT - ADy)}×(the period of the dot clock), the frame rate becomes slower.

[0076] The adjustment data 181 may be data indicating, for example, the total number of horizontal pixels HTT and the total number of vertical pixels VTT, or may be data indicating the number of pixels of the increase AD_BLAR in the horizontal scanning direction ADx and the number of pixels of the increase AD_BLAR in the vertical scanning direction ADy.

[0077] FIG. 12 shows a fifth example of frame rate adjustment. The synchronization signal generation circuit 133 increases the total number of horizontal pixels HTT and the total number of vertical pixels VTT, and combines a plurality of total numbers of horizontal pixels HTT to slow down the frame rate of the switching image data IMX.

[0078] AD_BLAR1 and AD_BLAR2 indicate an increase in the blanking area BLAR. AD_BLAR1 is an area corresponding to an increase in the total number of horizontal pixels HTT. Let the number of pixels of the increased portion AD_BLAR1 in the horizontal scanning direction be ADx. AD_BLAR2 is an area corresponding to an increase in the total number of vertical pixels VTT. Let the number of pixels of the increased portion AD_BLAR2 in the vertical scanning direction be ADy. However, in the increased portion AD_BLAR2, a horizontal scanning period in which the total number of horizontal pixels is HTT and a horizontal scanning period in which the total number of horizontal pixels is HTT2 are mixed. FIG. 12 shows an example in which the total number of horizontal pixels is HTT2 in the last horizontal scanning period. HTT2 < HTT. FIG. 12 shows an example in which HTT - HTT2 > ADx, but HTT - HTT2 ≤ ADx may also be possible.

[0079] The adjustment data 181 may be data indicating, for example, the total number of horizontal pixels HTT, the total number of vertical pixels VTT, and the total number of horizontal pixels HTT2 in the last horizontal scanning period. Alternatively, the adjustment data 181 may be data indicating the number of pixels ADx of the increased portion AD_BLAR in the horizontal scanning direction, the number of pixels ADy of the increased portion AD_BLAR in the vertical scanning direction, and the total number of horizontal pixels HTT2 in the last horizontal scanning period.

[0080] Although the present embodiment has been described in detail as above, those skilled in the art will easily understand that many modifications can be made without substantially departing from the novel matters and effects of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure. For example, in the specification or drawings, a term that is described at least once together with a broader or synonymous different term can be replaced with that different term anywhere in the specification or drawings. Also, all combinations of the present embodiment and the modifications are included within the scope of the present disclosure. Further, the configurations and operations of the electronic device, display system, display device, circuit device, first device, second device, first input circuit, second input circuit, frame memory, selection circuit, output circuit, control circuit, register, etc. are not limited to those described in the present embodiment, and various modified implementations are possible.

Explanation of Reference Numerals

[0081] 10... First device, 20... Second device, 100... Circuit device, 110... First input circuit, 120... Second input circuit, 130... Output circuit, 131... Buffer memory, 132... Image processing circuit, 133... Synchronization signal generation circuit, 134... Output interface circuit, 140... Control circuit, 150... First selection circuit, 160... Frame memory, 161... Compression circuit, 162... Decompression circuit, 170... Second selection circuit, 180... Register, 181... Adjustment data, 200... Display device, 300... Display system, 400... Electronic device, IMA... First image data, IMB... Second image data, IMQ... Output image data, IMS1... First selected image data, IMS2... Second selected image data, IMX... Switching image data, TIMX... Switching period

Claims

1. A first input circuit for receiving first image data, A second input circuit for receiving second image data, A frame memory for storing the second image data as switching image data, A first selection circuit for selecting any one of the first image data, the second image data, and the switching image data and outputting it as first selected image data, An output circuit for outputting output image data based on the first selected image data, A control circuit, comprising, The control circuit, controls the first selection circuit to switch from the first image data to the switching image data during the vertical blanking period of the first image data, controls the output circuit to output the output image data at a frame rate different from that of the second image data during a switching period in which the switching image data is selected by the first selection circuit, A circuit device, characterized in that the first selection circuit is controlled to switch from the switching image data to the second image data during an overlapping period between the vertical blanking period of the switching image data and the vertical blanking period of the second image data.

2. In the circuit device according to Claim 1, comprising a compression circuit for compressing the second image data, The frame memory, stores the second image data compressed by the compression circuit as the switching image data. A circuit device characterized by this.

3. In the circuit device according to Claim 2, comprising a decompression circuit for decompressing the switching image data stored in the frame memory and outputting it to the first selection circuit. A circuit device characterized by this.

4. In the circuit device according to Claim 1, The control circuit, sets the frame rate of the switching image data to a frame rate slower than the frame rate of the second image data. A circuit device characterized by this.

5. In the circuit device according to Claim 1, comprising a second selection circuit for selecting any one of the first image data and the second image data and outputting it as second selected image data, The frame memory, stores the second selected image data as the switching image data. A circuit device characterized by this.

6. In the circuit device according to Claim 5, The second selection circuit, When the first selection circuit switches from the second image data to the first image data, the first image data is selected as the second selected image data. The control circuit: controls the first selection circuit to switch from the second image data to the switching image data during the vertical blanking period of the second image data. sets the frame rate of the switching image data to a frame rate different from that of the first image data during the switching period. A circuit device characterized in that the first selection circuit is controlled to switch from the switching image data to the first image data during an overlapping period between the vertical blanking period of the switching image data and the vertical blanking period of the first image data.

7. In the circuit device according to claim 1, the control circuit: A circuit device characterized in that the frame rate of the switching image data is set by adjusting the length of the vertical blanking period, the length of the horizontal blanking period, or both the length of the vertical blanking period and the length of the horizontal blanking period of the switching image data during the switching period.

8. In the circuit device according to claim 7, including a register for storing adjustment data of the frame rate of the switching image data, the control circuit: A circuit device characterized in that the length of the vertical blanking period, the length of the horizontal blanking period, or both the length of the vertical blanking period and the length of the horizontal blanking period of the switching image data are set based on the adjustment data during the switching period.

9. In the circuit device according to claim 1, The output circuit outputs the output image data based on a dot clock signal of the same frequency regardless of whether the first selection circuit selects the first image data, the switching image data, or the second image data. A circuit device characterized by this.

10. A circuit device according to any one of claims 1 to 9, and a display device for displaying an image based on the output image data, A display system characterized by including these.

Images