Control circuit

Abstract

To reduce the cost of switching between a transmission state and a reception state of a wireless device.SOLUTION: An electronic circuit 100 for switching between a transmission state and a reception state of a wireless device includes a frequency converter 3 for converting the frequency of a transmission signal or a reception signal, a D / A converter 102 for generating a bias voltage for operating the frequency converter 3, a changeover switch for switching between a first state in which a voltage based on the bias voltage is supplied to the frequency converter 3 and a second state in which a predetermined voltage is supplied to the frequency converter 3, and a control circuit 1 for controlling the changeover switch to switch between the first state and the second state depending on whether the wireless device is in the transmission state or the reception state.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a control circuit for generating a bias voltage.

Background Art

[0002] It has been proposed to operate a transmission circuit and a reception circuit in a time-division manner in wireless transmission (for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the invention described in Patent Document 1, a circuit for biasing a transmission circuit or a reception circuit is required to have high-speed switching operation performance. In the invention described in Patent Document 1, since it is necessary to prepare a D / A converter having a plurality of output terminals capable of coping with such control of a bias voltage, there is a problem that the cost increases.

[0005] The present invention has been made in view of the above problems, and an object thereof is to provide a control circuit capable of reducing the cost required for switching between a transmission state and a reception state of a wireless device.

Means for Solving the Problems

[0006] The electronic circuit according to the first aspect of the present invention is an electronic circuit for switching between a transmission state and a reception state of a wireless device, and includes a frequency converter for converting the frequency of a transmission signal or a reception signal, a D / A converter for generating a bias voltage for operating the frequency converter, a switching switch for switching between a first state in which a voltage based on the bias voltage is supplied to the frequency converter and a second state in which a predetermined voltage is supplied to the frequency converter, and a control circuit for controlling the switching switch so as to switch between the first state and the second state according to whether the wireless device is in a transmission state or a reception state.

[0007] The electronic circuit further includes an amplifier provided between the switching switch and the frequency converter, and a pull-up resistor provided at an input stage of the amplifier. The control circuit may generate a control signal for switching the switching switch such that, in the first state, a first input terminal of the switching switch to which the bias voltage is input is connected to the amplifier, and in the second state, a second input terminal of the open switching switch is connected to the amplifier.

[0008] The control circuit may include a control signal generation unit for generating the control signal, a reset signal generation unit for generating a reset voltage for a predetermined time after the electronic circuit is powered on, and a three-state buffer for generating a voltage for setting the switching switch to the second state when the reset signal generation unit is generating the reset voltage or when the control signal generation unit is not generating an open enable voltage, and for inputting the control signal to the switching switch when the reset signal generation unit is not generating the reset voltage and the control signal generation unit is generating the open enable voltage.

[0009] The electronic circuit has a plurality of the switching switches corresponding to a plurality of output terminals of the D / A converter, and the control signal generation unit may have a shift register that generates a plurality of the control signals for controlling the plurality of the switching switches in a predetermined sequence.

Effect of the Invention

[0010] According to the present invention, there is an effect of reducing the cost required to switch between the transmission state and the reception state of the wireless device.

Brief Description of the Drawings

[0011]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Modes for Carrying Out the Invention

[0012] <First Embodiment> [Configuration of Electronic Circuit] FIG. 1 shows the configuration of an electronic circuit 100 according to the first embodiment. The electronic circuit 100 is mounted on a wireless device. The electronic circuit 100 is a circuit for switching between the transmission state and the reception state of this wireless device. The electronic circuit 100 includes a control circuit 1, an amplification circuit 2a, an amplification circuit 2b, an amplification circuit 2c, and a frequency converter 3. The control circuit 1 controls the amplification circuits 2a to 2c according to whether the wireless device is in a transmission state or a reception state. The control circuit 1 includes a control signal generation unit 101 and a D / A converter 102.

[0013] The frequency converter 3 converts the frequency of the transmission signal or the reception signal. The frequency converter 3 includes an up-converter 31 and a down-converter 32. The up-converter 31 converts a low-frequency transmission signal into a high-frequency signal. The down-converter 32 converts a high-frequency reception signal into a low-frequency signal.

[0014] The D / A converter 102 generates a bias voltage for operating the frequency converter 3. The amplification circuits 2a, 2b, and 2c amplify the bias voltage input from the D / A converter 102. The amplification circuits 2a, 2b, and 2c are circuits for adjusting the gain of the amplified bias voltage. The amplification circuits 2a, 2b, and 2c apply the amplified bias voltage to the frequency converter 3.

[0015] The control signal generation unit 101 has, for example, a CPLD (Complex Programmable Logic Device). The control signal generation unit 101 may have an FPGA (Field-Programmable Gate Array). The control signal generation unit 101 generates a control signal for controlling the amplification circuits 2a, 2b, and 2c.

[0016] The control signal generation unit 101 generates a control signal corresponding to the transmission timing and the reception timing of the wireless device on which the electronic circuit 100 is mounted. The control signal generation unit 101 generates a control signal by counting the number of reference clocks input from an oscillation circuit (not shown). By generating a control signal, the control signal generation unit 101 controls a switching switch provided in the amplification circuits 2a to 2c so as to switch between a first state in which a voltage based on the bias voltage from the D / A converter 102 is supplied to the frequency converter and a second state in which a predetermined voltage is supplied to the frequency converter according to whether the wireless device is in a transmission state or a reception state.

[0017] In this way, the control signal generation unit 101 can change a plurality of bias voltages input to the frequency converter 3 in accordance with the timing at which the transmission state and the reception state are switched. At this time, the control signal generation unit 101 changes the bias voltage by a switching switch (described later) provided in the amplification circuits 2a to 2c. Therefore, compared with the case where a plurality of bias voltages input to the frequency converter 3 by the D / A converter 102 alone are each changed, the performance required of the D / A converter 102 can be reduced. For this reason, the cost of the electronic circuit 100 is reduced.

[0018] FIG. 2 shows the configurations of the amplification circuits 2a, 2b, and 2c in FIG. 1. Since the amplification circuits 2a to 2c all have the same configuration, the configuration of the amplification circuit 2a will be described as a representative example. The amplification circuit 2a includes a switching switch 201, an amplifier 202, a resistor 203, a pull-up resistor 204, a resistor 205, a resistor 206, a pull-up resistor 207, and a resistor 208.

[0019] The amplifier 202 is provided between the switching switch 201 and the frequency converter 3. The amplifier 202 amplifies the voltage of the signal input from the switching switch 201. The pull-up resistor 204 and the resistor 205 are connected to the input stage of the non-inverting input terminal of the amplifier 202. The pull-up resistor 204 and the resistor 205 are resistors for adjusting the voltage input to the input stage of the non-inverting input terminal of the amplifier 202. The pull-up resistor 204 and the resistor 205 are provided to adjust an offset that is the difference between the voltage input to the non-inverting input terminal of the amplifier 202 and the voltage input to the inverting input terminal of the amplifier 202.

[0020] Resistors 203 and 206 are resistors for adjusting the gain of amplifier 202. Resistor 203 is connected to the input stage of the inverting input terminal of amplifier 202. Resistor 206 is provided between the inverting input terminal and the output terminal of amplifier 202. Pull-up resistor 207 is provided to prevent the voltage input to the inverting input terminal of amplifier 202 from becoming unstable when the second input terminal B opened in switch 201 is connected to amplifier 202. Resistor 208 is provided between the inverting input terminal of amplifier 202 and GND. Resistor 208 is a resistor for adjusting the voltage input to the inverting input terminal of amplifier 202 when switch 201 is open.

[0021] Switch 201 is an element for switching between a first state in which a voltage based on the bias voltage from D / A converter 102 is supplied to the frequency converter and a second state in which a predetermined voltage is supplied to the frequency converter. The voltage based on the bias voltage is, for example, the bias voltage amplified by amplifier 202. The predetermined voltage is, for example, the power supply voltage supplied to the second input terminal B of switch 201. For example, switch 201 is an SPDT (Single-Pole Double-Throw). In the electronic circuit 100 of FIG. 1, switch 201 is provided for each amplification circuit.

[0022] In electronic circuit 100, a plurality of switches 201 are respectively provided, each connected to a plurality of output terminals of D / A converter 102. The bias voltage generated by D / A converter 102 is input to the first input terminal A of switch 201. The first input terminal A of switch 201 is connected to amplifier 202 in the first state. As shown in FIG. 2, the second input terminal B of switch 201 is open. The second input terminal B is connected to amplifier 202 in the second state.

[0023] FIG. 3 shows the relationship between the bias voltage input to the input stage of the inverting input terminal of the amplifier 202 and the output voltage of the amplifier 202. The vertical axis in FIG. 3 indicates the output voltage of the amplifier 202. The horizontal axis in FIG. 3 indicates the bias voltage input to the input stage of the inverting input terminal of the amplifier 202. As shown in FIG. 3, the output voltage of the amplifier 202 shows a negative value, and as the bias voltage input to the input stage of the inverting input terminal of the amplifier 202 increases, the absolute value of the output voltage of the amplifier 202 increases.

[0024] FIG. 4 shows an example of the control signal generation unit 101. The control signal generation unit 101 includes a signal generation unit 401, a reset signal generation unit 402, a digital transistor 403, a three-state buffer 404, a NOR circuit 405, a pull-up resistor 406, a pull-up resistor 407, a pull-up resistor 408, and a pull-up resistor 409.

[0025] The three-state buffer 404 inputs the control signal from the signal generation unit 401 for transitioning the switching switch 201 to the first state or the second state to the switching switch 201. The three-state buffer 404 switches between a buffer state in which the control signal generated by the SW terminal of the signal generation unit 401 is directly input to the switching switch 201 and a high-impedance state in which the control signal generated by the SW terminal of the signal generation unit 401 is not input to the switching switch 201. In the high-impedance state, a voltage signal for switching the switching switch 201 to the second state is input to the switching switch 201 so that the open second input terminal B (see FIG. 6) of the switching switch 201 is connected to the amplifier 202. This voltage is based on the pull-up resistor 407.

[0026] The reset signal generation unit 402 generates a reset voltage for a predetermined time after the power is turned on for each element of the electronic circuit 200 such as the signal generation unit 401. The predetermined time is, for example, a time longer than the time required for the signal generation unit 401 to rise after the power is turned on for the electronic circuit 200.

[0027] The SW terminal of the signal generation unit 401 is connected to the switching switch 201 via the 3-state buffer 404. The _OE terminal of the signal generation unit 401 is connected to the NOR circuit 405.

[0028] The signal generation unit 401 controls the switching switch 201 to switch between the first state and the second state via the SW terminal. After the rising of the signal generation unit 401 at the time of power-on is completed, the signal generation unit 401 generates a control signal of the open enable voltage from the _OE terminal. The signal generation unit 401 does not generate a control signal of the open enable voltage from the _OE terminal until the rising at the time of power-on of the signal generation unit 401 is completed. This control signal is for switching between the high impedance state and the buffer state of the 3-state buffer 404.

[0029] The NPN digital transistor 403 is an NPN transistor having a base resistor and a base-emitter resistance. The base terminal of the NPN digital transistor 403 is connected to the output terminal of the NOR circuit 405. The collector terminal of the NPN digital transistor 403 is connected to the control input terminal of the 3-state buffer 404.

[0030] The NPN digital transistor 403 is in the off state when the reset voltage (high level voltage) generated by the reset signal generation unit 402 is input to the NOR circuit 405, or when the open enable signal (low level voltage) is not input from the open enable terminal of the signal generation unit 401 to the NOR circuit 405. At this time, a high level voltage is applied to the control input terminal of the 3-state buffer 404 via the pull-up resistor 409, and the 3-state buffer 404 becomes the high impedance state.

[0031] The NPN digital transistor 403 is in an on state when the reset voltage (high-level voltage) generated by the reset signal generation unit 402 is not input to the NOR circuit 405 and the open enable signal (low-level voltage) is input from the open enable terminal of the signal generation unit 401 to the NOR circuit 405. At this time, a low-level voltage is applied to the control input terminal of the 3-state buffer 404, and the 3-state buffer 404 outputs the signal input from the signal generation unit 401. The pull-up resistors 406 to 409 are resistors for stabilizing the voltage of the signal input to the control input terminal of the NOR circuit 405, the changeover switch 201, or the 3-state buffer 404 at the rising edge when the electronic circuit 200 is powered on.

[0032] In the electronic circuit 100, by setting the 3-state buffer 404 to a high-impedance state at the rising edge when the electronic circuit 100 is powered on, it is possible to suppress the signal generated at the SW terminal of the signal generation unit 401 during the rising edge from being input to the changeover switch 201. Therefore, in the electronic circuit 100, it is possible to suppress the malfunction of the changeover switch 201.

[0033] <Second Embodiment> The control signal generation unit 101 may include a shift register that generates a plurality of control signals for controlling a plurality of changeover switches 201 in a predetermined sequence. FIG. 5 shows the configuration of the electronic circuit 200 according to the second embodiment. The electronic circuit 200 is different from the electronic circuit 100 in FIG. 1 in that it includes a shift register 50. The shift register 50 includes an auxiliary signal generation unit 501. The auxiliary signal generation unit 501 switches the changeover switch 201 provided in the plurality of amplification circuits 2a to 2c to the first state or the second state.

[0034] The control signal generation unit 101 is connected to a plurality of amplification circuits 2a to 2c via the shift register 50. The auxiliary signal generation unit 501 of this shift register 50 generates a control signal for controlling a plurality of switching switches 201 in a predetermined sequence. The sequence determines, for example, the timing for switching the switching switches 201 of the amplification circuits 2a to 2c to the first state or the second state, respectively.

[0035] Figures 6(a) to 6(g) show examples of the timing for switching the switching switches 201 provided in the amplification circuits 2a to 2c to the first state and the second state. Figure 6(a) shows an example of the reset signal generated by the reset signal generation unit 402. Figure 6(b) shows an example of the clock supplied to each element of the electronic circuit.

[0036] Figure 6(c) shows the on-processing period for switching the switching switches 201 provided in the plurality of amplification circuits 2a to 2c to the first state by the auxiliary signal generation unit 501 mounted on the shift register 50. This on-processing period starts, for example, when the signal generation unit 401 inputs an on-processing start signal to the auxiliary signal generation unit 501. Figure 6(d) shows the off-processing period for switching the switching switches 201 provided in the plurality of amplification circuits 2a to 2c to the second state by the auxiliary signal generation unit 501. This off-processing period starts, for example, when the signal generation unit 401 inputs an off-processing start signal to the auxiliary signal generation unit 501.

[0037] Figure 6(e) shows the timing for switching the switching switch 201 provided in the amplification circuit 2a to the first state and the second state. Figure 6(f) shows the timing for switching the switching switch 201 provided in the amplification circuit 2b to the first state and the second state. Figure 6(g) shows the timing for switching the switching switch 201 provided in the amplification circuit 2c to the first state and the second state.

[0038] As shown in FIGS. 6(e) to 6(g), the auxiliary signal generation unit 501 sequentially switches the switching switches 201 provided in the amplification circuits 2a, 2b, and 2c to the first state within the on-processing period shown in FIG. 6(c). The timing from the start of the on-processing period until the switching switches 201 of the amplification circuits 2a to 2c are switched to the first state is stored, for example, in a storage unit (not shown) of the shift register 50.

[0039] Similarly, the auxiliary signal generation unit 501 sequentially switches the switching switches 201 provided in the amplification circuits 2a, 2b, and 2c to the second state within the off-processing period shown in FIG. 6(d). The timing from the start of the off-processing period until the switching switches 201 of the amplification circuits 2a to 2c are switched to the second state is stored, for example, in the storage unit of the shift register 50.

[0040] For example, when the control signal generation unit 101 in FIG. 1 is implemented in an FPGA, if the number of output terminals of the FPGA is small, the control signal generation unit 101 cannot individually control the plurality of amplification circuits 2a to 2c. In the electronic circuit 200 of the second embodiment, since the auxiliary signal generation unit 501 switches the switching switches 201 of the amplification circuits 2a to 2c to the first state or the second state, it is not necessary to secure output terminals corresponding to each of the amplification circuits 2a to 2c on the control circuit 1 side. Therefore, in the electronic circuit 200, the control circuit 1 can be made low-cost.

[0041] [Effects of the Electronic Circuit 100 or 200 of the Present Invention] The control signal generation unit 101 can change a plurality of bias voltages input to the frequency converter 3 in accordance with the timing at which the transmission state and the reception state are switched. At this time, the control signal generation unit 101 changes the bias voltage by means of the switching switch 201 provided in the amplification circuits 2a to 2c, and thus can reduce the performance requirements for the D / A converter 102 as compared with the case where a plurality of bias voltages input to the frequency converter 3 are each changed by the D / A converter 102 alone. Therefore, in the electronic circuit 100, the cost required for the entire electronic circuit 100 including the D / A converter 102 can be reduced.

[0042] As described above, the present invention has been described using the embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments, and various modifications and changes are possible within the scope of the gist thereof. For example, all or part of the device can be configured by being functionally or physically dispersed and integrated in an arbitrary unit. Also, new embodiments resulting from an arbitrary combination of a plurality of embodiments are also included in the embodiments of the present invention. The effects of the new embodiments resulting from the combination have the effects of the original embodiments combined.

Explanation of Reference Numerals

[0043] 1 Control circuit 2a Amplification circuit 2b Amplification circuit 2c Amplification circuit 3 Frequency converter 31 Upconverter 32 Downconverter 100 Electronic circuit 101 Control signal generation unit 102 D / A converter 200 Electronic circuit 201 Switching switch 202 Amplifier 203 Resistor 204 Pull-up resistor 205 Resistor 206 Resistor 207 Pull-up resistor 401 Signal Generation Unit 402 Reset Signal Generation Unit 403 Digital Transistor 404 State Buffer 405 Circuit 406 Resistor 407 Resistor 408 Resistor 409 Resistor

Claims

1. An electronic circuit for switching between a transmission state and a reception state of a wireless device, comprising: a frequency converter for converting the frequency of a transmission signal or a reception signal; a D / A converter for generating a bias voltage for operating the frequency converter; a first state in which a voltage based on the bias voltage is supplied to the frequency converter; a switching switch for switching between a second state in which a predetermined voltage is supplied to the frequency converter; a control circuit for controlling the switching switch so as to switch between the first state and the second state according to whether the wireless device is in a transmission state or a reception state; An electronic circuit comprising the above components.

2. An amplifier provided between the switching switch and the frequency converter; a pull-up resistor provided at an input stage of the amplifier; The electronic circuit further comprising: In the first state, the control circuit generates a control signal for switching the switching switch such that a first input terminal of the switching switch to which the bias voltage is input is connected to the amplifier, and in the second state, a second input terminal of the switching switch that is open is connected to the amplifier. The electronic circuit according to Claim 1.

3. The control circuit includes: a control signal generation unit for generating the control signal; a reset signal generation unit for generating a reset voltage over a predetermined time after the electronic circuit is powered on; a three-state buffer that generates a voltage for setting the switching switch to the second state when the reset signal generation unit is generating the reset voltage or when the control signal generation unit is not generating an open enable voltage, and inputs the control signal to the switching switch when the reset signal generation unit is not generating the reset voltage and the control signal generation unit is generating the open enable voltage. The electronic circuit according to Claim 2.

4. The electronic circuit has a plurality of the switching switches corresponding to a plurality of output terminals of the D / A converter; The control signal generation unit has a shift register for generating a plurality of the control signals for controlling the plurality of the switching switches in a predetermined sequence. The electronic circuit according to Claim 3. ​ ​ ​ ​

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