Game machine

Abstract

To provide a game machine capable of suitably performing management of a game machine.SOLUTION: A main control board 61 includes a setting key insertion part 68a, and a setting state of a Pachinko machine 10 can be changed by starting to supply operating power to the Pachinko machine 10 in a state in which ON operation is performed by inserting a setting key into the setting key insertion part 68a. A winning probability of a jackpot result at least in a low-probability mode varies according to the setting state of the Pachinko machine 10. Game history is stored as history information in a management IC 66, and a management result of the game history is computed by utilizing the history information at operation timing. In this case, when a setting state of the Pachinko machine 10 is set newly, a management result of game history is computed by utilizing history information at that point and then the history information at that point is erased.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] The present invention relates to a gaming machine.

Background Art

[0002] As gaming machines, pachinko machines and slot machines are known. For example, a pachinko machine includes a dish storage unit for storing game balls given to a player on the front surface of the gaming machine, and the game balls stored in the dish storage unit are guided to a game ball launching device and launched toward the game area according to the launching operation of the player. Then, for example, when a game ball enters a ball entry part provided in the game area, game balls are paid out from a payout device to the dish storage unit. In addition, in a pachinko machine, a configuration including an upper dish storage unit and a lower dish storage unit as dish storage units is also known. In this case, the game balls stored in the upper dish storage unit are guided to the game ball launching device, and the surplus game balls in the upper dish storage unit are discharged to the lower dish storage unit (see, for example, Patent Document 1).

[0003] In addition, in a slot machine, when a start lever is operated in a situation where medals are bet and a new game is started, a lottery process is executed by control means. Further, when the lottery process is executed, rotation start control is executed by the control means to start the rotation of the reel. When a stop button is operated during the rotation of the reel, rotation stop control is executed by the control means to stop the rotation of the reel. Then, when the stop result after the rotation stop of the reel corresponds to the winning combination of the lottery process, a privilege corresponding to the winning combination is given to the player.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] Here, in a gaming machine such as the above-described example, the game needs to be suitably played, and there is still room for improvement in this regard.

[0006] The present invention has been made in view of the above-described circumstances and the like, and an object thereof is to provide a gaming machine capable of suitably playing a game.

Means for Solving the Problems

[0007] In order to solve the above problems, the invention according to claim 1 is electrically connected to a predetermined detection means, and a game value imparting means for executing a process for imparting a game value to a game, A process execution means that is electrically connected to the game value imparting means and executes a predetermined process, In a gaming machine comprising: The game value imparting means includes: A first reference information storage means for storing reference information, which is information used in the process for imparting the game value and is referred to in relation to the detection by the predetermined detection means, A first transmission means for transmitting a reference information signal corresponding to the reference information stored in the first reference information storage means to the process execution means after a predetermined supply of power to the present gaming machine is started and before the execution of a predetermined process for advancing the game is started, A second transmission means for transmitting a predetermined information signal based on the information acquired based on the detection by the predetermined detection means to the process execution means, Means for transmitting a predetermined transition signal to the process execution means when the game state shifts to a predetermined game state in a situation where a game is being played, Means for executing a process for causing a predetermined signal to be externally output to the outside of the present gaming machine when the game state shifts to the predetermined game state in a situation where a game is being played, Means for executing a predetermined determination process for determining whether a predetermined storage area is normal after a predetermined supply of power to the present gaming machine is started and before the execution of the predetermined process is started, comprising when it is determined in the predetermined determination process that the predetermined storage area is not normal, a corresponding process is executed; when it is determined in the predetermined determination process that the predetermined storage area is normal, the transmission of the reference information signal by the first transmission means is then executed; the process execution means a second reference information storage means for storing reference information corresponding to the reference information signal transmitted from the game value giving means; an execution means for executing the predetermined process based on the predetermined information signal transmitted from the second transmission means and the reference information stored in the second reference information storage means; a process result information storage means for storing information regarding the process result of the predetermined process by the execution means; a means for storing information corresponding to the case where the predetermined transition signal is received; a means for causing the process result information stored in the process result information storage means to be erased when a predetermined opportunity occurs based on a predetermined operation being performed; comprising the game value giving means is a main control means for controlling the progress of the game; the process execution means is an effect control means for controlling the execution of an effect; even in a situation where a predetermined event that stops the progress control of the game has occurred, the transmission of the reference information signal from the game value giving means is performed; when a predetermined event that stops the progress control of the game has occurred, predetermined control for transmitting the predetermined information signal by the second transmission means is not executed; the predetermined process is a process different from the giving of value used for playing the game.

Effect of the Invention

[0008] According to the present invention, it becomes possible to suitably play the game.

Brief Description of the Drawings

[0009]

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Embodiments for Carrying Out the Invention

[0010] <First Embodiment> Hereinafter, a first embodiment of a pachinko game machine (hereinafter referred to as "pachinko machine"), which is a type of gaming machine, will be described in detail with reference to the drawings. FIG. 1 is a perspective view of the pachinko machine 10, and FIG. 2 is a perspective view showing the main components of the pachinko machine 10 disassembled. In FIG. 2, for the sake of convenience, the configuration within the game area PA of the pachinko machine 10 is omitted.

[0011] As shown in FIG. 1, the pachinko machine 10 includes an outer frame 11 that forms the outer shell of the pachinko machine 10, and a game machine main body 12 that is rotatably attached to the front of the outer frame 11. The outer frame 11 is formed by connecting wooden plates on four sides and has a rectangular frame shape. The pachinko machine 10 is installed in a game hall by attaching and fixing the outer frame 11 to the island equipment. Note that the outer frame 11 is not an essential configuration in the pachinko machine 10, and the outer frame 11 may be provided on the island equipment in the game hall.

[0012] As shown in Fig. 2, the gaming machine main body 12 includes an inner frame 13, a front door frame 14 disposed in front of the inner frame 13, and a back pack unit 15 disposed behind the inner frame 13. Among them, the inner frame 13 of the gaming machine main body 12 is rotatably supported by the outer frame 11. Specifically, when viewed from the front, with the left side as the rotation base end side and the right side as the rotation tip end side, the inner frame 13 can rotate forward.

[0013] The front door frame 14 is rotatably supported by the inner frame 13. When viewed from the front, with the left side as the rotation base end side and the right side as the rotation tip end side, it can rotate forward. Also, the back pack unit 15 is rotatably supported by the inner frame 13. When viewed from the front, with the left side as the rotation base end side and the right side as the rotation tip end side, it can rotate backward.

[0014] Note that the gaming machine main body 12 is provided with a locking device at its rotation tip end, and has a function of locking the gaming machine main body 12 in a non-openable state with respect to the outer frame 11, and also has a function of locking the front door frame 14 in a non-openable state with respect to the inner frame 13. Each of these locked states is released by performing an unlocking operation using an unlocking key on the cylinder lock 17 provided to be exposed on the front surface of the pachinko machine 10.

[0015] Next, the configuration on the front side of the gaming machine main body 12 will be described.

[0016] The inner frame 13 is mainly composed of a resin base 21 whose outer shape is substantially the same as that of the outer frame 11. A substantially elliptical window hole 23 is formed in the central portion of the resin base 21. A game board 24 is detachably attached to the resin base 21. The game board 24 is made of plywood, and the game area PA formed on the front surface of the game board 24 is exposed on the front side of the inner frame 13 through the window hole 23 of the resin base 21.

[0017] Here, the configuration of the game board 24 will be described based on Fig. 3. Fig. 3 is a front view of the game board 24.

[0018] On the game board 24, an inner rail portion 25 and an outer rail portion 26 are attached so as to partition a part of the outer edge of the game area PA, and an induction rail as an induction means is constituted by these inner rail portion 25 and outer rail portion 26. The game balls launched from the game ball launching mechanism 27 (see FIG. 2) attached below the window hole 23 in the resin base 21 are guided to the upper part of the game area PA by the induction rail.

[0019] Incidentally, the game ball launching mechanism 27 includes a launching rail 27a extending toward the induction rail, a ball feeding device 27b that supplies the game balls stored in the upper plate 55a described later onto the launching rail 27a, and a solenoid 27c which is an electric actuator that launches the game balls supplied onto the launching rail 27a toward the induction rail. When the launching operation device (or operation handle) 28 provided on the front door frame 14 is rotated, the solenoid 27c is driven and controlled, and the game balls are launched.

[0020] The game board 24 is formed with a plurality of large and small openings penetrating in the front-rear direction. A general winning opening 31, a special electric winning device 32, a first operation opening 33, a second operation opening 34, a through gate 35, a variable display unit 36, a special figure unit 37, a general figure unit 38, etc. are respectively provided in each opening. A total of 4 general winning openings 31 are provided, and the others are provided one by one.

[0021] Even if a game ball enters the through gate 35, the payout of the game ball is not executed. On the other hand, when a game ball enters the general winning opening 31, the special electric winning device 32, the first operation opening 33, and the second operation opening 34, the payout of a predetermined number of game balls is executed. Specifically regarding the number of prize balls, when one game ball enters the first operation opening 33 or when one game ball enters the second operation opening 34, the payout of one prize ball is executed. When one game ball enters the general winning opening 31, the payout of 10 prize balls is executed. When one game ball enters the special electric winning device 32, the payout of 15 prize balls is executed.

[0022] Incidentally, the number of prize balls is arbitrary. For example, the second operation port 34 may be configured to have a smaller number of prize balls than the first operation port 33, or the second operation port 34 may be configured to have a larger number of prize balls than the first operation port 33.

[0023] In addition, an out port 24a is provided at the lowermost part of the game board 24, and game balls that have not entered various winning ports or the like are discharged from the game area PA through the out port 24a. Also, a large number of pins 24b are implanted in the game board 24 to appropriately disperse and adjust the falling direction of the game balls, and various members such as windmills are arranged.

[0024] Here, "entering the ball" means that the game ball passes through a predetermined opening, and it includes not only the mode of being discharged from the game area PA after passing through the opening, but also the mode of continuing to flow down in the game area PA without being discharged from the game area PA after passing through the opening. However, in the following description, in order to clearly distinguish from the entry of the game ball into the out port 24a, the entry of the game ball into the general winning port 31, the special electric winning device 32, the first operation port 33, the second operation port 34, and the through gate 35 is also expressed as "winning".

[0025] The first operation port 33 and the second operation port 34 are unitized as an operation port device and installed on the game board 24. Both the first operation port 33 and the second operation port 34 are open upward. Also, the two operation ports 33 and 34 are arranged vertically with the first operation port 33 above. A general electric accessory 34a as a guide piece composed of a pair of left and right movable pieces is provided at the second operation port 34. In the closed state of the general electric accessory 34a, the game ball cannot win at the second operation port 34, and when the general electric accessory 34a is in the open state, winning at the second operation port 34 becomes possible.

[0026] A through gate 35 is provided on the upstream side in the flowing direction of the game ball from the second operation port 34. The through gate 35 has a through hole (not shown) penetrating in the vertical direction, and the game ball that has won at the through gate 35 flows down in the game area PA after winning. Thereby, it is possible for the game ball that has won at the through gate 35 to win at the second operation port 34.

[0027] Based on winning the through gate 35, the normal power role 34a of the second operating port 34 is switched from a closed state to an open state. Specifically, an internal lottery is performed with the winning of the through gate 35 as a trigger, and a variable picture display is performed on the normal map display section 38a of the normal map unit 38 provided in the lower right corner of the play area PA, which is an area where the game ball does not pass. Then, when the result of the internal lottery is a win for the electric role opening and the stop result corresponding to the result is displayed and the variable display of the normal map display section 38a is terminated, the state transitions to the normal power opening state. In the normal power opening state, the normal power role 34a is opened in a predetermined manner.

[0028] The map display unit 38a is composed of a segment display in which a plurality of segment light-emitting parts are arranged in a predetermined manner, but is not limited thereto, and may be composed of other types of display devices such as a liquid crystal display device, an organic EL display device, a CRT, or a dot matrix display device. As for the pattern displayed variably on the map display unit 38a, a configuration in which a plurality of characters are displayed variably, a configuration in which a plurality of symbols are displayed variably, a configuration in which a plurality of characters are displayed variably, or a configuration in which a plurality of colors are displayed in a switched manner may be considered.

[0029] In the normal map unit 38, a normal map reserve display section 38b is provided adjacent to the normal map display section 38a. The number of game balls that enter the through gate 35 is reserved up to a maximum of four, and the number of reserved balls is displayed by lighting up the normal map reserve display section 38b.

[0030] A winning lottery is held by triggering a winning entry into the first operating port 33 or the second operating port 34. The lottery result is then displayed clearly through the display effects on the special symbol unit 37 and the symbol display device 41 of the variable display unit 36.

[0031] Regarding the special figure unit 37 in detail, the special figure unit 37 is provided with a special figure display section 37a. The display area of the special figure display section 37a is narrower than the display surface 41a of the symbol display device 41. In the special figure display section 37a, based on winning at the first operation port 33 or winning at the second operation port 34 as a trigger, a hit lottery is conducted, and thus a variable display of the pattern or a predetermined display is performed. Then, a result corresponding to the lottery result is displayed. Note that the special figure display section 37a is constituted by a segment display device in which a plurality of segment light emitting sections are arranged in a predetermined manner, but it is not limited thereto, and it may be constituted by other types of display devices such as a liquid crystal display device, an organic EL display device, a CRT, or a dot matrix display. Also, as for the pattern displayed in the special figure display section 37a, a configuration in which a plurality of types of characters are displayed, a configuration in which a plurality of types of symbols are displayed, a configuration in which a plurality of types of characters are displayed, or a configuration in which a plurality of types of colors are displayed, etc. are conceivable.

[0032] In the special figure unit 37, at a position adjacent to the special figure display section 37a, a special figure hold display section 37b is provided. The number of game balls that have won at the first operation port 33 or the second operation port 34 is held up to a maximum of 4, and the held number is displayed by lighting the special figure hold display section 37b.

[0033] Regarding the symbol display device 41 in detail, the symbol display device 41 is configured as a liquid crystal display device equipped with a liquid crystal display, and the display content is controlled by a display control device described later. Note that the symbol display device 41 is not limited to a liquid crystal display device, and it may be another display device having a display screen such as a plasma display device, an organic EL display device, or a CRT, or it may be a dot matrix display.

[0034] In the symbol display device 41, when a winning occurs at the first operation port 33 or the second operation port 34 and a variable display of symbols or a predetermined display is performed in the special symbol display unit 37a, a variable display of symbols or a predetermined display is performed accordingly. For example, on the display surface 41a of the symbol display device 41, three symbol columns, namely an upper row, a middle row, and a lower row, are set as a plurality of display areas, and main symbols with numbers from "1" to "9" are arranged in ascending or descending order in each symbol column and are scrolled and displayed. In this scroll display, first, the scroll display in all symbol columns is started, and the scroll display is switched to the standby display in the order of the upper symbol column → the lower symbol column → the middle symbol column, and finally, it ends with a predetermined symbol being statically displayed in each symbol column. And in a game round where the game result is a big win result, a combination of predetermined symbols is stopped and displayed on an effective line preset on the display surface 41a of the symbol display device 41. Specifically, when it becomes the most advantageous big win result described later, a combination of the same odd symbols is stopped and displayed, when it becomes the low probability big win result described later, a combination of the same even symbols is stopped and displayed, and when it becomes the low winning high probability big win result described later, a combination of symbols that is not the same combination but is not a low winning high probability big win result and is not stopped and displayed in normal cases is stopped and displayed.

[0035] Note that in the symbol display device 41, not only the display effect triggered by winning at the first operation port 33 or the second operation port 34, but also the display effect during the opening and closing execution mode that transitions after winning and being selected is performed. Also, based on winning at any of the operation ports 33, 34, the display is started in the special symbol display unit 37a and the symbol display device 41, and one game round corresponds to the period from the start of the display until a predetermined result is displayed and ended. Also, the mode of the variable display of symbols in the symbol display device 41 is not limited to the above and is arbitrary, and the number of symbol columns, the direction of the variable display of symbols in the symbol column, the number of symbols in each symbol column, etc. can be changed as appropriate. Also, the symbols that are variably displayed in the symbol display device 41 are not limited to the symbols as described above, and for example, a configuration where only numbers are variably displayed as symbols may be adopted.

[0036] When winning the jackpot in the jackpot lottery based on winning the first operation port 33 or the second operation port 34, it shifts to the opening / closing execution mode in which winning the special electric winning device 32 becomes possible. The special electric winning device 32 includes a big winning port (not shown) leading to the back side of the game board 24, and an opening / closing door 32a for opening and closing the big winning port. The opening / closing door 32a is arranged in either a closed state or an open state. Specifically, the opening / closing door 32a is normally in a closed state where game balls cannot win, and is switched to an open state where game balls can win when winning the shift to the opening / closing execution mode in the internal lottery. Incidentally, the opening / closing execution mode is a mode that will shift when a winning result occurs. Note that in the closed state, winning is not impossible, but it may be configured such that winning is less likely to occur than in the open state.

[0037] FIG. 4 is an explanatory diagram for explaining the configuration related to the discharge of game balls flowing down in the game area PA.

[0038] As already described, game balls that enter any of the general winning port 31, the special electric winning device 32, the first operation port 33, the second operation port 34, and the out port 24a are discharged from the game area PA. In other words, game balls launched from the game ball launching mechanism 27 and flowing into the game area PA are discharged from the game area PA by entering any of the general winning port 31, the special electric winning device 32, the first operation port 33, the second operation port 34, and the out port 24a. Game balls that enter any of the general winning port 31, the special electric winning device 32, the first operation port 33, the second operation port 34, and the out port 24a are guided to the back side of the game board 24.

[0039] On the back surface of the game board 24, discharge passage portions 42 to 48 are formed corresponding to the general winning opening 31, the special electric winning device 32, the first operation opening 33, the second operation opening 34, and the out opening 24a, respectively. The game balls that have flowed into the discharge passage portions 42 to 48 flow down through the discharge passage portions 42 to 48 into which they have flowed, and are guided to the lower end portion of the game board 24 on the back side of the game board 24 and collected by a discharge ball collection portion (not shown). Then, the game balls collected by the discharge ball collection portion are discharged to the ball circulation device of the island facility where the pachinko machine 10 is installed in the game hall.

[0040] Each of the discharge passage portions 42 to 48 is provided with various detection sensors 42a to 48a for detecting game balls. The discharge passage portions 42 to 48 and the detection sensors 42a to 48a will be described below. Since four general winning openings 31 are provided as already described, there are discharge passage portions 42 to 44 corresponding to each of the four. In this case, one detection sensor 42a, 43a is provided for each of the first discharge passage portion 42 corresponding to the leftmost general winning opening 31 and the second discharge passage portion 43 corresponding to the general winning opening 31 adjacent thereto on the right. Specifically, the first winning opening detection sensor 42a is provided at an intermediate position in the first discharge passage portion 42 so that a detection range exists, and the second winning opening detection sensor 43a is provided at an intermediate position in the second discharge passage portion 43 so that a detection range exists. A game ball that has entered the leftmost general winning opening 31 is detected by the first winning opening detection sensor 42a while passing through the first discharge passage portion 42, and a game ball that has entered the general winning opening 31 adjacent thereto on the right is detected by the second winning opening detection sensor 43a while passing through the second discharge passage portion 43. Further, a third discharge passage portion 44 is provided so as to merge at an intermediate position with respect to the two general winning openings 31 on the right side. The third discharge passage portion 44 has an entrance side region corresponding to each of the two general winning openings 31, and has one exit side region by the entrance side regions merging on the way. The third winning opening detection sensor 44a is provided at an intermediate position in the exit side region of the third discharge passage portion 44 so that a detection range exists. A game ball that has entered any of the two general winning openings 31 on the right side is detected by the third winning opening detection sensor 44a while passing through the third discharge passage portion 44.

[0041] There is a fourth discharge passage portion 45 corresponding to the special-electric winning device 32. A special-electric detection sensor 45a is provided such that a detection range exists at an intermediate position of the fourth discharge passage portion 45. The game ball that has entered the special-electric winning device 32 is detected by the special-electric detection sensor 45a while passing through the fourth discharge passage portion 45. There is a fifth discharge passage portion 46 corresponding to the first operation port 33. A first operation port detection sensor 46a is provided such that a detection range exists at an intermediate position of the fifth discharge passage portion 46. The game ball that has entered the first operation port 33 is detected by the first operation port detection sensor 46a while passing through the fifth discharge passage portion 46. There is a sixth discharge passage portion 47 corresponding to the second operation port 34. A second operation port detection sensor 47a is provided such that a detection range exists at an intermediate position of the sixth discharge passage portion 47. The game ball that has entered the second operation port 34 is detected by the second operation port detection sensor 47a while passing through the sixth discharge passage portion 47. There is a seventh discharge passage portion 48 corresponding to the out port 24a. An out port detection sensor 48a is provided such that a detection range exists at an intermediate position of the seventh discharge passage portion 48. The game ball that has entered the out port 24a is detected by the out port detection sensor 48a while passing through the seventh discharge passage portion 48.

[0042] Note that the game ball detected by any one of the various detection sensors 42a to 48a will not be detected by the other detection sensors 42a to 48a. Also, a gate detection sensor 49a is provided for the through gate 35, and the game ball passing through the through gate 35 while flowing down in the game area PA is detected by the gate detection sensor 49a.

[0043] As various detection sensors 42a to 49a, electromagnetic induction type proximity sensors are all used, but the sensors to be used are arbitrary as long as they can individually detect game balls. Further, the various detection sensors 42a to 49a are electrically connected to a main control device 60 described later, and the detection results of the various detection sensors 42a to 49a are output to the main control device 60. Specifically, the various detection sensors 42a to 49a output a LOW level signal in a situation where no game ball is detected, and output a HI level signal in a situation where a game ball is detected. Note that it is not limited to this, and the relationship between HI and LOW may be reversed.

[0044] As shown in FIG. 2, a front door frame 14 is provided so as to cover the entire front side of an inner frame 13 to which the game board 24 having the above-described configuration is attached to a resin base 21. As shown in FIG. 1, a window portion 51 is formed in the front door frame 14 so that substantially the entire game area PA can be visually recognized from the front. The window portion 51 has a substantially elliptical shape, and a window panel 52 is fitted therein. The window panel 52 is formed of glass to be colorless and transparent, but it is not limited to this, and it may be formed of synthetic resin to be colorless and transparent, or may be formed of colored transparent as long as the game area PA can be visually recognized through the window panel 52 from the front of the pachinko machine 10.

[0045] A display light emitting portion 53 is provided above the window portion 51. Further, a pair of left and right speaker portions 54 for outputting sound effects and the like according to the game state are provided. Further, below the window portion 51, an upper bulging portion 55 bulging forward and a lower bulging portion 56 are arranged side by side vertically. An upper dish 55a opening upward is provided inside the upper bulging portion 55, and a lower dish 56a also opening upward is provided inside the lower bulging portion 56. The upper dish 55a has a function of temporarily storing game balls paid out from a payout device described later and guiding them to the game ball launching mechanism 27 side while aligning them in a row. Further, the lower dish 56a has a function of storing surplus game balls in the upper dish 55a.

[0046] Next, the configuration on the back side of the game machine main body 12 will be described.

[0047] As shown in FIG. 2, a main control device 60 that controls the main game operations is mounted on the back surface of the inner frame 13 (specifically, the game board 24). FIG. 5 is a front view of the main control device 60.

[0048] As shown in FIG. 5, the main control device 60 includes a main control board 61 housed in a board box 60a. An MPU 62 is mounted on the element mounting surface, which is one of the board surfaces of the main control board 61. The board box 60a is formed transparently so that the MPU 62 housed in the board box 60a can be visually observed from the outside of the board box 60a. Although the board box 60a is formed colorlessly and transparently, it may be formed with colored transparency as long as the MPU 62 housed in the board box 60a can be visually observed from the outside of the board box 60a. The main control device 60 is mounted on the back surface of the resin base 21 such that the opposing wall portion 60b of the board box 60a facing the element mounting surface of the main control board 61 faces the rear of the pachinko machine 10. Therefore, by opening the game machine main body 12 forward with respect to the outer frame 11 to expose the back surface of the resin base 21, it becomes possible to visually observe the opposing wall portion 60b of the board box 60a and also to visually observe the MPU 62 through the opposing wall portion 60b.

[0049] The substrate box 60a is formed by combining a plurality of case bodies 60c in the front-rear direction. In these plurality of case bodies 60c, there are provided coupling portions 60e for preventing the separation of these case bodies 60c and leaving a trace when separating these case bodies 60c. The coupling portions 60e are arranged in parallel on one side of the substantially rectangular parallelepiped-shaped substrate box 60a. Thus, even if the case body 60c is separated by destroying a part of the coupling portions 60e in a state where the separation of the case body 60c is prevented by using a part of the coupling portions 60e, it is possible to prevent the separation of the case body 60c again by making another coupling portion 60e in a coupled state later. Further, when the coupling portion 60e is destroyed and a trace remains when the case body 60c is separated, it is possible to grasp whether the separation of the case body 60c is performed illegally by visually checking the coupling portion 60e. Further, on the side opposite to the side where the coupling portions 60e are arranged in parallel in the substrate box 60a, a sealing seal 60f is attached so as to straddle the boundary between the case bodies 60c. When the sealing seal 60f is peeled off, the adhesive layer remains on the case body 60c. Thus, when the sealing seal 60f is peeled off when the case body 60c is separated, it is possible to leave a trace.

[0050] In the main control device 60 configured as described above, on the main control board 61, there is a setting key insertion part 68a into which a setting key owned by the manager of the game hall is inserted and turned on to cause an opportunity to change the setting state of the pachinko machine 10 within the range from "Setting 1" to "Setting 6", an update button 68b that is operated to sequentially change the setting state of the pachinko machine 10 after the ON operation on the setting key insertion part 68a, a reset button 68c that is operated to clear the data of the main side RAM 65 provided in the MPU 62 of the main control device 60 described later, and first to third notification display devices 69a to 69c for notifying the management result of the game history. Also, on the MPU 62 mounted on the main control board 61, there is a reading terminal 68d for connecting the connection terminal of the external device to read the management result of the game history or the information (program and data) stored in the main side ROM 64 by the external device. Note that the setting state of the pachinko machine 10 is not limited to six levels from "Setting 1" to "Setting 6" and can be arbitrarily set as long as there are multiple levels.

[0051] These setting key insertion part 68a, update button 68b, reset button 68c, reading terminal 68d (that is, MPU 62), and first to third notification display devices 69a to 69c are all provided on the element mounting surface of the main control board 61. Also, as already described, the element mounting surface of the main control board 61 faces the opposing wall part 60b of the board box 60a, but the setting key insertion part 68a, update button 68b, reset button 68c, and reading terminal 68d are not covered by the opposing wall part 60b. That is, in the opposing wall part 60b, regions facing the setting key insertion part 68a, update button 68b, reset button 68c, and reading terminal 68d respectively are individual openings. Thereby, it is possible to insert the setting key into the setting key insertion part 68a, press the update button 68b, press the reset button 68c, and connect the connection terminal of the external device to the reading terminal 68d without requiring the opening of the board box 60a.

[0052] When a setting key is inserted into the setting key insertion part 68a and rotated in a predetermined direction, the setting key insertion part 68a is turned on. By starting the supply of operating power to the pachinko machine 10 in this state (that is, by starting the supply of operating power to the MPU 62 of the main control device 60), a changeable state in which the setting state of the pachinko machine 10 can be changed is achieved. Then, each time the update button 68b is pressed once in this state, the setting state of the pachinko machine 10 is changed step by step in ascending order within the range of "Setting 1" to "Setting 6". When the update button 68b is operated in the state of "Setting 6", it is updated to "Setting 1". Also, by rotating the setting key inserted into the setting key insertion part 68a in the direction opposite to the predetermined direction from the ON operation position and returning it to the initial position, the setting key insertion part 68a is turned off. When the setting key insertion part 68a is turned off, the changeable state ends, and a state is achieved in which the game can be played with the setting value state at that time. That is, even if the update button 68b is operated after the changeable state ends, the setting value cannot be changed.

[0053] The ON operation on the setting key insertion part 68a is valid only when the supply of operating power to the pachinko machine 10 is started (that is, when the supply of operating power to the MPU 62 of the main control device 60 is started). Therefore, even if an ON operation is performed on the setting key insertion part 68a after the processing at the start of the supply of operating power is completed in the MPU 62 of the main control device 60, the setting value cannot be changed.

[0054] The setting state of the pachinko machine 10 determines the degree of advantage per unit time in the pachinko machine 10. The larger the value of n in "Setting n" (n is an integer from "1" to "6") (that is, the higher the setting value), the higher the degree of advantage. Details will be described later, but there are a low probability mode in which the winning probability of the jackpot result is relatively low and a high probability mode in which the winning probability is relatively high as the winning or losing lottery mode for determining the winning probability of the jackpot result. The winning probability of the jackpot result in the low probability mode is set to increase as the setting value increases. On the other hand, the winning probability of the jackpot result in the high probability mode is constant regardless of the setting value.

[0055] The reset button 68c is operated to clear the data in the main-side RAM 65 as described above. However, in order to cause the clearing of the data, it is necessary to start supplying operating power to the pachinko machine 10 while the reset button 68c is being pressed (that is, it is necessary to start supplying operating power to the MPU 62 of the main control device 60). The ON operation for the reset button 68c is effective only when starting to supply operating power to the pachinko machine 10 (that is, when starting to supply operating power to the MPU 62 of the main control device 60). Therefore, even if the reset button 68c is pressed after the processing at the start of supplying operating power in the MPU 62 of the main control device 60 is completed, the data in the main-side RAM 65 cannot be cleared.

[0056] As already described, the read terminal 68d has the connection terminal of the external device connected to read the management result of the game history or the information (programs and data) stored in the main-side ROM 64 by the external device. However, in order to perform external output to the external device, it is necessary to start supplying operating power to the pachinko machine 10 while the connection terminal of the external device is connected to the read terminal 68d (that is, it is necessary to start supplying operating power to the MPU 62 of the main control device 60). The connection of the external device to the read terminal 68d is effective only when starting to supply operating power to the pachinko machine 10 (that is, when starting to supply operating power to the MPU 62 of the main control device 60). Therefore, even if an external device is connected to the read terminal 68d after the processing at the start of supplying operating power in the MPU 62 of the main control device 60 is completed, external output to the external device is not performed.

[0057] Each of the first to third notification display devices 69a to 69c is a segment display in which seven display segments using LEDs are arranged, but it is not limited to this, and it may be a single light emitter of a multicolor light emission type, a liquid crystal display device, or an organic EL display. Each of the first to third notification display devices 69a to 69c is installed such that its display surface faces the direction in which the element mounting surface of the main control board 61 faces, and is covered by the opposing wall portion 60b of the board box 60a. In this case, since the board box 60a is formed transparently, it is possible to visually observe the display surfaces of the first to third notification display devices 69a to 69c accommodated in the board box 60a from the outside of the board box 60a. Also, as already described, since the main control device 60 is mounted on the back surface of the resin base 21 such that the opposing wall portion 60b facing the element mounting surface of the main control board 61 in the board box 60a faces the rear of the pachinko machine 10, when the game machine main body 12 is opened forward of the pachinko machine 10 with respect to the outer frame 11 and the back surface of the resin base 21 is exposed forward of the pachinko machine 10, it is possible to visually observe the display surfaces of the first to third notification display devices 69a to 69c through the opposing wall portion 60b.

[0058] On the display surface of the first notification display device 69a, various characters including alphabetic characters as well as the numbers from "0" to "9" are displayed. On the other hand, on the second notification display device 69b and the third notification display device 69c, the numbers from "0" to "9" are displayed. The management results of the game history are notified using the first to third notification display devices 69a to 69c, and the details of this notification will be described later. Also, in a changeable state where the setting state of the pachinko machine 10 can be changed, a value corresponding to the current setting value is displayed on the third notification display device 69c. Note that the value corresponding to the setting value may be configured to be displayed on the first notification display device 69a, or may be configured to be displayed on the second notification display device 69b. Also, the setting value before entering the changeable state may be displayed on one of the first to third notification display devices 69a to 69c, and the current setting value may be displayed on another one of the first to third notification display devices 69a to 69c.

[0059] As shown in FIG. 2, a back pack unit 15 is installed so as to cover the back side of the inner frame 13 including the main control device 60. The back pack unit 15 includes a back pack 72 formed of a synthetic resin having transparency, and a payout mechanism unit 73 and a control device assembly unit 74 are attached to the back pack 72.

[0060] The payout mechanism unit 73 includes a tank 75 to which game balls supplied from the island equipment in the game hall are sequentially replenished, and a payout device 76 for paying out the game balls stored in the tank 75. The game balls paid out from the payout device 76 are discharged to the upper tray 55a or the lower tray 56a through a payout passage provided on the downstream side of the payout device 76. Note that the payout mechanism unit 73 is supplied with, for example, a main power supply of 24 volts AC, and a back pack substrate having a power switch for performing ON and OFF operations of the power supply is mounted thereon.

[0061] The control device set unit 74 includes a payout control device 77 having a function of controlling the payout device 76, and a power supply / launch control device 78 that generates and outputs predetermined power required by various control devices and the like, and controls the launch of the game balls accompanying the operation of the launch operation device 28 by the player. These payout control device 77 and power supply / launch control device 78 are arranged one on top of the other in the front - rear direction so that the payout control device 77 is at the rear of the pachinko machine 10.

[0062] <Electrical Configuration of Pachinko Machine 10> FIG. 6 is a block diagram showing the electrical configuration of the pachinko machine 10.

[0063] The main control device 60 includes a main control board 61 that controls the main game, and a power failure monitoring board 67 that monitors the power supply. The main control board 61 is equipped with an MPU 62. In the MPU 62, in addition to the main - side CPU 63 which is an arithmetic processing device including a control unit and an arithmetic unit, a main - side ROM 64, a main - side RAM 65, and a management IC 66 are built - in. In addition to the above - mentioned elements, the MPU 62 also has a built - in interrupt circuit, a timer circuit, a data input / output circuit, and various counter circuits as a random number generator.

[0064] The main - side ROM 64 is a memory (that is, a non - volatile storage means) such as a NOR - type flash memory and a NAND - type flash memory that does not require external power supply for memory retention, and is used as read - only. The main - side ROM 64 stores various control programs and fixed - value data executed by the main - side CPU 63.

[0065] The main - side RAM 65 is a memory (that is, a volatile storage means) such as SRAM and DRAM that requires external power supply for memory retention, and is used for both reading and writing. The main - side RAM 65 allows random access and has a shorter read time than the main - side ROM 64 when compared with the same data capacity. The main - side RAM 65 temporarily stores various data for the execution of the control programs stored in the main - side ROM 64.

[0066] The management IC 66 is a management device that manages game history based on information supplied from the main CPU 63. Although details will be described later, the management IC 66 grasps the ball entry history of the general winning port 31, special electric winning device 32, first operation port 33, second operation port 34, and out port 24a, and based on the grasped ball entry history, the ball entry frequencies to the general winning port 31, special electric winning device 32, first operation port 33, and second operation port 34 are grasped. Also, the management IC 66 grasps the occurrence frequencies of the opening / closing execution mode and high-frequency support mode described later.

[0067] The MPU 62 is provided with an input port and an output port respectively. On the input side of the MPU 62, a power failure monitoring board 67 and a payout control device 77 provided in the main control device 60 are connected. A power supply / transmission control device 78 having a function of supplying operating power is connected to the power failure monitoring board 67, and operating power is supplied to the MPU 62 via the power failure monitoring board 67.

[0068] On the input side of the MPU 62, various sensors such as each ball entry detection sensor 42a to 49a are connected. As already described, each ball entry detection sensor 42a to 49a includes a first winning port detection sensor 42a, a second winning port detection sensor 43a, a third winning port detection sensor 44a, a special electric detection sensor 45a, a first operation port detection sensor 46a, a second operation port detection sensor 47a, an out port detection sensor 48a, and a gate detection sensor 49a. Based on the detection results of these ball entry detection sensors 42a to 49a, the main CPU 63 makes a ball entry determination for each ball entry part. Also, in the main CPU 63, various lotteries are executed based on winning at the first operation port 33 and various lotteries are executed based on winning at the second operation port 34.

[0069] On the input side of the MPU62, a setting key insertion part 68a, an update button 68b, and a reset button 68c provided on the main control board 61 are provided. A sensor (not shown) is provided in the setting key insertion part 68a, and the sensor detects whether the setting key insertion part 68a is arranged at the ON operation position or the OFF operation position. Then, the main CPU 63 specifies whether the setting key insertion part 68a is arranged at the ON operation position or the OFF operation position based on the detection result from the sensor. A sensor (not shown) is provided in the update button 68b, and the sensor detects whether the update button 68b is being pressed. Then, the main CPU 63 specifies whether the update button 68b is being pressed based on the detection result from the sensor. A sensor (not shown) is provided in the reset button 68c, and the sensor detects whether the reset button 68c is being pressed. Then, the main CPU 63 specifies whether the reset button 68c is being pressed based on the detection result from the sensor.

[0070] On the output side of the MPU62, a power failure monitoring board 67, a payout control device 77, and an audio-visual control device 81 are connected. For example, in the payout control device 77, a bonus ball command is output based on the fact that a game ball has entered the bonus ball corresponding ball entry part among the above-mentioned ball entry parts where the occurrence of ball entry corresponds to the payout of game balls. Various commands such as a variation command, a type command, and an opening command are output to the audio-visual control device 81.

[0071] On the output side of the MPU62, a special power drive unit 32b for opening and closing the opening / closing door 32a of the special power winning device 32, a general power drive unit 34b for opening and closing the general power component 34a of the second operation port 34, a special diagram unit 37, and a general diagram unit 38 are connected. Incidentally, the special diagram unit 37 is provided with a special diagram display section 37a and a special diagram hold display section 37b, and all of these are connected to the output side of the MPU62. Similarly, the general diagram unit 38 is provided with a general diagram display section 38a and a general diagram hold display section 38b, and all of these are connected to the output side of the MPU62. The main control board 61 is provided with various driver circuits, and through these driver circuits, the MPU62 executes drive control of various drive units and various display sections.

[0072] That is, in the opening / closing execution mode, drive control of the special power drive unit 32b is executed in the main CPU63 so that the special power winning device 32 is opened and closed. Also, when the general power component 34a is selected as the open state winning, drive control of the general power drive unit 34b is executed in the main CPU63 so that the general power component 34a is opened and closed. Also, in each game round, display control of the special diagram display section 37a is executed in the main CPU63. Also, when indicating the lottery result of whether or not to set the general power component 34a to the open state, display control of the general diagram display section 38a is executed in the main CPU63. Also, when a winning occurs at the first operation port 33 or the second operation port 34, or when variable display starts in the special diagram display section 37a, display control of the special diagram hold display section 37b is executed in the main CPU63, and when a winning occurs at the through gate 35, or when variable display starts in the general diagram display section 38a, display control of the general diagram hold display section 38b is executed in the main CPU63.

[0073] On the output side of the MPU62, first to third notification display devices 69a to 69c are connected. Also, the management result of the game history in the management IC66 is notified through the displays in the first to third notification display devices 69a to 69c. Further, when changing the setting state of the pachinko machine 10, the current setting value is displayed on the third notification display device 69c. In this case, the first notification display device 69a and the second notification display device 69b are under display control by the management IC66 and not under display control by the main CPU63, while the third notification display device 69c is under display control by the main CPU63 and also under display control by the management IC66. The display of the third notification display device 69c gives priority to the display control by the main CPU63 over the display control by the management IC66.

[0074] However, it is not limited to this, and the third notification display device 69c may also be configured to be under display control by the management IC66 and not under display control by the main CPU63. In this case, when displaying the current setting value on the third notification display device 69c when changing the setting state of the pachinko machine 10, it is advisable to adopt a configuration in which a display instruction of the setting value is given from the main CPU63 to the management IC66.

[0075] The MPU62 is provided with a reading terminal 68d. A sensor (not shown) is provided at the reading terminal 68d, and it is detected by the sensor whether a connection terminal of an external device is connected to the reading terminal 68d. Then, the main CPU63 specifies whether a connection terminal of an external device is connected to the reading terminal 68d based on the detection result from the sensor. Also, when an external device is connected to the reading terminal 68d, the management result of the game history in the management IC66 or the information (program and data) stored in the main ROM64 is externally output to the external device.

[0076] The power failure monitoring board 67 relays between the main control board 61 and the power supply / emission control device 78, and monitors the voltage of 24 VDC stabilized power, which is the maximum voltage output from the power supply / emission control device 78. The payout control device 77 controls the payout of prize balls and loaned balls by the payout device 76 based on the prize ball command received from the main control device 60.

[0077] The power supply / emission control device 78 is connected to a commercial power supply (external power supply) in a game hall or the like, for example. Then, based on the external power supplied from the commercial power supply, it generates the necessary operating power for the main control board 61, the payout control device 77, etc., respectively, and supplies the generated operating power. Incidentally, the power supply / emission control device 78 is provided with a power supply unit for power failure, such as a backup capacitor. Even when the power of the pachinko machine 10 is in the OFF state, power for storage retention is supplied from the power supply unit for power failure to the main side RAM 65 of the main control device 60 and the payout control device 77. In addition, the power supply / emission control device 78 is responsible for the emission control of the game ball emission mechanism 27, and the game ball emission mechanism 27 is driven when predetermined emission conditions are met. Further, as already described, the payout mechanism unit 73 is provided with a power switch. When the power switch is turned on, the supply of operating power to the pachinko machine 10 is started, and when the power switch is turned off, the supply of operating power to the pachinko machine 10 is stopped.

[0078] The audio / light emission control device 81 drives and controls the display light emission unit 53 and the speaker unit 54 provided on the front door frame 14 based on various commands received from the main control device 60, and controls the display control device 82. The display control device 82 executes the display control of the symbol display device 41 based on the command received from the audio / light emission control device 81.

[0079] <Electrical configuration for performing various lotteries by the main side CPU 63> Next, the electrical configuration for performing various lotteries by the main side CPU 63 will be described with reference to FIG. 7.

[0080] During the game, the main CPU 63 uses various counter information to perform jackpot occurrence lottery, setting of the display of the special drawing display unit 37a, setting of the symbol display of the symbol display device 41, setting of the display of the normal drawing display unit 38a, etc. Specifically, as shown in FIG. 7, a jackpot random number counter C1 used for the lottery of jackpot occurrence, a jackpot type counter C2 used for determining the jackpot type, a reach random number counter C3 used for the reach occurrence lottery when the symbol display device 41 fluctuates out of range, a random number initial value counter CINI used for setting the initial value of the jackpot random number counter C1, and a variation type counter CS for determining the display duration in the special drawing display unit 37a and the symbol display device 41 are used. Further, a general electric accessory release counter C4 used for the lottery of whether to put the general electric accessory 34a of the second operation port 34 in the general electric open state is used. Each of the above counters C1 to C3, CINI, CS, and C4 is provided in various counter areas 65b of the main RAM 65.

[0081] Each of the counters C1 to C3, CINI, CS, and C4 is a loop counter that adds 1 to the previous value each time it is updated and returns to "0" after reaching the maximum value. Each counter is updated at short time intervals. Information corresponding to the jackpot random number counter C1, the jackpot type counter C2, and the reach random number counter C3 is stored in a hold storage area 65a provided as acquisition information storage means in the main RAM 65 when a winning occurs at the first operation port 33 or the second operation port 34.

[0082] The hold storage area 65a includes a hold area RE and an execution area AE. The hold area RE includes a first hold area RE1, a second hold area RE2, a third hold area RE3, and a fourth hold area RE4. According to the winning history at the first operation port 33 or the second operation port 34, a combination of numerical information of the jackpot random number counter C1, the jackpot type counter C2, and the reach random number counter C3 is stored as hold information in any one of the hold areas RE1 to RE4.

[0083] In this case, in the first to fourth hold areas RE1 to RE4, when a winning in the first operation port 33 or the second operation port 34 occurs continuously multiple times, each numerical information is stored in chronological order in the order of the first hold area RE1 → the second hold area RE2 → the third hold area RE3 → the fourth hold area RE4. By providing the four hold areas RE1 to RE4 in this way, the winning history of the game balls in the first operation port 33 or the second operation port 34 can be stored in hold memory up to a maximum of four.

[0084] Note that the number that can be stored in hold memory is not limited to four and can be arbitrary, and can be other plural numbers such as two, three, or five or more, or can be a single number.

[0085] The execution area AE is an area for moving each numerical information stored in the first hold area RE1 of the hold area RE when starting the variable display of the special figure display unit 37a. At the start of one game round, a win / loss determination or the like is performed based on various numerical information stored in the execution area AE.

[0086] Each of the above counters will be described in detail.

[0087] First, the general power item release counter C4 will be described. The general power item release counter C4 is configured to be incremented by 1 in order within a range of, for example, 0 to 250, and to return to "0" after reaching the maximum value. The general power item release counter C4 is updated regularly and is stored in the general power hold area 65c of the main side RAM 65 at the timing when a game ball wins in the through gate 35. Then, at a predetermined timing, a lottery is performed to determine whether to control the general power item 34a to an open state based on the value of the stored general power item release counter C4.

[0088] In this pachinko machine 10, a plurality of types of support modes are set so that the support modes by the general electric component 34a are different from each other. Specifically, in the support mode, when compared with the situation where the shooting of the game balls continues in the same manner in the game area PA, the high-frequency support mode and the low-frequency support mode are set so that the frequency of the general electric component 34a of the second operation port 34 being in the open state per unit time is relatively high or low.

[0089] In the high-frequency support mode and the low-frequency support mode, the probability of winning the general electric open state in the general electric open lottery using the general electric open counter C4 is the same (for example, both are 4 / 5). However, in the high-frequency support mode, compared with the low-frequency support mode, when winning the general electric open state, the number of times the general electric component 34a is in the open state is set to be larger, and furthermore, the opening time for one time is set to be longer. In this case, when winning the general electric open state in the high-frequency support mode and the open state of the general electric component 34a occurs multiple times, the closing time from the end of one open state to the start of the next open state is set to be shorter than the opening time for one time. Furthermore, in the high-frequency support mode, compared with the low-frequency support mode, the guaranteed time (that is, the display duration for one time in the general diagram display unit 38a) that is minimally guaranteed when the next general electric open lottery is conducted after one general electric open lottery is set to be shorter.

[0090] As described above, in the high-frequency support mode, the probability of winning a prize at the second operation port 34 is higher than that in the low-frequency support mode. In other words, in the low-frequency support mode, the probability of winning a prize at the first operation port 33 is higher than that at the second operation port 34, but in the high-frequency support mode, the probability of winning a prize at the second operation port 34 is higher than that at the first operation port 33. When a prize is won at the second operation port 34, a predetermined number of game balls are paid out. Therefore, in the high-frequency support mode, the player can play the game while not reducing the number of balls in hand too much.

[0091] Note that the configuration for making the frequency of the general power release state per unit time higher in the high-frequency support mode than in the low-frequency support mode is not limited to the above, and for example, it may be a configuration for increasing the probability of winning the general power release state in the general power release lottery. Further, in a configuration in which a plurality of types of guaranteed times (for example, the time of the variable display executed by the general drawing display unit 38a based on winning in the through gate 35) are prepared for the next general power release lottery after one general power release lottery is performed, in the high-frequency support mode, a shorter guaranteed time may be more likely to be selected or the average guaranteed time may be set to be shorter than in the low-frequency support mode. Furthermore, by applying any one condition or an arbitrary combination of conditions among increasing the number of release times, increasing the release time, shortening the guaranteed time ensured for the next general power release lottery after one general power release lottery is performed, shortening the average time of such guaranteed times, and increasing the winning probability, the advantage of the high-frequency support mode over the low-frequency support mode may be enhanced.

[0092] Here, as already described, the pachinko machine 10 has setting states of "Setting 1" to "Setting 6", but the release frequency and release mode of the general power device 34a in the low-frequency support mode are the same regardless of any set value, and the release frequency and release mode of the general power device 34a in the high-frequency support mode are also the same regardless of any set value. However, it is not limited to this, and a configuration may be adopted in which at least one of the release frequency and release mode of the general power device 34a varies according to the setting state of the pachinko machine 10 for at least one of the low-frequency support mode and the high-frequency support mode. For example, the higher the set value, the higher the release frequency of the general power device 34a in the low-frequency support mode may be, and the higher the probability of a game ball entering the second operating port 34 when the general power device 34a is in the open state once in the low-frequency support mode may be. Also, the higher the set value, the higher the release frequency of the general power device 34a in the high-frequency support mode may be, and the higher the probability of a game ball entering the second operating port 34 when the general power device 34a is in the open state once in the high-frequency support mode may be.

[0093] Next, the winning random number counter C1 will be described. The winning random number counter C1 is configured to be incremented by 1 in sequence within a range of, for example, 0 to 599, and return to "0" after reaching the maximum value. In particular, when the winning random number counter C1 makes one full cycle, the value of the random number initial value counter CINI at that time is read as the initial value of the winning random number counter C1. Note that the random number initial value counter CINI is a loop counter similar to the winning random number counter C1 (value = 0 to 599). The winning random number counter C1 is updated periodically and stored in the reserved storage area 65a of the main-side RAM 65 at the timing when the game ball wins the first operation port 33 or the second operation port 34.

[0094] The values of the random numbers for a big win are stored in the main-side ROM 64 as a hit or miss table. FIG. 8 is an explanatory diagram for explaining various tables stored in the main-side ROM 64. As the hit or miss table, low-probability hit or miss tables 64a to 64f for the low-probability mode and a high-probability hit or miss table 64g for the high-probability mode are stored.

[0095] The low-probability hit or miss tables 64a to 64f are provided in a one-to-one correspondence with the setting states of "Setting 1" to "Setting 6". That is, the low-probability hit or miss table 64a for Setting 1 to be referred to when the setting state of the pachinko machine 10 is "Setting 1", the low-probability hit or miss table 64b for Setting 2 to be referred to when the setting state of the pachinko machine 10 is "Setting 2", the low-probability hit or miss table 64c for Setting 3 to be referred to when the setting state of the pachinko machine 10 is "Setting 3", the low-probability hit or miss table 64d for Setting 4 to be referred to when the setting state of the pachinko machine 10 is "Setting 4", the low-probability hit or miss table 64e for Setting 5 to be referred to when the setting state of the pachinko machine 10 is "Setting 5", and the low-probability hit or miss table 64f for Setting 6 to be referred to when the setting state of the pachinko machine 10 is "Setting 6" exist.

[0096] These low hit probability tables 64a to 64f are set such that the higher the setting value, the higher the winning probability of a big win result. Specifically, when the low hit probability table 64a for setting 1 is referred to, the big win result occurs at approximately 1 / 320; when the low hit probability table 64b for setting 2 is referred to, the big win result occurs at approximately 1 / 310; when the low hit probability table 64c for setting 3 is referred to, the big win result occurs at approximately 1 / 300; when the low hit probability table 64d for setting 4 is referred to, the big win result occurs at approximately 1 / 290; when the low hit probability table 64e for setting 5 is referred to, the big win result occurs at approximately 1 / 280; and when the low hit probability table 64f for setting 6 is referred to, the big win result occurs at approximately 1 / 270. As a result, the higher the setting state of the pachinko machine 10, the more likely a big win result will occur in the low probability mode, which is advantageous for the player.

[0097] On the other hand, only one type of high hit probability table 64g is provided so as to be common in any setting state from "Setting 1" to "Setting 6". The high hit probability table 64g is set such that the winning probability of a big win result is higher than that of the low hit probability tables 64a to 64f in any setting state from "Setting 1" to "Setting 6". Specifically, when the high hit probability table 64g is referred to, the big win result occurs at approximately 1 / 30. As a result, it becomes possible to make the high probability mode more advantageous than the low probability mode regardless of the setting state of the pachinko machine 10. Also, even in the lowest setting state of "Setting 1", by setting it to the high probability mode, it becomes possible to increase the probability of getting a big win result compared to the low probability mode of the highest setting state of "Setting 6". In addition, it becomes possible to prevent the high probability mode from being advantageous or disadvantageous depending on the setting state of the pachinko machine 10, and it also becomes possible to suppress the storage capacity for preliminarily storing the high hit probability table 64g in the main side ROM 64.

[0098] The jackpot type counter C2 is configured to be incremented by 1 in sequence within the range of 0 to 29, and return to "0" after reaching the maximum value. The jackpot type counter C2 is updated periodically and stored in the hold storage area 65a at the timing when the game ball wins the first activation port 33 or the second activation port 34.

[0099] In this pachinko machine 10, a plurality of jackpot results are set. These multiple jackpot results are set by providing differences in three conditions: (1) the opening and closing control mode of the special electric winning device 32 in the opening and closing execution mode, (2) the lottery mode in the winning or losing lottery means after the end of the opening and closing execution mode, and (3) the support mode in the general electric accessory 34a of the second activation port 34 after the end of the opening and closing execution mode.

[0100] As the opening and closing control mode of the special electric winning device 32 in the opening and closing execution mode, a high-frequency winning mode and a low-frequency winning mode are set so that the frequency of winning the special electric winning device 32 becomes relatively high or low from the start to the end of the opening and closing execution mode. Specifically, in either the high-frequency winning mode or the low-frequency winning mode, the round game is executed with a predetermined number of rounds as the upper limit.

[0101] The round game is a game that continues until either the condition that a predetermined upper limit duration has elapsed or the condition that a predetermined upper limit number of game balls win the special electric winning device 32 is satisfied. Also, the number of rounds of the round game in the opening and closing execution mode triggered by the jackpot result is the same fixed number of rounds regardless of the type of jackpot result that triggers the transition. Specifically, the upper limit number of rounds of the round game is set to 15 rounds regardless of the jackpot result.

[0102] In addition, in this pachinko machine 10, multiple types of release modes of the special electric winning device 32 are set by varying the release duration from when the special electric winning device 32 is released until it is closed. Specifically, a long-duration mode set to 29 seconds with a long release duration and a short-duration mode set to 0.06 seconds, which is shorter than the long duration, are set.

[0103] In this pachinko machine 10, when the launch operation device 28 is being operated by the player, the game ball launch mechanism 27 is driven and controlled so that one game ball is launched toward the game area PA every 0.6 seconds. Also, the upper limit number of end conditions for the round game is set to 9. Then, in the long-duration mode among the above release modes, a release duration longer than the product of the game ball launch cycle and one round game is set. On the other hand, in the short-duration mode, a release duration shorter than the product of the game ball launch cycle and one round game, more specifically, shorter than the game ball launch cycle, is set. Therefore, when one release is performed in the long-duration mode, it is expected that winnings corresponding to the upper limit number in one round game will occur for the special electric winning device 32, and when one release is performed in the short-duration mode, it is expected that no winnings will occur for the special electric winning device 32 or, if winnings do occur, only about one.

[0104] In the high-frequency winning mode, the special electric winning device 32 is released once in each round game in the long-duration mode. On the other hand, in the low-frequency winning mode, the special electric winning device 32 is released once in each round game in the short-duration mode.

[0105] Note that the number of openings and closings of the special electric winning device 32, the number of round games, the release duration for one release, and the upper limit number in one round game in the high-frequency winning mode and the low-frequency winning mode are not limited to the above values and are arbitrary as long as the frequency of winnings occurring for the special electric winning device 32 from the start to the end of the opening and closing execution mode is higher in the high-frequency winning mode than in the low-frequency winning mode.

[0106] The destination for distributing the jackpot result to the jackpot type counter C2 is stored as a distribution table 64h in the main-side ROM64 as shown in FIG. 8. In the distribution table 64h, the low-probability jackpot result, the low-win high-probability jackpot result, and the most advantageous jackpot result are set as the destinations for distributing the jackpot result when a jackpot result occurs.

[0107] The low-probability jackpot result is a jackpot result in which the opening / closing execution mode becomes the high-frequency winning mode, and after the end of the opening / closing execution mode, the win / loss lottery mode becomes the low-probability mode and the support mode becomes the high-frequency support mode. However, this high-frequency support mode shifts to the low-frequency support mode when the number of game plays reaches the end reference number of times (specifically, 100 times) after the shift.

[0108] The low-win high-probability jackpot result is a jackpot result in which the opening / closing execution mode becomes the low-frequency winning mode, and after the end of the opening / closing execution mode, the win / loss lottery mode becomes the high-probability mode and the support mode becomes the high-frequency support mode. These high-probability mode and high-frequency support mode continue until the lottery result in the win / loss lottery becomes a jackpot state win and a transition to the jackpot state occurs.

[0109] The most advantageous jackpot result is a jackpot result in which the opening / closing execution mode becomes the high-frequency winning mode, and after the end of the opening / closing execution mode, the win / loss lottery mode becomes the high-probability mode and the support mode becomes the high-frequency support mode. These high-probability mode and high-frequency support mode continue until the lottery result in the win / loss lottery becomes a jackpot state win and a transition to the jackpot state occurs.

[0110] Note that the normal game state in relation to each of the above game states refers to a state where the opening / closing execution mode is not in effect, the winning / losing lottery mode is the low-probability mode, and the support mode is the low-frequency support mode. Also, as a game result configuration, it may be such that a low-win high-probability jackpot result is not set. Further, in the opening / closing execution mode for the low-win high-probability jackpot result, the number of rounds of the round game may be configured to be less than that in the case of the low-probability jackpot result and the most advantageous jackpot result.

[0111] In the distribution table 64h, among the values of the jackpot type counter C2 from "0 to 29", "0 to 9" correspond to the low-probability jackpot result, "10 to 14" correspond to the low-win high-probability jackpot result, and "15 to 29" correspond to the most advantageous jackpot result.

[0112] The distribution table 64h is provided in only one type so as to be common regardless of any of the setting states from "Setting 1" to "Setting 6". As a result, it becomes possible to prevent any advantage or disadvantage due to the setting state of the pachinko machine 10 regarding the distribution mode of the jackpot result, and it also becomes possible to suppress the storage capacity for preliminarily storing the distribution table 64h in the main-side ROM 64.

[0113] Note that it may also be configured such that the distribution mode of the jackpot result differs according to the setting state of the pachinko machine 10. For example, it may be configured such that the higher the setting value, the higher the probability of being allocated to the most advantageous jackpot result. Or it may be configured such that the higher the setting value, the higher the probability of being allocated to the most advantageous jackpot result or the low-win high-probability jackpot result. In this case, it becomes possible to increase the probability of entering the high-probability mode after a jackpot result occurs as the setting value increases. Also, it may be configured such that the higher the setting value, the lower the probability of being allocated to the low-win high-probability jackpot result. Or it may be configured such that at a high setting value, it cannot be allocated to the low-win high-probability jackpot result, while at a low setting value, it can be allocated to the low-win high-probability jackpot result. In this case, it becomes possible to increase the probability of the opening / closing execution mode of the high-frequency winning mode occurring as the setting value increases.

[0114] Next, the reach random number counter C3 will be described. The reach random number counter C3 is configured to be incremented by 1 in sequence within a range of, for example, 0 to 238, and to return to "0" after reaching the maximum value. In this pachinko machine 10, an expected effect is set as a type of display effect in the symbol display device 41. The expected effect refers to a gaming machine that is equipped with a symbol display device 41 capable of performing variable display of symbols, and in a game round that results in a predetermined jackpot, the display state that makes the player think that it is a variable display state that is likely to be the given corresponding result in the stage before the stop result is derived and displayed after the variable display of the symbols in the symbol display device 41 is started. Specifically, for the given corresponding result, a combination of symbols with the same number assigned on any of the valid lines is stopped and displayed.

[0115] Two types of expected effects are set: a reach display and a preview display for expecting the occurrence of the reach display and the occurrence of the given corresponding result in the stage before the reach display occurs.

[0116] The reach display includes a display state in which a combination of reach symbols is displayed by stopping the display of symbols for some of the symbol columns among the plurality of symbol columns displayed on the display surface 41a of the symbol display device 41, and variable display of symbols is performed in the remaining symbol columns in that state. Also, in the state where the combination of reach symbols is displayed as described above, while performing variable display of symbols in the remaining symbol columns, a reach effect is performed by displaying a predetermined character or the like as a video on the background screen, or a reach effect is performed by reducing or hiding the combination of reach symbols and then displaying a predetermined character or the like as a video on substantially the entire display surface 41a.

[0117] The preview display includes a mode of displaying a character separately from the symbols on the symbol display column in a situation where the symbol variation display has started on the display surface 41a of the symbol display device 41, in a situation where the symbols are being variably displayed in all the symbol columns, or in a situation where the symbols are being variably displayed in some of the symbol columns, that is, in a plurality of symbol columns. Further included are those that change the background screen to a predetermined mode different from the previous mode, and those that change the symbols on the symbol display column to a predetermined mode different from the previous mode. Such a preview display can occur in any game round, whether or not a reach display is performed, but it is set to occur with a higher probability when a reach display is performed than when a reach display is not performed.

[0118] The reach display is executed regardless of the value of the reach random number counter C3 in a game round where the same combination of symbols is finally stopped and displayed. Also, in a game round corresponding to a jackpot result where the same combination of symbols is not stopped and displayed, it is not executed regardless of the value of the reach random number counter C3. Further, in a game round corresponding to a non-winning result, it is executed when the reach random number counter C3 obtained at a predetermined timing by referring to the reach table stored in the main-side ROM 64 corresponds to the occurrence of the reach display.

[0119] On the other hand, the decision of whether to perform the preview display is not made by the main control device 60 but by the audio-visual control device 81. In this case, the audio-visual control device 81 executes a lottery process for the preview display so as to satisfy at least one of the conditions that a preview display is more likely to occur in a game round corresponding to any jackpot result than in a game round corresponding to a non-winning result, and that a preview display with a low appearance rate is more likely to occur. Incidentally, the result of this lottery is reflected when an effect for the game is executed on the symbol display device 41.

[0120] Here, the probability of the occurrence of the reach display in a game turn that results in a losing outcome is the same regardless of the setting state among "Setting 1" to "Setting 6". This makes it possible to prevent any advantage or disadvantage due to the setting state of the pachinko machine 10 regarding the probability of the occurrence of the reach display in a game turn that results in a losing outcome. However, it is not limited to this, and it may be configured such that the higher the setting value, the higher the probability of the occurrence of the reach display in a game turn that results in a losing outcome.

[0121] Next, the variable type counter CS will be described. The variable type counter CS is configured to be incremented by 1 in order within a range of, for example, 0 to 198, and to return to "0" after reaching the maximum value. The variable type counter CS is used in the main CPU 63 to determine the display duration in the special figure display section 37a and the display duration of the symbols in the symbol display device 41. The variable type counter CS is updated once each time the timer interrupt process described later is executed once, and is repeatedly updated even within the remaining time until the next timer interrupt process is executed. Then, the buffer value of the variable type counter CS is acquired when determining the variable pattern at the start of the variable display in the special figure display section 37a and at the start of the symbol variation by the symbol display device 41.

[0122] <Regarding the processing configuration of the main CPU 63> Next, each process executed by the main CPU 63 to advance the game will be described. Such processes of the main CPU 63 are roughly classified into a main process that is started when the power is turned on and a timer interrupt process that is started periodically (at a cycle of 4 msec in this embodiment).

[0123] <Main process> First, the main process will be described with reference to the flowchart of FIG. 9.

[0124] First, execute the power-on wait process (step S101). In this power-on wait process, for example, after the main process is started, it waits without proceeding to the next process until a predetermined time for waiting (specifically, 1 sec) has elapsed. During the execution period of such a power-on wait process, the operation start and initial settings of the symbol display device 41 will be completed. After that, access to the main-side RAM 65 is permitted (step S102).

[0125] After that, it is determined whether the setting key insertion part 68a has been turned on (step S103). If the setting key insertion part 68a has not been turned on (step S103: NO), it is determined whether the reset button 68c has been pressed (step S104). If the reset button 68c has been pressed (step S104: YES), except for the area in the main-side RAM 65 where the information of the setting value indicating the setting state of the pachinko machine 10 is set, each area of the main-side RAM 65 is cleared to "0" (step S105). That is, when the supply of operating power to the pachinko machine 10 is started while pressing the reset button 68c without the ON operation of the setting key insertion part 68a, the clear process of the main-side RAM 65 is executed while maintaining the information of the setting value in the state before the supply of operating power to the pachinko machine 10 is stopped. Thereby, it becomes possible to initialize other areas of the main-side RAM 65 without requiring a change in the setting value.

[0126] When the reset button 68c is not being pressed (step S104: NO), it is determined whether the power failure flag is set to "1" (step S106). The power failure flag is provided in the main-side RAM 65, and when the power supply to the main-side CPU 63 is stopped and the predetermined power failure processing is executed normally, the power failure flag is set to "1". When the power failure flag is set to "1", it is determined whether the calculated checksum matches the checksum saved at the time of power-off, that is, the validity of the stored data is determined (step S107). When the process of step S105 is executed, or when an affirmative determination is made in step S107, it is determined whether the set value of the pachinko machine 10 is normal by checking the main-side RAM 65 (step S108). Specifically, it is determined to be normal when the set value is any one of "Setting 1" to "Setting 6", and abnormal when it is "0" or 7 or more.

[0127] If a negative determination is made in any of steps S106 to S108, the operation prohibition process is executed. In the operation prohibition process, after executing an error notification process for notifying the hall manager or the like of the occurrence of an error (step S109), it becomes an infinite loop. The operation prohibition process is released when the all clear process (step S117) described later is executed.

[0128] If affirmative determinations are made in all of steps S106 to S108, the power-on setting process is executed (step S110). In the power-on setting process, a predetermined area of the main-side RAM 65 such as the initialization of the power failure flag is set to the initial value, and a command corresponding to the current game state is transmitted to the audio-visual control device 81. Further, after executing the process of step S110, a recognition process for causing the management IC 66 to recognize various information (step S111), and a data output process for outputting various data to an external device connected to the reading terminal 68d of the MPU 62 are executed (step S112). Details of these recognition process and data output process will be described later.

[0129] Note that the host CPU 63 is configured to periodically execute timer interrupt processing, but the generation of timer interrupt processing is prohibited at the stage when the main processing is started. The state in which the generation of this timer interrupt processing is prohibited is released at the timing before the processing of step S112 is completed and the processing of step S113 is executed, and the execution of the timer interrupt processing is permitted. As a result, when the supply of operating power to the host CPU 63 is started, the data output processing in step S112 ends, and the timer interrupt processing is not executed until the stage before the processing of step S113 is started. Therefore, until such a situation occurs, the processing for advancing the game by the host CPU 63 is not started.

[0130] Thereafter, the process proceeds to the remaining processes of steps S113 to S116. That is, although the host CPU 63 is configured to periodically execute timer interrupt processing, a remaining time will occur between one timer interrupt processing and the next timer interrupt processing. This remaining time will vary according to the processing completion time of each timer interrupt processing, but the remaining processes of steps S113 to S116 are repeatedly executed using such irregular time. In this regard, it can be said that the remaining processes of steps S113 to S116 are non-periodic processes that are executed non-periodically.

[0131] In the residual process, first, in step S113, an interrupt prohibition setting is performed to prohibit the occurrence of timer interrupt processing. In the subsequent step S114, a random number initial value update process for updating the random number initial value counter CINI is executed, and in step S115, a variable counter update process for updating the variation type counter CS is executed. In these update processes, the current numerical information is read from the corresponding counter in the main RAM 65, and after executing the process of adding 1 to the read numerical information, the process of overwriting the original counter is executed. In this case, when the counter value exceeds the maximum value, it is cleared to "0" respectively. Then, in step S116, an interrupt permission setting is performed to switch from the state where the occurrence of timer interrupt processing is prohibited to the permitted state. When the process of step S116 is executed, the process returns to step S113, and the processes of steps S113 to S116 are repeated.

[0132] On the other hand, when the setting key insertion part 68a is in the ON operation state (step S103: YES), all areas of the main RAM 65, including the area where the information of the setting value indicating the setting state of the pachinko machine 10 is set in the main RAM 65, are cleared to "0" (step S117). That is, when an operation for changing the setting state of the pachinko machine 10 is performed, all areas of the main RAM 65 are cleared to "0" even if the reset button 68c is not pressed. Note that this is not limited thereto, and even when an operation for changing the setting state of the pachinko machine 10 is performed and the reset button 68c is not pressed, the all-clear process of the main RAM 65 may not be executed, and the all-clear process may be executed when an operation for changing the setting state of the pachinko machine 10 is performed and the reset button 68c is pressed.

[0133] Thereafter, in step S118, a setting value update process is executed, in step S119, an output process of a setting value update signal is executed, and then the process proceeds to step S110. Hereinafter, the setting value update process will be described. Note that the output process of the setting value update signal will be described in detail later. FIG. 10 is a flowchart showing the setting value update process.

[0134] First, set "1" to the set value counter provided in the main-side RAM 65 (step S201). The set value counter is a counter for the main-side CPU 63 to identify which set value the setting state of the pachinko machine 10 is. When "1" is set to the set value counter, the set value becomes "Setting 1" regardless of the previous set value when the set value update process is executed.

[0135] Thereafter, execute the set value display start process (step S202). In the set value display start process, the display of the third notification display device 69c is controlled so that the number "1" corresponding to "Setting 1" is displayed. When changing the set value, the administrator of the game hall can grasp the current setting state of the pachinko machine 10 by checking the third notification display device 69c.

[0136] Thereafter, on the condition that the setting key insertion part 68a has not been turned off (step S203: NO), it is determined whether the update button 68b has been pressed once (step S204). Specifically, it is determined whether the signal from the sensor that detects the pressing operation of the update button 68b has switched from the LOW level to the HI level. If a negative determination is made in step S204, the process returns to step S203 to determine whether the setting key insertion part 68a has been turned off.

[0137] When the update button 68b has been pressed once (step S204: YES), increment the value of the set value counter in the main-side RAM 65 by 1 (step S205). Further, when the value of the set value counter after the increment exceeds 6 (step S206: YES), set "1" to the set value counter (step S207). As a result, each time the update button 68b is pressed once, the set value is updated to the next higher set value, and when the update button 68b is pressed once in the situation of "Setting 6", it will return to "Setting 1".

[0138] When a negative determination is made in step S206, or when the process of step S207 is executed, a display update process for the set value is executed (step S208). In the display update process for the set value, the display control of the third notification display device 69c is performed so that the number corresponding to the value of the set value counter in the main-side RAM 65 is displayed. The manager of the game hall can grasp the set state of the pachinko machine 10 after pressing the update button 68b by checking the third notification display device 69c.

[0139] After the process of step S208 is executed, the process returns to step S203, and it is determined whether the setting key insertion part 68a has been turned off. If it has not been turned off (step S203: NO), the processes after step S204 are executed again. If it has been turned off (step S203: YES), an end process for displaying the set value is executed (step S209). In the end process for displaying the set value, the display of the set value on the third notification display device 69c is terminated.

[0140] <Timer interrupt process> Next, the timer interrupt process will be described with reference to the flowchart of FIG. 11. The timer interrupt process is executed periodically (for example, at a cycle of 4 milliseconds).

[0141] First, a power failure information storage process is executed (step S301). In the power failure information storage process, it is monitored whether a power failure signal corresponding to the occurrence of a power cut is received from the power failure monitoring board 67. When the occurrence of a power failure is identified, an infinite loop occurs after the power failure process is executed. In the power failure process, a "1" is set in the power failure flag of the main-side RAM 65, and a checksum is calculated and the calculated checksum is saved.

[0142] After that, a lottery random number update process is executed (step S302). In the lottery random number update process, updates of the winning random number counter C1, the jackpot type counter C2, the reach random number counter C3, and the ordinary electric accessory release counter C4 are executed. Specifically, the current numerical information is sequentially read from the winning random number counter C1, the jackpot type counter C2, the reach random number counter C3, and the ordinary electric accessory release counter C4, and after executing the process of adding 1 to each of the read numerical information, the process of overwriting the original counter is executed. In this case, when the counter value exceeds the maximum value, it is cleared to "0" respectively. After that, in step S303, a random number initial value update process is executed in the same manner as in step S114, and in step S304, a variable counter update process is executed in the same manner as in step S115.

[0143] After that, an illegal detection process for monitoring whether a predetermined event set as a monitoring target for illegal use has occurred is executed (step S305). In the illegal detection process, the occurrence of a plurality of types of events is monitored, and by confirming that a predetermined event has occurred, "1" is set in the game stop flag provided in the main side RAM65. In the subsequent step S306, it is determined whether the game is in a stopped state by determining whether "1" is set in the game stop flag. When a negative determination is made in step S306, the processes after step S307 are executed.

[0144] In step S307, port output processing is executed. In the port output processing, when output information is set in the previous timer interrupt processing, processing for performing an output corresponding to the output information to various drive units 32b and 34b is executed. For example, when information for switching the special electric winning device 32 to the open state is set, output of a drive signal to the special electric drive unit 32b is started, and when information for switching to the closed state is set, output of the drive signal is stopped. Also, when information for switching the general electric accessory 34a of the second operating port 34 to the open state is set, output of a drive signal to the general electric drive unit 34b is started, and when information for switching to the closed state is set, output of the drive signal is stopped.

[0145] Thereafter, reading processing is executed (step S308). In the reading processing, signals other than the power failure signal and the winning signal are read, and the read information is stored for use in future processing.

[0146] Thereafter, ball entry detection processing is executed (step S309). In the ball entry detection processing, signals received from each of the ball entry detection sensors 42a to 49a are read, and based on the read result, the presence or absence of a ball entry into the out port 24a, the general winning port 31, the special electric winning device 32, the first operating port 33, the second operating port 34, and the through gate 35 is specified. Details of the ball entry detection processing will be described later.

[0147] Thereafter, timer update processing for collectively updating the numerical information of a plurality of types of timer counters provided in the main side RAM 65 is executed (step S310). In this case, timer counters whose stored numerical information is updated by subtraction are aggregated and handled, but it may also be configured to collectively perform both the update of the subtraction type timer counter and the update of the addition type timer counter.

[0148] Thereafter, a launch control process for controlling the launch of game balls is executed (step S311). In a situation where the launch operation to the launch operation device 28 continues, one game ball is launched at a predetermined launch cycle of 0.6 seconds. In the subsequent step S312, as an input state monitoring process, based on the information read in the reading process of step S308, disconnection confirmation of each ball entry detection sensor 42a to 49a and opening confirmation of the game machine main body 12 and the front door frame 14 are performed.

[0149] Thereafter, a special drawing and special power control process for controlling the execution of the game round and the execution of the opening and closing execution mode is executed (step S313). The special drawing and special power control process will be described in detail later.

[0150] Thereafter, a general drawing and general power control process is executed (step S314). In the general drawing and general power control process, when a winning entry to the through gate 35 occurs, a process for acquiring the hold information on the general drawing side is executed, and when the hold information on the general drawing side is stored, an opening determination is made for the hold information, and further, a process for performing an effect for the general drawing is executed based on the result of the opening determination. Also, based on the result of the opening determination, a process for opening and closing the general power accessory 34a of the second operation port 34 is executed. In this case, if the support mode is the low-frequency support mode, the corresponding process is executed, and if the support mode is the high-frequency support mode, the corresponding process is executed. Also, in the case of the opening and closing execution mode, even if the immediately preceding support mode was the high-frequency support mode, it becomes the low-frequency support mode.

[0151] In the subsequent step S315, based on the processing results of the immediately preceding steps S313 and S314, output information for reflecting the increase or decrease in the number of pieces of hold information related to the special drawing display unit 37a in the special drawing hold display unit 37b is set, and output information for reflecting the increase or decrease in the number of pieces of hold information related to the general drawing display unit 38a in the general drawing hold display unit 38b is set. Also, in step S315, based on the processing results of the immediately preceding steps S313 and S314, output information for updating the display content of the special drawing display unit 37a is set, and output information for updating the display content of the general drawing display unit 38a is set.

[0152] Thereafter, the content of the commands and signals received from the payout control device 77 is confirmed, and a payout state reception process for performing processing corresponding to the confirmation result is executed (step S316). Also, a payout output process for setting a prize ball command as an output target is executed (step S317). Also, an external information setting process for controlling the start and end of the output of an external signal according to the processing results of various processes executed in the current timer interrupt process is executed (step S318). Thereafter, a management output process for outputting information corresponding to the result of the entry of game balls in the game area PA to the management IC 66 is executed (step S319). Details of the management output process will be described later.

[0153] Next, the special drawing special power control process of step S313 will be described with reference to the flowchart of FIG. 12.

[0154] First, execute the process of acquiring hold information (step S401). In the process of acquiring hold information, it is determined whether a winning has occurred at the first operation port 33 or the second operation port 34. If a winning has occurred, it is determined whether the number of holds in the hold storage area 65a is less than the upper limit value (in this embodiment, "4"). If the number of holds is less than the upper limit value, the number of holds is incremented by 1, and the numerical information of the hit random number counter C1, jackpot type counter C2, and reach random number counter C3 updated in the previous step S302 is stored in the first available hold area among the available hold areas RE1 to RE4 in the hold area RE. When a winning occurs simultaneously at the first operation port 33 and the second operation port 34, within the range of executing the process of acquiring hold information once, the process for acquiring the above hold information is executed multiple times. Also, when new hold information is acquired, the corresponding acquisition command is transmitted to the voice and light control device 81. When the voice and light control device 81 receives the command, it causes the display of the image indicating the number of hold information in the symbol display device 41 to be updated to the display content corresponding to the increase in hold information.

[0155] After that, the information of the special figure special power counter provided in the main side RAM 65 is read (step S402), and the special figure special power address table provided in the main side ROM 64 is read (step S403). Then, the start address corresponding to the information of the special figure special power counter is acquired from the special figure special power address table (step S404), and a jump is made to the process indicated by the acquired start address among the processes of steps S406 to S412 (step S405). The special figure special power counter is a counter for the main side CPU 63 to grasp which of the various processes of steps S406 to S412 should be executed. The special figure special power address table has the start address of the program for executing the processes of steps S406 to S412 set corresponding to the numerical information of the special figure special power counter.

[0156] In step S406, the special figure variation start process is executed. FIG. 13 is a flowchart showing the special figure variation start process.

[0157] In the special drawing change start process, on the condition that the number of hold information stored in the hold area RE is 1 or more (step S501: YES), data setting processing is executed (step S502). In the data setting process, first, the number of holds is decremented by 1, and the data stored in the first hold area RE1 of the hold area RE is moved to the execution area AE. Then, a process of shifting the data stored in each of the hold areas RE1 to RE4 of the hold area RE is executed. This data shift process is a process of shifting the data stored in the first hold area RE1 to the fourth hold area RE4 in order to the lower area side. Specifically, after shifting the data in each area such as the second hold area RE2 → the first hold area RE1, the third hold area RE3 → the second hold area RE2, and the fourth hold area RE4 → the third hold area RE3, the fourth hold area RE4 is cleared to "0". At this time, a shift command for recognizing that the data in the hold area has been shifted is transmitted to the voice and light control device 81. When the voice and light control device 81 receives the command, it causes the display of the image indicating the number of hold information in the symbol display device 41 to be updated to the display content corresponding to the decrease in the hold information.

[0158] After executing the data setting process, the pass / fail table is read from the main side ROM64 (step S503). Specifically, first, the current pass / fail lottery mode is grasped by reading the information indicating the pass / fail lottery mode of the main side RAM65. When it is the high probability mode, the high probability pass / fail table 64g is read from the main side ROM64. On the other hand, when it is the low probability mode, the setting state of the pachinko machine 10 is grasped by reading the value of the setting value counter of the main side RAM65. Then, the low probability pass / fail tables 64a to 64f corresponding to the grasped setting values are read from the main side ROM64.

[0159] After that, a win / loss determination process is executed with reference to the win / loss tables 64a to 64g read in step S503 (step S504). In the win / loss determination process, it is determined whether the information for win / loss determination among the information stored in the execution area AE, that is, the numerical information related to the jackpot random number counter C1, matches the jackpot numerical information set in the win / loss tables 64a to 64g read in step S503.

[0160] If the result of the win / loss determination process is a jackpot winning result (step S505: YES), a distribution determination process is executed (step S506). In the distribution determination process, the information for distribution determination among the information stored in the execution area AE, that is, the numerical information related to the jackpot type counter C2, is read. Then, with reference to the distribution table 64h provided in the main ROM 64, it is specified which jackpot result the read numerical information related to the jackpot type counter C2 corresponds to. Specifically, it is specified which of the low-probability jackpot result, the low-win high-probability jackpot result, and the most advantageous jackpot result the information corresponds to.

[0161] After that, a stop result setting process for the jackpot result is executed (step S507). Specifically, the information on the pattern aspect that is finally stopped and displayed on the special figure display unit 37a in the game round related to the start of the current variation is specified from the stop result table for the jackpot result prestored in the main ROM 64, and the specified information is written into the main RAM 65. In this stop result table for the jackpot result, the information on the pattern aspect to be stopped and displayed on the special figure display unit 37a is set to be different for each type of jackpot result.

[0162] After that, a flag setting process corresponding to the distribution determination result is executed (step S508). Specifically, flags corresponding to each type of jackpot result are provided in the main RAM 65, and in step S508, "1" is set for the flag corresponding to the result of the distribution determination process in step S506 among the flags corresponding to each type of jackpot result.

[0163] On the other hand, when it is determined in step S505 that the result is not a jackpot winning result, a stop result setting process for a losing result is executed (step S509). Specifically, information on the pattern mode to be finally stopped and displayed on the special figure display unit 37a in the game round related to the start of the current variation is specified from the stop result table for losing results pre-stored in the main ROM 64, and the specified information is written into the main RAM 65. The information on the pattern mode selected in this case is different from the information on the pattern mode selected in the case of a jackpot result.

[0164] After executing either the process of step S508 or step S509, a process for grasping the duration of the game round is executed (step S510). In such a process, numerical information of the variation type counter CS is acquired. Also, it is determined whether or not a reach display occurs on the symbol display device 41 in the current game round. Specifically, when the game round related to the start of the current variation is a low-probability jackpot result or a most advantageous jackpot result, it is determined that a reach display occurs. Also, when it is not any jackpot result and the numerical information related to the reach random number counter C3 stored in the execution area AE is numerical information corresponding to the occurrence of a reach, it is determined that a reach display occurs.

[0165] When it is determined that a reach display occurs, the duration of the game round corresponding to the numerical information of the current variation type counter CS is acquired with reference to the reach occurrence duration table stored in the main ROM 64. On the other hand, when it is determined that a reach display does not occur, the duration of the game round corresponding to the numerical information of the current variation type counter CS is acquired with reference to the reach non-occurrence duration table stored in the main ROM 64. Incidentally, the duration of the game round that can be acquired with reference to the reach non-occurrence duration table is different from the duration of the game round that can be acquired with reference to the reach occurrence duration table.

[0166] Note that the duration of a game round when a reach does not occur is set such that the longer the number of hold information stored in the hold area RE, the shorter the duration of the game round. Also, in a situation where the support mode is the high-frequency support mode, a shorter game round duration is selected compared to a situation where the support mode is the low-frequency support mode when the number of hold information is the same. The reach non-occurrence duration table is set accordingly. However, it is not limited to this, and the configuration may be such that the duration of the game round does not vary according to the number of hold information or the support mode, or it may be the opposite of the above relationship. Furthermore, the above configuration may be applied to the duration of a game round when a reach occurs. Also, for each case of various jackpot results, a duration table may be set individually for the case of a missed reach, the case of a reach non-occurrence with a missed result. In this case, the duration of the game round corresponding to each game result will be allocated.

[0167] Thereafter, the information on the duration of the game round acquired in step S510 is set in the special figure special power timer counter provided in the main-side RAM 65 (step S511). The update of the numerical information set in the special figure special power timer counter is executed in the timer update process (step S310). Incidentally, as an effect for the game, a variable display of the pattern in the special figure display section 37a and a variable display of the pattern in the pattern display device 41 are performed. When each of these variable displays ends, the stop result of that game round is displayed in a state where the stop result is displayed (in the pattern display device 41, a predetermined combination of patterns is waiting on the active line) for a final stop period (for example, 0.5 sec). In this case, the duration of the game round acquired in step S510 is the total time for one game round.

[0168] Thereafter, the variable command and the type command are transmitted to the voice and light control device 81 (step S512). The variable command includes information on the duration of the game round. Here, since the duration of the game round obtained by referring to the non-reach occurrence duration table as described above is different from the duration of the game round obtained by referring to the reach occurrence duration table, even if the variable command does not include information on the presence or absence of a reach, the voice and light control device 81 can specify the presence or absence of a reach from the information on the duration of the game round. In this regard, it can be said that the variable command includes information indicating the presence or absence of a reach. Note that the variable command may directly include information indicating the presence or absence of a reach. Also, the type command includes information on the game result.

[0169] When the voice and light control device 81 receives the variable command and the type command from the main CPU 63, the display light-emitting unit 53, the speaker unit 54, and the symbol display device 41 perform game-related effects. In this case, the game-related effects are performed in a manner corresponding to the contents of the variable command and the type command. Also, in the symbol display device 41, variable display of symbols is performed as a game-related effect, and when the game-related effect ends, the combination of symbols corresponding to the result of the win / loss determination process and the distribution determination process is stopped and displayed.

[0170] Thereafter, the variable display of the picture in the special figure display unit 37a is started (step S513). Then, the special figure special power counter is incremented by 1 (step S514). In this case, since the numerical information of the special figure special power counter when the special figure variable start process is executed is "0", the numerical information of the special figure special power counter becomes "1". Thereafter, "1" is set in the 11th output flag provided in the main RAM 65 (step S515). The 11th output flag is a flag for the main CPU 63 to specify that the information output indicating the start of the game round should be executed for the management IC 66.

[0171] Returning to the description of the special drawing special power control process (Figure 52), in step S407, the process during special drawing change is executed. In the process during special drawing change, it is determined whether it is during the duration of the game round and before the final stop display timing. If it is before the final stop display, a process for regularly changing the display mode of the pattern on the special drawing display unit 37a is executed. When it becomes the timing to perform the final stop display, the numerical information of the special drawing special power counter is incremented by 1, and the numerical information of the counter is updated from the one corresponding to the process during special drawing change to the one corresponding to the process during special drawing determination. Note that in this embodiment, the main CPU 63 does not send a final stop command to the audio-visual control device 81.

[0172] In step S408, the process during special drawing determination is executed. In the process during special drawing determination, the display mode of the pattern on the special drawing display unit 37a is set to the display mode corresponding to the lottery result of the current game round. Also, in the process during special drawing determination, it is determined whether the final stop period has elapsed. If the period has elapsed, it is determined whether a transition to the opening / closing execution mode occurs. If the transition to the opening / closing execution mode does not occur, the numerical information of the special drawing special power counter is cleared to "0". If the transition to the opening / closing execution mode occurs, the numerical information of the special drawing special power counter is incremented by 1, and the numerical information of the counter is updated from the one corresponding to the process during special drawing determination to the one corresponding to the special power start process.

[0173] In step S409, special power start processing is executed. In the special power start processing, if the processing for starting the opening period in the current opening / closing execution mode has not been executed yet, the setting process for the opening period is executed. Also, an opening command is transmitted to the audio-visual control device 81. The audio-visual control device 81 causes an opening effect to be executed by the display and lighting unit 53, the speaker unit 54, and the symbol display device 41 when receiving the opening command. If the opening period has elapsed, the start processing for starting the first round game is executed. In the start processing, the special power winning device 32 is set to the open state and the end condition of the round game is set. When setting this end condition, the upper limit duration for continuously keeping the special power winning device 32 in the open state in the first round game of this time is set, and the upper limit number of game balls that can win the special power winning device 32 in the first round game of this time is set to the winning number counter provided in the main side RAM 65.

[0174] In step S410, special power open processing is executed. In the special power open processing, it is determined whether the end condition of the round game is satisfied. If the end condition is satisfied, the special power winning device 32 is set to the closed state. Then, if the round game ended this time is not the last execution round of the round game, the numerical information of the special figure special power counter is incremented by 1 to update the numerical information of the counter from the one corresponding to the special power open processing to the one corresponding to the special power closed processing, and if the round game ended this time is the last execution round of the round game, the numerical information of the special figure special power counter is incremented by 2 to update the numerical information of the counter from the one corresponding to the special power open processing to the one corresponding to the special power end processing.

[0175] In step S411, the special power-off in-process processing is executed. In the special power-off in-process processing, it is determined whether or not the interval period between round games has elapsed. The interval period is set when the previous round game ends. When the interval period has elapsed, the special power winning device 32 is set to the open state and the end condition of the round game is set. Then, by subtracting 1 from the numerical information of the special figure special power counter, the numerical information of the counter is updated from the one corresponding to the special power-off in-process processing to the one corresponding to the special power-on in-process processing.

[0176] In step S412, the special power end processing is executed. In the special power end processing, when the processing for starting the ending period in the current opening / closing execution mode has not yet been executed, the ending period (for example, 5 seconds) is set and an ending command is transmitted to the voice and light control device 81. When the voice and light control device 81 receives the ending command, an ending effect is executed by the display and light emission unit 53, the speaker unit 54, and the symbol display device 41. When the ending period has elapsed, each of the win / loss lottery mode and the support mode after the end of the opening / closing execution mode is set to the mode corresponding to the jackpot result that triggered the start of the current opening / closing execution mode.

[0177] Next, a configuration for specifying the presence or absence of game balls entering the out port 24a, the general winning port 31, the special power winning device 32, the first operating port 33, the second operating port 34, and the through gate 35 based on the detection results of the ball entry detection sensors 42a to 49a by the main CPU 63 will be described. FIG. 14 is an explanatory diagram for explaining a configuration in which the detection results of the ball entry detection sensors 42a to 49a are input to the main CPU 63.

[0178] The main CPU 63 is provided with an input port 63a. The input port 63a is configured as an 8-bit parallel interface so that it can handle 8 types of signals simultaneously. And areas where information of "0" or "1" is stored according to the voltage of each signal are provided in a one-to-one correspondence with each terminal. That is, as said areas, it is equipped with the 0th bit D0 to the 7th bit D7. Also, although more than 8 types of signals will be input to the input port 63a, in order to limit the signals to be input simultaneously to 8 types, the signal group to be the input target to the input port 63a is switched through the switching control by the driver IC.

[0179] In the ball-in detection process (step S309) of the timer interrupt process (Figure 11), the signal group to be the input target to the input port 63a is set to the signal group from each ball-in detection sensor 42a to 49a. In the situation where such setting is made, the 0th bit D0 stores the information corresponding to the detection signal from the first winning port detection sensor 42a, the 1st bit D1 stores the information corresponding to the detection signal from the second winning port detection sensor 43a, the 2nd bit D2 stores the information corresponding to the detection signal from the third winning port detection sensor 44a, the 3rd bit D3 stores the information corresponding to the special power detection sensor 45a, the 4th bit D4 stores the information corresponding to the detection signal from the first operating port detection sensor 46a, the 5th bit D5 stores the information corresponding to the detection signal from the second operating port detection sensor 47a, the 6th bit D6 stores the information corresponding to the detection signal from the out port detection sensor 48a, and the 7th bit D7 stores the information corresponding to the detection signal from the gate detection sensor 49a.

[0180] When each of the above-mentioned ball entry detection sensors 42a to 49a does not detect the passage of a game ball, it outputs a LOW-level signal indicating non-detection as a detection signal. When it detects the passage of a game ball, it outputs a HI-level signal indicating detection as a detection signal. Then, when the input port 63a receives a LOW-level signal, "0" information is stored in the corresponding bit, and when it receives a HI-level signal, "1" information is stored in the corresponding bit. That is, in a situation where the passage of a game ball is not detected by the ball entry detection sensors 42a to 49a, "0" information corresponding to the information indicating non-detection is stored in the corresponding bit, and in a situation where the passage of a game ball is detected, "1" information corresponding to the information indicating detection is stored in the corresponding bit.

[0181] FIG. 15 is a flowchart showing the ball entry detection process executed in step S309 of the timer interrupt process (FIG. 11).

[0182] When it is confirmed that the information stored in the 0th bit D0 has been switched from the situation where "0" information is stored to the situation where "1" information is stored, it is determined that one game ball has been detected by the first winning port detection sensor 42a (step S601: YES). In this case, "1" is set in the first output flag provided in the main-side RAM 65 (step S602), and the value of the 10 prize ball counter provided in the main-side RAM 65 is incremented by 1 (step S603). The first output flag is a flag for the main CPU 63 to specify to the management IC 66 the information output indicating that one game ball has been detected by the first winning port detection sensor 42a. The 10 prize ball counter is a counter for the main CPU 63 to specify the number of times to execute the payout of 10 game balls. When the value of the 10 prize ball counter is 1 or more, in the payout output process of step S317 in the timer interrupt process (FIG. 11), a 10 prize ball command is output to the payout control device 77, and when the 10 prize ball command is output once, the value of the 10 prize ball counter is decremented by 1. When the payout control device 77 receives the 10 prize ball command, it drives and controls the payout device 76 so that 10 game balls are paid out.

[0183] When it is confirmed that the situation has switched from the situation where the information "0" is stored in the first bit D1 to the situation where the information "1" is stored, if it is determined that one game ball has been detected by the second winning port detection sensor 43a (step S604: YES). In this case, "1" is set to the second output flag provided in the main-side RAM 65 (step S605), and the value of the 10 prize ball counter provided in the main-side RAM 65 is incremented by 1 (step S606). The second output flag is a flag for the main CPU 63 to identify that the information output indicating that one game ball has been detected by the second winning port detection sensor 43a should be executed for the management IC 66.

[0184] When it is confirmed that the situation has switched from the situation where the information "0" is stored in the second bit D2 to the situation where the information "1" is stored, if it is determined that one game ball has been detected by the third winning port detection sensor 44a (step S607: YES). In this case, "1" is set to the third output flag provided in the main-side RAM 65 (step S608), and the value of the 10 prize ball counter provided in the main-side RAM 65 is incremented by 1 (step S609). The third output flag is a flag for the main CPU 63 to identify that the information output indicating that one game ball has been detected by the third winning port detection sensor 44a should be executed for the management IC 66.

[0185] When it is confirmed that the situation has switched from the situation where the information of "0" is stored in the third bit D3 to the situation where the information of "1" is stored, it is determined that one game ball has been detected by the special power detection sensor 45a (step S610: YES). In this case, "1" is set to the special power winning flag provided in the main side RAM 65 (step S611), "1" is set to the fourth output flag provided in the main side RAM 65 (step S612), and further, the value of the 15 prize ball counter provided in the main side RAM 65 is incremented by 1 (step S613). The special power winning flag is a flag for the main side CPU 63 to identify that one game ball has entered the special power winning device 32 in the round game of the opening / closing execution mode. In the special power control process (step S313) of the timer interrupt process (FIG. 11), by confirming that "1" is set in the special power winning flag, it is identified that one game ball has entered the special power winning device 32, and the remaining number of possible balls to enter the special power winning device 32 in the round game is decremented by 1. When the process of decrementing the number of possible balls to enter by 1 is executed, the special power winning flag is cleared to "0". The fourth output flag is a flag for the main side CPU 63 to identify that the information output indicating that one game ball has been detected by the special power detection sensor 45a should be executed for the management IC 66. The 15 prize ball counter is a counter for the main side CPU 63 to identify the number of times to execute the payout of 15 game balls. When the value of the 15 prize ball counter is 1 or more, in the payout output process of step S317 in the timer interrupt process (FIG. 11), a 15 prize ball command is output to the payout control device 77, and when the 15 prize ball command is output once, the value of the 15 prize ball counter is decremented by 1. When the payout control device 77 receives the 15 prize ball command, it drives and controls the payout device 76 so that 15 game balls are paid out.

[0186] When it is confirmed that the situation has switched from the situation where the information "0" is stored in the fourth bit D4 to the situation where the information "1" is stored, it is determined that one game ball has been detected by the first operation port detection sensor 46a (step S614: YES). In this case, "1" is set to the first operation winning flag provided in the main-side RAM 65 (step S615), "1" is set to the fifth output flag provided in the main-side RAM 65 (step S616), and further, the value of the single prize ball counter provided in the main-side RAM 65 is incremented by 1 (step S617). The first operation winning flag is a flag for the main-side CPU 63 to identify that one game ball has entered the first operation port 33. In the special figure special power control process (step S313) of the timer interrupt process (FIG. 11), by confirming that "1" is set in the first operation winning flag, the process of newly storing the held information is executed on the condition that the number of held information stored in the holding area RE of the holding storage area 65a is less than the upper limit number of 4. When it is confirmed in the special power special power control process (step S313) that "1" is set in the first operation winning flag and the process corresponding to the confirmation is executed, the first operation winning flag is cleared to "0". The fifth output flag is a flag for the main-side CPU 63 to identify that the information output indicating that one game ball has been detected by the first operation port detection sensor 46a should be executed for the management IC 66. The single prize ball counter is a counter for the main-side CPU 63 to identify the number of times to execute the payout of one game ball. When the value of the single prize ball counter is 1 or more, in the payout output process of step S317 in the timer interrupt process (FIG. 11), a single prize ball command is output to the payout control device 77, and when a single prize ball command is output once, the value of the single prize ball counter is decremented by 1. When the payout control device 77 receives a single prize ball command, it drives and controls the payout device 76 so that one game ball is paid out.

[0187] When it is confirmed that the situation has switched from the situation where the information "0" is stored in the 5th bit D5 to the situation where the information "1" is stored, it is determined that one game ball has been detected by the second operation port detection sensor 47a (step S618: YES). In this case, "1" is set to the second operation winning flag provided in the main side RAM 65 (step S619), "1" is set to the sixth output flag provided in the main side RAM 65 (step S620), and further, the value of the one prize ball counter provided in the main side RAM 65 is incremented by 1 (step S621). The second operation winning flag is a flag for the main side CPU 63 to identify that one game ball has entered the second operation port 34. In the special figure special power control process (step S313) of the timer interrupt process (FIG. 11), by confirming that "1" is set in the second operation winning flag, the number of reserved information stored in the reserved area RE of the reserved storage area 65a is less than the upper limit number of 4, and a process of newly storing the reserved information is executed. When it is confirmed in the special power special power control process (step S313) that "1" is set in the second operation winning flag and the process corresponding to the confirmation is executed, the second operation winning flag is cleared to "0". The sixth output flag is a flag for the main side CPU 63 to identify that the information output indicating that one game ball has been detected by the second operation port detection sensor 47a should be executed for the management IC 66.

[0188] When it is confirmed that the situation has switched from the situation where the information "0" is stored in the 6th bit D6 to the situation where the information "1" is stored, it is determined that one game ball has been detected by the out port detection sensor 48a (step S622: YES). In this case, "1" is set to the seventh output flag provided in the main side RAM 65 (step S623). The seventh output flag is a flag for the main side CPU 63 to identify that the information output indicating that one game ball has been detected by the out port detection sensor 48a should be executed for the management IC 66.

[0189] When it is confirmed that the situation has switched from the state where the information "0" is stored in the 7th bit D7 to the state where the information "1" is stored, it is determined that one game ball has been detected by the gate detection sensor 49a (step S624: YES). In this case, "1" is set in the gate winning flag provided in the main side RAM 65 (step S625). The gate winning flag is a flag for the main side CPU 63 to identify that one game ball has entered the through gate 35. In the general diagram general power control process (step S314) of the timer interrupt process (FIG. 11), by confirming that "1" is set in the gate winning flag, on the condition that the number of reserved information on the general diagram side stored in the general power reserve area 65c is less than the upper limit number of 4, the process of storing the numerical information of the current general power accessory release counter C4 as the reserved information on the general diagram side in the general power reserve area 65c is executed. When it is confirmed in the general diagram general power control process (step S314) that "1" is set in the gate winning flag and the process corresponding to the confirmation is executed, the gate winning flag is cleared to "0".

[0190] Note that since the timer interrupt process (FIG. 11) is started at a cycle of 4 msec as already described, when the detection of one game ball is started by one of the ball entry detection sensors 42a to 49a, in the situation where the detection of that one game ball is continued by the ball entry detection sensors 42a to 49a, the main side CPU 63 identifies that one game ball has been detected by the ball entry detection sensors 42a to 49a. Therefore, it is sufficient to provide one each of the first to seventh output flags.

[0191] Next, the processing content executed by the payout control device 77 will be described. First, the electrical configuration of the payout control device 77 and various devices that communicate with the payout control device 77 will be described with reference to the block diagram of FIG. 16.

[0192] The payout control device 77 includes an MPU 91. In the MPU 91, in addition to the payout side CPU 92 which is an arithmetic processing device including a control unit and an arithmetic unit, a payout side ROM 93, a payout side RAM 94, an interrupt circuit, a timer circuit, a data input / output circuit, etc. are built-in.

[0193] The payout-side ROM 93 is a memory that does not require external power supply for data retention, such as a NOR-type flash memory and a NAND-type flash memory (i.e., non-volatile storage means), and is used as read-only. The payout-side ROM 93 stores various control programs and fixed-value data executed by the payout-side CPU 92.

[0194] The payout-side RAM 94 is a memory that requires external power supply for data retention, such as an SRAM and a DRAM (i.e., volatile storage means), and is used for both reading and writing. The payout-side RAM 94 allows random access and has a shorter read time than the payout-side ROM 93 when compared with the same data capacity. The payout-side RAM 94 temporarily stores various data for the execution of the control programs stored in the payout-side ROM 93.

[0195] The payout-side CPU 92 can communicate bidirectionally with the main-side CPU 63. When the payout-side CPU 92 receives a prize ball command from the main-side CPU 63, it drives and controls the payout device 76 so that the number of game balls corresponding to the prize ball command is paid out. Also, the payout-side CPU 92 monitors whether it is possible to normally pay out game balls. If it determines that it is not in a state where normal payout is possible, even if the number of unpayout prize balls is stored in the payout-side RAM 94, it stops the payout device 76. Further, the payout-side CPU 92 transmits a payout restriction command indicating that it is not in a state where normal payout is possible to the main-side CPU 63. When the main-side CPU 63 receives the payout restriction command, it transmits a notification command to the audio-visual control device 81 so that a notification indicating that it is not in a state where normal payout of game balls is possible is executed by the symbol display device 41, the display light-emitting unit 53, and the speaker unit 54. The states where normal payout of game balls is not possible include a full state where the lower tray 56a is full of game balls, a ballless state where the tank 75 is not replenished with game balls, a payout abnormality state where the payout device 76 does not operate normally, a main body open state where the game machine main body 12 is opened from the outer frame 11, and a front door open state where the front door frame 14 is opened from the inner frame 13.

[0196] A full detection sensor (not shown) is provided at an intermediate position of the game ball passage leading from the payout device 76 to the lower tray 56a, and the detection result of the full detection sensor is input to the payout-side CPU 92. When the full detection sensor continuously detects a game ball, the payout-side CPU 92 determines that it is in a full state. When the state where the full detection sensor continuously detects a game ball is released, the payout-side CPU 92 determines that the full state has been released.

[0197] A ball non-detection sensor (not shown) is provided at an intermediate position of the game ball passage leading from the tank 75 to the payout device 76, and the detection result of the ball non-detection sensor is input to the payout-side CPU 92. When the game ball is not continuously detected by the ball non-detection sensor, the payout-side CPU 92 specifies that it is in a ball non-state, and when the state where the game ball is not continuously detected by the ball non-detection sensor is released, the payout-side CPU 92 specifies that the ball non-state has been released.

[0198] The payout device 76 is provided with a payout detection sensor (not shown) for detecting the game balls paid out from the payout device 76, and the detection result of the payout detection sensor is input to the payout-side CPU 92. When the game ball is detected by the payout detection sensor, the payout-side CPU 92 specifies that one game ball has been paid out from the payout device 76. Further, even though the payout-side CPU 92 is driving and controlling the payout device 76 so that the game balls are paid out, when the game ball is not continuously detected by the payout detection sensor, the payout-side CPU 92 specifies that it is in a payout abnormal state, and when the state where the game ball is not continuously detected by the payout detection sensor is released, the payout-side CPU 92 specifies that the payout abnormal state has been released.

[0199] A front door opening sensor 95 is provided on the front surface portion of the inner frame 13 (see FIG. 2), and the detection result of the front door opening sensor 95 is input to the dispensing side CPU 92. In this case, when the front door frame 14 is in the closed state with respect to the inner frame 13, the front door opening sensor 95 transmits a closed detection signal to the dispensing side CPU 92, and when the front door frame 14 is in the open state with respect to the inner frame 13, the front door opening sensor 95 transmits an open detection signal to the dispensing side CPU 92. The dispensing side CPU 92 identifies that the front door frame 14 is in the closed state when receiving a closed detection signal from the front door opening sensor 95, and identifies that the front door frame 14 is in the open state when receiving an open detection signal from the front door opening sensor 95. Further, the dispensing side CPU 92 transmits a front door opening command to the main side CPU 63 at the timing when it is identified that the front door frame 14 has changed from the closed state to the open state, and transmits a front door closing command to the main side CPU 63 at the timing when it is identified that the front door frame 14 has changed from the open state to the closed state. The main side CPU 63 identifies that the front door frame 14 is in the open state when receiving the front door opening command, and identifies that the front door frame 14 is in the closed state when receiving the front door closing command.

[0200] A main body opening sensor 96 is provided on the front part of the inner pack unit 15 (see FIG. 2), and the detection result of the main body opening sensor 96 is input to the payout-side CPU 92. In this case, when the gaming machine main body 12 is in the closed state with respect to the outer frame 11, the main body opening sensor 96 transmits a closed detection signal to the payout-side CPU 92, and when the gaming machine main body 12 is in the open state with respect to the outer frame 11, the main body opening sensor 96 transmits an open detection signal to the payout-side CPU 92. When the payout-side CPU 92 receives a closed detection signal from the main body opening sensor 96, it determines that the gaming machine main body 12 is in the closed state, and when it receives an open detection signal from the main body opening sensor 96, it determines that the gaming machine main body 12 is in the open state. Further, the payout-side CPU 92 transmits a main body opening command to the main-side CPU 63 at the timing when it determines that the gaming machine main body 12 has changed from the closed state to the open state, and transmits a main body closing command to the main-side CPU 63 at the timing when it determines that the gaming machine main body 12 has changed from the open state to the closed state. The main-side CPU 63 determines that the gaming machine main body 12 is in the open state when it receives the main body opening command, and determines that the gaming machine main body 12 is in the closed state when it receives the main body closing command.

[0201] With reference to the flowchart of FIG. 17, the timer interrupt process executed by the payout-side CPU 92 will be described. The timer interrupt process is repeatedly started at a predetermined cycle (for example, 2 msec).

[0202] First, the full-state process is executed (step S701). In the full-state process, as already described, based on the detection result of the full-state detection sensor, it is determined whether or not it is in the full state. When it is in the full state, a process for stopping the payout of the game balls is executed, and a command indicating that it is in the full state is transmitted to the main-side CPU 63. Also, when the full state is released, a process for enabling the payout of the game balls is executed, and a command indicating that the full state has been released is transmitted to the main-side CPU 63.

[0203] Thereafter, a ball-free process is executed (step S702). In the ball-free process, as already described, it is determined whether or not it is in a ball-free state based on the detection result of the ball-free detection sensor. When it is in a ball-free state, a process for stopping the payout of the game balls is executed, and a command indicating that it is in a ball-free state is transmitted to the main CPU 63. Also, when the ball-free state is released, a process for enabling the payout of the game balls is executed, and a command indicating that the ball-free state has been released is transmitted to the main CPU 63.

[0204] Thereafter, a payout abnormality monitoring process is executed (step S703). In the payout abnormality monitoring process, as already described, it is determined whether or not it is in a payout abnormality state based on the detection result of the payout detection sensor. When it is in a payout abnormality state, a process for stopping the payout of the game balls is executed, and a command indicating that it is in a payout abnormality state is transmitted to the main CPU 63. Also, when the payout abnormality state is released, a process for enabling the payout of the game balls is executed, and a command indicating that the payout abnormality state has been released is transmitted to the main CPU 63.

[0205] Thereafter, a front door opening monitoring process is executed (step S704). In the front door opening monitoring process, as already described, it is determined whether or not the front door frame 14 is in an open state based on the detection result of the front door opening sensor 95. When the front door frame 14 is in an open state, a process for stopping the payout of the game balls is executed, and a front door opening command is transmitted to the main CPU 63. Also, when the front door frame 14 is closed, a process for enabling the payout of the game balls is executed, and a front door closing command is transmitted to the main CPU 63.

[0206] Thereafter, the main body opening monitoring process is executed (step S705). In the main body opening monitoring process, as already described, it is specified whether the gaming machine main body 12 is in an open state based on the detection result of the main body opening sensor 96. When the gaming machine main body 12 is in an open state, a process of stopping the payout of game balls is executed, and a main body opening command is transmitted to the main CPU 63. Also, when the gaming machine main body 12 is closed, a process of enabling the payout of game balls is executed, and a main body closing command is transmitted to the main CPU 63.

[0207] Thereafter, the command reading process is executed (step S706). In the command reading process, a process of reading the bonus ball command transmitted by the main CPU 63 is executed, and the bonus ball command is stored in the payout side RAM 94. Then, after executing a bonus ball setting process for adding the number corresponding to the received bonus ball command to the number information of un-paid-out bonus balls in the payout side RAM 94 (step S707), a payout control process for executing control over the payout of game balls by the payout device 76 is executed (step S708). In the payout control process, when the number information of un-paid-out bonus balls stored in the payout side RAM 94 is a value of 1 or more, drive control of the payout device 76 is performed, and when one game ball is detected by the payout detection sensor, the value of the bonus ball number information is decremented by 1. And when the value of the bonus ball number information becomes "0", the drive control of the payout device 76 is stopped. Thereafter, an external information setting process for controlling the start and end of the output of an external signal according to the processing results of various processes executed in this timer interrupt process is executed (step S709).

[0208] Next, a configuration for externally outputting information from the pachinko machine 10 to the hall computer HC provided in the game hall will be described.

[0209] As shown in FIG. 2, an external terminal board 97 is provided in the back pack unit 15. A number of external terminals are provided on the external terminal board 97. Some of the external terminals, i.e., a plurality of external terminals, are electrically connected to the main CPU 63, and some of the external terminals, i.e., a plurality of external terminals, are electrically connected to the payout CPU 92. Since each of the main CPU 63 and the payout CPU 92 is electrically connected to the external terminal board 97 in this way, as shown in FIG. 16, the main CPU 63 and the payout CPU 92 can externally output information to the whole computer HC.

[0210] One external terminal of the external terminal board 97 is electrically connected to the front door open sensor 95, and one external terminal of the external terminal board 97 is electrically connected to the main body open sensor 96. Regarding the details of this electrical connection configuration, a signal relay board 98 is provided at an intermediate position in the signal path from the front door open sensor 95 to the payout CPU 92. A branch path SL2 is provided on the signal relay board 98 by branching from the signal path SL1 from the front door open sensor 95 to the payout CPU 92. And the branch path SL2 is connected to the external terminal for opening the front door on the external terminal board 97. Therefore, the electrical signal corresponding to the detection result of the front door open sensor 95 is input not only to the payout CPU 92 but also to the external terminal for opening the front door on the external terminal board 97. Thereby, it becomes possible to externally output a signal indicating whether or not the front door frame 14 is in an open state to the whole computer HC without going through the control by the payout CPU 92.

[0211] Regarding the main body opening sensor 96 in detail, the signal relay board 98 is provided with a branch path SL4 branched from the signal path SL3 directed from the main body opening sensor 96 toward the payout-side CPU 92. And the branch path SL4 is connected to the external terminal for main body opening on the external terminal board 97. Therefore, the electrical signal corresponding to the detection result of the main body opening sensor 96 is input not only to the payout-side CPU 92 but also to the external terminal for main body opening on the external terminal board 97. Thereby, it becomes possible to externally output a signal indicating whether or not the gaming machine main body 12 is in an open state to the hall computer HC without going through the control by the payout-side CPU 92.

[0212] Next, the content of the information externally output from the main-side CPU 63 and the payout-side CPU 92 to the hall computer HC will be described. First, the content of the information externally output from the main-side CPU 63 to the hall computer HC will be described.

[0213] The main-side CPU 63 performs output setting of information to each external terminal assigned to the main-side CPU 63 on the external terminal board 97 in the external information setting process (step S318) in the timer interrupt process (FIG. 11). Information output from the main-side CPU 63 to the external terminal board 97 includes information indicating that it is in the opening / closing execution mode, information indicating that the support mode is in the high-frequency support mode, information indicating that one game round has ended, information indicating that a predetermined number (for example, 100) of game balls have been discharged from the game area PA through any one of the out port 24a, the general winning port 31, the special electric winning device 32, the first operation port 33, and the second operation port 34, information indicating that a game ball has entered the first operation port 33, and information indicating that a game ball has entered the second operation port 34.

[0214] The payout-side CPU 92 performs output setting of information to each external terminal assigned to the payout-side CPU 92 on the external terminal board 97 in the external information setting process (step S709) in the timer interrupt process (FIG. 17). Information output from the payout-side CPU 92 to the external terminal board 97 includes information indicating that 10 game balls have been paid out.

[0215] In the hall computer HC, it is possible to grasp the execution mode of paying out game balls in the pachinko machine 10 according to various information received from the pachinko machine 10 through the external terminal board 97. For example, · The ball payout rate, which is the ratio of the number of game balls paid out until 100 game balls are discharged from the game area PA of the pachinko machine 10 · The ball payout rate in the normal game state that is not the opening / closing execution mode and the high-frequency support mode (hereinafter, this ball payout rate is referred to as "B") · The ball payout rate in the opening / closing execution mode · The ball payout rate in the high-frequency support mode · The number of game turns executed until 100 game balls are discharged from the game area PA of the pachinko machine 10 (hereinafter, this ratio is referred to as "S") · B - S × "The number of prize balls for winning in the first operation port 33 and the second operation port 34" · The number of game balls entering the first operation port 33 until 100 game balls are discharged from the game area PA of the pachinko machine 10 (hereinafter, this ratio is referred to as "S1") · The number of game balls entering the second operation port 34 until 100 game balls are discharged from the game area PA of the pachinko machine 10 (hereinafter, this ratio is referred to as "S2") · B - (S1 × "The number of prize balls for winning in the first operation port 33" + S2 × "The number of prize balls for winning in the second operation port 34") · The occurrence probability of the opening / closing execution mode per unit game turn · The occurrence probability of the high-frequency support mode per unit game turn etc. are calculated. As a result, it becomes possible for the hall computer HC to manage the ball entry mode in the game area PA of the pachinko machine 10. Note that the number of prize balls refers to the number of game balls paid out when one game ball enters the corresponding ball entry part.

[0216] <Configuration for managing the prize mode of game balls> Next, a configuration for managing game history using the management IC 66 will be described. First, the electrical configuration of the management IC 66 will be described with reference to the block diagram of FIG. 18.

[0217] As already described, the MPU 62 of the main control device 60 includes a main CPU 63, a main ROM 64, a main RAM 65, and a management IC 66. In addition, the MPU 62 includes an I / F 101 and the already-described reading terminal 68d.

[0218] The I / F 101 is an interface for transmitting and receiving signals between the MPU 62 and external devices. The I / F 101 is electrically connected to the main CPU 63 via an internal bus 103. Detection results from sensors such as each ball entry detection sensor 42a to 49a and commands from the payout-side CPU 92 are input to the MPU 62 through the input port of the I / F 101, and various processes are executed by the main CPU 63 as already described based on the input detection results and command contents. Also, when a signal output is performed to a device such as the special power drive unit 32b as a result of various processes being executed by the main CPU 63, the signal output is performed through the output port of the I / F 101, and when a command output is performed to the payout-side CPU 92 and the sound and light control device 81 as a result of various processes being executed by the main CPU 63, the command output is performed through the output port of the I / F 101.

[0219] The management IC 66 includes a management-side I / F 111, a management-side CPU 112, a management-side ROM 113, a management-side RAM 114, an RTC 115, a correspondence relation memory 116, a history memory 117, and a calculation result memory 131. These devices are connected so as to be capable of two-way communication through an internal bus 66a provided in the management IC 66.

[0220] The management-side I / F 111 is an interface for receiving various signals from the main-side CPU 63 via the signal path group 118 for unidirectional communication built into the MPU 62 and transmitting various signals to the reading terminal 68d via the signal path group 119 for unidirectional communication built into the MPU 62. Various signals from the main-side CPU 63 are input to the input port of the management-side I / F 111, and various signals to the reading terminal 68d are output from the output port of the management-side I / F 111. Note that the main-side CPU 63 is electrically connected to the reading terminal 68d via the signal path group 120 for bidirectional communication built into the MPU 62.

[0221] The management-side CPU 112 is an arithmetic processing unit including a control unit and an arithmetic unit. The management-side ROM 113 is a memory (i.e., non-volatile storage means) such as a NOR-type flash memory and a NAND-type flash memory that does not require external power supply for storage retention, and is used as read-only. The management-side ROM 113 stores various control programs and fixed-value data executed by the management-side CPU 112. The management-side RAM 114 is a memory (i.e., volatile storage means) such as an SRAM and a DRAM that requires external power supply for storage retention, and is used for both reading and writing. The management-side RAM 114 allows random access and has a shorter read time than the management-side ROM 113 when compared with the same data capacity. The management-side RAM 114 temporarily stores various data and the like for the execution of the control program stored in the management-side ROM 113.

[0222] The RTC 115 is a real-time clock, which constantly measures the year / month / day information and time information, and is configured to output the measured year / month / day information and time information (hereinafter also referred to as date / time information) according to an instruction from the management-side CPU 112. Note that the RTC 115 is provided with a backup power supply, and it is possible to measure the year / month / day information and time information even when the power of the pachinko machine 10 is cut off.

[0223] The correspondence memory 116 is a memory that requires external power supply for memory retention, such as SRAM and DRAM (i.e., volatile memory means), and is used for both reading and writing. The correspondence memory 116 is used to store information on the correspondence relationship between each buffer 122a to 122p provided in the input port 121 of the management-side I / F 111 and the types of signals input to these buffers 122a to 122p. Details of the content of the correspondence memory 116 will be described later.

[0224] The history memory 117 is a memory that does not require external power supply for memory retention, such as NOR-type flash memory and NAND-type flash memory (i.e., non-volatile memory means), and is used for both reading and writing. The history memory 117 is used to store information regarding the game history received from the main CPU 63 through the management-side I / F 111. Details of the content of the history memory 117 will be described later.

[0225] The calculation result memory 131 is a memory that does not require external power supply for memory retention, such as NOR-type flash memory and NAND-type flash memory (i.e., non-volatile memory means), and is used for both reading and writing. The calculation result memory 131 is used to sequentially store various parameters calculated by the management-side CPU 112 using the history information stored in the history memory 117. The content of the various parameters stored in the calculation result memory 131 is sequentially displayed on the first to third notification display devices 69a to 69c and output to an external device connected to the reading terminal 68d.

[0226] Next, the configuration of the input port 121 provided in the management-side I / F 111 will be described. FIG. 19 is an explanatory diagram for explaining the configuration of the input port 121 of the management-side I / F 111.

[0227] A plurality of buffers 122a to 122p are provided in the input port 121. Specifically, the first to sixteenth buffers 122a to 122p are provided. Each of the first to sixteenth buffers 122a to 122p can input one type of signal through signal paths 118a to 118p. When the signal to be input is at the LOW level, the information of "0" is stored as the first data in each of the first to sixteenth buffers 122a to 122p, and when the signal to be input is at the HI level, the information of "1" is stored as the second data. Note that the relationship between LOW and HI and the first and second data may be reversed.

[0228] A first signal corresponding to the detection result of the first winning port detection sensor 42a is input to the first buffer 122a. In this case, the main CPU 63 outputs a LOW-level first signal when no new game ball is detected by the first winning port detection sensor 42a, and outputs a HI-level first signal for a specific period when one game ball is detected by the first winning port detection sensor 42a. This specific period is sufficient for the management CPU 112 to specify that the HI-level first signal is input to the first buffer 122a.

[0229] A second signal corresponding to the detection result of the second winning port detection sensor 43a is input to the second buffer 122b. In this case, the main CPU 63 outputs a LOW-level second signal when no new game ball is detected by the second winning port detection sensor 43a, and outputs a HI-level second signal for a specific period when one game ball is detected by the second winning port detection sensor 43a. This specific period is sufficient for the management CPU 112 to specify that the HI-level second signal is input to the second buffer 122b.

[0230] A third signal corresponding to the detection result of the third winning port detection sensor 44a is input to the third buffer 122c. In this case, the main CPU 63 outputs a third signal of LOW level when no new game ball is detected by the third winning port detection sensor 44a, and outputs a third signal of HI level for a specific period when one game ball is detected by the third winning port detection sensor 44a. This specific period is long enough for the management CPU 112 to identify that a HI-level third signal is input to the third buffer 122c.

[0231] A fourth signal corresponding to the detection result of the special power detection sensor 45a is input to the fourth buffer 122d. In this case, the main CPU 63 outputs a fourth signal of LOW level when no new game ball is detected by the special power detection sensor 45a, and outputs a fourth signal of HI level for a specific period when one game ball is detected by the special power detection sensor 45a. This specific period is long enough for the management CPU 112 to identify that a HI-level fourth signal is input to the fourth buffer 122d.

[0232] A fifth signal corresponding to the detection result of the first operation port detection sensor 46a is input to the fifth buffer 122e. In this case, the main CPU 63 outputs a fifth signal of LOW level when no new game ball is detected by the first operation port detection sensor 46a, and outputs a fifth signal of HI level for a specific period when one game ball is detected by the first operation port detection sensor 46a. This specific period is long enough for the management CPU 112 to identify that a HI-level fifth signal is input to the fifth buffer 122e.

[0233] A sixth signal corresponding to the detection result of the second operation port detection sensor 47a is input to the sixth buffer 122f. In this case, the main CPU 63 outputs a LOW-level sixth signal when no new game ball is detected by the second operation port detection sensor 47a, and outputs a HI-level sixth signal for a specific period when one game ball is detected by the second operation port detection sensor 47a. This specific period is sufficient for the management-side CPU 112 to identify that a HI-level sixth signal is input to the sixth buffer 122f.

[0234] A seventh signal corresponding to the detection result of the out-port detection sensor 48a is input to the seventh buffer 122g. In this case, the main CPU 63 outputs a LOW-level seventh signal when no new game ball is detected by the out-port detection sensor 48a, and outputs a HI-level seventh signal for a specific period when one game ball is detected by the out-port detection sensor 48a. This specific period is sufficient for the management-side CPU 112 to identify that a HI-level seventh signal is input to the seventh buffer 122g.

[0235] An eighth signal corresponding to whether it is during the period of the opening / closing execution mode is input to the eighth buffer 122h. In this case, the main CPU 63 continuously outputs a LOW-level eighth signal when it is not in the opening / closing execution mode, and continuously outputs a HI-level eighth signal when it is in the opening / closing execution mode.

[0236] A ninth signal corresponding to whether it is during the period of the high-frequency support mode is input to the ninth buffer 122i. In this case, the main CPU 63 continuously outputs a LOW-level ninth signal when it is not in the high-frequency support mode, and continuously outputs a HI-level ninth signal when it is in the high-frequency support mode.

[0237] A 10th signal corresponding to whether or not the front door frame 14 is open during the period is input to the 10th buffer 122j. In this case, the main CPU 63 continuously outputs a 10th signal at a LOW level when the front door frame 14 is in the closed state, and continuously outputs a 10th signal at a HI level when the front door frame 14 is in the open state.

[0238] An 11th signal corresponding to whether or not a game round has started is input to the 11th buffer 122k. In this case, the main CPU 63 continuously outputs an 11th signal at a LOW level until a game round starts, and outputs an 11th signal at a HI level for a specific period when a game round starts. This specific period is long enough for the management CPU 112 to identify that a HI level 11th signal is input to the 11th buffer 122k.

[0239] A setting value update signal for causing the management CPU 112 to recognize that a new setting of the setting state of the pachinko machine 10 has been made by the main CPU 63 is input to the 15th buffer 122o. In this case, the main CPU 63 outputs a LOW level setting value update signal when no new setting of the setting state of the pachinko machine 10 is made, and outputs a pulse signal in which a HI level setting value update signal is maintained for a specific period corresponding to the newly set setting value for several minutes when a new setting of the setting state of the pachinko machine 10 is made. This specific period is long enough for the management CPU 112 to identify that a HI level setting value update signal is input to the 15th buffer 122o.

[0240] An output instruction signal for causing the management-side CPU 112 to recognize an opportunity to output the history information stored in the history memory 117 and various parameters stored in the operation result memory 131 to the read terminal 68d is input to the 16th buffer 122p. In this case, the master CPU 63 outputs a LOW-level output instruction signal when there is no need to output the history information, and outputs a HI-level output instruction signal for a specific period when it is necessary to output the history information. This specific period is long enough for the management-side CPU 112 to identify that a HI-level output instruction signal is input to the 16th buffer 122p.

[0241] Although the 12th buffer 122l, the 13th buffer 122m, and the 14th buffer 122n can receive signals from the master CPU 63, they are blank and do not receive normal signals in the pachinko machine 10. As described above, since a larger number of buffers 122a to 122p than the types of signals output from the master CPU 63 to the management IC 66 in the pachinko machine 10 are provided as the input ports 121 of the management-side I / F 111, the management IC 66 can be used in models different from the pachinko machine 10. This makes it possible to enhance the versatility of the management IC 66. Incidentally, signal paths 118a to 118p are formed between the master CPU 63 and each of the 1st to 16th buffers 122a to 122p so as to correspond one-to-one to the 1st to 16th buffers 122a to 122p, but it is not limited thereto, and signal paths 118l to 118n may not be formed between the buffers 122l to 122n to be blanked.

[0242] The input of the set value update signal to the 15th buffer 122o and the input of the output instruction signal to the 16th buffer 122p are determined at the design stage of the management IC66. Without receiving an instruction from the main CPU63, the management CPU112 can identify the input of the set value update signal to the 15th buffer 122o and the input of the output instruction signal to the 16th buffer 122p. On the other hand, what types of signals are input to the 1st to 14th buffers 122a to 122n are not determined at the design stage of the management IC66, and the types of these signals are identified by the management CPU112 upon receiving an instruction from the main CPU63. The identification of the types of these signals in the management CPU112, the details of which will be described later, is performed by the main CPU63 sending a type identification command to the management CPU112 when control starts in the main CPU63 and the management CPU112 with the start of the supply of operating power to the MPU62. In this case, the information on the types of various signals provided by the type identification command is stored in the correspondence memory 116, and when the management CPU112 identifies the types of various signals in the situation where operating power is being supplied, the information stored in the correspondence memory 116 is referred to.

[0243] Figure 20 is an explanatory diagram for explaining the configuration of the correspondence memory 116. In the correspondence memory 116, 1st to 14th correspondence areas 123a to 123n are provided in one-to-one correspondence with the 1st to 14th buffers 122a to 122n provided in the input port 121 of the management I / F 111.

[0244] In the first correspondence area 123a, information indicating that it is the general winning port 31 is stored as information for the management-side CPU 112 to identify the type of signal input to the first buffer 122a. Further, in the first correspondence area 123a, information indicating that it is the general winning port 31 and information on the number of game balls (10) to be paid out when one game ball enters the general winning port 31 are also stored. In the second correspondence area 123b, information indicating that it is the general winning port 31 is stored as information for the management-side CPU 112 to identify the type of signal input to the second buffer 122b. Further, in the second correspondence area 123b, information indicating that it is the general winning port 31 and information on the number of game balls (10) to be paid out when one game ball enters the general winning port 31 are also stored. In the third correspondence area 123c, information indicating that it is the general winning port 31 is stored as information for the management-side CPU 112 to identify the type of signal input to the third buffer 122c. Further, in the third correspondence area 123c, information indicating that it is the general winning port 31 and information on the number of game balls (10) to be paid out when one game ball enters the general winning port 31 are also stored.

[0245] In the fourth correspondence area 123d, information indicating that it is the special electric winning device 32 is stored as information for the management side CPU 112 to identify the type of signal input to the fourth buffer 122d. Further, in the fourth correspondence area 123d, information indicating that it is the special electric winning device 32 and information on the number of game balls paid out when one game ball enters the special electric winning device 32 (15 balls) are also stored. In the fifth correspondence area 123e, information indicating that it is the first operation port 33 is stored as information for the management side CPU 112 to identify the type of signal input to the fifth buffer 122e. Further, in the fifth correspondence area 123e, information indicating that it is the first operation port 33 and information on the number of game balls paid out when one game ball enters the first operation port 33 (1 ball) are also stored. In the sixth correspondence area 123f, information indicating that it is the second operation port 34 is stored as information for the management side CPU 112 to identify the type of signal input to the sixth buffer 122f. Further, in the sixth correspondence area 123f, information indicating that it is the second operation port 34 and information on the number of game balls paid out when one game ball enters the second operation port 34 (1 ball) are also stored. In the seventh correspondence area 123g, information indicating that it is the out port 24a is stored as information for the management side CPU 112 to identify the type of signal input to the seventh buffer 122g.

[0246] In the eighth correspondence area 123h, information indicating that it is the opening / closing execution mode is stored as information for the management side CPU 112 to identify the type of signal input to the eighth buffer 122h. In the ninth correspondence area 123i, information indicating that it is the high-frequency support mode is stored as information for the management side CPU 112 to identify the type of signal input to the ninth buffer 122i. In the tenth correspondence area 123j, information indicating that it is the front door frame 14 is stored as information for the management side CPU 112 to identify the type of signal input to the tenth buffer 122j. In the eleventh correspondence area 123k, information indicating the start of a game round is stored as information for the management side CPU 112 to identify the type of signal input to the eleventh buffer 122k.

[0247] In the 12th correspondence relation area 123l, information indicating that it is a blank not corresponding to any information for specifying the type of signal input to the 12th buffer 122l by the management-side CPU 112 is stored. In the 13th correspondence relation area 123m, information indicating that it is a blank not corresponding to any information for specifying the type of signal input to the 13th buffer 122m by the management-side CPU 112 is stored. In the 14th correspondence relation area 123n, information indicating that it is a blank not corresponding to any information for specifying the type of signal input to the 14th buffer 122n by the management-side CPU 112 is stored.

[0248] As described above, by adopting a configuration in which the management-side CPU 112 specifies the types of signals input to the 1st to 14th buffers 122a to 122n by receiving an instruction from the main-side CPU 63, the management IC 66 can be applied to models different from this pachinko machine 10. Thereby, it becomes possible to enhance the versatility of the management IC 66.

[0249] Also, instead of outputting information for recognizing the type of the signal every time a signal output corresponding to the storage of history information is performed to the 1st to 14th buffers 122a to 122n, information for recognizing the type of the signal is output in advance, and information for specifying the types of signals input to the 1st to 14th buffers 122a to 122n by the management-side CPU 112 based on the output information is stored in the correspondence relation memory 116. Thereby, compared with a configuration in which information for recognizing the type of the signal is output every time a signal output corresponding to the storage of history information is performed to the 1st to 14th buffers 122a to 122n, it becomes possible to suppress the amount of information output from the main-side CPU 63 to the management-side CPU 112 at the time of each signal output.

[0250] In addition, the output of information for identifying the types of signals input to the first to fourteenth buffers 122a to 122n is performed by the management-side CPU 112 at the start of the supply of operating power. Thereby, in the situation where a game is started in the pachinko machine 10, it becomes possible for the management-side CPU 112 to identify the types of signals input to the first to fourteenth buffers 122a to 122n.

[0251] In addition, the information setting for the input of the set value update signal to the fifteenth buffer 122o and the information setting for the input of the output instruction signal to the sixteenth buffer 122p are performed at the design stage of the management IC 66. Thereby, not only in the pachinko machine 10 but also in other models of pachinko machines that use the management IC 66, it becomes possible to omit the process for identifying the types of signals input to the fifteenth buffer 122o and the sixteenth buffer 122p for the set value update signal and the output instruction signal that are surely used. Therefore, it becomes possible to suppress the processing load of the process for identifying the types of such signals.

[0252] Next, the history memory 117 of the management IC 66 will be described. FIG. 21 is an explanatory diagram for explaining the configuration of the history memory 117.

[0253] The history memory 117 is provided with a history area 124 for sequentially storing history information. In the history area 124, a plurality of pointer information is set in serial numbers, and a history information storage area 125 is set in one-to-one correspondence with each pointer information. The history information storage area 125 can store a combination of RTC information and correspondence relationship information. In this case, each history information storage area 125 has a data capacity of 2 bytes, a data capacity of 1 byte is allocated as an area for storing RTC information, and a data capacity of 1 byte is allocated as an area for storing the correspondence relationship information. When it is necessary to store the correspondence relationship information according to the signals input to the first to fourteenth buffers 122a to 122n (in the case of this pachinko machine 10, actually the first to eleventh buffers 122a to 122k), first, the current RTC115 The date and time information measured in is stored in the area for storing the RTC information of the history information storage area 125 corresponding to the pointer information that is currently the write target. After that, the correspondence relationship information corresponding to the buffers 122a to 122n that triggered this information storage is read from the correspondence relationship areas 123a to 123n corresponding to the buffers 122a to 122n in the correspondence relationship memory 116, and the read correspondence relationship information is stored in the area for storing the correspondence relationship information of the history information storage area 125 corresponding to the pointer information that is currently the write target.

[0254] Specifically regarding the correspondence information stored in the history information storage area 125, as described above, signals corresponding to the detection results of the ball entry detection sensors 42a to 48a are input to the first to seventh buffers 122a to 122g. Therefore, information corresponding to the types of the ball entry detection sensors 42a to 48a is stored in the first to seventh correspondence areas 123a to 123g in the correspondence memory 116. More specifically, information corresponding to the types of the ball entry parts corresponding to each of the ball entry detection sensors 42a to 48a is stored in the first to seventh correspondence areas 123a to 123g. In this pachinko machine 10, as described above, since the first to third winning port detection sensors 42a to 44a all detect the game balls that have entered the general winning port 31, information indicating that it is the general winning port 31 is stored in the first to third correspondence areas 123a to 123c corresponding to these first to third winning port detection sensors 42a to 44a. Also, information indicating that it is the special winning device 32 is stored in the fourth correspondence area 123d, information indicating that it is the first operating port 33 is stored in the fifth correspondence area 123e, information indicating that it is the second operating port 34 is stored in the sixth correspondence area 123f, and information indicating that it is the out port 24a is stored in the seventh correspondence area 123g. When the buffers 122a to 122n that triggered the current information storage are any of the first to seventh buffers 122a to 122g, the information on the type of the ball entry part corresponding to that buffer 122a to 122g is read from any of the first to seventh correspondence areas 123a to 123g, and the read information on the type of the ball entry part is directly stored in the area for storing the correspondence information in the history information storage area 125.

[0255] On one hand, a signal indicating whether the 8th buffer 122h is in the open / close execution mode is input, a signal indicating whether the 9th buffer 122i is in the high-frequency support mode is input, a signal indicating whether the front door frame 14 is open is input to the 10th buffer 122j, and a signal indicating whether a game round has started is input to the 11th buffer 122k. Therefore, information indicating that it is in the open / close execution mode is stored in the 8th corresponding relationship area 123h, information indicating that it is in the high-frequency support mode is stored in the 9th corresponding relationship area 123i, information indicating that it is the front door frame 14 is stored in the 10th corresponding relationship area 123j, and information indicating that it is a game round is stored in the 11th corresponding relationship area 123k.

[0256] As described above, the main CPU 63 continuously outputs the 8th signal at the LOW level in a situation where it is not in the open / close execution mode, and continuously outputs the 8th signal at the HI level in a situation where it is in the open / close execution mode. Therefore, the management CPU 112 can identify that the open / close execution mode has started when the 8th signal changes from the LOW level to the HI level, and can identify that the open / close execution mode has ended when the 8th signal changes from the HI level to the LOW level. And in both cases where the 8th signal changes from the LOW level to the HI level and from the HI level to the LOW level, the management CPU 112 identifies that an opportunity to store the corresponding relationship information in the history information storage area 125 has occurred. That is, when the 8th signal changes from the LOW level to the HI level, not only the information indicating that it is in the open / close execution mode read from the 8th corresponding relationship area 123h but also the start information is stored together in the area for storing the corresponding relationship information in the history information storage area 125. Also, when the 8th signal changes from the HI level to the LOW level, not only the information indicating that it is in the open / close execution mode read from the 8th corresponding relationship area 123h but also the end information is stored together in the area for storing the corresponding relationship information in the history information storage area 125.

[0257] As described above, the master CPU 63 continuously outputs the 9th signal at LOW level when not in the high-frequency support mode, and continuously outputs the 9th signal at HI level when in the high-frequency support mode. Therefore, the management CPU 112 can identify that the high-frequency support mode has started when the 9th signal changes from LOW level to HI level, and can identify that the high-frequency support mode has ended when the 9th signal changes from HI level to LOW level. And in both cases where the 9th signal changes from LOW level to HI level and where it changes from HI level to LOW level, the management CPU 112 identifies that an opportunity to store the correspondence information in the history information storage area 125 has occurred. That is, when the 9th signal changes from LOW level to HI level, not only the information indicating that it is in the high-frequency support mode read from the 9th correspondence area 123i but also the start information are stored together in the area for storing the correspondence information in the history information storage area 125. Also, when the 9th signal changes from HI level to LOW level, not only the information indicating that it is in the high-frequency support mode read from the 9th correspondence area 123i but also the end information are stored together in the area for storing the correspondence information in the history information storage area 125.

[0258] As described above, the main CPU 63 continuously outputs the 10th signal at LOW level when the front door frame 14 is in the closed state, and continuously outputs the 10th signal at HI level when the front door frame 14 is in the open state. Therefore, the management CPU 112 can identify that the front door frame 14 has been opened when the 10th signal changes from LOW level to HI level, and can identify that the front door frame 14 has been closed when the 10th signal changes from HI level to LOW level. And in either case where the 10th signal changes from LOW level to HI level or from HI level to LOW level, the management CPU 112 identifies that an opportunity to store the correspondence information in the history information storage area 125 has occurred. That is, when the 10th signal changes from LOW level to HI level, not only the information indicating that it is the front door frame 14 read from the 10th correspondence area 123j but also the opening start information are stored together in the area for storing the correspondence information in the history information storage area 125. Also, when the 10th signal changes from HI level to LOW level, not only the information indicating that it is the front door frame 14 read from the 10th correspondence area 123j but also the opening end information are stored together in the area for storing the correspondence information in the history information storage area 125.

[0259] As described above, the main CPU 63 continuously outputs the 11th signal at LOW level until the start timing of the game round, and outputs the 11th signal at HI level for a specific period when the start timing of the game round arrives. Therefore, the management CPU 112 identifies that the game round has started when the 11th signal changes from LOW level to HI level. That is, when the 11th signal changes from LOW level to HI level, the information indicating that it is the game round read from the 11th correspondence area 123k is stored in the area for storing the correspondence information in the history information storage area 125.

[0260] The history information storage area 125 is provided with several minutes' worth of storage space that can store all the history information generated during the continuous operation of the pachinko machine 10 for 10 consecutive business days, even if the firing of game balls continues during that period. For example, if 60,000 pieces of history information are generated in one day, more than 600,000 history information storage areas 125 are provided. This enables the history memory 117 to store and retain all the history information for at least 10 days.

[0261] In addition to the history area 124, a pointer area 126 is provided in the history memory 117. The pointer area 126 stores information for the management-side CPU 112 to identify the pointer information that is currently the write target in the history memory 117. Specifically, at the time of shipment of the pachinko machine 10, information designating the pointer information of "0" as the write target is set in the pointer area 126. Then, each time a piece of history information is newly stored in the history information storage area 125, the information in the pointer area 126 is updated so that the value of the pointer information for the write target is incremented by 1. When the last-order pointer information becomes the write target and history information is stored in the history information storage area 125 corresponding to the last-order pointer information, the information in the pointer area 126 is updated so that the pointer information of "0" becomes the write target. As a result, when a storage trigger for history information occurs beyond the number of storable history information, the old history information is overwritten by the new history information in the history information storage areas 125 in order.

[0262] Also, when the external device reads the history information from the history memory 117, all the history information storage areas 125 are cleared to "0", and the information in the pointer area 126 is updated so that the pointer information of "0" becomes the write target. This makes it possible to prevent the history information that has once been the read target from becoming the read target again.

[0263] Next, a specific processing configuration for managing game history using the management IC 66 will be described. First, a processing configuration for storing information on the correspondence relationship between the first to fourteenth buffers 122a to 122n provided in the input port 121 of the management-side I / F 111 and the types of signals in the correspondence relationship memory 116 will be described. FIG. 22 is a flowchart showing the recognition processing executed by the main CPU 63. Note that the recognition processing is executed in step S111 in the main processing (FIG. 9).

[0264] First, "14" is set in the recognition output counter provided in the main RAM 65 (step S801). The recognition output counter is a counter for the main CPU 63 to specify the remaining required number of times of information output for the management-side CPU 112 to recognize which types of signals the first to fourteenth buffers 122a to 122n in the input port 121 of the management-side I / F 111 correspond to. Since the 14 first to fourteenth buffers 122a to 122n are the objects of recognition of the signal types as already described, "14" is set in the recognition output counter.

[0265] Thereafter, the output process of the identification start command is executed (step S802). The host CPU 63 outputs various commands to the management CPU 112 in order to make the management CPU 112 recognize which type of signal the first to fourteenth buffers 122a to 122n correspond to. When outputting this command, the first to eighth signals input to the first to eighth buffers 122a to 122h are used. That is, the first to eighth signals (i.e., the first to eighth signal paths 118a to 118h) used to instruct the management CPU 112 of the opportunity to store history information are used to output a command for the management CPU 112 to recognize which type of signal the first to fourteenth buffers 122a to 122n correspond to. Thereby, compared with a configuration in which the signal path for outputting this command is provided separately from the signal paths 118a to 118p for outputting signals to the first to sixteenth buffers 122a to 122p, the number of signal paths can be reduced and the configuration can be simplified. The identification start command has a data capacity of 8 bits, and the data of each bit is input to the first to eighth buffers 122a to 122h as the first to eighth signals, respectively. Further, in the output process of the identification start command, in order to make the management CPU 112 recognize that a new command has been transmitted, the output state of the ninth signal is switched to the HI level at the timing of starting the output of the identification start command. Also, the output period of the identification start command and the period for maintaining the output state of the ninth signal at the HI level are set to a period sufficient for the management CPU 112 to recognize these identification start command and the output state of the ninth signal. By receiving the identification start command, the management CPU 112 specifies that it should start a process for storing information on the correspondence between the first to fourteenth buffers 122a to 122n and the types of signals in the correspondence memory 116.

[0266] Thereafter, a type identification command corresponding to the current value of the recognition output counter of the main-side RAM 65 is read from the main-side ROM 64 (step S803). In this case, the first buffer 122a is the first to be the target for setting the signal type, and thereafter, the recognition settings for the signal types corresponding to the first to fourteenth buffers 122a to 122n are performed such that the (n + 1)-th buffer becomes the target for setting the signal type after the n-th buffer. Therefore, if the recognition output counter is "14" to "12", a type identification command indicating that it is the general winning port 31 and the number of prize balls thereof is read; if the recognition output counter is "11", a type identification command indicating that it is the special electric winning device 32 and the number of prize balls thereof is read; if the recognition output counter is "10", a type identification command indicating that it is the first operation port 33 and the number of prize balls thereof is read; if the recognition output counter is "9", a type identification command indicating that it is the second operation port 34 and the number of prize balls thereof is read; if the recognition output counter is "8", a type identification command indicating that it is the out port 24a is read; if the recognition output counter is "7", a type identification command indicating that it is the open / close execution mode is read; if the recognition output counter is "6", a type identification command indicating that it is the high-frequency support mode is read; if the recognition output counter is "5", a type identification command indicating that it is the front door frame 14 is read; if the recognition output counter is "4", a type identification command indicating that it is a game turn is read; and if the recognition output counter is "3" to "1", a type identification command indicating that it is blank is read.

[0267] Thereafter, the output process of the read type identification command is executed (step S804). The type identification command has a data capacity of 8 bits, similar to the identification start command, and the data of each bit is input into the first to eighth buffers 122a to 122h as the first to eighth signals, respectively. Also, in the output process of the identification type command, in order to make the management-side CPU 112 recognize that a new command has been transmitted, the output state of the ninth signal is switched to the HI level at the timing of starting the output of the identification type command. Also, the output period of the identification type command and the period for maintaining the output state of the ninth signal at the HI level are set to a period sufficient for the management-side CPU 112 to recognize these identification type commands and the output state of the ninth signal. By receiving the identification type command, the management-side CPU 112 stores the information corresponding to the identification type command in the corresponding relationship areas 123a to 123n corresponding to the buffers that are the current setting targets among the first to fourteenth buffers 122a to 122n.

[0268] Thereafter, the value of the recognition output counter in the main-side RAM 65 is decremented by 1 (step S805), and it is determined whether the value of the recognition output counter after the decrement by 1 is "0" (step S806). If the value of the recognition output counter is 1 or more (step S806: NO), the process for outputting the type identification command corresponding to the value of the recognition output counter after the decrement by 1 is executed (steps S803 and S804).

[0269] On one hand, when the value of the recognition output counter is "0" (step S806: YES), the output process of the identification end command is executed (step S807). The identification end command has a data capacity of 8 bits, and the data of each bit is input into the first to eighth buffers 122a to 122h as the first to eighth signals, respectively. Also, in the output process of the identification end command, in order to let the management side CPU 112 recognize that a new command has been transmitted, the output state of the ninth signal is switched to the HI level at the timing of starting the output of the identification end command. Also, the output period of the identification end command and the period for maintaining the output state of the ninth signal at the HI level are set to a period sufficient for the management side CPU 112 to recognize these identification end command and the output state of the ninth signal. By receiving the identification end command, the management side CPU 112 identifies that the process for storing the information on the correspondence between the first to fourteenth buffers 122a to 122n and the signal types in the correspondence relationship memory 116 has been completed.

[0270] Next, the management process executed by the management side CPU 112 will be described with reference to the flowchart of FIG. 23. The management process starts when the supply of operating power to the management side CPU 112 is started. Note that the processing speed of the management side CPU 112 is configured to be faster than the processing speed of the main side CPU 63. After one timer interrupt process (FIG. 11) is started in the main side CPU 63 until the next timer interrupt process (FIG. 11) is started, the combination of the processes after step S908 in the management process is executed 16 times or more.

[0271] First, it is determined whether an identification start command has been received from the main side CPU 63 (step S901). If the identification start command has not been received (step S901: NO), after executing the setting update recognition process (step S902), the process returns to step S901. In the setting update recognition process, although the details will be described later, when a new setting of the setting state of the pachinko machine 10 is made by the main side CPU 63, the corresponding process is executed.

[0272] When the main CPU 63 receives an identification start command (step S901: YES), the value of the counter to be set provided in the management-side RAM 114 is cleared to "0" (step S903). The counter to be set is a counter for the management-side CPU 112 to identify the types of the buffers 122a to 122n that are the targets for setting the signal types. The first buffer 122a becomes the target for setting the signal type first, and thereafter, the (n + 1)-th buffer becomes the target for setting the signal type after the n-th buffer.

[0273] Thereafter, on the condition that the main CPU 63 has received a type identification command (step S904: YES), the correspondence relationship setting process is executed (step S905). In the correspondence relationship setting process, among the first to fourteenth correspondence relationship areas 123a to 123n of the correspondence relationship memory 116, the information on the signal type set in the type identification command received this time is stored in the correspondence relationship area corresponding to the current value in the counter to be set in the management-side RAM 114. Thereafter, the value of the counter to be set in the management-side RAM 114 is incremented by 1 (step S906).

[0274] If a negative determination is made in step S904, or if the process of step S906 is executed, it is determined whether the main CPU 63 has received an identification end command (step S907). If the identification end command has not been received (step S907: NO), the process returns to step S904, and on the condition that the main CPU 63 newly receives a type identification command (step S904: YES), the processes of step S905 and step S906 are executed again.

[0275] When the main CPU 63 has received an identification completion command (step S907: YES), the processes of steps S908 to S910 are repeatedly executed. Although details will be described later, in step S908, a history setting process is executed to store history information corresponding to the type of signal received from the main CPU 63 in the history memory 117. Although details will be described later, in step S909, a display output process is executed to calculate various parameters using the history information stored in the history memory 117 and notify the calculation results on the first to third notification display devices 69a to 69c. Although details will be described later, in step S910, an external output process is executed to output the history information stored in the history memory 117 and various parameters stored in the calculation result memory 131 to the reading terminal 68d.

[0276] FIG. 24 is a time chart showing a state in which information on the correspondence relationship between the first to fourteenth buffers 122a to 122n and the types of signals input to these buffers 122a to 122n is stored in the correspondence relationship memory 116. FIG. 24(a) shows a period during which a command is output from the main CPU 63 to the management CPU 112 using the first to eighth signals (i.e., the first to eighth signal paths 118a to 118h), FIG. 24(b) shows a period during which the output state of the ninth signal is at the HI level, FIG. 24(c) shows an execution period of an identification state in which a process for identifying the correspondence relationship between the first to fourteenth buffers 122a to 122n and the types of signals input to these buffers 122a to 122n is executed, and FIG. 24(d) shows a timing at which the correspondence relationship setting process (step S905) is executed by the management CPU 112.

[0277] When the supply of operating power to the main CPU 63 and the management CPU 112 is started, the output of an identification start command using the first to eighth signals starts at timing t1 as shown in Fig. 24(a). Also, at the timing t1, the output state of the ninth signal is changed from the LOW level to the HI level as shown in Fig. 24(b). Then, at timing t2 when the output of the identification start command is continuing, the output state of the ninth signal is changed from the HI level to the LOW level as shown in Fig. 24(b). The management CPU 112 identifies that a command is being transmitted from the main CPU 63 by confirming that the output state of the ninth signal has changed from the HI level to the LOW level, and grasps the content of the command received from the main CPU 63 by checking the information in the first to eighth buffers 122a to 122h. In this case, since the identification start command is being received, the management CPU 112 makes an affirmative determination in step S901 of the management process (Fig. 23) to enter the identification state. Then, the output of the identification start command stops at timing t3 as shown in Fig. 24(a).

[0278] After that, at the timing of t4, as shown in FIG. 24(a), the output of the first type identification command using the first to eighth signals is started. Also, at the timing of t4, as shown in FIG. 24(b), the output state of the ninth signal is changed from the LOW level to the HI level. After that, at the timing of t5 when the output of the type identification command is continuing, as shown in FIG. 24(b), the output state of the ninth signal is changed from the HI level to the LOW level. The management-side CPU 112 identifies that a command has been transmitted from the main-side CPU 63 by confirming that the output state of the ninth signal has changed from the HI level to the LOW level, and grasps the content of the command received from the main-side CPU 63 by checking the information in the first to eighth buffers 122a to 122h. In this case, since the first type identification command is being received, the management-side CPU 112 executes the correspondence relationship setting process as shown in FIG. 24(d) at the timing of t5. In the correspondence relationship setting process, information indicating that it is the general winning port 31 and information on the number of winning balls are stored in the first correspondence area 123a of the correspondence relationship memory 116. After that, at the timing of t6, as shown in FIG. 24(a), the output of the type identification command is stopped.

[0279] After that, at each of the timings from t7 to t9, from t10 to t12, from t13 to t15, and from t16 to t18, similar to the timings from t4 to t6, the management-side CPU 112 executes the correspondence relationship setting process corresponding to the type identification command output from the main-side CPU 63. In this case, at the timings from t16 to t18, the correspondence relationship setting process corresponding to the 14th type identification command is completed.

[0280] Thereafter, at the timing of t19, as shown in Fig. 24(a), the output of the identification end command using the first to eighth signals is started. Also, at the timing of t19, as shown in Fig. 24(b), the output state of the ninth signal is changed from the LOW level to the HI level. Thereafter, at the timing of t20 when the output of the identification end command is continuing, as shown in Fig. 24(b), the output state of the ninth signal is changed from the HI level to the LOW level. The management-side CPU 112 identifies that a command has been transmitted from the main-side CPU 63 by confirming that the output state of the ninth signal has changed from the HI level to the LOW level, and grasps the content of the command received from the main-side CPU 63 by checking the information in the first to eighth buffers 122a to 122h. In this case, since the identification end command is being received, the identification state of the management-side CPU 112 ends as shown in Fig. 24(c) at the timing of t20. Thereafter, at the timing of t21, the output of the identification end command is stopped as shown in Fig. 24(a).

[0281] With the configuration that allows the management-side CPU 112 to recognize whether or not a command is being output using the ninth signal as described above, even in a configuration where command output is performed using the first to eighth signals (i.e., the first to eighth signal paths) that are used to instruct the management-side CPU 112 of the timing for storing history information, it is possible to clearly make the management-side CPU 112 recognize that a command is being output.

[0282] Next, a processing configuration for storing the history information in the history memory 117 will be described. Fig. 25 is a flowchart showing the management output processing executed by the main-side CPU 63. Note that the management output processing is executed in step S319 in the timer interrupt processing (Fig. 11).

[0283] First, set "11" in the counter to be managed provided in the main-side RAM 65 (step S1001). The counter to be managed is a counter for the main-side CPU 63 to identify whether there is a management target that is not the target to be identified for whether to change the signal output state to the management-side CPU 112 in the current management output process, and to identify for which management target the signal output state to the management-side CPU 112 should be changed. In one management output process, the management targets for which the main-side CPU 63 determines whether to change the signal output state to the management-side CPU 112 are a total of 11, including the seven ball-in detection sensors 42a to 48a, the presence or absence of execution of the open / close execution mode, the presence or absence of execution of the high-frequency support mode, the presence or absence of opening / closing of the front door frame 14, and the presence or absence of start of a game round. Therefore, first set "11" in the counter to be managed.

[0284] Thereafter, it is determined whether the output state of the signal to the management-side CPU 112 for the management target corresponding to the current value of the counter to be managed is at the HI level (step S1002). If it is not at the HI level (step S1002: NO), by determining whether the value of the counter to be managed is 5 or more, it is identified whether the management target corresponding to the value of the counter to be managed is any of the seven ball-in detection sensors 42a to 48a (step S1003).

[0285] If an affirmative determination is made in step S1003, it is determined whether "1" is set in the output flag of the main-side RAM 65 corresponding to the value of the counter to be managed (step S1004). Specifically, when the value of the counter to be managed is "11" and corresponds to the first winning port detection sensor 42a, it is determined whether "1" is set in the first output flag. When the value of the counter to be managed is "10" and corresponds to the second winning port detection sensor 43a, it is determined whether "1" is set in the second output flag. When the value of the counter to be managed is "9" and corresponds to the third winning port detection sensor 44a, it is determined whether "1" is set in the third output flag. When the value of the counter to be managed is "8" and corresponds to the special power detection sensor 45a, it is determined whether "1" is set in the fourth output flag. When the value of the counter to be managed is "7" and corresponds to the first operation port detection sensor 46a, it is determined whether "1" is set in the fifth output flag. When the value of the counter to be managed is "6" and corresponds to the second operation port detection sensor 47a, it is determined whether "1" is set in the sixth output flag. When the value of the counter to be managed is "5" and corresponds to the out port 24a, it is determined whether "1" is set in the seventh output flag. Note that, as already described, "1" is set in these first to seventh output flags in the ball entry detection process (FIG. 15).

[0286] When "1" is set in the output flag corresponding to the value of the counter to be managed (step S1004: YES), the output state of the signal corresponding to the value of the counter to be managed among the first to seventh signals is set to the HI level (step S1005). Then, the output flag corresponding to the value of the counter to be managed is cleared to "0" (step S1006).

[0287] When a negative determination is made in step S1003, it is determined whether an opportunity has occurred to switch the output state of the signal corresponding to the value of the counter to be managed to the HI level (step S1007). Specifically, when the value of the counter to be managed is "4", it is determined whether a transition to the open / close execution mode has occurred, and when the value of the counter to be managed is "3", it is determined whether a transition to the high-frequency support mode has occurred. When the value of the counter to be managed is "2", it is determined whether the front door frame 14 has been opened, and when the value of the counter to be managed is "1", it is determined whether the game has started by determining whether "1" is set in the 11th output flag. When an affirmative determination is made in step S1007, the output state of the signal corresponding to the value of the counter to be managed is set to the HI level (step S1008). When the process of step S1008 is executed when the value of the counter to be managed is "1", the 11th output flag is cleared to "0".

[0288] When a positive determination is made in step S1002, it is determined whether or not an opportunity has occurred to switch the output state of the signal corresponding to the value of the counter to be managed to the LOW level (step S1009). Specifically, when the value of the counter to be managed is 5 or more or "1" and the current management target is any of the ball entry detection sensors 42a to 48a or the start of a game round, it is determined whether or not the HI output continuation period (specifically, 10 msec) has elapsed after switching the output state of the signal corresponding to the value of the counter to be managed among the first to seventh signals and the eleventh signal from the LOW level to the HI level. This HI output continuation period is set to a period longer than the longest processing interval of the history setting process (step S908) of the management process (FIG. 23) in the management side CPU 112, and it is a period in which the management side CPU 112 can surely identify the output state of the signal switched from the LOW level to the HI level. Also, when the value of the counter to be managed is "4" and the current management target is the open / close execution mode, it is determined whether or not the open / close execution mode has ended. When the value of the counter to be managed is "3" and the current management target is the high-frequency support mode, it is determined whether or not the high-frequency support mode has ended. When the value of the counter to be managed is "2" and the current management target is the front door frame 14, it is determined whether or not the front door frame 14 is in the closed state. When an opportunity has occurred to switch the output state of the signal corresponding to the value of the counter to be managed to the LOW level (step S1009: YES), the output state of the signal corresponding to the value of the counter to be managed is set to the LOW level (step S1010).

[0289] If a negative determination is made in step S1004, if the process of step S1006 is executed, if a negative determination is made in step S1007, if the process of step S1008 is executed, if a negative determination is made in step S1009, or if the process of step S1010 is executed, the value of the management target counter in the main side RAM 65 is decremented by 1 (step S1011). Then, it is determined whether or not the value of the management target counter after the decrement by 1 is "0" (step S1012). If the value of the management target counter is 1 or more (step S1012: NO), for the management target corresponding to the new value of the management target counter, the processes after step S1002 are executed.

[0290] Next, the history setting process executed by the management side CPU 112 will be described with reference to the flowchart of FIG. 26. The history setting process is executed in step S908 of the management process (FIG. 23).

[0291] First, the number of buffers to be confirmed in the management side CPU 112 among the first to fourteenth buffers 122a to 122n is set in the confirmation target counter provided in the management side RAM 114 (step S1101). Specifically, the number of correspondence relation areas in which information other than the information indicating blank among the first to fourteenth correspondence relation areas 123a to 123n in the correspondence relation memory 116 is stored is specified, and the information of the specified number is set in the confirmation target counter. In this pachinko machine 10, as already described, information other than the information indicating blank is stored in the first to eleventh correspondence relation areas 123a to 123k. Therefore, in step S1101, "11" is set in the confirmation target counter.

[0292] Thereafter, by checking whether the numerical information stored in the buffer corresponding to the value of the current confirmation target counter among the first to fourteenth buffers 122a to 122n has been changed from "0" to "1", it is determined whether the output state of the input signal from the master CPU 63 to the buffer has been switched from the LOW level to the HI level (step S1102). When the value of the confirmation target counter is "n", the nth buffer 122a to 122n is the target for checking the numerical information. For example, if the value of the confirmation target counter is "11", the 11th buffer 122k is the target for checking the numerical information, and if the value of the confirmation target counter is "5", the 5th buffer 122e is the target for checking the numerical information.

[0293] If an affirmative determination is made in step S1102, RTC information, which is year / month / day information and time information, is read from RTC 115 (step S1103). Then, a writing process to the history memory 117 is executed (step S1104). In this writing process, by referring to the pointer area 126 of the history memory 117, the pointer information of the history area 124 that is the current writing target is specified, and the RTC information read in step S1103 is written to the history information storage area 125 of the history area 124 corresponding to the pointer information that is the writing target. Also, correspondence information is read from the correspondence areas 123a to 123n corresponding to the value of the current confirmation target counter, and the correspondence information is written to the history information storage area 125 corresponding to the pointer information that is the writing target. Further, when the correspondence information is any one of information indicating the open / close execution mode, information indicating the high-frequency support mode, and information indicating the front door frame 14, not only the correspondence information but also start information is written to the history information storage area 125 corresponding to the pointer information that is the writing target. Note that when the value of the confirmation target counter is "n", the nth correspondence areas 123a to 123n are the reading targets of the correspondence information. For example, if the value of the confirmation target counter is "11", the 11th correspondence area 123k is the reading target of the correspondence information, and if the value of the confirmation target counter is "5", the 5th correspondence area 123e is the reading target of the correspondence information.

[0294] By executing the writing process as described above, when the value of the confirmation target counter is any one of the output port 24a, the general winning port 31, the special electric winning device 32, the first operation port 33, the second operation port 34, and the game turn, in the history information storage area 125 corresponding to the pointer information to be written, a combination of the RTC information and the correspondence information indicating that it is any one of the output port 24a, the general winning port 31, the special electric winning device 32, the first operation port 33, the second operation port 34, and the game turn is stored as the history information. Also, when the value of the confirmation target counter is any one of the opening / closing execution mode, the high-frequency support mode, and the front door frame 14, in the history information storage area 125 corresponding to the pointer information to be written, a combination of the RTC information, the correspondence information indicating that it is any one of the opening / closing execution mode, the high-frequency support mode, and the front door frame 14, and the start information is stored as the history information.

[0295] Thereafter, an update process for the target pointer is executed (step S1105). In this update process, the numerical information stored in the pointer area 126 of the history memory 117 is read out and incremented by 1. It is determined whether the pointer information after the increment of 1 exceeds the maximum value of the pointer information in the history area 124. If it does not exceed the maximum value, the pointer information after the increment of 1 is overwritten in the pointer area 126 as the new pointer information to be written. If it exceeds the maximum value, the pointer area 126 is cleared to "0" so that the pointer information to be written becomes the first pointer information.

[0296] When a negative determination is made in step S1102, or when the process of step S1105 is executed, it is determined whether correspondence information to be checked as to whether the signal output has been switched to the LOW level is stored in the correspondence area 123a to 123n corresponding to the value of the current confirmation target counter (step S1106). Specifically, when the value of the current confirmation target counter is from "8" to "10", since any one of the information indicating that it is in the opening / closing execution mode, the information indicating that it is in the high-frequency support mode, and the information indicating that it is the front door frame 14 is stored in the corresponding correspondence areas 123h to 123j, an affirmative determination is made in step S1106.

[0297] If an affirmative determination is made in step S1106, it is determined whether the numerical information stored in the buffer corresponding to the value of the current confirmation target counter among the first to fourteenth buffers 122a to 122n has been changed from "1" to "0", thereby determining whether the output state of the input signal from the host CPU 63 to the buffer has been switched from the HI level to the LOW level (step S1107). If an affirmative determination is made in step S1107, the RTC information is read in the same manner as in step S1103 (step S1108), and further, a writing process to the history memory 117 is executed (step S1109). In this writing process, the RTC information read in step S1108 is written to the history information storage area 125 of the history area 124 corresponding to the pointer information to be written. Also, the correspondence information is read from the correspondence areas 123a to 123n corresponding to the value of the current confirmation target counter, and the correspondence information is written to the history information storage area 125 corresponding to the pointer information to be written. Further, not only the correspondence information but also the end information is written to the history information storage area 125 corresponding to the pointer information to be written. By executing the writing process in this way, when the value of the confirmation target counter is any one of the opening / closing execution mode, the high-frequency support mode, and the front door frame 14, the history information storage area 125 corresponding to the pointer information to be written stores a combination of the RTC information, the correspondence information indicating that it is any one of the opening / closing execution mode, the high-frequency support mode, and the front door frame 14, and the end information as history information. Thereafter, the update process of the target pointer is executed in the same manner as in step S1105 (step S1110).

[0298] When a negative determination is made in step S1106, when a negative determination is made in step S1107, or when the process of step S1110 is executed, the value of the counter to be confirmed in the management side RAM 114 is decremented by 1 (step S1111). Then, it is determined whether the value of the counter to be confirmed after the decrement by 1 is "0" (step S1112). When the value of the counter to be confirmed is 1 or more (step S1112: NO), the processes after step S1102 are executed for the object to be confirmed corresponding to the new value of the counter to be confirmed.

[0299] Next, the state in which the history information is stored in the history memory 117 will be described with reference to the time chart of FIG. 27. FIG. 27(a) shows the period during which a signal of HI level is input to any one of the first to seventh and eleventh buffers 122a to 122g and 122k, FIG. 27(b) shows the period during which a signal of HI level is input to the eighth buffer 122h, FIG. 27(c) shows the period during which a signal of HI level is input to the ninth buffer 122i, FIG. 27(d) shows the period during which a signal of HI level is input to the tenth buffer 122j, and FIG. 27(e) shows the writing timing of the history information to the history memory 117.

[0300] At the timing of t1, as shown in FIG. 27(a), the output state of the signal input to any one of the first to seventh and eleventh buffers 122a to 122g and 122k is switched from the LOW level to the HI level. Therefore, as shown in FIG. 27(e), the history information is written into the history memory 117 at the timing of t1. After that, at the timing of t2, as shown in FIG. 27(a), the signal switched to the HI level at the timing of t1 is switched to the LOW level. However, since the signal is a signal input to any one of the first to seventh and eleventh buffers 122a to 122g and 122k and the switching to the LOW level is not the target for storing the history information, the writing of the history information is not executed at the timing of t2 as shown in FIG. 27(e).

[0301] After that, at each of the timings of t3, t5, t6, t9, t10, t13, and t14, as shown in FIG. 27(a), the output state of the signal input to any of the first to seventh and eleventh buffers 122a to 122g, 122k is switched from the LOW level to the HI level. Therefore, history information is written as shown in FIG. 27(e) at each of these timings.

[0302] As shown in FIG. 27(b), from the timing of t4 to the timing of t7, the output state of the signal input to the eighth buffer 122h becomes the HI level. This eighth buffer 122h corresponds to the presence or absence of the occurrence of the opening / closing execution mode. Therefore, at the timing of t4 when the output state of the signal input to the eighth buffer 122h switches to the HI level and at the timing of t7 when the output state of the signal switches to the LOW level, both as shown in FIG. 27(e), history information is written. In this case, the history information written at the timing of t4 includes start information, and the history information written at the timing of t7 includes end information. Thereby, it becomes possible to grasp the execution period of the opening / closing execution mode by checking the history information in the history memory 117.

[0303] Also, the history information is written in the history memory 117 in the order of the passage of time. Therefore, it becomes possible to distinguish whether the history information indicating that a ball has entered any of the out port 24a, the general winning port 31, the special electric winning device 32, the first operation port 33, and the second operation port 34 is during the opening / closing execution mode. Also, since the history information includes RTC information, it is also possible to distinguish whether the history information indicating that a ball has entered any of the out port 24a, the general winning port 31, the special electric winning device 32, the first operation port 33, and the second operation port 34 is during the opening / closing execution mode by comparing the RTC information.

[0304] As shown in FIG. 27(c), the output state of the signal input to the ninth buffer 122i becomes the HI level from the timing of t8 to the timing of t11. This ninth buffer 122i corresponds to the presence or absence of the occurrence of the high-frequency support mode. Therefore, at the timing of t8, which is the timing when the output state of the signal input to the ninth buffer 122i switches to the HI level as shown in FIG. 27(e), and at the timing of t11, which is the timing when the output state of the signal switches to the LOW level, history information is written. In this case, the history information written at the timing of t8 includes start information, and the history information written at the timing of t11 includes end information. Thereby, it becomes possible to grasp the execution period of the high-frequency support mode by checking the history information in the history memory 117.

[0305] Also, the history information is written in the history memory 117 in the order of the passage of time. Therefore, it becomes possible to distinguish whether the history information indicating that a ball has entered any of the out port 24a, the general winning port 31, the special electric winning device 32, the first operating port 33, and the second operating port 34 is during the high-frequency support mode. Further, since the history information includes RTC information, it is also possible to distinguish whether the history information indicating that a ball has entered any of the out port 24a, the general winning port 31, the special electric winning device 32, the first operating port 33, and the second operating port 34 is during the high-frequency support mode by comparing the RTC information.

[0306] As shown in FIG. 27(d), from the timing of t12 to the timing of t15, the output state of the signal input to the tenth buffer 122j becomes the HI level. This tenth buffer 122j corresponds to the presence or absence of the opening of the front door frame 14. Therefore, as shown in FIG. 27(e), at the timing of t12 when the output state of the signal input to the tenth buffer 122j switches to the HI level, and at the timing of t15 when the output state of the signal switches to the LOW level, history information is written. In this case, the history information written at the timing of t12 includes start information, and the history information written at the timing of t15 includes end information. Thereby, by checking the history information in the history memory 117, it becomes possible to grasp the period during which the front door frame 14 is in the open state.

[0307] Also, the history information is written in the history memory 117 in the order of the passage of time. Therefore, it becomes possible to distinguish whether the history information indicating that a ball has entered any of the out port 24a, the general winning port 31, the special electric winning device 32, the first operating port 33, and the second operating port 34 is during the opening of the front door frame 14. Further, since the history information includes RTC information, by comparing the RTC information, it is also possible to distinguish whether the history information indicating that a ball has entered any of the out port 24a, the general winning port 31, the special electric winning device 32, the first operating port 33, and the second operating port 34 is during the opening of the front door frame 14.

[0308] Next, the output process of the set value update signal executed when the main CPU 63 sets the setting state of the pachinko machine 10 will be described. FIG. 28 is a flowchart showing the output process of the set value update signal executed by the main CPU 63. Note that the output process of the set value update signal is executed in step S119 in the main process (FIG. 9).

[0309] Set a value corresponding to the set value of the pachinko machine 10 currently set in the pulse number counter provided in the main-side RAM 65 (step S1201). Specifically, set the value of the set value counter in the main-side RAM 65 to the pulse number counter. Then, determine whether the set value update signal directed to the management-side CPU 112 is at the HI level (step S1202). As already described, the set value update signal is input to the 15th buffer 122o of the input port 121 in the management IC 66. Here, the output process of the set value update signal is executed at a timing earlier than the recognition process, which is a process for allowing the management-side CPU 112 to specify the types of signals input to the 1st to 14th buffers 122a to 122n of the input port 121 in the main process (Figure 9). On the other hand, since the set value update signal is input to the 15th buffer 122o being set in the management IC 66 at the design stage of the pachinko machine 10, even if the output process of the set value update signal is executed before the recognition process, it is possible for the management-side CPU 112 to identify that the signal input to the 15th buffer 122o is the set value update signal.

[0310] If a negative determination is made in step S1202, decrement the value of the LOW level counter provided in the main-side RAM 65 by 1 (step S1203), and determine whether the value of the LOW level counter after the decrement by 1 is "0" (step S1204). The LOW level counter is a counter for the main CPU 63 to identify whether the set value update signal has been maintained at the LOW level for a predetermined period while a plurality of pulses with the set value update signal at the HI level are output. When the value of the LOW level counter is "0" (step S1204: YES), it means that it is the timing to set the set value update signal to the HI level, so set the set value update signal to the HI level (step S1205).

[0311] After that, "20" is set to the HI-level counter provided in the main-side RAM 65 (step S1206). The HI-level counter is a counter for the main-side CPU 63 to specify the period during which the set value update signal is maintained at the HI level. Since the value set in the HI-level counter is decremented by 1 at a cycle of about 10 microseconds, the set value update signal is maintained at the HI level for 200 microseconds when one pulse is output. This period of maintaining the HI level is sufficient for the management-side CPU 112 to identify that the set value update signal has changed from the LOW level to the HI level.

[0312] When the set value update signal is at the HI level (step S1202: YES), the value of the HI-level counter in the main-side RAM 65 is decremented by 1 (step S1207), and it is determined whether the value of the HI-level counter after the decrement is "0" (step S1208). When the value of the HI-level counter is "0" (step S1208: YES), it means that it is time to set the set value update signal to the LOW level, so the set value update signal is set to the LOW level (step S1209).

[0313] After that, the value of the pulse count counter in the main-side RAM 65 is decremented by 1 (step S1210), and it is determined whether the value of the pulse count counter after the decrement is "0" (step S1211). When the value of the pulse count counter is not "0" (step S1211: NO), it means that the output of the pulse signal by the set value update signal corresponding to the set value of the pachinko machine 10 set this time is not completed, so "20" is set to the LOW-level counter in the main-side RAM 65 (step S1212). Since the value set in the LOW-level counter is decremented by 1 at a cycle of about 10 microseconds, it is maintained at the LOW level for 200 microseconds between multiple pulse outputs by the set value update signal. This period of maintaining the LOW level is sufficient for the management-side CPU 112 to identify that the set value update signal has changed from the HI level to the LOW level.

[0314] When the value of the pulse counter is "0" (step S1211: YES), it means that the output of the pulse signal by the set value update signal corresponding to the number of minutes corresponding to the set value of the pachinko machine 10 set this time has been completed. Therefore, the output process of the set value identification end command is executed (step S1213). The set value identification end command is a command for causing the management-side CPU 112 to recognize that the output of the set value update signal for causing the management-side CPU 112 to recognize the set value of the pachinko machine 10 set this time has been completed. When outputting the set value identification end command, the first to eighth signals input to the first to eighth buffers 122a to 122h are used in the same manner as the identification start command, the type identification command, and the identification end command. However, the signal pattern of the set value identification end command is different from that of the identification start command, the type identification command, and the identification end command.

[0315] As described above, in the output process of the set value update signal, a pulse signal by the set value update signal corresponding to the number of minutes corresponding to the value of the set value of the pachinko machine 10 set at the start of the supply of the operating power this time is output to the management IC 66. The management-side CPU 112 executes the set update recognition process to grasp the number of pulse signals by the set value update signal and based on that, grasps the set value of the pachinko machine 10 set this time.

[0316] FIG. 29 is a flowchart showing the set update recognition process executed by the management-side CPU 112. The set update recognition process is executed in step S902 of the management process (FIG. 23).

[0317] It is determined whether or not the setting value update signal input to the 15th buffer 122o of the input port 121 has switched from the LOW level to the HI level (step S1301). If an affirmative determination is made in step S1301, the value of the setting value grasping counter provided in the management side RAM 114 is set to "1" (step S1302). The setting value grasping counter is a counter for specifying the setting value of the pachinko machine 10 by the management side CPU 112. For example, if the value of the setting value grasping counter is "1", it means "setting 1", and if the value of the setting value grasping counter is "6", it means "setting 6".

[0318] Thereafter, it is determined whether or not the setting value update signal input to the 15th buffer 122o of the input port 121 has switched from the LOW level to the HI level again (step S1303). If an affirmative determination is made in step S1303, the value of the setting value grasping counter in the management side RAM 114 is incremented by 1 (step S1304). As a result, the setting value of the pachinko machine 10 specified by the management side CPU 112 is incremented by one step.

[0319] If a negative determination is made in step S1303, or if the process of step S1304 is executed, it is determined whether or not a setting value identification end command has been received from the main side CPU 63 based on the input states of the first to eighth signals input to the first to eighth buffers 122a to 122h of the input port 121 (step S1305). If a negative determination is made in step S1305, the process returns to step S1303.

[0320] If an affirmative determination is made in step S1305, RTC information, which is the date, month, year information and time information, is read from RTC115 (step S1306). Then, a writing process to the history memory 117 is executed (step S1307). In this writing process, by referring to the pointer area 126 of the history memory 117, the pointer information of the history area 124 that is currently the writing target is specified, and the RTC information read in step S1306 is written to the history information storage area 125 of the history area 124 corresponding to the pointer information that is the writing target. Also, both the information for identifying that it is a set value and the information of the value of the set value grasp counter are written to the history information storage area 125 corresponding to the pointer information that is the writing target. As a result, a combination of information indicating that the setting state of the pachinko machine 10 has been newly set, the RTC information corresponding to the date and time when the setting was made, and the information of the set value when the setting was made is stored as history information.

[0321] Thereafter, an update process for the target pointer is executed (step S1308). In this update process, the numerical information stored in the pointer area 126 of the history memory 117 is read and incremented by 1. It is determined whether the pointer information after the increment of 1 exceeds the maximum value of the pointer information in the history area 124. If it does not exceed the maximum value, the pointer information after the increment of 1 is overwritten to the pointer area 126 as the new writing target pointer information. If it exceeds the maximum value, the pointer area 126 is cleared to "0" so that the pointer information of the writing target becomes the first pointer information.

[0322] When the setting update recognition process is executed as described above, if the setting state of the pachinko machine 10 is newly set, the fact that the setting has been made, the date and time when the setting was made, and the combination of setting values when the setting was made are stored in the history area 124 as history information. Thus, by reading and analyzing the information stored in the history memory 117 using an external device connected to the reading terminal 68d, it becomes possible to grasp the date and time when the setting state of the pachinko machine 10 was newly set and the content of the setting values when the setting was made.

[0323] Here, even if the setting state of the pachinko machine 10 is newly set, the information stored in the history memory 117 is maintained as it is. As a result, it becomes possible to prevent the history information in the history memory 117 from being erased even if the setting state of the pachinko machine 10 is newly set, and various parameters described later are calculated using the history information existing across the timing before and after the change in the setting state of the pachinko machine 10. In this case, since the date and time when the setting state of the pachinko machine 10 was newly set is stored in the history memory 117 as described above, by connecting an external device to the reading terminal 68d and reading the information stored in the history memory 117, it becomes possible to calculate various parameters in the period after the timing when the setting state of the pachinko machine 10 was newly set and during which the setting state is maintained.

[0324] Next, the display output process executed by the management side CPU 112 will be described with reference to the flowchart of FIG. 30. Note that the display output process is executed in step S909 of the management process (FIG. 23).

[0325] First, it is determined whether it is the operation timing (step S1401). If 51 seconds have elapsed since the supply of operating power to the management-side CPU 112 was started, or if 51 seconds have elapsed since the affirmative determination was made in the previous step S1401, an affirmative determination is made in step S1401. If an affirmative determination is made in step S1401, various normal ball entry counts are calculated (step S1402). Specifically, first, the number of ball entry counts to the out port 24a is calculated by counting the number of history information storage areas 125 in the history area 124 of the history memory 117 where correspondence relationship information indicating that it is the out port 24a is stored. Also, the number of ball entry counts to the general winning port 31 is calculated by counting the number of history information storage areas 125 in the history area 124 of the history memory 117 where correspondence relationship information indicating that it is the general winning port 31 is stored. Also, the number of ball entry counts to the special electric winning device 32 is calculated by counting the number of history information storage areas 125 in the history area 124 of the history memory 117 where correspondence relationship information indicating that it is the special electric winning device 32 is stored. Also, the number of ball entry counts to the first operation port 33 is calculated by counting the number of history information storage areas 125 in the history area 124 of the history memory 117 where correspondence relationship information indicating that it is the first operation port 33 is stored. Also, the number of ball entry counts to the second operation port 34 is calculated by counting the number of history information storage areas 125 in the history area 124 of the history memory 117 where correspondence relationship information indicating that it is the second operation port 34 is stored.

[0326] Thereafter, by referring to the history information storage area 125 existing during the period between the history information storage area 125 in which the correspondence information indicating that it is the front door frame 14 and the start information are stored and the history information storage area 125 in which the correspondence information indicating that it is the front door frame 14 and the end information are stored in the history area 124 of the history memory 117, the number of balls entering each of the out ports 24a, general winning ports 31, special electric winning devices 32, first operating ports 33, and second operating ports 34 that occurred in the situation where the front door frame 14 is in the open state is calculated (step S1403). The period between the history information storage area 125 in which the correspondence information indicating that it is the front door frame 14 and the start information are stored and the history information storage area 125 in which the correspondence information indicating that it is the front door frame 14 and the end information are stored in the history area 124 of the history memory 117 is calculated from the RTC information stored in these history information storage areas 125. Also, in the whole of the pointer information with consecutive numbers, when there are a plurality of sections between the history information storage area 125 in which the correspondence information indicating that it is the front door frame 14 and the start information are stored and the history information storage area 125 in which the correspondence information indicating that it is the front door frame 14 and the end information are stored, the number of balls entering for each sum of those sections is calculated. Also, although there is a history information storage area 125 in which the correspondence information indicating that it is the front door frame 14 and the start information are stored, when the correspondence information indicating that it is the front door frame 14 and the end information are not stored in the history information storage area 125 storing the RTC information corresponding to the time after the history information storage area 125, all the history information in the history information storage area 125 storing the RTC information corresponding to the time after the history information storage area 125 in which the correspondence information indicating that it is the front door frame 14 and the start information are stored is treated as being in the state where the front door frame 14 is open.

[0327] After that, various parameters are calculated using the calculation results of step S1402 and step S1403 (step S1404). Specifically, first, the number of balls entering the front door frame 14 calculated in step S1403 is subtracted from each number of balls entering calculated in step S1402. Then, the following first to eighth parameters are calculated using the number of balls entering after the subtraction. The difference between the number of balls entering the outlet 24a calculated in step S1403 and the number of balls entering the outlet 24a calculated in step S1402 is defined as the number of balls entering K1, the difference between the number of balls entering the general winning port 31 calculated in step S1403 and the number of balls entering the general winning port 31 calculated in step S1402 is defined as the number of balls entering K2, the difference between the number of balls entering the special electric winning device 32 calculated in step S1403 and the number of balls entering the special electric winning device 32 calculated in step S1402 is defined as the number of balls entering K3, the difference between the number of balls entering the first operating port 33 calculated in step S1403 and the number of balls entering the first operating port 33 calculated in step S1402 is defined as the number of balls entering K4, and the difference between the number of balls entering the second operating port 34 calculated in step S1403 and the number of balls entering the second operating port 34 calculated in step S1402 is defined as the number of balls entering K5. · First parameter: The ratio of the total number of payout game balls (K2 × "number of prize balls for winning at the general winning port 31" + K3 × "number of prize balls for winning at the special electric winning device 32" + K4 × "number of prize balls for winning at the first operating port 33" + K5 × "number of prize balls for winning at the second operating port 34") to the total number of game balls discharged from the game area PA (K1 + K2 + K3 + K4 + K5) (hereinafter, this ratio is referred to as "D1") · Second parameter: The ratio of the total number of game balls entering the general winning port 31, K2, to the total number of game balls discharged from the game area PA (K1 + K2 + K3 + K4 + K5) · Third parameter: The ratio of the total number of game balls entering the special electric winning device 32, K3, to the total number of game balls discharged from the game area PA (K1 + K2 + K3 + K4 + K5) · Fourth parameter: The ratio of the total number of game balls entering the first operating port 33, K4, to the total number of game balls discharged from the game area PA (K1 + K2 + K3 + K4 + K5) (hereinafter, this ratio is referred to as "D2") · Fifth parameter: Ratio of the total number of game balls K5 entering the second operation port 34 to the total number of game balls (K1 + K2 + K3 + K4 + K5) discharged from the game area PA (hereinafter, this ratio is referred to as "D3") · Sixth parameter: D1 - (D2 × "number of prize balls for winning at the first operation port 33" + D3 × "number of prize balls for winning at the second operation port 34") · Seventh parameter: Ratio of (K3 × "number of prize balls for winning at the special electric winning device 32" + K5 × "number of prize balls for winning at the second operation port 34") to the total number of game balls paid out (K2 × "number of prize balls for winning at the general winning port 31" + K3 × "number of prize balls for winning at the special electric winning device 32" + K4 × "number of prize balls for winning at the first operation port 33" + K5 × "number of prize balls for winning at the second operation port 34") · Eighth parameter: Ratio of K3 × "number of prize balls for winning at the special electric winning device 32" to the total number of game balls paid out (K2 × "number of prize balls for winning at the general winning port 31" + K3 × "number of prize balls for winning at the special electric winning device 32" + K4 × "number of prize balls for winning at the first operation port 33" + K5 × "number of prize balls for winning at the second operation port 34") In step S1404, the above first to eighth parameters, which are the calculation results, are stored in the normal-time storage area in the calculation result memory 131. The above first to eighth parameters stored in the normal-time storage area are retained until the next step S1404 is executed. That is, when the next step S1404 is executed and the above first to eighth parameters are calculated, the newly calculated above first to eighth parameters are stored in the normal-time storage area, overwriting the calculation results of the previous first to eighth parameters that were stored in the normal-time storage area until then.

[0328] After that, by referring to the history information storage area 125 existing during the period between the history information storage area 125 in which the correspondence information indicating the open / close execution mode and the start information are stored in the history area 124 of the history memory 117, and the history information storage area 125 in which the correspondence information indicating the open / close execution mode and the end information are stored, the number of balls entering each of the out port 24a, the general winning port 31, the special electric winning device 32, the first operation port 33, and the second operation port 34 that occurred in the open / close execution mode is calculated (step S1405). The period between the history information storage area 125 in which the correspondence information indicating the open / close execution mode and the start information are stored in the history area 124 of the history memory 117, and the history information storage area 125 in which the correspondence information indicating the open / close execution mode and the end information are stored, is calculated from the RTC information stored in these history information storage areas 125. Also, in the whole of the pointer information with consecutive numbers, when there are a plurality of sections between the history information storage area 125 in which the correspondence information indicating the open / close execution mode and the start information are stored, and the history information storage area 125 in which the correspondence information indicating the open / close execution mode and the end information are stored, the number of balls entering for each total of those sections is calculated. Further, although the history information storage area 125 in which the correspondence information indicating the open / close execution mode and the start information are stored exists, when the correspondence information indicating the open / close execution mode and the end information are not stored in the history information storage area 125 corresponding to the time after the history information storage area 125, all the history information in the history information storage area 125 corresponding to the time after the history information storage area 125 in which the correspondence information indicating the open / close execution mode and the start information are stored is treated as being in the open / close execution mode.

[0329] Thereafter, among the periods in the opening / closing execution mode specified in step S1405, the number of game balls entering each of the out ports 24a, general winning ports 31, special winning devices 32, first operation ports 33, and second operation ports 34 that occurred in the situation where the front door frame 14 was in the open state is calculated (step S1406). The method for calculating these numbers of game balls entering is the same as in the case of step S1403, except that it is based on the period in the opening / closing execution mode specified in step S1405.

[0330] Thereafter, various parameters are calculated using the calculation results of steps S1405 and S1406 (step S1407). Specifically, first, the number of game balls entering during the opening of the front door frame 14 calculated in step S1406 is subtracted from each number of game balls entering calculated in step S1405. Then, the following 11th to 18th parameters are calculated using the number of game balls entering after the subtraction. The difference between the number of game balls entering the out port 24a calculated in step S1406 and the number of game balls entering the out port 24a calculated in step S1405 is defined as the number of game balls K11, the difference between the number of game balls entering the general winning port 31 calculated in step S1406 and the number of game balls entering the general winning port 31 calculated in step S1405 is defined as the number of game balls K12, the difference between the number of game balls entering the special winning device 32 calculated in step S1406 and the number of game balls entering the special winning device 32 calculated in step S1405 is defined as the number of game balls K13, the difference between the number of game balls entering the first operation port 33 calculated in step S1406 and the number of game balls entering the first operation port 33 calculated in step S1405 is defined as the number of game balls K14, and the difference between the number of game balls entering the second operation port 34 calculated in step S1406 and the number of game balls entering the second operation port 34 calculated in step S1405 is defined as the number of game balls K15. · 11th parameter: The ratio of the total number of payout game balls (K12 × "number of bonus balls for winning at the general winning port 31" + K13 × "number of bonus balls for winning at the special winning device 32" + K14 × "number of bonus balls for winning at the first operation port 33" + K15 × "number of bonus balls for winning at the second operation port 34") to the total number of game balls discharged from the game area PA (K11 + K12 + K13 + K14 + K15) (hereinafter, this ratio is referred to as "D11") · 12th parameter: Ratio of the total number of game balls K12 entering the general winning opening 31 to the total number of game balls (K11 + K12 + K13 + K14 + K15) discharged from the game area PA · 13th parameter: Ratio of the total number of game balls K13 entering the special electric winning device 32 to the total number of game balls (K11 + K12 + K13 + K14 + K15) discharged from the game area PA · 14th parameter: Ratio of the total number of game balls K14 entering the first operation opening 33 to the total number of game balls (K11 + K12 + K13 + K14 + K15) discharged from the game area PA (hereinafter, this ratio is referred to as "D12") · 15th parameter: Ratio of the total number of game balls K15 entering the second operation opening 34 to the total number of game balls (K11 + K12 + K13 + K14 + K15) discharged from the game area PA (hereinafter, this ratio is referred to as "D13") · 16th parameter: D11 - (D12 × "Number of prize balls for winning at the first operation opening 33" + D13 × "Number of prize balls for winning at the second operation opening 34") · 17th parameter: Ratio of (K13 × "Number of prize balls for winning at the special electric winning device 32" + K15 × "Number of prize balls for winning at the second operation opening 34") to the total number of game balls paid out (K12 × "Number of prize balls for winning at the general winning opening 31" + K13 × "Number of prize balls for winning at the special electric winning device 32" + K14 × "Number of prize balls for winning at the first operation opening 33" + K15 × "Number of prize balls for winning at the second operation opening 34") · 18th parameter: Ratio of K13 × "Number of prize balls for winning at the special electric winning device 32" to the total number of game balls paid out (K12 × "Number of prize balls for winning at the general winning opening 31" + K13 × "Number of prize balls for winning at the special electric winning device 32" + K14 × "Number of prize balls for winning at the first operation opening 33" + K15 × "Number of prize balls for winning at the second operation opening 34") In step S1407, the 11th to 18th parameters, which are the calculation results, are stored in the storage area for the open / close execution mode in the calculation result memory 131. The 11th to 18th parameters stored in the storage area for the open / close execution mode are retained until the next step S1407 is executed. That is, when the next step S1407 is executed and the 11th to 18th parameters are calculated, the newly calculated 11th to 18th parameters are stored in the storage area for the open / close execution mode, thereby overwriting the calculation results of the previous 11th to 18th parameters that were stored in the storage area for the open / close execution mode until then.

[0331] Thereafter, by referring to the history information storage area 125 existing during the period between the history information storage area 125 in which the correspondence information and start information indicating the high-frequency support mode are stored and the history information storage area 125 in which the correspondence information and end information indicating the high-frequency support mode are stored in the history area 124 of the history memory 117, the number of balls entering each of the out-port 24a, general winning port 31, special electric winning device 32, first operation port 33, and second operation port 34 that occurred in the situation of the high-frequency support mode is calculated (step S1408). The period between the history information storage area 125 in which the correspondence information and start information indicating the high-frequency support mode are stored and the history information storage area 125 in which the correspondence information and end information indicating the high-frequency support mode are stored in the history area 124 of the history memory 117 is calculated from the RTC information stored in these history information storage areas 125. Also, in the whole of the serial pointer information, when there are a plurality of sections between the history information storage area 125 in which the correspondence information and start information indicating the high-frequency support mode are stored and the history information storage area 125 in which the correspondence information and end information indicating the high-frequency support mode are stored, the number of balls entering for each total of those sections is calculated. Further, although the history information storage area 125 in which the correspondence information and start information indicating the high-frequency support mode are stored exists, when the correspondence information and end information indicating the high-frequency support mode are not stored in the history information storage area 125 storing the RTC information corresponding to the time after the history information storage area 125, all of the history information in the history information storage area 125 storing the RTC information corresponding to the time after the history information storage area 125 in which the correspondence information and start information indicating the high-frequency support mode are stored is treated as being in the high-frequency support mode.

[0332] After that, among the periods in the high-frequency support mode identified in step S1408, the number of game balls entering each of the out port 24a, the general winning port 31, the special electric winning device 32, the first operation port 33, and the second operation port 34 that occurred in the situation where the front door frame 14 was in the open state is calculated (step S1409). The method of calculating these numbers of game balls entering is the same as in the case of step S1403, except that it is premised on the period in the high-frequency support mode identified in step S1408.

[0333] After that, various parameters are calculated using the calculation results of steps S1408 and S1409 (step S1410). Specifically, first, from each number of game balls entering calculated in step S1408, the number of game balls entering calculated in step S1409 that occurred while the front door frame 14 was open is subtracted. Then, the following 21st to 26th parameters are calculated using the number of game balls entering after the subtraction. Note that the difference between the number of game balls entering the out port 24a calculated in step S1408 and the number of game balls entering the out port 24a calculated in step S1409 is defined as the number of game balls entering K21, the difference between the number of game balls entering the general winning port 31 calculated in step S1408 and the number of game balls entering the general winning port 31 calculated in step S1409 is defined as the number of game balls entering K22, the difference between the number of game balls entering the special electric winning device 32 calculated in step S1408 and the number of game balls entering the special electric winning device 32 calculated in step S1409 is defined as the number of game balls entering K23, the difference between the number of game balls entering the first operation port 33 calculated in step S1408 and the number of game balls entering the first operation port 33 calculated in step S1409 is defined as the number of game balls entering K24, and the difference between the number of game balls entering the second operation port 34 calculated in step S1408 and the number of game balls entering the second operation port 34 calculated in step S1409 is defined as the number of game balls entering K25. · 21st parameter: The ratio of the total number of game balls paid out ((K22 × "number of prize balls for winning at the general winning port 31" + K23 × "number of prize balls for winning at the special electric winning device 32" + K24 × "number of prize balls for winning at the first operation port 33" + K25 × "number of prize balls for winning at the second operation port 34")) to the total number of game balls discharged from the game area PA (K21 + K22 + K23 + K24 + K25) (hereinafter, this ratio is referred to as "D11") · 22nd parameter: Ratio of the total number of game balls K22 entering the general winning opening 31 to the total number of game balls (K21 + K22 + K23 + K24 + K25) discharged from the game area PA · 23rd parameter: Ratio of the total number of game balls K23 entering the special winning device 32 to the total number of game balls (K21 + K22 + K23 + K24 + K25) discharged from the game area PA · 24th parameter: Ratio of the total number of game balls K24 entering the first operation opening 33 to the total number of game balls (K21 + K22 + K23 + K24 + K25) discharged from the game area PA (hereinafter, this ratio is referred to as "D22") · 25th parameter: Ratio of the total number of game balls K25 entering the second operation opening 34 to the total number of game balls (K21 + K22 + K23 + K24 + K25) discharged from the game area PA (hereinafter, this ratio is referred to as "D23") · 26th parameter: D21 - (D22 × "number of prize balls for winning at the first operation opening 33" + D23 × "number of prize balls for winning at the second operation opening 34") In step S1410, the 21st to 26th parameters, which are the calculation results, are stored in the storage area for the high-frequency support mode in the calculation result memory 131. The 21st to 26th parameters stored in the storage area for the high-frequency support mode are stored and retained until the next step S1410 is executed. That is, when the next step S1410 is executed and the 21st to 26th parameters are calculated, the newly calculated 21st to 26th parameters are stored in the storage area for the high-frequency support mode, overwriting the previous calculation results of the 21st to 26th parameters that were stored in the storage area for the high-frequency support mode until then.

[0334] After that, the occurrence frequency of the opening / closing execution mode is calculated and stored (step S1411). Specifically, the number of history information storage areas 125 in which the correspondence information and start information indicating that it is the opening / closing execution mode are stored in the history area 124 of the history memory 117 is counted to calculate the number of occurrences of the opening / closing execution mode. Also, the number of history information storage areas 125 in which the correspondence information indicating the start of a game round is stored in the history area 124 of the history memory 117 is counted to calculate the number of occurrences of the game round. Then, the number of occurrences of the opening / closing execution mode per unit game round is calculated. Note that the number of occurrences of the opening / closing execution mode is defined as the occurrence number K31, and the number of occurrences of the game round is defined as the occurrence number K32. · 31st parameter: K31 / K32 In step S1411, the 31st parameter, which is the calculation result, is stored in the storage area for the opening / closing execution mode frequency in the calculation result memory 131. The 31st parameter stored in the storage area for the opening / closing execution mode frequency is retained until the next step S1411 is executed. That is, when the next step S1411 is executed and the 31st parameter is calculated, the newly calculated 31st parameter is stored in the storage area for the opening / closing execution mode frequency, thereby overwriting the calculation result of the previous 31st parameter stored in the storage area for the opening / closing execution mode frequency until then.

[0335] After that, the occurrence frequency of the high-frequency support mode is calculated and stored (step S1412). Specifically, the number of history information storage areas 125 in which the correspondence information and start information indicating that it is the high-frequency support mode are stored in the history area 124 of the history memory 117 is counted to calculate the number of occurrences of the high-frequency support mode. Also, the number of occurrences of the game rounds is calculated by counting the number of history information storage areas 125 in which the correspondence information indicating the start of the game rounds is stored in the history area 124 of the history memory 117. Then, the number of occurrences of the high-frequency support mode per unit game round and the ratio of the number of occurrences of the high-frequency support mode to the number of occurrences of the opening / closing execution mode are calculated. Note that the number of occurrences of the high-frequency support mode is the occurrence number K41, the number of occurrences of the game rounds is the occurrence number K42, and the number of occurrences of the opening / closing execution mode calculated in step S1411 is the occurrence number K43. · Parameter 41: K41 / K42 · Parameter 42: K41 / K43 In step S1412, the above-mentioned Parameter 41 to Parameter 42, which are the calculation results, are stored in the high-frequency support mode frequency storage area in the calculation result memory 131. The above-mentioned Parameter 41 to Parameter 42 stored in the high-frequency support mode frequency storage area are stored and held until the next step S1412 is executed. That is, when the next step S1412 is executed and the above-mentioned Parameter 41 to Parameter 42 are calculated, the newly calculated above-mentioned Parameter 41 to Parameter 42 are stored in the high-frequency support mode frequency storage area, so that the calculation results of the previous Parameter 41 to Parameter 42 stored in the high-frequency support mode frequency storage area until then are overwritten.

[0336] When a negative determination is made in step S1401, or when the process of step S1412 is executed, display processing is executed (step S1413). FIG. 31 is a flowchart showing the display processing.

[0337] First, decrement the value of the update timing counter provided in the management-side RAM 114 by 1 (step S1501). The update timing counter is a counter for the management-side CPU 112 to identify the timing for updating the display content of the game history management results in the first to third notification display devices 69a to 69c. The management-side CPU 112 controls the display of the first to third notification display devices 69a to 69c to notify the calculation results of the above first to eighth parameters, the above eleventh to eighteenth parameters, the above twenty-first to twenty-sixth parameters, the above thirty-first parameter, and the above forty-first to forty-second parameters. In this case, in the first notification display device 69a, information corresponding to the type of parameter to be notified is displayed. Also, among the values obtained by multiplying the parameter to be notified by 100, the digit corresponding to the tens place is displayed on the second notification display device 69b, and the digit corresponding to the units place is displayed on the third notification display device 69c. And in the first to third notification display devices 69a to 69c, the displays corresponding to the calculation results of the above first to eighth parameters, the above eleventh to eighteenth parameters, the above twenty-first to twenty-sixth parameters, the above thirty-first parameter, and the above forty-first to forty-second parameters are sequentially switched according to a predetermined order. After the calculation result of the forty-second parameter, which is the display target in the last order, is displayed, the calculation result of the first parameter, which is the display target in the first order, is displayed. In this case, the period during which the calculation result of one parameter is continuously displayed is 2 seconds.

[0338] Here, the calculation cycle of the above various parameters in the management-side CPU 112 is 51 seconds. On the other hand, the number of various parameters is 25, and the period during which the calculation result of one parameter is continuously displayed is 2 seconds. Therefore, the various parameters calculated by the management-side CPU 112 will be the display targets in the first to third notification display devices 69a to 69c at least once.

[0339] When the process of step S1501 is executed, it is determined whether the value of the update timing counter after the 1-subtraction is "0" to determine whether it is the timing to update the display contents of the first to third notification display devices 69a to 69c (step S1502). If an affirmative determination is made in step S1502, the value of the display target counter provided in the management-side RAM 114 is incremented by 1 (step S1503). Then, when the value of the display target counter after the 1-increment exceeds the maximum value of "24" (step S1504: YES), the value of the display target counter is cleared to "0" (step S1505).

[0340] The display target counter is a counter for the management-side CPU 112 to specify the types of parameters to be displayed on the first to third notification display devices 69a to 69c. The above first to eighth parameters, the above eleventh to eighteenth parameters, the above twenty-first to twenty-sixth parameters, the above thirty-first parameter, and the above forty-first to forty-second parameters correspond one-to-one with the possible values of the display target counter from "0" to "24". For example, when the value of the display target counter is "0", the first parameter, which is the first display target, becomes the display target of the first to third notification display devices 69a to 69c. When the value of the display target counter is "24", the forty-second parameter, which is the last display target, becomes the display target of the first to third notification display devices 69a to 69c.

[0341] If a negative determination is made in step S1504, or if the process of step S1505 is executed, the first notification display device 69a is controlled for display so that information corresponding to the type of parameter corresponding to the value of the display target counter is displayed (step S1506). Further, the parameter corresponding to the value of the display target counter is read from the operation result memory 131, the read parameter is multiplied by 100, and the digit corresponding to the tens place is displayed on the second notification display device 69b, and the digit corresponding to the units place is displayed on the third notification display device 69c (step S1507). The content displayed on the first to third notification display devices 69a to 69c by steps S1506 and S1507 continues until the next update timing or until the supply of operating power to the management side CPU 112 is stopped. Thereafter, a value corresponding to 2 seconds is set as the value corresponding to the next update timing in the update timing counter of the management side RAM 114 (step S1508).

[0342] As described above, when the supply of operating power to the management side CPU 112 is started by executing the display process, the management result of the game history is displayed on the first to third notification display devices 69a to 69c. The display of the management result of the game history is performed regardless of whether the game is continuing or not, and regardless of whether the game machine main body 12 is opened with respect to the outer frame 11 and the main control device 60 is visible from the front of the pachinko machine 10. By controlling the display of the first to third notification display devices 69a to 69c in this way regardless of the game situation and the state of the pachinko machine 10, it becomes possible to simplify the processing configuration for controlling the display of the first to third notification display devices 69a to 69c.

[0343] The display of the management results of the game history in the first to third notification display devices 69a to 69c is started after the supply of operating power to the management-side CPU 112 is started and after the identification end command is received from the main-side CPU 63. In this case, the information stored in the operation result memory 131 is stored and retained even when the supply of operating power to the pachinko machine 10 is stopped, similar to the information stored in the history memory 117. Therefore, when the supply of operating power to the management-side CPU 112 is started, the management results of the game history calculated before the supply of operating power to the management-side CPU 112 is stopped are displayed.

[0344] When the settings of the pachinko machine 10 are set when the supply of operating power to the main-side CPU 63 is started, the information corresponding to the setting value during the change is displayed on the third notification display device 69c. The display of the information corresponding to the setting value is performed before the identification end command is transmitted from the main-side CPU 63, while the display of the management results of the game history in the first to third notification display devices 69a to 69c is started after the identification end command is transmitted from the main-side CPU 63. Thus, even in a configuration where the third notification display device 69c is used as a display device for both displaying the information corresponding to the setting value and the management results of the game history, it is possible to prevent the display periods of these displays from overlapping.

[0345] Also, when the information corresponding to the setting value is displayed, the first notification display device 69a and the second notification display device 69b are made non-display. On the other hand, when the management results of the game history are being displayed, the first notification display device 69a and the second notification display device 69b are not made non-display. This makes it possible to identify which of the display of the information corresponding to the setting value and the display of the management results of the game history is being performed on the third notification display device 69c.

[0346] Next, a processing configuration for outputting the history information stored in the history memory 117 and various parameters stored in the calculation result memory 131 to an external device electrically connected to the reading terminal 68d of the MPU62 will be described. FIG. 32(a) is a flowchart showing the data output processing executed by the main CPU 63. Note that the data output processing is executed in step S112 in the main processing (FIG. 9).

[0347] In the data output processing, first, it is determined whether a connection signal indicating that an external device is electrically connected to the reading terminal 68d is received from the reading terminal 68d (step S1601). If a negative determination is made in step S1601, this data output processing is terminated as it is. In this case, in order to execute the data output processing, it is necessary to restart the supply of operating power to the main CPU 63. Thus, in order to enable the external output of the history information and various parameters, it is necessary to start the supply of operating power to the main CPU 63 with the external device electrically connected to the reading terminal 68d. Since the power switch for performing the stop operation and start operation of the supply of operating power to the main CPU 63 is provided in the payout mechanism unit 73 mounted on the back surface of the back pack unit 15, in order to perform these stop operation and start operation, it is necessary to open the gaming machine body 12 with respect to the outer frame 11 and expose the back surface of the back pack unit 15. In such circumstances, by adopting a configuration in which it is necessary to start the supply of operating power to the main CPU 63 with the external device electrically connected to the reading terminal 68d in order to enable the external output of the history information and various parameters, even if a person other than the administrator of the game hall tries to read the history information and various parameters, it can be made difficult to do so.

[0348] When an affirmative determination is made in step S1601, it is determined whether a signal for control information confirmation is being received from the reading terminal 68d, thereby determining whether the current connection of the external device to the reading terminal 68d corresponds to the confirmation of the control information (program and data) of the main ROM 64 (step S1602). The external device is configured to be able to perform both the confirmation of control information and the confirmation of history information and various parameters. When the confirmation of control information is selected by a manual operation on the external device, a signal for control information confirmation is transmitted from the external device. When the confirmation of history information and various parameters is selected by a manual operation on the external device, a signal for history confirmation is transmitted from the external device. Note that it is not limited to this, and a configuration in which the external device for control information confirmation and the external device for history confirmation are separate may also be used. In this case, when the external device for control information confirmation is electrically connected to the reading terminal 68d, a signal for control information confirmation is transmitted from the external device. When the external device for history confirmation is electrically connected to the reading terminal 68d, a signal for history confirmation is transmitted from the external device.

[0349] When an affirmative determination is made in step S1602, output processing for control information confirmation is executed (step S1603). In the output processing, the program and data are read as control information from the main ROM 64, and the read control information is output to the reading terminal 68d. As a result, it becomes possible to read the control information in the external device electrically connected to the reading terminal 68d, and it becomes possible to confirm whether the control information is regular or normal.

[0350] When a negative determination is made in step S1602, an output instruction signal is sent to the management-side CPU 112 (step S1604). Specifically, the output state of the output instruction signal is switched from the LOW level to the HI level. This HI-level output state is continued for a specific period. This specific period is long enough for the management-side CPU 112 to identify that the HI-level output instruction signal has been input to the 16th buffer 122p. When the output state of the output instruction signal is switched to the HI level, a process for outputting history information is executed in the management-side CPU 112.

[0351] Specifically, as shown in the flowchart of FIG. 32(b), when the output state of the output instruction signal input to the 16th buffer 122p of the input port 121 is switched from the LOW level to the HI level (step S1701: YES), the management-side CPU 112 reads out the history information stored in the history memory 117 and various parameters stored in the calculation result memory...

Claims

【Claim 1】 Game value imparting means that is electrically connected to predetermined detection means and executes a process for imparting a game value to a game; Process execution means that is electrically connected to the game value imparting means and executes a predetermined process; In a gaming machine comprising: The game value imparting means includes: First reference information storage means for storing reference information which is information used in the process for imparting the game value and which is referred to in relation to detection by the predetermined detection means; First transmission means for transmitting a reference information signal corresponding to the reference information stored in the first reference information storage means to the process execution means after a predetermined supply of power to the gaming machine has started and before execution of a predetermined process for advancing the game is started; Second transmission means for transmitting a predetermined information signal based on information acquired based on detection by the predetermined detection means to the process execution means; Means for transmitting a predetermined transition signal to the process execution means when the game state has shifted to a predetermined game state in a situation where a game is being played; Means for executing a process for causing a predetermined signal to be externally output to the outside of the gaming machine when the game state has shifted to the predetermined game state in a situation where a game is being played; Means for executing a predetermined determination process for determining whether a predetermined storage area is normal after a predetermined supply of power to the gaming machine has started and before execution of the predetermined process is started; Comprising: When it is determined in the predetermined determination process that the predetermined storage area is not normal, a process corresponding thereto is executed; When it is determined in the predetermined determination process that the predetermined storage area is normal, transmission of the reference information signal by the first transmission means is then executed; The process execution means includes: Second reference information storage means for storing reference information corresponding to the reference information signal transmitted from the game value imparting means; Execution means for executing the predetermined process based on the predetermined information signal transmitted from the second transmission means and the reference information stored in the second reference information storage means; Process result information storage means for storing information regarding a process result of the predetermined process by the execution means; Means for storing information corresponding thereto when the predetermined transition signal is received; a means for erasing the processing result information stored in the processing result information storage means when a predetermined event occurs based on the performance of a predetermined operation; Equipped with The game value providing means is a main control means for controlling the progress of a game, The process execution means is a performance control means for controlling the execution of a performance, The reference information signal is transmitted from the game value providing means even in a situation where a predetermined event that stops control of game progress occurs, When a predetermined event occurs that stops control of game progress, the predetermined control for transmitting the predetermined information signal by the second transmitting means is not executed, The predetermined process is a process different from the provision of value used for playing a game.

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