multiplexer

Abstract

To improve an attenuation characteristic in a non-passage band including a high-frequency band while improving a loss against a signal in a passage band.SOLUTION: In a multiplexer 7B, a first inductor via VH1, a second inductor via VH2, and a third inductor via VH3 form a first inductor LH1, a second inductor LH2, and a third inductor LH3, respectively. A fourth inductor via VH4 forms a fourth inductor LH4. A fifth inductor via VH5 forms a fifth inductor LH5. A sixth inductor via VH6 forms a sixth inductor LH6. At least one of the fourth inductor via VH4, the fifth inductor via VH5, and the sixth inductor via VH6 is arranged in a boundary region 74 of a first filter 71B and a second filter 72B.SELECTED DRAWING: Figure 22

Description

Technical Field

[0001] The present invention generally relates to a multiplexer.

Background Art

[0002] Patent Document 1 describes an LC filter. The LC filter described in Patent Document 1 includes a laminate, a first electrode and a second electrode in a flat plate shape, and a first capacitor electrode, a second capacitor electrode, and a third capacitor electrode. The laminate is formed by laminating a plurality of dielectric layers. The first capacitor electrode, the second capacitor electrode, and the third capacitor electrode form a capacitor with the second electrode. The LC filter described in Patent Document 1 further includes capacitor electrodes facing the first capacitor electrode and the third capacitor electrode.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] By the way, in the conventional LC filter described in Patent Document 1, since capacitor electrodes facing the first capacitor electrode and the third capacitor electrode are provided, there are cases where a sufficient attenuation amount in the high frequency band cannot be obtained.

[0005] The present invention has been made in view of the above points, and an object of the present invention is to provide a multiplexer that can improve the loss with respect to signals in the passband and improve the attenuation characteristics in the stopband including the high frequency band.

Means for Solving the Problems

[0006] The LC filter according to one aspect of the present invention includes a laminate, a first input / output port, a second input / output port, a first electrode, a second electrode, a first capacitor electrode, a second capacitor electrode, a third capacitor electrode, a first inductor via, a second inductor via, a third inductor via, and a first inductor pattern portion. The laminate has a plurality of dielectric layers laminated thereon. The first input / output port is provided on the laminate. The second input / output port is provided on the laminate and is different from the first input / output port. The first electrode is a flat electrode provided on a first dielectric layer among the plurality of dielectric layers. The second electrode is a flat electrode provided on a second dielectric layer different from the first dielectric layer among the plurality of dielectric layers. The first capacitor electrode forms a first capacitor with the second electrode. The second capacitor electrode forms a second capacitor with the second electrode. The third capacitor electrode forms a third capacitor with the second electrode. The first inductor via has a first end connected to the first capacitor electrode and a second end connected to the first electrode, forming a first inductor. The second inductor via has a third end connected to the second capacitor electrode and a fourth end connected to the first electrode, forming a second inductor. The third inductor via has a fifth end connected to the third capacitor electrode and a sixth end connected to the first electrode, forming a third inductor. The first inductor pattern portion forms a fourth inductor. The first capacitor electrode and the second capacitor electrode form a fourth capacitor. The second capacitor electrode and the third capacitor electrode form a fifth capacitor. The first inductor pattern portion has a first end connected to at least one of the first electrode, the first inductor via, and the first capacitor electrode, and a second end connected to the first input / output port. The first capacitor electrode and the third capacitor electrode do not face each other.

[0007] The multiplexer according to one aspect of the present invention includes a first filter including the LC filter and a second filter. The second filter passes a signal in a frequency band higher than the passband of the first filter.

[0008] The high-frequency module according to one aspect of the present invention includes a filter including the LC filter and an amplifier.

[0009] The communication device according to one aspect of the present invention includes the high-frequency module and a signal processing circuit.

[0010] The multiplexer according to one aspect of the present invention includes a first filter, a second filter, and a laminate. The first filter is a low-pass filter. The second filter passes a signal in a frequency band higher than the pass band of the first filter. The laminate has a plurality of dielectric layers laminated thereon. The first filter includes a first electrode, a second electrode, a first capacitor electrode, a second capacitor electrode, a third capacitor electrode, a first inductor via, a second inductor via, a third inductor via, and a first inductor pattern portion. The first electrode is provided on a first dielectric layer among the plurality of dielectric layers. The second electrode is provided on a second dielectric layer different from the first dielectric layer among the plurality of dielectric layers and is a ground electrode. The first capacitor electrode forms a first capacitor with the second electrode. The second capacitor electrode forms a second capacitor with the second electrode. The third capacitor electrode forms a third capacitor with the second electrode. The first inductor via has a first end connected to the first capacitor electrode and a second end connected to the first electrode, forming a first inductor. The second inductor via has a third end connected to the second capacitor electrode and a fourth end connected to the first electrode, forming a second inductor. The third inductor via has a fifth end connected to the third capacitor electrode and a sixth end connected to the first electrode, forming a third inductor. The first inductor pattern portion forms a fourth inductor. The second filter has a first electrode for the second filter, a second electrode for the second filter, a first capacitor electrode for the second filter, a second capacitor electrode for the second filter, a third capacitor electrode for the second filter, a first inductor via for the second filter, a second inductor via for the second filter, a third inductor via for the second filter, a fourth inductor via for the second filter, a fifth inductor via for the second filter, and a sixth inductor via for the second filter. The first electrode for the second filter is provided on the first dielectric layer among the plurality of dielectric layers. The second electrode for the second filter is provided on a second dielectric layer different from the first dielectric layer among the plurality of dielectric layers and is a ground electrode.The first capacitor electrode for the second filter forms a first capacitor for the second filter with the second electrode for the second filter. The second capacitor electrode for the second filter forms a second capacitor for the second filter with the second electrode for the second filter. The third capacitor electrode for the second filter forms a third capacitor for the second filter with the second electrode for the second filter. The first inductor via for the second filter is connected between the first capacitor electrode for the second filter and the first electrode for the second filter, and forms a first inductor for the second filter. The second inductor via for the second filter is connected between the second capacitor electrode for the second filter and the first electrode for the second filter, and forms a second inductor for the second filter. The third inductor via for the second filter is connected between the third capacitor electrode for the second filter and the first electrode for the second filter, and forms a third inductor for the second filter. The fourth inductor via for the second filter is connected between the first electrode for the second filter and the second electrode for the second filter, and forms a fourth inductor for the second filter that is connected in series with the first inductor for the second filter. The fifth inductor via for the second filter is connected between the first electrode for the second filter and the second electrode for the second filter, and forms a fifth inductor for the second filter that is connected in series with the second inductor for the second filter. The sixth inductor via for the second filter is connected between the first electrode for the second filter and the second electrode for the second filter, and forms a sixth inductor for the second filter that is connected in series with the third inductor for the second filter. At least one of the fourth inductor via for the second filter, the fifth inductor via for the second filter, and the sixth inductor via for the second filter is disposed in the boundary region between the first filter and the second filter.

Advantages of the Invention

[0011] According to the LC filter, multiplexer, high-frequency module, and communication device according to the above aspect of the present invention, it is possible to improve the loss for signals in the passband and improve the attenuation characteristics in the stopband including the high-frequency band.

Brief Description of the Drawings

[0012]

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Mode for Carrying Out the Invention

[0013] Hereinafter, the LC filter according to Embodiments 1 to 4, the multiplexer according to Embodiments 5, 7 to 12, and the high-frequency module and the communication device according to Embodiment 6 will be described with reference to the drawings. The drawings referred to in the following embodiments and the like are schematic diagrams, and the ratios of the sizes and thicknesses of the respective components in the drawings do not necessarily reflect the actual dimensional ratios.

[0014] In the following description, the stacking direction of the stacked body 2 (the stacking direction of the plurality of dielectric layers in the stacked body 2) is defined as the "first direction D1", the direction orthogonal to the first direction D1 and along one side of the stacked body 2 is defined as the "second direction D2", and the direction along the other side of the stacked body 2 is defined as the "third direction D3".

[0015] Note that in FIGS. 1 to 3, FIGS. 6 to 8, FIGS. 10 to 12, FIGS. 15 to 17, FIGS. 22 to 24, FIGS. 26, 27, 29, and 30, the dielectric layers of the stacked body 2 are omitted, and only the wiring pattern portions, vias, and conductors of the terminals formed inside the dielectric layers are shown.

[0016] (Embodiment 1) (1) Overall Structure of LC Filter The structure of the LC filter 1 according to Embodiment 1 will be described with reference to the drawings. The LC filter 1 according to Embodiment 1 is a low-pass filter that passes signals in a frequency band lower than a specific frequency.

[0017] (2) Each Component of LC Filter Hereinafter, each component of the LC filter 1 according to Embodiment 1 will be described with reference to the drawings.

[0018] As shown in FIGS. 1 to 3, the LC filter 1 includes a stacked body 2, a plurality of terminals 3, a first electrode P1, a second electrode P2, a plurality of capacitor electrodes PC0, and a plurality of inductor vias V0.

[0019] (2.1) Stacked Body As shown in FIGS. 1 to 3, the laminate 2 is a rectangular parallelepiped or a substantially rectangular parallelepiped, and is formed by laminating a plurality of dielectric layers (not shown) in the lamination direction. That is, the laminate 2 is a structure in which a plurality of dielectric layers are laminated. Each of the plurality of dielectric layers of the laminate 2 is formed of, for example, ceramic. Inside the laminate 2, an inductor and a capacitor are formed by a plurality of wiring pattern portions, a plurality of electrodes, and a plurality of vias (via conductors) formed in each dielectric layer. Note that the laminate 2 is not limited to a rectangular parallelepiped or a substantially rectangular parallelepiped, and may be a three-dimensional body having other shapes.

[0020] The laminate 2 has a first main surface 201 and a second main surface 202. A second electrode P2 is formed on a second dielectric layer (not shown) close to the second main surface 202 of the laminate 2. Also, a first electrode P1 is formed on a first dielectric layer (not shown) close to the first main surface 201 of the laminate 2. In FIGS. 1 to 3, the first electrode P1 is indicated by a two-dot chain line.

[0021] (2.2) Terminals The plurality of terminals 3 (input terminal T1, output terminal T2, and ground terminal GND) are flat plate-shaped electrodes provided on the laminate 2. More specifically, the plurality of terminals 3 are arranged on the second main surface 202 of the laminate 2. The plurality of terminals 3 are LGA (Land Grid Array) terminals regularly arranged on the second main surface 202 of the laminate 2. The plurality of terminals 3 are external terminals for connecting the LC filter 1 and an external device (not shown).

[0022] The plurality of terminals 3 include an input terminal T1 (first input / output port) and an output terminal T2 (second input / output port). The input terminal T1 is connected to a first capacitor electrode PC1. The output terminal T2 is connected to a third capacitor electrode PC3. Also, the plurality of terminals 3 include a ground terminal GND. The ground terminal GND has a ground potential.

[0023] (2.3) First Electrode, Second Electrode As shown in FIGS. 1 to 3, the first electrode P1 is provided in a first dielectric layer (not shown) among a plurality of dielectric layers of the laminate 2. The first electrode P1 is a flat electrode having a flat plate shape. In a plan view from the lamination direction (first direction D1) of the laminate 2, the first electrode P1 has a rectangular shape.

[0024] The second electrode P2 is provided in a second dielectric layer (not shown) different from the first dielectric layer among the plurality of dielectric layers of the laminate 2. The second electrode P2 is a flat electrode having a flat plate shape. The second electrode P2 is connected to the ground terminal GND. More specifically, the second electrode P2 is connected to the ground terminal GND disposed on the second main surface 202 of the laminate 2 via a via (not shown).

[0025] (2.4) Capacitor electrodes As shown in FIGS. 1 to 3, the LC filter 1 includes a first capacitor electrode PC1, a second capacitor electrode PC2, and a third capacitor electrode PC3 as a plurality of capacitor electrodes PC0.

[0026] The first capacitor electrode PC1 has a flat plate shape and is formed in a dielectric layer (not shown) between the first electrode P1 and the second electrode P2 in the first direction D1. The first capacitor electrode PC1 is disposed spaced apart from the second electrode P2, and forms a first capacitor C1 (see FIG. 4) with the second electrode P2. The first capacitor electrode PC1 is connected to the first inductor pattern portion PL1.

[0027] The second capacitor electrode PC2 has a flat plate shape and is formed in a dielectric layer (not shown) between the first electrode P1 and the second electrode P2 in the first direction D1. More specifically, the second capacitor electrode PC2 has a first portion PC21 and a second portion PC22. The second capacitor electrode PC2 is disposed spaced apart from the second electrode P2, and forms a second capacitor C2 (see FIG. 4) with the second electrode P2.

[0028] The third capacitor electrode PC3 has a flat plate shape and is formed in a dielectric layer (not shown) between the first electrode P1 and the second electrode P2 in the first direction D1. The third capacitor electrode PC3 is arranged spaced apart from the second electrode P2 and forms a third capacitor C3 (see FIG. 4) with the second electrode P2. The third capacitor electrode PC3 is connected to the output terminal T2 via the via conductor V33.

[0029] The first capacitor electrode PC1 and the second capacitor electrode PC2 form a fourth capacitor C4 (see FIG. 4). The second capacitor electrode PC2 and the third capacitor electrode PC3 form a fifth capacitor C5 (see FIG. 4). More specifically, the first portion PC21 of the second capacitor electrode PC2 and the first capacitor electrode PC1 form the fourth capacitor C4. The second portion PC22 of the second capacitor electrode PC2 and the third capacitor electrode PC3 form the fifth capacitor C5.

[0030] The first capacitor electrode PC1, the second capacitor electrode PC2, and the third capacitor electrode PC3 are provided between the first electrode P1 and the second electrode P2 in the stacking direction (the first direction D1) of the laminate 2. In a plan view from the stacking direction of the laminate 2, a part of the first capacitor electrode PC1 may overlap with the first electrode P1 and the second electrode P2, or all of it may overlap with the first electrode P1 and the second electrode P2. In other words, the first capacitor electrode PC1 is provided between the first electrode P1 and the second electrode P2 such that at least a part of the first capacitor electrode PC1 overlaps with the first electrode P1 and the second electrode P2 in a plan view from the stacking direction of the laminate 2. Also, in a plan view from the stacking direction of the laminate 2, a part of the second capacitor electrode PC2 may overlap with the first electrode P1 and the second electrode P2, or all of it may overlap with the first electrode P1 and the second electrode P2. In other words, the second capacitor electrode PC2 is provided between the first electrode P1 and the second electrode P2 such that at least a part of the second capacitor electrode PC2 overlaps with the first electrode P1 and the second electrode P2 in a plan view from the stacking direction of the laminate 2. Furthermore, in a plan view from the stacking direction of the laminate 2, a part of the third capacitor electrode PC3 may overlap with the first electrode P1 and the second electrode P2, or all of it may overlap with the first electrode P1 and the second electrode P2. In other words, the third capacitor electrode PC3 is provided between the first electrode P1 and the second electrode P2 such that at least a part of the third capacitor electrode PC3 overlaps with the first electrode P1 and the second electrode P2 in a plan view from the stacking direction of the laminate 2.

[0031] (2.5) Inductor via As shown in FIGS. 1 to 3, the LC filter 1 includes a plurality of inductor vias V0, namely, a first inductor via V1, a second inductor via V2, and a third inductor via V3.

[0032] The first inductor via V1 is connected between the first capacitor electrode PC1 and the first electrode P1. More specifically, the first inductor via V1 has a first end 11 and a second end 12. The first end 11 of the first inductor via V1 is connected to the first capacitor electrode PC1. The second end 12 of the first inductor via V1 is connected to the first electrode P1. The first inductor via V1 forms a first inductor L1 (see FIG. 4).

[0033] The second inductor via V2 is connected between the second capacitor electrode PC2 and the first electrode P1. More specifically, the second inductor via V2 has a third end 21 and a fourth end 22. The third end 21 of the second inductor via V2 is connected to the second capacitor electrode PC2. The fourth end 22 of the second inductor via V2 is connected to the first electrode P1. The second inductor via V2 forms a second inductor L2 (see FIG. 4). The second inductor via V2 includes a plurality (two in the illustrated example) of via conductors V21, V22 that extend in the stacking direction (first direction D1) of the laminate 2. The plurality of via conductors V21, V22 are connected in parallel between the second capacitor electrode PC2 and the first electrode P1. Also, the plurality of via conductors V21, V22 are arranged side by side along the second direction D2.

[0034] The third inductor via V3 is connected between the third capacitor electrode PC3 and the first electrode P1. More specifically, the third inductor via V3 has a fifth end 31 and a sixth end 32. The fifth end 31 of the third inductor via V3 is connected to the third capacitor electrode PC3. The sixth end 32 of the third inductor via V3 is connected to the first electrode P1. The third inductor via V3 forms a third inductor L3 (see FIG. 4). The third inductor via V3 includes a plurality (two in the illustrated example) of via conductors V31, V32 that extend in the stacking direction (first direction D1) of the laminate 2. The plurality of via conductors V31, V32 are connected in parallel between the third capacitor electrode PC3 and the first electrode P1. Also, the plurality of via conductors V31, V32 are arranged side by side along the second direction D2.

[0035] Each of the first inductor via V1, the second inductor via V2, and the third inductor via V3 includes at least one via conductor.

[0036] The number of via conductors of each of the second inductor via V2 and the third inductor via V3 is greater than the number of via conductors of the first inductor via V1.

[0037] (2.6) Inductor pattern portion As shown in FIGS. 1 to 3, the first inductor pattern portion PL1 has its first end connected to at least one of the first electrode P1, the first inductor via V1, and the first capacitor electrode PC1, and its second end connected to the input terminal T1. The first inductor pattern portion PL1 forms a fourth inductor L4 (see FIG. 4).

[0038] More specifically, the first inductor pattern portion PL1 includes a plurality (two in the illustrated example) of pattern portions P41, P42 and a plurality (three in the illustrated example) of via conductors V41 to V43. The pattern portion P42 is connected to the first capacitor electrode PC1 via the via conductor V41. The pattern portion P41 is connected to the input terminal T1 via the via conductor V42. Also, the pattern portion P41 and the pattern portion P42 are connected by the via conductor V43 and are arranged side by side in the first direction D1. The via conductor V41 corresponds to the first end of the first inductor pattern portion PL1, and the via conductor V42 corresponds to the second end of the first inductor pattern portion PL1. The pattern portion P41 is provided in a state of being wound in a plane in one of the plurality of dielectric layers of the laminate 2 (not shown). The pattern portion P42 is provided in a state of being wound in a plane in one of the plurality of dielectric layers of the laminate 2, which is different from the dielectric layer in which the pattern portion P41 is provided (not shown).

[0039] As shown in FIGS. 1 to 3, in the LC filter 1, the first capacitor electrode PC1 and the third capacitor electrode PC3 do not face each other. Specifically, in the LC filter 1, a capacitor formed by the first capacitor electrode PC1 and the third capacitor electrode PC3 is not provided. As a result, the fourth inductor L4 (see FIG. 4) formed in the first inductor pattern portion PL1 can improve the loss with respect to the signals in the passband and can improve the attenuation characteristics in the stopband including the high-frequency band.

[0040] Incidentally, the inductance of the first inductor pattern portion PL1 is larger than the inductance of each of the first inductor via V1, the second inductor via V2, and the third inductor via V3. As a result, high-frequency components can be reduced by the fourth inductor L4 (see FIG. 4) constituted by the first inductor pattern portion PL1, so that the attenuation amount in the high-frequency band can be further increased.

[0041] As described above, the first inductor pattern portion PL1 (pattern portions P41, P42) is provided in a state of being wound in a plane in at least one of a plurality of dielectric layers (not shown) of the laminate 2. As a result, the inductance of the fourth inductor L4 can be easily increased as compared with the inductors (the first inductor L1, the second inductor L2, and the third inductor L3) formed by the inductor vias.

[0042] More specifically, the first inductor pattern portion PL1 of Embodiment 1 is provided in a state of being laminated and wound in at least two of the plurality of dielectric layers. Thereby, without increasing the planar area of the first inductor pattern portion PL1, the inductance of the fourth inductor L4 can be further increased. In other words, compared with an inductor that is not a laminated structure, even if the area in a plan view from the lamination direction (the first direction D1) of the laminate 2 is small, it is possible to increase the inductance of the fourth inductor L4. The planar area of the first inductor pattern portion PL1 refers to the area of the region surrounded by the outer periphery of the first inductor pattern portion PL1 in a plan view from the lamination direction (the first direction D1) of the laminate 2. The outer periphery of the first inductor pattern portion PL1 refers to the outermost edge of the first inductor pattern portion PL1 and the line connecting the outermost edges in a plan view from the lamination direction of the laminate 2.

[0043] The first inductor pattern portion PL1 is provided between the first electrode P1 and the second electrode P2 in the lamination direction (the first direction D1) of the plurality of dielectric layers in the laminate 2. In a plan view from the lamination direction of the laminate 2, a part of the first inductor pattern portion PL1 may overlap with the first electrode P1 and the second electrode P2, or all of it may overlap with the first electrode P1 and the second electrode P2. In other words, the first inductor pattern portion PL1 is provided between the first electrode P1 and the second electrode P2 so that at least a part of the first inductor pattern portion PL1 overlaps with the first electrode P1 and the second electrode P2 in a plan view from the lamination direction of the laminate 2.

[0044] In particular, the first inductor pattern portion PL1 is provided between the first electrode P1 and the first capacitor electrode PC1 in the stacking direction (first direction D1) of the laminate 2. The first inductor pattern portion PL1 may partially overlap with the first electrode P1 and the first capacitor electrode PC1, or may entirely overlap with the first electrode P1 and the first capacitor electrode PC1 in a plan view from the stacking direction of the laminate 2. In other words, the first inductor pattern portion PL1 is provided between the first electrode P1 and the first capacitor electrode PC1 such that at least a part of the first inductor pattern portion PL1 overlaps with the first electrode P1 and the first capacitor electrode PC1 in a plan view from the stacking direction of the laminate 2.

[0045] The second capacitor electrode PC2 has a first portion PC21 and a second portion PC22. The first portion PC21 faces the first capacitor electrode PC1 in the stacking direction (first direction D1) of the laminate 2. The second portion PC22 faces the third capacitor electrode PC3 in the stacking direction (first direction D1) of the laminate 2.

[0046] The first inductor pattern portion PL1 is provided between the first electrode P1 and the first portion PC21 of the second capacitor electrode PC2 in the stacking direction (first direction D1) of the laminate 2. The first inductor pattern portion PL1 may partially overlap with the first electrode P1 and the first portion PC21 of the second capacitor electrode PC2, or may entirely overlap with the first electrode P1 and the first portion PC21 of the second capacitor electrode PC2 in a plan view from the stacking direction of the laminate 2. In other words, the first inductor pattern portion PL1 is provided between the first electrode P1 and the first portion PC21 of the second capacitor electrode PC2 such that at least a part of the first inductor pattern portion PL1 overlaps with the first electrode P1 and the first portion PC21 of the second capacitor electrode PC2 in a plan view from the stacking direction of the laminate 2.

[0047] (3) Circuit configuration of the LC filter Next, the circuit configuration of the LC filter 1 will be described with reference to FIG. 4. In FIG. 4, the connection portions indicated by broken lines correspond to the first electrode P1, the second electrode P2, the first capacitor electrode PC1, the second capacitor electrode PC2, and the third capacitor electrode PC3 in FIGS. 1 to 3.

[0048] As shown in FIG. 4, the LC filter 1 includes a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a first inductor L1, a second inductor L2, a third inductor L3, and a fourth inductor L4.

[0049] (3.1) First capacitor, first inductor The first capacitor C1 is formed between the first capacitor electrode PC1 and the second electrode P2. The first capacitor C1 is formed by capacitive coupling between the first capacitor electrode PC1 and the second electrode P2. The second electrode P2 is connected to the ground terminal GND. The first inductor L1 is connected between the first capacitor electrode PC1 and the first electrode P1. The first inductor L1 corresponds to the first inductor via V1.

[0050] (3.2) Second capacitor, second inductor The second capacitor C2 is formed between the second capacitor electrode PC2 and the second electrode P2. The second capacitor C2 is formed by capacitive coupling between the second capacitor electrode PC2 and the second electrode P2. The second inductor L2 is connected between the second capacitor electrode PC2 and the first electrode P1. The second inductor L2 corresponds to the second inductor via V2 (via conductors V21, V22, see FIG. 1).

[0051] (3.3) Third capacitor, third inductor The third capacitor C3 is formed between the third capacitor electrode PC3 and the second electrode P2. The third capacitor C3 is formed by the capacitive coupling between the third capacitor electrode PC3 and the second electrode P2. The third capacitor C3 is connected to the output terminal T2. The third inductor L3 is connected between the third capacitor electrode PC3 and the first electrode P1. The third inductor L3 corresponds to the third inductor via V3 (via conductors V31, V32, see FIG. 1).

[0052] (3.4) Fourth capacitor The fourth capacitor C4 is formed between the first capacitor electrode PC1 and the second capacitor electrode PC2. The fourth capacitor C4 is formed by the capacitive coupling between the first capacitor electrode PC1 and the second capacitor electrode PC2.

[0053] (3.5) Fifth capacitor The fifth capacitor C5 is formed between the second capacitor electrode PC2 and the third capacitor electrode PC3. The fifth capacitor C5 is formed by the capacitive coupling between the second capacitor electrode PC2 and the third capacitor electrode PC3.

[0054] (3.6) Fourth inductor The fourth inductor L4 is connected between the input terminal T1 and the first capacitor electrode PC1. The fourth inductor L4 corresponds to the first inductor pattern portion PL1.

[0055] In the LC filter 1, no capacitor is formed between the first capacitor electrode PC1 and the third capacitor electrode PC3. That is, there is no capacitor formed by the capacitive coupling between the first capacitor electrode PC1 and the third capacitor electrode PC3 in the LC filter 1.

[0056] (4) Filter characteristics Next, the simulation results of the passing characteristics of the LC filter 1 according to Embodiment 1 will be described with reference to FIG. 5. FIG. 5 shows the passing characteristics (solid lines S1, S2) of the LC filter 1 according to Embodiment 1 and the passing characteristics (dashed lines S3, S4) of the LC filter of the comparative example. In FIG. 5, the horizontal axis represents the frequency, and the vertical axis represents the insertion loss (solid line S1, dashed line S3) and the reflection loss (solid line S2, dashed line S4) of the LC filter 1.

[0057] First, the LC filter of the comparative example will be described. In the LC filter of the comparative example, the fourth inductor L4 is not connected between the input terminal T1 and the first capacitor electrode PC1. Also, in the LC filter of the comparative example, the first capacitor electrode PC1 and the third capacitor electrode PC3 face each other. Specifically, in the LC filter of the comparative example, a capacitor formed by the first capacitor electrode PC1 and the third capacitor electrode PC3 is provided. Regarding the insertion loss (dashed line S3), about 10 dB is achieved at the high-frequency side end of the passband. On the other hand, in the stopband, which is a frequency band higher than the cut-off frequency, there is a band with an attenuation amount less than 10 dB, and sufficient attenuation cannot be ensured. In the reflection characteristic (dashed line S4), it is lower than 12 dB throughout the passband.

[0058] Next, the LC filter 1 according to Embodiment 1 will be described. As described above, in the LC filter 1 according to Embodiment 1, a fourth inductor L4 is connected between the input terminal T1 and the first capacitor electrode PC1 (see FIG. 4). Further, in the LC filter 1 according to Embodiment 1, the first capacitor electrode PC1 and the third capacitor electrode PC3 do not face each other (see FIGS. 1 to 3). Specifically, in the LC filter 1 according to Embodiment 1, a capacitor formed by the first capacitor electrode PC1 and the third capacitor electrode PC3 is not provided. As a result, about 10 dB is realized at the high-frequency side end of the passband for the insertion loss (solid line S1). Also, in the stopband higher in frequency than the passband, an attenuation characteristic of 10 dB or more is obtained. Also, the reflection characteristic (solid line S2) is lower than 12 dB over the entire passband, similar to the reflection characteristic (dashed line S4) of the comparative example.

[0059] As described above, by applying a configuration in which the fourth inductor L4 is connected between the input terminal T1 and the first capacitor electrode PC1 and there is no capacitor between the first capacitor electrode PC1 and the third capacitor electrode PC3 to the LC filter (low-pass filter) 1, it is possible to improve the attenuation characteristic in the stopband while maintaining the loss for the signal in the passband at the same level.

[0060] (5) Effects In the LC filter 1 according to Embodiment 1, a fourth inductor L4 connected to at least one of the first electrode P1, the first inductor via V1, and the first capacitor electrode PC1 and the input terminal T1 (first input / output port) is provided. Also, the first capacitor electrode PC1 and the third capacitor electrode PC3 do not face each other. As a result, the fourth inductor L4 formed in the first inductor pattern portion PL1 can improve (maintain) the loss for the signal in the passband and improve the attenuation characteristic in the stopband including the high-frequency band.

[0061] In the LC filter 1 according to Embodiment 1, the inductance of the first inductor pattern portion PL1 forming the fourth inductor L4 is larger than the inductance of each of the first inductor via V1 forming the first inductor L1, the second inductor via V2 forming the second inductor L2, and the third inductor via V3 forming the third inductor L3. Thereby, since the high-frequency component can be reduced by the fourth inductor L4, the attenuation amount in the high-frequency band can be further increased.

[0062] In the LC filter 1 according to Embodiment 1, the first inductor pattern portion PL1 forming the fourth inductor L4 is provided in at least one of the plurality of dielectric layers in a state of being wound on a plane. Thereby, the inductance of the fourth inductor L4 can be easily increased as compared with the inductors (the first inductor L1, the second inductor L2, and the third inductor L3) formed by inductor vias.

[0063] In the LC filter 1 according to Embodiment 1, the first inductor pattern portion PL1 forming the fourth inductor L4 is provided in a state of being laminated and wound in at least two of the plurality of dielectric layers. Thereby, the inductance of the fourth inductor L4 can be further increased without increasing the area on the plane in the first inductor pattern portion PL1. The area on the plane in the first inductor pattern portion PL1 refers to the area of the region surrounded by the outer periphery of the first inductor pattern portion PL1 in a plan view from the lamination direction (the first direction D1) of the laminate 2. The outer periphery of the first inductor pattern portion PL1 refers to the outermost edge of the first inductor pattern portion PL1 and the line connecting the outermost edges in a plan view from the lamination direction of the laminate 2.

[0064] (6) Modification Hereinafter, a modification of Embodiment 1 will be described.

[0065] (6.1) Modification 1 As a first modification example of Embodiment 1, the first inductive via V1 may be formed of a plurality of via conductors. In other words, the first inductive via V1 may have at least one via conductor.

[0066] (6.2) Second modification example As a second modification example of Embodiment 1, the second inductive via V2 may be formed of one via conductor, similar to the first inductive via V1. Alternatively, the second inductive via V2 may be formed of three or more via conductors. In other words, the second inductive via V2 may have at least one via conductor.

[0067] (6.3) Third modification example As a third modification example of Embodiment 1, the third inductive via V3 may be formed of one via conductor, similar to the first inductive via V1. Alternatively, the third inductive via V3 may be formed of three or more via conductors. In other words, the third inductive via V3 may have at least one via conductor.

[0068] (6.4) Fourth modification example As a fourth modification example of Embodiment 1, the first inductor pattern portion PL1 may be provided in a state of being wound on a plane in one of a plurality of dielectric layers (not shown) of the laminate 2. Further, the first inductor pattern portion PL1 may be provided in a state of being laminated and wound in three or more of a plurality of dielectric layers of the laminate 2. In other words, the first inductor pattern portion PL1 may be provided in a state of being wound on a plane in at least one of a plurality of dielectric layers of the laminate 2.

[0069] Also in the LC filter 1 according to each of the above modification examples, the same effects as those of the LC filter 1 according to Embodiment 1 are achieved.

[0070] (Embodiment 2) As shown in FIGS. 6 to 8, the LC filter 1A according to Embodiment 2 is different from the LC filter 1 (see FIG. 1) according to Embodiment 1 in that the first inductor via V1 has a plurality (two in the illustrated example) of via conductors V11 and V12. Regarding the LC filter 1A according to Embodiment 2, components similar to those of the LC filter 1 according to Embodiment 1 are denoted by the same reference numerals and the description thereof is omitted.

[0071] (1) Configuration As shown in FIGS. 6 to 8, the first inductor via V1 of Embodiment 2 has a via conductor V11 (first partial via) and a via conductor V12 (second partial via). The via conductor V11 is connected to the first electrode P1 and the first inductor pattern portion PL1. The via conductor V12 is connected to the first capacitor electrode PC1 and the first inductor pattern portion PL1. Regarding the first inductor via V1 of Embodiment 2, the description of the configuration and function similar to those of the first inductor via V1 (see FIG. 1) of Embodiment 1 is omitted.

[0072] As shown in FIGS. 6 to 8, the first inductor pattern portion PL1 of Embodiment 2 has its first end connected to at least one of the first electrode P1, the first inductor via V1, and the first capacitor electrode PC1, and its second end connected to the input terminal T1. The first inductor pattern portion PL1 forms a fourth inductor L4 (see FIG. 9).

[0073] More specifically, the first inductor pattern portion PL1 includes a plurality (two in the illustrated example) of pattern portions P41, P42, a connection portion P43, and a plurality (two in the illustrated example) of via conductors V42, V43. The pattern portion P42 is connected to the first inductor via V1 through the connection portion P43. The pattern portion P41 is connected to the input terminal T1 through the via conductor V42. Further, the pattern portion P41 and the pattern portion P42 are connected by the via conductor V43 and are arranged side by side in the first direction D1. The connection portion P43 corresponds to the first end of the first inductor pattern portion PL1, and the via conductor V42 corresponds to the second end of the first inductor pattern portion PL1. Regarding the first inductor pattern portion PL1 of the second embodiment, descriptions of the same configuration and functions as those of the first inductor pattern portion PL1 (see FIG. 1) of the first embodiment are omitted.

[0074] As shown in FIG. 9, the first inductor L1 of the second embodiment has two inductors L11, L12. The inductor L11 is formed by the via conductor V11. The inductor L12 is formed by the via conductor V12. The inductor L11 is connected to the second inductor L2, the third inductor L3, and the fourth inductor L4. The inductor L12 is connected to the first capacitor C1, the fourth capacitor C4, and the fourth inductor L4. Regarding the first inductor L1 of the second embodiment, descriptions of the same configuration and functions as those of the first inductor L1 (see FIG. 4) of the first embodiment are omitted.

[0075] In the LC filter 1A according to the second embodiment, similar to the LC filter 1 (see FIG. 4) according to the first embodiment, no capacitor is formed between the first capacitor electrode PC1 and the third capacitor electrode PC3. That is, there is no capacitor formed by the capacitive coupling between the first capacitor electrode PC1 and the third capacitor electrode PC3 in the LC filter 1A.

[0076] (2) Effects Also in the LC filter 1A according to Embodiment 2, similar to the LC filter 1 according to Embodiment 1, the fourth inductor L4 formed by the first inductor pattern portion PL1 can improve the loss with respect to the signals in the passband and can improve the attenuation characteristics in the stopband including the high-frequency band.

[0077] (3) Modification As a modification of Embodiment 2, the first inductor via V1 is not limited to being formed of two via conductors, and may be formed of three or more via conductors.

[0078] Also in the LC filter 1A according to the above modification, the same effects as those of the LC filter 1A according to Embodiment 2 can be obtained.

[0079] (Embodiment 3) As shown in FIGS. 10 to 12, the LC filter 1B according to Embodiment 3 is different from the LC filter 1 (see FIG. 1) according to Embodiment 1 in that it includes a second inductor pattern portion PL2. For the LC filter 1B according to Embodiment 3, the same components as those of the LC filter 1 according to Embodiment 1 are denoted by the same reference numerals and the description thereof is omitted.

[0080] (1) Configuration As shown in FIGS. 10 to 12, the LC filter 1B according to Embodiment 3 includes a second inductor pattern portion PL2.

[0081] The second inductor pattern portion PL2 has its third end connected to at least one of the first electrode P1, the third inductor via V3, and the third capacitor electrode PC3, and its fourth end connected to the output terminal T2. The second inductor pattern portion PL2 forms a fifth inductor L5 (see FIG. 13).

[0082] More specifically, the second inductor pattern portion PL2 includes a plurality (two in the illustrated example) of pattern portions P51 and P52 and a plurality (three in the illustrated example) of via conductors V51 to V53. The pattern portion P51 is connected to the third capacitor electrode PC3 via the via conductor V51. The pattern portion P51 is connected to the output terminal T2 via the via conductor V52, the pattern portion P52, and the via conductor V53. The via conductor V51 corresponds to the third end of the second inductor pattern portion PL2, and the via conductor V53 corresponds to the second end of the second inductor pattern portion PL2.

[0083] Next, the circuit configuration of the LC filter 1B according to Embodiment 3 will be described with reference to FIG. 13. In FIG. 13, the connection portions indicated by broken lines correspond to the first electrode P1, the second electrode P2, the first capacitor electrode PC1, the second capacitor electrode PC2, and the third capacitor electrode PC3 in FIGS. 10 to 12.

[0084] As shown in FIG. 13, the LC filter 1B includes a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a first inductor L1, a second inductor L2, a third inductor L3, a fourth inductor L4, and a fifth inductor L5.

[0085] The fifth inductor L5 is connected between the output terminal T2 and the third capacitor electrode PC3. The fifth inductor L5 corresponds to the second inductor pattern portion PL2.

[0086] Incidentally, the inductance of the second inductor pattern portion PL2 is larger than the inductance of each of the first inductor via V1, the second inductor via V2, and the third inductor via V3. Thereby, since the high-frequency component can be reduced by the fifth inductor L5 (see FIG. 13) constituted by the second inductor pattern portion PL2, the attenuation amount in the high-frequency band can be further increased.

[0087] Further, the second inductor pattern portion PL2 is provided in a state of being wound in a plane in at least one of a plurality of dielectric layers (not shown) of the laminate 2. Thereby, the inductance of the fifth inductor L5 can be easily increased as compared with the inductors (the first inductor L1, the second inductor L2, and the third inductor L3) formed by inductor vias.

[0088] In the LC filter 1B according to the third embodiment, no capacitor is formed between the first capacitor electrode PC1 and the third capacitor electrode PC3. That is, the LC filter 1B does not have a capacitor formed by the capacitive coupling between the first capacitor electrode PC1 and the third capacitor electrode PC3.

[0089] (2) Filter characteristics Next, the simulation results of the passing characteristics of the LC filter 1B according to the third embodiment will be described with reference to FIG. 14. FIG. 14 shows the passing characteristics (solid lines S5 and S6) of the LC filter 1B according to the third embodiment and the passing characteristics (dashed lines S7 and S8) of the LC filter of the comparative example. In FIG. 14, the horizontal axis represents the frequency, and the vertical axis represents the insertion loss (solid lines S5 and S7) and the reflection loss (solid lines S6 and S8) of the LC filter 1B.

[0090] First, the LC filter of the comparative example will be described. In the LC filter of the comparative example, the fourth inductor L4 is not connected between the input terminal T1 and the first capacitor electrode PC1, and the fifth inductor L5 is not connected between the output terminal T2 and the third capacitor electrode PC3. Also, in the LC filter of the comparative example, the first capacitor electrode PC1 and the third capacitor electrode PC3 face each other. Specifically, in the LC filter of the comparative example, a capacitor formed by the first capacitor electrode PC1 and the third capacitor electrode PC3 is provided. Regarding the insertion loss (dashed line S7), about 10 dB is achieved at the high-frequency side end of the passband. On the other hand, in the stopband, which is a frequency band higher than the cut-off frequency, there is a band with an attenuation amount less than 10 dB, and sufficient attenuation cannot be ensured. Note that in terms of the reflection characteristic (dashed line S8), it is lower than 12 dB throughout the passband.

[0091] Subsequently, the LC filter 1B according to Embodiment 3 will be described. As described above, in the LC filter 1B according to Embodiment 3, the fourth inductor L4 is connected between the input terminal T1 and the first capacitor electrode PC1 (see FIG. 13), and the fifth inductor L5 is connected between the output terminal T2 and the third capacitor electrode PC3 (see FIG. 13). Also, in the LC filter 1B according to Embodiment 3, the first capacitor electrode PC1 and the third capacitor electrode PC3 do not face each other (see FIGS. 10 to 12). Specifically, in the LC filter 1B according to Embodiment 3, a capacitor formed by the first capacitor electrode PC1 and the third capacitor electrode PC3 is not provided. As a result, regarding the insertion loss (solid line S5), about 10 dB is achieved at the high-frequency side end of the passband. Also, in the stopband on the higher frequency side than the passband, an attenuation characteristic of 20 dB or more is obtained. Also, the reflection characteristic (solid line S6) is lower than 16 dB throughout the passband.

[0092] As described above, a fourth inductor L4 is connected between the input terminal T1 and the first capacitor electrode PC1, and a fifth inductor L5 is connected between the output terminal T2 and the third capacitor electrode PC3. By applying a configuration without a capacitor between the first capacitor electrode PC1 and the third capacitor electrode PC3 to the LC filter (low-pass filter) 1B, it is possible to improve the attenuation characteristics in the non-passband while maintaining the loss for the signals in the passband at the same level.

[0093] (3) Effects In the LC filter 1B according to Embodiment 3, a fifth inductor L5 is provided that is connected to at least one of the first electrode P1, the third inductor via V3, and the third capacitor electrode PC3 and the output terminal T2 (the second input / output port). Thereby, since the high-frequency components can be reduced by the fifth inductor L5, the attenuation amount in the high-frequency band can be further increased.

[0094] In the LC filter 1B according to Embodiment 3, the inductance of the second inductor pattern portion PL2 forming the fifth inductor L5 is larger than the inductance of each of the first inductor via V1 forming the first inductor L1, the second inductor via V2 forming the second inductor L2, and the third inductor via V3 forming the third inductor L3. Thereby, since the high-frequency components can be reduced by the fifth inductor L5, the attenuation amount in the high-frequency band can be further increased.

[0095] In the LC filter 1B according to Embodiment 3, the second inductor pattern portion PL2 forming the fifth inductor L5 is provided in a state of being wound on a plane in at least one of the plurality of dielectric layers. Thereby, the inductance of the fifth inductor L5 can be easily increased compared to the inductors (the first inductor L1, the second inductor L2, the third inductor L3) formed by the inductor vias.

[0096] (4) Modification As a modification of Embodiment 3, the second inductor pattern portion PL2 may be provided in a state of being stacked and wound in at least two of a plurality of dielectric layers (not shown) of the laminate 2. In other words, the second inductor pattern portion PL2 may be provided in a state of being wound on a plane in at least one of a plurality of dielectric layers of the laminate 2.

[0097] In the LC filter 1B according to the modification of Embodiment 3, the second inductor pattern portion PL2 forming the fifth inductor L5 is provided in a state of being stacked and wound in at least two of a plurality of dielectric layers. Thereby, the inductance of the fifth inductor L5 can be further increased without increasing the area on the plane in the second inductor pattern portion PL2.

[0098] The LC filter 1B according to the above modification also has the same effects as the LC filter 1B according to Embodiment 3.

[0099] (Embodiment 4) The LC filter 1C according to Embodiment 4 is different from the LC filter 1B (see FIG. 10) according to Embodiment 3 in that the third inductor via V3 has a plurality (two in the illustrated example) of via conductors V33 and V34. For the LC filter 1C according to Embodiment 4, the same components as those of the LC filter 1B according to Embodiment 3 are denoted by the same reference numerals and the description thereof is omitted.

[0100] (1) Configuration As shown in FIGS. 15 to 17, the third inductor via V3 of Embodiment 4 has a via conductor V33 (first partial via) and a via conductor V34 (second partial via). More specifically, the via conductor V32 in the third inductor via V3 has the via conductor V33 and the via conductor V34. The via conductor V33 is connected to the first electrode P1 and the second inductor pattern portion PL2. The via conductor V34 is connected to the third capacitor electrode PC3 and the second inductor pattern portion PL2. Regarding the third inductor via V3 of Embodiment 4, descriptions of the same configuration and function as those of the third inductor via V3 (see FIG. 10) of Embodiment 3 are omitted.

[0101] As shown in FIG. 18, the third inductor L3 of Embodiment 4 has two inductors L31 and L32. The inductor L31 is formed by the via conductor V33. The inductor L32 is formed by the via conductor V34. The inductor L31 is connected to the first inductor L1, the second inductor L2, and the fifth inductor L5. The inductor L32 is connected to the third capacitor C3, the fifth capacitor C5, and the fifth inductor L5. Regarding the first inductor L1 of Embodiment 2, descriptions of the same configuration and function as those of the first inductor L1 (see FIG. 4) of Embodiment 1 are omitted.

[0102] In the LC filter 1C according to Embodiment 4, similar to the LC filter 1B according to Embodiment 3 (see FIG. 13), no capacitor is formed between the first capacitor electrode PC1 and the third capacitor electrode PC3. That is, there is no capacitor formed by the capacitive coupling between the first capacitor electrode PC1 and the third capacitor electrode PC3 in the LC filter 1C.

[0103] (2) Effects Also in the LC filter 1C according to Embodiment 4, similar to the LC filter 1B according to Embodiment 3, the high-frequency components can be reduced by the fifth inductor L5, so that the attenuation amount in the high-frequency band can be further increased.

[0104] (3) Modifications As a modification of Embodiment 4, the third inductor via V3 (via conductor V32) is not limited to being formed by two via conductors V33 and V34 (partial vias), and may be formed by three or more via conductors (partial vias).

[0105] Also in the LC filter 1C according to the above modification, the same effects as those of the LC filter 1C according to Embodiment 4 are achieved.

[0106] (Embodiment 5) In Embodiment 5, a configuration in which the LC filters 1, 1A to 1C according to Embodiments 1 to 4 and each modification are applied to a multiplexer 7 (see FIG. 19) will be described. Hereinafter, a case where the LC filter 1 according to Embodiment 1 is applied to the multiplexer 7 will be described.

[0107] (1) Configuration As shown in FIG. 19, the multiplexer 7 according to Embodiment 5 includes an input terminal T31, two output terminals T32 and T33, a first filter 71, a second filter 72, a plurality (two in the illustrated example) of inductors L10 and L20, and a plurality (two in the illustrated example) of capacitors C10 and C20.

[0108] The first filter 71 is connected between the input terminal T31 and the output terminal T32. The first filter 71 is a low-pass filter (LPF) that passes signals in a frequency band lower than a predetermined frequency and includes the LC filter 1.

[0109] One end (first end) of the inductor L10 is connected to the input terminal T31, and the other end (second end) is connected to the first filter 71. The capacitor C10 is connected between the connection node between the inductor L10 and the first filter 71 and the ground. The inductor L10 and the capacitor C10 form a low-pass filter and function as a branching circuit for high-frequency signals input to the input terminal T31.

[0110] The second filter 72 is connected between the input terminal T31 and the output terminal T33. The second filter 72 is a band-pass filter (BPF) or a high-pass filter (HPF) that passes signals in a frequency band higher than the passband of the first filter 71.

[0111] One end (the first end) of the capacitor C20 is connected to the input terminal T31, and the other end (the second end) is connected to the second filter 72. The inductor L20 is connected between the connection node between the capacitor C20 and the second filter 72 and the ground. The inductor L20 and the capacitor C20 form a high-pass filter and function as a frequency division circuit for the high-frequency signal received at the input terminal T31.

[0112] (2) Effects By applying the LC filter 1 according to Embodiment 1 as the first filter 71 (low-pass filter) in the multiplexer 7 according to Embodiment 5, a multiplexer 7 with low loss and high attenuation characteristics can be realized. Even when any one of the LC filters 1A to 1C according to Embodiments 2 to 4 is applied as the first filter 71, the same effect can be obtained.

[0113] (3) Modification As a modification of Embodiment 5, any one of the LC filters 1, 1A to 1C according to Embodiments 1 to 4 and each modification may be applied to a multiplexer 7A composed of three or more filters.

[0114] As shown in FIG. 20, the multiplexer 7A includes an input terminal T34, three output terminals T35 to T37, a first filter 71A, a second filter 72A, a third filter 73A, a plurality (two in the illustrated example) of inductors L10, L30, and a plurality (two in the illustrated example) of capacitors C10, C30.

[0115] The first filter 71A is connected between the input terminal T34 and the output terminal T35. The first filter 71A is a low-pass filter (LPF) that passes signals in a frequency band lower than a predetermined frequency, and a configuration similar to any of the LC filters 1, 1A to 1C according to Embodiments 1 to 4 and each modification can be applied.

[0116] One end (the first end) of the inductor L10 is connected to the input terminal T34, and the other end (the second end) is connected to the first filter 71A. The capacitor C10 is connected between the connection node between the inductor L10 and the first filter 71A and the ground. The inductor L10 and the capacitor C10 form a low-pass filter and function as a frequency-dividing circuit for high-frequency signals input to the input terminal T34.

[0117] The second filter 72A is connected between the input terminal T34 and the output terminal T36. The second filter 72A is a band-pass filter (BPF) that passes signals in a frequency band higher than the passband of the first filter 71A.

[0118] The third filter 73A is connected between the input terminal T34 and the output terminal T37. The third filter 73A is a high-pass filter (HPF) or a band-pass filter (BPF) that passes signals in a frequency band even higher than the passband of the second filter 72A.

[0119] One end (the first end) of the capacitor C30 is connected to the input terminal T34, and the other end (the second end) is connected to the third filter 73A. The inductor L30 is connected between the connection node between the capacitor C30 and the third filter 73A and the ground. The inductor L30 and the capacitor C30 form a high-pass filter and function as a frequency-dividing circuit for high-frequency signals input to the input terminal T34.

[0120] Also in the multiplexer 7A according to the modification example, by applying any one of the LC filters 1, 1A to 1C according to Embodiments 1 to 4 and each modification example as the low-pass filter provided in the signal passing path of the lowest frequency band, a multiplexer 7A with low loss and high attenuation characteristics can be realized. That is, also in the multiplexer 7A, while maintaining the loss for the signals in the passband to the same extent, the attenuation characteristics in the non-passband can be improved.

[0121] Also in the multiplexer 7A according to the above modification example, the same effects as those of the multiplexer 7 according to Embodiment 5 are achieved.

[0122] (Embodiment 6) In Embodiment 6, a high-frequency module 8 including any one of the LC filters 1, 1A to 1C according to Embodiments 1 to 4 and each modification example, and a communication device 9 including the high-frequency module 8 will be described with reference to the drawings. Hereinafter, the case where the LC filter 1 according to Embodiment 1 is used will be described.

[0123] (1) High-frequency module As shown in FIG. 21, the high-frequency module 8 according to Embodiment 6 includes a filter 81 and an amplifier 82. The filter 81 includes the LC filter 1 (see FIG. 1).

[0124] The high-frequency module 8 is, for example, a module compatible with 4G (Fourth Generation Mobile Communication) standards and 5G (Fifth Generation Mobile Communication) standards. The 4G standard is, for example, the 3GPP (registered trademark, Third Generation Partnership Project) LTE (registered trademark, Long Term Evolution) standard. The 5G standard is, for example, 5G NR (New Radio). The high-frequency module 8 is a module compatible with carrier aggregation and dual connectivity.

[0125] The high-frequency module 8 is configured to amplify the received signal (high-frequency signal) received by the antenna 91 described later and output it to the signal processing circuit 92 described later. Further, the high-frequency module 8 is configured to amplify the transmission signal from the signal processing circuit 92 and output it to the antenna 91. The high-frequency module 8 is controlled by, for example, the signal processing circuit 92.

[0126] (2) Communication device As shown in FIG. 21, the communication device 9 according to Embodiment 6 includes a high-frequency module 8, at least one (one in the illustrated example) antenna 91, and a signal processing circuit 92. The communication device 9 is, for example, a mobile terminal (e.g., a smartphone), but is not limited to a mobile terminal and may be, for example, a wearable terminal (e.g., a smartwatch).

[0127] The signal processing circuit 92 processes the high-frequency signals (transmission signal and reception signal) passing through the high-frequency module 8. More specifically, the signal processing circuit 92 is configured to perform signal processing on the reception signal received from the high-frequency module 8. Further, the signal processing circuit 92 is configured to perform signal processing on the transmission signal output to the high-frequency module 8. The signal processing circuit 92 includes an RF signal processing circuit 93 and a baseband signal processing circuit 94.

[0128] The RF signal processing circuit 93 is, for example, an RFIC (Radio Frequency Integrated Circuit) and performs signal processing on the high-frequency signal (reception signal). The RF signal processing circuit 93, for example, performs signal processing such as down-conversion on the reception signal received from the high-frequency module 8 and outputs it to the baseband signal processing circuit 94. Further, the RF signal processing circuit 93 performs signal processing such as up-conversion on the transmission signal output from the baseband signal processing circuit 94 and outputs it to the high-frequency module 8.

[0129] The baseband signal processing circuit 94 is, for example, a BBIC (Baseband Integrated Circuit). The baseband signal processing circuit 94 outputs the received signal received from the RF signal processing circuit 93 to the outside. This output signal (received signal) is used, for example, as an image signal for image display or as an audio signal for a call. Further, the baseband signal processing circuit 94 generates a transmission signal from the baseband signal (for example, an audio signal and an image signal) input from the outside, and outputs the generated transmission signal to the RF signal processing circuit 93.

[0130] (3) Effect By applying the LC filter 1 according to Embodiment 1 as the filter 81 (low-pass filter) in the high-frequency module 8 and the communication device 9 according to Embodiment 6, a high-frequency module 8 and a communication device 9 having low loss and high attenuation characteristics can be realized. That is, in the high-frequency module 8 and the communication device 9, the attenuation characteristics in the non-passband can be improved while maintaining the loss for the signals in the passband to the same extent. Note that the same effect can be obtained even when any one of the LC filters 1A to 1C according to Embodiments 2 to 4 is applied as the filter 81.

[0131] (Embodiment 7) In Embodiment 7, the multiplexer 7B as shown in FIGS. 22 to 25 will be described.

[0132] (1) Structure of Multiplexer As shown in FIGS. 22 to 24, the multiplexer 7B includes a laminate 2, a plurality of terminals 3, a plurality (two in the illustrated example) of first electrodes P1, a second electrode P2, a plurality of capacitor electrodes PC0, PCH0, and a plurality of inductor vias V0, VH0. Further, the multiplexer 7B according to Embodiment 7 includes a first filter 71B and a second filter 72B as shown in FIG. 25.

[0133] (1.1) Laminate The laminate 2 shown in FIGS. 22 to 24 has a rectangular parallelepiped or a substantially rectangular parallelepiped shape, and is formed by laminating a plurality of dielectric layers (not shown) in the lamination direction. That is, the laminate 2 is a structure in which a plurality of dielectric layers are laminated. Each of the plurality of dielectric layers of the laminate 2 is formed of, for example, ceramic. Inside the laminate 2, an inductor and a capacitor are formed by a plurality of wiring pattern portions, a plurality of electrodes, and a plurality of vias (via conductors) formed in each dielectric layer. Note that the laminate 2 is not limited to a rectangular parallelepiped or a substantially rectangular parallelepiped, and may be a solid having another shape.

[0134] The laminate 2 has a first main surface 201 and a second main surface 202. A second electrode P2 is formed on a second dielectric layer (not shown) close to the second main surface 202 of the laminate 2. A plurality of first electrodes P1 are formed on a first dielectric layer (not shown) close to the first main surface 201 of the laminate 2. In FIGS. 22 to 24, the plurality of first electrodes P1 are indicated by a two-dot chain line.

[0135] (1.2) Terminals The plurality of terminals 3 (common terminal T40, first terminal T41, second terminal T42, and ground terminal GND) are flat plate-shaped electrodes provided on the laminate 2. More specifically, the plurality of terminals 3 are arranged on the second main surface 202 of the laminate 2. The plurality of terminals 3 are LGA terminals regularly arranged on the second main surface 202 of the laminate 2. The plurality of terminals 3 are external terminals for connecting the multiplexer 7B and an external device (not shown).

[0136] The plurality of terminals 3 include a common terminal T40, a first terminal T41, and a second terminal T42. The plurality of terminals 3 are external terminals for connecting the multiplexer 7B and an external device (not shown).

[0137] (1.3) First Electrode, Second Electrode As shown in FIGS. 22 to 24, a plurality of first electrodes P1 are provided in a first dielectric layer (not shown) among the plurality of dielectric layers of the laminate 2. Each of the plurality of first electrodes P1 is a flat electrode having a flat plate shape. In a plan view from the lamination direction (first direction D1) of the laminate 2, each first electrode P1 has a rectangular shape. As shown in FIG. 25, among the plurality of first electrodes P1, the first electrode P11 is an electrode for the first filter 71B, and the first electrode P12 is an electrode for the second filter 72B.

[0138] The second electrode P2 is provided in a second dielectric layer (not shown) different from the first dielectric layer among the plurality of dielectric layers of the laminate 2. The second electrode P2 is a flat electrode having a flat plate shape. The second electrode P2 is connected to the ground terminal GND. More specifically, the second electrode P2 is connected to the ground terminal GND disposed on the second main surface 202 of the laminate 2 via a via (not shown).

[0139] From the above, the first filter 71B and the second filter 72B are connected to a common ground terminal GND via the second electrode P2.

[0140] (1.4) Capacitor electrodes of the first filter As shown in FIGS. 22 to 24, the first filter 71B includes a first capacitor electrode PC1, a second capacitor electrode PC2, and a third capacitor electrode PC3 as a plurality of capacitor electrodes PC0.

[0141] The first capacitor electrode PC1 has a flat plate shape and is formed in a dielectric layer (not shown) between the first electrode P11 and the second electrode P2 in the first direction D1. The first capacitor electrode PC1 is disposed at a distance from the second electrode P2 and forms a first capacitor C1 (see FIG. 25) with the second electrode P2. The first capacitor electrode PC1 is connected to the first inductor pattern portion PL1.

[0142] The second capacitor electrode PC2 has a flat plate shape and is formed in a dielectric layer (not shown) between the first electrode P11 and the second electrode P2 in the first direction D1. More specifically, the second capacitor electrode PC2 has a first portion PC21 and a second portion PC22. The second capacitor electrode PC2 is disposed at a distance from the second electrode P2 and forms a second capacitor C2 (see FIG. 25) therebetween.

[0143] The third capacitor electrode PC3 has a flat plate shape and is formed in a dielectric layer (not shown) between the first electrode P11 and the second electrode P2 in the first direction D1. The third capacitor electrode PC3 is disposed at a distance from the second electrode P2 and forms a third capacitor C3 (see FIG. 25) therebetween. The third capacitor electrode PC3 is connected to the first terminal T41 via the via conductor V33.

[0144] The first capacitor electrode PC1 and the second capacitor electrode PC2 form a fourth capacitor C4 (see FIG. 25). The second capacitor electrode PC2 and the third capacitor electrode PC3 form a fifth capacitor C5 (see FIG. 25). More specifically, the first portion PC21 of the second capacitor electrode PC2 and the first capacitor electrode PC1 form the fourth capacitor C4. The second portion PC22 of the second capacitor electrode PC2 and the third capacitor electrode PC3 form the fifth capacitor C5.

[0145] The first capacitor electrode PC1, the second capacitor electrode PC2, and the third capacitor electrode PC3 are provided between the first electrode P11 and the second electrode P2 in the stacking direction (the first direction D1) of the laminate 2. The first capacitor electrode PC1 may partially overlap with the first electrode P11 and the second electrode P2, or may entirely overlap with the first electrode P11 and the second electrode P2 in a plan view from the stacking direction of the laminate 2. In other words, the first capacitor electrode PC1 is provided between the first electrode P11 and the second electrode P2 such that at least a part of the first capacitor electrode PC1 overlaps with the first electrode P11 and the second electrode P2 in a plan view from the stacking direction of the laminate 2. Also, the second capacitor electrode PC2 may partially overlap with the first electrode P11 and the second electrode P2, or may entirely overlap with the first electrode P11 and the second electrode P2 in a plan view from the stacking direction of the laminate 2. In other words, the second capacitor electrode PC2 is provided between the first electrode P11 and the second electrode P2 such that at least a part of the second capacitor electrode PC2 overlaps with the first electrode P11 and the second electrode P2 in a plan view from the stacking direction of the laminate 2. Further, the third capacitor electrode PC3 may partially overlap with the first electrode P11 and the second electrode P2, or may entirely overlap with the first electrode P11 and the second electrode P2 in a plan view from the stacking direction of the laminate 2. In other words, the third capacitor electrode PC3 is provided between the first electrode P11 and the second electrode P2 such that at least a part of the third capacitor electrode PC3 overlaps with the first electrode P11 and the second electrode P2 in a plan view from the stacking direction of the laminate 2.

[0146] (1.5) Inductor via of the first filter As shown in FIGS. 22 to 24, the first filter 71B includes a first inductor via V1, a second inductor via V2, and a third inductor via V3 as a plurality of inductor vias V0.

[0147] The first inductor via V1 is connected between the first capacitor electrode PC1 and the first electrode P11. More specifically, the first inductor via V1 has a first end 11 and a second end 12. The first end 11 of the first inductor via V1 is connected to the first capacitor electrode PC1. The second end 12 of the first inductor via V1 is connected to the first electrode P11. The first inductor via V1 forms a first inductor L1 (see FIG. 25).

[0148] The second inductor via V2 is connected between the second capacitor electrode PC2 and the first electrode P11. More specifically, the second inductor via V2 has a third end 21 and a fourth end 22. The third end 21 of the second inductor via V2 is connected to the second capacitor electrode PC2. The fourth end 22 of the second inductor via V2 is connected to the first electrode P11. The second inductor via V2 forms a second inductor L2 (see FIG. 25). The second inductor via V2 includes a plurality (two in the illustrated example) of via conductors V21, V22 extending in the stacking direction (first direction D1) of the laminate 2. The plurality of via conductors V21, V22 are connected in parallel between the second capacitor electrode PC2 and the first electrode P11. Also, the plurality of via conductors V21, V22 are arranged side by side along the second direction D2.

[0149] The third inductor via V3 is connected between the third capacitor electrode PC3 and the first electrode P11. More specifically, the third inductor via V3 has a fifth end 31 and a sixth end 32. The fifth end 31 of the third inductor via V3 is connected to the third capacitor electrode PC3. The sixth end 32 of the third inductor via V3 is connected to the first electrode P11. The third inductor via V3 forms a third inductor L3 (see FIG. 25). The third inductor via V3 includes a plurality (two in the illustrated example) of via conductors V31, V32 extending in the stacking direction (first direction D1) of the laminate 2. The plurality of via conductors V31, V32 are connected in parallel between the third capacitor electrode PC3 and the first electrode P11. Also, the plurality of via conductors V31, V32 are arranged side by side along the second direction D2.

[0150] (1.6) Inductor pattern portion of the first filter As shown in FIGS. 22 to 24, the first inductor pattern portion PL1 has its first end connected to the first capacitor electrode PC1 and its second end connected to the common terminal T40. The first inductor pattern portion PL1 forms the fourth inductor L4 (see FIG. 25).

[0151] More specifically, the first inductor pattern portion PL1 includes a plurality (two in the illustrated example) of pattern portions P41, P42 and a plurality (three in the illustrated example) of via conductors V41 to V43. The pattern portion P42 is connected to the first capacitor electrode PC1 via the via conductor V41. The pattern portion P41 is connected to the common terminal T40 via the via conductor V42. Also, the pattern portion P41 and the pattern portion P42 are connected by the via conductor V43 and are arranged side by side in the first direction D1. The via conductor V41 corresponds to the first end of the first inductor pattern portion PL1, and the via conductor V42 corresponds to the second end of the first inductor pattern portion PL1. The pattern portion P41 is provided in a state of being wound in a plane in one of the plurality of dielectric layers of the laminate 2 (not shown). The pattern portion P42 is provided in a state of being wound in a plane in one dielectric layer different from the dielectric layer in which the pattern portion P41 is provided among the plurality of dielectric layers of the laminate 2 (not shown).

[0152] The first inductor pattern portion PL1 forms a helical coil. The helical coil is a coil of one turn or more. More preferably, the helical coil is a coil of two turns or more. In the first inductor pattern portion PL1, the distance between the pattern portion P41 and the pattern portion P42, that is, the layer spacing of the helical coil, is, for example, 50 μm or more.

[0153] (1.7) Capacitor electrode of the second filter As shown in FIGS. 22 to 24, the second filter 72B includes a plurality of capacitor electrodes PCH0, namely, a first capacitor electrode PCH1, a second capacitor electrode PCH2, a third capacitor electrode PCH3, a fourth capacitor electrode PCH4, a fifth capacitor electrode PCH5, a sixth capacitor electrode PCH6, and a seventh capacitor electrode PCH7.

[0154] The first capacitor electrode PCH1 has a flat plate shape and is formed in a dielectric layer (not shown) between the first electrode P12 and the second electrode P2 in the first direction D1. The first capacitor electrode PCH1 is arranged at a distance from the second electrode P2 and forms a first capacitor CH1 (see FIG. 25) with the second electrode P2. The first capacitor electrode PCH1 is connected to the first inductor via VH1.

[0155] The second capacitor electrode PCH2 has a flat plate shape and is formed in a dielectric layer (not shown) between the first electrode P12 and the second electrode P2 in the first direction D1. The second capacitor electrode PCH2 is arranged at a distance from the second electrode P2 and forms a second capacitor CH2 (see FIG. 25) with the second electrode P2. The second capacitor electrode PCH2 is connected to the second inductor via VH2.

[0156] The third capacitor electrode PCH3 has a flat plate shape and is formed in a dielectric layer (not shown) between the first electrode P12 and the second electrode P2 in the first direction D1. The third capacitor electrode PCH3 is arranged at a distance from the second electrode P2 and forms a third capacitor CH3 (see FIG. 25) with the second electrode P2. The third capacitor electrode PCH3 is connected to the second terminal T42 via the via conductor VH31.

[0157] The fourth capacitor electrode PCH4 has a flat plate shape and is formed in a dielectric layer (not shown) between the first electrode P12 and the second electrode P2 in the first direction D1. The fourth capacitor electrode PCH4 is arranged at a distance from the second capacitor electrode PCH2 and forms a fourth capacitor CH4 (see FIG. 25) with the second capacitor electrode PCH2.

[0158] The fifth capacitor electrode PCH5 has a flat plate shape and is formed in a dielectric layer (not shown) between the first electrode P12 and the second electrode P2 in the first direction D1. The fifth capacitor electrode PCH5 is disposed spaced apart from the second capacitor electrode PCH2 and forms a fifth capacitor CH5 (see FIG. 25) therebetween with the second capacitor electrode PCH2.

[0159] The sixth capacitor electrode PCH6 has a flat plate shape and is formed in a dielectric layer (not shown) between the first electrode P12 and the second electrode P2 in the first direction D1. The sixth capacitor electrode PCH6 is disposed spaced apart from the fourth capacitor electrode PCH4 and forms a sixth capacitor CH6 (see FIG. 25) therebetween with the fourth capacitor electrode PCH4.

[0160] The seventh capacitor electrode PCH7 has a flat plate shape and is formed in a dielectric layer (not shown) between the first electrode P12 and the second electrode P2 in the first direction D1. The seventh capacitor electrode PCH7 is disposed spaced apart from the first capacitor electrode PCH1 and forms a seventh capacitor CH7 (see FIG. 25) therebetween with the first capacitor electrode PCH1. The seventh capacitor electrode PCH7 is connected to a via conductor VH71.

[0161] (1.8) Inductor vias of the second filter As shown in FIGS. 22 to 24, the second filter 72B includes a plurality of inductor vias VH0, namely, a first inductor via VH1, a second inductor via VH2, a third inductor via VH3, a fourth inductor via VH4, a fifth inductor via VH5, and a sixth inductor via VH6.

[0162] The first inductor via VH1 is connected between the first capacitor electrode PCH1 and the first electrode P12. The first inductor via VH1 forms a first inductor LH1 (see FIG. 25).

[0163] The second inductor via VH2 is connected between the second capacitor electrode PCH2 and the first electrode P12. The second inductor via VH2 forms a second inductor LH2 (see FIG. 25).

[0164] The third inductor via VH3 is connected between the third capacitor electrode PCH3 and the first electrode P12. The third inductor via VH3 forms a third inductor LH3 (see FIG. 25).

[0165] The fourth inductor via VH4 is connected between the first electrode P12 and the second electrode P2. The fourth inductor via VH4 forms a fourth inductor LH4 (see FIG. 25).

[0166] The fifth inductor via VH5 is connected between the first electrode P12 and the second electrode P2. The fifth inductor via VH5 forms a fifth inductor LH5 (see FIG. 25).

[0167] The sixth inductor via VH6 is connected between the first electrode P12 and the second electrode P2. The sixth inductor via VH6 forms a sixth inductor LH6 (see FIG. 25).

[0168] (1.9) Inductor pattern section of the second filter As shown in FIGS. 22 to 24, one end of the inductor pattern section PLH1 is connected to the seventh capacitor electrode PCH7, and the other end is connected to the common terminal T40. The inductor pattern section PLH1 forms a seventh inductor LH7 (see FIG. 25).

[0169] More specifically, the inductor pattern portion PLH1 includes a plurality (two in the illustrated example) of pattern portions PLH11 and PLH12, and a plurality (two in the illustrated example) of via conductors VH71 and VH72. The pattern portion PLH11 is connected to the common terminal T40 via the via conductor V42. The pattern portion PLH12 is connected to the seventh capacitor electrode PCH7 via the via conductor VH71. Further, the pattern portion PLH11 and the pattern portion PLH12 are connected by the via conductor VH72 and are arranged side by side in the first direction D1. The via conductor VH71 corresponds to the first end of the inductor pattern portion PLH1, and the via conductor V42 corresponds to the second end of the inductor pattern portion PLH1. The pattern portion PLH11 is provided in a state of being wound in a plane in one of the plurality of dielectric layers of the laminate 2 (not shown). The pattern portion PLH12 is provided in a state of being wound in a plane in one of the plurality of dielectric layers of the laminate 2, which is different from the dielectric layer in which the pattern portion PLH11 is provided (not shown).

[0170] The inductor pattern portion PLH1 forms a helical coil. The helical coil is a coil having one or more turns. More preferably, the helical coil is a coil having two or more turns. In the inductor pattern portion PLH1, the distance between the pattern portion PLH11 and the pattern portion PLH12, that is, the interlayer distance of the helical coil, is, for example, 50 μm or more.

[0171] (1.10) Arrangement of a plurality of inductor vias in the second filter As shown in FIGS. 22 to 24, in the second filter 72B, the first inductor via VH1 to the third inductor via VH3 are not directly connected to the second electrode P2 which is the ground potential. The first inductor via VH1 is connected to the first capacitor electrode PCH1, the second inductor via VH2 is connected to the second capacitor electrode PCH2, and the third inductor via VH3 is connected to the third capacitor electrode PCH3. The first capacitor electrode PCH1 to the third capacitor electrode PCH3 face the second electrode P2. Such first inductor via VH1 to third inductor via VH3 are called open - end vias. Also, the first inductor LH1 to the third inductor LH3 are called open - end coils. On the other hand, the fourth inductor via VH4 to the sixth inductor via VH6 are directly connected to the second electrode P2 which is the ground potential. Such fourth inductor via VH4 to sixth inductor via VH6 are called short - circuit vias. Also, the fourth inductor LH4 to the sixth inductor LH6 are called short - circuit coils.

[0172] The fourth inductor via VH4 to the sixth inductor via VH6 are arranged in the boundary region 74 between the first filter 71B and the second filter 72B. More specifically, the fourth inductor via VH4 to the sixth inductor via VH6 are arranged closer to the first filter 71B side than the first inductor via VH1 to the third inductor via VH3. Also, the fourth inductor via VH4 to the sixth inductor via VH6 are arranged so as to be aligned along the third direction D3. Here, the boundary region 74 is a region close to the boundary 75 between the first electrode P11 and the first electrode P12 in the second direction D2 among the regions overlapping the first electrode P12 in a plan view from the lamination direction (first direction D1) of the laminate 2.

[0173] Current flows from the first capacitor CH1 to the third capacitor CH3 in the direction of the first inductor LH1 (the first inductor via VH1) to the third inductor LH3 (the third inductor via VH3), and the fourth inductor LH4 (the fourth inductor via VH4) to the sixth inductor LH6 (the sixth inductor via VH6). That is, current flows from the open - end coil (open - end via) to the short - circuit end coil (short - circuit end via). As a result, the current flowing through the fourth inductor via VH4 to the sixth inductor via VH6 and the current flowing through the first inductor via V1 to the third inductor via V3 of the first filter 71B are in opposite directions, so that the deterioration of isolation between the first filter 71B and the second filter 72B can be reduced.

[0174] (2) Circuit configuration of the multiplexer As shown in FIG. 25, the multiplexer 7B according to Embodiment 7 includes a common terminal T40, a first terminal T41, a second terminal T42, a first filter 71B, and a second filter 72B.

[0175] (2.1) Circuit configuration of the first filter The first filter 71B is connected between the common terminal T40 and the first terminal T41. The first filter 71B is a low - pass filter (LPF) that passes signals in a frequency band lower than a predetermined frequency.

[0176] The first filter 71B includes a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a first inductor L1, a second inductor L2, a third inductor L3, and a fourth inductor L4. Note that the description of the configuration similar to that of the LC filter 1 according to Embodiment 1 is omitted.

[0177] (2.2) Circuit configuration of the second filter The second filter 72B is connected between the common terminal T40 and the second terminal T42. The second filter 72B is a band - pass filter or a high - pass filter that passes signals in a frequency band higher than the pass - band of the first filter 71B.

[0178] The second filter 72B includes a first capacitor CH1 (first capacitor for the second filter), a second capacitor CH2 (second capacitor for the second filter), a third capacitor CH3 (third capacitor for the second filter), a fourth capacitor CH4, a fifth capacitor CH5, and a sixth capacitor CH6. The second filter 72B also includes a first inductor LH1 (first inductor for the second filter), a second inductor LH2 (second inductor for the second filter), a third inductor LH3 (third inductor for the second filter), a fourth inductor LH4, a fifth inductor LH5, and a sixth inductor LH6. Further, the second filter 72B includes a seventh inductor LH7 (seventh inductor for the second filter) and a seventh capacitor CH7 (series capacitor for the second filter).

[0179] (2.2.1) First capacitor, first inductor, fourth inductor The first capacitor CH1 is formed between a first capacitor electrode PCH1 and a second electrode P2. The first capacitor CH1 is formed by capacitive coupling between the first capacitor electrode PCH1 and the second electrode P2. The first inductor LH1 is connected between the first capacitor electrode PCH1 and a first electrode P12. The first inductor LH1 corresponds to a first inductor via VH1. The fourth inductor LH4 is connected between the first electrode P12 and the second electrode P2. The fourth inductor LH4 corresponds to a fourth inductor via VH4.

[0180] (2.2.2) Second capacitor, second inductor, fifth inductor The second capacitor CH2 is formed between the second capacitor electrode PCH2 and the second electrode P2. The second capacitor CH2 is formed by the capacitive coupling between the second capacitor electrode PCH2 and the second electrode P2. The second inductor LH2 is connected between the second capacitor electrode PCH2 and the first electrode P12. The second inductor LH2 corresponds to the second inductor via VH2. The fifth inductor LH5 is connected between the first electrode P12 and the second electrode P2. The fifth inductor LH5 corresponds to the fifth inductor via VH5.

[0181] (2.2.3) The third capacitor, the third inductor, the sixth inductor The third capacitor CH3 is formed between the third capacitor electrode PCH3 and the second electrode P2. The third capacitor CH3 is formed by the capacitive coupling between the third capacitor electrode PCH3 and the second electrode P2. The third capacitor CH3 is connected to the second terminal T42. The third inductor LH3 is connected between the third capacitor electrode PCH3 and the first electrode P12. The third inductor LH3 corresponds to the third inductor via VH3. The sixth inductor LH6 is connected between the first electrode P12 and the second electrode P2. The sixth inductor LH6 corresponds to the sixth inductor via VH6.

[0182] (2.2.4) The fourth capacitor, the fifth capacitor, the sixth capacitor The fourth capacitor CH4 is formed between the second capacitor electrode PCH2 and the fourth capacitor electrode PCH4. The fourth capacitor CH4 is formed by the capacitive coupling between the second capacitor electrode PCH2 and the fourth capacitor electrode PCH4.

[0183] The fifth capacitor CH5 is formed between the second capacitor electrode PCH2 and the fifth capacitor electrode PCH5. The fifth capacitor CH5 is formed by the capacitive coupling between the second capacitor electrode PCH2 and the fifth capacitor electrode PCH5.

[0184] The sixth capacitor CH6 is formed between the fourth capacitor electrode PCH4 and the sixth capacitor electrode PCH6. The sixth capacitor CH6 is formed by capacitive coupling between the fourth capacitor electrode PCH4 and the sixth capacitor electrode PCH6.

[0185] (2.2.5) The seventh inductor, the seventh capacitor The seventh inductor LH7 is connected between the common terminal T40 and the seventh capacitor CH7. The seventh inductor LH7 corresponds to the inductor pattern portion PLH1.

[0186] The seventh capacitor CH7 is connected between the seventh capacitor electrode PCH7 and the first capacitor electrode PCH1. The seventh capacitor CH7 is formed by capacitive coupling between the seventh capacitor electrode PCH7 and the first capacitor electrode PCH1. The seventh capacitor CH7 is connected in series with the seventh inductor LH7.

[0187] (3) Effects In the multiplexer 7B according to Embodiment 7, the fourth inductor via VH4 to the sixth inductor via VH6 of the second filter 72B are arranged in the boundary region 74 between the first filter 71B and the second filter 72B. Thereby, deterioration of isolation between the first filter 71B and the second filter 72B can be reduced.

[0188] (Embodiment 8) The multiplexer 7C according to Embodiment 8 is different from the multiplexer 7B (see FIGS. 22 to 24) according to Embodiment 7 in that a plurality of inductor vias VH0 are arranged as shown in FIGS. 26 and 27. For the multiplexer 7C according to Embodiment 8, components similar to those of the multiplexer 7B according to Embodiment 7 are denoted by the same reference numerals and the description thereof is omitted.

[0189] (1) Structure of the multiplexer The multiplexer 7C according to Embodiment 8, similar to the multiplexer 7B according to Embodiment 7, as shown in FIGS. 26 and 27, includes a laminate 2, a plurality of terminals 3, a plurality of first electrodes P11, P12, a plurality of capacitor electrodes PC0, and a plurality of inductor vias VH0. Also, the multiplexer 7C according to Embodiment 8, similar to the multiplexer 7B according to Embodiment 7, as shown in FIGS. 26 and 27, includes a first filter 71C and a second filter 72C.

[0190] (1.1) Inductor vias of the second filter The second filter 72C according to Embodiment 8, similar to the multiplexer 7B according to Embodiment 7 (see FIGS. 22 to 24), as shown in FIGS. 26 and 27, includes, as a plurality of inductor vias VH0, a first inductor via VH1, a second inductor via VH2, a third inductor via VH3, a fourth inductor via VH4, a fifth inductor via VH5, and a sixth inductor via VH6.

[0191] (1.2) Arrangement of a plurality of inductor vias in the second filter As shown in FIGS. 26 and 27, in the second filter 72C of Embodiment 8, similar to Embodiment 7, the first inductor via VH1 to the third inductor via VH3 are not directly connected to the second electrode P2 having a ground potential, but are connected to the first capacitor electrode PCH1 to the third capacitor electrode PCH3, and the first capacitor electrode PCH1 to the third capacitor electrode PCH3 face the second electrode P2. On the other hand, the fourth inductor via VH4 to the sixth inductor via VH6 are directly connected to the second electrode P2 having a ground potential.

[0192] In Embodiment 8, the first to third inductive vias VH1 to VH3 are arranged in a staggered pattern. Also, the fourth to sixth inductive vias VH4 to VH6 are arranged in a staggered pattern. More specifically, the fourth inductive via VH4, the sixth inductive via VH6, and the second inductive via VH2 are arranged in the boundary region 74 between the first filter 71C and the second filter 72C. More specifically, the fourth inductive via VH4, the sixth inductive via VH6, and the second inductive via VH2 are arranged closer to the first filter 71C than the first inductive via VH1, the third inductive via VH3, and the fifth inductive via VH5. Also, the fourth inductive via VH4, the second inductive via VH2, and the sixth inductive via VH6 are arranged to be aligned along the third direction D3.

[0193] (2) Effect Also in the multiplexer 7C according to Embodiment 8, in the boundary region 74 between the first filter 71C and the second filter 72C, there are more short - circuit vias (the fourth inductive via VH4, the sixth inductive via VH6) than open - end vias (the second inductive via VH2). As a result, the currents flowing through the fourth inductive via VH4 and the sixth inductive via VH6 and the currents flowing through the first to third inductive vias V1 to V3 of the first filter 71C are in opposite directions, so that deterioration of isolation between the first filter 71C and the second filter 72C can be reduced.

[0194] (Embodiment 9) The multiplexer 7B (see FIG. 25) according to Embodiment 9 is different from the multiplexer 7B according to Embodiment 7 in that the inductance of the fourth inductor L4 of the first filter 71B and the inductance of the seventh inductor LH7 of the second filter 72B are large. Regarding the multiplexer 7B according to Embodiment 9, components similar to those of the multiplexer 7B according to Embodiment 7 are denoted by the same reference numerals and the description thereof is omitted.

[0195] (1) Circuit Configuration of Multiplexer The multiplexer 7B according to Embodiment 9 includes a first filter 71B and a second filter 72B, similar to the multiplexer 7B according to Embodiment 7.

[0196] The first filter 71B of Embodiment 9 includes a first capacitor C1 to a fifth capacitor C5 and a first inductor L1 to a fourth inductor L4, similar to the first filter 71B of Embodiment 7. Regarding the configuration similar to that of the first filter 71B of Embodiment 7, the description is omitted.

[0197] The second filter 72B of Embodiment 9 includes a first capacitor CH1 to a seventh capacitor CH7 and a first inductor LH1 to a seventh inductor LH7, similar to the second filter 72B of Embodiment 7. Regarding the configuration similar to that of the second filter 72B of Embodiment 7, the description is omitted.

[0198] In the first filter 71B of Embodiment 9, the inductance of the fourth inductor L4 is larger than the inductance of each of the first inductor L1 to the third inductor L3. Since the fourth inductor L4 is formed in the first inductor pattern portion PL1, it is possible to increase the inductance compared to the case where it is formed by an inductor via.

[0199] In the second filter 72B of Embodiment 9, the inductance of the seventh inductor LH7 is larger than the inductance of each of the first inductor LH1 to the sixth inductor LH6. Since the seventh inductor LH7 is formed in the inductor pattern portion PLH1, it is possible to increase the inductance compared to the case where it is formed by an inductor via.

[0200] In the multiplexer 7B according to Embodiment 9, the passing characteristics as shown in FIG. 28 can be obtained. FIG. 28 shows the passing characteristics (solid line S9) of the first filter 71B and the passing characteristics (dashed line S10) of the second filter 72B.

[0201] In the first filter 71B, attenuation is obtained in the stop band on the higher frequency side than the pass band of the first filter 71B. On the other hand, in the second filter 72B, attenuation is obtained in the stop band on the lower frequency side than the pass band of the second filter 72B.

[0202] (2) Effect In the multiplexer 7B according to Embodiment 9, the inductance of the fourth inductor L4 of the first filter 71B is larger than the inductance of each of the first inductor L1 to the third inductor L3. Also, the inductance of the seventh inductor LH7 of the second filter 72B is larger than the inductance of each of the first inductor LH1 to the sixth inductor LH6. Thereby, the characteristics of the multiplexer 7B can be improved.

[0203] (3) Modification As a modification of Embodiment 9, it is not limited to both the inductance of the fourth inductor L4 of the first filter 71B and the inductance of the seventh inductor LH7 of the second filter 72B being large, and only the inductance of the fourth inductor L4 of the first filter 71B may be large. More specifically, the inductance of the fourth inductor L4 is larger than the inductance of each of the first inductor L1 to the third inductor L3. Alternatively, only the inductance of the seventh inductor LH7 of the second filter 72B may be large. More specifically, the inductance of the seventh inductor LH7 is larger than the inductance of each of the first inductor LH1 to the sixth inductor LH6. In short, it is sufficient that the inductance of at least one of the fourth inductor L4 of the first filter 71B and the seventh inductor LH7 of the second filter 72B is large.

[0204] (Embodiment 10) The multiplexer 7B according to Embodiment 10 is different from the multiplexer 7B according to Embodiment 7 in that the seventh inductor LH7 of the second filter 72B is a coil having a plurality of turns (4 turns in the illustrated example) as shown in FIG. 29. For the multiplexer 7B according to Embodiment 10, components similar to those of the multiplexer 7B according to Embodiment 7 are denoted by the same reference numerals and the description thereof is omitted.

[0205] (1) Configuration In the multiplexer 7B according to Embodiment 10, the seventh inductor LH7 of the second filter 72B is a coil having a plurality of turns as shown in FIG. 29. The seventh inductor LH7 has a plurality of (8 in the illustrated example) inductor pattern portions PLH21 and a plurality of (8 in the illustrated example) inductor vias VH73.

[0206] Half of the plurality of inductor pattern portions PLH21 are provided in one dielectric layer (not shown) of the plurality of dielectric layers of the laminate 2. The remaining inductor pattern portions PLH21 are provided in one dielectric layer (not shown) different from the above dielectric layer among the plurality of dielectric layers of the laminate 2.

[0207] The plurality of inductor vias VH73 are provided between the two dielectric layers in which the plurality of inductor pattern portions PLH21 are provided in the stacking direction of the laminate 2. Each inductor via VH73 is connected to two inductor pattern portions PLH21.

[0208] (2) Effects According to the multiplexer 7B according to Embodiment 10, it is easy to increase the inductance of the seventh inductor LH7.

[0209] Note that, as a modification of Embodiment 10, the seventh inductor LH7 of the second filter 72B is not limited to a multi-turn coil, and may be a single-turn coil. In short, the seventh inductor LH7 may be a coil having one or more turns. Thereby, the inductance of the seventh inductor LH7 can be increased as compared with the case where it is constituted by an inductor via.

[0210] The fifth inductor L5 of the first filter 71B may be a multi-turn coil as shown in FIG. 29, or may be a single-turn coil. In short, the fifth inductor L5 of the first filter 71B may be a coil having one or more turns. Thereby, the inductance of the fifth inductor L5 can be increased as compared with the case where it is constituted by an inductor via.

[0211] Also, as another modification of Embodiment 10, the seventh inductor LH7 of the second filter 72B may be a spiral coil as shown in FIG. 30. The seventh inductor LH7 has an inductor pattern portion PLH31. Thereby, the inductance of the seventh inductor LH7 can be increased as compared with the case where it is constituted by an inductor via.

[0212] The fifth inductor L5 of the first filter 71B may be a spiral coil as shown in FIG. 30. Thereby, the inductance of the fifth inductor L5 can be increased as compared with the case where it is constituted by an inductor via.

[0213] (Embodiment 11) The multiplexer 7B (see FIG. 25) according to Embodiment 11 is different from the multiplexer 7B according to Embodiment 7 in that the ratio of inductance to capacitance in the second filter 72B is larger than the ratio of inductance to capacitance in the first filter 71B. Note that, regarding the multiplexer 7B according to Embodiment 11, the same components as those of the multiplexer 7B according to Embodiment 7 are denoted by the same reference numerals and the description thereof is omitted.

[0214] In the multiplexer 7B according to Embodiment 11, the ratio of the inductance of the seventh inductor LH7 to the capacitance of the seventh capacitor CH7 in the second filter 72B is larger than the ratio of the inductance of the fourth inductor L4 to the capacitance of the first capacitor C1 in the first filter 71B. Thereby, the multiplexing between the first filter 71B and the second filter 72B can be achieved well.

[0215] (Embodiment 12) As shown in FIG. 31, the multiplexer 7D according to Embodiment 12 is different from the multiplexer 7B (see FIG. 25) according to Embodiment 9 in that it includes an inductor LA1 and a capacitor CA1. For the components similar to those of the multiplexer 7B according to Embodiment 9 in the multiplexer 7D according to Embodiment 12, the same reference numerals are used and the description thereof is omitted.

[0216] (1) Circuit configuration of the multiplexer As shown in FIG. 31, the multiplexer 7D according to Embodiment 12 includes an inductor LA1 and a capacitor CA1. Also, similar to the multiplexer 7B according to Embodiment 7, the multiplexer 7D includes a first filter 71D and a second filter 72D.

[0217] The inductor LA1 is connected between the common terminal T40 and the branch point T43. The branch point T43 is the branch point of the first filter 71D and the second filter 72D. The inductor LA1 is formed by, for example, an inductor via.

[0218] The capacitor CA1 is connected between the path between the common terminal T40 and the branch point T43 and the ground. More specifically, the capacitor CA1 is connected between the path between the inductor LA1 and the branch point T43 and the path to the ground. The capacitor CA1 is formed by, for example, two capacitor electrodes.

[0219] (2) Effects Also in the multiplexer 7D according to Embodiment 12, similar to the multiplexer 7B according to Embodiment 9, steep attenuation characteristics can be obtained. Thereby, the characteristics of the multiplexer 7B can be improved.

[0220] (3) Modification As a modification of Embodiment 12, the multiplexer 7D may include only the inductor LA1 instead of both the inductor LA1 and the capacitor CA1. Alternatively, the multiplexer 7D may include only the capacitor CA1. In short, the multiplexer 7D only needs to include at least one of an inductor and a capacitor.

[0221] The embodiments and modifications described above are only a part of various embodiments and modifications of the present invention. Also, the embodiments and modifications can be variously changed according to design and the like as long as the object of the present invention can be achieved.

[0222] (Aspect) The following aspects are disclosed in this specification.

[0223] The LC filter (1; 1A; 1B; 1C) according to the first aspect includes a laminate (2), a first input / output port (input terminal T1), a second input / output port (output terminal T2), a first electrode (P1), a second electrode (P2), a first capacitor electrode (PC1), a second capacitor electrode (PC2), a third capacitor electrode (PC3), a first inductor via (V1), a second inductor via (V2), a third inductor via (V3), and a first inductor pattern portion (PL1). The laminate (2) has a plurality of dielectric layers laminated thereon. The first input / output port is provided on the laminate (2). The second input / output port is provided on the laminate (2) and is different from the first input / output port. The first electrode (P1) is a flat electrode provided on the first dielectric layer among the plurality of dielectric layers. The second electrode (P2) is a flat electrode provided on a second dielectric layer different from the first dielectric layer among the plurality of dielectric layers. The first capacitor electrode (PC1) forms a first capacitor (C1) with the second electrode (P2). The second capacitor electrode (PC2) forms a second capacitor (C2) with the second electrode (P2). The third capacitor electrode (PC3) forms a third capacitor (C3) with the second electrode (P2). The first inductor via (V1) has a first end (11) connected to the first capacitor electrode (PC1) and a second end (12) connected to the first electrode (P1), forming a first inductor (L1). The second inductor via (V2) has a third end (21) connected to the second capacitor electrode (PC2) and a fourth end (22) connected to the first electrode (P1), forming a second inductor (L2). The third inductor via (V3) has a fifth end (31) connected to the third capacitor electrode (PC3) and a sixth end (32) connected to the first electrode (P1), forming a third inductor (L3). The first inductor pattern portion (PL1) forms a fourth inductor (L4). The first capacitor electrode (PC1) and the second capacitor electrode (PC2) form a fourth capacitor (C4). The second capacitor electrode (PC2) and the third capacitor electrode (PC3) form a fifth capacitor (C5).The first inductor pattern portion (PL1) has a first end (via conductor V41) connected to at least one of a first electrode (P1), a first inductor via (V1), and a first capacitor electrode (PC1), and a second end (via conductor V42) connected to a first input / output port. The first capacitor electrode (PC1) and the third capacitor electrode (PC3) do not face each other.

[0224] According to the LC filter (1; 1A; 1B; 1C) according to the first aspect, the fourth inductor (L4) formed by the first inductor pattern portion (PL1) can improve the loss with respect to the signal in the passband and improve the attenuation characteristics in the stopband including the high-frequency band.

[0225] In the LC filter (1; 1A; 1B; 1C) according to the second aspect, in the first aspect, the inductance of the first inductor pattern portion (PL1) is larger than the inductance of each of the first inductor via (V1), the second inductor via (V2), and the third inductor via (V3).

[0226] According to the LC filter (1; 1A; 1B; 1C) according to the second aspect, since the high-frequency components can be reduced by the fourth inductor (L4), the attenuation amount in the high-frequency band can be further increased.

[0227] In the LC filter (1; 1A; 1B; 1C) according to the third aspect, in the first or second aspect, the first inductor pattern portion (PL1) is provided in a state of being wound in a plane in at least one of a plurality of dielectric layers.

[0228] According to the LC filter (1; 1A; 1B; 1C) according to the third aspect, the inductance of the fourth inductor (L4) can be easily increased compared to the inductors (the first inductor L1, the second inductor L2, the third inductor L3) formed by the inductor vias (the first inductor via V1, the second inductor via V2, the third inductor via V3).

[0229] In the LC filter (1; 1A; 1B; 1C) according to the fourth aspect, in the third aspect, the first inductor pattern portion (PL1) is provided in a state of being laminated and wound in at least two of the plurality of dielectric layers.

[0230] According to the LC filter (1; 1A; 1B; 1C) according to the fourth aspect, the inductance of the fourth inductor (L4) can be further increased without increasing the planar area of the first inductor pattern portion (PL1).

[0231] The LC filter (1B; 1C) according to the fifth aspect further includes a second inductor pattern portion (PL2) in any one of the first to fourth aspects. The second inductor pattern portion (PL2) forms a fifth inductor (L5). The second inductor pattern portion (PL2) has a third end (via conductor V51) connected to at least one of the first electrode (P1), the third inductor via (V3), and the third capacitor electrode (PC3), and a fourth end (via conductor V53) connected to the second input / output port (output terminal T2).

[0232] According to the LC filter (1B; 1C) according to the fifth aspect, since the high-frequency component can be reduced by the fifth inductor (L5), the attenuation amount in the high-frequency band can be further increased.

[0233] In the LC filter (1B; 1C) according to the sixth aspect, in the fifth aspect, the inductance of the second inductor pattern portion (PL2) is larger than the inductance of each of the first inductor via (V1), the second inductor via (V2), and the third inductor via (V3).

[0234] According to the LC filter (1B; 1C) according to the sixth aspect, since the high-frequency component can be reduced by the fifth inductor (L5), the attenuation amount in the high-frequency band can be further increased.

[0235] In the LC filter (1B; 1C) according to the seventh aspect, in the fifth or sixth aspect, the second inductor pattern portion (PL2) is provided in a state of being wound in a plane in at least one of the plurality of dielectric layers.

[0236] According to the LC filter (1B; 1C) according to the seventh aspect, the inductance of the fifth inductor (L5) can be easily increased as compared with the inductors (the first inductor L1, the second inductor L2, the third inductor L3) formed by the inductor vias (the first inductor via V1, the second inductor via V2, the third inductor via V3).

[0237] In the LC filter (1B; 1C) according to the eighth aspect, in the seventh aspect, the second inductor pattern portion (PL2) is provided in a state of being laminated and wound in at least two of the plurality of dielectric layers.

[0238] According to the LC filter (1B; 1C) according to the eighth aspect, the inductance of the fifth inductor (L5) can be further increased without increasing the planar area of the second inductor pattern portion (PL2).

[0239] In the LC filter (1C) according to the ninth aspect, in any one of the fifth to eighth aspects, the third inductor via (V3) has a first partial via (via conductor V33) and a second partial via (via conductor V34). The first partial via (via conductor V33) is connected to the first electrode (P1) and the second inductor pattern portion (PL2). The second partial via (via conductor V34) is connected to the third capacitor electrode (PC3) and the second inductor pattern portion (PL2).

[0240] In the LC filter (1; 1A; 1B; 1C) according to the tenth aspect, in any one of the first to ninth aspects, the first inductor pattern portion (PL1) is provided between the first electrode (P1) and the second electrode (P2) in the stacking direction of the plurality of dielectric layers in the laminate (2).

[0241] In the LC filter (1; 1A; 1B; 1C) according to the 11th aspect, in the 10th aspect, the first inductor pattern portion (PL1) is provided between the first electrode (P1) and the first capacitor electrode (PC1) in the stacking direction (first direction D1) of the laminate (2).

[0242] In the LC filter (1; 1A; 1B; 1C) according to the 12th aspect, in the 11th aspect, the second capacitor electrode (PC2) has a first portion (PC21) and a second portion (PC22). The first portion (PC21) faces the first capacitor electrode (PC1). The second portion (PC22) faces the third capacitor electrode (PC3). The first inductor pattern portion (PL1) is provided between the first electrode (P1) and the first portion (PC21) of the second capacitor electrode (PC2) in the stacking direction (first direction D1) of the laminate (2).

[0243] In the LC filter (1A) according to the 13th aspect, in any one of the 1st to 12th aspects, the first inductor via (V1) has a first partial via (via conductor V11) and a second partial via (via conductor V12). The first partial via is connected to the first electrode (P1) and the first inductor pattern portion (PL1). The second partial via is connected to the first capacitor electrode (PC1) and the first inductor pattern portion (PL1).

[0244] In the LC filter (1; 1A; 1B; 1C) according to the 14th aspect, in any one of the 1st to 13th aspects, the first capacitor electrode (PC1), the second capacitor electrode (PC2), and the third capacitor electrode (PC3) are provided between the first electrode (P1) and the second electrode (P2) in the stacking direction (first direction D1) of the plurality of dielectric layers in the laminate (2).

[0245] In the LC filter (1; 1A; 1B; 1C) according to the 15th aspect, in any one of the 1st to 14th aspects, each of the first inductor via (V1), the second inductor via (V2), and the third inductor via (V3) includes at least one via conductor. The number of via conductors of each of the second inductor via (V2) and the third inductor via (V3) is larger than the number of via conductors of the first inductor via (V1).

[0246] In the LC filter (1; 1A; 1B; 1C) according to the 16th aspect, in any one of the 1st to 15th aspects, the plurality of dielectric layers are formed of ceramic.

[0247] The LC filter (1; 1A; 1B; 1C) according to the 17th aspect functions as a low-pass filter that passes a signal in a frequency band lower than a specific frequency in any one of the 1st to 16th aspects.

[0248] The multiplexer (7; 7A; 7B; 7C; 7D) according to the 18th aspect includes a first filter (71; 71A; 71B; 71C; 71D) and a second filter (72; 72A; 72B; 72C; 72D). The first filter (71; 71A; 71b; 71C; 71D) includes an LC filter (1; 1A; 1B; 1C) according to any one of the 1st to 17th aspects. The second filter (72; 72A; 72B; 72C; 72D) passes a signal in a frequency band higher than the pass band of the first filter (71; 71A; 71b; 71C; 71D).

[0249] The high-frequency module (8) according to the 19th aspect includes a filter (81) including an LC filter (1; 1A; 1B; 1C) according to any one of the 1st to 17th aspects and an amplifier (82).

[0250] The communication device (9) according to the 20th aspect includes the high-frequency module (8) according to the 19th aspect and a signal processing circuit (92).

[0251] The multiplexer (7B; 7C; 7D) according to the 21st aspect includes a first filter (71B; 71C; 71D), a second filter (72B; 72C; 72D), and a laminate (2). The first filter (71B; 71C; 71D) is a low-pass filter. The second filter (72B; 72C; 72D) passes a signal in a frequency band higher than the passband of the first filter (71B; 71C; 71D). The laminate (2) has a plurality of dielectric layers laminated thereon. The first filter (71B; 71C; 71D) includes a first electrode (P11), a second electrode (P2), a first capacitor electrode (PC1), a second capacitor electrode (PC2), a third capacitor electrode (PC3), a first inductor via (V1), a second inductor via (V2), a third inductor via (V3), and a first inductor pattern portion (PL1). The first electrode (P11) is provided on a first dielectric layer among the plurality of dielectric layers. The second electrode (P2) is provided on a second dielectric layer different from the first dielectric layer among the plurality of dielectric layers and is a ground electrode. The first capacitor electrode (PCH1) forms a first capacitor (CH1) with the second electrode (P2). The second capacitor electrode (PCH2) forms a second capacitor (CH2) with the second electrode (P2). The third capacitor electrode (PCH3) forms a third capacitor (CH3) with the second electrode (P2). The first inductor via (V1) has a first end connected to the first capacitor electrode (PC1) and a second end connected to the first electrode (P11), forming a first inductor (L1). The second inductor via (V2) has a third end connected to the second capacitor electrode (PC2) and a fourth end connected to the first electrode (P11), forming a second inductor (L2). The third inductor via (V3) has a fifth end connected to the third capacitor electrode (PC3) and a sixth end connected to the first electrode (P11), forming a third inductor (L3). The first inductor pattern portion (PL1) forms a fourth inductor (L4).The second filter (72B; 72C; 72D) includes a first electrode for the second filter (first electrode P12), a second electrode for the second filter (second electrode P2), a first capacitor electrode for the second filter (first capacitor electrode PCH1), a second capacitor electrode for the second filter (second capacitor electrode PCH2), a third capacitor electrode for the second filter (third capacitor electrode PCH3), a first inductor via for the second filter (first inductor via VH1), a second inductor via for the second filter (second inductor via VH2), a third inductor via for the second filter (third inductor via VH3), a fourth inductor via for the second filter (fourth inductor via VH4), a fifth inductor via for the second filter (fifth inductor via VH5), and a sixth inductor via for the second filter (sixth inductor via VH6). The first electrode for the second filter is provided on the first dielectric layer among the plurality of dielectric layers. The second electrode for the second filter is provided on a second dielectric layer different from the first dielectric layer among the plurality of dielectric layers and is a ground electrode. The first capacitor electrode for the second filter forms a first capacitor for the second filter (first capacitor CH1) with the second electrode for the second filter. The second capacitor electrode for the second filter forms a second capacitor for the second filter (second capacitor CH2) with the second electrode for the second filter. The third capacitor electrode for the second filter forms a third capacitor for the second filter (third capacitor CH3) with the second electrode for the second filter. The first inductor via for the second filter is connected between the first capacitor electrode for the second filter and the first electrode for the second filter and forms a first inductor for the second filter (first inductor LH1). The second inductor via for the second filter is connected between the second capacitor electrode for the second filter and the first electrode for the second filter and forms a second inductor for the second filter (second inductor LH2). The third inductor via for the second filter is connected between the third capacitor electrode for the second filter and the first electrode for the second filter and forms a third inductor for the second filter (third inductor LH3).The fourth inductor via for the second filter is connected between the first electrode for the second filter and the second electrode for the second filter, and forms a fourth inductor for the second filter (the fourth inductor LH4) that is connected in series with the first inductor for the second filter. The fifth inductor via for the second filter is connected between the first electrode for the second filter and the second electrode for the second filter, and forms a fifth inductor for the second filter (the fifth inductor LH5) that is connected in series with the second inductor for the second filter. The sixth inductor via for the second filter is connected between the first electrode for the second filter and the second electrode for the second filter, and forms a sixth inductor for the second filter (the sixth inductor LH6) that is connected in series with the third inductor for the second filter. At least one of the fourth inductor via for the second filter, the fifth inductor via for the second filter, and the sixth inductor via for the second filter is disposed in the boundary region (74) between the first filter (71B; 71C; 71D) and the second filter (72B; 72C; 72D).

[0252] In the multiplexer (7B; 7D) according to the 22nd aspect, in the 21st aspect, all of the fourth inductor via for the second filter (the fourth inductor via VH4), the fifth inductor via for the second filter (the fifth inductor via VH5), and the sixth inductor via for the second filter (the sixth inductor via VH6) are disposed in the boundary region (74).

[0253] In the multiplexer (7C) according to the 23rd aspect, in the 21st aspect, the plurality of open - end vias are arranged in a staggered pattern. The plurality of open - end vias include the first inductor via (first inductor via VH1) for the second filter, the second inductor via (second inductor via VH2) for the second filter, and the third inductor via (third inductor via VH3) for the second filter. The plurality of short - circuit end vias are arranged in a staggered pattern. The plurality of short - circuit end vias include the fourth inductor via (fourth inductor via VH4) for the second filter, the fifth inductor via (fifth inductor via VH5) for the second filter, and the sixth inductor via (sixth inductor via VH6) for the second filter. In the boundary region (74), there are more short - circuit end vias than open - end vias.

[0254] In the multiplexer (7B; 7C; 7D) according to the 24th aspect, in any one of the 21st to 23rd aspects, the first filter (71B; 71C; 71D) and the second filter (72B; 72C; 72D) are connected to a common ground terminal (GND).

[0255] The multiplexer (7B; 7C; 7D) according to the 25th aspect further includes a common port (common terminal T40) in any one of the 21st to 24th aspects. The common port is provided in the laminate (2). The second filter (72B; 72C; 72D) has a seventh inductor for the second filter (seventh inductor LH7). The seventh inductor for the second filter is connected between the common port and the first capacitor for the second filter (first capacitor CH1). The inductance of the fourth inductor (L4) of the first filter (71B; 71C; 71D) is greater than the inductance of each of the first inductor (L1), the second inductor (L2), and the third inductor (L3). The inductance of the seventh inductor for the second filter (seventh inductor LH7) of the second filter (72B; 72C; 72D) is greater than the inductance of each of the first inductor for the second filter (first inductor LH1), the second inductor for the second filter (second inductor LH2), the third inductor for the second filter (third inductor LH3), the fourth inductor for the second filter (fourth inductor LH4), the fifth inductor for the second filter (fifth inductor LH5), and the sixth inductor for the second filter (sixth inductor LH6).

[0256] In the multiplexer (7B; 7C; 7D) according to the 26th aspect, in the 25th aspect, the second filter (72B; 72C; 72D) further has a series capacitor for the second filter (seventh capacitor CH7). The series capacitor for the second filter is connected between the seventh inductor for the second filter (seventh inductor LH7) and the first capacitor for the second filter (first capacitor CH1).

[0257] In the multiplexer (7B; 7C; 7D) according to the 27th aspect, in the 25th or 26th aspect, at least one of the fourth inductor (L4) of the first filter (71B; 71C; 71D) and the seventh inductor for the second filter (seventh inductor LH7) of the second filter (72B; 72C; 72D) is formed of a helical coil having one or more turns. The interlayer distance of the helical coil is 50 μm or more.

[0258] In the multiplexer (7B; 7C; 7D) according to the 28th aspect, in the 25th or 26th aspect, at least one of the fourth inductor (L4) of the first filter (71B; 71C; 71D) and the seventh inductor for the second filter (seventh inductor LH7) of the second filter (72B; 72C; 72D) is formed of a coil having an inductor via and a pattern portion, or a spiral coil.

[0259] In the multiplexer (7B; 7C; 7D) according to the 29th aspect, in any one of the 25th to 28th aspects, the second filter (72B; 72C; 72D) further includes a series capacitor for the second filter (seventh capacitor CH7). The series capacitor for the second filter is connected between the seventh inductor for the second filter (seventh inductor LH7) and the first capacitor for the second filter (first capacitor CH1). The ratio of the inductance of the seventh inductor for the second filter to the capacitance of the series capacitor for the second filter in the second filter (72B; 72C; 72D) is larger than the ratio of the inductance of the fourth inductor (L4) to the capacitance of the first capacitor (C1) in the first filter (71B; 71C; 71D).

[0260] The multiplexer (7D) according to the 30th aspect further includes at least one of an inductor (LA1) and a capacitor (CA1) in any one of the 25th to 29th aspects. At least one of the inductor (LA1) and the capacitor (CA1) is connected to a path between the branch point (T43) and the common port (common terminal T40). The branch point (T43) is a branch point between the first filter (71D) and the second filter (72D).

Explanation of Reference Numerals

[0261] 1, 1A, 1B, 1C LC filter 2 laminate 201 first main surface 202 second main surface 3 terminal 7, 7A, 7B, 7C, 7D multiplexer 71, 71A, 71B, 71C, 71D First Filter 72, 72A, 72B, 72C, 72D Second Filter 73A Third Filter 74 Boundary Region 75 Boundary 8 High - frequency Module 81 Filter 82 Amplifier 9 Communication Device 91 Antenna 92 Signal Processing Circuit 93 RF Signal Processing Circuit 94 Baseband Signal Processing Circuit PC0 Capacitor Electrode PC1 First Capacitor Electrode PC2 Second Capacitor Electrode PC21 First Portion PC22 Second Portion PC3 Third Capacitor Electrode PCH0 Capacitor Electrode PCH1 First Capacitor Electrode (First Capacitor Electrode for the Second Filter) PCH2 Second Capacitor Electrode (Second Capacitor Electrode for the Second Filter) PCH3 Third Capacitor Electrode (Third Capacitor Electrode for the Second Filter) PCH4 Fourth Capacitor Electrode PCH5 Fifth Capacitor Electrode PCH6 Sixth Capacitor Electrode PCH7 Seventh Capacitor Electrode V0 Inductor Via V1 First Inductor Via V11 Via Conductor (First Portion Via) V12 Via Conductor (Second Portion Via) 11 First Terminal 12 Second Terminal V2 Second Inductor Via V21, V22 Via Conductors 21 Third Terminal 22 Fourth Terminal V3 Third Inductor Via V31, V32 Via Conductors V33 Via Conductor (First Part Via) V34 Via Conductor (Second Part Via) 31 Fifth Terminal 32 Sixth Terminal PL1 First Inductor Pattern Section P41, P42 Pattern Sections P43 Connection Section (First End of First Inductor Pattern Section) V41 Via Conductor (First End of First Inductor Pattern Section) V42 Via Conductor (Second End of First Inductor Pattern Section) V43 Via Conductor PL2 Second Inductor Pattern Section P51, P52 Pattern Sections V51 Via Conductor (Third End of Second Inductor Pattern Section) V52 Via Conductor V53 Via Conductor (Fourth End of Second Inductor Pattern Section) VH0 Inductor Via VH1 First Inductor Via (First Inductor Via for Second Filter) VH2 Second Inductor Via (Second Inductor Via for Second Filter) VH3 Third Inductor Via (Third Inductor Via for Second Filter) VH4 Fourth Inductor Via (Fourth Inductor Via for Second Filter) VH5 Fifth Inductor Via (Fifth Inductor Via for Second Filter) VH6 Sixth Inductor Via (Sixth Inductor Via for Second Filter) PLH1 Inductor Pattern Section PLH11, PLH12 Pattern Sections VH71, VH72 Via Conductors PLH21, PLH31 Inductor Pattern Sections C1 First Capacitor C2 Second Capacitor C3 Third Capacitor C4 Fourth Capacitor C5 Fifth Capacitor CH1 First Capacitor (First Capacitor for Second Filter) CH2 Second Capacitor (Second Capacitor for Second Filter) CH3 Third Capacitor (Third Capacitor for Second Filter) CH4 Fourth Capacitor CH5 Fifth Capacitor CH6 Sixth Capacitor CH7 Seventh Capacitor (Series Capacitor for Second Filter) CA1 Capacitor L1 First Inductor L11, L12 Inductors L2 Second Inductor L3 Third Inductor L31, L32 Inductors L4 Fourth Inductor L5 Fifth Inductor LH1 First Inductor (First Inductor for Second Filter) LH2 Second Inductor (Second Inductor for Second Filter) LH3 Third Inductor (Third Inductor for Second Filter) LH4 Fourth Inductor (Fourth Inductor for Second Filter) LH5 Fifth Inductor (Fifth Inductor for Second Filter) LH6 Sixth Inductor (Sixth Inductor for Second Filter) LH7 Seventh Inductor (Seventh Inductor for Second Filter) LA1 Inductor C10, C20, C30 Capacitors L10, L20, L30 Inductors P1 First Electrode P11 First Electrode P12 First Electrode (Second Electrode for Second Filter) P2 Second Electrode (Second Electrode for Second Filter) T1 Input Terminal (First Input / Output Port) T2 Output Terminal (Second Input / Output Port) T31, T34 Input Terminals T32, T33, T35, T36, T37 Output Terminals T40 Common Terminal (Common Port) T41 First Terminal T42 Second Terminal T43 Branch Point GND Ground Terminal D1 First Direction (Laminating Direction) D2 Second Direction D3 Third Direction S1,S2,S5,S6,S9 Solid Line S3,S4,S7,S8,S10 Dashed Line

Claims

1. a first filter that is a low-pass filter; a second filter that passes signals in a frequency band higher than the pass band of the first filter; a laminate in which a plurality of dielectric layers are laminated; and the first filter includes a first electrode provided on a first dielectric layer among the plurality of dielectric layers; a second electrode that is a ground electrode and is provided on a second dielectric layer different from the first dielectric layer among the plurality of dielectric layers; a first capacitor electrode that forms a first capacitor with the second electrode; a second capacitor electrode that forms a second capacitor with the second electrode; a third capacitor electrode that forms a third capacitor with the second electrode; a first inductor via having a first end connected to the first capacitor electrode and a second end connected to the first electrode, forming a first inductor; a second inductor via having a third end connected to the second capacitor electrode and a fourth end connected to the first electrode, forming a second inductor; a third inductor via having a fifth end connected to the third capacitor electrode and a sixth end connected to the first electrode, forming a third inductor; a first inductor pattern portion that forms a fourth inductor; and the second filter includes a first electrode for the second filter provided on the first dielectric layer among the plurality of dielectric layers; a second electrode for the second filter that is a ground electrode and is provided on a second dielectric layer different from the first dielectric layer among the plurality of dielectric layers; a first capacitor electrode for the second filter that forms a first capacitor for the second filter with the second electrode for the second filter; a second capacitor electrode for the second filter that forms a second capacitor for the second filter with the second electrode for the second filter; a third capacitor electrode for the second filter that forms a third capacitor for the second filter with the second electrode for the second filter; a first inductor via for the second filter connected between the first capacitor electrode for the second filter and the first electrode for the second filter, forming a first inductor for the second filter; a second inductor via for the second filter connected between the second capacitor electrode for the second filter and the first electrode for the second filter, forming a second inductor for the second filter; A third inductor via for the second filter, which is connected between the third capacitor electrode for the second filter and the first electrode for the second filter, and forms a third inductor for the second filter; A fourth inductor via for the second filter, which is connected between the first electrode for the second filter and the second electrode for the second filter, and forms a fourth inductor for the second filter that is connected in series with the first inductor for the second filter; A fifth inductor via for the second filter, which is connected between the first electrode for the second filter and the second electrode for the second filter, and forms a fifth inductor for the second filter that is connected in series with the second inductor for the second filter; A sixth inductor via for the second filter, which is connected between the first electrode for the second filter and the second electrode for the second filter, and forms a sixth inductor for the second filter that is connected in series with the third inductor for the second filter, and has: At least one of the fourth inductor via for the second filter, the fifth inductor via for the second filter, and the sixth inductor via for the second filter is disposed in a boundary region between the first filter and the second filter; Multiplexer.

2. All of the fourth inductor via for the second filter, the fifth inductor via for the second filter, and the sixth inductor via for the second filter are disposed in the boundary region; The multiplexer according to claim 1.

3. A plurality of open-end vias including the first inductor via for the second filter, the second inductor via for the second filter, and the third inductor via for the second filter are arranged in a staggered manner; A plurality of short-circuit end vias including the fourth inductor via for the second filter, the fifth inductor via for the second filter, and the sixth inductor via for the second filter are arranged in a staggered manner; In the boundary region, there are more short-circuit end vias than open-end vias; The multiplexer according to claim 1.

4. The first filter and the second filter are connected to a common ground terminal; The multiplexer according to any one of claims 1 to 3.

5. Further comprising a common port provided in the laminate; The second filter has a seventh inductor for the second filter, which is connected between the common port and the first capacitor for the second filter; The inductance of the fourth inductor of the first filter is greater than the inductance of each of the first inductor, the second inductor, and the third inductor. The inductance of the seventh inductor for the second filter of the second filter is greater than the inductance of each of the first inductor for the second filter, the second inductor for the second filter, the third inductor for the second filter, the fourth inductor for the second filter, the fifth inductor for the second filter, and the sixth inductor for the second filter. The multiplexer according to claim 1.

6. The second filter further includes a series capacitor for the second filter connected between the seventh inductor for the second filter and the first capacitor for the second filter. The multiplexer according to claim 5.

7. At least one of the fourth inductor of the first filter and the seventh inductor for the second filter of the second filter is formed of a helical coil having one or more turns. The interlayer distance of the helical coil is 50 μm or more. The multiplexer according to claim 5 or 6.

8. At least one of the fourth inductor of the first filter and the seventh inductor for the second filter of the second filter is formed of a coil having an inductor via and a pattern portion, or a spiral coil. The multiplexer according to claim 5 or 6.

9. The second filter further includes a series capacitor for the second filter connected between the seventh inductor for the second filter and the first capacitor for the second filter. The ratio of the inductance of the seventh inductor for the second filter to the capacitance of the series capacitor for the second filter in the second filter is greater than the ratio of the inductance of the fourth inductor to the capacitance of the first capacitor in the first filter. The multiplexer according to claim 5 or 6.

10. The multiplexer further includes at least one of an inductor and a capacitor connected to a path between a branch point of the first filter and the second filter and the common port. The multiplexer according to claim 5 or 6.

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