Receiving circuit

Abstract

To provide a receiving circuit, a display device, and an electronic apparatus, capable of reducing variations in a receiving circuit of a differential system.SOLUTION: A receiving circuit 10 for converting a first signal and a second signal imparted in a differential system to a third signal in a single-ended system and outputting it, has an operational amplifier 11, elements 12C, 13C, transistors 17A, 17B, and a circuit 14. The elements 12C, 13C are connected to the circuit 14 through nodes N5, N6 to which the transistors are connected. The first signal and the second signal in which the first signal is inverted, are imparted to the operational amplifier. The operational amplifier imparts an output signal to the elements and a preset electric potential is imparted to the node through the transistor 1. A signal including variations in the operational amplifier is stored in the element by the preset electric potential. The circuit 14 determines an initial value of the third signal without being influenced by the signal including variations in the operational amplifier, by imparting the preset electric potential.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] One aspect of the present invention relates to a receiving circuit, a display device, or an electronic device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The invention disclosed in this specification etc. The technical field of one aspect relates to an article, a method, or a manufacturing method. Or, the present invention relates to a process , a machine, a manufacture, or a composition of matter. . In particular, one aspect of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a storage device, and their driving methods, or their manufacturing methods.

[0003] Note that in this specification etc., a semiconductor device refers to an element, a circuit, or a device etc. that can function by utilizing semiconductor characteristics. As an example, semiconductor elements such as transistors and diodes are semiconductor devices. As another example, a circuit having semiconductor elements is a semiconductor device . As another example, a device including a circuit having semiconductor elements is a semiconductor device .

Background Art

[0004] In recent years, the high definition of display devices has been progressing. The high definition of display devices tends to cause an increase in the number of wirings for transmitting an image signal to the display device, and further an increase in power consumption. Also, when an image signal is transmitted at high speed, electromagnetic interference (EMI) occurs, and noise may affect other peripheral circuits or other electronic devices. Furthermore, electromagnetic susceptibility (EMS) to correctly transmit without being affected by noise generated by signals in the display device or other electronic devices around it ​​​It is required to be equipped with (Magnetic Susceptibility).

[0005] As the high definition of the display device progresses, the signal transmission means to the display device uses two signal lines and expresses the signal "H" or "L" according to which signal has a higher potential by the differential method, and this differential method has become the mainstream. As one of the differential methods, TIA / EIA 644 standard (TIA: Telecommunications Industry Association of the United States, EIA: Electronic Industries Association of the United States) is standardized and LVDS (Low voltage differential signaling ) is often used. LVDS has a differential circuit that operates in the differential method and can reduce power consumption and the influence of noise by using a differential signal with a small amplitude, which is one of the communication technologies with such potential .

[0006] For example, Patent Document 1 discloses a driver circuit used for LVDS

Prior Art Documents

Patent Documents

[0007]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0008] As the display device becomes more high-definition, the number of pixels increases, and as the number of pixels increases, the amount of image signals to be transmitted increases. Therefore, it is required to transmit the image signals at high speed LVDS can remove noise by using a differential input signal using an operational amplifier, suppress the deterioration of the image signals to be transmitted, and suppress the deterioration of the display quality

[0009] However, there was a problem that the image signal was not correctly received due to the variation in the differential amplitude of the differential input signal in the transistors constituting the LVDS receiver circuit. Also, in the provided operational amplifier, when the differential amplitude of the differential input signal becomes less than a certain potential difference, there was a problem that the transmitted image signal deteriorates and is converted into an incorrect image signal. In view of the above problems, one aspect of the present invention aims to provide a receiving circuit with a novel configuration. Or, one aspect of the present invention aims to suppress the degradation of the transmitted signal by suppressing the variation in the electrical characteristics of the receiving circuit. Or, one aspect of the present invention aims to provide a display device with a novel configuration. Or, one aspect of the present invention aims to suppress the degradation of the transmitted image signal by suppressing the variation in the electrical characteristics of the display device.

[0010]

[0011] Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not need to solve all of these problems. Note that other problems will naturally become clear from the descriptions in the specification, drawings, claims, etc., and it is possible to extract these other problems from the descriptions in the specification, drawings, claims, etc.

[0012] Note that the problems of one aspect of the present invention are not limited to the problems listed above. The problems listed above do not prevent the existence of other problems. Note that other problems are the problems not mentioned in this section described below. Problems not mentioned in this section can be derived by those skilled in the art from the descriptions in the specification or drawings, etc., and can be appropriately extracted from these descriptions. ​​​​​​​​​​​​​. Note that one aspect of the present invention solves at least one of the above-listed problems and / or other problems.

Means for Solving the Problems

[0013] One aspect of the present invention is a receiving circuit that converts first and second signals given in a differential manner into a third signal in a single-ended manner and outputs the third signal. The receiving circuit includes an op amp, a first element, a first transistor, and a first circuit. The op amp has a first input terminal, a second input terminal, and a first output terminal. The op amp is electrically connected to the first element. The first element is electrically connected to the first circuit via a first node. One of the source or drain of the first transistor is electrically connected to the first node. The first signal is applied to the first input terminal. The second signal obtained by inverting the first signal is applied to the second input terminal. The op amp supplies the signal output from the first output terminal to the first element. A first preset potential is applied to the first node via the first transistor. A signal including the variation of the op amp is stored in the first element by the first preset potential. The first circuit determines the initial value of the third signal without being affected by the signal including the variation of the op amp when the first preset potential is applied. It is a receiving circuit.

[0014] In the above configuration, it is preferable that the receiving circuit further includes a second element and a second transistor. The second element is electrically connected to the first input terminal of the op amp via a second node. One of the source or drain of the second transistor is electrically connected to the second node. is electrically connected. A first signal is applied to the second element. To the second node, a first program potential is applied via a second transistor. To the second element, the first variation included in the first signal is stored by the first program potential. The operational amplifier outputs a signal including the variation of the operational amplifier to the first output terminal without being affected by the variation included in the first signal when the first program potential is applied.

[0015] In each of the above configurations, it is preferable that the receiving circuit further includes a third element and a third transistor. The operational amplifier further has a second output terminal. The third element is electrically connected to the second input terminal of the operational amplifier via a third node. To the third node, one of the source or drain of the third transistor is electrically connected. A second signal is applied to the third element. To the third node, a second program potential is applied via the third transistor. To the third element, the variation included in the second signal is stored by the second program potential. The operational amplifier outputs a signal including the variation of the operational amplifier to the second output terminal without being affected by the variation included in the second signal when the second program potential is applied.

[0016] In the above configuration, it is preferable that the first element to the third element are capacitive elements.

[0017] In the above configuration, the operational amplifier has a fourth transistor. It is preferable that the semiconductor layers of the first transistor and the fourth transistor each contain the same material.

[0018] In the above configuration, it is preferable that the first transistor has a metal oxide in the semiconductor layer. Shi i.

Advantages of the Invention

[0019] One aspect of the present invention can provide a receiving circuit with a novel configuration. Or, one aspect of the present invention can suppress the degradation of the transmitted signal by suppressing the variation in the electrical characteristics of the receiving circuit. Or, one aspect of the present invention can provide a display device with a novel configuration. Or, one aspect of the present invention can suppress the degradation of the transmitted image signal by suppressing the variation in the electrical characteristics of the display device.

[0020] The effects of one aspect of the present invention are not limited to the effects listed above. The effects listed above do not prevent the existence of other effects. Other effects are those not mentioned in this item described below. Effects not mentioned in this item can be derived by those skilled in the art from the descriptions in the specification or drawings, etc., and can be appropriately extracted from these descriptions. Note that one aspect of the present invention has at least one of the effects listed above and / or other effects. Therefore, one aspect of the present invention may, in some cases, not have the effects listed above.

Brief Description of the Drawings

[0021]

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Embodiments for Carrying Out the Invention

[0022] Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments can be implemented in many different ways, and it is easily understood by those skilled in the art that the form and details can be variously changed without departing from the spirit and its scope. Therefore, the present invention should not be construed as being limited to the description of the following embodiments.

[0023] In the drawings, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. The drawings are schematic illustrations of ideal examples and are not limited to the shapes or values shown in the drawings. There are cases. Thus, it is not necessarily limited to that scale. Note that the drawings are schematic illustrations of ideal examples and are not limited to the shapes or values shown in the drawings.

[0024] Also, the ordinal numbers "first", "second", "third", etc. used in this specification are added to avoid confusion of components, and it is noted that they do not numerically limit. There are cases. Thus, it is not necessarily limited to that scale. Note that the drawings are

[0025] Also, in this specification, terms indicating arrangements such as "above" and "below" are used for convenience in explaining the positional relationship between components with reference to the drawings. Also, the positional relationship between components changes appropriately according to the direction in which each component is depicted. Therefore, it is not limited to the terms described in the specification and can be appropriately rephrased according to the situation. There are cases. Thus, it is not necessarily limited to that scale. Note that the drawings are schematic illustrations of ideal examples and are not limited to the shapes or values shown in the drawings. Therefore, it is not limited to the terms described in the specification and can be appropriately rephrased according to the situation.

[0026] Also, in this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. And there is a channel formation region between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, the channel formation region refers to the region where current mainly flows. And there is a channel formation region between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, the channel formation region refers to the region where current mainly flows. And there is a channel formation region between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, the channel formation region refers to the region where current mainly flows. And there is a channel formation region between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, the channel formation region refers to the region where current mainly flows. And there is a channel formation region between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, the channel formation region refers to the region where current mainly flows. And there is a channel formation region between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, the channel formation region refers to the region where current mainly flows.

[0027] Also, the functions of the source and drain may be interchanged when transistors of different polarities are employed or when the direction of current changes in circuit operation. Therefore, in this specification and the like, the terms source and drain can be used interchangeably. There are cases. Thus, it is not necessarily limited to that scale. Note that the drawings are schematic illustrations of ideal examples and are not limited to the shapes or values shown in the drawings. It follows that

[0028] In addition, in this specification and the like, "electrically connected" includes cases where connection is made through "something having some electrical effect". Here, "something having some electrical effect" is not particularly limited as long as it enables the transfer of electrical signals between the connection targets. For example, "something having some electrical effect" includes electrodes, wiring, switching elements such as transistors, resistive elements, inductors, capacitors, and other elements having various functions.

[0029] In addition, in this specification and the like, "parallel" means a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, cases where the angle is -5° or more and 5° or less are also included. Also, "perpendicular" means a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, cases where the angle is 85° or more and 95° or less are also included.

[0030] In addition, in this specification and the like, the term "film" and the term "layer" can be used interchangeably. For example, the term "conductive layer" may be changed to the term "conductive film". Or, for example, the term "insulating film" may be changed to the term "insulating layer".

[0031] In addition, in this specification and the like, unless otherwise specified, the off-current refers to the drain current when the transistor is in the off state (also referred to as the non-conducting state or the cut-off state). The off state, unless otherwise specified, for an n-channel type transistor, is when the voltage V between the gate and the source When gs is in a state lower than the threshold voltage Vth, for a p-channel transistor, it means a state where the voltage Vgs between the gate and the source is higher than the threshold voltage Vth. For example, the off-current of an n-channel transistor may refer to the drain current when the voltage Vgs between the gate and the source is lower than the threshold voltage Vt h.

[0032] The off-current of a transistor may depend on Vgs. Therefore, when it is said that the off-current of a transistor is I or less, it may mean that there exists a value of Vgs for which the off-current of the transistor becomes I or less. The off-current of a transistor may refer to the off-current in the off-state at a predetermined Vgs, in the off-state at Vgs within a predetermined range, or in the off-state at Vgs where a sufficiently reduced off-current can be obtained, etc.

[0033] As an example, assume an n-channel transistor where the threshold voltage Vth is 0.5V, the drain current at Vgs = 0.5V is 1×10 A, the drain current at Vgs = 0.1V is 1×10 -9 A, the drain current at Vgs = -0.5V is 1×10 -1 3 A, and the drain current at Vgs = -0.8V is 1×10 -19 A. Since the drain current of the transistor is 1×10 A or less at Vgs = -0.5V or in the range of Vgs from -0.5V to -0.8V, it may be said that the off-current of the transistor is 1×10 -22 A or less. -19 -19 -22 since there exists a Vgs for which the drain current of the transistor becomes 1×10 When the off-current of the transistor is 1×10 -22 A or less, it may be said so.

[0034] Also, in this specification and the like, the off-current of a transistor having a channel width W may be expressed as the current value flowing per channel width W. Also, it may be expressed as the current value flowing per a predetermined channel width (for example, 1 μm). In the latter case, the unit of the off-current may be expressed in a unit having a unit of current / length (for example, A / μm).

[0035] The off-current of a transistor may depend on temperature. In this specification, unless otherwise specified, the off-current may represent the off-current at room temperature, 60 °C, 85 °C, 95 °C, or 125 °C. Or, the temperature at which the reliability of a semiconductor device or the like including the transistor is guaranteed, or the temperature at which a semiconductor device or the like including the transistor is used (for example, any one of 5 °C to 35 °C), may represent the off-current. That the off-current of a transistor is I or less means that there exists a value of Vgs such that the off-current of the transistor at room temperature, 60 °C, 85 °C, 95 °C, 125 °C, the temperature at which the reliability of a semiconductor device or the like including the transistor is guaranteed, or the temperature at which a semiconductor device or the like including the transistor is used (for example, any one of 5 °C to 35 °C ) is I or less. ) is I or less.

[0036] The off-current of a transistor may depend on the voltage Vds between the drain and the source . In this specification, unless otherwise specified, the off-current is when Vds is 0.1 V, 0.8 V, 1 V, 1.2 V, 1.8 V, 2.5 V, 3 V, 3.3 V, 10 V, 12 V, 16 V, or It may represent the off-current at 20V. Or, it may represent the off-current at Vds where the reliability of a semiconductor device including the transistor is guaranteed, or the off-current at Vds used in a semiconductor device including the transistor. When the transistor is included in a semiconductor device or the like, the off-current at Vds where the reliability is guaranteed, or the off-current at Vds used in a semiconductor device including the transistor. When the off-current of the transistor is I or less, it may mean that there exists a value of Vgs such that the off-current of the transistor is I or less at Vds of 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5 V, 3V, 3.3V, 10V, 12V, 16V, 20V, at Vds where the reliability of a semiconductor device including the transistor is guaranteed, or at Vds used in a semiconductor device including the transistor. In the description of the off-current above, the drain and source may be read as swapped. That is, the off-current may refer to the current flowing through the source when the transistor is in the off state. In the description of the off-current above, the drain and source may be read as swapped. That is, the off-current may refer to the current flowing through the source when the transistor is in the off state. In the description of the off-current above, the drain and source may be read as swapped. That is, the off-current may refer to the current flowing through the source when the transistor is in the off state.

[0037] In the description of the off-current above, the drain and source may be read as swapped. That is, the off-current may refer to the current flowing through the source when the transistor is in the off state. In the description of the off-current above, the drain and source may be read as swapped. That is, the off-current may refer to the current flowing through the source when the transistor is in the off state.

[0038] Also, in this specification etc., it may be described as leakage current with the same meaning as off-current. Furthermore, in this specification etc., the off-current may refer to, for example, the current flowing between the source and the drain when the transistor is in the off state. In the description of the off-current above, the drain and source may be read as swapped. That is, the off-current may refer to the current flowing through the source when the transistor is in the off state.

[0039] Note that voltage refers to the potential difference between two points, and potential refers to the electrostatic energy (electrical potential energy) possessed by a unit charge in an electrostatic field at a certain point. Generally, the potential difference between the potential at a certain point and the reference potential (e.g., ground potential) is simply called potential or voltage, and potential and voltage are often used synonymously. Therefore, in this specification, unless otherwise specified, potential may be read as voltage. In the description of the off-current above, the drain and source may be read as swapped. That is, the off-current may refer to the current flowing through the source when the transistor is in the off state. Therefore, in this specification, unless otherwise specified, potential may be read as voltage. It is assumed that the voltage may be read as a potential.

[0040] (Embodiment 1) In this embodiment, a receiving circuit that converts a first signal given in a differential method into a second signal of a single-ended method and outputs it will be described with reference to FIGS. 1 to 8. .

[0041] One aspect of the present invention can reduce the offset component of a receiving circuit into which a differential data signal is input. Here, as an example, a receiving circuit that receives a data signal transmitted using LVDS standardized in the TIA / EIA644 standard will be described. However, the method of transmitting a data signal in a differential method is not limited to LVDS. Other differential standards such as ECL (Emitter Coupled Logic), PECL (Positive Emitter Coupled Logic), LVPECL (Low-Voltage Positive Emitter Coupled Logic), RS422 (TIA / EIA422 standard), and RS485 (TIA / EIA485 standard) can also be applied. Positive Emitter Coupled Logic), LVPECL (L ow-Voltage Positive Emitter Coupled Logi c), RS422 (TIA / EIA422 standard), RS485 (TIA / EIA485 standard ).

[0042] One of the electronic devices in which it is preferable to transmit a data signal in a differential method is a display device. The data signal can be rephrased as an image signal given to a pixel. As the display device becomes higher definition, the number of pixels increases, and as the number of pixels increases, the amount of data of the image signal required for display increases. Therefore, it is required to transmit the image signal at high speed. .

[0043] ​​​​​​​Differential method (explained using LVDS as an example of the differential method) In this method, by transmitting the image signal using a differential signal, noise components such as EMI and EMS that are superimposed on the image signal can be reduced. Therefore, LVDS can suppress the deterioration of the display quality by suppressing the deterioration of the transmitted image signal. Note that LVDS has a differential circuit and can suppress the influence of EMI or EMC by using a differential signal with a small amplitude, and can reduce power consumption.

[0044] Here, an electronic device including a receiving circuit according to an aspect of the present invention will be described. For example the electronic device preferably has a control unit and a display device. As an example, the display device has a display controller and a display panel. The display controller has a transmission circuit (transmitter) that transmits a first signal which is an image signal in a differential method to the display device. The display device has a receiving circuit (receiver), a driver circuit, and a display unit. The display unit has a plurality of pixels.

[0045] The transmission circuit is connected to the receiving circuit via a first transmission line and a second transmission line. The first transmission line is electrically connected to the first input terminal of the receiving circuit, and the second transmission line is electrically connected to the second input terminal of the receiving circuit. A first signal is applied to the first transmission line, and a second signal is applied to the second transmission line. The second signal is a signal obtained by inverting the first signal . More specifically, when a signal "H" is applied to the first transmission line, a signal "L" is applied to the second transmission line . Or when a signal "L" is applied to the first transmission line, a signal "H" is applied to the second transmission line . ​

[0046] That is, the transmission circuit transmits the first signal and the second signal in a differential manner, and the receiving circuit has a first input terminal for receiving the first signal and a second input terminal for receiving the second signal. The receiving circuit can convert the first signal and the second signal, which are differential-mode image signals, into a third signal, which is a single-ended mode image signal. The third signal is supplied to the pixel, and the pixel performs display based on the third signal. The receiving circuit has a resistor element, a first circuit, a second circuit, a first input terminal, a second input terminal, and a first output terminal. The first circuit has an operational amplifier, a first transistor, a second transistor, a first element, and a second element. The second circuit has a third transistor, a fourth transistor, a third element, a fourth element, and a third circuit. The operational amplifier has a third input terminal, a fourth input terminal, a second output terminal, and a third output terminal. The third circuit has a fifth input terminal, a sixth input terminal, and a fourth output terminal. The third input terminal is electrically connected to one electrode of the first element and one of the source or drain of the first transistor via the first node. The fourth input terminal is electrically connected to one electrode of the second element and one of the source or drain of the second transistor via the second node. The second output terminal is electrically connected to one electrode of the third element. The third output terminal is electrically connected to one electrode of the fourth element. The fifth input terminal is electrically connected to the other electrode of the third element and the source of the third transistor via the third node.

[0047]

[0048] ​​​​​​​​​​​​​- is electrically connected to one of the source or drain. The sixth input terminal is connected to the fourth node through the other electrode of the fourth element and one of the source or drain of the fourth transistor and is electrically connected.

[0049] The first transmission line is electrically connected to the first element through the first input terminal, and the second transmission line is electrically connected to the second element through the second input terminal. The first transmission line is connected to the second transmission line through a resistive element. Note that the resistive element is preferably arranged near the receiving circuit. That is, the resistive element has a function of terminating the transmission line. Furthermore, the shorter the length of the node connecting the first element and the resistive element, the better, and the shorter the length of the node connecting the second element and the resistive element, the better. Also, the length of the node connecting the first element and the resistive element is preferably equal to the length of the node connecting the second element and the resistive element. When the length of the node connecting the first element and the resistive element is equal to the length of the node connecting the second element and the resistive element, the impedance of the transmission line can be made the same. By making the impedance of the first transmission line and the second transmission line the same for differential signals that operate complementarily, unwanted reflections of the signal can be reduced.

[0050] However, the signal "H" applied to the first input terminal or the signal "L" applied to the second input terminal may contain offset components of the transmission circuit, transmission line, etc. Therefore, it is preferable to reduce the offset components such as those of the transmission line. For example, as a method of reducing the offset components of the transmission line, etc., it is preferable to insulate the first node from the first transmission line. More specifically, the first transmission line uses the first element. This can insulate the first node. The first element is preferably, for example, a capacitive element. As different first elements, transistors with a small off-current may be used. For example, a transistor having an oxide semiconductor in the semiconductor layer of the channel formation region is known to have a small off-current.

[0051] Next, the first circuit will be described. A first program potential is applied to the first node via a first transistor. A second program potential is applied to the second node via a second transistor. The first program potential is a potential that stores the offset component of the first signal applied to the first element. The second program potential is a potential that stores the offset component of the second signal applied to the second element.

[0052] During the period when the first program potential or the second program potential is applied, it is preferable that the display device stops transmitting and receiving the image signal. For example, during the period when the reception of the image signal is stopped, a signal “H” of a fixed potential is applied to the first input terminal, and a signal “L” of a fixed potential is applied to the second input terminal. Or, a signal “L” of a fixed potential may be applied to the first input terminal, and a signal “H” of a fixed potential may be applied to the second input terminal.

[0053] The first transistor and the second transistor are preferably transistors with a small off-current. When a transistor with a small off-current is used, by turning off the transistor, the first node or the second node becomes a floating state. Therefore, the first The variation of the first program potential applied to the node or the second program potential applied to the second node can be suppressed. That is, the frequency of refreshing the first program potential or the second program potential can be reduced. The variation of the first program potential or the second program potential can be suppressed. That is, the frequency of refreshing the first program potential or the second program potential can be reduced. The variation of the first program potential or the second program potential can be suppressed. That is, the frequency of refreshing the first program potential or the second program potential can be reduced.

[0054] The first program potential is applied to the third input terminal via the first transistor. The first element stores the variation included in the first signal by the first program potential. The second program potential is applied to the fourth input terminal via the second transistor. The second element stores the variation included in the second signal by the second program potential. is stored.

[0055] Therefore, the operational amplifier included in the first circuit can output a fourth signal including the variation of the operational amplifier to the second output terminal without being affected by the variation included in the first signal when the first program potential is applied. Therefore, the operational amplifier included in the first circuit can output a fourth signal including the variation of the operational amplifier to the second output terminal without being affected by the variation included in the first signal when the first program potential is applied. The operational amplifier included in the first circuit can output a fifth signal including the variation of the operational amplifier to the third output terminal without being affected by the variation included in the second signal when the second program potential is applied. The operational amplifier included in the first circuit can output a fifth signal including the variation of the operational amplifier to the third output terminal without being affected by the variation included in the second signal when the second program potential is applied. Note that the variation of the operational amplifier may be regarded as the variation of the transistors constituting the operational amplifier. Note that the variation of the operational amplifier may be regarded as the variation of the transistors constituting the operational amplifier.

[0056] In this embodiment, it is preferable that the same potential as the second program potential is applied as the first program potential. The same potential is applied to the first node and the second node, and the variation of the operational amplifier is output to the second output terminal or the third output terminal. The same potential is applied to the first node and the second node, and the variation of the operational amplifier is output to the second output terminal or the third output terminal. When the operational amplifier outputs a single-ended output signal, the fourth signal may be output to the second output terminal. When the operational amplifier outputs a single-ended output signal, the fourth signal may be output to the second output terminal.

[0057] Note that a potential different from the second program potential may be applied as the first program potential. For example, by applying a potential different from the first program potential or the second program potential, the first element stores the influence of the offset component included in the first signal, or the second element stores the influence of the offset component included in the second signal, so that the output of the operational amplifier may be determined by the first program potential or the second program potential. Next, the second circuit will be described. A first preset potential is applied to a third node connecting a third element and a fifth input terminal of the third circuit via a third transistor. The third element stores the variation included in the output signal of the operational amplifier by the first preset potential. A second preset potential is applied to a fourth node connecting a fourth element and a sixth input terminal of the third circuit via a fourth transistor. The fourth element stores the variation included in the output signal of the operational amplifier by the second preset potential. Therefore, the influence of the offset component included in the third signal can be reduced. Note that during the period when the first preset potential or the second preset potential is applied, it is preferable that the display device stops transmitting and receiving the image signal. For example, during the period when the reception of the image signal is stopped, it is preferable that a signal "H" of a fixed potential is applied to the first input terminal and a signal "L" of a fixed potential is applied to the second input terminal.

[0058] Next, the second circuit will be described. A first preset potential is applied to a third node connecting a third element and a fifth input terminal of the third circuit via a third transistor. The third element stores the variation included in the output signal of the operational amplifier by the first preset potential. A second preset potential is applied to a fourth node connecting a fourth element and a sixth input terminal of the third circuit via a fourth transistor. The fourth element stores the variation included in the output signal of the operational amplifier by the second preset potential. A first preset potential is applied to a third node connecting a third element and a fifth input terminal of the third circuit via a third transistor. The third element stores the variation included in the output signal of the operational amplifier by the first preset potential. A second preset potential is applied to a fourth node connecting a fourth element and a sixth input terminal of the third circuit via a fourth transistor. The fourth element stores the variation included in the output signal of the operational amplifier by the second preset potential. Therefore, the influence of the offset component included in the third signal can be reduced. Therefore, the influence of the offset component included in the third signal can be reduced.

[0059] Note that during the period when the first preset potential or the second preset potential is applied, it is preferable that the display device stops transmitting and receiving the image signal. For example, during the period when the reception of the image signal is stopped, it is preferable that a signal "H" of a fixed potential is applied to the first input terminal and a signal "L" of a fixed potential is applied to the second input terminal. For example, during the period when the reception of the image signal is stopped, it is preferable that a signal "H" of a fixed potential is applied to the first input terminal and a signal "L" of a fixed potential is applied to the second input terminal. For example, during the period when the reception of the image signal is stopped, it is preferable that a signal "H" of a fixed potential is applied to the first input terminal and a signal "L" of a fixed potential is applied to the second input terminal.

[0060] In addition, the third transistor and the fourth transistor are transistors with a small off-current. It is preferable to use. When a transistor with a small current in the off state is used, the transistor is turned off, and the third node or the fourth node becomes a floating state. Therefore the fluctuation of the first preset potential applied to the third node or the second preset potential applied to the fourth node can be suppressed. That is, the frequency of refreshing the first preset potential or the second preset potential can be reduced.

[0061] Next, the third circuit will be described. The third circuit converts the differential mode fourth signal and fifth signal generated by the first circuit into a single-ended mode third signal, and can output the third signal from the second output terminal. That is, when the first preset potential is applied to the third node and the second preset potential is applied to the fourth node , the initial value of the third signal is determined by the first preset potential or the second preset potential .

[0062] That is, in the third circuit, the offset components of the fourth signal and the fifth signal are reduced by the third element and the fourth element. Therefore, the third circuit is not affected by the offset components of the fourth signal and the fifth signal. Note that the fourth output terminal of the third circuit preferably has an initial value of either signal “H” or signal “L”.

[0063] In this embodiment, the initial value of the third signal is determined by the first program potential, the second program potential applied to the first circuit, the first preset potential and the second preset potential applied to the second circuit. The first signal received in differential mode and and the second signal is converted into a third signal by a receiving circuit initialized by the first program potential, the second program potential, the first preset potential , and the second preset potential. Therefore, the receiving circuit shown in this embodiment can reduce variations caused by the transmission line or output variations of the operational amplifier included in the receiving circuit. Subsequently, a transceiver circuit that converts and outputs a first signal given in a differential method into a second signal in a single-ended method will be described in detail with reference to the block diagram shown in FIG. 1. In FIG. 1, the case where the control unit 51 transmits a data signal to the control unit 52 via the transceiver circuit 50 will be described. Note that the control unit 52 may be a passive device such as a display panel, a storage device, or a data server. The transceiver circuit 50 includes a transmission circuit 53, a receiving circuit 54, a transmission line 55, a transmission line 56, and a resistance element 57. Note that the resistance element 57 may be included in the receiving circuit 54. The control unit 51 is electrically connected to the transmission circuit 53. The transmission circuit 53 is electrically connected to the receiving circuit 54 via the transmission line 55 and the transmission line 56. The receiving circuit 54 is electrically connected to the control unit 52. The transmission line 55 is electrically connected to the transmission line 56 via the resistance element 57.

[0064] The transmission circuit 53 can transmit the first signal to the receiving circuit 54 in a differential method. The receiving circuit 54 can convert the first signal into a second signal in a single-ended method and provide it to the control unit 52. The receiving circuit 10 will be described in detail with reference to the circuit diagram shown in FIG. 2(A). The receiving circuit 1 The transceiver circuit 50 has a transmission circuit 53, a receiving circuit 54, a transmission line 55, a transmission line 56, and a resistance element 57. The resistance element 57 may be included in the configuration of the receiving circuit 54. The control unit 51 is electrically connected to the transmission circuit 53. The transmission circuit 53 is electrically connected to the receiving circuit 54 via the transmission line 55 and the transmission line 56. The receiving circuit 54 is electrically connected to the control unit 52. The transmission line 55 is electrically connected to the transmission line 56 via the resistance element 57. The transmission circuit 53 can transmit the first signal to the receiving circuit 54 in a differential method. The receiving circuit 54 can convert the first signal into a second signal in a single-ended method and provide it to the control unit 52. The receiving circuit 10 will be described in detail with reference to the circuit diagram shown in FIG. 2(A). The receiving circuit 1

[0065] The transceiver circuit 50 has a transmission circuit 53, a receiving circuit 54, a transmission line 55, a transmission line 56, and a resistance element 57. The resistance element 57 may be included in the configuration of the receiving circuit 54. The control unit 51 is electrically connected to the transmission circuit 53. The transmission circuit 53 is electrically connected to the receiving circuit 54 via the transmission line 55 and the transmission line 56. The receiving circuit 54 is electrically connected to the control unit 52. The transmission line 55 is electrically connected to the transmission line 56 via the resistance element 57. The transmission circuit 53 can transmit the first signal to the receiving circuit 54 in a differential method. The receiving circuit 54 can convert the first signal into a second signal in a single-ended method and provide it to the control unit 52. The receiving circuit 10 will be described in detail with reference to the circuit diagram shown in FIG. 2(A). The receiving circuit 1 The transceiver circuit 50 has a transmission circuit 53, a receiving circuit 54, a transmission line 55, a transmission line 56, and a resistance element 57. The resistance element 57 may be included in the configuration of the receiving circuit 54. The control unit 51 is electrically connected to the transmission circuit 53. The transmission circuit 53 is electrically connected to the receiving circuit 54 via the transmission line 55 and the transmission line 56. The receiving circuit 54 is electrically connected to the control unit 52. The transmission line 55 is electrically connected to the transmission line 56 via the resistance element 57. The transmission circuit 53 can transmit the first signal to the receiving circuit 54 in a differential method. The receiving circuit 54 can convert the first signal into a second signal in a single-ended method and provide it to the control unit 52.

[0066] The transmission circuit 53 can transmit the first signal to the receiving circuit 54 in a differential method. The receiving circuit 54 can convert the first signal into a second signal in a single-ended method and provide it to the control unit 52. The receiving circuit 54 can convert the first signal into a second signal in a single-ended method and provide it to the control unit 52. The receiving circuit 10 will be described in detail with reference to the circuit diagram shown in FIG. 2(A). The receiving circuit 1

[0067] The receiving circuit 10 will be described in detail with reference to the circuit diagram shown in FIG. 2(A). The receiving circuit 1 0 corresponds to the receiving circuit 54 in FIG. 1. The receiving circuit 10 includes a resistance element 18, circuits 20A, 20B, an input terminal INP, an input terminal INM, and an output terminal OUT. Circuit 20A includes an operational amplifier 11, transistors 15A and 15B, an element 12A, and an element 13A. Circuit 20B includes transistors 17A and 17B, an element 12C , an element 13C, and a circuit 14. The operational amplifier 11 has an input terminal 19a, an input terminal 1 9b, an output terminal 19c, and an output terminal 19d. Circuit 14 has an input terminal 19e, an input terminal 19f, and an output terminal 19g.

[0068] The input terminal 19a is electrically connected to one electrode of the element 12A and one of the source or drain of the transistor 15 A via a node N1. The input terminal 19b is electrically connected to one electrode of the element 13A and one of the source or drain of the transistor 15B via a node N2. The output terminal 19c is electrically connected to one electrode of the element 12C . The output terminal 19d is electrically connected to one electrode of the element 13C. The input terminal 1 9e is electrically connected to the other electrode of the element 12C and one of the source or drain of the transistor 17A via a node N5. The input terminal 19f is electrically connected to the other electrode of the element 13C and one of the source or drain of the transistor 17B via a node N6 . The signal line G1 is electrically connected to the gates of the transistors 15A and 15B respectively . The signal line G3 is electrically connected to the gate of the transistor 17A . The signal line G4 is electrically connected to the gate of the transistor 17B.

[0069] ​​The transmission line 55 is electrically connected to the element 12A via the input terminal INP, and the transmission line 56 is , electrically connected to the element 13A via the input terminal INM. The transmission line 55 is electrically connected to the transmission line 56 via the resistance element 1 8. Note that the resistance element 18 is preferably arranged in the vicinity of the operational amplifier 11.

[0070] The signal “H” applied to the input terminal INP or the signal “ L” applied to the input terminal INM may include offset components such as the transmission circuit 53, the transmission line 55, and the transmission line 56 (the transmission lines 55 and 56 may be collectively referred to as the transmission line). Therefore, it is preferable that the offset components of the transmission line and the like are reduced. For example, as a method of reducing the offset components of the transmission line and the like, it is preferable to insulate the node N1 from the transmission line 55. More specifically, the transmission line 55 can insulate the node N1 by using the element 12A. The element 12A can use, for example, a capacitive element. As a different element 12A, a transistor with a small off-current may be used. For example, it is known that a transistor having an oxide semiconductor in the semiconductor layer of the channel formation region has a small off-current.

[0071] Next, the circuit 20A will be described. The program potential Vref1 is applied to the node N1 via the transistor 15A. The program potential Vref2 is applied to the node N2 via the transistor 15B. The program potential Vref1 is a potential including the offset component of the first signal applied to the element 12A. The program potential Vref2 is a potential including the offset component of the second signal applied to the element 13A.

[0072] ​​​​​​​​​​​ During the period when the program potential Vref1 or the program potential Vref2 is applied, it is preferable to stop the transmission and reception of the first signal. For example, during the period when the reception of the first signal is stopped, a fixed-potential signal "H" is applied to the input terminal INP, and a fixed-potential signal "L" is applied to the input terminal INM. Alternatively, a fixed-potential signal "L" may be applied to the input terminal INP, and a fixed-potential signal "H" may be applied to the input terminal INM. .

[0073] Also, it is preferable to use transistors 15A and 15B with a small off-current. When transistors with a small off-current are used, by turning off transistors 15A and 15B, node N1 or node N2 becomes floating. Therefore, fluctuations in the program potential Vref1 applied to node N1 or the program potential Vref2 applied to node N2 can be suppressed. That is, the frequency of refreshing the program potential Vref1 or the program potential Vref2 can be reduced. The program potential Vref1 is applied to the input terminal 19a via the transistor 15A. In the element 12A, the variations included in the first signal are stored by the program potential Vref1. Also, the program potential V ref2 is applied to the input terminal 19b via the transistor 15B. In the element 13A, the variations included in the second signal are stored by the program potential Vref2.

[0074] Therefore, when the program potential Vref1 is applied, the operational amplifier 11 generates the first signal.

[0075] Thus, when the program potential Vref1 is applied, the first ​​​​​​The fourth signal including the variations of the operational amplifier can be output to the output terminal 19c without being affected by the variations included in the signal. Also, when the program potential Vref2 is applied to the operational amplifier 11, the fifth signal including the variations of the operational amplifier can be output to the output terminal 19d without being affected by the variations included in the second signal. In this embodiment, it is preferable that the same potential as the program potential Vref2 is applied as the program potential Vref1. By applying the same potential to the node N1 and the node N2, the variations of the operational amplifier 11 are output to the output terminal 19c or the output terminal 19d. When the operational amplifier 11 outputs a single-ended output signal, the fourth signal may be output to the output terminal 19d. Incidentally, different potentials may be applied as the program potential Vref1 and the program potential Vref2. For example, by applying different potentials to the program potential Vref1 and the program potential Vref2, the element 12A stores the influence of the offset component included in the first signal, and the element 13A stores the influence of the offset component included in the second signal. As described above, the output of the operational amplifier 11 may be determined by the program potential Vref1 or the program potential Vref2. Next, the circuit 20B will be described. A preset potential Vref3 is applied to the node N5 connecting the element 12C and the input terminal 19e of the circuit 14 via the transistor 17A. The output signal of the operational amplifier 11 is input to the element 12C by the preset potential Vref3.

[0076] In this embodiment, it is preferable that the same potential as the program potential Vref2 is applied as the program potential Vref1. By applying the same potential to the node N1 and the node N2, the variations of the operational amplifier 11 are output to the output terminal 19c or the output terminal 19d. Note that when the operational amplifier 11 outputs a single-ended output signal, the fourth signal may be output to the output terminal 19d. Incidentally, different potentials may be applied as the program potential Vref1 and the program potential Vref2. For example, by applying different potentials to the program potential Vref1 and the program potential Vref2, the element 12A stores the influence of the offset component included in the first signal, and the element 13A stores the influence of the offset component included in the second signal.

[0077] As described above, the output of the operational amplifier 11 may be determined by the program potential Vref1 or the program potential Vref2. Next, the circuit 20B will be described. A preset potential Vref3 is applied to the node N5 connecting the element 12C and the input terminal 19e of the circuit 14 via the transistor 17A. The output signal of the operational amplifier 11 is input to the element 12C by the preset potential Vref3. As described above, the output of the operational amplifier 11 may be determined by the program potential Vref1 or the program potential Vref2. Note that when the operational amplifier 11 outputs a single-ended output signal, the fourth signal may be output to the output terminal 19d.

[0078] Next, the circuit 20B will be described. A preset potential Vref3 is applied to the node N5 connecting the element 12C and the input terminal 19e of the circuit 14 via the transistor 17A. The output signal of the operational amplifier 11 is input to the element 12C by the preset potential Vref3. The output signal of the operational amplifier 11 is input to the element 12C by the preset potential Vref3. The variation included is memorized. Also, the element 13C and the input terminal 19f of the circuit 14 are connected to the node N6 to which the preset potential Vref4 is applied via the transistor 17B. The preset potential Vref4 is applied to the node N6 through the transistor 17B. The element 13C memorizes the variation included in the output signal of the operational amplifier 11 by the preset potential Vref4. Therefore, the influence of the offset component included in the third signal can be reduced.

[0079] During the period when the preset potential Vref3 or the preset potential Vref4 is applied, it is preferable to stop the transmission and reception of the first signal. For example, during the period when the reception of the first signal is stopped, a signal "H" of a fixed potential is applied to the input terminal INP, and a signal "L" of a fixed potential is applied to the input terminal INM.

[0080] Also, it is preferable to use transistors with small off-currents for the transistor 17A and the transistor 17B. When transistors with small off-currents are used, the node N5 or the node N6 becomes floating by turning off the transistor 17A or the transistor 17B. Therefore, the variation of the preset potential Vref3 applied to the node N5 or the preset potential Vref4 applied to the node N6 can be suppressed. That is, the frequency of refreshing the preset potential Vref3 or the preset potential Vref4 can be reduced.

[0081] Next, the circuit 14 will be described. The circuit 14 can convert the differential-mode fourth signal and fifth signal generated by the circuit 20A into a single-ended mode third signal and output the third signal to the output terminal OUT. That is, the preset potential is applied to the node N5. ​​​​​​​​​​​​A reference potential Vref3 is applied, and a preset potential Vref4 is applied to node N6. When this is the case, the initial value of the third signal is determined by the preset potential Vref3 or the preset potential Vref4.

[0082] That is, in circuit 20B, the offset components of the fourth and fifth signals are reduced by elements 1 2C and 13C. Therefore, circuit 20B is not affected by the offset components of the fourth and fifth signals. Note that the output terminal 19g of circuit 20B preferably has an initial value that is either signal “H” or signal “L”.

[0083] In this embodiment, the initial value of the third signal is determined by the program potential Vref1, the program potential Vref2 applied to circuit 20A, the preset potential Vref3 applied to circuit 20B, and the preset potential Vref4. The first and second signals received in differential mode are converted into the third signal by the receiving circuit 10 initialized by the program potential Vref1, the program potential Vref 2, the preset potential Vref3, and the preset potential Vref4. That is, the receiving circuit 1 0 shown in this embodiment can reduce variations due to the transmission line or variations in the output of the operational amplifier 11.

[0084] Subsequently, the details of the operational amplifier 11 included in the receiving circuit 10 will be described with reference to the circuit diagram shown in FIG. 2(B). The operational amplifier 11 includes an operational amplifier 11A, an operational amplifier 11B, an element 1 2B, an element 13B, a transistor 16A, and a transistor 16B.

[0085] The input terminal 19a is electrically connected to the input terminal IP1 (not shown in the figure) of the operational amplifier 11A. The input terminal 19b is electrically connected to the input terminal IM1 (not shown in the figure) of the operational amplifier 11A. The output terminal OP1 (not shown in the figure) of the operational amplifier 11A is electrically connected to the element 12B. The output terminal OM1 (not shown in the figure) of the operational amplifier 11A is electrically connected to the element 13B. The element 12B is connected to the input terminal IP2 (not shown in the figure) of the operational amplifier 11 B via the node N3 and to either the source or the drain of the transistor 16A electrically. The element 13B is connected to the input terminal IM2 (not shown in the figure) of the operational amplifier 11B via the node N4 and to either the source or the drain of the transistor 16B electrically. The output terminal OP2 (not shown in the figure) of the operational amplifier 11B is electrically connected to the output terminal 19c. The output terminal OM2 (not shown in the figure) of the operational amplifier 11A is electrically connected to the output terminal 19d. The gates of the transistors 16A and 16B are electrically connected to the signal line G2.

[0086] The program potential Vref1A is applied to the node N3 via the transistor 16A. The program potential Vref2A is applied to the node N4 via the transistor 16B. Note that for the functions of the element 12B, element 13B, transistor 16A, and transistor 16B, reference can be made to the descriptions of the element 12C, element 13C, transistor 17A, and transistor 17B.

[0087] The operational amplifier 11A preferably amplifies the amplitude of the first signal or the second signal. Alternatively, it can be said that the operational amplifier 11A functions as a comparator. The operational amplifier Op-amp 11B preferably has frequency characteristics that allow it to drive the first or second signal amplified in amplitude by op-amp 11A without degrading the frequency components.

[0088] Note that op-amp 11A or op-amp 11B may have an offset component due to variations in the transistors that make up each op-amp. Therefore, it is preferable to cancel the offset component of op-amp 11A or op-amp 11B. Note that as the program potentials Vref1A and Vref2A, it is preferable to apply the same potential as the program potential Vref1. By applying the same potential as the program potential Vref1 to the program potentials Vref1A and Vref2A, the offset component due to variations in op-amp 11B is applied to elements 12C and 13C. Note that op-amp 11A and op-amp 11B may be composed of a single op-amp.

[0089] Using the circuit diagram of the receiving circuit 10 shown in Fig. 3(A), a detailed description of elements 12A to 12C and elements 13A to 13C will be given. In the example shown in Fig. 3(A), elements 12A to 12C and elements 13A to 13C are composed of capacitive elements. By using capacitive elements, nodes N1 to N6 can be easily made to float. Note that elements 12A to 12C and elements 13A to 13C may use transistors with a small off-current. An example using transistors with a small off-current will be described in detail in Fig. 5(A).

[0090] Next, the circuit 14 included in the reception circuit 10 will be described in detail with reference to the circuit diagram shown in FIG. 3(B). The circuit 14 includes an input terminal 19e, an input terminal 19f, an output terminal 19g, a circuit 1 4A, a circuit 14B, and a circuit 14C. The circuit 14A includes a transistor 21A and a t ransistor 21B. The circuit 14B includes a transistor 22A, a transistor 22B , a transistor 23A, a transistor 23B, and a capacitive element 23C. The circuit 14C includes a transistor 24A, a transistor 24B, a transistor 24C, and a capacitive element 24 D. The input terminal 19e is electrically connected to the gate of the transistor 21A. The input terminal 19f is electrically connected to the gate of the transistor 21B.

[0091] One of the source or drain of the transistor 21A is electrically connected to one of the source or drain of the transistor 21B, the gate of the transistor 22B, and the gate of the transistor 23B. The other of the source or drain of the transistor 21A is electrically connected to the power supply line V1. The other of the source or drain of the transistor 21B is electrically connected to the power supply line V6.

[0092] One of the source or drain of the transistor 22A is electrically connected to one of the source or drain of the transistor 22B, the gate of the transistor 23A, and one of the electrodes of the capacitive element 23C. The gate of the transistor 22A is electrically connected to the other of the source or drain of the transistor 22A and the power supply line V2. The other of the electrodes of the capacitive element 23C is electrically connected to one of the source or drain of the transistor 23A, one of the source or drain of the transistor 23B, and the gate of the transistor 24B. One of the source or drain of the transistor 23A ​​ Or the other of the drains is electrically connected to the power line V3. The source or the other of the drains is electrically connected to the power line V6. The source or the other of the drains is electrically connected to the power line V6.

[0093] One of the source or drain of the transistor 24B is electrically connected to one of the source or drain of the transistor 24A, one of the electrodes of the capacitor element 24D, and the output terminal 19g. . The gate of the transistor 24A is electrically connected to the other of the electrodes of the capacitor element 24D and one of the source or drain of the transistor 24C. The other of the source or drain of the transistor 24A is electrically connected to the power line V5. The other of the source or drain of the transistor 24C is electrically connected to the gate of the transistor 24C and the power line V4. The other of the source or drain of the transistor 24B is electrically connected to the power line V6.

[0094] A signal after the offset component included in the fourth signal or the fifth signal is removed is provided to the circuit 14. Note that the fourth signal or the fifth signal provided to the circuit 14 is a differential signal. The circuit 14A functions as a switching circuit for converting the differential fourth signal or fifth signal into a single-ended sixth signal. The potential applied to the power line V1 is preferably made larger than the potential width of the output potential of the operational amplifier 11. The potential applied to the power line V6 is preferably the reference potential of the circuit 14. For example, the potential applied to the power line V6 can be the ground potential. .

[0095] Circuit 14B functions as a level shifter circuit. The potential applied to the power supply line V2 is preferably the highest among the potentials applied to circuit 14. Therefore, the amplitude of the sixth signal can be increased. Transistor 22A is a diode-connected transistor, and the current supply capacity of transistor 22A determines the switching speed of transistor 23A. The potential applied to the power supply line V3 is preferably equal to the potential applied to the power supply line V5 described later. Note that the potential applied to the gate of transistor 23A is boosted by a bootstrap using the capacitor element 23C. Therefore, the current supply capacity of transistor 23A increases. Circuit 14C functions as a buffer circuit. The power supply line V5 determines the magnitude of the potential when circuit 14C outputs a signal "H" to the output terminal 19g. Transistor 24C is a diode-connected transistor, and the current supply capacity of transistor 24C determines the switching speed of transistor 24A. The potential applied to the gate of transistor 24A is boosted by a bootstrap using the capacitor element 24D. Therefore, the current supply capacity of transistor 24A increases. Note that the potential applied to the power supply line V4 is preferably greater than the potential applied to the power supply line V5. Alternatively, the potential applied to the power supply line V4 may be the same as the potentials applied to the power supply line V3 and the power supply line V5. By making them the same potential, the types of power supplies used can be reduced. The magnitude of the potential applied to the power supply line connected to circuit 14 is preferably such that the potential applied to the power supply line V1 is the smallest and the potential applied to the power supply line V5 is the largest.

[0096] ​​​​​​​​​​​​​​​​​

[0097] As an example, the operational amplifier 11A will be described in detail using the circuit diagram shown in FIG. 4. The operational amplifier 11A has an input terminal 11A1, an input terminal 11A2, an output terminal 11A3, and an output terminal 11A4.

[0098] The operational amplifier 11A includes transistors 31 to 37, a capacitive element 38, and a capacitive element 39. One of the source or drain of transistor 31 is electrically connected to the power supply line V7 and one of the source or drain of transistor 32. The other of the source or drain of transistor 31 is electrically connected to one of the source or drain of transistor 33, one of the electrodes of the capacitive element 38, and the output terminal 11A4. The other of the source or drain of transistor 32 is electrically connected to one of the source or drain of transistor 34, one of the electrodes of the capacitive element 39, and the output terminal 11A3.

[0099] The other of the source or drain of transistor 33 is electrically connected to one of the source or drain of transistor 35 and the other of the source or drain of transistor 34. The other of the source or drain of transistor 35 is electrically connected to the power supply line V8. The gate of transistor 33 is electrically connected to the input terminal 11A1. The gate of transistor 34 is electrically connected to the input terminal 11A2.

[0100] One of the source or drain of transistor 36 is electrically connected to the gate of transistor 31 and the other of the electrodes of the capacitive element 38. The other of the source or drain of transistor 36 is electrically connected to the power supply line V3. One of the source or drain of transistor 37 The transistor 32 is electrically connected to the gate of the capacitor 39. The other of the source and drain of the transistor 37 is electrically connected to the power supply line V3. The gate of the transistor 35 is electrically connected to the power supply line VBIAS. The gate of the transistor 37 is electrically connected to a signal line G5.

[0101] A signal applied to signal line G5 turns on transistor 36, The potential of the power supply line V3 is applied to the gate of the transistor 31 via the transistor 36. A signal applied to the signal line G5 turns on the transistor 37, and the transistor The potential of the power supply line V3 is applied to the gate of the transistor 32 via the transistor 37. The gate of the transistor 31 and the gate of the transistor 32 are driven by a signal applied to a signal line G5. As a result, the transistors 36 and 37 are turned off, resulting in a floating state. 3B, the potential applied to the power supply line V8 is smaller than the potential applied to the power supply line V6 in FIG. It is preferably an electric potential.

[0102] The capacitor 38 and the capacitor 39 have a bootstrap function. , and the potential of the gate of the transistor 32 is raised, This has the effect of increasing the current supply capability of the transistor 32. or transistor 32 outputs to output terminal 11A3 or output terminal 11A4, respectively. It acts as a current source for the signal.

[0103] The receiving circuit 10A will be described in detail with reference to the circuit diagram shown in FIG. 10A includes transistor 19A, transistor 19B, operational amplifier 11B1, and circuit 1 The difference from FIG. 3(A) is that it has 4D. Here, the receiving circuit described in FIG. 3(A) will be described in terms of the differences.

[0104] In FIG. 5(A), node N1 or node N2 can be put in a floating state using transistor 19A and transistor 19B. In this case, it is preferable to use a transistor with a small off-current. The transistor can be a transistor having an oxide semiconductor in the semiconductor layer of the channel formation region. Note that the gates of transistor 19A and transistor 19B are preferably controlled to be in an on state or an off state by a signal applied to signal line G6.

[0105] Next, operational amplifier 11B1 will be described. The difference of operational amplifier 11B1 is that it outputs a single-ended type signal. Compared with the differential type output, it has the effect of reducing transistor 17A, element 12C, and wiring, etc.

[0106] Next, circuit 14D will be described in detail with reference to the circuit diagram of FIG. 5(B). The difference between circuit 14D and FIG. 3(B) is that circuit 14D has circuit 14C1. Circuit 14C1 includes input terminal 19 h, transistor 24E, transistor 24F, transistor 24G, and capacitor element 24 H.

[0107] Input terminal 19h is electrically connected to the gate of transistor 24F. One of the source or drain of transistor 24F is connected to one of the source or drain of transistor 24E. On the other hand, one of the electrodes of the capacitor 24H, the gate of the transistor 22B, and the gate of the transistor 23 The gate of the transistor 24E is electrically connected to the gate of the transistor 24G. One of the source and drain is electrically connected to the other electrode of the capacitor element 24H. The other of the source and drain of the transistor 24E is electrically connected to the power supply line V5A. The other of the source and drain of the transistor 24G is electrically connected to the power supply line V4A. The other of the source or the drain of the transistor 24F is electrically connected to a power supply line V6.

[0108] The circuit 14C1 functions as a buffer circuit similar to the circuit 14C. The potential of the signal "H" applied to the gate of the transistor 22B and the gate of the transistor 23B Transistor 24G is a diode-connected transistor. The current supply capability of transistor 24G determines the switching speed of transistor 24E. The capacitance element 24H has a bootstrap function and is connected to the gate of the transistor 24E. By raising the potential applied to the transistor 24E, the current supply capability of the transistor 24E is increased. The gate of the transistor 22B and the gate of the transistor 23B are charged and discharged. The potential applied to the power supply line V4A can be increased by 100% compared to the potential applied to the power supply line V5A. It is preferable that the potential applied to the power supply lines V4A and V5A is larger than that applied to the power supply lines V5A and V6A. By making the potentials the same, it is possible to reduce the number of types of power sources used. can.

[0109] In addition, the operational amplifier 11B1 constituting the receiving circuit 10A or the multiple The transistor preferably has an oxide semiconductor in the semiconductor layer of the channel formation region. It is preferably used.

[0110] Regarding the operation of the reception circuit 10 described with reference to FIG. 3(A), it will be described using the timing chart shown in FIG. 6. It is used for explanation.

[0111] At time T0, a signal “H” is applied to the input terminal INP, a signal “L” is applied to the input terminal INM, a signal “H” is applied to the signal line G 1, a signal “H” is applied to the signal line G2, a signal “H” is applied to the signal line G3, a signal “H” is applied to the signal line G4, and a signal “H” and a signal “L” are applied to the signal line G5. For example, the potential of the signal “H” applied to the signal line G1 is preferably equal to or higher than the potential of the power supply line V2. The potential of the signal “H” applied to the signal line G2 is preferably equal to or higher than the potential of the power supply line V3. The potential of the signal “H” applied to the signal line G3 is preferably equal to or higher than the potential of the power supply line V4. The potential of the signal “H” applied to the signal line G4 is preferably equal to or higher than the potential of the power supply line V3. The potential of the signal “H” applied to the signal line G 5 is preferably equal to the potential of the power supply line V6. The potential of the signal “H” applied to the signal line G2 is preferably equal to or higher than the potential of the power supply line V3. The potential of the signal “H” applied to the signal line G3 is preferably equal to or higher than the potential of the power supply line V4. The potential of the signal “H” applied to the signal line G4 is preferably equal to or higher than the potential of the power supply line V3. The potential of the signal “H” applied to the signal line G 5 is preferably equal to the potential of the power supply line V6. The potential of the signal “H” applied to the signal line G4 is preferably equal to or higher than the potential of the power supply line V3. The potential of the signal “H” applied to the signal line G 5 is preferably equal to the potential of the power supply line V6.

[0112] The signals applied to the input terminal INP and the input terminal INM are preferably potentials conforming to the differential system standard. For example, in the case of LVDS, when a potential of 1.4V is applied to the input terminal INP, 1.05V is applied to the input terminal INM. Or when a potential of 1.05V is applied to the input terminal INP, 1.4V is applied to the input terminal INM. is applied. When a potential of 1.05V is applied to the input terminal INP, 1.4V is applied to the input terminal INM. is applied.

[0113] For example, the program potential Vref1 applied to the node N1 is applied with reference to the power supply line V6 by the signal applied to the signal line G1 or the signal line G2, and is applied to the node N2 is applied. The program potential Vref2 to be applied is given with reference to the power supply line V6 and applied to the node N3. The program potential Vref1A to be applied is given with reference to the power supply line V6 and applied to the node N4. The program potential Vref2A to be applied to the node N4 is preferably given with reference to the power supply line V6. In FIG. 6, an example is shown in which the same potential as the program potential Vref1 is applied as the program potential Vref2, Vref1A, and Vref2A. In FIG. 6, an example is shown in which the same potential as the program potential Vref1 is applied as the program potential Vref2, Vref1A, and Vref2A. ref2, Vref1A, and Vref2A.

[0114] At time T1, a signal "H" is applied to the signal line G5. The magnitude of the signal applied to the signal line G5 is preferably greater than that of the power supply line V3. When the signal "H" is applied to the signal line G5, the transistors 36 and 37 are turned on, and the gates of the transistors 31 and 32 are supplied with the potential of the power supply line V3. When the signal "H" is applied to the signal line G5, the transistors 36 and 37 are turned on, and the gates of the transistors 31 and 32 are supplied with the potential of the power supply line V3. When the signal "H" is applied to the signal line G5, the transistors 36 and 37 are turned on, and the gates of the transistors 31 and 32 are supplied with the potential of the power supply line V3. The gates of the transistors 31 and 32 are supplied with the potential of the power supply line V3.

[0115] At time T2, a signal "L" is applied to the signal line G1, a signal "L" is applied to the signal line G2, a signal "L" is applied to the signal line G3, a signal "L" is applied to the signal line G4, and a signal "L" is applied to the signal line G5. The magnitude of the signals applied to the signal lines G1 to G5 is preferably the same as the potential applied to the power supply line V6. When the signal "L" is applied to the signal line G5, the transistors 36 and 37 are turned off, and the gates of the transistors 31 and 32 are in a floating state and hold the potential applied to the power supply line V3. Therefore, the transistor 31 or the transistor 32 functions as a current source for the output signal output to the output terminal 11A3 or the output terminal 11A4. The potential applied to the gate of the transistor 31 or the gate of the transistor 32 is a capacitive element. When the signal "L" is applied to the signal line G5, the transistors 36 and 37 are turned off, and the gates of the transistors 31 and 32 are in a floating state and hold the potential applied to the power supply line V3. When the signal "L" is applied to the signal line G5, the transistors 36 and 37 are turned off, and the gates of the transistors 31 and 32 are in a floating state and hold the potential applied to the power supply line V3. When the signal "L" is applied to the signal line G5, the transistors 36 and 37 are turned off, and the gates of the transistors 31 and 32 are in a floating state and hold the potential applied to the power supply line V3. When the signal "L" is applied to the signal line G5, the transistors 36 and 37 are turned off, and the gates of the transistors 31 and 32 are in a floating state and hold the potential applied to the power supply line V3. When the signal "L" is applied to the signal line G5, the transistors 36 and 37 are turned off, and the gates of the transistors 31 and 32 are in a floating state and hold the potential applied to the power supply line V3. Therefore, the transistor 31 or the transistor 32 functions as a current source for the output signal output to the output terminal 11A3 or the output terminal 11A4. The potential applied to the gate of the transistor 31 or the gate of the transistor 32 is a capacitive element. Therefore, the transistor 31 or the transistor 32 functions as a current source for the output signal output to the output terminal 11A3 or the output terminal 11A4. The potential applied to the gate of the transistor 31 or the gate of the transistor 32 is a capacitive element. It is lifted by bootstrap using the capacitor 38 or the capacitive element 39. Therefore, the current supply capacity of the transistor 31 or the transistor 32 increases.

[0116] At time T3, a signal "L" is applied to the input terminal INP, and further, a signal "H" is applied to the input terminal INM. A signal "L" is output to the output terminal OUT.

[0117] At time T4, a signal "H" is applied to the input terminal INP, and further, a signal "L" is applied to the input terminal INM. A signal "H" is output to the output terminal OUT.

[0118] After time T5, the output terminal OUT is determined by the signal applied to the input terminal INP or the input terminal INM.

[0119] The receiving circuit 10 can cancel the variations or offset components of the receiving circuit 10. Therefore, the first signal or the second signal received in the differential method is correctly converted into the third signal in the single-ended method.

[0120] In FIG. 7, the electronic device having the receiving circuit of the present embodiment will be described in detail. The electronic device 100 preferably has a control unit 101 and a display device 110. The control unit 101 preferably has a processor 102, a communication circuit 103, an input / output circuit 104, a storage 105, and a memory 106 and the like. The communication circuit 103 preferably has functions of wired communication and wireless communication. Further, the input / output circuit 104 has sensors (force, displacement, position, speed, acceleration, angular velocity, revolution speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, electric (including functions for measuring force, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays) and may have an image sensor, a keyboard, etc.

[0121] The display device 110 includes a display controller 111 and a display panel 121. . The display controller 111 includes a control unit 112, a frame memory 113, and a driver circuit 114. The control unit 112 includes an arithmetic unit 112A and a timing generation circuit 1 12B. The driver circuit 114 includes a plurality of transmission circuits 53.

[0122] The display panel 121 includes a source driver circuit 122, a gate driver circuit 123, and a display unit 124. The source driver circuit 122 includes a plurality of reception circuits 54. Note that the reception circuit 54 corresponds to the reception circuit 10 described in this embodiment. The display unit 124 includes a plurality of pixels 124A.

[0123] The image signal stored in the frame memory 113 is transmitted by the display controller 111 to the reception circuit 54 using the transmission circuit 53. Note that the image signal is transmitted after being converted into a first differential signal by the transmission circuit 53.

[0124] The reception circuit 54 can convert the first signal or the second signal received in differential form into a third signal in single-ended form. The source driver circuit 122 can convert the third signal into an analog signal. The pixels selected by the gate driver circuit 123 are supplied with the third signal, and the pixels can perform display according to the third signal.

[0125] Regarding the pixel 124A included in the display unit 124 of the display panel 121, a circuit diagram shown in FIG. 8(A) will be used to explain it in detail. The pixel 124A is connected to a signal line G1, a signal line G2, a signal line G3, a wiring S1, a wiring MN1, a wiring Ano, and a wiring Cath. The pixel 124A has a transistor 41, a transistor 42, a transistor 43, a transistor 44, a capacitor element 45, a capacitor element 46, and a light-emitting element 47. Note that the pixel 124A may have a configuration that does not include the transistor 44 and the capacitor element 46.

[0126] The gate of the transistor 41 is electrically connected to the signal line G1. One of the source or drain of the transistor 41 is electrically connected to the wiring S1. The other of the source or drain of the transistor 41 is electrically connected to the gate of the transistor 42, one of the electrodes of the capacitor element 45, and one of the electrodes of the capacitor element 46.

[0127] One of the source or drain of the transistor 42 is electrically connected to one of the electrodes of the light-emitting element 47, one of the source or drain of the transistor 43, and the other of the electrodes of the capacitor element 45. The other of the source or drain of the transistor 42 is electrically connected to the wiring Ano. The other of the electrodes of the light-emitting element 47 is electrically connected to the wiring Cath. The other of the source or drain of the transistor 43 is electrically connected to the wiring MN1.

[0128] The gate of the transistor 44 is electrically connected to the signal line G3. One of the source or drain of the transistor 44 is electrically connected to the wiring S1. The other of the source or drain of the transistor 44 is electrically connected to the other of the electrodes of the capacitor element 46.

[0129] Node FN1 indicates a wiring to which one of the gates of transistor 42, one of the electrodes of capacitor element 45, and one of the electrodes of capacitor element 46 are connected. Node FN2 indicates a wiring to which the other of the source or drain of transistor 44 and the other of the electrodes of capacitor element 46 are connected. Pixel 124A is supplied with different scanning signals from gate driver circuit 123 via signal lines G1, G2, and G3. Also, pixel 124A is supplied with an image signal via wiring S1. Also, pixel 124A can monitor, as an observation signal, the current flowing through pixel 124A via wiring MN1. Note that the observation signal is either the current flowing through transistor 43 or the current flowing through light-emitting element 47. Regarding pixel 124B, it will be described in detail using the circuit diagram shown in FIG. 8(B). Here, differences from pixel 124A described in FIG. 8(A) will be described. Pixel 124B is different in that any one or more of transistor 41, transistor 42, transistor 43, or transistor 44 have a back gate. Note that FIG. 8(B) shows an example in which all transistors have a back gate. By having a back gate in the transistor, the on-current can be increased. Also, the threshold value of the transistor can be controlled.

[0130] It is preferable that display panel 121, gate driver circuit 123, display unit 124, and the operational amplifier 11 constituting reception circuit 10 included in source driver circuit, or a plurality of transistors constituting circuit 14 are formed on the same substrate.

[0131]

[0132]

[0133] ​​​​​​​​​​​​​​ Note that the transistor preferably has an oxide semiconductor in the semiconductor layer of the channel formation region. Such a transistor can reduce the off-current. Therefore, the holding time of a program potential, a preset potential, or an image signal or the like can be lengthened. Thus, since the frequency of the refresh operation can be decreased, it has the effect of reducing power consumption. The transistor having an oxide semiconductor in the semiconductor layer will be described in detail in Embodiment 5.

[0134] Alternatively, silicon may be used for the semiconductor layer of the channel formation region of the transistor. Although amorphous silicon may be used as the silicon, it is particularly preferable to use silicon having crystallinity. For example, microcrystalline silicon, polycrystalline silicon, single-crystalline silicon, or the like is preferably used. In particular, polycrystalline silicon can be formed at a lower temperature than single-crystalline silicon, and has a higher field-effect mobility and higher reliability than amorphous silicon.

[0135] As described above, the configurations and methods shown in this embodiment can be used in appropriate combination with the configurations and methods shown in other embodiments.

[0136] (Embodiment 2) In this embodiment, a configuration example of a display device using a liquid crystal element and a configuration example of a display device using a light-emitting element will be described. Note that in this embodiment, descriptions of the elements, operations, and functions of the display device described in Embodiment 1 are omitted.

[0137] The display device described in this embodiment can use the reception circuit described in Embodiment 1. Note that the scanning line driving circuit described below is a gate driver circuit, a signal line driving circuit ​​corresponds to a source driver circuit. This is a diagram.

[0138] In FIG. 9A, a display portion 215 provided on a first substrate 4001 is surrounded by a A sealant 4005 is provided, and the display portion 215 is disposed between the sealant 4005 and the second substrate 40. It is sealed by 06.

[0139] In FIG. 9A, a scanning line driving circuit 221a, a signal line driving circuit 231a, and a signal line driving circuit 232a and the common line driver circuit 241a are provided on a printed circuit board 4041. The integrated circuits 4042 are made of a single crystal semiconductor or a polycrystalline semiconductor. The common line driving circuit 241a is formed of the wirings Ano and C shown in the first embodiment. It has the function of supplying a specified potential to ath, etc.

[0140] A scanning line driver circuit 221a, a common line driver circuit 241a, a signal line driver circuit 231a, and a signal Various signals and potentials are applied to the line driver circuit 232a via a flexible printed circuit (FPC). The input voltage is supplied via a 4018 printed circuit.

[0141] The integrated circuit 4042 included in the scanning line driver circuit 221a and the common line driver circuit 241a is The signal line driver circuit 231a and the signal line driver The integrated circuit 4042 in the circuit 232a has a function of supplying image data to the display unit 215. The integrated circuit 4042 is surrounded by a sealant 4005 on the first substrate 4001. It is implemented in a different area than the area in which it is installed.

[0142] Note that the connection method of the integrated circuit 4042 is not particularly limited, and wire bonding method, COG (Chip On Glass) method, TCP (Tape Carrier Package) method, COF (Chip On Film) method, etc. can be used thereof.

[0143] FIG. 9(B) shows an example of mounting the integrated circuit 4042 included in the signal line driving circuit 231a and the signal line driving circuit 232a by the COG method. Further, a part or the whole of the driving circuit can be integrally formed on the same substrate as the display unit 215 to form a system-on-panel

[0144] In FIG. 9(B), an example of forming the scanning line driving circuit 221a and the common line driving circuit 241a on the same substrate as the display unit 21 5 is shown. By forming the driving circuit simultaneously with the pixel circuit in the display unit 215, the number of components can be reduced. Therefore, productivity can be improved

[0145] Further, in FIG. 9(B), a sealing material 4005 is provided so as to surround the display unit 215 provided on the first substrate 4001, the scanning line driving circuit 221a, and the common line driving circuit 241a. Further, a second substrate 4006 is provided on the display unit 215, the scanning line driving circuit 221a, and the common line driving circuit 24 1a. Therefore, the display unit 215, the scanning line driving circuit 221a, and the common line driving circuit 241a are sealed together with the display elements by the first substrate 4001, the sealing material 4005, and the second substrate 4006.

[0146] Further, in FIG. 9(B), the signal line driving circuit 231a and the signal line driving circuit 232a are separately formed ​​​​​​​​Although an example of mounting on the first substrate 4001 is shown, the configuration is not limited to this. The scanning line driving circuit may be separately formed and mounted, or a part of the signal line driving circuit or a part of the scanning line driving circuit may be separately formed and mounted. Further, as shown in FIG. 9(C), the signal line driving circuit 231a and the signal line driving circuit 232a may be formed on the same substrate as the display unit 215 .

[0147] Further, the display device may include a display panel in a state where the display elements are sealed, and a module in a state where an IC including a controller is mounted on the display panel.

[0148] Further, the display unit and the scanning line driving circuit provided on the first substrate have a plurality of transistors The transistors shown in the above embodiment can be applied as the transistors. It is possible.

[0149] The structure of the transistors included in the peripheral driving circuit and the transistors included in the pixel circuit of the display unit may be the same or different. The transistors included in the peripheral driving circuit may all have the same structure, or two or more types of structures may be used in combination. Similarly, the transistors included in the pixel circuit may all have the same structure, or two or more types of structures may be used in combination. It is possible.

[0150] Further, an input device 4200 can be provided on the second substrate 4006. FIG. 9(A) to (C) The configuration in which the input device 4200 is provided in the display device shown can function as a touch panel It is possible.

[0151] There is no limitation on the detection element (also referred to as a sensor element) included in the touch panel according to one aspect of the present invention Various sensors capable of detecting the proximity or contact of a detected object such as a finger or a stylus can be applied as a detection element.

[0152] As the sensor method, for example, various methods such as a capacitance method, a resistive film method, a surface acoustic wave method, an infrared method, an optical method, and a pressure-sensitive method can be used.

[0153] In this embodiment, a touch panel having a capacitance-type detection element will be described as an example.

[0154] As the capacitance method, there are a surface capacitance method, a projected capacitance method, etc. Also, as the projected capacitance method, there are a self-capacitance method, a mutual-capacitance method, etc. Using the mutual-capacitance method is preferable because simultaneous multi-point detection becomes possible.

[0155] A touch panel according to an aspect of the present invention can adopt various configurations, such as a configuration in which a separately manufactured display device and a detection element are bonded together, and a configuration in which electrodes or the like constituting the detection element are provided on one or both of a substrate supporting the display element and a counter substrate.

[0156] FIGS. 10(A) and (B) are diagrams for explaining an example of a touch panel. FIG. 10(A) is a perspective view of a touch panel 4210. FIG. 10(B) is a schematic perspective view of an input device 4200. For clarity, only typical components are shown.

[0157] The touch panel 4210 has a configuration in which a separately manufactured display device and a detection element are bonded together.

[0158] The touch panel 4210 has an input device 4200 and a display device, and these are stacked. ​​​​​

[0159] The input device 4200 includes a substrate 4263, electrodes 4227, electrode 4228, a plurality of wirings 423 7, a plurality of wirings 4238, and a plurality of wirings 4239. For example, the electrode 4227 can be electrically connected to the wiring 4237 or the wiring 4239. Also, the electrode 4228 can be electrically connected to the wiring 4239. The FPC 4272b is electrically connected to each of the plurality of wirings 4237 and the plurality of wirings 4238. An IC 4273b can be provided on the FPC 4272b .

[0160] Alternatively, a touch sensor may be provided between the first substrate 4001 and the second substrate 4006 of the display device . When a touch sensor is provided between the first substrate 4001 and the second substrate 4006, in addition to the capacitive touch sensor, an optical touch sensor using a photoelectric conversion element may be applied.

[0161] FIGS. 11(A) and (B) are diagrams for explaining a cross-sectional view of the display device. FIGS. 11(A) and (B) are cross-sectional views of the portion indicated by the one-dot chain line N1-N2 in FIG. 9(B). The display device shown in FIGS. 11( A) and (B) has an electrode 4015, and the electrode 4015 is electrically connected to the terminal of the FPC 40 18 via the anisotropic conductive layer 4019. Also, in FIGS. 11(A) and (B), the electrode 4015 is electrically connected to the wiring 4014 at the opening formed in the insulating layer 4112, the insulating layer 4111, and the insulating layer 4110.

[0162] The electrode 4015 is formed from the same conductive layer as the first electrode layer 4030, and the wiring 4014 is the same as the source electrodes and drain electrodes of the transistors 4010 and 4011 It is formed by a conductive layer.

[0163] In addition, the display unit 215 and the scanning line driving circuit 221a provided on the first substrate 4001 have a plurality of transistors. In FIGS. 11(A) and (B), the transistors 4010 included in the display unit 215 and the transistor 4011 included in the scanning line driving circuit 221a are illustrated. Note that in FIGS. 11(A) and (B), the transistors 4010 and the transistors 4011 are illustrated as bottom gate type transistors, but they may be top gate type transistors.

[0164] In FIGS. 11(A) and (B), an insulating layer 4112 is provided on the transistors 4010 and the transistor 4011. In addition, in FIG. 11(B), a partition wall 4510 is formed on the insulating layer 4112.

[0165] In addition, the transistors 4010 and the transistor 4011 are provided on an insulating layer 4102. In addition, the transistors 4010 and the transistor 4011 have an electrode 4017 formed on an insulating layer 4111. The electrode 4017 functions as a back gate electrode.

[0166] In addition, the display device shown in FIGS. 11(A) and (B) has a capacitive element 4020. The capacitive element 4020 has an electrode 4021 formed in the same process as the gate electrode of the transistor 4010 and an electrode formed in the same process as the source electrode and the drain electrode. Each electrode overlaps via an insulating layer 4103.

[0167] Generally, the capacitance of the capacitive element provided in the pixel portion of the display device is the same as that of the transistor arranged in the pixel portion. It is set so that charge can be held for a predetermined period in consideration of the leakage current of the capacitor and the like. The capacitance of the capacitance element may be set in consideration of the off-current of the transistor and the like.

[0168] The transistor 4010 provided in the display unit 215 is electrically connected to the display element. FIG. 1 1(A) is an example of a liquid crystal display device using a liquid crystal element as a display element. FIG. 11(A) In, the liquid crystal element 4013 as a display element includes a first electrode layer 4030, a second electrode layer 4 031, and a liquid crystal layer 4008. Note that insulating layers 4032 and 4033 that function as alignment films are provided so as to sandwich the liquid crystal layer 4008. The second electrode layer 4031 is provided on the second substrate 4006 side, and the first electrode layer 4030 and the second electrode layer 4031 overlap via the liquid crystal layer 4008.

[0169] As the liquid crystal element 4013, liquid crystal elements to which various modes are applied can be used. For example, VA (Vertical Alignment) mode, TN (Twisted Nematic) mode, IPS (In-Plane-Switching) mode, ASM (Axially Symmetric aligned Micro-cell ) mode, OCB (Optically Compensated Bend) mode, FLC (Ferroelectric Liquid Crystal) mode, AFL C (AntiFerroelectric Liquid Crystal) mode, E CB (Electrically Controlled Birefringence ) mode, VA-IPS mode, guest-host mode, etc. can be used.

[0170] In addition, a normally black type liquid crystal display device shown in this embodiment, for example, a transmissive liquid crystal display device adopting a vertical alignment (VA) mode may be applied. As the vertical alignment mode, an MVA (Multi-Domain Vertical Alignment ent) mode, a PVA (Patterned Vertical Alignment ) mode, an ASV (Advanced Super View) mode, etc. can be used.

[0171] Note that a liquid crystal element is an element that controls light transmission or non-transmission by the optical modulation action of liquid crystal. The optical modulation action of liquid crystal is controlled by an electric field applied to the liquid crystal (including a horizontal electric field, a vertical electric field, or an oblique angled electric field). As the liquid crystal used for the liquid crystal element, a thermotropic liquid crystal, a low molecular liquid crystal, a high molecular liquid crystal, a polymer dispersed liquid crystal (PDLC: Polymer Dispersed Liquid Crystal), a ferroelectric liquid crystal, an antiferroelectric liquid crystal etc. can be used. These liquid crystal materials show a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, etc. depending on conditions.

[0172] In FIGS. 11(A) and (B), an example of a liquid crystal display device having a vertical electric field type liquid crystal element is shown, but in one aspect of the present invention, a liquid crystal display device having a horizontal electric field type liquid crystal element can be applied. When adopting a horizontal electric field method, a liquid crystal showing a blue phase without using an alignment film may also be used. The blue phase is one of the liquid crystal phases, and when the cholesteric liquid crystal is heated, it is a phase that appears immediately before the transition from the cholesteric phase to the isotropic phase. The blue phase exists only in a narrow temperature range. ​​Since it does not occur, a liquid crystal mixed with 5 wt% or more of a chiral agent is used to improve the temperature range. The composition is used for the liquid crystal layer 4008. A liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent has a short response time and exhibits optical isotropy. Also, a liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent does not require alignment treatment and has a small viewing angle dependence. Also, since an alignment film does not need to be provided, rubbing treatment is not required, so electrostatic breakdown caused by rubbing treatment can be prevented, and defects or breakage of the liquid crystal display device during the manufacturing process can be reduced.

[0173] Also, the spacer 4035 is a columnar spacer obtained by selectively etching an insulating layer, and is provided to control the distance (cell gap) between the first electrode layer 4030 and the second electrode layer 4031. Note that a spherical spacer may be used.

[0174] Also, if necessary, optical members (optical substrates) such as a black matrix (light-shielding layer), a coloring layer (color filter), a polarizing member, a retardation member, and an antireflection member may be appropriately provided. For example, circular polarization using a polarizing substrate and a retardation substrate may be used. Also, as the light source, backlight, side light, etc. may be used. Also, as the above backlight and side light , micro LEDs, etc. may be used.

[0175] In the display device shown in FIG. 11(A), a light-shielding layer 4132, a coloring layer 4131, and an insulating layer 4133 are provided between the substrate 4006 and the second electrode layer 4031.

[0176] Materials that can be used as the light-shielding layer include carbon black, titanium black, Examples include composite oxides containing metals, metal oxides, solid solutions of multiple metal oxides, etc. Light-shielding layer It may be a film containing a resin material, or may be a thin film of an inorganic material such as a metal. Also A laminated film of a film containing the material of the colored layer can also be used for the light-shielding layer. For example, a film containing the material used for a colored layer that transmits light of a certain color and a film containing the material used for a colored layer that transmits light of another color can be used in a laminated structure. By sharing the materials of the colored layer and the light-shielding layer , it is preferable because the device can be shared and the process can be simplified

[0177] Examples of materials that can be used for the colored layer include resin materials containing metal materials, resin materials, pigments, or dyes. The formation of the light-shielding layer and the colored layer may be performed in the same manner as the formation methods of the respective layers described above. For example, it may be performed by an inkjet method or the like

[0178] In addition, the display devices shown in FIGS. 11(A) and (B) have an insulating layer 4111 and an insulating layer 4104 As the insulating layer 4111 and the insulating layer 4104, an insulating layer that hardly transmits impurity elements is used By sandwiching the semiconductor layer of the transistor with the insulating layer 4111 and the insulating layer 4104, intrusion of impurities from the outside can be prevented

[0179] In addition, a light-emitting element can be used as the display element included in the display device. As the light-emitting element For example, an EL element utilizing electroluminescence can be applied The EL element has a layer containing a light-emitting compound (also referred to as an "EL layer") between a pair of electrodes When a potential difference larger than the threshold voltage of the EL element is generated between the pair of electrodes, holes are injected into the EL layer from the anode side, and electrons are injected from the cathode side. The injected electrons and holes are E ​Recombination occurs in the L layer, and the light-emitting substance contained in the EL layer emits light.

[0180] Also, EL elements are classified according to whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element, and the latter is called an inorganic EL element.

[0181] In an organic EL element, by applying a voltage, electrons are injected from one electrode and holes are injected from the other electrode into the EL layer respectively. Then, these carriers (electrons and holes) recombine, forming an excited state of a light-emitting organic compound, and light is emitted when the excited state returns to the ground state. Due to such a mechanism, such a light-emitting element is called a current-excited light-emitting element.

[0182] In addition to the light-emitting compound, the EL layer may also contain a substance with high hole injection property, a substance with high hole transport property, a hole blocking material, a substance with high electron transport property, a substance with high electron injection property, or a bipolar substance (a substance with high electron transport property and high hole transport property).

[0183] The EL layer can be formed by methods such as vapor deposition (including vacuum vapor deposition), transfer method, printing method, inkjet method, coating method.

[0184] Inorganic EL elements are classified into dispersed inorganic EL elements and thin-film inorganic EL elements according to their element structures. Dispersed inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and the light-emitting mechanism is donor-acceptor recombination light emission using donor levels and acceptor levels. Thin-film inorganic EL elements have a structure in which a light-emitting layer is sandwiched between dielectric layers and further sandwiched between electrodes, and the light-emitting mechanism is inner-shell electron transition of metal ions. ​​​​​​​​​​ It is the localized light emission to be used. Here, an organic EL element is used as the light emitting element for explanation. This will be described.

[0185] For the light emitting element to extract light emission, it is sufficient that at least one of a pair of electrodes is transparent. Thus, a transistor and a light emitting element are formed on a substrate, and top emission (top emission) structure for extracting light emission from the surface on the side opposite to the substrate, bottom emission structure for extracting light emission from the surface on the substrate side (bottom emission), and dual emission structure for extracting light emission from both sides (dual emission) There is a light emitting element of the structure, and a light emitting element of any emission structure can be applied. And a bottom emission structure for extracting light emission from the surface on the substrate side (bottom emission), and a dual emission structure for extracting light emission from both sides (dual emission) There is a light emitting element of the structure, and a light emitting element of any emission structure can be applied. And a bottom emission structure for extracting light emission from the surface on the substrate side (bottom emission), and a dual emission structure for extracting light emission from both sides (dual emission) There is a light emitting element of the structure, and a light emitting element of any emission structure can be applied. (Bottom emission) structure and a dual emission structure for extracting light emission from both sides (dual emission) There is a light emitting element of the structure, and a light emitting element of any emission structure can be applied. There is a light emitting element of the structure, and a light emitting element of any emission structure can be applied.

[0186] Figure 11(B) is an example of a light emitting display device (also referred to as an "EL display device") using a light emitting element as a display element. The light emitting element 4513 which is a display element is electrically connected to the transistor 4010 provided in the display unit 215. The structure of the light emitting element 4513 is a laminated structure of a first electrode layer 4030, a light emitting layer 4511, and a second electrode layer 4031, but is not limited to this structure. The structure of the light emitting element 4513 can be appropriately changed according to the direction of light extracted from the light emitting element 4513 and the like. Figure 11(B) is an example of a light emitting display device (also referred to as an "EL display device") using a light emitting element as a display element. The light emitting element 4513 which is a display element is electrically connected to the transistor 4010 provided in the display unit 215. The structure of the light emitting element 4513 is a laminated structure of a first electrode layer 4030, a light emitting layer 4511, and a second electrode layer 4031, but is not limited to this structure. The structure of the light emitting element 4513 can be appropriately changed according to the direction of light extracted from the light emitting element 4513 and the like. Figure 11(B) is an example of a light emitting display device (also referred to as an "EL display device") using a light emitting element as a display element. The light emitting element 4513 which is a display element is electrically connected to the transistor 4010 provided in the display unit 215. The structure of the light emitting element 4513 is a laminated structure of a first electrode layer 4030, a light emitting layer 4511, and a second electrode layer 4031, but is not limited to this structure. The structure of the light emitting element 4513 can be appropriately changed according to the direction of light extracted from the light emitting element 4513 and the like. The structure of the light emitting element 4513 is a laminated structure of a first electrode layer 4030, a light emitting layer 4511, and a second electrode layer 4031, but is not limited to this structure. The structure of the light emitting element 4513 can be appropriately changed according to the direction of light extracted from the light emitting element 4513 and the like. The structure of the light emitting element 4513 can be appropriately changed according to the direction of light extracted from the light emitting element 4513 and the like. The structure of the light emitting element 4513 can be appropriately changed according to the direction of light extracted from the light emitting element 4513 and the like.

[0187] The partition wall 4510 is formed using an organic insulating material or an inorganic insulating material. In particular, it is preferable to use a photosensitive resin material to form an opening on the first electrode layer 4030 so that the side surface of the opening becomes an inclined surface formed with a continuous curvature. The partition wall 4510 is formed using an organic insulating material or an inorganic insulating material. In particular, it is preferable to use a photosensitive resin material to form an opening on the first electrode layer 4030 so that the side surface of the opening becomes an inclined surface formed with a continuous curvature. The partition wall 4510 is formed using an organic insulating material or an inorganic insulating material. In particular, it is preferable to use a photosensitive resin material to form an opening on the first electrode layer 4030 so that the side surface of the opening becomes an inclined surface formed with a continuous curvature.

[0188] The light emitting layer 4511 may be composed of a single layer or may be composed of a plurality of layers laminated. The light emitting layer 4511 may be composed of a single layer or may be composed of a plurality of layers laminated.

[0189] The emission color of the light-emitting element 4513 can be white, red, green, blue, cyan, magenta, yellow, or the like depending on the material constituting the light-emitting layer 4511.

[0190] As a method for realizing color display, there are a method of combining a light-emitting element 4513 having a white emission color with a coloring layer, and a method of providing light-emitting elements 4513 having different emission colors for each pixel. The former method has higher productivity than the latter method. On the other hand, in the latter method, since it is necessary to separately produce the light-emitting layer 451 1 for each pixel, the productivity is inferior to that of the former method. However, in the latter method, it is possible to obtain an emission color with higher color purity than the former method. In addition to the latter method, the color purity can be further increased by imparting a microcavity structure to the light-emitting element 4513.

[0191] Note that the light-emitting layer 4511 may contain an inorganic compound such as quantum dots. For example, by using quantum dots in the light-emitting layer, it can also function as a light-emitting material.

[0192] A protective layer may be formed on the second electrode layer 4031 and the partition wall 4510 so that oxygen, hydrogen, moisture, carbon dioxide, etc. do not enter the light-emitting element 4513. As the protective layer, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxynitride, DLC (Diamond Like Carbon), or the like can be formed. In addition, a filling material 4514 is provided and sealed in the space sealed by the first substrate 4001, the second substrate 4006, and the sealing material 40 05. In this way, the airtightness is high so as not to be exposed to the outside air, and a protective film (laminated film) with little outgassing is used. It is preferable to package (enclose) it with a cover material (such as a lum, an ultraviolet curable resin film, etc.). Preferably.

[0193] As the filler 4514, in addition to an inert gas such as nitrogen or argon, an ultraviolet curable resin or a thermosetting resin can be used, and PVC (polyvinyl chloride), acrylic resin, polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate), etc. can be used. Further, the filler 4514 may contain a desiccant. It may also be included.

[0194] As the sealing material 4005, a glass material such as glass frit, or a resin material such as a two-component mixed resin a curable resin that cures at room temperature, a photocurable resin, a thermosetting resin, etc. can be used. Further, the sealing material 4005 may contain a desiccant.

[0195] Also, if necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) a retardation plate (λ / 4 plate, λ / 2 plate), a color filter, etc. can be appropriately provided on the light emitting surface of the light emitting element. Further, an antireflection film may be provided on the polarizing plate or the circular polarizing plate. For example, due to surface irregularities diffuse the reflected light and perform an antiglare treatment that can reduce reflection.

[0196] Also, by making the light emitting element have a microcavity structure, light with high color purity can be extracted. Also, by combining the microcavity structure and the color filter, reflection can be reduced and the visibility of the display image can be improved.

[0197] A first electrode layer and a second electrode layer (pixel electrode layer, common electrode layer, (also referred to as the counter electrode layer, etc.), the light extraction direction, the location where the electrode layer is provided, and depending on the electrode layer's pattern structure, the light transmittance and reflectivity can be selected.

[0198] The first electrode layer 4030 and the second electrode layer 4031 can use a conductive material with light transmittance such as indium oxide containing tungsten, indium zinc oxide containing tungsten, indium oxide containing titanium, indium tin oxide, indium tin oxide containing titanium, indium zinc oxide, indium tin oxide added with silicon oxide, etc. can be used. can be used. can be used. can be used.

[0199] Further, the first electrode layer 4030 and the second electrode layer 4031 can be formed using one or more of metals such as tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium ( Nb), tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni), titanium ( Ti), platinum (Pt), aluminum (Al), copper (Cu), silver (Ag), etc., or their alloys, or their metal nitrides. can be formed. can be formed. .

[0200] Also, as the first electrode layer 4030 and the second electrode layer 4031, a conductive composition containing a conductive polymer (also referred to as a conductive polymer) can be used for formation. As the conductive polymer, a so-called π - electron conjugated system conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives, or a copolymer composed of two or more of aniline, pyrrole, and thiophene or its derivatives, etc. can be mentioned. derivatives, or a copolymer composed of two or more of aniline, pyrrole, and thiophene or its derivatives, etc. can be mentioned. derivatives, etc. can be mentioned.

[0201] In addition, since transistors are easily damaged by static electricity or the like, it is preferable to provide a protection circuit for protecting the drive circuit. The protection circuit is preferably configured using a non-linear element. It is also preferable to configure the protection circuit using a non-linear element.

[0202] Note that, as shown in FIG. 12, a stack structure in which regions where transistors and capacitor elements overlap in the height direction may be used. For example, if the transistors 4011 and 4022 that make up the drive circuit are stacked, a display device with a narrow border can be obtained. In addition, if the transistors 4010, 4023, capacitor element 4020, etc. that make up the pixel circuit are arranged so as to have a region where they partially overlap, the aperture ratio and resolution can be improved. Note that FIG. 12 shows an example in which the stack structure is applied to the liquid crystal display device shown in FIG. 11(A), but it may also be applied to the EL display device shown in FIG. 11(B). Further, in the pixel circuit, by using a transparent conductive film having high transparency to visible light for electrodes and wirings, the light transmittance within the pixel can be increased, and the aperture ratio can be substantially improved. Note that when an OS transistor is used, since the semiconductor layer also has transparency, the aperture ratio can be further increased. These are also effective even when the transistors or the like are not in a stack structure. In addition, a display device may be configured by combining a liquid crystal display device and a light-emitting device. The light-emitting device is arranged on the reverse side of the display surface or at the end of the display surface. The light-emitting device has a function of supplying light to the display element. The light-emitting device can also be called a backlight.

[0203]

[0204]

[0205]

[0206] ​​​​​​​​Here, the light-emitting device can have a plate-like or sheet-like light guide part (also referred to as a light guide plate) and a plurality of light-emitting elements that exhibit light of different colors. When the light-emitting elements are arranged near the side surface of the light guide part, light can be emitted from the side surface of the light guide part into the interior. The light guide part has a mechanism for changing the optical path ( also referred to as a light extraction mechanism), and thereby, the light-emitting device can uniformly irradiate the pixel part of the display panel with light. Alternatively, a configuration may be adopted in which the light guide part is not provided and the light-emitting device is arranged directly below the pixel.

[0207] The light-emitting device preferably has light-emitting elements of three colors: red (R), green (G), and blue (B). Furthermore, it may also have a white (W) light-emitting element. It is preferable to use a light-emitting diode (LED) as these light-emitting elements.

[0208] Furthermore, the light-emitting element preferably has a very high color purity such that the full width at half maximum (FWHM) of its emission spectrum is 50 nm or less, preferably 40 nm or less, more preferably 30 nm or less, and even more preferably 20 nm or less. Note that the full width at half maximum of the emission spectrum is preferably as small as possible, but can be, for example, 1 nm or more. Thereby, when performing color display, a vivid display with high color reproducibility can be achieved.

[0209] Also, for the red light-emitting element, it is preferable to use an element whose peak wavelength of the emission spectrum is in the range of 625 nm or more and 650 nm or less. Also, for the green light-emitting element, it is preferable to use an element whose peak wavelength of the emission spectrum is in the range of 515 nm or more and 540 nm or less. ​It is preferable. The blue light-emitting element preferably uses an element in which the peak wavelength of the emission spectrum is in the range of 445 nm or more and 470 nm or less.

[0210] The display device can sequentially blink the three-color light-emitting elements and drive the pixels in synchronization therewith to perform color display based on the sequential addition color mixing method. This driving method can also be called field sequential driving.

[0211] In field sequential driving, a vivid color image can be displayed. Also a smooth moving image can be displayed. Further, by using the above driving method, it is not necessary to configure one pixel with a plurality of sub-pixels of different colors, and the effective reflection area (also referred to as the effective display area, aperture ratio) of one pixel can be increased, so that bright display can be performed. Furthermore since it is not necessary to provide a color filter for the pixel, the transmittance of the pixel can also be improved and further bright display can be performed. Also, the manufacturing process can be simplified and the manufacturing cost can be reduced.

[0212] Figs. 13(A) and (B) are schematic cross-sectional views of an example of a display device capable of field sequential driving. On the substrate 4001 side of the display device, a backlight unit capable of emitting RGB colors is provided. Note that in field sequential driving, since colors are expressed by time-division emission of RGB colors, a color filter is not required.

[0213] The backlight unit 4340a shown in Fig. 13(A) has a configuration in which a plurality of light-emitting elements 4342 are provided via a diffusion plate 4352 directly below the pixels. The diffusion plate 4352 is for the light-emitting element 4 A function that diffuses the light emitted from 342 toward the substrate 4001 side and equalizes the luminance within the display section is provided. A polarizing plate may be provided between the light-emitting element 4342 and the diffusion plate 4352 as needed. Also, if the diffusion plate 4352 is unnecessary, it may not be provided. Further, a light-shielding layer 4132 may be omitted.

[0214] The backlight unit 4340a can mount many light-emitting elements 4342, so that a bright display is possible. Also, a light guide plate is unnecessary, and there is an advantage that the efficiency of the light of the light-emitting element 4342 is hardly impaired. Note that a lens 4 344 for light diffusion may be provided to the light-emitting element 4342 as needed.

[0215] The backlight unit 4340b shown in Fig. 13(B) has a configuration in which a light guide plate 4341 is provided via a diffusion plate 4352 directly under the pixel. A plurality of light-emitting elements 4 342 are provided at the end of the light guide plate 4341. The light guide plate 4341 has a concavo-convex shape on the side opposite to the diffusion plate 4352 and can scatter the guided light with the concavo-convex shape and emit it in the direction of the diffusion plate 4352.

[0216] The light-emitting element 4342 can be fixed to the printed circuit board 4347. Note that in Fig. 13( B), although the light-emitting elements 4342 of each of RGB colors are shown overlapping, they may be arranged so that the light-emitting elements 4342 of each of R GB colors are arranged side by side in the depth direction. Also, in the light guide plate 4341 , a reflection layer 4348 that reflects visible light may be provided on the side surface opposite to the light-emitting element 4342 .

[0217] The backlight unit 4340b can reduce the number of light-emitting elements 4342, so that it can be made low-cost and thin.

[0218] In addition, a light-scattering type liquid crystal element may be used for the liquid crystal element. As the light-scattering type liquid crystal element, it is preferable to use an element having a composite material of liquid crystal and polymer. For example, a polymer-dispersed liquid crystal element can be used. Alternatively, a polymer network type liquid crystal (PNLC (Polymer Network Liquid Crystal)) element may be used.

[0219] The light-scattering type liquid crystal element has a structure in which a liquid crystal portion is provided in a three-dimensional network structure of a resin portion sandwiched between a pair of electrodes. As the material used for the liquid crystal portion, for example, nematic liquid crystal can be used. In addition, a photocurable resin can be used as the resin portion. As the photocurable resin, for example, monofunctional monomers such as acrylate and methacrylate, difunctional monomers such as diacrylate, triacrylate, dimethacrylate, and trimethacrylate, or a polymerizable compound obtained by mixing these can be used.

[0220] The light-scattering type liquid crystal element utilizes the anisotropy of the refractive index of the liquid crystal material to display by transmitting or scattering light. In addition, the resin portion may also have anisotropy of the refractive index. When the liquid crystal molecules are aligned in a certain direction according to the voltage applied to the light-scattering type liquid crystal element, the difference in refractive index between the liquid crystal portion and the resin portion becomes small, and the light incident along the direction is transmitted through the liquid crystal portion without being scattered. Therefore, the light-scattering type liquid crystal element is visually recognized as a transparent state from that direction. On the other hand, when the alignment of the liquid crystal molecules becomes random according to the applied voltage, since a large change does not occur in the difference in refractive index between the liquid crystal portion and the resin portion, the incident light is scattered by the liquid crystal portion. Therefore, the light-scattering type liquid crystal element becomes opaque regardless of the viewing direction.

[0221] Figure 14(A) shows a configuration in which the liquid crystal element 4013 of the display device in Fig. 13(A) is replaced with a light-scattering liquid crystal element 40 16. The light-scattering liquid crystal element 4016 has a liquid crystal part and a resin part Composite layer 4009, and electrode layers 4030 and 4031. The elements related to field-sequential driving are the same as those in Fig. 13(A), but when using the light-scattering liquid crystal element 4016 the alignment film and polarizing plate become unnecessary. Note that the spacer 4035 is shown in a spherical form but may be columnar.

[0222] Figure 14(B) shows a configuration in which the liquid crystal element 4013 of the display device in Fig. 13(B) is replaced with a light-scattering liquid crystal element 40 16. In the configuration of Fig. 13(B), it is preferably configured to operate in a mode where light is transmitted when no voltage is applied to the light-scattering liquid crystal element 4016 and light is scattered when a voltage is applied . By adopting such a configuration, a transparent display device can be obtained in the normal state (a state where display is not performed). In this case, color display can be performed when the operation of scattering light is performed . .

[0223] Modifications of the display device shown in Fig. 14(B) are shown in Figs. 15(A) to (E). Note that in Figs. 15 (A) to (E), for clarity, some elements of Fig. 14(B) are used and other elements are omitted from the illustration.

[0224] Figure 15(A) shows a configuration in which the substrate 4001 has a function as a light guide plate. An uneven shape may be provided on the outer surface of the substrate 400 1. In this configuration, since there is no need to separately provide a light guide plate, the manufacturing cost can be reduced. Also, the light attenuation by the light guide plate is also reduced Since it is eliminated, the light emitted from the light-emitting element 4342 can be efficiently utilized.

[0225] FIG. 15(B) shows a configuration in which light is incident from the vicinity of the end of the composite layer 4009. The composite layer 40 Total reflection at the interface between 09 and the substrate 4006 and at the interface between the composite layer 4009 and the substrate 4001 is utilized, and light can be emitted to the outside from the light-scattering liquid crystal element. For the resin portion of the composite layer 4009, a material having a refractive index larger than that of the substrates 4001 and 4006 is used.

[0226] Note that the light-emitting element 4342 may be provided not only on one side of the display device but also on two opposite sides as shown in FIG. 15(C). Furthermore, it may be provided on three sides or four sides. By providing the light-emitting element 4342 on a plurality of sides, light attenuation can be compensated for, and a large-area display element can also be supported.

[0227] FIG. 15(D) shows a configuration in which the light emitted from the light-emitting element 4342 is guided to the display device through the mirror 4345. With this configuration, it is easy to guide light to the display device at a certain angle, so that total reflection light can be obtained efficiently.

[0228] FIG. 15(E) shows a configuration having a stack of the layer 4003 and the layer 4004 on the composite layer 4009. One of the layer 4003 and the layer 4004 is a support such as a glass substrate, and the other can be formed of an inorganic film, a coating film of an organic resin, a film, or the like. For the resin portion of the composite layer 4009, a material having a refractive index larger than that of the layer 4004 is used. Also, for the layer 4004, a material having a refractive index larger than that of the layer 4003 is used.

[0229] A first interface is formed between the composite layer 4009 and the layer 4004, and between the layer 4004 and the layer 40 A second interface is formed between the two and 03. With this configuration, the light that has passed through without being totally reflected at the first interface can be totally reflected at the second interface and returned to the composite layer 4009. Therefore, the light emitted from the light-emitting element 4342 can be efficiently utilized.

[0230] Note that the configurations in FIGS. 14(B) and 15(A) to (E) can be combined with each other.

[0231] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments and the like.

[0232] (Embodiment 3) In this embodiment, an example of a transistor that can be used in place of each transistor shown in the above embodiment will be described with reference to the drawings.

[0233] A display device according to an aspect of the present invention can be manufactured using various types of transistors such as bottom-gate type transistors and top-gate type transistors. Therefore, it is possible to easily replace the material of the semiconductor layer and the transistor structure to be used according to the existing manufacturing line.

[0234] 〔Bottom-gate type transistor〕 FIG. 16(A1) is a cross-sectional view of a channel protection type transistor 810, which is a type of bottom-gate type transistor, in the channel length direction. In FIG. 16(A1), the transistor 810 is formed on a substrate 771. Further, the transistor 810 has an electrode 746 on the substrate 771 via an insulating layer 772. Further, an insulating layer 726 is provided on the electrode 746. The insulating layer 726 has a semiconductor layer 742. The electrode 746 can function as a gate electrode. It can function as a gate insulating layer.

[0235] In addition, an insulating layer 741 is provided over a channel formation region of the semiconductor layer 742. An electrode 744a and an electrode 744b are provided on the insulating layer 726 in contact with a part of the insulating layer 742. Electrode 744a can function as either a source or drain electrode. A part of the electrode 744a and the electrode 74 A part of 4b is formed on the insulating layer 741.

[0236] The insulating layer 741 can function as a channel protection layer. By providing the insulating layer 1, the exposure of the semiconductor layer 742 that occurs when the electrodes 744a and 744b are formed can be prevented. Therefore, when the electrodes 744a and 744b are formed, the semiconductor layer 7 This can prevent the channel formation region 42 from being etched. As a result, a transistor with good electrical characteristics can be realized.

[0237] The transistor 810 has an insulating layer 741 formed on the electrode 744a, the electrode 744b, and the insulating layer 741. A layer 728 is provided, and an insulating layer 729 is provided on the insulating layer 728 .

[0238] When an oxide semiconductor is used for the semiconductor layer 742, at least At least in the portion in contact with the semiconductor layer 742, oxygen is taken from a portion of the semiconductor layer 742, and oxygen vacancies are formed. It is preferable to use a material capable of generating oxygen vacancies in the semiconductor layer 742. The resulting region has an increased carrier concentration, which makes it n-type, and the region is called an n-type region (n + layer). Therefore, the said region can function as a source region or a drain region. When a semiconductor oxide is used for the semiconductor layer 742, examples of materials that can extract oxygen from the semiconductor layer 742 and cause oxygen deficiency include tungsten, titanium, etc.

[0239] When a source region and a drain region are formed in the semiconductor layer 742, the contact resistance between the electrodes 744a and the semiconductor layer 742 can be reduced. Thus, electrical characteristics of the transistor, such as field effect mobility and threshold voltage, can be made good.

[0240] When a semiconductor such as silicon is used for the semiconductor layer 742, it is preferable to provide a layer that functions as an n-type semiconductor or a p-type semiconductor between the semiconductor layer 742 and the electrode 744 a, and between the semiconductor layer 742 and the electrode 744b. The layer that functions as an n-type semiconductor or a p-type semiconductor can function as a source region or a drain region of the transistor.

[0241] The insulating layer 729 is preferably formed using a material having a function of preventing or reducing diffusion of impurities from the outside into the transistor. Note that the insulating layer 729 can be omitted if necessary.

[0242] The transistor 811 shown in FIG. 16(A2) is different from the transistor 810 in that it has an electrode 723 that can function as a back gate electrode on the insulating layer 729. The electrode 723 can be formed of the same material and by the same method as the electrode 746.

[0243] Generally, a back gate electrode is formed of a conductive layer, and a semiconductor is provided between the gate electrode and the back gate electrode. It is arranged so as to sandwich the channel formation region of the layer. Therefore, the back gate electrode can function in the same way as the gate electrode. The potential of the back gate electrode may be the same as that of the gate electrode, or it may be the ground potential (GND potential) or an arbitrary potential. Also, by changing the potential of the back gate electrode independently without linking it to the gate electrode, the threshold voltage of the transistor can be changed.

[0244] In addition, both the electrode 746 and the electrode 723 can function as gate electrodes. Therefore, the insulating layer 726, the insulating layer 728, and the insulating layer 729 can each function as a gate insulating layer. Note that the electrode 723 may be provided between the insulating layer 728 and the insulating layer 729.

[0245] When one of the electrode 746 or the electrode 723 is referred to as the "gate electrode", the other is referred to as the "back gate electrode". For example, in the transistor 811, when the electrode 723 is referred to as the "gate electrode", the electrode 746 is referred to as the "back gate electrode". Also, when the electrode 723 is used as the "gate electrode", the transistor 811 can be considered as a type of top gate transistor. In addition, either the electrode 746 or the electrode 723 may be referred to as the "first gate electrode" and the other as the "second gate electrode".

[0246] By providing the electrode 746 and the electrode 723 with the semiconductor layer 742 interposed therebetween, and further by making the electrode 74 6 and the electrode 723 at the same potential, the region where carriers flow in the semiconductor layer 742 becomes larger in the film thickness direction, so the amount of carrier movement increases. As a result, the on-current of the transistor 811 increases and the field effect mobility becomes higher.​

[0247] Therefore, the transistor 811 is a transistor having a large on-current with respect to the occupied area. That is, the occupied area of the transistor 811 can be reduced with respect to the required on-current. According to one aspect of the present invention, the occupied area of the transistor can be reduced. Thus, according to one aspect of the present invention, a semiconductor device with a high integration degree can be realized. Moreover, since the gate electrode and the back gate electrode are formed of a conductive layer, it has a function of preventing the electric field generated outside the transistor from acting on the semiconductor layer where the channel is formed (particularly, an electric field shielding function against electrostatic charges and the like). Note that by forming the back gate electrode larger than the semiconductor layer and covering the semiconductor layer with the back gate electrode, the electric field shielding function can be enhanced. Also, by forming the back gate electrode with a conductive film having light-shielding properties, it is possible to prevent light from entering the semiconductor layer from the back gate electrode side. Therefore, it is possible to prevent light degradation of the semiconductor layer and deterioration of electrical characteristics such as a shift in the threshold voltage of the transistor. According to one aspect of the present invention, a transistor with good reliability can be realized. Also, a semiconductor device with good reliability can be realized.

[0248] Also, since the gate electrode and the back gate electrode are formed of a conductive layer, it has a function of preventing the electric field generated outside the transistor from acting on the semiconductor layer where the channel is formed (particularly, an electric field shielding function against electrostatic charges and the like). Note that by forming the back gate electrode larger than the semiconductor layer and covering the semiconductor layer with the back gate electrode, the electric field shielding function can be enhanced. Also, since the gate electrode and the back gate electrode are formed of a conductive layer, it has a function of preventing the electric field generated outside the transistor from acting on the semiconductor layer where the channel is formed (particularly, an electric field shielding function against electrostatic charges and the like). Note that by forming the back gate electrode larger than the semiconductor layer and covering the semiconductor layer with the back gate electrode, the electric field shielding function can be enhanced. Moreover, since the gate electrode and the back gate electrode are formed of a conductive layer, it has a function of preventing the electric field generated outside the transistor from acting on the semiconductor layer where the channel is formed (particularly, an electric field shielding function against electrostatic charges and the like). Note that by forming the back gate electrode larger than the semiconductor layer and covering the semiconductor layer with the back gate electrode, the electric field shielding function can be enhanced. Moreover, since the gate electrode and the back gate electrode are formed of a conductive layer, it has a function of preventing the electric field generated outside the transistor from acting on the semiconductor layer where the channel is formed (particularly, an electric field shielding function against electrostatic charges and the like). Note that by forming the back gate electrode larger than the semiconductor layer and covering the semiconductor layer with the back gate electrode, the electric field shielding function can be enhanced.

[0249] Also, by forming the back gate electrode with a conductive film having light-shielding properties, it is possible to prevent light from entering the semiconductor layer from the back gate electrode side. Therefore, it is possible to prevent light degradation of the semiconductor layer and deterioration of electrical characteristics such as a shift in the threshold voltage of the transistor. Also, by forming the back gate electrode with a conductive film having light-shielding properties, it is possible to prevent light from entering the semiconductor layer from the back gate electrode side. Therefore, it is possible to prevent light degradation of the semiconductor layer and deterioration of electrical characteristics such as a shift in the threshold voltage of the transistor. Also, by forming the back gate electrode with a conductive film having light-shielding properties, it is possible to prevent light from entering the semiconductor layer from the back gate electrode side. Therefore, it is possible to prevent light degradation of the semiconductor layer and deterioration of electrical characteristics such as a shift in the threshold voltage of the transistor.

[0250] According to one aspect of the present invention, a transistor with good reliability can be realized. Also, a semiconductor device with good reliability can be realized. According to one aspect of the present invention, a transistor with good reliability can be realized. Also, a semiconductor device with good reliability can be realized.

[0251] FIG. 16(B1) is a cross-sectional view of the channel protection type transistor 820 having a configuration different from that of FIG. 16(A1) in the channel length direction. The transistor 820 is substantially the same as the transistor 810. FIG. 16(B1) is a cross-sectional view of the channel protection type transistor 820 having a configuration different from that of FIG. 16(A1) in the channel length direction. The transistor 820 is substantially the same as the transistor 810. ​​​The structure is almost the same as that of the semiconductor layer 742, except that the insulating layer 741 covers the edge of the semiconductor layer 742. In addition, a portion of the insulating layer 741 overlapping the semiconductor layer 742 is selectively removed to form an opening. At the opening, the semiconductor layer 742 and the electrode 744a are electrically connected. In another opening formed by selectively removing a portion of the insulating layer 741 overlapping with the semiconductor layer 742, The conductor layer 742 and the electrode 744b are electrically connected to each other. The region overlapping the first region can function as a channel protection layer.

[0252] The transistor 821 illustrated in FIG. 16B2 has a backgate electrode over the insulating layer 729. The transistor 820 differs from the transistor 820 in that it has an electrode 723 that can function as a transistor.

[0253] By providing the insulating layer 741, the semiconductor generated when the electrodes 744a and 744b are formed can be prevented. Therefore, the layer 742 can be prevented from being exposed during the formation of the electrodes 744a and 744b. This can prevent the semiconductor layer 742 from becoming thin.

[0254] In addition, the transistors 820 and 821 are the same as the transistors 810 and The distance between electrodes 744a and 746 and the distance between electrodes 744b and 746 are larger than the distance between electrodes 744a and 746 and the distance between electrodes 744b and 746. Therefore, the parasitic capacitance between the electrode 744a and the electrode 746 is reduced. In addition, the parasitic capacitance between the electrode 744b and the electrode 746 can be reduced. According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be provided. do.

[0255] The transistor 825 shown in FIG. 16C1 is a bottom-gate transistor. It is a cross-sectional view in the channel length direction of a certain channel etching type transistor 825. The trans istor 825 forms electrode 744a and electrode 744b without using an insulating layer 741. Therefore, a part of the semiconductor layer 742 exposed during the formation of electrode 744a and electrode 744b may be etched. On the other hand, since the insulating layer 741 is not provided, the productivity of the transistor can be increased.

[0256] The transistor 826 shown in Fig. 16(C2) is different from the transistor 825 in that it has an electrode 723 that can function as a back gate electrode on the insulating layer 729.

[0257] Cross-sectional views in the channel width direction of transistors 810, 811, 820, 821, 825, and 826 are shown in Figs. 17(A1), (A2), (B1), (B2), (C1), and (C2) respectively.

[0258] In the structures shown in Figs. 17(B2) and (C2), the gate electrode and the back gate electrode are connected, and the potentials of the gate electrode and the back gate electrode become the same potential. Also, the semiconductor layer 742 is sandwiched between the gate electrode and the back gate electrode.

[0259] The length of each of the gate electrode and the back gate electrode in the channel width direction is longer than the length of the semiconductor layer 742 in the channel width direction, and the entire channel width direction of the semiconductor layer 742 is covered by the gate electrode or the back gate electrode with the insulating layers 726, 741, 728, and 729 in between.

[0260] With this configuration, the semiconductor layer 742 included in the transistor can be electrically surrounded by the electric fields of the gate electrode and the back gate electrode. ​​​​​​​​​​

[0261] Like the transistor 821 or the transistor 826, the gate electrode and the back gate electrode The electric field of the pole electrically surrounds the semiconductor layer 742 in which the channel formation region is formed. The device structure of the transistor is surrounded channel (S-channel l) It can be called a structure.

[0262] By adopting an S-channel structure, one or both of the gate electrode and the back gate electrode By using this method, an electric field for inducing a channel can be effectively applied to the semiconductor layer 742. This improves the current drive capability of the transistor, making it possible to obtain high on-current characteristics. In addition, since it is possible to increase the on-current, the transistor can be miniaturized. In addition, the S-channel structure improves the mechanical strength of the transistor. The degree can be increased.

[0263] [Top-gate transistor] The transistor 842 illustrated in FIG. 18A1 is a top-gate transistor. In the transistor 842, the insulating layer 729 is formed, and then the electrode 744a and the electrode 744b are The transistor 810 and the transistor 820 are different in that the electrode 744a is formed. The electrode 744b is formed by arranging the semiconductor layer 724 in an opening formed in the insulating layer 728 and the insulating layer 729. 742 and electrically connected.

[0264] In addition, a portion of the insulating layer 726 that does not overlap the electrode 746 is removed, and the electrode 746 and the remaining insulating layer 726 are separated. Impurities 755 are introduced into the semiconductor layer 742 using the layer 726 as a mask, thereby forming a semiconductor Impurity regions may be formed in layer 742 in a self-aligned manner. The transistor 842 has a region where the insulating layer 726 extends beyond the end of the electrode 746. The impurity concentration in the region where the impurities 755 are introduced through the insulating layer 726 of the semiconductor layer 742 is smaller than that in the region where the impurities 755 are introduced without passing through the insulating layer 726. The semiconductor layer 7 42 has an LDD (Lightly Doped Drain) region formed in a region that does not overlap with the electrode 746.

[0265] The transistor 843 shown in FIG. 18(A2) is different from the transistor 8 42 in that it has an electrode 723. The transistor 843 has an electrode 723 formed on the substrate 771. The electrode 723 has a region that overlaps with the semiconductor layer 742 through the insulating layer 772. The electrode 72 3 can function as a back gate electrode.

[0266] Also, as in the transistor 844 shown in FIG. 18(B1) and the transistor 845 shown in FIG. 18(B2), all of the insulating layer 726 in the region that does not overlap with the electrode 746 may be removed. Also, as in the transistor 846 shown in FIG. 18(C1) and the transistor 847 shown in FIG. 18(C2), the insulating layer 726 may be left.

[0267] After forming the electrode 746, the transistors 842 to 847 also introduce the impurities 755 into the semiconductor layer 742 using the electrode 74 6 as a mask, so that impurity regions can be self-alignedly formed in the semiconductor layer 74 2. According to one aspect of the present invention, a transistor with good electrical characteristics can be realized. Also, according to one aspect of the present invention, a highly integrated semiconductor device can be realized.

[0268] Cross-sectional views in the channel width direction of transistors 842, 843, 844, 845, 846, and 847 are shown in FIGS. 19(A1), (A2), (B1), (B2), (C1), and (C2), respectively.

[0269] Transistors 843, 845, and 847 each have the S-channel structure described above. However, the present invention is not limited thereto, and transistors 843, 845, and 847 do not necessarily have to have the S-channel structure.

[0270] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments and the like.

[0271] (Embodiment 4) As electronic devices that can use the display device according to an aspect of the present invention, there are display devices, personal computers, image storage devices or image playback devices equipped with recording media, mobile phones, game machines including portable types, portable data terminals, electronic book terminals, video cameras, cameras such as digital still cameras, goggle-type displays (head-mounted displays), navigation systems, audio playback devices (car audio, digital audio players, etc.), copiers, facsimiles, printers, printer multifunction devices, automated teller machines (ATMs), vending machines, and the like. Specific examples of these electronic devices are shown in FIGS. 20(A) to (F).

[0272] FIG. 20(A) is a digital camera, which includes a housing 961, a shutter button 962, a microphone 963, a speaker 967, a display unit 965, operation keys 966, a zoom lever 968, and a lens. ​​​​​​​​​​​​​It has 969 etc. By using the display device according to one aspect of the present invention for the display unit 965, various images can be displayed.

[0273] FIG. 20(B) is a digital signage, and has a configuration in which a large display unit 922 is attached to the side surface of the column 921. By using the display device according to one aspect of the present invention for the display unit 922, a display with high display quality can be performed.

[0274] FIG. 20(C) is an example of a mobile phone, and has a housing 951, a display unit 952, operation buttons 95 3, an external connection port 954, a speaker 955, a microphone 956, a camera 957, etc. The mobile phone is provided with a touch sensor on the display unit 952. Any operation such as making a call or inputting characters can be performed by touching the display unit 952 with a finger or a stylus. Also, the housing 951 and the display unit 952 have flexibility and can be bent and used as shown. By using the display device according to one aspect of the present invention for the display unit 952 various images can be displayed.

[0275] FIG. 20(D) is a video camera, and has a first housing 901, a second housing 902, a display unit 903 , operation keys 904, a lens 905, a connection part 906, a speaker 907, etc. The operation keys 904 and the lens 905 are provided on the first housing 901, and the display unit 903 is provided on the second housing 9 02. By using the display device according to one aspect of the present invention for the display unit 903, various images can be displayed.

[0276] FIG. 20(E) is a television, and has a housing 971, a display unit 973, operation keys 974, a speaker ​​​​It has a communication connection terminal 975, an optical sensor 977, etc. A touch sensor is provided on the display unit 973, and input operations can also be performed. By using the display device of one aspect of the present invention on the display unit 973, various images can be displayed. A touch sensor is provided, and information input / output can be performed. By using the display device of one aspect of the present invention on the display unit 973, various images can be displayed.

[0277] Figure 20(F) is a portable data terminal, which has a housing 911, a display unit 912, a speaker 913, a camera 919, etc. Information input / output can be performed by the touch panel function of the display unit 912. By using the display device of one aspect of the present invention on the display unit 912, various images can be displayed. By using the display device of one aspect of the present invention on the display unit 912, various images can be displayed.

[0278] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments and the like.

[0279] (Embodiment 5) In this embodiment, a metal oxide that can be suitably used for the channel formation region of a transistor will be described.

[0280] As a semiconductor material used for a transistor, a metal oxide having an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more can be used. Typically, it is a metal oxide containing indium, and for example, CAC-OS described later can be used.

[0281] A transistor using a metal oxide having a wider bandgap and a smaller carrier density than silicon can hold the charge accumulated in a capacitive element connected in series with the transistor for a long time due to its low off-current.

[0282] ​​​​​​​​​​The semiconductor layer can be a film represented by an In-M-Zn-based oxide containing, for example, metals such as indium, zinc, and M (aluminum, titanium, gallium, germanium, magnesium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or hafnium). When the metal oxide constituting the semiconductor layer is an In-M-Zn-based oxide, the atomic ratio of the metal elements of the sputtering target used to form the In-M-Zn oxide

[0283] is preferably such that In ≥ M and Zn ≥ M. Preferred atomic ratios of the metal elements of such a sputtering target include In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In :M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4. 1, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5: 1:8, etc. The atomic ratio of the semiconductor layer to be formed includes fluctuations of plus or minus 40% of the atomic ratio of the metal elements contained in the above sputtering target. As the semiconductor layer, a metal oxide film with a low carrier density is used. For example, the semiconductor layer has a carrier density of 1×10 / cm or less, preferably 1×10

[0284] / cm or less, more preferably 1×10 17 / cm 3 or less, still more preferably 1×10 15 / cm 3 or less, even more preferably 1×10 / cm 13 or less, and most preferably less than 1×10 3 / cm 11 and greater than or equal to 1×10 3 / cm of carriers. 10 / cm 3 When the carrier density is 1×10 -9 / cm 3 or more, the carrier Metal oxides with a density can be used. Such metal oxides are called high-purity genuine or substantially high-purity genuine metal oxides. It can be said that the metal oxide has a low density of defect levels and stable characteristics .

[0285] Note that it is not limited to these, and an oxide semiconductor with an appropriate composition may be used according to the semiconductor characteristics and electrical characteristics (field effect mobility, threshold voltage, etc.) of the required transistor. Also, in order to obtain the semiconductor characteristics of the required transistor, the carrier density, impurity concentration of the semiconductor layer, defect density, atomic number ratio of metal elements and oxygen, interatomic distance, density, etc. should be made appropriate .

[0286] In the metal oxide constituting the semiconductor layer, if silicon or carbon, which is one of the Group 14 elements, is contained, oxygen deficiency increases in the semiconductor layer and it becomes n-type. For this reason, the concentration of silicon or carbon (concentration obtained by secondary ion mass spectrometry) in the semiconductor layer should be 2× 10 18 atoms / cm 3 or less, preferably 2×10 17 atoms / cm 3 or less.

[0287] Also, when alkali metals and alkaline earth metals combine with the metal oxide, carriers may be generated , and the off-current of the transistor may increase. For this reason, the concentration of alkali metals or alkaline earth metals obtained by secondary ion mass spectrometry in the semiconductor layer should be 1×10 atoms / cm 18 or less, preferably 2×10 3 atoms / cm 16 or less, 3 and made to be 2×10

[0288] In addition, when nitrogen is contained in the metal oxide constituting the semiconductor layer, electrons as carriers are generated, the carrier density increases, and it tends to be n-type. As a result, a transistor using a metal oxide containing nitrogen tends to have normally-on characteristics. Therefore, the nitrogen concentration obtained by secondary ion mass spectrometry in the semiconductor layer is preferably 5×10 18 atoms / cm 3 or less.

[0289] Oxide semiconductors can be divided into single crystal oxide semiconductors and non-single crystal oxide semiconductors. Non- single crystal oxide semiconductors include CAAC-OS (c-axis-aligned cry stalline oxide semiconductor), polycrystalline oxide semiconductors, nc-OS (nanocrystalline oxide semiconducto r), pseudo-amorphous oxide semiconductors (a-like OS: amorphous-like oxide semiconductor), and amorphous oxide semiconductors.

[0290] In addition, CAC-OS (Cl oud-Aligned Composite oxide semiconducto r) may be used for the semiconductor layer of the transistor disclosed in one aspect of the present invention.

[0291] Note that the semiconductor layer of the transistor disclosed in one aspect of the present invention can preferably use the above-described non-single crystal oxide semiconductor or CAC-OS. In addition, as the non-single crystal oxide semiconductor, nc-OS or CAAC-OS can be preferably used.

[0292] ​In one aspect of the present invention, it is preferable to use CAC-OS as the semiconductor layer of the transistor. By using CAC-OS, high electrical characteristics or high reliability can be imparted to the transistor.

[0293] Note that the semiconductor layer may be a mixed film having two or more of the regions of CAAC-OS, polycrystalline oxide semiconductor, nc-OS, pseudo-amorphous oxide semiconductor, and amorphous oxide semiconductor. The mixed film may have, for example, a single-layer structure or a laminated structure including any two or more of the above-described regions.

[0294] Hereinafter, the configuration of CAC (Cloud-Aligned Composite)-OS that can be used for the transistor disclosed in one aspect of the present invention will be described.

[0295] CAC-OS is, for example, a structure of a material in which the elements constituting the metal oxide are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or in the vicinity thereof. Note that hereinafter, in the metal oxide, one or more metal elements are unevenly distributed, and the region having the metal element is mixed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or in the vicinity thereof, and this state is also referred to as a mosaic state or a patch state.

[0296] The metal oxide preferably contains at least indium. In particular, it preferably contains indium and zinc. In addition to these, aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium ​​​​​​​​​​​​Manium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum Contains one or more of the following: tantalum, tungsten, or magnesium. It's fine.

[0297] For example, CAC-OS in In-Ga-Zn oxide (In- The Ga-Zn oxide may be specifically referred to as CAC-IGZO. (hereinafter referred to as InO X1 (X1 is a real number greater than 0) or indium zinc oxide compound (hereinafter referred to as In X2 Zinc Y2 O Z2 (X2, Y2, and Z2 are real numbers greater than 0) ) and gallium oxide (GaO X3 (X3 is a real number greater than 0). ), or gallium zinc oxide (Ga X4 Zinc Y4 O Z4 (X4, Y4, and Z4 are The material is separated into mosaics, and the mosaic is created. Zinc-like InO X1 , or In X2 Zinc Y2 O Z2 The structure in which the ions are uniformly distributed in the film (see below) (Also called cloud-like.)

[0298] In other words, CAC-OS is X3 The region where In is the main component and X2 Zinc Y2 O Z2 , or InO X1 A composite metal oxide having a structure in which a region in which In this specification, for example, the atomic ratio of In to the element M in the first region is , the first region is considered to have a higher In concentration compared to the second region, where the atomic ratio of In to the elements M in the second region is greater. In terms of the concentration of In, the first region is higher compared to the second region.

[0299] Note that IGZO is a common name and refers to a compound composed of In, Ga, Zn, and O in some cases. As a representative example, InGaO3(ZnO) (m1 is a natural number), or In m1 (m1 is a natural number), or In (1 +x0) Ga (1-x0) O3(ZnO) m0 (-1 ≤ x0 ≤ 1, m0 is an arbitrary number) can be mentioned as crystalline compounds. The above crystalline compounds have a single crystal structure, a polycrystalline structure, or a CAAC structure. Note that

[0300] The CAAC structure is a crystal structure in which multiple IGZO nanocrystals have a c-axis orientation and are connected without orientation in the a-b plane. The CAAC structure is a crystal structure in which multiple IGZO nanocrystals have a c-axis orientation and are connected without orientation in the a-b plane. is a crystal structure in which multiple IGZO nanocrystals have a c-axis orientation and are connected without orientation in the a-b plane.

[0301] On the other hand, CAC-OS relates to the material composition of metal oxides. CAC-OS refers to a structure in which in a material composition containing In, Ga, Zn, and O, a region observed as nanoparticle-like with Ga as the main component and a region observed as nanoparticle-like with In as the main component are randomly dispersed in a mosaic pattern. Therefore, in CAC-OS, the crystal structure is a secondary element. a region observed as nanoparticle-like with Ga as the main component and a region observed as nanoparticle-like with In as the main component are randomly dispersed in a mosaic pattern. Therefore, in CAC-OS, the crystal structure is a secondary element. a region observed as nanoparticle-like with Ga as the main component and a region observed as nanoparticle-like with In as the main component are randomly dispersed in a mosaic pattern. Therefore, in CAC-OS, the crystal structure is a secondary element. a region observed as nanoparticle-like with Ga as the main component and a region observed as nanoparticle-like with In as the main component are randomly dispersed in a mosaic pattern. Therefore, in CAC-OS, the crystal structure is a secondary element. a region observed as nanoparticle-like with Ga as the main component and a region observed as nanoparticle-like with In as the main component are randomly dispersed in a mosaic pattern. Therefore, in CAC-OS, the crystal structure is a secondary element.

[0302] Note that CAC-OS does not include a laminated structure of two or more films with different compositions. For example, a structure consisting of two layers of a film with In as the main component and a film with Ga as the main component is not included. Note that CAC-OS does not include a laminated structure of two or more films with different compositions. For example, a structure consisting of two layers of a film with In as the main component and a film with Ga as the main component is not included. is not included.

[0303] Note that the region where GaO X3 is the main component and the region where In X2 ZnY2 O Z2 、 or InO X1 is There may be cases where no clear boundary can be observed in the region where it is the main component.

[0304] Note that when one or more selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, etc. are included instead of gallium, CAC-OS is observed in part as a region of nanoparticles mainly composed of the metal element and in part as a region of nanoparticles mainly composed of In, and they are randomly dispersed mosaically. This is what is meant by the structure.

[0305] CAC-OS can be formed by, for example, a sputtering method under conditions where the substrate is not heated. Also, when forming CAC-OS by the sputtering method, as the film-forming gas, any one or more selected from inert gases (typically argon), oxygen gas, and nitrogen gas may be used. Also, the lower the flow rate ratio of oxygen gas to the total flow rate of the film-forming gas during film formation, the more preferable it is. For example, the flow rate ratio of oxygen gas is preferably 0% or more and less than 30%, preferably 0% or more and 10% or less.

[0306] CAC-OS has the characteristic that no clear peak is observed when measured using the θ / 2θ scan by the Out-of-plane method, which is one of the X-ray diffraction (XRD) measurement methods. That is, from the X-ray diffraction measurement, it can be seen that there is no orientation in the a-b plane direction and the c-axis direction of the measurement region. ​​​​

[0307] In addition, CAC-OS uses an electron beam with a probe diameter of 1 nm (also called a nanobeam electron beam). In the electron beam diffraction pattern obtained by irradiating the sample, a ring-shaped region with high brightness and the corresponding Several bright spots are observed within the ring-shaped region. Therefore, the electron diffraction pattern indicates that CAC The crystal structure of -OS has no orientation in the planar direction and cross-sectional direction. It can be seen that the crystalline structure is o-crystal.

[0308] For example, in the CAC-OS of In-Ga-Zn oxide, the energy dispersive X Energy Dispersive X-ray spectroscopy (EDX) The EDX mapping obtained using scopy revealed that GaO X3 The area where is the main component And, In X2 Zinc Y2 O Z2 , or InO X1 The areas where the main component is It can be confirmed that the compound has the structure shown in FIG.

[0309] CAC-OS has a structure different from that of IGZO compounds in which metal elements are uniformly distributed. It has different properties from GZO compounds. That is, CAC-OS is GaO X3 The main components are and the region where In X2 Zinc Y2 O Z2 , or InO X1 The region where is the main component and The phase is separated into two layers, and the regions each containing one element as a main component are arranged in a mosaic pattern.

[0310] Here, In X2 Zinc Y2 O Z2 , or InO X1 The area where GaO is the main componentX3 is a region with high conductivity compared to a region where such as... are the main components. That is, In X2 Zn Y 2O Z2 , or InO X1 When the region where... is the main component allows carriers to flow, the conductivity as a metal oxide is manifested. Therefore, In Zn X2 Zn Y2 O Z2 , or InO X1 is the main component, and by being distributed in a cloud-like manner in the metal oxide, a high field-effect mobility ( μ) can be achieved.

[0311] On the other hand, a region where GaO X3 etc. are the main components is a region with high insulation compared to a region where In X2 Zn Y2 O Z2 , or InO X 1 is the main component. That is, when a region where GaO X3 etc. are the main components is distributed in the metal oxide, the leakage current can be suppressed and a good switching operation can be achieved.

[0312] Therefore, when CAC-OS is used in a semiconductor device, the insulation caused by GaO X3 etc. and , In X2 Zn Y2 O Z2 , or InO X1 etc. act complementarily, and as a result, a high on-current (I on ), and a high field-effect mobility (μ) can be achieved.

[0313] Also, a semiconductor device using CAC-OS has high reliability. Therefore, CAC-OS is optimal for various semiconductor devices including displays.​

[0314] In addition, a transistor having a CAC-OS semiconductor layer has high field-effect mobility and Because of its high dynamic capability, the transistor is connected to a driving circuit, typically a scanning transistor which generates a gate signal. By using this in a line driver circuit, a display device with a narrow frame width can be provided. The transistor is connected to a signal line driver circuit (particularly, a shift register (SLC)) of the display device. By using it as a demultiplexer connected to the output terminal of a display device, It is possible to provide a display device with a small number of wirings.

[0315] In addition, the transistor with CAC-OS in the semiconductor layer is a transistor using low-temperature polysilicon. Unlike conventional transistors, no laser crystallization process is required. It is possible to reduce the manufacturing cost even for ultra-high visibility display devices. ("4K resolution", "4K2K", "4K"), Super Hi-Vision ("8K resolution" In the case of large-scale display devices with high resolution such as 1080p, 1080p, 8K4K, and 8K, By using transistors having CAC-OS in the semiconductor layer for the driver circuits and display section, This is preferable because it is possible to write in a short time and reduce display defects.

[0316] Alternatively, silicon may be used as the semiconductor in which the channel of the transistor is formed. Although amorphous silicon may be used as the silicon, it is particularly preferable to use silicon having crystallinity. For example, it is preferable to use microcrystalline silicon, polycrystalline silicon, single crystal silicon, etc. In particular, polycrystalline silicon can be formed at a lower temperature than single crystal silicon, and has a higher field-effect mobility and higher reliability compared to amorphous silicon.

[0317] This embodiment can be implemented in appropriate combination with at least some of the other embodiments described in this specification. and implemented in combination with each other.

Explanation of Reference Numerals

[0318] FN1: Node, FN2: Node, G1: Signal line, G2: Signal line, G3: Signal line, G4 : Signal line, G5: Signal line, IM1: Input terminal, IM2: Input terminal, IP1: Input terminal, I P2: Input terminal, MN1: Wiring, N1: Node, N2: Node, N3: Node, N4: No de, N5: Node, N6: Node, OM1: Output terminal, OM2: Output terminal, OP1: Out put terminal, OP2: Output terminal, V1: Power supply line, V2: Power supply line, V3: Power supply line, V4: Power supply line , V4A: Power supply line, V5: Power supply line, V5A: Power supply line, V6: Power supply line, V7: Power supply line, V8 : Power supply line, Vre1: Program potential, Vref1: Program potential, Vref1A: Pro gram potential, Vref2: Program potential, Vref2A: Program potential, Vref 3: Preset potential, Vref4: Preset potential, 10: Receiving circuit, 10A: Receiving circuit , 11: Operational amplifier, 11A: Operational amplifier, 11A1: Input terminal, 11A2: Input terminal, 11A3: Output terminal, 11A4: Output terminal, 11B: Operational amplifier, 11B1: Operational amplifier , 12: Transistor, 12A: Element, 12B: Element, 12C: Element, 13A: Element, 1 3B: Element, 13C: Element, 14: Circuit, 14A: Circuit, 14B: Circuit, 14C: Circuit, 14C1: Circuit, 15: Light-emitting element, 15A: Transistor, 15B: Transistor, 16 A: Transistor, 16B: Transistor, 17a: Transistor, 17A: Transistor Ta, 17B: Transistor, 18: Resistor element, 19a: Input terminal, 19A: Transistor , 19b: Input terminal, 19B: Transistor, 19c: Output terminal, 19d: Output terminal, 1 9e: Input terminal, 19f: Input terminal, 19g: Output terminal, 19h: Input terminal, 20A: Circuit , 20B: Circuit, 21A: Transistor, 21B: Transistor, 22A: Transistor , 22B: Transistor, 23A: Transistor, 23B: Transistor, 23C: Capacitor element , 24A: Transistor, 24B: Transistor, 24C: Transistor, 24D : Capacitor element, 24E: Transistor, 24F: Transistor, 24G: Transistor, 2 4H: Capacitor element, 31: Transistor, 32: Transistor, 33: Transistor, 34 : Transistor, 35: Transistor, 36: Transistor, 37: Transistor, 38 : Capacitor element, 39: Capacitor element, 41: Transistor, 42: Transistor, 43: Transistor , 44: Transistor, 45: Capacitor element, 46: Capacitor element, 47: Light-emitting element, 50 : Receiving circuit, 51: Control unit, 52: Control unit, 53: Transmitting circuit, 54: Receiving circuit, 55: Transmission line , 56: Transmission line, 57: Resistor element, 100: Electronic device, 101: Control unit, 102: Processor , 103: Communication circuit, 104: Input / output circuit, 105: Storage, 106: Memory , 110: Display device, 111: Display controller, 112: Control unit, 112A : Arithmetic unit, 112B: Timing generation circuit, 113: Frame memory, 114: Driver circuit , 121: Display panel, 122: Source driver circuit, 123: Gate driver circuit , 124: Display unit, 124A: Pixel, 124B: Pixel

Claims

【Claim 1】 A receiving circuit that converts a first signal and a second signal given in a differential manner into a third signal in a single-ended manner and outputs the converted signal, comprising: an operational amplifier, a first element, a first transistor, and a first circuit; the operational amplifier has a first input terminal, a second input terminal, and a first output terminal; the operational amplifier is electrically connected to the first element; the first element is electrically connected to the first circuit via a first node; one of the source or drain of the first transistor is electrically connected to the first node; the first signal is applied to the first input terminal; the second signal obtained by inverting the first signal is applied to the second input terminal; the operational amplifier applies the signal output from the first output terminal to the first element; a first preset potential is applied to the first node via the first transistor; the first element stores a signal including the variation of the operational amplifier by the first preset potential; the first circuit determines an initial value of the third signal without being affected by the signal including the variation of the operational amplifier when the first preset potential is applied. A receiving circuit characterized by this.

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