Semiconductor device

Abstract

To prevent a transistor from malfunctioning during a non-selective period by suppressing fluctuations in the threshold voltage of the transistor, in a shift register.SOLUTION: In a pulse output circuit provided on a shift register, electric potential is supplied periodically to a gate electrode of a transistor which is in a floating state such that the gate electrode is turned on during a non-selective period where a pulse is not output. In addition, the electric potential is supplied to the gate electrode of the transistor by periodically turning on or off other transistors.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a pulse output circuit, a shift register, and a display device having the shift register, a semiconductor device, and an electronic device, and particularly to a pulse output circuit, a shift register, a display device, a semiconductor device, and an electronic device configured by a single-conductive type thin film transistor (TFT).

Background Art

[0002] In recent years, there has been progress in the development of a display device in which a circuit is formed using a thin film transistor (hereinafter also referred to as "TFT") formed of a semiconductor thin film on an insulator, particularly on a glass or plastic substrate, and particularly an active matrix type display device. The active matrix type display device formed using TFTs has hundreds of thousands to millions of pixels arranged in a matrix, and the charge of each pixel is controlled by the TFTs arranged in each pixel to display an image.

[0003] Furthermore, as a recent technology, a method of simultaneously forming a drive circuit using TFTs in the peripheral region of the pixel portion in addition to the pixel TFTs constituting the pixel has been developed, which has greatly contributed to the reduction in size, thickness, and power consumption of the device. Along with this, in recent years, the application fields of such devices have been significantly expanded, and they have become indispensable devices for display units of portable information terminals,

[0004] Generally, as a circuit constituting the drive circuit of a display device, a CMOS circuit combining an N-type TFT and a P-type TFT is used. The characteristics of a CMOS circuit are that the logic changes from a H (High) level to an L (Low) level, or from an L level to a H level, Current flows only instantaneously from L to the H level, and ideally no current flows during the holding of a certain logic (in reality, there is a small leakage current), so the power consumption of the entire circuit can be very low This makes it possible to significantly suppress the power consumption of the entire circuit. Also, since the TFTs with opposite polarities operate complementarily, high-speed operation is possible.

[0005] However, considering the manufacturing process, CMOS circuits involve complicated processes such as ion doping, and the large number of processes directly affects the manufacturing cost. Therefore, a circuit that was conventionally composed of CMOS circuits is proposed to be composed of either N-type or P-type unipolar TFTs and achieve high-speed operation comparable to that of CMOS circuits (for example, see Patent Document 1).

[0006] As shown in FIGS. 7(A) to 7(C), the circuit described in Patent Document 1 temporarily floats the gate electrode of the TFT2050 electrically connected to the output terminal, and utilizes the capacitive coupling between the gate and source of the TFT2050 to make the potential of the gate electrode higher than the power supply potential. As a result, an output without amplitude attenuation can be obtained without causing a voltage drop due to the threshold value of the TFT2050. 2010, 2020, 2030, 2040, and 2060 are TFTs, 2070 is a capacitive element, 2100 is the first amplitude compensation circuit, and 2200 is the second amplitude compensation circuit.

[0007] Such an operation in the TFT2050 is called a bootstrap operation. By this operation, an output pulse can be obtained without causing a voltage drop due to the threshold value of the TFT.

[0008] ​​​​​​​​​​Also, in the circuits shown in FIGS. 7(A) to (C), during the period when there is no pulse input / output, the TF gate electrodes of T2050 and 2060 are both in a floating state, causing potential fluctuations such as noise at node α. To solve this problem, during the period when there is no pulse input / output, T FT1020 and 1060 are turned on and set to a floating state to reduce the noise generated at node α (see FIGS. 8(A) to (C)) (for example, refer to Patent Document 2 ). 1010, 1030, 1040, and 1050 are TFTs, 1070 is a capacitive element, 1100 is a first amplitude compensation circuit, and 1200 is a second amplitude compensation circuit.

Prior Art Documents

Patent Documents

Patent Document 1

[0009]

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

Overview of the Invention

Problems to be Solved by the Invention

[0010] In FIG. 8, when paying attention to SROut1, after the pulse is output, eventually CK1 changes from the H level to the L level. Along with this, the potential of SROut1 also begins to decline. On the other hand, at the timing when C K2 becomes the H level, the same operation as described above is also performed in the second stage, and a pulse is output to SR Out2. This pulse is input to the input terminal 3 in the first stage, and TFT1030 is turned on. As a result, the electric potential of the gate electrodes of TFT1020 and 1060 rises and they turn on. Along with this, the potential of the gate electrode of TFT1050, and SRO the potential of the gate electrode of TFT1050, and SRO The potential of ut1 drops. After that, when the output of SROut2 changes from H level to L level, At this moment, the gate electrodes of the TFTs 1020 and 1060 are turned off. After that, this state continues in the first stage until the next SP is input. This will be the case.

[0011] Thus, in the circuits of Figs. 8(A) and 8(B), node β has no pulse input or output. For example, the circuits in Fig. 8(A) and 8(B) are used as a scan driver. When using TF as a TF, it is necessary to hold the potential of node β for about one frame. The channel widths of T1040 and TFT1060 are relatively large, so the off-current is also high. At this time, the potential of node β drops due to the off-current of TFT1040 and TFT1060. The TFT1060 may turn off. This may result in capacitive coupling to the clock signal. There is a greater possibility of malfunction.

[0012] Also, when a pulse is output from the TFT 1050, the node β is in a floating state. Therefore, when the potential of node γ rises from the L level to the H level, the The potential of β may increase. As a result, the TFT1020 may turn on and malfunction. This potential fluctuation is much smaller than the amplitude of a normal pulse, so the potential fluctuation If the voltage fluctuation is smaller than the threshold voltage of the TFT1020, this is not a problem. If it exceeds the threshold of T1020, the potential of node α will drop and cause malfunction. In particular, when amorphous silicon is used for the TFT, the gate insulating film In many cases, a nitride film is used for the transistor, and the threshold voltage may vary. As a result, the pulse output circuit is likely to malfunction.

[0013] Also, when using amorphous silicon as the TFT, compared with the TFT using polysilicon, since the electrical characteristics are inferior, it is difficult to obtain sufficient driving ability, and the threshold value shifts depending on the voltage conditions. Therefore, the circuit technology for forming a drive circuit for driving pixels using the TFT with amorphous silicon has become a problem. The invention disclosed in this specification aims to provide a pulse output circuit, a shift register, and a display device that reduce malfunction within a circuit and guarantee more reliable operation by solving one or more of such problems.

[0014] The invention disclosed in this specification aims to provide a pulse output circuit, a shift register, and a display device that reduce malfunction within a circuit and guarantee more reliable operation by solving one or more of such problems. reduce malfunction within the circuit and guarantee more reliable operation. The purpose is to provide a pulse output circuit, a shift register, and a display device.

Means for Solving the Problem

[0015] The pulse output circuit of the present invention is characterized in that a potential is periodically supplied to the gate electrode of a transistor that is in a floating state so that the gate electrode is turned on during a non-selection period when no pulse is output. Also, the supply of the potential to the gate electrode of the transistor is characterized by being performed by periodically turning on or off other transistors. Also, the supply of the potential to the gate electrode of the transistor is characterized by being performed by periodically turning on or off other transistors. The shift register of the present invention is characterized by being driven such that the pulse output from the m-th pulse output circuit and the pulse output from the (m + 1)-th pulse output circuit overlap by half (for a half cycle). Hereinafter, the specific

[0016] configurations of the shift register and the pulse output circuit of the present invention will be described. configurations of the shift register and the pulse output circuit of the present invention will be described. The shift register of the present invention includes a (m - 2)-th pulse output circuit, a (m - 1)-th pulse output circuit.

[0017] The shift register of the present invention includes a (m - 2)-th pulse output circuit, a (m - 1)-th pulse output A force circuit, an m-th pulse output circuit, an (m + 1)-th pulse output circuit, and an (m + 2)-th pulse output circuit (m ≧ 3), including at least a plurality of pulse output circuits, and a first signal line to a fourth signal line for outputting a clock signal. The pulse output circuit has a first input terminal to a sixth input terminal and an output terminal. In the m-th pulse output circuit, the first input terminal to the third input terminal are electrically connected to three different signal lines among the first signal line to the fourth signal line, the fourth input terminal is electrically connected to the output terminal of the (m - 2)-th pulse output circuit, the fifth input terminal is electrically connected to the output terminal of the (m - 1)-th pulse output circuit, the sixth input terminal is electrically connected to the output terminal of the (m + 2)-th pulse output circuit, and the output terminal is electrically connected to the sixth input terminal of the (m - 2)-th pulse output circuit, the fifth input terminal of the (m + 1)-th pulse output circuit, and the fourth input terminal of the (m + 2)-th pulse output circuit. The pulse output circuit of the present invention has a first transistor to a ninth transistor. The first transistor has its first electrode electrically connected to the first power line, its second electrode electrically connected to the gate electrode of the third transistor, and its gate electrode electrically connected to the fourth input terminal. The second transistor has its first electrode electrically connected to the second power line, its second electrode electrically connected to the gate electrode of the third transistor, and its gate electrode electrically connected to the gate electrode of the fourth transistor. The third transistor has its first electrode electrically connected to the first input terminal and its second electrode electrically connected to the output terminal. The fourth transistor has its first electrode electrically connected to the third power line and its second electrode electrically connected to the output terminal. The pulse output circuit has a first input terminal to a sixth input terminal and an output terminal. In the m-th pulse output circuit, the first input terminal to the third input terminal are electrically connected to three different signal lines among the first signal line to the fourth signal line, the fourth input terminal is electrically connected to the output terminal of the (m - 2)-th pulse output circuit, the fifth input terminal is electrically connected to the output terminal of the (m - 1)-th pulse output circuit, the sixth input terminal is electrically connected to the output terminal of the (m + 2)-th pulse output circuit, and the output terminal is electrically connected to the sixth input terminal of the (m - 2)-th pulse output circuit, the fifth input terminal of the (m + 1)-th pulse output circuit, and the fourth input terminal of the (m + 2)-th pulse output circuit. The pulse output circuit has a first input terminal to a sixth input terminal and an output terminal. In the m-th pulse output circuit, the first input terminal to the third input terminal are electrically connected to three different signal lines among the first signal line to the fourth signal line, the fourth input terminal is electrically connected to the output terminal of the (m - 2)-th pulse output circuit, the fifth input terminal is electrically connected to the output terminal of the (m - 1)-th pulse output circuit, the sixth input terminal is electrically connected to the output terminal of the (m + 2)-th pulse output circuit, and the output terminal is electrically connected to the sixth input terminal of the (m - 2)-th pulse output circuit, the fifth input terminal of the (m + 1)-th pulse output circuit, and the fourth input terminal of the (m + 2)-th pulse output circuit. The first input terminal to the third input terminal are electrically connected to three different signal lines among the first signal line to the fourth signal line, the fourth input terminal is electrically connected to the output terminal of the (m - 2)-th pulse output circuit, the fifth input terminal is electrically connected to the output terminal of the (m - 1)-th pulse output circuit, the sixth input terminal is electrically connected to the output terminal of the (m + 2)-th pulse output circuit, and the output terminal is electrically connected to the sixth input terminal of the (m - 2)-th pulse output circuit, the fifth input terminal of the (m + 1)-th pulse output circuit, and the fourth input terminal of the (m + 2)-th pulse output circuit. The fourth input terminal is electrically connected to the output terminal of the (m - 2)-th pulse output circuit, the fifth input terminal is electrically connected to the output terminal of the (m - 1)-th pulse output circuit, the sixth input terminal is electrically connected to the output terminal of the (m + 2)-th pulse output circuit, and the output terminal is electrically connected to the sixth input terminal of the (m - 2)-th pulse output circuit, the fifth input terminal of the (m + 1)-th pulse output circuit, and the fourth input terminal of the (m + 2)-th pulse output circuit. The fourth input terminal is electrically connected to the output terminal of the (m - 2)-th pulse output circuit, the fifth input terminal is electrically connected to the output terminal of the (m - 1)-th pulse output circuit, the sixth input terminal is electrically connected to the output terminal of the (m + 2)-th pulse output circuit, and the output terminal is electrically connected to the sixth input terminal of the (m - 2)-th pulse output circuit, the fifth input terminal of the (m + 1)-th pulse output circuit, and the fourth input terminal of the (m + 2)-th pulse output circuit. The sixth input terminal is electrically connected to the output terminal of the (m + 2)-th pulse output circuit, and the output terminal is electrically connected to the sixth input terminal of the (m - 2)-th pulse output circuit, the fifth input terminal of the (m + 1)-th pulse output circuit, and the fourth input terminal of the (m + 2)-th pulse output circuit. The output terminal is electrically connected to the sixth input terminal of the (m - 2)-th pulse output circuit, the fifth input terminal of the (m + 1)-th pulse output circuit, and the fourth input terminal of the (m + 2)-th pulse output circuit. The output terminal is electrically connected to the sixth input terminal of the (m - 2)-th pulse output circuit, the fifth input terminal of the (m + 1)-th pulse output circuit, and the fourth input terminal of the (m + 2)-th pulse output circuit. It is characterized by the above.

[0018] The pulse output circuit of the present invention has a first transistor to a ninth transistor. The first transistor has its first electrode electrically connected to the first power line, its second electrode electrically connected to the gate electrode of the third transistor, and its gate electrode electrically connected to the fourth input terminal. The second transistor has its first electrode electrically connected to the second power line, its second electrode electrically connected to the gate electrode of the third transistor, and its gate electrode electrically connected to the gate electrode of the fourth transistor. The third transistor has its first electrode electrically connected to the first input terminal and its second electrode electrically connected to the output terminal. The fourth transistor has its first electrode electrically connected to the third power line and its second electrode electrically connected to the output terminal. The first transistor has its first electrode electrically connected to the first power line, its second electrode electrically connected to the gate electrode of the third transistor, and its gate electrode electrically connected to the fourth input terminal. The first transistor has its first electrode electrically connected to the first power line, its second electrode electrically connected to the gate electrode of the third transistor, and its gate electrode electrically connected to the fourth input terminal. The second transistor has its first electrode electrically connected to the second power line, its second electrode electrically connected to the gate electrode of the third transistor, and its gate electrode electrically connected to the gate electrode of the fourth transistor. The second transistor has its first electrode electrically connected to the second power line, its second electrode electrically connected to the gate electrode of the third transistor, and its gate electrode electrically connected to the gate electrode of the fourth transistor. The third transistor has its first electrode electrically connected to the first input terminal and its second electrode electrically connected to the output terminal. The third transistor has its first electrode electrically connected to the first input terminal and its second electrode electrically connected to the output terminal. The fourth transistor has its first electrode electrically connected to the third power line and its second electrode electrically connected to the output terminal. is connected, and the fifth transistor has its first electrode electrically connected to the fourth power line, its second electrode electrically connected to the gate electrodes of the second transistor and the fourth transistor, its gate electrode electrically connected to the fourth input terminal, and the sixth transistor has its first electrode electrically connected to the fourth power line, its second electrode electrically connected to the gate electrodes of the second transistor and the fourth transistor, its gate electrode electrically connected to the fifth input terminal, the seventh transistor has its first electrode electrically connected to the fifth power line, its second electrode electrically connected to the gate electrodes of the second transistor and the fourth transistor, its gate electrode electrically connected to the sixth input terminal, the eighth transistor has its first electrode electrically connected to the fifth power line, its second electrode electrically connected to the second electrode of the ninth transistor, its gate electrode electrically connected to the second input terminal, the ninth transistor has its first electrode electrically connected to the gate electrodes of the second transistor and the fourth transistor, its gate electrode electrically connected to the third input terminal, and is characterized by the above. The display device of the present invention has pixels and a shift register for driving the pixels. The shift register has at least a plurality of pulse output circuits including a (m - 2)-th pulse output circuit, a (m - 1)-th pulse output circuit, an m-th pulse output circuit, a (m + 1)-th pulse output circuit, and a (m + 2)-th pulse output circuit (m ≥ 3), and has first to fourth signal lines for outputting a clock signal. The pulse output circuit has first to sixth input terminals and an output terminal.

[0019] The display device of the present invention has pixels and a shift register for driving the pixels. The shift register has at least a plurality of pulse output circuits including a (m - 2)-th pulse output circuit, a (m - 1)-th pulse output circuit, an m-th pulse output circuit, a (m + 1)-th pulse output circuit, and a (m + 2)-th pulse output circuit (m ≥ 3), and has first to fourth signal lines for outputting a clock signal. The pulse output circuit has first to sixth input terminals and an output terminal. has at least a plurality of pulse output circuits including a (m - 2)-th pulse output circuit, a (m - 1)-th pulse output circuit, an m-th pulse output circuit, a (m + 1)-th pulse output circuit, and a (m + 2)-th pulse output circuit (m ≥ 3), and has first to fourth signal lines for outputting a clock signal. The pulse output circuit has first to sixth input terminals and an output terminal. In the m-th pulse output circuit, the first to third input terminals are electrically connected to any one of the first to fourth signal lines, and the fourth input terminal is electrically connected to the output terminal of the (m - 2)-th pulse output circuit, the fifth input terminal is electrically connected to the output terminal of the (m - 1)-th pulse output circuit, the sixth input terminal is electrically connected to the output terminal of the (m + 2)-th pulse output circuit, and the output terminal is electrically connected to the sixth input terminal of the (m - 2)-th pulse output circuit, the fifth input terminal of the (m + 1)-th pulse output circuit, and the fourth input terminal of the (m + 2)-th pulse output circuit.

Advantages of the Invention

[0020] According to the present invention, by periodically supplying a potential to the gate electrode of a transistor that is in a floating state during a non-selection period when no pulse input / output is performed, malfunction of the pulse output circuit can be suppressed.

[0021] Also, by using a driving method in which the pulse output from the m-th pulse output circuit and the pulse output from the (m + 1)-th pulse output circuit overlap by half (for a half cycle), a large load can be applied, and a pulse output circuit that operates at a high frequency can be provided.

Brief Description of the Drawings

[0022]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Embodiments for Carrying Out the Invention

[0023] Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention can be implemented in many different modes, and it will be easily understood by those skilled in the art that the form and details thereof can be variously changed without departing from the spirit and scope of the present invention. Therefore it should not be construed as being limited to the description content of the present embodiment. In the configuration of the present invention described below, reference numerals indicating the same objects are common among different drawings. In the configuration of the present invention described below, reference numerals indicating the same objects are common among different drawings.

[0024] (Embodiment 1) In this embodiment, a pulse output circuit of the present invention and a shift register including the pulse output circuit will be described with reference to the drawings for an example thereof.

[0025] The shift register shown in this embodiment includes a first pulse output circuit 10 _1 to an n-th pulse output circuit 10 _n (n ≧ 3), and first to fourth signal lines 11 to 14 that output clock signals (see FIG. 1(A)). The first signal line 11 outputs a first clock signal (CK 1), the second signal line 12 outputs a second clock signal (CK2), the third signal line 13 outputs a third clock signal (CK3), and the fourth signal line 14 outputs a fourth clock signal (CK4).

[0026] The clock signal (CK) is a signal that repeats H (High) signals and L (Low) signals at regular intervals. Here, the first to fourth clock signals (CK 1 to CK4) are delayed by 1 / 2 cycle in order. In this embodiment, the first to fourth clock signals (CK 1 to CK4) are used to control the driving of the pulse output circuit and the like.

[0027] Each of the first to n-th pulse output circuits 10 _1 to 10 has a first input _n terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a fifth input terminal 25, a sixth input terminal 26, and an output terminal 27 (see FIG. 1(B)).

[0028] The first input terminal 21, the second input terminal 22, and the third input terminal 23 are connected to the first signal line 1 It is electrically connected to any one of the first to fourth signal lines 14. For example, in FIG. 1, the first pulse output circuit 10 _1 has its first input terminal 21 electrically connected to the first signal line 11, its second input terminal 22 electrically connected to the second signal line 12, and its third input terminal 23 electrically connected to the third signal line 13. Also, the second pulse output circuit 10 _2 has its first input terminal 21 electrically connected to the second signal line 12, its second input terminal 22 electrically connected to the third signal line 13, and its third input terminal 23 electrically connected to the fourth signal line 14.

[0029] Also, in the m-th pulse output circuit (m≥3) of the shift register shown in this embodiment, the fourth input terminal 24 is electrically connected to the output terminal 27 of the (m - 2)-th pulse output circuit and the fifth input terminal 25 of the (m - 1)-th pulse output circuit. The fifth input terminal 25 is electrically connected to the output terminal 27 of the ( m - 1)-th pulse output circuit and the fourth input terminal 24 of the (m + 1)-th pulse output circuit. The sixth input terminal 26 is electrically connected to the output terminal 27 of the (m + 2)-th pulse output circuit. The output terminal 27 is electrically connected to the sixth input terminal 26 of the (m - 2)-th pulse output circuit, the fifth input terminal 25 of the (m + 1)-th pulse output circuit, and the fourth input terminal 24 of the (m + 2)-th pulse output circuit, and outputs a signal to OUT(m). For example, in the third pulse output circuit 10

[0030] _3 _1 _2 output circuit 10 _1 and the fifth input terminal of the second pulse output circuit 10 _2 and is electrically is connected, and the fifth input terminal 25 is the second pulse output circuit 10 _2 of the output terminal and the fourth pulse output circuit 10 _4 is electrically connected to the fourth input terminal of, and the sixth input terminal 26 is the fifth pulse output circuit 10 _5 is electrically connected to the output terminal of, and the output terminal is the first pulse output circuit 10 _1 of the sixth input terminal, the fourth pulse output circuit 10 _4 of the fifth input terminal and and the fourth input terminal of the fifth pulse output circuit 10 _5 are electrically connected. Also, in the third pulse output circuit 10 _3 the fourth input terminal 24 is the first pulse output circuit 10 _1 the signal output from the output terminal of is input, and the fifth input terminal 25 is the second pulse output circuit 10 _2 the signal output from the output terminal of is input, and the sixth input terminal 26 is the fifth pa lse output circuit 10 _5 the signal output from the output terminal of is input, and the signal output from the output terminal 27 is the first pulse output circuit 10 _1 of the sixth input terminal, the fourth pulse output circuit 1 0 _4 of the fifth input terminal and the fourth input terminal of the fifth pulse output circuit 10 _5 is input to it.

[0031] Also, in the first pulse output circuit, a first start pulse (SP 1) is input to the fourth input terminal 24, and a second start pulse (SP2) is input to the fifth input terminal 25.

[0032] Next, the specific configuration of the first pulse output circuit 10 _1 ~ the nth pulse output circuit 10 _n will be described. will be described.

[0033] The first pulse output circuit 10 _1 ~ the nth pulse output circuit 10 _n each has a first transistor 101 to the ninth transistor 109, a first capacitor element 111, and a second capacitor element 112 (see Fig. 1(C)). In addition to the first input terminal 21 to the sixth input terminal 26 and the output terminal 27 described above, signals are supplied from the first power supply line 31 to the sixth power supply line 36 to the first transistor 101 to the ninth transistor 109.

[0034] The first transistor 101 has one of its first electrodes (either the source electrode or the drain electrode) electrically connected to the first power supply line 31, and the second electrode (the other of the source electrode or the drain electrode) is electrically connected to the gate electrode of the third transistor 103 and the second electrode of the second capacitor element 112, and the gate electrode is electrically connected to the fourth input terminal 24. The second transistor 102 has its first electrode electrically connected to the second power supply line 32, and the second electrode is electrically connected to the gate electrode of the third transistor 103, and the gate electrode is electrically connected to the gate electrode of the fourth transistor 104. The third transistor 103 has its first electrode electrically connected to the first input terminal 21, and the second electrode is electrically connected to the output terminal 27 . The fourth transistor 104 has its first electrode electrically connected to the third power supply line 33, and the second electrode is electrically connected to the output terminal 27. The fifth transistor 105 has its first electrode electrically connected to the fourth power supply line 34, and the second electrode is electrically connected to the gate electrode of the second transistor 102 and the gate electrode of the fourth transistor 104, and the second electrode is electrically connected to the gate electrode of the second transistor 102 and the gate electrode of the fourth transistor 104, and the second electrode is electrically connected to the gate electrode of the second transistor 102 and the gate electrode of the fourth transistor 104, is provided, and the gate electrode is electrically connected to the fourth input terminal 24. The sixth transistor 106 has its first electrode electrically connected to the fourth power supply line 34, and its second electrode electrically connected to the gate electrodes of the second transistor 102 and the fourth transistor 104, and the gate electrode is electrically connected to the fifth input terminal 25. The seventh transistor 107 has its first electrode electrically connected to the fifth power supply line 35, and its second electrode electrically connected to the gate electrodes of the second transistor 102 and the fourth transistor 104, and the gate electrode is electrically connected to the sixth input terminal 26. The eighth transistor 108 has its first electrode electrically connected to the fifth power supply line 35, and its second electrode electrically connected to the second electrode of the ninth transistor 109, and the gate electrode is electrically connected to the second input terminal 22. The ninth transistor 109 has its first electrode electrically connected to the gate electrodes of the second transistor 102 and the fourth transistor 104, and the gate electrode is electrically connected to the third input terminal 23. The first capacitor 111 has its first electrode electrically connected to the sixth power supply line 36, and its second electrode electrically connected to the gate electrodes of the second transistor 102 and the fourth transistor 104. The second capacitor 112 has its first electrode electrically connected to the output terminal 27, and its second electrode electrically connected to the second electrode of the first transistor 101 and the gate electrode of the third transistor 103. In FIG. 1(C), the second electrode of the first transistor 101, the second electrode of the second transistor 102, the gate electrode of the third transistor 103, the second electrode of the second capacitor 112 is provided, and the gate electrode is electrically connected to the fourth input terminal 24. The sixth transistor 106 has its first electrode electrically connected to the fourth power supply line 34, and its second electrode electrically connected to the gate electrodes of the second transistor 102 and the fourth transistor 104, and the gate electrode is electrically connected to the fifth input terminal 25. The seventh transistor 107 has its first electrode electrically connected to the fifth power supply line 35, and its second electrode electrically connected to the gate electrodes of the second transistor 102 and the fourth transistor 104, and the gate electrode is electrically connected to the sixth input terminal 26. The eighth transistor 108 has its first electrode electrically connected to the fifth power supply line 35, and its second electrode electrically connected to the second electrode of the ninth transistor

[0035] In FIG. 1(C), the second electrode of the first transistor 101, the second electrode of the second transistor 1 02, the gate electrode of the third transistor 103, the second electrode of the second capacitor 112 Let the connection point of the electrode of 2 be node A. Also, the gate electrode of the second transistor 102, the gate electrode of the fourth transistor 104, the second electrode of the fifth transistor 105, the sixth the second electrode of the transistor 106, the second electrode of the seventh transistor 107, the first electrode of the ninth transistor 109, and the connection point of the second electrode of the first capacitor element 111 be node B. Also, the second electrode of the third transistor 103, the second electrode of the fourth transistor 104, the first electrode of the second capacitor element 112, and the connection point of the output terminal 27 be node C .

[0036] Next, the operation of the shift register shown in FIG. 1 will be described with reference to FIGS. 2 to 4. Specifically, in the timing chart of FIG. 2, it will be described by dividing it into a first period 51, a second period 52, a third period 53, a fourth period 54, and a fifth period 55. In the following description, the first transistor 101 to the ninth transistor 109 are N-channel thin-film transistors, and it is assumed that they are in a conductive state when the voltage between the gate and the source (Vgs) exceeds the threshold voltage (Vth).

[0037] Also, here, the output of the second pulse output circuit 10 _2 will be described. The second pulse output circuit 10 _2 is electrically connected to the second signal line 12 to which the first input terminal 21 supplies the second clock signal (CK2), and the second input terminal 22 is electrically connected to the third signal line 13 to which the third clock signal (CK 3) is supplied, and the third input terminal 23 is electrically connected to the fourth signal line 14 to which the fourth clock signal (CK 4) is supplied.

[0038] Note that a potential of V1 (VDD) is supplied to the first power line 31 and the fifth power line 35, and a potential of V2 (VSS) is supplied to the second power line 32 to the fourth power line 34 and the sixth power line 36. Here, let V1 > V2. Also, the first clock signal (CK1) to the fourth clock signal (CK4) are signals that repeat between the H level and the L level at regular intervals. Assume that it is VDD when at the H level and VSS when at the L level. Also, for simplicity of explanation here, let VSS = 0, but it is not limited to this. It is assumed that a potential of V2 (VSS) is supplied to the second power line 32 to the fourth power line 34 and the sixth power line 36. Here, let V1 > V2. Also, the first clock signal (CK1) to the fourth clock signal (CK4) are signals that repeat between the H level and the L level at regular intervals. It is assumed that it is VDD when at the H level and VSS when at the L level. Also, for simplicity of explanation here, let VSS = 0, but it is not limited to this. Note that a potential of V1 (VDD) is supplied to the first power line 31 and the fifth power line 35, and a potential of V2 (VSS) is supplied to the second power line 32 to the fourth power line 34 and the sixth power line 36. Here, let V1 > V2. Also, the first clock signal (CK1) to the fourth clock signal (CK4) are signals that repeat between the H level and the L level at regular intervals. It is assumed that it is VDD when at the H level and VSS when at the L level. Also, for simplicity of explanation here, let VSS = 0, but it is not limited to this.

[0039] In the first period 51, the second start pulse (SP2) becomes the H level, and the first transistor 101 and the fifth transistor 105, which are electrically connected to the fourth input terminal 24 of the second pulse output circuit 10, turn on. Since the third clock signal (CK3) and the fourth clock signal (CK4) are also at the H level, the eighth transistor 108 and the ninth transistor 109 also turn on (see Fig. 3(A)). The second pulse output circuit 10 _2 The first transistor 101 and the fifth transistor 105, which are electrically connected to the fourth input terminal 24 of the second pulse output circuit 10, turn on. Since the third clock signal (CK3) and the fourth clock signal (CK4) are also at the H level, the eighth transistor 108 and the ninth transistor 109 also turn on (see Fig. 3(A)). Since the third clock signal (CK3) and the fourth clock signal (CK4) are also at the H level, the eighth transistor 108 and the ninth transistor 109 also turn on (see Fig. 3(A)). At this time, since the first transistor 101 is on, the potential of node A rises. Also, a through current flows between the fifth power line 35 and the fourth power line 34, but by adjusting the transistor sizes, the potential of node B is controlled so that the second transistor 102 is in the off state. For example, it is realized by making the channel width of the fifth transistor 105 (the width of the channel in the direction perpendicular to the direction in which carriers flow between the source region and the drain region) larger than that of the eighth transistor 108 and the ninth transistor 109.

[0040] At this time, since the first transistor 101 is on, the potential of node A rises. Also, a through current flows between the fifth power line 35 and the fourth power line 34, but by adjusting the transistor sizes, the potential of node B is controlled so that the second transistor 102 is in the off state. For example, it is realized by making the channel width of the fifth transistor 105 (the width of the channel in the direction perpendicular to the direction in which carriers flow between the source region and the drain region) larger than that of the eighth transistor 108 and the ninth transistor 109. At this time, since the first transistor 101 is on, the potential of node A rises. Also, a through current flows between the fifth power line 35 and the fourth power line 34, but by adjusting the transistor sizes, the potential of node B is controlled so that the second transistor 102 is in the off state. For example, it is realized by making the channel width of the fifth transistor 105 (the width of the channel in the direction perpendicular to the direction in which carriers flow between the source region and the drain region) larger than that of the eighth transistor 108 and the ninth transistor 109. At this time, since the first transistor 101 is on, the potential of node A rises. Also, a through current flows between the fifth power line 35 and the fourth power line 34, but by adjusting the transistor sizes, the potential of node B is controlled so that the second transistor 102 is in the off state. For example, it is realized by making the channel width of the fifth transistor 105 (the width of the channel in the direction perpendicular to the direction in which carriers flow between the source region and the drain region) larger than that of the eighth transistor 108 and the ninth transistor 109. At this time, since the first transistor 101 is on, the potential of node A rises. Also, a through current flows between the fifth power line 35 and the fourth power line 34, but by adjusting the transistor sizes, the potential of node B is controlled so that the second transistor 102 is in the off state. For example, it is realized by making the channel width of the fifth transistor 105 (the width of the channel in the direction perpendicular to the direction in which carriers flow between the source region and the drain region) larger than that of the eighth transistor 108 and the ninth transistor 109. At this time, since the first transistor 101 is on, the potential of node A rises. Also, a through current flows between the fifth power line 35 and the fourth power line 34, but by adjusting the transistor sizes, the potential of node B is controlled so that the second transistor 102 is in the off state. For example, it is realized by making the channel width of the fifth transistor 105 (the width of the channel in the direction perpendicular to the direction in which carriers flow between the source region and the drain region) larger than that of the eighth transistor 108 and the ninth transistor 109. At this time, since the first transistor 101 is on, the potential of node A rises. Also, a through current flows between the fifth power line 35 and the fourth power line 34, but by adjusting the transistor sizes, the potential of node B is controlled so that the second transistor 102 is in the off state. For example, it is realized by making the channel width of the fifth transistor 105 (the width of the channel in the direction perpendicular to the direction in which carriers flow between the source region and the drain region) larger than that of the eighth transistor 108 and the ninth transistor 109. At this time, since the first transistor 101 is on, the potential of node A rises. Also, a through current flows between the fifth power line 35 and the fourth power line 34, but by adjusting the transistor sizes, the potential of node B is controlled so that the second transistor 102 is in the off state. For example, it is realized by making the channel width of the fifth transistor 105 (the width of the channel in the direction perpendicular to the direction in which carriers flow between the source region and the drain region) larger than that of the eighth transistor 108 and the ninth transistor 109.

[0041] In the second period 52, the first pulse output circuit 10_1 The output terminal 27 (OUT(1 )) outputs an H-level signal, and the fifth input terminal 2 of the second pulse output circuit 10 _2 5 is electrically connected to the sixth transistor 106, which turns on. Also, since the third clock signal (CK3) becomes the L level and the eighth transistor 108 turns off, the through current observed in the first period 5 1 disappears (see Fig. 3(B)). (See Fig. 3(B).)

[0042] At this time, the potential of node A is such that the second electrode of the first transistor 101 becomes the source electrode, and subtracting the threshold voltage of the first transistor 101 from the potential of the first power supply line 31 results in a value of V1 - Vth101 (Vth101 is the threshold voltage of the first transistor 101). Then, the first transistor 101 turns off, and node A becomes floating while maintaining V1 - Vth1 01. (Vth101 is the threshold voltage of the first transistor 101). And the first transistor 101 turns off, and node A becomes floating while maintaining V1 - Vth1 01.

[0043] Here, in the third transistor 103, the potential of the gate electrode is V1 - Vth101 . If the voltage between the gate and the source of the third transistor 103 exceeds its threshold value, that is, if V1 - Vth101 - V2 > Vth103 (Vth103 is the threshold voltage of the third transistor 103), then the third transistor 103 turns on . turns on.

[0044] In the third period 53, the second start pulse (SP2) becomes the L level, and the first transistor 101 and the fifth transistor 105 turn off. Also, the second clock signal ( CK2) becomes the H level, and an H-level signal is supplied to the first electrode of the third transistor 103 electrically connected to the first input terminal 21 (see Fig. 3(C)).

[0045] Here, since the third transistor 103 is on, a current is generated between the source and the drain, and the potential of node C (output terminal 27 (OUT(2))), that is, the second electrode (in this case, the source electrode) of the third transistor 10 3 starts to rise. There is a capacitive coupling due to the second capacitor element 112 between the gate and the source of the third transistor 1 03, and as the potential of node C rises, the potential of the gate electrode of the third transistor 103 in a floating state rises (bootstrap operation). Finally, the potential of the gate electrode of the third transistor 103 becomes higher than V1 + Vth103, and the potential of node C becomes equal to V1. Note that this bootstrap operation is performed by providing the second capacitor element 112 between the gate electrode and the second electrode of the third transistor 103. However, even without providing the second capacitor element 112, it may be performed by the capacitive coupling of the channel capacitance of the third transistor 103 and the parasitic capacitance between the gate electrode and the second electrode of the third transistor

[0046] 103. Also, at this time, since the output terminal 27 (OUT(1)) of the first pulse output circuit 10 is at the H level, the sixth transistor 106 is on and node B is maintained at the L level. Therefore, when the potential of node C rises from the L level to the H level, problems due to the capacitive coupling between node B and

[0047] node C can be suppressed. _1 node C can be suppressed. Subsequently, in the second half of the third period 53, the output terminal 27 (OUT(1)) of the first pulse output circuit 10 becomes the L level, the sixth transistor 106 turns off, and node B becomes floating and the capacitive coupling problem between node B and node C can be suppressed.

[0048] After that, in the second half of the third period 53, the output terminal 27 (OUT(1)) of the first pulse output circuit 10 _1 becomes the L level, the sixth transistor 106 turns off, and node B becomes floating and node B becomes floating enters a state. Also, the third clock signal (CK3) becomes high level, and the eighth transistor 108 turns on (see Fig. 3(D)).

[0049] In the fourth period 54, the output terminal 27 (OUT(4 _4 )) of the fourth pulse output circuit 10 becomes high level, and the input terminal 26 of the second pulse output circuit 10 _4 electrically connected to the output terminal 27 of the fourth pulse output circuit 10 becomes high level, and the seventh transistor 107 turns on, making node B also high level. As a result, the second transistor 1 _2 02 and the fourth transistor 104 turn on, the third transistor 103 turns off, and the output terminal 27 (OUT(2)) becomes low level. Also, the fourth clock signal (CK4) becomes H level, and the ninth transistor 109 turns on (see Fig. 4(A)). After that, in the second half of the fourth period 54, the third clock signal (CK3) becomes low level, and the eighth transistor 108 turns off (see Fig. 4(B)).

[0050] Then, in the fifth period 55, the output terminal 27 (OUT(4 )) of the fourth pulse output circuit 10 becomes low level, the seventh transistor 107 turns off, and node B remains high level and enters a floating state. As a result, the second transistor 102 and the fourth transistor 104 remain on (see Fig. 4(C)).

[0051] Then, during a certain period in the fifth period 55 (when both the third clock signal (CK3) and the fourth clock signal (CK4) are high level), the eighth transistor 108 and the _4 fourth pulse output circuit 10 )) becomes low level, the seventh transistor 107 turns off, and node B remains high level and enters a floating state. As a result, the second transistor 102 and the fourth transistor 104 remain on (see Fig. 4(C)). maintain the state of remaining on. (See Fig. 4(C)). transistor 104 continue to be in the on state (see Fig. 4(C)).

[0052] After that, during a certain period in the fifth period 55 (when both the third clock signal (CK3) and the fourth clock signal (CK4) are high level), the eighth transistor 108 and the ninth transistor 109 are both high level), the eighth transistor 108 and the The transistor 109 of 9 is turned on, and a signal of H level is periodically supplied to node B (see Fig. 4(D)).

[0053] In this way, by configuring the signal of H level to be periodically supplied to node B during the period when the potential of the output terminal 27 is held at the L level, malfunction of the pulse output circuit can be suppressed. Also, by periodically turning on or off the eighth transistor 108 and the ninth transistor 109, it is possible to reduce the shift of the threshold value of the transistor. Moreover, during the fifth period 55, while a signal of H level is not being supplied to node B from the fifth power supply line 35, the off - currents of the fifth transistor 105 and the sixth transistor 106 may cause the potential of node B to drop. However, since the first capacitor element 111 is electrically connected to node B, the drop in the potential of node B can be mitigated. In the present embodiment, the case where the fifth power supply line 35 is set to the same potential V1 (VDD) as the first power supply line 31 is shown. However, the fifth power supply line 35 may be set lower than the first power supply line 31 (V1 > V35 > V2, where V35 is the potential of the fifth power supply line 35). As a result, the potential of the gate electrodes of the second transistor 102 and the fourth transistor 104 can be kept low, the shift of the threshold values of the second transistor 102 and the fourth transistor 104 can be reduced, and deterioration can be suppressed. Furthermore, as shown in Fig. 5(A), the shift register shown in the present embodiment has the m - th pulse

[0054] Also, during the fifth period 55, while a signal of H level is not being supplied to node B from the fifth power supply line 35, the off - currents of the fifth transistor 105 and the sixth transistor 106 may cause the potential of node B to drop. However, since the first capacitor element 111 is electrically connected to node B, the drop in the potential of node B can be mitigated. Moreover, during the fifth period 55, while a signal of H level is not being supplied to node B from the fifth power supply line 35, the off - currents of the fifth transistor 105 and the sixth transistor 106 may cause the potential of node B to drop. However, since the first capacitor element 111 is electrically connected to node B, the drop in the potential of node B can be mitigated. Furthermore, as shown in Fig. 5(A), the shift register shown in the present embodiment has the m - th pulse In addition, during the fifth period 55, while a signal of H level is not being supplied to node B from the fifth power supply line 35, the off - currents of the fifth transistor 105 and the sixth transistor 106 may cause the potential of node B to drop. However, since the first capacitor element 111 is electrically connected to node B, the drop in the potential of node B can be mitigated.

[0055] Note that in the present embodiment, the case where the fifth power supply line 35 is set to the same potential V1 (VDD) of the first power supply line 31 is shown. However, the fifth power supply line 35 may be set lower than the first power supply line 31 (V1 > V35 > V2, where V35 is the potential of the fifth power supply line 35). As a result, the potential of the gate electrodes of the second transistor 102 and the fourth transistor 104 can be kept low, the shift of the threshold values of the second transistor 102 and the fourth transistor 104 can be reduced, and deterioration can be suppressed. Also, during the fifth period 55, while a signal of H level is not being supplied to node B from the fifth power supply line 35, the off - currents of the fifth transistor 105 and the sixth transistor 106 may cause the potential of node B to drop. However, since the first capacitor element 111 is electrically connected to node B, the drop in the potential of node B can be mitigated. Furthermore, as shown in Fig. 5(A), the shift register shown in the present embodiment has the m - th pulse Moreover, during the fifth period 55, while a signal of H level is not being supplied to node B from the fifth power supply line 35, the off - currents of the fifth transistor 105 and the sixth transistor 106 may cause the potential of node B to drop. However, since the first capacitor element 111 is electrically connected to node B, the drop in the potential of node B can be mitigated. In addition, during the fifth period 55, while a signal of H level is not being supplied to node B from the fifth power supply line 35, the off - currents of the fifth transistor 105 and the sixth transistor 106 may cause the potential of node B to drop. However, since the first capacitor element 111 is electrically connected to node B, the drop in the potential of node B can be mitigated. Furthermore, as shown in Fig. 5(A), the shift register shown in the present embodiment has the m - th pulse

[0056] Also, the shift register shown in this embodiment, as shown in Fig. 5(A), has the m - th pulse ​The pulse output from the s output circuit and the pulse output from the (m + 1)-th pulse output circuit uses a driving method in which they overlap by half (for a half cycle). This is different from the conventional shift register in that the pulse output from the m-th pulse output circuit and the pulse output from the (m + 1)-th pulse output circuit do not overlap (see Fig. 5(B)). Compared with this driving method, the time required to charge the wiring can be approximately doubled. Thus, by using the driving method in which the pulse output from the m-th pulse output circuit and the pulse output from the (m + 1)-th pulse output circuit overlap by half (for a half cycle), a large load can be applied and a pulse output circuit that operates at a high frequency can be provided. Also, the operating conditions of the pulse output circuit can be widened. In particular, it is very effective to use the driving method shown in Fig. 5(A) for a thin film transistor using amorphous silicon with poor electrical characteristics.

[0057] Note that the shift register and the pulse output circuit shown in this embodiment can be implemented in combination with the configurations of the shift register and the pulse output circuit shown in other embodiments in this specification. Also, the invention of this embodiment can be applied to a semiconductor device. In this specification, a semiconductor device means a device that can function by utilizing semiconductor characteristics.

[0058] (Embodiment 2) In this embodiment, a configuration different from the shift register and the pulse output circuit shown in the above embodiment will be described with reference to the drawings.

[0059] The shift register shown in this embodiment includes a first pulse output circuit 10 _1 ~ the n-th pulse output circuit 10 _n ​​​(n ≧ 3), and has first to fourth signal lines 11 to 14 for outputting a clock signal (see Fig. 6(A)). Also, each of the first to nth pulse output circuits 10 has a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a fifth input terminal 25, a sixth input terminal 26, a first output terminal 27, and a second output terminal 28 (see Fig. 6(B)). Note that in the pulse output circuit shown in the above Embodiment 1, the second output terminal 28 is newly added. _1 ~ the nth pulse output circuits 10 _n The first input terminal 21, the second input terminal 22, and the third input terminal 23 are electrically connected to any one of the first to fourth signal lines 11 to 14. Also, in the mth pulse output circuit (m ≧ 3) of the shift register shown in this embodiment, the fourth input terminal 24 is connected to the first output terminal 27 of the (m - 2)th pulse output circuit and the fifth input terminal 25 of the (m - 1)th pulse output circuit, the fifth input terminal 25 is connected to the first output terminal 27 of the (m - 1)th pulse output circuit and the fourth input terminal 24 of the (m + 1)th pulse output circuit, the sixth input terminal 26 is connected to the first output terminal 27 of the (m + 2)th pulse output circuit, the first output terminal 27 is connected to the sixth input terminal 26 of the (m - 2)th pulse output circuit, the fifth input terminal 25 of the (m + 1)th pulse output circuit, and the fourth input terminal 24 of the (m + 2)th pulse output circuit, and the second output terminal 28 outputs a signal to OUT(m). That is, the shift register shown in this embodiment has a first output terminal 27 and a second output terminal (Fig. 6(B) reference). In addition, the above-described embodiment In the pulse output circuit shown in State 1, the second output terminal 28 is newly added configured.

[0060] The first input terminal 21, the second input terminal 22, and the third input terminal 23 are electrically connected to any one of the first to fourth signal lines 11 to 14. Also, in the mth pulse output circuit (m ≧ 3) of the shift register shown in this embodiment, the fourth input terminal 24 is connected to the first output terminal 27 of the (m - 2)th pulse output circuit and the fifth input terminal 25 of the (m - 1)th pulse output circuit, the fifth input terminal 25 is connected to the first output terminal 27 of the (m - 1)th pulse output circuit and the fourth input terminal 24 of the (m + 1)th pulse output circuit, the sixth input terminal 26 is connected to the first output terminal 27 of the (m + 2)th pulse output circuit, the first output terminal 27 is connected to the sixth input terminal 26 of the (m - 2)th pulse output circuit, the fifth input terminal 25 of the (m + 1)th pulse output circuit, and the fourth input terminal 24 of the (m + 2)th pulse output circuit, and the second output terminal 28 outputs a signal to OUT(m). electrically connected. Also, in the shift register shown in this embodiment In the mth pulse output circuit (m ≧ 3) of the shift register, the fourth input terminal 24 is the first output terminal 27 of the ( (m - 2))th pulse output circuit and the fifth input terminal 25 of the (m - 1)th pulse output circuit electrically connected, the fifth input terminal 25 is the first output terminal 27 of the (m - 1)th pulse output circuit circuit and the fourth input terminal 24 of the (m + 1)th pulse output circuit electrically connected, the sixth input terminal 26 is the first output terminal of the (m + 2)th pulse output circuit 27 is electrically connected, the first output terminal 27 is the sixth input terminal 26 of the (m - 2)th pulse output circuit, the fifth input terminal 25 of the (m + 1)th pulse output circuit, and the fourth input terminal 24 of the (m + 2)th pulse output circuit is electrically connected, and the second output terminal 28 outputs a signal to OUT (m).

[0061] That is, the shift register shown in this embodiment has a first output terminal 27 and a second output terminal 28 is provided, and there is a configuration in which an output terminal for outputting a signal to other pulse output circuits and an output terminal for outputting a signal to the outside are provided separately.

[0062] Next, the specific configuration of the first pulse output circuit 10 _1 ~ the nth pulse output circuit 10 _n will be described.

[0063] The first pulse output circuit 10 _1 ~ the nth pulse output circuit 10 _n each has a first transistor 101 ~ a ninth transistor 109, a tenth transistor 201 ~ a thirteenth transistor 204, a first capacitive element 111, a second capacitive element 112, and a third capacitive element 21 1 (see FIG. 6(C)). The pulse output circuit shown in this embodiment is the pulse output circuit shown in the above Embodiment 1 with the addition of a tenth transistor 201 ~ a thirteenth transistor 2 04 and a third capacitive element 211. Also, in addition to the first input terminal 21 ~ the sixth input terminal 26, the first output terminal 27, and the first power supply line 31 ~ the sixth power supply line 36 shown in the above Embodiment 1, a second output terminal 28, a seventh power supply line 37 ~ a ninth power supply line 39 are added, and signals are supplied to the transistors from these lines. The tenth transistor 201 has its first electrode electrically connected to the first input terminal 21 and its second electrode electrically connected to the second output terminal 28, and its gate electrode electrically connected to the second electrode of the first transistor

[0064] 101. The eleventh transistor 202 has its first electrode electrically connected to the eighth power supply line 38 and its second electrode electrically connected to the second output terminal 28, and its gate electrode electrically connected to the second electrode of the first transistor 101. The eleventh transistor 202 has its first electrode electrically connected to the eighth power supply line 38 and its second electrode electrically connected to the second output terminal 28, and its gate electrode electrically connected to the second electrode of the first transistor ​is connected, and the gate electrode is electrically connected to the gate electrode of the second transistor 102 and the gate electrode of the fourth transistor 104. The twelfth transistor 203 has its first electrode electrically connected to the ninth power line 39, its second electrode electrically connected to the second output terminal 28, and its gate electrode electrically connected to the gate electrode of the ninth transistor 109. The thirteenth transistor 204 has its first electrode electrically connected to the seventh power line 37, its second electrode electrically connected to the first output terminal 27, and its gate electrode electrically connected to the gate electrode of the ninth transistor 109. In the third capacitor element 211, the first electrode is electrically connected to the second output terminal 28, and the second electrode is electrically connected to the second electrode of the first transistor 101 and the gate electrode of the tenth transistor 201. Connected, its second electrode is electrically connected to the first output terminal 27, and its gate electrode is electrically connected to the gate electrode of the ninth transistor 109. In the third capacitor element 211, the first electrode is electrically connected to the second output terminal 28, and the second electrode is electrically connected to the second electrode of the first transistor 101 and the gate electrode of the tenth transistor 201. That is.

[0065] Also, the seventh power line 37 to the ninth power line 39 can be configured such that the potential (VSS) of V2 is supplied in the same manner as the second power line 32 to the fourth power line 34 and the sixth power line 36. That is possible.

[0066] The first output terminal 27 and the second output terminal 28 are provided so that the same signal is output, and the tenth transistor 201 corresponds to the third transistor 103, and the fourth transistor 104 corresponds to the eleventh transistor 202. That is, the tenth transistor 201 performs a bootstrap operation in the same manner as the third transistor 103. Note that the bootstrap operation of the tenth transistor 201 is achieved by providing the third capacitor element 211 between the gate electrode and the second electrode of the tenth transistor 201. 10 performs a bootstrap operation in the same manner as the third transistor 103. The bootstrap operation of the tenth transistor 201 is achieved by providing the third capacitor element 211 between the gate electrode and the second electrode of the tenth transistor 201. 201, the third capacitor element 211 is provided between the gate electrode and the second electrode of the tenth transistor although it is going on, without providing the third capacitive element 211, the channel capacitance of the tenth transistor 201 and the parasitic capacitance between the gate electrode of the tenth transistor 201 and the second electrode may be used for capacitive coupling.

[0067] The twelfth transistor 203 and the thirteenth transistor 204 are used to shorten the fall time of the potential of the scanning line. If the fall time of the potential of the scanning line can be sufficiently shortened by the twelfth transistor 203 and the thirteenth transistor 204, it is not necessary to shorten the fall time of the potential of the scanning line by the fourth transistor 1 04 and the eleventh transistor 202. Therefore, it is also possible to set the potential of the fifth power supply line 35 lower than the power supply of the first power supply line 31. This can reduce the threshold shift of the fourth transistor 104, the eleventh transistor 202, and the second transistor 1 02. In addition, the shift register and the pulse output circuit shown in the present embodiment can be implemented in combination with the configurations of the shift register and the pulse output circuit shown in other embodiments in this specification. Further, the invention of the present embodiment can also be applied to a semiconductor device.

[0068] Note that the shift register and the pulse output circuit shown in the present embodiment can be implemented in combination with the configurations of the shift register and the pulse output circuit shown in other embodiments in this specification. Further, the invention of the present embodiment can also be applied to a semiconductor device.

[0069] (Embodiment 3) In the present embodiment, a configuration different from the shift register and the pulse output circuit shown in the above embodiment will be described.

[0070] In the configurations shown in the above Embodiment 1 and Embodiment 2, an example in which all circuits are configured using N-channel type thin film transistors is shown. However, in terms of using unipolar thin film transistors, a similar configuration may be adopted using only P-channel type thin film transistors. In particular, in FIG. ​ Although not shown, in the figures shown in FIG. 1(C) or FIG. 6(C), the connection of the transistors is the same and the potential levels of the power supply lines may be reversed from those described in Embodiment 1 and Embodiment 2. Also, the configuration may be such that all the H levels and L levels of the input signals are inverted before being input. Note that the invention of this embodiment can also be applied to semiconductor devices.

[0071] (Embodiment 4) With reference to the drawings, a configuration in which the shift register shown in the above embodiment is provided in a display device will be described.

[0072] In FIG. 9(A), a pixel portion 1102 in which a plurality of pixels 1101 are arranged in a matrix is provided on a substrate 1107, and a signal line driving circuit 1103, a first scanning line driving circuit 1104, and a second scanning line driving circuit 1105 are provided around the pixel portion 1102. These driving circuits are supplied with signals from the outside via an FPC 1106.

[0073] FIG. 9(B) shows the configurations of the first scanning line driving circuit 1104 and the second scanning line driving circuit 1105. The scanning line driving circuits 1104 and 1105 include a shift register 1114 and a buffer 1115. Further, FIG. 9(C) shows the configuration of the signal line driving circuit 1103. The signal line driving circuit 1103 includes a shift register 1111, a first latch circuit 1112, a second latch circuit 1113, and a buffer 1117.

[0074] The circuit that operates as the shift register shown in this embodiment can be applied to the circuits of the above shift register 111 1 and the shift register 1114. By applying the circuit that operates as the shift register shown in the above embodiment, amorphous silicon can be ​ This is the case where a circuit that operates as the shift register using the thin-film transistor used is provided. It can also be operated at a high frequency.

[0075] Note that the configurations of the scanning line driving circuit and the signal line driving circuit are not limited to the configurations shown in FIG. 9, and for example it may include a sampling circuit, a level shifter, etc. Further, outside the above driving circuit circuits such as a CPU or a controller may be integrally formed on the substrate 1107. By doing so the number of external circuits (ICs) to be connected is reduced, and it is possible to further achieve lightweight and thinness, which is particularly effective for portable terminals etc.

[0076] Note that the display device shown in this embodiment can be implemented in combination with the configurations of the shift register, the pulse output circuit, or the display device shown in other embodiments in this specification.

[0077] (Embodiment 5) In this embodiment, the configuration of the display panel used in the display device shown in the above Embodiment 4 will be described with reference to the drawings.

[0078] First, a display panel applicable to the display device will be described with reference to FIG. 10. Note that FIG. 1 0(A) is a top view showing the display panel, and FIG. 10(B) is a cross-sectional view taken along A-A' of FIG. 10(A). It has a signal line driving circuit 3601, a pixel portion 3602, a second scanning line driving circuit 3603, and a first scanning line driving circuit 3606 indicated by dotted lines. Further, it has a sealing substrate 3604 and a sealing material 3605, and the inside surrounded by the sealing material 3605 becomes a space 3607.

[0079] Note that the wiring 3608 is connected to the second scanning line driving circuit 3603 and the first scanning line driving circuit 3606. and wiring for transmitting signals input to the signal line driving circuit 3601, and an external input terminal receives a video signal, a clock signal, a start signal, etc. from an FPC (Flexible Printed Circuit) 3609 that serves as a child. On the joint between the FPC 3609 and the display panel, IC chips (semiconductor chips on which a memory circuit, a buffer circuit, etc. are formed) 3618 and IC chips 3619 are mounted by COG (Chip On Glass) or the like. Although only the FPC is shown here, a printed wiring board (PWB) may be attached to this FPC. The display device in this specification refers to not only the display panel main body but also a state in which an FPC or a PWB is attached thereto. Further, it includes those in which IC chips and the like are mounted.

[0080] Next, the cross-sectional structure will be described with reference to FIG. 10(B). On the substrate 3610, a pixel portion 3 602 and its peripheral driving circuits (the second scanning line driving circuit 3603, the first scanning line driving circuit 36 06, and the signal line driving circuit 3601) are formed. Here, the signal line driving circuit 36 01 and the pixel portion 3602 are shown.

[0081] The signal line driving circuit 3601 constitutes a CMOS circuit using an N-channel type TFT 3620 and a P-channel type TFT 3621. Further, in this embodiment, a display panel in which peripheral driving circuits are integrally formed on a substrate is shown, but this is not necessarily required, and all or part of the peripheral driving circuits may be formed on an IC chip or the like and mounted by COG or the like.

[0082] It has a plurality of circuits that make up the pixels. Note that the source electrode of the driving TFT 3612 is electrically connected to the first electrode 3613. Also, an insulator 3614 is formed to cover the end of the first electrode 3613 Here, it is formed by using a positive photosensitive acrylic resin film to form it.

[0083] Also, in order to achieve good coverage, a curved surface with a curvature is formed at the upper or lower end of the insulator 3614 For example, when using positive photosensitive acrylic as the material of the insulator 3614, it is preferable to provide a curved surface with a radius of curvature (0.2 μm to 3 μm) only at the upper end of the insulator 3614. Also, as the insulator 3614, either a negative type that becomes insoluble in the etchant by light or a positive type that becomes soluble in the etchant by light can be used.

[0084] A layer 3616 containing an organic compound and a second electrode 3617 are respectively formed on the first electrode 3613 Here, as the material used for the first electrode 3613 that functions as an anode, it is desirable to use a material with a large work function. For example, ITO (indium tin oxide) film, indium zinc oxide (IZO) film, titanium nitride film, chromium film, tantalum sten film, Zn film, Pt film, etc. In addition to single-layer films, a laminate of a film mainly composed of titanium nitride and aluminum and a three-layer structure of a film mainly composed of titanium nitride and aluminum and a titanium nitride film can be used When a laminated structure is used, the resistance as wiring is low, good ohmic contact can be achieved, and it can further function as an anode.

[0085] ​​​In addition, the layer 3616 containing an organic compound is formed by a vapor deposition method using a vapor deposition mask or an inkjet method. As a part of the layer 3616 containing an organic compound, a metal complex of Group 4 of the periodic table is used. In addition, as materials that can be used in combination, either low molecular weight materials or high molecular weight materials may be used. Also, as materials used for the layer containing an organic compound, usually, an organic compound is often used alone or in a laminate. However, in this embodiment, a configuration in which an inorganic compound is used for a part of the film made of an organic compound is also included. Furthermore, it is also possible to use a known triplet material. Furthermore, as the material used for the second electrode (cathode) 3617 formed on the layer 3616 containing an organic compound, a material having a small work function (Al, Ag, Li, Ca, or an alloy thereof such as MgAg, MgIn, AlLi, CaF2, or calcium nitride) may be used. When the light generated in the layer 3616 containing an organic compound is transmitted through the second electrode 3617, as the second electrode (cathode) 3617, a laminated body of a thin metal film with a reduced film thickness and a transparent conductive film (ITO (indium tin oxide), indium zinc oxide alloy (In2O3—ZnO), zinc oxide (ZnO), etc.) is preferably used. Furthermore, by bonding the sealing substrate 3604 to the substrate 3610 with the sealing material 3605, a structure is formed in which the display element 3622 is provided in the space 3607 surrounded by the substrate 3610, the sealing substrate 3604, and the sealing material 3605. Note that the space 3607 includes not only the case where it is filled with an inert gas (such as nitrogen or argon), but also a configuration filled with the sealing material 3605.

[0086]

[0087]

[0088] Note that it is preferable to use an epoxy resin for the sealing material 3605. Also, these materials are desirably materials that do not permeate moisture and oxygen as much as possible. Further, as materials for the sealing substrate 36 04, in addition to a glass substrate and a quartz substrate, a plastic substrate made of FRP (Fiberglass-Reinforced Plastics), PVF (polyvinyl fluoride), polyester, or acrylic, etc. can be used.

[0089] In this way, a display panel can be obtained.

[0090] As shown in FIG. 10, by integrally forming the signal line drive circuit 3601, the pixel portion 3602, the second scan line drive circuit 3603, and the first scan line drive circuit 3606, the cost reduction of the display device can be achieved.

[0091] Note that as the configuration of the display panel, as shown in FIG. 10(A), it is not limited to the configuration in which the signal line drive circuit 360 1, the pixel portion 3602, the second scan line drive circuit 3603, and the first scan line drive circuit 3606 are integrally formed. The signal line drive circuit 4201 shown in FIG. 11(A) corresponding to the signal line drive circuit 3601 can be formed on an IC chip and mounted on the display panel by COG or the like. Note that the substrate 4200, the pixel portion 4202, the second scan line drive circuit 4203, the first scan line drive circuit 4204, the FPC 4205, the IC chip 4206 , the IC chip 4207, the sealing substrate 4208, and the sealing material 4209 in FIG. 11(A) are the substrate 36 10, the pixel portion 3602, the second scan line drive circuit 3603, the first scan line drive circuit 3606 , the FPC 3609, the IC chip 3618, the IC chip 3619, the sealing substrate 3604, and the seal ​​​​​​​This corresponds to the routing material 3605.

[0092] That is, only the signal line drive circuit that requires high-speed operation in the drive circuit is formed on the IC chip using CMOS or the like to achieve low power consumption. Also, by using a semiconductor chip such as a silicon wafer for the IC chip, higher-speed operation and lower power consumption can be achieved. Moreover, by integrally forming the first scan line drive circuit 4203 and the second scan line drive circuit 4204 provided with the shift register shown in the above embodiment with the pixel portion 4202, cost reduction can be achieved. In this way, cost reduction of a high-definition display device can be achieved. Also, by mounting an IC chip in which a functional circuit (memory or buffer) is formed at the connection portion between the FPC 4205 and the substrate 4200, the substrate area can be effectively utilized.

[0093] And, a configuration in which the signal line drive circuit 4211, the second scan line drive circuit 4214, and the first scan line drive circuit 4213 corresponding to the signal line drive circuit 3601, the second scan line drive circuit 3603, and the first scan line drive circuit 3606 in FIG. 10(A) are formed on the IC chip and mounted on the display panel by COG or the like may also be used. In this case, it is possible to make the high-definition display device consume less power. Therefore, in order to make a display device consume less power, it is desirable to use polysilicon for the semiconductor layer of the transistor used in the pixel portion. Note that the substrate 4210, the pixel portion 4212, the FPC 4215, the IC chip 4216, the IC chip 4217, the sealing substrate 4218, and the sealing material 4219 in FIG. 11(B) are those in FIG. 10(A).

[0094]

[0095] ​​​​​​​​​​​​​Substrate 3610, pixel section 3602, FPC 3609, IC chip 3618, IC chip 36 correspond to 19, sealing substrate 3604, and sealing material 3605.

[0096] In addition, by using amorphous silicon for the semiconductor layer of the transistor in the pixel section 4212, cost reduction can be achieved. Furthermore, it is also possible to fabricate a large-sized display panel. It becomes possible.

[0097] Furthermore, examples of display elements applicable to the display element 3622 are shown in FIGS. 15(A) and (B). That is, the configuration of the display element applicable to the pixel shown in the above embodiment will be described with reference to FIGS. 15(A) , (B).

[0098] The display element in FIG. 15(A) has an anode 4402, a hole injection layer 4403 made of a hole injection material, a hole transport layer 4404 made of a hole transport material, a light-emitting layer 440 5, an electron transport layer 4406 made of an electron transport material, an electron injection layer 440 7, and a cathode 4408 laminated on a substrate 4401. Here, the light-emitting layer 4405 may be formed of only one type of light-emitting material, or may be formed of two or more types of materials. Moreover, the structure of the element of the present invention is not limited to this structure.

[0099] In addition to the laminated structure in which each functional layer shown in FIGS. 15(A) and 15(B) is laminated, there are various variations such as an element using a polymer, a high-efficiency element using a triplet light-emitting material that emits light from a triplet excited state in the light-emitting layer. It is also applicable to a white display element obtained by controlling the carrier recombination region by a hole blocking layer and dividing the light-emitting region into two regions.

[0100] The method for fabricating the device of the present invention shown in Fig. 15(A) first involves depositing a hole injection material, a hole transport material, and a light-emitting material in sequence on a substrate 4401 having an anode 4402 (ITO). Next, an electron transport material and an electron injection material are deposited, and finally, a cathode 4408 is formed by deposition.

[0101] Next, suitable materials for the hole injection material, hole transport material, electron transport material, electron injection material, and light-emitting material are listed below.

[0102] As the hole injection material, if it is an organic compound, porphyrin-based compounds, phthalocyanine (hereinafter referred to as "H2Pc"), copper phthalocyanine (hereinafter referred to as "CuPc"), etc. are effective. Also, if the value of the ionization potential is smaller than that of the hole transport material to be used and it has a hole transport function, this can also be used as the hole injection material. There are also materials obtained by chemically doping conductive polymer compounds, such as polyethylenedioxythiophene doped with polystyrene sulfonic acid (hereinafter referred to as "PSS" ) (hereinafter referred to as "PEDOT") and polyaniline. In addition, insulating polymer compounds are effective in terms of flattening the anode, and polyimide (hereinafter referred to as "PI") is often used. Furthermore, inorganic compounds are also used. In addition to metal thin films such as gold and platinum, there are ultra-thin films of aluminum oxide (hereinafter referred to as "alumina" ). ) etc.

[0103] The most widely used hole transport material is an aromatic amine-based (i.e., having a benzene ring-nitrogen bond) compound. Widely used materials include 4, 4'-bis(diphenylamino)-biphenyl (hereinafter referred to as "TAD") and its derivatives ​4,4'-bis[N-(3-methylphenyl)-N-phenyl-amino]-biphenyl (hereinafter referred to as "TPD"), 4,4'-bis[N-(1-naphthyl)-N-phenyl-amino]-biphenyl (hereinafter referred to as "α-NPD"). There are 4,4',4''-tris(N,N-diphenyl-amino)-triphenylamine (hereinafter referred to as "TDATA"), 4,4',4''-tris[N-(3-methylphenyl)-N-phenyl-amino]-triphenylamine (hereinafter referred to as "MTDATA") and other starburst-type aromatic amine compounds. enyl (hereinafter referred to as "TPD"), 4,4'-bis[N-(1-naphthyl)-N-phenyl- nil-amino]-biphenyl (hereinafter referred to as "α-NPD"). 4,4',4''- tris(N,N-diphenyl-amino)-triphenylamine (hereinafter referred to as "TDATA" and denoted), 4,4',4''-tris[N-(3-methylphenyl)-N-phenyl-a mino]-triphenylamine (hereinafter referred to as "MTDATA") and other starburst-type aromatic amine compounds.

[0104] As the electron transport material, metal complexes are often used, such as Alq, BAlq, tris(4-methyl-8-quinolinolato)aluminum (hereinafter referred to as "Almq"), bis(10-hydroxybenzo[h]-quinolinato)beryllium (hereinafter referred to as "BeBq") and other metal complexes having a quinoline skeleton or a benzoquinoline skeleton. In addition, there are also metal complexes having oxazole-based or thiazole-based ligands such as bis[2-(2-hydroxyphenyl)-benzoxazolato]zinc (hereinafter referred to as "Zn(BOX)2"), bis[2-(2-hydroxyphenyl)-benzothiazolato]zinc (hereinafter referred to as "Zn(BTZ)2"). Furthermore, in addition to metal complexes, 2-(4-biphenylyl)-5-(4-tert-butylphenyl)-1,3,4-oxadiazole (hereinafter referred to as "PBD"), oxadiazole derivatives such as OXD-7, TAZ, 3-(4-tert-butylphenyl)-4-(4-ethylphenyl)-5-(4-biphenylyl)-1,2,4-triazole (hereinafter referred to as "p-EtTAZ") and other triazole derivatives, bathophenanthroline -8-quinolinolato)aluminum (hereinafter referred to as "Almq"), bis(10-hi droxybenzo[h]-quinolinato)beryllium (hereinafter referred to as "BeBq") and other ki noline skeleton or benzoquinoline skeleton metal complexes. Also, bis[2-( 2-hydroxyphenyl)-benzoxazolato]zinc (hereinafter referred to as "Zn(BOX)2") and bis[2-(2-hydroxyphenyl)-benzothiazolato]zinc (hereinafter referred to as "Z n(BTZ)2") and other metal complexes having oxazole-based and thiazole-based ligands are also available. Furthermore, in addition to metal complexes, 2-(4-biphenylyl)-5-(4-tert- butylphenyl)-1,3,4-oxadiazole (hereinafter referred to as "PBD"), OXD -7 and other oxadiazole derivatives, TAZ, 3-(4-tert-butylphenyl)- 4-(4-ethylphenyl)-5-(4-biphenylyl)-1,2,4-triazole ( hereinafter referred to as "p-EtTAZ") and other triazole derivatives, bathophenanthroline (hereinafter referred to as "BPhen"), phenanthroline derivatives such as BCP have electron transporting properties. They do.

[0105] As the electron injection material, the electron transporting materials described above can be used. In addition, ultrathin films of insulators such as metal halides such as calcium fluoride, lithium fluoride, cesium fluoride, and alkali metal oxides such as lithium oxide are often used. Further, alkali metal complexes such as lithium acetylacetonate (hereinafter referred to as "Li(acac)") and lithium 8-quinolinolato (hereinafter referred to as "Liq") are also effective. Calcium fluoride, lithium fluoride, cesium fluoride and other metal halides, and ultrathin films of insulators such as alkali metal oxides such as lithium oxide are often used. Also, alkali metal complexes such as lithium acetylacetonate (hereinafter referred to as "Li(acac)") and lithium 8-quinolinolato (hereinafter referred to as "Liq") are also effective. As the electron injection material, the electron transporting materials described above can be used. In addition, ultrathin films of insulators such as metal halides such as calcium fluoride, lithium fluoride, cesium fluoride, and alkali metal oxides such as lithium oxide are often used. Further, alkali metal complexes such as lithium acetylacetonate (hereinafter referred to as "Li(acac)") and lithium 8-quinolinolato (hereinafter referred to as "Liq") are also effective. Lithium acetylacetonate (hereinafter referred to as "Li(acac)") and 8-quinolinolato-lithium (hereinafter referred to as "Liq") are also effective. Lithium acetylacetonate (hereinafter referred to as "Li(acac)") and 8-quinolinolato-lithium (hereinafter referred to as "Liq") are also effective.

[0106] As the light emitting material, in addition to metal complexes such as Alq, Almq, BeBq, BAlq, Zn(BOX)2, Zn(BTZ)2, various fluorescent dyes are effective. As the fluorescent dye, blue 4,4'-bis(2,2-diphenyl-vinyl)-biphenyl, red-orange 4-( dicyanomethylene)-2-methyl-6-(p-dimethylaminostyryl)-4H-pyran and the like are available. Further, triplet light emitting materials are also possible, and complexes having platinum or iridium as the central metal are mainly used. As the triplet light emitting material, tris(2-phenylpyridine) iridium, bis(2-(4'-tolyl)pyridinato-N,C ) acetylacetonato iridium (hereinafter referred to as "acacIr(tpy)2"), 2,3,7,8,12,13,1 7,18-octaethyl-21H,23H porphyrin-platinum and the like are known. As the light emitting material, in addition to metal complexes such as Alq, Almq, BeBq, BAlq, Zn(BOX)2, Zn(BTZ)2, various fluorescent dyes are effective. As the fluorescent dye, blue 4,4'-bis(2,2-diphenyl-vinyl)-biphenyl, red-orange 4-( dicyanomethylene)-2-methyl-6-(p-dimethylaminostyryl)-4H-pyran and the like are available. Further, triplet light emitting materials are also possible, and complexes having platinum or iridium as the central metal are mainly used. As the triplet light emitting material, tris(2-phenylpyridine) iridium, bis(2-(4'-tolyl)pyridinato-N,C ) acetylacetonato iridium (hereinafter referred to as "acacIr(tpy)2"), 2,3,7,8,12,13,1 2’ ) acetylacetonato iridium (hereinafter referred to as "acacIr(tpy)2"), 2,3,7,8,12,13,1 7,18-octaethyl-21H,23H porphyrin-platinum and the like are known. 7,18-octaethyl-21H,23H porphyrin-platinum and the like are known.

[0107] By combining the materials having the respective functions as described above, a highly reliable display element can be manufactured. It can be manufactured.

[0108] In addition, the polarity of the driving transistor in the pixel configuration shown in the above embodiment is changed to an N-channel The potential of the opposing electrode of the display element is set to a potential set to the power line. By reversing the above, a display element having layers formed in the reverse order to that shown in FIG. 15(A) can be used. That is, as shown in FIG. 15(B), a cathode 4408, an electron injection material 4409, and a an electron transport layer 4406 made of an electron transport material; layer 4405, a hole transport layer 4404 made of a hole transport material, a hole injection layer 4405 made of a hole injection material, The element structure is a laminate of a layer 4403 and an anode 4402 .

[0109] In addition, the display element requires that at least one of the anode or cathode is transparent in order to extract light. Then, the TFT and the display element are formed on the substrate, and light is emitted from the opposite side of the substrate. Top emission, bottom emission, and both the substrate side and the opposite side of the substrate. There is a display element having a double-sided emission structure in which light is emitted from both sides. The composition can be applied to any display element with an ejection structure.

[0110] A display element having a top emission structure will be described with reference to FIG.

[0111] A driving TFT 4501 is formed on a substrate 4500 via an undercoat film 4505. A first electrode 4502 is formed in contact with the source electrode of the FT4501, and an organic compound A layer 4503 containing and a second electrode 4504 are formed.

[0112] The first electrode 4502 is an anode of the display element. The cathode of the element. In other words, the first electrode 4502 and the second electrode 4504 are connected to an organic compound. The portion where the containing layer 4503 is sandwiched becomes the display element.

[0113] Also, here, as the material used for the first electrode 4502 that functions as an anode, it is desirable to use a material with a large work function. For example, in addition to single-layer films such as titanium nitride film, chromium film, tungsten film, Zn film, Pt film, etc., a laminate of a film mainly composed of titanium nitride and aluminum, a three-layer structure of a titanium nitride film, a film mainly composed of aluminum, and a titanium nitride film, etc. can be used. Note that when forming a laminated structure, the resistance as wiring is low, good ohmic contact can be achieved, and it can further function as an anode. By using a metal film that reflects light, an anode that does not transmit light can be formed. For example, in addition to single-layer films such as titanium nitride film, chromium film, tungsten film, Zn film, Pt film, etc., a laminate of a film mainly composed of titanium nitride and aluminum, a three-layer structure of a titanium nitride film, a film mainly composed of aluminum, and a titanium nitride film, etc. can be used. Note that when forming a laminated structure, the resistance as wiring is low, good ohmic contact can be achieved, and it can further function as an anode. By using a metal film that reflects light, an anode that does not transmit light can be formed. For example, in addition to single-layer films such as titanium nitride film, chromium film, tungsten film, Zn film, Pt film, etc., a laminate of a film mainly composed of titanium nitride and aluminum, a three-layer structure of a titanium nitride film, a film mainly composed of aluminum, and a titanium nitride film, etc. can be used. Note that when forming a laminated structure, the resistance as wiring is low, good ohmic contact can be achieved, and it can further function as an anode. By using a metal film that reflects light, an anode that does not transmit light can be formed. For example, in addition to single-layer films such as titanium nitride film, chromium film, tungsten film, Zn film, Pt film, etc., a laminate of a film mainly composed of titanium nitride and aluminum, a three-layer structure of a titanium nitride film, a film mainly composed of aluminum, and a titanium nitride film, etc. can be used. Note that when forming a laminated structure, the resistance as wiring is low, good ohmic contact can be achieved, and it can further function as an anode. By using a metal film that reflects light, an anode that does not transmit light can be formed. For example, in addition to single-layer films such as titanium nitride film, chromium film, tungsten film, Zn film, Pt film, etc., a laminate of a film mainly composed of titanium nitride and aluminum, a three-layer structure of a titanium nitride film, a film mainly composed of aluminum, and a titanium nitride film, etc. can be used. Note that when forming a laminated structure, the resistance as wiring is low, good ohmic contact can be achieved, and it can further function as an anode. By using a metal film that reflects light, an anode that does not transmit light can be formed. For example, in addition to single-layer films such as titanium nitride film, chromium film, tungsten film, Zn film, Pt film, etc., a laminate of a film mainly composed of titanium nitride and aluminum, a three-layer structure of a titanium nitride film, a film mainly composed of aluminum, and a titanium nitride film, etc. can be used. Note that when forming a laminated structure, the resistance as wiring is low, good ohmic contact can be achieved, and it can further function as an anode. By using a metal film that reflects light, an anode that does not transmit light can be formed. For example, in addition to single-layer films such as titanium nitride film, chromium film, tungsten film, Zn film, Pt film, etc., a laminate of a film mainly composed of titanium nitride and aluminum, a three-layer structure of a titanium nitride film, a film mainly composed of aluminum, and a titanium nitride film, etc. can be used. Note that when forming a laminated structure, the resistance as wiring is low, good ohmic contact can be achieved, and it can further function as an anode. By using a metal film that reflects light, an anode that does not transmit light can be formed.

[0114] Also, as the material used for the second electrode 4504 that functions as a cathode, it is good to use a laminate of a thin metal film made of a material with a small work function (Al, Ag, Li, Ca, or their alloys MgAg, MgIn, AlLi, CaF2, or calcium nitride) and a transparent conductive film (ITO (indium tin oxide), indium zinc oxide (IZO), zinc oxide (ZnO), etc.). By using such a thin metal film and a transparent conductive film with transparency in this way, a cathode that can transmit light can be formed. Also, as the material used for the second electrode 4504 that functions as a cathode, it is good to use a laminate of a thin metal film made of a material with a small work function (Al, Ag, Li, Ca, or their alloys MgAg, MgIn, AlLi, CaF2, or calcium nitride) and a transparent conductive film (ITO (indium tin oxide), indium zinc oxide (IZO), zinc oxide (ZnO), etc.). By using such a thin metal film and a transparent conductive film with transparency in this way, a cathode that can transmit light can be formed. Also, as the material used for the second electrode 4504 that functions as a cathode, it is good to use a laminate of a thin metal film made of a material with a small work function (Al, Ag, Li, Ca, or their alloys MgAg, MgIn, AlLi, CaF2, or calcium nitride) and a transparent conductive film (ITO (indium tin oxide), indium zinc oxide (IZO), zinc oxide (ZnO), etc.). By using such a thin metal film and a transparent conductive film with transparency in this way, a cathode that can transmit light can be formed. Also, as the material used for the second electrode 4504 that functions as a cathode, it is good to use a laminate of a thin metal film made of a material with a small work function (Al, Ag, Li, Ca, or their alloys MgAg, MgIn, AlLi, CaF2, or calcium nitride) and a transparent conductive film (ITO (indium tin oxide), indium zinc oxide (IZO), zinc oxide (ZnO), etc.). By using such a thin metal film and a transparent conductive film with transparency in this way, a cathode that can transmit light can be formed. Also, as the material used for the second electrode 4504 that functions as a cathode, it is good to use a laminate of a thin metal film made of a material with a small work function (Al, Ag, Li, Ca, or their alloys MgAg, MgIn, AlLi, CaF2, or calcium nitride) and a transparent conductive film (ITO (indium tin oxide), indium zinc oxide (IZO), zinc oxide (ZnO), etc.). By using such a thin metal film and a transparent conductive film with transparency in this way, a cathode that can transmit light can be formed. Also, as the material used for the second electrode 4504 that functions as a cathode, it is good to use a laminate of a thin metal film made of a material with a small work function (Al, Ag, Li, Ca, or their alloys MgAg, MgIn, AlLi, CaF2, or calcium nitride) and a transparent conductive film (ITO (indium tin oxide), indium zinc oxide (IZO), zinc oxide (ZnO), etc.). By using such a thin metal film and a transparent conductive film with transparency in this way, a cathode that can transmit light can be formed.

[0115] In this way, as shown by the arrow in Fig. 12(A), it becomes possible to extract the light from the display element to the upper surface. That is, when applied to the display panel in Fig. 10, the light will be emitted toward the sealing substrate 3604 side. Therefore, when using a display element with an upper surface emission structure in a display device, the sealing substrate 3604 uses a substrate with light transmissibility. In this way, as shown by the arrow in Fig. 12(A), it becomes possible to extract the light from the display element to the upper surface. That is, when applied to the display panel in Fig. 10, the light will be emitted toward the sealing substrate 3604 side. Therefore, when using a display element with an upper surface emission structure in a display device, the sealing substrate 3604 uses a substrate with light transmissibility. In this way, as shown by the arrow in Fig. 12(A), it becomes possible to extract the light from the display element to the upper surface. That is, when applied to the display panel in Fig. 10, the light will be emitted toward the sealing substrate 3604 side. Therefore, when using a display element with an upper surface emission structure in a display device, the sealing substrate 3604 uses a substrate with light transmissibility. In this way, as shown by the arrow in Fig. 12(A), it becomes possible to extract the light from the display element to the upper surface. That is, when applied to the display panel in Fig. 10, the light will be emitted toward the sealing substrate 3604 side. Therefore, when using a display element with an upper surface emission structure in a display device, the sealing substrate 3604 uses a substrate with light transmissibility.

[0116] In the case of providing an optical film, the optical film may be provided on the sealing substrate 3604. That's it.

[0117] Next, the display element with a bottom surface injection structure will be described with reference to FIG. 12(B). Since the display element has the same structure as that in FIG. 12(A) except for the injection structure, the same reference numerals will be used for the description.

[0118] Here, as the material used for the first electrode 4502 that functions as an anode, it is desirable to use a material with a large work function. For example, a transparent conductive film such as an ITO (indium tin oxide) film or an indium zinc oxide (IZO) film can be used. By using a transparent conductive film having transparency, an anode capable of transmitting light can be formed.

[0119] Also, as the material used for the second electrode 4504 that functions as a cathode, a material with a small work function (Al, Ag, Li, Ca, or an alloy thereof such as MgAg, MgIn, AlLi, CaF2, or calcium nitride) can be used to form a metal film. In this way, by using a metal film that reflects light, a cathode that does not transmit light can be formed.

[0120] In this way, as shown by the arrow in FIG. 12(B), the light from the display element can be extracted to the bottom surface. That is, when applied to the display panel of FIG. 10, light is emitted to the substrate 3610 side. Therefore, when a display element with a bottom surface injection structure is used in a display device, the substrate 36 10 uses a substrate having light transmissibility.

[0121] In the case of providing an optical film, the optical film may be provided on the substrate 3610.

[0122] Next, the display element with a double-sided injection structure will be described with reference to FIG. 12(C). Since the display element has the same structure as that in FIG. 12(A) except for the injection structure, the same reference numerals will be used for the description. Since the display element has the same structure as that in FIG. 12(A) except for the injection structure, the same reference numerals will be used for the description.

[0123] Here, as the material used for the first electrode 4502 that functions as an anode, it is desirable to use a material with a large work function. For example, a transparent conductive film such as an ITO (indium tin oxide) film or an indium zinc oxide (IZO) film can be used. By using a transparent conductive film having transparency, an anode capable of transmitting light can be formed. Here, as the material used for the first electrode 4502 that functions as an anode, it is desirable to use a material with a large work function. For example, a transparent conductive film such as an ITO (indium tin oxide) film or an indium zinc oxide (IZO) film can be used. By using a transparent conductive film having transparency, an anode capable of transmitting light can be formed. Here, as the material used for the first electrode 4502 that functions as an anode, it is desirable to use a material with a large work function. For example, a transparent conductive film such as an ITO (indium tin oxide) film or an indium zinc oxide (IZO) film can be used. By using a transparent conductive film having transparency, an anode capable of transmitting light can be formed. Here, as the material used for the first electrode 4502 that functions as an anode, it is desirable to use a material with a large work function. For example, a transparent conductive film such as an ITO (indium tin oxide) film or an indium zinc oxide (IZO) film can be used. By using a transparent conductive film having transparency, an anode capable of transmitting light can be formed.

[0124] Also, as the material used for the second electrode 4504 that functions as a cathode, a material with a small work function (Al, Ag, Li, Ca, or an alloy thereof such as MgAg, MgIn, AlLi, CaF2, or calcium nitride) and a transparent conductive film (ITO (indium tin oxide), indium zinc oxide alloy (In2O3-ZnO), zinc oxide (Zn O), etc.) are preferably used in a laminated structure. By using such a thin metal film and a transparent conductive film having transparency, a cathode capable of transmitting light can be formed. O), etc.) are preferably used in a laminated structure. By using such a thin metal film and a transparent conductive film having transparency, a cathode capable of transmitting light can be formed. O), etc.) are preferably used in a laminated structure. By using such a thin metal film and a transparent conductive film having transparency, a cathode capable of transmitting light can be formed. O), etc.) are preferably used in a laminated structure. By using such a thin metal film and a transparent conductive film having transparency, a cathode capable of transmitting light can be formed.

[0125] Thus, as shown by the arrow in FIG. 12(C), light can be extracted from both sides of the display element. That is, when applied to the display panel of FIG. 10, light will be emitted from both the substrate 3610 side and the sealing substrate 3604 side. Therefore, when a display element with a double-sided injection structure is used in a display device, both the substrate 3610 and the sealing substrate 3604 are made of substrates having light transmissibility. Thus, as shown by the arrow in FIG. 12(C), light can be extracted from both sides of the display element. That is, when applied to the display panel of FIG. 10, light will be emitted from both the substrate 3610 side and the sealing substrate 3604 side. Therefore, when a display element with a double-sided injection structure is used in a display device, both the substrate 3610 and the sealing substrate 3604 are made of substrates having light transmissibility. Thus, as shown by the arrow in FIG. 12(C), light can be extracted from both sides of the display element. That is, when applied to the display panel of FIG. 10, light will be emitted from both the substrate 3610 side and the sealing substrate 3604 side. Therefore, when a display element with a double-sided injection structure is used in a display device, both the substrate 3610 and the sealing substrate 3604 are made of substrates having light transmissibility. Thus, as shown by the arrow in FIG. 12(C), light can be extracted from both sides of the display element. That is, when applied to the display panel of FIG. 10, light will be emitted from both the substrate 3610 side and the sealing substrate 3604 side. Therefore, when a display element with a double-sided injection structure is used in a display device, both the substrate 3610 and the sealing substrate 3604 are made of substrates having light transmissibility. Thus, as shown by the arrow in FIG. 12(C), light can be extracted from both sides of the display element. That is, when applied to the display panel of FIG. 10, light will be emitted from both the substrate 3610 side and the sealing substrate 3604 side. Therefore, when a display element with a double-sided injection structure is used in a display device, both the substrate 3610 and the sealing substrate 3604 are made of substrates having light transmissibility.

[0126] Also, when an optical film is provided, it is provided on both the substrate 3610 and the sealing substrate 3604. An optical film may be provided.

[0127] In addition, the present invention can also be applied to a display device that realizes full-color display using a white display element and a color filter. It is also applicable to the display device driven by the pulse output circuit and the shift register of the present invention.

[0128] For example, as shown in FIG. 13, a base film 4602 is formed on a substrate 4600, and thereon a driving TFT 4601 is formed, a first electrode 4603 is formed in contact with the source electrode of the driving TFT 4601, and thereon a layer 4604 containing an organic compound and a second electrode 4605 are formed. It can also be configured as described above. The first electrode 4603 is the anode of the display element. And the second electrode 4605 is the cathode of the display element. That is, the layer 4604 containing the organic compound is sandwiched between the first electrode 4603 and the second electrode 4605, and this is the display element. In the configuration of FIG. 13, white light is emitted. And, a red color filter 4606R, a green color filter 4606G, and a blue color filter 4606B are provided above the display element, and full-color display can be performed. Also, a black matrix (also referred to as BM) 4607 for isolating these color filters is provided.

[0129] The above-described configurations of the display elements can be used in combination, and can be appropriately used in a display device driven by the pulse output circuit and the shift register of the present invention. Also, the configurations of the above-described display panel and the display elements are examples, and of course, other configurations can also be applied. The above-described configurations of the display elements can be used in combination, and can be appropriately used in a display device driven by the pulse output circuit and the shift register of the present invention. Also, the configurations of the above-described display panel and the display elements are examples, and of course, other configurations can also be applied. The above-described configurations of the display elements can be used in combination, and can be appropriately used in a display device driven by the pulse output circuit and the shift register of the present invention. Also, the configurations of the above-described display panel and the display elements are examples, and of course, other configurations can also be applied. The above-described configurations of the display elements can be used in combination, and can be appropriately used in a display device driven by the pulse output circuit and the shift register of the present invention. Also, the configurations of the above-described display panel and the display elements are examples, and of course, other configurations can also be applied. The above-described configurations of the display elements can be used in combination, and can be appropriately used in a display device driven by the pulse output circuit and the shift register of the present invention. Also, the configurations of the above-described display panel and the display elements are examples, and of course, other configurations can also be applied. The above-described configurations of the display elements can be used in combination, and can be appropriately used in a display device driven by the pulse output circuit and the shift register of the present invention. Also, the configurations of the above-described display panel and the display elements are examples, and of course, other configurations can also be applied. The above-described configurations of the display elements can be used in combination, and can be appropriately used in a display device driven by the pulse output circuit and the shift register of the present invention. Also, the configurations of the above-described display panel and the display elements are examples, and of course, other configurations can also be applied.

[0130] The above-described configurations of the display elements can be used in combination, and can be appropriately used in a display device driven by the pulse output circuit and the shift register of the present invention. Also, the configurations of the above-described display panel and the display elements are examples, and of course, other configurations can also be applied. The above-described configurations of the display elements can be used in combination, and can be appropriately used in a display device driven by the pulse output circuit and the shift register of the present invention. Also, the configurations of the above-described display panel and the display elements are examples, and of course, other configurations can also be applied. The above-described configurations of the display elements can be used in combination, and can be appropriately used in a display device driven by the pulse output circuit and the shift register of the present invention. Also, the configurations of the above-described display panel and the display elements are examples, and of course, other configurations can also be applied.

[0131] (Embodiment 6) The present invention can be applied to various electronic devices. Specifically, it can be applied to the driving of the display unit of an electronic device. Such electronic devices include video cameras, digital cameras, and other cameras, goggle-type displays, navigation systems, audio playback devices (such as car audio, audio components, etc.), computers, game devices, portable information terminals (mobile computers, mobile phones, portable game machines, or e-books, etc.), image playback devices equipped with a recording medium (specifically, devices equipped with a light-emitting device that can play a recording medium such as a Digital Versatile Disc (DVD) and display its image), and the like.

[0132] Figure 14(A) shows a light-emitting device, which includes a housing 6001, a support base 6002, a display unit 6003, a speaker unit 6004, a video input terminal 6005, and the like. The display device of the present invention can be used for the display unit 6003. The light-emitting device includes all light-emitting devices for information display, such as those for personal computers, television broadcast reception, and advertisement display. By driving the display unit 6003 using the shift register of the present invention, power consumption can be reduced.

[0133] Figure 14(B) shows a camera, which includes a main body 6101, a display unit 6102, an imaging unit 6103, an operation key 6104, an external connection port 6105, a shutter button 6106, and the like. By driving the display unit 6102 using the shift register of the present invention, power consumption can be reduced.

[0134] Figure 14(C) shows a computer, which includes a main body 6201, a housing 6202, a display unit 6203, a keyboard 6204, an external connection port 6205, a pointing device 6206, and the like. ​ By driving the display unit 6203 using the shift register of the present invention, power consumption can be reduced.

[0135] FIG. 14(D) shows a mobile computer, which includes a main body 6301, a display unit 6302, a switch 6303, operation keys 6304, an infrared port 6305, etc. By driving the display unit 6302 using the shift register of the present invention, power consumption can be reduced. .

[0136] FIG. 14(E) shows a portable image playback device (specifically, a DVD playback device) equipped with a recording medium , which includes a main body 6401, a housing 6402, a display unit A 6403, a display unit B 6404, a recording medium (such as a DVD) reading unit 6405, operation keys 6406, a speaker unit 6407, etc. The display unit A 6403 mainly displays image information, and the display unit B 6404 can mainly display character information. By driving the display unit A 6403 and the display unit B 6404 using the shift register of the present invention, power consumption can be reduced.

[0137] FIG. 14(F) shows a goggle-type display, which includes a main body 6501, a display unit 6502, and an arm unit 6503. By driving the display unit 6502 using the shift register of the present invention, power consumption can be reduced.

[0138] FIG. 14(G) shows a video camera, which includes a main body 6601, a display unit 6602, a housing 6603, an external connection port 6604, a remote control receiving unit 6605, an imaging unit 6606, a battery 660 7, an audio input unit 6608, operation keys 6609, an eyepiece 6610, etc. By using the shift By driving the display unit 6602 using a register, power consumption can be reduced. This can be achieved.

[0139] Figure 14(H) shows a mobile phone, which includes a main body 6701, a housing 6702, a display unit 6703, a voice input unit 6704, a voice output unit 6705, operation keys 6706, an external connection port 6707, an antenna 6708, etc. By driving the display unit 6703 using the shift register of the present invention, power consumption can be reduced.

[0140] Thus, the present invention can be applied to any electronic device.

Explanation of Reference Numerals

[0141] 10 Pulse output circuit 11 Signal line 12 Signal line 13 Signal line 14 Signal line 21 Input terminal 22 Input terminal 23 Input terminal 24 Input terminal 25 Input terminal 26 Input terminal 27 Output terminal 31 Power supply line 32 Power supply line 33 Power supply line 34 Power supply line 35 Power supply line 36 Power supply line 51 Period 52 Period 53 Period 54 Period 55 Period 101 Transistor 102 Transistor 103 Transistor 104 Transistor 105 Transistor 106 Transistor 107 Transistor 108 Transistor 109 Transistor 111 Capacitive element 112 Capacitive element

Claims

【Claim 1】 having a first transistor to a ninth transistor, a first input terminal to a sixth input terminal, and an output terminal, electrically connected to a first power line to a fifth power line, for the first transistor, a first electrode is electrically connected to the first power line, a second electrode is electrically connected to the gate electrode of the third transistor, and the gate electrode is electrically connected to the fourth input terminal; for the second transistor, a first electrode is electrically connected to the second power line, a second electrode is electrically connected to the gate electrode of the third transistor, and the gate electrode is electrically connected to the gate electrode of the fourth transistor; for the third transistor, a first electrode is electrically connected to the first input terminal, and a second electrode is electrically connected to the output terminal; for the fourth transistor, a first electrode is electrically connected to the third power line, and a second electrode is electrically connected to the output terminal; for the fifth transistor, a first electrode is electrically connected to the fourth power line, a second electrode is electrically connected to the gate electrode of the second transistor and the gate electrode of the fourth transistor, and the gate electrode is electrically connected to the fourth input terminal; for the sixth transistor, a first electrode is electrically connected to the fourth power line, a second electrode is electrically connected to the gate electrode of the second transistor and the gate electrode of the fourth transistor, and the gate electrode is electrically connected to the fifth input terminal; for the seventh transistor, a first electrode is electrically connected to the fifth power line, a second electrode is electrically connected to the gate electrode of the second transistor and the gate electrode of the fourth transistor, and the gate electrode is electrically connected to the sixth input terminal; for the eighth transistor, a first electrode is electrically connected to the fifth power line, a second electrode is electrically connected to the second electrode of the ninth transistor, and the gate electrode is electrically connected to the second input terminal; a pulse output circuit, wherein for the ninth transistor, a first electrode is electrically connected to the gate electrode of the second transistor and the gate electrode of the fourth transistor, and the gate electrode is electrically connected to the third input terminal.

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