Time digital conversion device, distance measuring device, movable body, and apparatus

Abstract

To achieve accurate time digital conversion.SOLUTION: A time digital conversion device outputs time digital data having a plurality of bits and according to the time from first timing to second timing. The time digital conversion device comprises: a first circuit that generates lower bits of the plurality of bits; a second circuit that generates upper bits of the plurality of bits; and a third circuit that generates a second signal by using a first signal output from the first circuit and outputs the second signal to the second circuit, to synchronize the first circuit and the second circuit with each other. The first signal is generated by using signals of a plurality of bits of the lower bits.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] The present invention relates to a time digital conversion device, a distance measuring device, a moving body, and a device.

Background Art

[0002] In recent years, a time digital conversion device (TDC: Time to Digital Converter) that converts time into a digital signal has been used in various fields. The time digital conversion device described in Patent Document 1 is applied to a sensor capable of imaging a three-dimensional (3D) distance image, and measures the flight time of photons detected by SPAD (Single Photon Avalanche Diode) pixels. Further, the time digital conversion device in Patent Document 1 includes an upper (Coarse) TDC and a lower (Fine) TDC.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in the time digital conversion device described in Patent Document 1, due to the connection code error between the upper TDC data and the lower TDC data, the conversion accuracy has decreased.

Means for Solving the Problems

[0005] According to one disclosure of this specification, a time digital conversion device that outputs time digital data having a plurality of bits according to the time from a first timing to a second timing, comprising: a first circuit that generates lower bits among the plurality of bits; a second circuit that generates upper bits among the plurality of bits; and a third circuit that generates a second signal using a first signal output from the first circuit and outputs the second signal to the second circuit to synchronize the first circuit and the second circuit, wherein the first signal is generated using signals of a plurality of bits among the lower bits. A time digital conversion device is provided.

Effect of the Invention

[0006] According to the present invention, it becomes possible to realize highly accurate time digital conversion.

Brief Description of the Drawings

[0007]

Figure 1

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Figure 15

Mode for Carrying Out the Invention

[0008] Hereinafter, each embodiment will be described with reference to the drawings. Note that the following embodiments do not limit the invention according to the claims. Although a plurality of features are described in the embodiments, not all of these plurality of features are essential to the invention, and the plurality of features may be arbitrarily combined. Furthermore, in the accompanying drawings, the same or similar configurations are denoted by the same reference numerals, and redundant descriptions are omitted.

[0009] In this specification, terms indicating specific directions and positions (for example, "up", "down", "right", "left", and other terms including those terms) are used as necessary. The use of those terms is for facilitating the understanding of the embodiments with reference to the drawings, and the technical scope of the present invention is not limited by the meanings of those terms.

[0010] 〈First Embodiment〉 The distance image sensor system according to the first embodiment of the present invention will be described with reference to FIG. 1.

[0011] FIG. 1 is an example of a block diagram of a distance image sensor system according to the present embodiment. The distance image sensor system is a ranging device that measures the distance to an object based on the time of flight (TOF) of light, and includes a light emitting unit 110, an optical system 105, a distance image sensor 100, an image processing circuit 101, a memory 102, and a monitor 103.

[0012] The light emitting unit 110 can irradiate the object with pulsed light such as a laser. The optical system 105 includes one or more lenses and forms an image of the image light (incident light) reflected by the object on the light receiving surface (light receiving unit) of the distance image sensor 100. The distance image sensor 100 includes a single photon avalanche diode (SPAD) that receives a single photon and a time-to-digital converter that converts the time from emission to reception into a digital signal. The image processing circuit 101 generates a distance image corresponding to the distance to the object based on the time-to-digital data output from the time-to-digital converter and the known speed of light. The generated distance image is input to the memory 102 and the monitor 103. The memory 102 stores the distance image, and the monitor 103 can display the distance image.

[0013] The distance image sensor according to the first embodiment of the present invention will be described with reference to FIG. 2.

[0014] FIG. 2 is an example of a block diagram of the distance image sensor according to the present embodiment. The distance image sensor 100 includes a plurality of pixels 10 arranged over a plurality of rows and columns, a TDC 20, a polyphase PLL (Phase Locked Loop) circuit 30, and a gray counter 40. Further, the distance image sensor 100 includes a buffer circuit 60, a vertical scanning circuit 70, a horizontal transfer circuit 50, and a digital processing circuit 90. The vertical scanning circuit 70 supplies control pulses to each of the plurality of pixels. Logic circuits such as a shift register and an address decoder are used for the vertical scanning circuit 70. The horizontal transfer circuit 50 inputs a signal to the digital processing circuit 90 based on the signal output from the time digital conversion device. The digital processing circuit 90 performs digital processing on the signal output from the horizontal transfer circuit 50. The TDC 20 converts the time from light emission to light reception into a digital signal based on signals from the plurality of pixels 10. Further, the TDC 20 corresponds to a Start channel and a Stop channel.

[0015] The pixel according to the first embodiment of the present invention will be described with reference to FIG. 3.

[0016] FIG. 3 is an example of a circuit diagram of the pixel 10 according to the present embodiment. The pixel 10 includes an SPAD 11, a quenching element 12, and a waveform shaping unit 13, and functions as a light receiving unit for pulsed light. The SPAD 11 generates a pair of charges corresponding to incident light by photoelectric conversion. A voltage VL (first voltage) is supplied to the anode of the SPAD 11, and a voltage VH (second voltage) higher than the voltage VL supplied to the anode is supplied to the cathode of the SPAD 11. A reverse bias voltage is applied between the anode and the cathode, and the SPAD 11 is in a state where avalanche multiplication is possible. When photons are incident on the SPAD 11 in a state where a reverse bias voltage is supplied, the charges generated by the photons cause avalanche multiplication, and an avalanche current is generated.

[0017] The quenching element 12 is provided between the power supply line supplying the voltage VH and the cathode of the SPAD 11. The quenching element 12 functions as a load circuit (quenching circuit) during signal multiplication by avalanche multiplication, suppresses the voltage supplied to the SPAD 11, and has the function of suppressing avalanche multiplication (quenching operation). Further, the quenching element 12 has the function of returning the voltage supplied to the SPAD 11 to the voltage VH by flowing a current corresponding to the voltage drop during the quenching operation (charging operation). The quenching element 12 and the SPAD 11 are electrically connected at the node A. The quenching element 12 may be a resistance element or a transistor having a gate to which a control signal is input. When the quenching element 12 is in the form of a transistor, the charging operation is not performed during the period when the transistor is turned off by the control signal. In this case, when the avalanche multiplication operation is performed, the voltage of the node A changes to the voltage at which the avalanche multiplication of the SPAD 11 stops. Thereafter, when the transistor is turned on by the control signal, the voltage of the node A is charged to the voltage corresponding to the voltage VH. This control signal may be a clock pulse signal. Note that the quenching element 12 may be configured to include a plurality of elements. For example, the quenching element 12 may include an element that limits the amplitude of the change in the node A and an element that charges the node A.

[0018] The waveform shaping unit 13 functions as a signal generation unit that generates a detection pulse based on the output generated by the incidence of photons. That is, the waveform shaping unit 13 shapes the potential change of the cathode of the SPAD 11 obtained at the time of photon detection and outputs a rectangular STOP signal (detection pulse). The waveform shaping unit 13 may be configured by, for example, an inverter circuit. Although one inverter circuit is shown in FIG. 3, a circuit in which a plurality of inverter circuits are connected in series may be used. Further, other circuits having a waveform shaping effect may be used.

[0019] The TDC 20 according to the first embodiment of the present invention will be described with reference to FIGS. 4 to 8.

[0020] FIG. 4 is an example of a block diagram of the TDC20 according to the present embodiment. The TDC20 is provided for each row of the pixels 10, and the pixels 10 in each column can be sequentially connected to the TDC20. The TDC20 includes a lower TDC21, an upper TDC22, and a synchronization circuit 23. In the following description, the lower TDC21 may be referred to as the first circuit, the upper TDC22 may be referred to as the second circuit, and the synchronization circuit 23 may be referred to as the third circuit. Note that the TDC20 may be provided for each pixel 10 (each light receiving unit). Note that the TDC20 may be provided for each sub-array including a plurality of pixels 10.

[0021] A START signal, a STOP signal, and a multi-phase clock signal Φ are input to the lower TDC21. The START signal is a signal synchronized with the light emission timing (the first timing) of the light emitting unit 110 in FIG. 1. The TDC20 starts time measurement in response to the START signal. The STOP signal is a signal output from the pixel 10. That is, the STOP signal represents the timing (the second timing) at which the pulsed light emitted from the light emitting unit 110 and reflected by the object is received by the pixel 10. The TDC20 outputs time digital data having a plurality of bits according to the time from the first timing to the second timing. That is, the TDC20 can convert the time from the START signal to the STOP signal into a digital signal. The multi-phase clock signal Φ is a clock signal output from the multi-phase PLL circuit 30. The lower TDC21 generates lower bits (lower results) based on the input START signal, STOP signal, and multi-phase clock signal Φ. Further, the lower TDC21 generates a One-hot signal (the first signal) based on the input START signal, STOP signal, and multi-phase clock signal Φ. The One-hot signal generated using signals of a plurality of bits among the lower bits is a 4-bit signal that is a bit string in which only 1 bit is at a high level (1) and the other bits are at a low level (0). Here, as an example, the One-hot signal is a 4-bit signal, but the number of bits is not particularly limited.

[0022] In the following, when it is necessary to distinguish the multi-phase clock signals Φ from each other, an identification number (0, 1, 2, …, 7) is added to the end of the symbol of the components of the multi-phase clock signal Φ. However, when it is not necessary to distinguish the multi-phase clock signals Φ from each other, the identification number at the end of the symbol of the components of the multi-phase clock signal Φ is omitted.

[0023] A timing signal (second signal) and a Gray code G are input to the upper TDC22. The timing signal is a signal output from the synchronization circuit 23. The Gray code G is a signal output from the Gray counter 40. The Gray code G is in binary representation such that the bit change between adjacent values is only 1 bit. The upper TDC22 generates upper bits (upper result) based on the input timing signal and Gray code G.

[0024] A START signal, a STOP signal, a multi-phase clock signal Φ, and a One-hot signal are input to the synchronization circuit 23. The One-hot signal is a signal output from the lower TDC21. The synchronization circuit 23 generates a timing signal based on the input START signal, STOP signal, multi-phase clock signal Φ, and One-hot signal. The synchronization circuit 23 outputs the timing signal to the upper TDC22 to synchronize the lower TDC21 and the upper TDC22.

[0025] In the following, when it is necessary to distinguish the Gray codes G from each other, an identification number (0, 1, 2, …, 5) is added to the end of the symbol of the components of the Gray code G. However, when it is not necessary to distinguish the Gray codes G from each other, the identification number at the end of the symbol of the components of the Gray code G is omitted.

[0026] FIG. 5 is an example of a circuit diagram of the TDC20 according to the present embodiment. The lower TDC21 includes a plurality of latch circuits 211, a differentiating circuit 212, and an encoder 213. The plurality of latch circuits 211 are D-type. Note that the plurality of D-type latch circuits 211 may be a plurality of D-type flip-flop circuits. Note that the lower TDC21 may include a plurality of D-type latch circuits 211 and a plurality of D-type flip-flop circuits. A START signal or a STOP signal is input to the inverting input node E (first input node) of the plurality of latch circuits 211, and a multi-phase clock signal Φ is input to the input node D (second input node) of the plurality of latch circuits 211. In FIG. 5, as the multi-phase clock signal Φ, for example, multi-phase clock signals Φ0 to Φ7 having different phases are input corresponding to the respective ones of the plurality of latch circuits 211-0 to 211-7. That is, the multi-phase clock signal Φ0 is input to the latch circuit 211-0, the multi-phase clock signal Φ1 is input to the latch circuit 211-1, the multi-phase clock signal Φ2 is input to the latch circuit 211-2, and the multi-phase clock signal Φ3 is input to the latch circuit 211-3. Also, the multi-phase clock signal Φ4 is input to the latch circuit 211-4, the multi-phase clock signal Φ5 is input to the latch circuit 211-5, the multi-phase clock signal Φ6 is input to the latch circuit 211-6, and the multi-phase clock signal Φ7 is input to the latch circuit 211-7. Note that the phases of the multi-phase clock signals Φ1 to Φ7 are shifted in order from the multi-phase clock signal Φ0 to the multi-phase clock signal Φ7, and the phase difference between adjacent clock signals with adjacent numbers is a predetermined amount a. The output nodes of the plurality of latch circuits 211 are connected to a differentiating circuit 212 that performs a differentiating process. The differentiating circuit 212 includes a plurality of gate circuits 214, and the output nodes of the plurality of latch circuits 211 are connected to the inverting input nodes or non-inverting input nodes of the plurality of gate circuits 214. That is, the output node of the latch circuit 211-0 is connected to the non-inverting input node of the gate circuit 214-0, and the output node of the latch circuit 211-1 is connected to the inverting input node of the gate circuit 214-0. Also, the output node of the latch circuit 211-1 is connected to the non-inverting input node of the gate circuit 214-1, and the output node of the latch circuit 211-2 is connected to the inverting input node of the gate circuit 214-1.Also, the output node of the latch circuit 211-2 is connected to the non-inverting input node of the gate circuit 214-2, and the output node of the latch circuit 211-3 is connected to the inverting input node of the gate circuit 214-2. Also, the output node of the latch circuit 211-3 is connected to the non-inverting input node of the gate circuit 214-3, and the output node of the latch circuit 211-4 is connected to the inverting input node of the gate circuit 214-3. Also, the output node of the latch circuit 211-4 is connected to the non-inverting input node of the gate circuit 214-4, and the output node of the latch circuit 211-5 is connected to the inverting input node of the gate circuit 214-4. Also, the output node of the latch circuit 211-5 is connected to the non-inverting input node of the gate circuit 214-5, and the output node of the latch circuit 211-6 is connected to the inverting input node of the gate circuit 214-5. Also, the output node of the latch circuit 211-6 is connected to the non-inverting input node of the gate circuit 214-6, and the output node of the latch circuit 211-7 is connected to the inverting input node of the gate circuit 214-6. Also, the output node of the latch circuit 211-7 is connected to the non-inverting input node of the gate circuit 214-7, and the output node of the latch circuit 211-0 is connected to the inverting input node of the gate circuit 214-7. Also, the output nodes of the plurality of gate circuits 214 are connected to the synchronization circuit 23 and the encoder 213. Then, the signals output from the output nodes of the plurality of gate circuits 214 are input to the synchronization circuit 23 as One-hot signals. The signal H0 output from the gate circuit 214-0, the signal H1 output from the gate circuit 214-1, the signal H2 output from the gate circuit 214-2, and the signal H3 output from the gate circuit 214-3 are input to the encoder 213. Also, the signal H4 output from the gate circuit 214-4, the signal H5 output from the gate circuit 214-5, the signal H6 output from the gate circuit 214-6, and the signal H7 output from the gate circuit 214-7 are input to the encoder 213. The encoder 213 encodes the signals output from the output nodes of the plurality of gate circuits 214 and outputs a binary-coded signal (lower-order result).

[0027] In the following, when it is necessary to distinguish a plurality of latch circuits 211 from each other, an identification number (0, 1, 2, …, 7) is assigned to the end of the reference numeral of the components of the latch circuit 211. However, when it is not necessary to distinguish a plurality of latch circuits 211 from each other, the identification number at the end of the reference numeral of the components of the latch circuit 211 is omitted. In the following, when it is necessary to distinguish a plurality of gate circuits 214 from each other, an identification number (0, 1, 2, …, 7) is assigned to the end of the reference numeral of the components of the gate circuit 214. However, when it is not necessary to distinguish a plurality of gate circuits 214 from each other, the identification number at the end of the reference numeral of the components of the gate circuit 214 is omitted.

[0028] The upper TDC 22 includes a plurality of latch circuits 221. The plurality of latch circuits 221 are of D type. Note that the plurality of D-type latch circuits 221 may be a plurality of D-type flip-flop circuits. Note that the upper TDC 22 may include a plurality of D-type latch circuits 221 and a plurality of D-type flip-flop circuits. A timing signal is input to the inverting input node E (first input node) of the plurality of latch circuits 221, and a Gray code G is input to the input node D (second input node) of the plurality of latch circuits 221. The signals output from the plurality of latch circuits 221 are output as upper results.

[0029] In the following, when it is necessary to distinguish a plurality of latch circuits 221 from each other, an identification number (0, 1, 2, …, 7) is assigned to the end of the reference numeral of the components of the latch circuit 221. However, when it is not necessary to distinguish a plurality of latch circuits 221 from each other, the identification number at the end of the reference numeral of the components of the latch circuit 221 is omitted.

[0030] The synchronization circuit 23 includes a first flip-flop circuit 231, a second flip-flop circuit 232, a third flip-flop circuit 233, a multiplexer (selection circuit) 234, and a selection signal generation circuit 235. The first flip-flop circuit 231, the second flip-flop circuit 232, and the third flip-flop circuit 233 are D-type. Note that the first flip-flop circuit 231, the second flip-flop circuit 232, and the third flip-flop circuit 233 may be D-type latch circuits. Note that the synchronization circuit 23 may include a plurality of flip-flop circuits and a plurality of latch circuits. A START signal or a STOP signal is input to the input node D (first input node) of the first flip-flop circuit 231 and the second flip-flop circuit 232. Also, a multi-phase clock signal Φ is input to the clock nodes (second input nodes) of the first flip-flop circuit 231 and the second flip-flop circuit 232. In FIG. 5, as the multi-phase clock signal Φ, for example, the multi-phase clock signal Φ6 among the multi-phase clock signals Φ1 to Φ7 with different phases is input to the first flip-flop circuit 231, and the multi-phase clock signal Φ2 is input to the second flip-flop circuit 232. Note that the phase difference between the phase of the multi-phase clock signal Φ2 and the phase of the multi-phase clock signal Φ6 is set to half a cycle. The output node of the first flip-flop circuit 231 is connected to input node 1 of the multiplexer 234, and the output node of the second flip-flop circuit 232 is connected to input node 0 of the multiplexer 234. The signal output by the first flip-flop circuit 231 is referred to as signal A. Also, the signal output by the second flip-flop circuit 232 is referred to as signal B. The output nodes of the gate circuits 214-0, 214-1, 214-2, 214-3 are connected to a plurality of input nodes of the selection signal generation circuit 235. Also, the signals output from the respective output nodes are input as one-hot signals to the plurality of input nodes of the selection signal generation circuit 235. For example, signal H0, signal H1, signal H2, and signal H3 are input to the selection signal generation circuit 235. The output node of the selection signal generation circuit 235 is connected to the multiplexer 234, and the selection signal generation circuit 235 outputs a selection signal. The output node of the multiplexer 234 is connected to the input node D of the third flip-flop circuit 233.Let the signal output by the multiplexer 234 be the C signal. The multiplexer 234 outputs the C signal generated using the A signal or the B signal to the third flip-flop circuit 233 based on the selection signal. That is, the multiplexer 234 selects one of the A signal or the B signal and outputs the selected signal as the C signal. The C signal output from the multiplexer 234 is input to the input node D of the third flip-flop circuit 233, and the multi-phase clock signal Φ is input to the clock node of the third flip-flop circuit 233. In FIG. 5, as the multi-phase clock signal Φ, for example, the multi-phase clock signal Φ6 input to the first flip-flop circuit 231 is also input to the third flip-flop circuit 233. The output node of the third flip-flop circuit 233 is connected to the inverted input node E of the plurality of latch circuits 221 included in the upper TDC 22. The timing signal output from the third flip-flop circuit 233 is input to the plurality of latch circuits 221.

[0031] FIG. 6 is an example of a drive timing chart of the distance image sensor according to the present embodiment. In an actual circuit, an operation delay may occur. Therefore, in the drive timing chart of FIG. 6, the START signal considering the operation delay of the circuit is denoted as the START signal (delay).

[0032] At time t10, the START signal transitions from the low level to the high level (the first timing). However, due to the influence of the operation delay of the circuit, actually, at time t10, the light emitting unit 110 does not emit pulsed light toward the object. At time t20, the START signal (delay) transitions from the low level to the high level, and the light emitting unit 110 emits pulsed light toward the object. At time t30, the pixel 10 detects the pulsed light reflected by the object and outputs the STOP signal (the second timing).

[0033] The lower TDC21 corresponding to the Start channel and the upper TDC22 corresponding to the Start channel perform time-to-digital conversion on the time from time t10 to time t20 and output a digital signal A. The lower TDC21 corresponding to the Stop channel and the upper TDC22 corresponding to the Stop channel perform time-to-digital conversion on the time from time t10 to time t30 and output a digital signal B. A digital signal C is generated by subtracting the digital signal A output from the lower TDC21 corresponding to the Start channel from the digital signal B output from the lower TDC21 corresponding to the Stop channel. A digital signal D is generated by subtracting the digital signal A output from the upper TDC22 corresponding to the Start channel from the digital signal B output from the upper TDC22 corresponding to the Stop channel. The digital signal obtained by combining the digital signal C and the digital signal D is the digital signal corresponding to the time from light emission to light reception.

[0034] FIGS. 7 and 8 are examples of drive timing charts of the TDC20 corresponding to the Stop channel according to the present embodiment. Note that FIGS. 7 and 8 show examples in which the timing at which the STOP signal transitions from the low level to the high level and the phase of the multiphase clock signal Φ are different.

[0035] In FIGS. 7 and 8, at time t30, the STOP signal transitions from the low level to the high level, and after time t34, the STOP signal transitions from the high level to the low level.

[0036] The STOP signal is input to the inverted input node E of the plurality of latch circuits 211, and the multiphase clock signal Φ is input to the input node D of the plurality of latch circuits 211. Therefore, at least during the period from time t30 to time t34, the plurality of latch circuits 211 output the level (for example, low level or high level) of the multiphase clock signal Φ input to the input node D at time t30.

[0037] Also, the plurality of gate circuits 214 output a high-level signal when the signal input to the inverting input node is at a low level and the signal input to the non-inverting input node is at a high level. Also, the plurality of gate circuits 214 output a low-level signal when the signal input to the inverting input node is at a high level or the signal input to the non-inverting input node is at a low level.

[0038] Also, the selection signal generation circuit 235 outputs, as a selection signal, the result of an OR operation using the signals respectively output from the gate circuits 214-0, 214-1, 214-2, and 214-3.

[0039] Also, a STOP signal is input to the input node D of the first flip-flop circuit 231 and the second flip-flop circuit 232. Also, a polyphase clock signal Φ6 is input to the clock node of the first flip-flop circuit 231. Also, a polyphase clock signal Φ2 is input to the clock node of the second flip-flop circuit 232. Therefore, before the polyphase clock signal Φ6 transitions from a low level to a high level during the period from time t30 to time t34, the first flip-flop circuit 231 outputs a low-level signal as the A signal. Also, after the polyphase clock signal Φ6 transitions from a low level to a high level during the period from time t30 to time t34, the first flip-flop circuit 231 outputs a high-level signal as the A signal. Also, before the polyphase clock signal Φ2 transitions from a low level to a high level during the period from time t30 to time t34, the second flip-flop circuit 232 outputs a low-level signal as the B signal. Also, after the polyphase clock signal Φ2 transitions from a low level to a high level during the period from time t30 to time t34, the second flip-flop circuit 232 outputs a high-level signal as the B signal.

[0040] Also, an A signal is input to input node 1 of multiplexer 234, and a B signal is input to input node 0 of multiplexer 234. Multiplexer 234 outputs one of the A signal or the B signal as a C signal based on the selection signal. For example, multiplexer 234 outputs the A signal as the C signal when the selection signal is at a high level, and outputs the B signal as the C signal when the selection signal is at a low level.

[0041] Also, a C signal is input to input node D of the third flip-flop circuit 233, and a polyphase clock signal Φ6 is input to the clock node of the third flip-flop circuit 233. Therefore, during the period from time t30 to time t34, the third flip-flop circuit 233 outputs the C signal at the time when the polyphase clock signal Φ6 transitions from a low level to a high level as a timing signal.

[0042] Also, a timing signal is input to the inverted input node E of the plurality of latch circuits 221, and a Gray code G is input to the input node D of the plurality of latch circuits 221. Therefore, during the period from time t30 to time t34, after the timing signal input to the inverted input node E of the plurality of latch circuits 221 transitions to a high level, the plurality of latch circuits 221 output the level of the Gray code G input to the input node D.

[0043] With the above driving, the lower TDC 21 outputs a lower result corresponding to the lower bits based on the signals output from the plurality of gate circuits 214. Also, the upper TDC 22 outputs an upper result corresponding to the upper bits based on the signals output from the plurality of latch circuits 221.

[0044] Figure 7 shows that at time t30, the polyphase clock signals Φ0, Φ1, and Φ7 are at high levels, and the polyphase clock signals Φ3 to Φ5 are at low levels. Also at time t30, the polyphase clock signal Φ2 transitions from a low level to a high level, and the polyphase clock signal Φ6 transitions from a high level to a low level. Therefore, in response to the STOP signal transitioning from a low level to a high level, the latch circuits 211-0 to 211-2, 211-7 output high-level signals, and the latch circuits 211-3 to 211-6 output low-level signals. Then, based on the signals output from the plurality of latch circuits 211, the gate circuit 214-2 outputs a high-level signal, and the gate circuits 214-0, 214-1, 214-3 to 214-7 output low-level signals. The encoder 213 determines, for example, "2" as the lower bit based on the high-level signal output from the gate circuit 214-2. Note that in this specification, for convenience, the value of the lower bit is represented in decimal, but actually, a signal represented in binary is held.

[0045] Also, at time t30, since the input polyphase clock signal Φ6 has not yet transitioned from a low level to a high level, the first flip-flop circuit 231 outputs a low-level signal as the A signal. Also at time t30, since the input polyphase clock signal Φ2 transitions from a low level to a high level, the second flip-flop circuit 232 outputs a high-level signal as the B signal. Also, since a high-level signal is input to the selection signal generation circuit 235 from the gate circuit 214-2, the selection signal generation circuit 235 outputs a high-level signal as the selection signal. Also, since a high-level signal is input to the multiplexer 234 as the selection signal, the multiplexer 234 outputs the A signal, that is, the low-level signal, as the C signal. Also, since a low-level signal is input to the third flip-flop circuit 233 as the C signal, the third flip-flop circuit 233 outputs a low-level signal as the timing signal.

[0046] At time t31, the multi-phase clock signal Φ6 transitions from a low level to a high level, and the multi-phase clock signal Φ2 transitions from a high level to a low level. Since the input multi-phase clock signal Φ6 transitions from a low level to a high level, the first flip-flop circuit 231 outputs a high-level signal as the A signal. Also, the second flip-flop circuit 232 continues to output a high-level signal as the B signal from time t30. Further, since a high-level signal is input from the gate circuit 214-2 to the selection signal generation circuit 235 continuously from time t30, the selection signal generation circuit 235 outputs a high-level signal as the selection signal. Also, since a high-level signal is input as the selection signal to the multiplexer 234 continuously from time t30, the multiplexer 234 outputs the A signal, that is, a high-level signal, as the C signal. Here, while the first flip-flop circuit 231 and the second flip-flop circuit 232 are provided in the first stage, the third flip-flop circuit 233 is provided in the second stage. Therefore, in response to the multi-phase clock signal Φ6 transitioning from a low level to a high level, the A signal output from the first flip-flop circuit 231 is input to the third flip-flop circuit 233 as the C signal via the multiplexer 234. That is, the output result of the first flip-flop circuit 231 is input to the third flip-flop circuit 233 under the influence of signal delay through the multiplexer 234. Thus, after the multi-phase clock signal Φ6 transitions from a low level to a high level, a high-level signal is input to the third flip-flop circuit 233 as the C signal. Therefore, the third flip-flop circuit 233 outputs a low-level signal as the timing signal based on the low-level C signal input at the time when the multi-phase clock signal Φ6 transitions from a low level to a high level.

[0047] At time t32, the polyphase clock signal Φ6 transitions from a high level to a low level, and the polyphase clock signal Φ2 transitions from a low level to a high level. The first flip-flop circuit 231 continues to output a high-level signal as the A signal from time t31. Also, the second flip-flop circuit 232 continues to output a high-level signal as the B signal from time t30. Further, since a high-level signal is input from the gate circuit 214-2 to the selection signal generation circuit 235 continuously from time t30, the selection signal generation circuit 235 outputs a high-level signal as the selection signal. Also, since a high-level signal is input as the selection signal to the multiplexer 234 from time t30, the multiplexer 234 outputs the A signal, that is, a high-level signal, as the C signal. Further, although a high-level signal is input to the third flip-flop circuit 233 as the C signal, since the input polyphase clock signal Φ6 is before transitioning from a low level to a high level, the third flip-flop circuit 233 outputs a low-level signal as the timing signal.

[0048] At time t33, the multi-phase clock signal Φ6 transitions from a low level to a high level, and the multi-phase clock signal Φ2 transitions from a high level to a low level. The first flip-flop circuit 231 continues to output a high-level signal as the A signal since time t31. Also, the second flip-flop circuit 232 continues to output a high-level signal as the B signal since time t30. Further, since a high-level signal is input from the gate circuit 214-2 to the selection signal generation circuit 235 continuously from time t30, the selection signal generation circuit 235 outputs a high-level signal as the selection signal. Also, since a high-level signal is input as the selection signal to the multiplexer 234 continuously from time t30, the multiplexer 234 outputs the A signal, that is, a high-level signal, as the C signal. Further, since a high-level signal is input as the C signal to the third flip-flop circuit 233, in response to the input multi-phase clock signal Φ6 transitioning from a low level to a high level, the third flip-flop circuit 233 outputs a high-level signal as the timing signal. Furthermore, based on the high-level signal output as the timing signal and the Gray code G, for example, "8" is determined as the upper bit. Note that in this specification, for convenience, the signal of the upper bit is also represented in decimal in the same way as the lower bit, but it is actually held as a binary signal.

[0049] Note that at time t30, the STOP signal transitions from a low level to a high level, and while the polyphase clock signal Φ2 transitions from a low level to a high level, the second flip-flop circuit 232 may output a low-level signal as the B signal. This is because when the timings of the two input signals transitioning from a low level to a high level are close, due to performance limitations, the second flip-flop circuit 232 does not function properly as a flip-flop circuit. Also, at time t30, after the polyphase clock signal Φ2 transitions from a low level to a high level, the STOP signal transitions from a low level to a high level, and the second flip-flop circuit 232 may output a low-level signal as the B signal. This is due to the operation delay of the circuit that generates the STOP signal or the circuit that transmits the STOP signal. However, in the present embodiment, high-precision time digital conversion is possible because the B signal whose signal level may not be determined as described above is not used to generate the upper bits.

[0050] FIG. 8 shows that at time t30, the polyphase clock signals Φ3 to Φ5 are at a high level, and the polyphase clock signals Φ0, Φ1, and Φ7 are at a low level. Also, at time t30, the polyphase clock signal Φ2 transitions from a high level to a low level, and the polyphase clock signal Φ6 transitions from a low level to a high level. Therefore, in response to the STOP signal transitioning from a low level to a high level, the latch circuits 211-3 to 211-6 output high-level signals, and the latch circuits 211-0 to 211-2 and 211-7 output low-level signals. Then, based on the signals output from the plurality of latch circuits 211, the gate circuit 214-6 outputs a high-level signal, and the gate circuits 214-0 to 214-5 and 214-7 output low-level signals. The encoder 213 determines, for example, "6" as the lower bit based on the high-level signal output from the gate circuit 214-6. Note that in this specification, for convenience, the value of the lower bit is represented in decimal, but actually, a signal represented in binary is held.

[0051] Also, at time t30, since the input polyphase clock signal Φ6 transitions from a low level to a high level, the first flip-flop circuit 231 outputs a high-level signal as the A signal. Also, at time t30, since the input polyphase clock signal Φ2 is before transitioning from a low level to a high level, the second flip-flop circuit 232 outputs a low-level signal as the B signal. Also, since low-level signals are input to the selection signal generation circuit 235 from the gate circuits 214-0 to 214-3, the selection signal generation circuit 235 outputs a low-level signal as the selection signal. Also, since a low-level signal is input to the multiplexer 234 as the selection signal, the multiplexer 234 outputs the B signal, that is, the low-level signal, as the C signal. Also, since a low-level signal is input to the third flip-flop circuit 233 as the C signal, the third flip-flop circuit 233 outputs a low-level signal as the timing signal.

[0052] At time t31, the polyphase clock signal Φ6 transitions from a high level to a low level, and the polyphase clock signal Φ2 transitions from a low level to a high level. The first flip-flop circuit 231 continues to output a high-level signal as the A signal from time t30. Also, since the input polyphase clock signal Φ2 transitions from a low level to a high level, the second flip-flop circuit 232 outputs a high-level signal as the B signal. Also, since low-level signals are input to the selection signal generation circuit 235 from the gate circuits 214-0 to 214-3 continuously from time t30, the selection signal generation circuit 235 outputs a low-level signal as the selection signal. Also, since a low-level signal is input to the multiplexer 234 as the selection signal continuously from time t30, the multiplexer 234 outputs the B signal, that is, the high-level signal, as the C signal. Also, although a high-level signal is input to the third flip-flop circuit 233 as the C signal, since the input polyphase clock signal Φ6 is before transitioning from a low level to a high level, the third flip-flop circuit 233 outputs a low-level signal as the timing signal.

[0053] At time t32, the multi-phase clock signal Φ6 transitions from a low level to a high level, and the multi-phase clock signal Φ2 transitions from a high level to a low level. The first flip-flop circuit 231 continues to output a high-level signal as the A signal since time t30. Also, the second flip-flop circuit 232 continues to output a high-level signal as the B signal since time t31. Further, since a low-level signal is input to the gate circuits 214-0 to 214-3 from time t30, the selection signal generation circuit 235 outputs a low-level signal as the selection signal. Also, since a low-level signal is input as the selection signal to the multiplexer 234 from time t30, the multiplexer 234 outputs the B signal, that is, a high-level signal, as the C signal. Further, since a high-level signal is input as the C signal to the third flip-flop circuit 233, in response to the input multi-phase clock signal Φ6 transitioning from a low level to a high level, the third flip-flop circuit 233 outputs a high-level signal as the timing signal. Furthermore, based on the high-level signal output as the timing signal and the Gray code G, for example, "7" is determined as the upper bit. In this specification, for convenience, the upper-bit signal is also represented in decimal in the same way as the lower bits, but in reality, it is held as a binary signal.

[0054] Note that at time t30, while the STOP signal transitions from the low level to the high level and the multiphase clock signal Φ6 transitions from the low level to the high level, the first flip-flop circuit 231 may output a low-level signal as the A signal. This is because when the timings of the two input signals transitioning from the low level to the high level are close, the first flip-flop circuit 231 does not function properly as a flip-flop circuit due to performance limitations. Also, at time t30, after the multiphase clock signal Φ6 transitions from the low level to the high level, the STOP signal transitions from the low level to the high level, and the first flip-flop circuit 231 may output a low-level signal as the A signal. This is due to the operation delay of the circuit that generates the STOP signal or the circuit that transmits the STOP signal. However, in this embodiment, high-precision time digital conversion is possible because the A signal whose signal level may not be determined as described above is not used to generate the upper bits.

[0055] Therefore, this embodiment can achieve high-precision time digital conversion even when the timing at which the STOP signal transitions from the low level to the high level is close to the timing at which the multiphase clock signal Φ transitions from the low level to the high level or when an operation delay of the circuit occurs.

[0056] FIG. 9 is an example of a drive timing chart of the TDC20 corresponding to the Stop channel according to this embodiment. FIG. 9 shows a case in FIG. 7 where the signal quality of the multiphase clock signal Φ deteriorates, for example, due to deterioration of the duty ratio of the multiphase clock signal Φ. For example, in FIG. 9, compared with FIG. 7, the falling timing of the multiphase clock signal Φ is earlier, and the ratio of the multiphase clock signal Φ being a low-level signal is increasing.

[0057] Figure 9 shows that at time t30, the STOP signal transitions from a low level to a high level, and after time t34, the STOP signal transitions from a high level to a low level. At time t30, the polyphase clock signal Φ1 is at a high level, the polyphase clock signals Φ3 to Φ7 are at a low level, the polyphase clock signal Φ0 transitions from a high level to a low level, and the polyphase clock signal Φ2 transitions from a low level to a high level. Therefore, in response to the STOP signal transitioning from a low level to a high level, the latch circuits 211-1 and 211-2 output high-level signals, and the latch circuits 211-0, 211-3 to 211-7 output low-level signals. Then, based on the signals output from the plurality of latch circuits 211, the gate circuit 214-2 outputs a high-level signal, and the gate circuits 214-0, 214-1, 214-3 to 214-7 output low-level signals. The encoder 213 determines, for example, "2" as the lower bit based on the high-level signal output from the gate circuit 214-2. Note that in this specification, for convenience, the value of the lower bit is represented in decimal, but actually, a signal represented in binary is held.

[0058] Also, at time t30, since the input polyphase clock signal Φ6 to the first flip-flop circuit 231 has not yet transitioned from a low level to a high level, the first flip-flop circuit 231 outputs a low-level signal as the A signal. Also, at time t30, since the input polyphase clock signal Φ2 to the second flip-flop circuit 232 transitions from a low level to a high level, the second flip-flop circuit 232 outputs a high-level signal as the B signal. Also, since a high-level signal is input from the gate circuit 214-2 to the selection signal generation circuit 235, the selection signal generation circuit 235 outputs a high-level signal as the selection signal. Also, since a high-level signal is input as the selection signal to the multiplexer 234, the multiplexer 234 outputs the A signal, that is, the low-level signal, as the C signal. Also, since a low-level signal is input as the C signal to the third flip-flop circuit 233, the third flip-flop circuit 233 outputs a low-level signal as the timing signal.

[0059] During the period from time t30 to time t31, the polyphase clock signal Φ2 transitions from a high level to a low level, and at time t31, the polyphase clock signal Φ6 transitions from a low level to a high level. Since the input polyphase clock signal Φ6 transitions from a low level to a high level, the first flip-flop circuit 231 outputs a high-level signal as the A signal. Also, the second flip-flop circuit 232 continues to output a high-level signal as the B signal from time t30. Further, since a high-level signal is input to the selection signal generation circuit 235 from the gate circuit 214-2 continuously from time t30, the selection signal generation circuit 235 outputs a high-level signal as the selection signal. Also, since a high-level signal is input to the multiplexer 234 as the selection signal continuously from time t30, the multiplexer 234 outputs the A signal, that is, a high-level signal, as the C signal. Here, while the first flip-flop circuit 231 and the second flip-flop circuit 232 are provided in the first stage, the third flip-flop circuit 233 is provided in the second stage. Therefore, in response to the polyphase clock signal Φ6 transitioning from a low level to a high level, the A signal output from the first flip-flop circuit 231 is input to the third flip-flop circuit 233 as the C signal via the multiplexer 234. That is, the output result of the first flip-flop circuit 231 is input to the third flip-flop circuit 233 under the influence of signal delay through the multiplexer 234. Thus, the third flip-flop circuit 233 will have a high-level signal input as the C signal after the polyphase clock signal Φ6 transitions from a low level to a high level. Therefore, the third flip-flop circuit 233 outputs a low-level signal as the timing signal based on the low-level C signal input at the time when the polyphase clock signal Φ6 transitions from a low level to a high level.

[0060] During the period from time t31 to time t32, the polyphase clock signal Φ6 transitions from a high level to a low level, and at time t32, the polyphase clock signal Φ2 transitions from a low level to a high level. The first flip-flop circuit 231 continues to output a high-level signal as the A signal from time t31. Also, the second flip-flop circuit 232 continues to output a high-level signal as the B signal from time t30. Further, since a high-level signal is input to the selection signal generation circuit 235 from the gate circuit 214-2 continuously from time t30, it outputs a high-level signal as the selection signal. Also, since a high-level signal is input to the multiplexer 234 as the selection signal continuously from time t30, it outputs the A signal, that is, a high-level signal, as the C signal. Also, although a high-level signal is input to the third flip-flop circuit 233 as the C signal, since the input polyphase clock signal Φ6 is before transitioning from a low level to a high level, it outputs a low-level signal as the timing signal.

[0061] At time t33, the polyphase clock signal Φ6 transitions from a low level to a high level. The first flip-flop circuit 231 continues to output a high-level signal as the A signal since time t31. Also, the second flip-flop circuit 232 continues to output a high-level signal as the B signal since time t30. Further, since a high-level signal is input from the gate circuit 214-2 to the selection signal generation circuit 235 since time t30, the selection signal generation circuit 235 outputs a high-level signal as the selection signal. Also, since a high-level signal is input as the selection signal to the multiplexer 234 since time t30, the multiplexer 234 outputs the A signal, that is, a high-level signal, as the C signal. Further, since a high-level signal is input as the C signal to the third flip-flop circuit 233, in response to the input polyphase clock signal Φ6 transitioning from a low level to a high level, the third flip-flop circuit 233 outputs a high-level signal as the timing signal. Furthermore, based on the high-level signal output as the timing signal and the Gray code G, for example, "8" is determined as the upper bit. Note that in this specification, for convenience, the upper-bit signal is also represented in decimal like the lower bits, but actually it is held as a binary signal.

[0062] Note that at time t30, while the STOP signal transitions from a low level to a high level and the polyphase clock signal Φ2 transitions from a low level to a high level, the second flip-flop circuit 232 may output a low-level signal as the B signal. This is because when the timing of the two input signals transitioning from a low level to a high level is close, due to performance limitations, the second flip-flop circuit 232 does not function properly as a flip-flop circuit. Also, at time t30, after the polyphase clock signal Φ2 transitions from a low level to a high level, the STOP signal transitions from a low level to a high level, and the second flip-flop circuit 232 may output a low-level signal as the B signal. This is due to the operation delay of the circuit that generates the STOP signal or the circuit that transmits the STOP signal. However, in the present embodiment, high-precision time digital conversion is possible because the B signal whose signal level may not be determined as described above is not used to generate the upper bits. Therefore, the present embodiment enables high-precision time digital conversion even when the signal quality of the polyphase clock signal Φ deteriorates due to, for example, deterioration of the duty ratio of the polyphase clock signal Φ.

[0063] The TDC20 according to the reference example will be described with reference to FIGS. 10 to 12. Note that the same reference numerals are assigned to the same components as in the first embodiment, and the description of these components may be omitted or simplified.

[0064] The reference example is different from the first embodiment in that it does not have the selection signal generation circuit 235. In the reference example, a signal output from one of the plurality of latch circuits 211 included in the lower TDC21 is input to the multiplexer 234 included in the synchronization circuit 23. FIG. 10 is an example of a circuit diagram of the TDC20 according to the reference example.

[0065] The lower TDC21 includes a plurality of latch circuits 211, a differentiating circuit 212, and an encoder 213. The plurality of latch circuits 211 are of D type. Note that the plurality of D-type latch circuits 211 may be a plurality of D-type flip-flop circuits. Note that the lower TDC21 may include a plurality of D-type latch circuits 211 and a plurality of D-type flip-flop circuits. A START signal or a STOP signal is input to the inversion input node E (first input node) of the plurality of latch circuits 211, and a multi-phase clock signal Φ is input to the input node D (second input node) of the plurality of latch circuits 211. In FIG. 10, as the multi-phase clock signal Φ, for example, multi-phase clock signals Φ0 to Φ7 having different phases are input corresponding to the respective ones of the plurality of latch circuits 211-0 to 211-7. That is, the multi-phase clock signal Φ0 is input to the latch circuit 211-0, the multi-phase clock signal Φ1 is input to the latch circuit 211-1, the multi-phase clock signal Φ2 is input to the latch circuit 211-2, and the multi-phase clock signal Φ3 is input to the latch circuit 211-3. Also, the multi-phase clock signal Φ4 is input to the latch circuit 211-4, the multi-phase clock signal Φ5 is input to the latch circuit 211-5, the multi-phase clock signal Φ6 is input to the latch circuit 211-6, and the multi-phase clock signal Φ7 is input to the latch circuit 211-7. Note that the phases of the multi-phase clock signals Φ1 to Φ7 are shifted in order from the multi-phase clock signal Φ0 to the multi-phase clock signal Φ7, and the phase difference between adjacent clock signals with adjacent numbers is a predetermined amount a. The output node of the latch circuit 211-0 is connected to the multiplexer 234 included in the synchronization circuit 23. Also, the output nodes of the plurality of latch circuits 211 are connected to the differentiating circuit 212. The differentiating circuit 212 includes a plurality of gate circuits 214, and the output nodes of the plurality of latch circuits 211 are connected to the inversion input nodes or non-inversion input nodes of the plurality of gate circuits 214. That is, the output node of the latch circuit 211-0 is connected to the non-inversion input node of the gate circuit 214-0, and the output node of the latch circuit 211-1 is connected to the inversion input node of the gate circuit 214-0. Also, the output node of the latch circuit 211-1 is connected to the non-inversion input node of the gate circuit 214-1, and the output node of the latch circuit 211-2 is connected to the inversion input node of the gate circuit 214-1.Also, the output node of the latch circuit 211-2 is connected to the non-inverting input node of the gate circuit 214-2, and the output node of the latch circuit 211-3 is connected to the inverting input node of the gate circuit 214-2. Also, the output node of the latch circuit 211-3 is connected to the non-inverting input node of the gate circuit 214-3, and the output node of the latch circuit 211-4 is connected to the inverting input node of the gate circuit 214-3. Also, the output node of the latch circuit 211-4 is connected to the non-inverting input node of the gate circuit 214-4, and the output node of the latch circuit 211-5 is connected to the inverting input node of the gate circuit 214-4. Also, the output node of the latch circuit 211-5 is connected to the non-inverting input node of the gate circuit 214-5, and the output node of the latch circuit 211-6 is connected to the inverting input node of the gate circuit 214-5. Also, the output node of the latch circuit 211-6 is connected to the non-inverting input node of the gate circuit 214-6, and the output node of the latch circuit 211-7 is connected to the inverting input node of the gate circuit 214-6. Also, the output node of the latch circuit 211-7 is connected to the non-inverting input node of the gate circuit 214-7, and the output node of the latch circuit 211-0 is connected to the inverting input node of the gate circuit 214-7. Also, the output nodes of the plurality of gate circuits 214 are connected to the encoder 213. The signal H0 output from the gate circuit 214-0, the signal H1 output from the gate circuit 214-1, the signal H2 output from the gate circuit 214-2, and the signal H3 output from the gate circuit 214-3 are input to the encoder 213. Also, the signal H4 output from the gate circuit 214-4, the signal H5 output from the gate circuit 214-5, the signal H6 output from the gate circuit 214-6, and the signal H7 output from the gate circuit 214-7 are input to the encoder 213. The encoder 213 encodes the signals output from the output nodes of the plurality of gate circuits 214 and outputs a binary-coded signal (lower-order result).

[0066] The upper TDC 22 includes a plurality of latch circuits 221. The plurality of latch circuits 221 are D-type. Note that the plurality of D-type latch circuits 221 may be a plurality of D-type flip-flop circuits. Note that the upper TDC 22 may include a plurality of D-type latch circuits 221 and a plurality of D-type flip-flop circuits. A timing signal is input to the inverted input node E (first input node) of the plurality of latch circuits 221, and a Gray code G is input to the input node D (second input node) of the plurality of latch circuits 211. The signal output from the plurality of latch circuits 221 is output as the upper result.

[0067] The synchronization circuit 23 includes a first flip-flop circuit 231, a second flip-flop circuit 232, a third flip-flop circuit 233, and a multiplexer 234. The first flip-flop circuit 231, the second flip-flop circuit 232, and the third flip-flop circuit 233 are of the D type. Note that the first flip-flop circuit 231, the second flip-flop circuit 232, and the third flip-flop circuit 233 may be D-type latch circuits. Note that the synchronization circuit 23 may include a plurality of flip-flop circuits and a plurality of latch circuits. A START signal or a STOP signal is input to the input node D (first input node) of the first flip-flop circuit 231 and the second flip-flop circuit 232. Also, a multiphase clock signal Φ is input to the clock nodes (second input nodes) of the first flip-flop circuit 231 and the second flip-flop circuit 232. In FIG. 10, as the multiphase clock signal Φ, for example, the multiphase clock signal Φ6 among the multiphase clock signals Φ1 to Φ7 with different phases is input to the first flip-flop circuit 231, and the multiphase clock signal Φ2 is input to the second flip-flop circuit 232. Note that the phase difference between the phase of the multiphase clock signal Φ2 and the phase of the multiphase clock signal Φ6 is set to half a cycle. The output node of the first flip-flop circuit 231 is connected to input node 1 of the multiplexer 234, and the output node of the second flip-flop circuit 232 is connected to input node 0 of the multiplexer 234. Let the signal output by the first flip-flop circuit 231 be the A signal. Also, let the signal output by the second flip-flop circuit 232 be the B signal. Also, the control signal output from the latch circuit 211-0 is input to the multiplexer 234. The output node of the multiplexer 234 is connected to the input node D of the third flip-flop circuit 233. Let the signal output by the multiplexer 234 be the C signal. The multiplexer 234 outputs the C signal generated using the A signal or the B signal to the third flip-flop circuit 233 based on the control signal. That is, the multiplexer 234 selects one of the A signal and the B signal and outputs the selected signal as the C signal.The C signal output from the multiplexer 234 is input to the input node D of the third flip-flop circuit 233, and the polyphase clock signal Φ is input to the clock node of the third flip-flop circuit 233. In FIG. 10, as the polyphase clock signal Φ, for example, the polyphase clock signal Φ6 input to the first flip-flop circuit 231 is also input to the third flip-flop circuit 233. The output node of the third flip-flop circuit 233 is connected to the inverted input node E of the plurality of latch circuits 221 included in the upper TDC 22. The timing signal output from the third flip-flop circuit 233 is input to the plurality of latch circuits 221.

[0068] FIG. 11 is an example of a drive timing chart of the TDC 20 corresponding to the Stop channel according to the reference example. Similar to FIG. 9, FIG. 11 shows a case where the signal quality of the polyphase clock signal Φ deteriorates due to, for example, deterioration of the duty ratio of the polyphase clock signal Φ in FIG. 7.

[0069] In FIG. 11, at time t30, the STOP signal transitions from a low level to a high level, and after time t34, the STOP signal transitions from a high level to a low level.

[0070] The STOP signal is input to the inverted input node E of the plurality of latch circuits 211, and the polyphase clock signal Φ is input to the input node D of the plurality of latch circuits 211. Therefore, at least during the period from time t30 to time t34, the plurality of latch circuits 211 output the level (for example, low level or high level) of the polyphase clock signal Φ input to the input node D at time t30.

[0071] Also, the plurality of gate circuits 214 output a high-level signal when the signal input to the inverted input node is at a low level and the signal input to the non-inverted input node is at a high level. Also, when the signal input to the inverted input node is at a high level or the signal input to the non-inverted input node is at a low level, a low-level signal is output.

[0072] Also, a STOP signal is input to the input node D of the first flip-flop circuit 231 and the second flip-flop circuit 232. Also, a polyphase clock signal Φ6 is input to the clock node of the first flip-flop circuit 231. Also, a polyphase clock signal Φ2 is input to the clock node of the second flip-flop circuit 232. Therefore, before the polyphase clock signal Φ6 transitions from the low level to the high level during the period from time t30 to time t34, the first flip-flop circuit 231 outputs a low-level signal as the A signal. Also, after the polyphase clock signal Φ6 transitions from the low level to the high level during the period from time t30 to time t34, the first flip-flop circuit 231 outputs a high-level signal as the A signal. Also, before the polyphase clock signal Φ2 transitions from the low level to the high level during the period from time t30 to time t34, the second flip-flop circuit 232 outputs a low-level signal as the B signal. Also, after the polyphase clock signal Φ2 transitions from the low level to the high level during the period from time t30 to time t34, the second flip-flop circuit 232 outputs a high-level signal as the B signal.

[0073] Also, the A signal is input to the input node 1 of the multiplexer 234, and the B signal is input to the input node 0 of the multiplexer 234. The multiplexer 234 outputs one of the A signal or the B signal as the C signal based on the control signal input from the latch circuit 211-0. For example, the multiplexer 234 outputs the A signal as the C signal when the control signal is at the high level, and outputs the B signal as the C signal when the control signal is at the low level.

[0074] Also, the C signal is input to the input node D of the third flip-flop circuit 233, and the polyphase clock signal Φ6 is input to the clock node of the third flip-flop circuit 233. Therefore, during the period from time t30 to time t34, the third flip-flop circuit 233 outputs the C signal at the time when the polyphase clock signal Φ6 transitions from the low level to the high level as the timing signal.

[0075] Further, a timing signal is input to the inversion input node E of the plurality of latch circuits 221, and a Gray code G is input to the input node D of the plurality of latch circuits 221. Therefore, during the period from time t30 to time t34, after the timing signal input to the inversion input node E of the plurality of latch circuits 221 transitions to the high level, the plurality of latch circuits 221 output the level of the Gray code G input to the input node D.

[0076] By the above driving, the lower TDC 21 outputs a lower result corresponding to the lower bits based on the signals output from the plurality of gate circuits 214. Further, the upper TDC 22 outputs an upper result corresponding to the upper bits based on the signals output from the plurality of latch circuits 221.

[0077] In FIG. 11, at time t30, the multi-phase clock signal Φ1 is at the high level, the multi-phase clock signals Φ3 to Φ7 are at the low level, the multi-phase clock signal Φ0 transitions from the high level to the low level, and the multi-phase clock signal Φ2 transitions from the low level to the high level. Therefore, in response to the STOP signal transitioning from the low level to the high level, the latch circuits 211-1 and 211-2 output high-level signals, and the latch circuits 211-0 and 211-3 to 211-7 output low-level signals. Then, based on the signals output from the plurality of latch circuits 211, the gate circuit 214-2 outputs a high-level signal, and the gate circuits 214-0, 214-1, 214-3 to 214-7 output low-level signals. The encoder 213 determines, for example, "2" as the lower bit based on the high-level signal output from the gate circuit 214-2. Although the value of the lower bit is represented in decimal for convenience in this specification, in reality, a signal represented in binary is held.

[0078] Also, at time t30, since the input polyphase clock signal Φ6 has not yet transitioned from the low level to the high level, the first flip-flop circuit 231 outputs a low-level signal as the A signal. Also, at time t30, since the input polyphase clock signal Φ2 has transitioned from the low level to the high level, the second flip-flop circuit 232 outputs a high-level signal as the B signal. Also, since a low-level signal is input as the control signal from the latch circuit 211-0 to the multiplexer 234, the multiplexer 234 outputs the B signal, that is, the high-level signal, as the C signal. Also, since a high-level signal is input as the C signal to the third flip-flop circuit 233 and the input polyphase clock signal Φ6 has not yet transitioned from the low level to the high level, the third flip-flop circuit 233 outputs a low-level signal as the timing signal.

[0079] During the period from time t30 to time t31, the polyphase clock signal Φ2 transitions from the high level to the low level, and at time t31, the polyphase clock signal Φ6 transitions from the low level to the high level. Since the input polyphase clock signal Φ6 has transitioned from the low level to the high level, the first flip-flop circuit 231 outputs a high-level signal as the A signal. Also, the second flip-flop circuit 232 continues to output a high-level signal as the B signal from time t30. Also, since a low-level signal continues to be input as the control signal to the multiplexer 234 from time t30, the multiplexer 234 outputs the B signal, that is, the high-level signal, as the C signal. Also, since a high-level signal is input as the C signal to the third flip-flop circuit 233, in response to the input polyphase clock signal Φ6 transitioning from the low level to the high level, the third flip-flop circuit 233 outputs a high-level signal as the timing signal. Further, based on the high-level signal output as the timing signal and the Gray code G, for example, "7" is determined as the upper bit. In this specification, for convenience, the signal of the upper bit is also represented in decimal in the same way as the lower bit, but in reality, it is held as a binary signal.

[0080] Note that at time t30, the STOP signal transitions from low level to high level, and while the polyphase clock signal Φ2 transitions from low level to high level, the second flip-flop circuit 232 may output a low-level signal as the B signal. This is because when the timing of the two input signals transitioning from low level to high level is close, the second flip-flop circuit 232 does not function properly as a flip-flop circuit due to performance limitations. Also, at time t30, after the polyphase clock signal Φ2 transitions from low level to high level, the STOP signal may transition from low level to high level, and the second flip-flop circuit 232 may output a low-level signal as the B signal. This is due to the operation delay of the circuit that generates the STOP signal or the circuit that transmits the STOP signal.

[0081] In the above case, during the period from time t30 to time t32, the B signal is at a low level, and since a low-level signal is input to the third flip-flop circuit 233 as the C signal, a low-level signal is output as the timing signal. At time t32, the multiphase clock signal Φ2 transitions from a low level to a high level. The first flip-flop circuit 231 continues to output a high-level signal as the A signal from time t31. Also, since the input multiphase clock signal Φ2 transitions from a low level to a high level, the second flip-flop circuit 232 outputs a high-level signal as the B signal. Further, since a low-level signal is continuously input as the control signal to the multiplexer 234 from time t30, the B signal, that is, the high-level signal, is output as the C signal. Also, although a high-level signal is input to the third flip-flop circuit 233 as the C signal, since the input multiphase clock signal Φ6 has not yet transitioned from a low level to a high level, a low-level signal is output as the timing signal. At time t33, the multiphase clock signal Φ6 transitions from a low level to a high level. The first flip-flop circuit 231 continues to output a high-level signal as the A signal from time t31. Also, the second flip-flop circuit 232 continues to output a high-level signal as the B signal from time t32. Further, since a low-level signal is continuously input as the control signal to the multiplexer 234 from time t30, the B signal, that is, the high-level signal, is output as the C signal. Also, since a high-level signal is input to the third flip-flop circuit 233 as the C signal, in response to the input multiphase clock signal Φ6 transitioning from a low level to a high level, a high-level signal is output as the timing signal. Furthermore, based on the high-level signal output as the timing signal and the Gray code G, for example, "8" is determined as the upper bit. In this specification, for convenience, the signal of the upper bit is also represented in decimal in the same way as the lower bit, but in reality, it is held as a binary signal.

[0082] Therefore, for example, when the signal quality of the multi-phase clock signal Φ deteriorates due to, for example, deterioration of the duty ratio of the multi-phase clock signal Φ, the value determined as the upper bit may be different. In that case, a code error occurs at the connection of the upper TDC data and the lower TDC data, and the accuracy of the time digital conversion decreases.

[0083] FIG. 12 is an example of a diagram for explaining the signal processing of the TDC 20 according to the first embodiment and the reference example. FIG. 12(a) shows a case where no code error occurs at the connection of the upper TDC data and the lower TDC data as in the first embodiment. FIG. 12(b) shows a case where a code error occurs at the connection of the upper TDC data and the lower TDC data as in the reference example. Note that the upper TDC data and the lower TDC data are connected by converting the Gray code corresponding to the upper TDC data into a binary code. This process may be executed by the digital processing circuit 90 or may be executed outside the distance image sensor 100.

[0084] In the first embodiment described with reference to FIGS. 7 to 9, “8” is alternatively generated as the upper bit for the STOP signal that transitions from the low level to the high level at a predetermined timing. Therefore, as shown in FIG. 12(a), no inconsistency occurs when the upper TDC data and the lower TDC data are connected. On the other hand, in the reference example described with reference to FIG. 11, different upper bits may be generated for the STOP signal that transitions from the low level to the high level at a predetermined timing. Here, consider a case where, for the predetermined STOP signal shown in FIG. 11, it is set so that “8” is correctly generated as the upper bit in consideration of the operation delay of the circuit and the performance limit of the second flip-flop circuit 232. As shown in FIG. 12(b), for the predetermined STOP signal shown in FIG. 11, although “8” should originally be generated as the upper bit, “7” may be generated as the upper bit. In this case, when the upper TDC data and the lower TDC data are connected, although “64, 65, 66” should originally be generated, “56, 57, 58” are generated. Therefore, an inconsistency occurs when the upper TDC data and the lower TDC data are connected.

[0085] In the reference example, since the lower TDC21 generates a timing signal by using both the rising and falling timings of the multiphase clock signal Φ, the accuracy of time digital conversion decreases as described above. On the other hand, in the first embodiment, since the lower TDC21 generates a timing signal by using only one of the rising or falling timings of the multiphase clock signal Φ, high-precision time digital conversion is possible.

[0086] <Second Embodiment> A time digital conversion device according to a second embodiment of the present invention will be described with reference to FIGS. 13 and 14. Note that the same reference numerals are assigned to the same components as those in the first embodiment, and the description of these components may be omitted or simplified.

[0087] This embodiment is different from the first embodiment in that the synchronization circuit 23 includes a timing adjustment circuit 236. FIG. 13 is an example of a block diagram of the TDC20 according to this embodiment. In FIG. 13, the synchronization circuit 23 further includes a timing adjustment circuit 236. The timing adjustment circuit 236 is a circuit for correcting the signal processing delay due to the operation delay of at least one of the lower TDC21 and the synchronization circuit 23 and outputting a timing signal.

[0088] FIG. 14 is an example of a circuit diagram of the TDC20 according to this embodiment.

[0089] The timing adjustment circuit 236 includes a fourth flip-flop circuit 237 and a fifth flip-flop circuit 238. The fourth flip-flop circuit 237 and the fifth flip-flop circuit 238 are of the D type. Note that the fourth flip-flop circuit 237 and the fifth flip-flop circuit 238 may be D-type latch circuits. A START signal or a STOP signal is input to the input node D (the first input node) of the fourth flip-flop circuit 237 and the fifth flip-flop circuit 238. Also, a multiphase clock signal Φ is input to the clock nodes (the second input nodes) of the fourth flip-flop circuit 237 and the fifth flip-flop circuit 238. In FIG. 14, as the multiphase clock signal Φ, for example, the multiphase clock signal Φ6 among the multiphase clock signals Φ1 to Φ7 having different phases is input to the fourth flip-flop circuit 237, and the multiphase clock signal Φ2 is input to the fifth flip-flop circuit 238. Note that the phase difference between the phase of the multiphase clock signal Φ2 and the phase of the multiphase clock signal Φ6 is set to a half cycle. The output node of the fourth flip-flop circuit 237 is connected to the input node D of the first flip-flop circuit 231, and the output node of the fifth flip-flop circuit 238 is connected to the input node D of the second flip-flop circuit 232.

[0090] Therefore, in this embodiment, even when the timing at which the STOP signal transitions from the low level to the high level is close to the timing at which the multiphase clock signal Φ transitions from the low level to the high level or when an operation delay of the circuit occurs, high-precision time-to-digital conversion can be realized.

[0091] Furthermore, in this embodiment, even when an operation delay occurs in the lower TDC 21, the synchronization circuit 23, etc., high-precision time-to-digital conversion is possible.

[0092] <Third Embodiment> The third embodiment is applicable to both the first and second embodiments. FIG. 15 is a schematic diagram for explaining a device 9191 including a semiconductor device 930 according to this embodiment. The time digital conversion device of each of the above embodiments can be used in the semiconductor device 930. The device 9191 including the semiconductor device 930 will be described in detail. The semiconductor device 930 can include a semiconductor device 910. In addition to the semiconductor device 910, the semiconductor device 930 can include a package 920 that houses the semiconductor device 910. The package 920 can include a substrate to which the semiconductor device 910 is fixed and a lid such as glass facing the semiconductor device 910. The package 920 can further include a bonding member such as a bonding wire or a bump that connects a terminal provided on the substrate and a terminal provided on the semiconductor device 910.

[0093] The device 9191 can include at least any one of an optical device 940, a control device 950, a processing device 960, a display device 970, a storage device 980, and a mechanical device 990. The optical device 940 corresponds to the semiconductor device 930. The optical device 940 is, for example, a lens, a shutter, or a mirror, and includes an optical system that guides light to the semiconductor device 930. The control device 950 controls the semiconductor device 930. The control device 950 is a semiconductor device such as an ASIC.

[0094] The processing device 960 processes a signal output from the semiconductor device 930. The processing device 960 is a semiconductor device such as a CPU or an ASIC for constituting an AFE (analog front end) or a DFE (digital front end). The display device 970 is an EL display device or a liquid crystal display device that displays information (image) obtained by the semiconductor device 930. The storage device 980 is a magnetic device or a semiconductor device that stores information (image) obtained by the semiconductor device 930. The storage device 980 is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive.

[0095] The mechanical device 990 has movable parts or propulsion parts such as motors and engines. In the device 9191, the signal output from the semiconductor device 930 is displayed on the display device 970 or transmitted to the outside by a communication device (not shown) provided in the device 9191. For this purpose, it is preferable that the device 9191 further includes a storage device 980 and a processing device 960 separately from the storage circuit and the arithmetic circuit included in the semiconductor device 930. The mechanical device 990 may be controlled based on the signal output from the semiconductor device 930.

[0096] In addition, the device 9191 is suitable for electronic devices such as information terminals having a photographing function (for example, smartphones and wearable terminals) and cameras (for example, interchangeable-lens cameras, compact cameras, video cameras, surveillance cameras). The mechanical device 990 in the camera can drive the components of the optical device 940 for zooming, focusing, and shutter operations. Alternatively, the mechanical device 990 in the camera can move the semiconductor device 930 for anti-vibration operation.

[0097] In addition, the device 9191 can be a transportation device such as a vehicle, a ship, or an aircraft (drone, airplane, etc.). The mechanical device 990 in the transportation device can be used as a moving device. The device 9191 as a transportation device is suitable for those that transport the semiconductor device 930 or those that assist and / or automate driving (operation) by means of a photographing function. The processing device 960 for assisting and / or automating driving (operation) can perform processing for operating the mechanical device 990 as a moving device based on the information obtained by the semiconductor device 930. Alternatively, the device 9191 may be a medical device such as an endoscope, a measuring device such as a distance measuring sensor, an analysis device such as an electron microscope, an office device such as a copier, or an industrial device such as a robot.

[0098] According to the above-described embodiment, it is possible to obtain good pixel characteristics. Therefore, the value of the semiconductor device can be increased. The increase in value here includes at least any one of the addition of functions, the improvement of performance, the improvement of characteristics, the improvement of reliability, the improvement of manufacturing yield, the reduction of environmental load, the cost reduction, the miniaturization, and the weight reduction.

[0099] Therefore, if the semiconductor device 930 according to this embodiment is used in the device 9191, the value of the device can also be improved. For example, when the semiconductor device 930 is mounted on a transportation device to perform external shooting or external environment measurement of the transportation device, excellent performance can be obtained. Therefore, in manufacturing and selling the transportation device, deciding to mount the semiconductor device according to this embodiment on the transportation device is advantageous for improving the performance of the transportation device itself. In particular, the semiconductor device 930 is suitable for a transportation device that performs driving support and / or autonomous driving of the transportation device using the information obtained by the semiconductor device.

[0100] Also, the time digital conversion system and the moving body of this embodiment will be described with reference to FIGS. 15(b) and (c).

[0101] FIG. 15(b) shows an example of a time digital conversion system for an in-vehicle camera. The time digital conversion system 8 includes a time digital conversion device 80. The time digital conversion device 80 is the time digital conversion device described in any of the above embodiments. The time digital conversion system 8 has an image processing unit 801 that performs image processing on a plurality of image data acquired by the time digital conversion device 80. Further, the time digital conversion system 8 has a parallax acquisition unit 802 that calculates parallax (phase difference of a parallax image) from a plurality of image data acquired by the time digital conversion system 8. Here, the time digital conversion system 8 may include an optical system (not shown) that guides light to the time digital conversion device 80, such as a lens, a shutter, or a mirror. Further, a plurality of photoelectric conversion units that are substantially conjugate to the pupil of the optical system may be arranged in the pixels of the time digital conversion device 80. For example, a plurality of photoelectric conversion units that are substantially conjugate to the pupil are arranged corresponding to one microlens. The plurality of photoelectric conversion units receive light beams that have passed through different positions of the pupil of the optical system, so that the time digital conversion device 80 outputs image data corresponding to the light beams that have passed through different positions. Then, the parallax acquisition unit 802 may calculate the parallax using the output image data. Further, the time digital conversion system 8 has a distance acquisition unit 803 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 804 that determines whether there is a possibility of collision based on the calculated distance. Here, the parallax acquisition unit 802 and the distance acquisition unit 803 are examples of distance information acquisition means for acquiring distance information to an object. That is, the distance information is information related to parallax, defocus amount, distance to an object, etc. The collision determination unit 804 may determine the possibility of collision using any of these distance information. Note that the distance information may be acquired by ToF (Time of Flight). The distance information acquisition means may be realized by dedicatedly designed hardware, or may be realized by a software module. Further, it may be realized by an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), etc., or may be realized by a combination of these.

[0102] The time digital conversion system 8 is connected to a vehicle information acquisition device 810 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. Further, the time digital conversion system 8 is connected to a control ECU 820, which is a control device that outputs a control signal for generating a braking force for the vehicle based on the determination result of the collision determination unit 804. Further, the time digital conversion system 8 is also connected to an alarm device 830 that issues an alarm to the driver based on the determination result of the collision determination unit 804. For example, when the collision determination unit 804 determines that there is a high possibility of collision, the control ECU 820 performs vehicle control to avoid the collision and reduce the damage, such as applying the brakes, returning the accelerator, and suppressing the engine output. The alarm device 830 warns the user by sounding an alarm such as a sound, displaying alarm information on a screen of a car navigation system, or vibrating the seat belt or the steering wheel.

[0103] In the present embodiment, the time digital conversion system 8 images the surroundings of the vehicle, for example, the front or the rear. FIG. 15(c) shows the time digital conversion system 8 when imaging the front of the vehicle (imaging range 850). The vehicle information acquisition device 810 sends an instruction to the time digital conversion system 8 or the time digital conversion device 80. With such a configuration, the ranging accuracy can be further improved.

[0104] In the above description, an example of controlling to avoid collision with other vehicles has been described. However, the present invention is also applicable to control for automatically driving while following other vehicles and control for automatically driving so as not to deviate from the lane. Further, the time digital conversion system 8 can be applied not only to vehicles such as automobiles but also to moving bodies (mobile devices) such as ships, airplanes, or industrial robots. This moving body mainly includes a driving force generation unit that generates a driving force used for moving the moving body, and one or both of rotating bodies mainly used for moving the moving body. The driving force generation unit can be an engine, a motor, or the like. The rotating body can be a tire, a wheel, a screw of a ship, a propeller of an aircraft, or the like. In addition, the present invention can be applied not only to moving bodies but also to devices that widely utilize object recognition, such as an advanced road traffic system (ITS).

[0105] In this specification, expressions such as "A or B", "at least one of A and B", "at least one of A or / and B", and "one or more of A or / and B" include all possible combinations of the listed items unless otherwise explicitly defined. That is, the above expressions are understood to disclose all cases including the case of including at least one A, the case of including at least one B, and the case of including both at least one A and at least one B. This is similarly applicable to combinations of three or more elements.

[0106] As described above, the embodiments described can be appropriately modified without departing from the technical idea. The disclosure of this specification includes not only what is described in this specification but also all matters that can be grasped from this specification and the drawings attached to this specification. Also, the disclosure of this specification includes the complementary set of the concepts described in this specification. That is, for example, if this specification describes that "A is larger than B", even if the description that "A is not larger than B" is omitted, it can be said that this specification discloses that "A is not larger than B". This is because when the description that "A is larger than B" is given, it is premised that the case where "A is not larger than B" is considered.

[0107] Note that the disclosure of this embodiment includes the following configurations.

[0108] (Configuration 1) A time-to-digital conversion device that outputs time-digital data having a plurality of bits according to the time from a first timing to a second timing, including: a first circuit that generates lower bits among the plurality of bits; a second circuit that generates upper bits among the plurality of bits; and a third circuit that generates a second signal using a first signal output from the first circuit and outputs the second signal to the second circuit to synchronize the first circuit and the second circuit, wherein the first signal is generated using signals of a plurality of bits among the lower bits. The time-to-digital conversion device is characterized by this.

[0109] (Configuration 2) The time-to-digital conversion device according to Configuration 1, wherein the first circuit, the second circuit, and the third circuit each include a plurality of flip-flop circuits, or a plurality of latch circuits, or a flip-flop circuit and a latch circuit.

[0110] (Configuration 3) Each of the plurality of flip-flop circuits included in the first circuit, or each of the plurality of latch circuits, or each of the flip-flop circuit and the latch circuit has a first input node and a second input node, and a signal corresponding to the second timing is input to the first input node, and clock signals having different phases are input to the second input node. The time-to-digital conversion device according to Configuration 1 or 2 is characterized by this.

[0111] (Configuration 4) The time-to-digital conversion device according to any one of Configurations 1 to 3, wherein the first circuit includes a differentiating circuit that generates the first signal by performing differentiating processing on signals output from each of the plurality of flip-flop circuits included in the first circuit, or each of the plurality of latch circuits, or each of the flip-flop circuit and the latch circuit.

[0112] (Configuration 5) The differential circuit has a plurality of input nodes and a plurality of output nodes. The plurality of input nodes are connected to the output nodes of each of the plurality of flip-flop circuits, or each of the plurality of latch circuits, or each of the flip-flop circuits and the latch circuits. The plurality of output nodes are connected to the third circuit. The time digital conversion device according to any one of Configurations 1 to 4, characterized in that.

[0113] (Configuration 6) Each of the plurality of flip-flop circuits included in the second circuit, or each of the plurality of latch circuits, or each of the flip-flop circuits and the latch circuits, has a first input node and a second input node. The second signal is input to the first input node, and a Gray code of different values is input to the second input node. The time digital conversion device according to any one of Configurations 1 to 5, characterized in that.

[0114] (Configuration 7) Each of the plurality of flip-flop circuits included in the third circuit, or each of the plurality of latch circuits, or each of the flip-flop circuits and the latch circuits, has a first input node and a second input node. A signal corresponding to the second timing is input to the first input node, and clock signals with different phases are input to the second input node. The time digital conversion device according to any one of Configurations 1 to 6, characterized in that.

[0115] (Configuration 8) The third circuit includes a selection circuit that receives a plurality of signals and a selection signal output from the plurality of flip-flop circuits, or the plurality of latch circuits, or the flip-flop circuits and the latch circuits, selects one signal from the plurality of signals using the selection signal, and outputs the one signal. The time digital conversion device according to any one of Configurations 1 to 7, characterized in that.

[0116] (Configuration 9) The third circuit includes a generation circuit that generates the selection signal. The time digital conversion device according to any one of Configurations 1 to 8, characterized in that.

[0117] (Configuration 10) The generation circuit has an output node and a plurality of input nodes, the plurality of input nodes are connected to the first circuit, and the output node is connected to the selection circuit. The time digital conversion device according to any one of Configurations 1 to 9.

[0118] (Configuration 11) The first circuit includes a differentiation circuit that generates the first signal by performing a differentiation process on a signal output from each of the plurality of flip-flop circuits included in the first circuit, or each of the plurality of latch circuits, or each of the flip-flop circuits and the latch circuits. The time digital conversion device according to any one of Configurations 1 to 10, characterized in that a plurality of output nodes of the differentiation circuit are connected to the plurality of input nodes.

[0119] (Configuration 12) The third circuit includes a timing adjustment circuit that corrects a delay in signal processing that occurs in at least one of the first circuit and the third circuit. The time digital conversion device according to any one of Configurations 1 to 11.

[0120] (Configuration 13) A distance measuring device comprising a light receiving unit that emits pulsed light toward an object and receives the pulsed light reflected by the object, and the time digital conversion device according to any one of Configurations 1 to 12, wherein the time digital conversion device uses the emission timing of the pulsed light as the first timing, the timing at which the pulsed light is received as the second timing, and based on the time digital data corresponding to the time from the first timing to the second timing, obtains distance information to the object.

[0121] (Configuration 14) The distance measuring device according to Configuration 13, further comprising a light emitting unit that emits the pulsed light.

[0122] (Configuration 15) The distance measuring device according to Configuration 14, wherein a plurality of the light receiving units are arranged over a plurality of rows and a plurality of columns, and the first circuit, the second circuit, and the third circuit are provided for each row among the plurality of rows.

[0123] (Configuration 16) The distance measuring device according to Configuration 14, wherein a plurality of the light receiving units are arranged over a plurality of rows and a plurality of columns, and the first circuit, the second circuit, and the third circuit are provided for each light receiving unit.

[0124] (Configuration 17) The distance measuring device according to Configuration 14, wherein a plurality of the light receiving units are arranged over a plurality of rows and a plurality of columns, and the first circuit, the second circuit, and the third circuit are provided for each sub-array including a plurality of the light receiving units.

[0125] (Configuration 18) A moving body, comprising the distance measuring device according to Configuration 14 and control means for controlling the moving body based on the distance information acquired by the distance measuring device.

[0126] (Configuration 19) A device including the time digital conversion device according to any one of Configurations 1 to 18, further comprising at least one of: an optical device for guiding light to the time digital conversion device; a control device for controlling the time digital conversion device; a processing device for processing a signal output from the time digital conversion device; a display device for displaying information obtained by the time digital conversion device; a storage device for storing information obtained by the time digital conversion device; and a mechanical device that operates based on information obtained by the time digital conversion device.

Explanation of Reference Numerals

[0127] 21 First circuit 22 Second circuit 23 Third circuit

Claims

1. A time-to-digital conversion device that outputs time-digital data having a plurality of bits according to the time from a first timing to a second timing, comprising: a first circuit that generates lower bits among the plurality of bits; a second circuit that generates upper bits among the plurality of bits; a third circuit that generates a second signal using a first signal output from the first circuit and outputs the second signal to the second circuit to synchronize the first circuit and the second circuit; wherein the first signal is generated using signals of a plurality of bits among the lower bits A time-to-digital conversion device characterized by the above.

2. The time-to-digital conversion device according to claim 1, wherein the first circuit, the second circuit, and the third circuit each include a plurality of flip-flop circuits, or a plurality of latch circuits, or a flip-flop circuit and a latch circuit.

3. Each of the plurality of flip-flop circuits included in the first circuit, or each of the plurality of latch circuits, or each of the flip-flop circuit and the latch circuit has a first input node and a second input node, a signal corresponding to the second timing is input to the first input node, and clock signals having different phases are input to the second input node. The time-to-digital conversion device according to claim 2, characterized by the above.

4. The first circuit includes a differentiating circuit that generates the first signal by performing a differentiating process on a signal output from each of the plurality of flip-flop circuits included in the first circuit, or each of the plurality of latch circuits, or each of the flip-flop circuit and the latch circuit. The time-to-digital conversion device according to claim 2, characterized by the above.

5. The differentiating circuit has a plurality of input nodes and a plurality of output nodes, the plurality of input nodes are connected to output nodes of each of the plurality of flip-flop circuits, or each of the plurality of latch circuits, or each of the flip-flop circuit and the latch circuit, and the plurality of output nodes are connected to the third circuit. The time-to-digital conversion device according to claim 4, characterized by the above.

6. Each of the plurality of flip-flop circuits included in the second circuit, or each of the plurality of latch circuits, or each of the flip-flop circuits and the latch circuits, has a first input node and a second input node, and the second signal is input to the first input node, and a Gray code of different values is input to the second input node. The time digital conversion device according to claim 2, characterized in that.

7. Each of the plurality of flip-flop circuits included in the third circuit, or each of the plurality of latch circuits, or each of the flip-flop circuits and the latch circuits, has a first input node and a second input node, and a signal corresponding to the second timing is input to the first input node, and clock signals with different phases are input to the second input node. The time digital conversion device according to claim 2, characterized in that.

8. The third circuit includes a selection circuit to which a plurality of signals and a selection signal output from the plurality of flip-flop circuits, or the plurality of latch circuits, or the flip-flop circuits and the latch circuits are input, and one of the plurality of signals is selected using the selection signal and the one signal is output. The time digital conversion device according to claim 2, characterized in that.

9. The third circuit includes a generation circuit that generates the selection signal. The time digital conversion device according to claim 8, characterized in that.

10. The generation circuit has an output node and a plurality of input nodes, the plurality of input nodes are connected to the first circuit, and the output node is connected to the selection circuit. The time digital conversion device according to claim 9, characterized in that.

11. The first circuit includes a differential circuit that generates the first signal by performing a differential process on a signal output from each of the plurality of flip-flop circuits included in the first circuit, or each of the plurality of latch circuits, or each of the flip-flop circuits and the latch circuits, and a plurality of output nodes of the differential circuit are connected to the plurality of input nodes. The time digital conversion device according to claim 10, characterized in that.

12. The time digital conversion device according to claim 1, wherein the third circuit includes a timing adjustment circuit that corrects a delay in signal processing occurring in at least one of the first circuit and the third circuit.

13. A light receiving unit that emits pulsed light toward an object and receives the pulsed light reflected by the object, A time digital conversion device according to any one of claims 1 to 12, The time digital conversion device uses the emission timing of the pulsed light as the first timing, the timing when the pulsed light is received as the second timing, and based on the time digital data corresponding to the time from the first timing to the second timing, a distance measuring device that acquires distance information to the object.

14. The distance measuring device according to claim 13, further comprising a light emitting unit that emits the pulsed light.

15. A plurality of the light receiving units are arranged over a plurality of rows and a plurality of columns, The first circuit, the second circuit, and the third circuit are provided for each row among the plurality of rows. The distance measuring device according to claim 14.

16. A plurality of the light receiving units are arranged over a plurality of rows and a plurality of columns, The first circuit, the second circuit, and the third circuit are provided for each light receiving unit. The distance measuring device according to claim 14.

17. A plurality of the light receiving units are arranged over a plurality of rows and a plurality of columns, The first circuit, the second circuit, and the third circuit are provided for each sub-array including a plurality of the light receiving units. The distance measuring device according to claim 14.

18. A moving body, The distance measuring device according to claim 14, And control means for controlling the moving body based on the distance information acquired by the distance measuring device A moving body characterized by having.

19. A device including the time digital conversion device according to claim 1, An optical device that guides light to the time digital conversion device, A control device that controls the time digital conversion device, A processing device that processes a signal output from the time digital conversion device, A display device that displays information obtained by the time digital conversion device, A storage device that stores information obtained by the time digital conversion device, and, A device characterized by further comprising at least one of a mechanical device that operates based on information obtained by the time digital conversion device.

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