Three-phase power factor correction converter

Abstract

To suppress a component from being damaged.SOLUTION: A three-phase power factor correction converter includes: a first diode having an anode electrically connected to a first input terminal and a cathode electrically connected to a first output terminal; a second diode having an anode electrically connected to a second input terminal and a cathode electrically connected to the first output terminal; a third diode having an anode electrically connected to a third input terminal and a cathode electrically connected to the first output terminal; a fourth diode having a cathode electrically connected to the first input terminal and an anode electrically connected to a second output terminal; a fifth diode having a cathode electrically connected to the second input terminal and an anode electrically connected to the second output terminal; and a sixth diode having a cathode electrically connected to the third input terminal and an anode electrically connected to the second output terminal.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present disclosure relates to a three-phase power factor improvement converter.

Background Art

[0002] Patent Document 1 and Non-Patent Document 1 describe a Vienna rectifier. The Vienna rectifier can be used as a three-phase power factor improvement converter.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Non-Patent Documents

[0004]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In the three-phase power factor improvement converter described in Patent Document 1 and Non-Patent Document 1, when a surge voltage caused by lightning or the like is input, the components may be damaged by receiving a high voltage.

[0006] An object of the present disclosure is to suppress damage to components.

Means for Solving the Problems

[0007] The three-phase power factor improvement converter according to one aspect of the present disclosure is A three-phase power factor improvement converter in which a three-phase AC voltage is input to a first input terminal, a second input terminal, and a third input terminal, and a DC voltage is output from a first output terminal and a second output terminal, a first diode having an anode electrically connected to the first input terminal and a cathode electrically connected to the first output terminal; a second diode having an anode electrically connected to the second input terminal and a cathode electrically connected to the first output terminal; a third diode having an anode electrically connected to the third input terminal and a cathode electrically connected to the first output terminal; a fourth diode having a cathode electrically connected to the first input terminal and an anode electrically connected to the second output terminal; a fifth diode having a cathode electrically connected to the second input terminal and an anode electrically connected to the second output terminal; a sixth diode having a cathode electrically connected to the third input terminal and an anode electrically connected to the second output terminal; comprising characterized in that.

[0008] In the three-phase power factor improvement converter, at least two of a first capacitor having one end electrically connected to the first input terminal and the other end electrically connected to a first node, a second capacitor having one end electrically connected to the second input terminal and the other end electrically connected to the first node, and a third capacitor having one end electrically connected to the third input terminal and the other end electrically connected to the first node; a fourth capacitor having one end electrically connected to the first output terminal and the other end electrically connected to a second node; a fifth capacitor having one end electrically connected to the second node and the other end electrically connected to the second output terminal; a wiring having one end electrically connected to the first node and the other end electrically connected to the second node; comprising characterized in that.

[0009] In the three-phase power factor improvement converter, at least two of a first capacitor having one end electrically connected to the first input terminal and the other end electrically connected to the first node, a second capacitor having one end electrically connected to the second input terminal and the other end electrically connected to the first node, and a third capacitor having one end electrically connected to the third input terminal and the other end electrically connected to the first node, a fourth capacitor having one end electrically connected to the first output terminal and the other end electrically connected to the second node, a fifth capacitor having one end electrically connected to the second node and the other end electrically connected to the second output terminal, an eighth capacitor having one end electrically connected to the first node and the other end electrically connected to the second node, including characterized in that.

[0010] In the three-phase power factor improvement converter, the DC voltage is higher than the product of the effective value of the maximum line voltage of the three-phase AC voltage and the square root of 2 (peak value of the maximum line voltage), characterized in that.

[0011] In the three-phase power factor improvement converter, the DC voltage is higher than the sum of the product of the effective value of the maximum line voltage of the three-phase AC voltage and the square root of 2 (peak value of the maximum line voltage) and the absolute value of the ripple voltage of the first capacitor, the second capacitor, and the third capacitor, characterized in that.

[0012] In the three-phase power factor improvement converter, a first inductor having one end electrically connected to the first input terminal, a second inductor having one end electrically connected to the second input terminal, a third inductor having one end electrically connected to the third input terminal, A seventh diode having an anode electrically connected to the other end of the first inductor and a cathode electrically connected to the first output terminal; An eighth diode having an anode electrically connected to the other end of the second inductor and a cathode electrically connected to the first output terminal; A ninth diode having an anode electrically connected to the other end of the third inductor and a cathode electrically connected to the first output terminal; A tenth diode having an anode electrically connected to the second output terminal and a cathode electrically connected to the other end of the first inductor; An eleventh diode having an anode electrically connected to the second output terminal and a cathode electrically connected to the other end of the second inductor; A twelfth diode having an anode electrically connected to the second output terminal and a cathode electrically connected to the other end of the third inductor; A first bidirectional switch having one end electrically connected to the other end of the first inductor; A second bidirectional switch having one end electrically connected to the other end of the second inductor and the other end electrically connected to the other end of the first bidirectional switch; A third bidirectional switch having one end electrically connected to the other end of the third inductor and the other end electrically connected to the other end of the first bidirectional switch; Including Characterized by

[0013] In the three-phase power factor improvement converter, The other ends of the first bidirectional switch, the second bidirectional switch, and the third bidirectional switch are electrically connected to the second node. Characterized by

[0014] In the three-phase power factor improvement converter, A sixth capacitor having one end electrically connected to the first output terminal and the other end electrically connected to the third node; A seventh capacitor having one end electrically connected to the third node and the other end electrically connected to the second output terminal; further includes The other ends of the first bidirectional switch, the second bidirectional switch, and the third bidirectional switch are electrically connected to the third node. which is characterized in that.

[0015] In the three-phase power factor improvement converter, a first inductor having one end electrically connected to the first input terminal; a second inductor having one end electrically connected to the second input terminal; a third inductor having one end electrically connected to the third input terminal; a first switching element having one end electrically connected to the other end of the first inductor and the other end electrically connected to the first output terminal; a second switching element having one end electrically connected to the second output terminal and the other end electrically connected to the other end of the first inductor; a third switching element having one end electrically connected to the other end of the second inductor and the other end electrically connected to the first output terminal; a fourth switching element having one end electrically connected to the second output terminal and the other end electrically connected to the other end of the second inductor; a fifth switching element having one end electrically connected to the other end of the third inductor and the other end electrically connected to the first output terminal; a sixth switching element having one end electrically connected to the second output terminal and the other end electrically connected to the other end of the third inductor; including which is characterized in that.

[0016] In the three-phase power factor improvement converter, further includes a ninth capacitor having one end electrically connected to the first output terminal and the other end electrically connected to the second output terminal. which is characterized in that.

Advantages of the Invention

[0017] According to the present disclosure, it is possible to suppress components from being damaged.

Brief Description of the Drawings

[0018]

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[0019] Hereinafter, embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. Note that the present disclosure is not limited by this embodiment, and in the following embodiments, the same parts are denoted by the same reference numerals to omit redundant explanations.

[0020] <Comparative Example> (Configuration) FIG. 1 is a diagram showing the configuration of a conventional three-phase power factor improvement converter of a comparative example. The three-phase power factor improvement converter 100 receives an input of a three-phase AC voltage and outputs a DC voltage. The three-phase power factor improvement converter 100 is a Vienna rectifier.

[0021] The three-phase power factor improvement converter 100 has terminals from terminal 11 to terminal 15.

[0022] Terminal 11 corresponds to an example of the "first input terminal" of the present disclosure. Terminal 12 corresponds to an example of the "second input terminal" of the present disclosure. Terminal 13 corresponds to an example of the "third input terminal" of the present disclosure. Terminal 14 corresponds to an example of the "first output terminal" of the present disclosure. Terminal 15 corresponds to an example of the "second output terminal" of the present disclosure.

[0023] The voltage V_R of the first phase among the three-phase AC voltages is input to terminal 11. The voltage V_S of the second phase among the three-phase AC voltages is input to terminal 12. The voltage V_T of the third phase among the three-phase AC voltages is input to terminal 13. The DC voltage Vout_P on the high potential side is output from terminal 14. The DC voltage Vout_N on the low potential side is output from terminal 15. The difference between the voltage Vout_P and the voltage Vout_N is the output voltage Vdc.

[0024] The three-phase power factor correction converter 100 includes capacitors C1 to C5, inductors L1 to L3, diodes D7 to D12, bidirectional switches 21 to 23, and a control unit 24.

[0025] It is assumed that the capacitance values of capacitors C1 to C3 are the same. It is assumed that the inductance values of inductors L1 to L3 are the same. It is assumed that the capacitance values of capacitors C4 and C5 are the same.

[0026] Capacitor C1 corresponds to an example of the "first capacitor" of the present disclosure. Capacitor C2 corresponds to an example of the "second capacitor" of the present disclosure. Capacitor C3 corresponds to an example of the "third capacitor" of the present disclosure. Capacitor C4 corresponds to an example of the "fourth capacitor" of the present disclosure. Capacitor C5 corresponds to an example of the "fifth capacitor" of the present disclosure.

[0027] Inductor L1 corresponds to an example of the "first inductor" of the present disclosure. Inductor L2 corresponds to an example of the "second inductor" of the present disclosure. Inductor L3 corresponds to an example of the "third inductor" of the present disclosure.

[0028] Diode D7 corresponds to an example of the "seventh diode" of the present disclosure. Diode D8 corresponds to an example of the "eighth diode" of the present disclosure. Diode D9 corresponds to an example of the "ninth diode" of the present disclosure. Diode D10 corresponds to an example of the "tenth diode" of the present disclosure. Diode D11 corresponds to an example of the "eleventh diode" of the present disclosure. Diode D12 corresponds to an example of the "twelfth diode" of the present disclosure.

[0029] Bidirectional switch 21 corresponds to an example of the "first bidirectional switch" of the present disclosure. Bidirectional switch 22 corresponds to an example of the "second bidirectional switch" of the present disclosure. Bidirectional switch 23 corresponds to an example of the "third bidirectional switch" of the present disclosure.

[0030] Bidirectional switch 21 includes switching element Q1 and switching element Q2. Bidirectional switch 22 includes switching element Q3 and switching element Q4. Bidirectional switch 23 includes switching element Q5 and switching element Q6. The switching element is exemplified by a FET (Field Effect Transistor), but the present disclosure is not limited thereto. Each of bidirectional switches 21 to 23 is configured with two switching elements, but this is an example and the present disclosure is not limited thereto.

[0031] One end of capacitor C1 is electrically connected to terminal 11. The other end of capacitor C1 is electrically connected to node N1. One end of capacitor C2 is electrically connected to terminal 12. The other end of capacitor C2 is electrically connected to node N1. One end of capacitor C3 is electrically connected to terminal 13. The other end of capacitor C3 is electrically connected to node N1. That is, capacitors C1 to C3 are Y (star) connected. Node N1 is defined as the neutral point on the input side.

[0032] Node N1 corresponds to an example of the "first node" of the present disclosure.

[0033] One end of inductor L1 is electrically connected to terminal 11. The other end of inductor L1 is electrically connected to node N11.

[0034] One end of inductor L2 is electrically connected to terminal 12. The other end of inductor L2 is electrically connected to node N12.

[0035] One end of inductor L3 is electrically connected to terminal 13. The other end of inductor L3 is electrically connected to node N13.

[0036] The anode of diode D7 is electrically connected to node N11. The cathode of diode D7 is electrically connected to terminal 14.

[0037] The anode of diode D8 is electrically connected to node N12. The cathode of diode D8 is electrically connected to terminal 14.

[0038] The anode of diode D9 is electrically connected to node N13. The cathode of diode D9 is electrically connected to terminal 14.

[0039] The cathode of diode D10 is electrically connected to node N11. The anode of diode D10 is electrically connected to terminal 15.

[0040] The cathode of diode D11 is electrically connected to node N12. The anode of diode D11 is electrically connected to terminal 15.

[0041] The cathode of diode D12 is electrically connected to node N13. The anode of diode D12 is electrically connected to terminal 15.

[0042] The drain of the switching element Q1 is electrically connected to the node N11. The source of the switching element Q1 is electrically connected to the source of the switching element Q2. The drain of the switching element Q2 is electrically connected to the node N2.

[0043] The node N2 corresponds to an example of the "second node" of the present disclosure.

[0044] The drain of the switching element Q3 is electrically connected to the node N12. The source of the switching element Q3 is electrically connected to the source of the switching element Q4. The drain of the switching element Q4 is electrically connected to the node N2.

[0045] The drain of the switching element Q5 is electrically connected to the node N13. The source of the switching element Q5 is electrically connected to the source of the switching element Q6. The drain of the switching element Q6 is electrically connected to the node N2.

[0046] One end of the capacitor C4 is electrically connected to the terminal 14. The other end of the capacitor C4 is electrically connected to the node N2.

[0047] One end of the capacitor C5 is electrically connected to the node N2. The other end of the capacitor C5 is electrically connected to the terminal 15.

[0048] The voltage of each of the capacitor C4 and the capacitor C5 is Vdc / 2. The node N2 is defined as the neutral point on the output side.

[0049] The capacitor C4 and the capacitor C5 are exemplified by electrolytic capacitors, but the present disclosure is not limited thereto.

[0050] The control unit 24 performs vector control to convert the input voltage and current information of the three-phase alternating current into direct current values (voltage value, current value), and switches from the bidirectional switch 21 to the bidirectional switch 23. As a result, the three-phase power factor improvement converter 100 can make the input current waveform sinusoidal and output a stable direct current voltage, and can perform output voltage variable control according to the optimal operating voltage characteristics of the converter connected to the subsequent stage.

[0051] In addition, after the first embodiment, the control unit 24 further performs envelope shift control. The envelope shift control will be described in the first embodiment.

[0052] (Problem) In the three-phase power factor improvement converter 100, when a surge voltage caused by lightning or the like is input, the components may be damaged by receiving a high voltage.

[0053] For example, when a surge voltage is input to the terminals 11, 12, and 13, the main semiconductors (diodes D7 to D12 and switching elements Q1 to Q6) may be damaged by receiving a high voltage.

[0054] <First Embodiment> (Configuration) FIG. 2 is a diagram showing the configuration of the three-phase power factor improvement converter according to the first embodiment.

[0055] The three-phase power factor improvement converter 1 further includes diodes D1 to D6 compared to the three-phase power factor improvement converter 100 (see FIG. 1).

[0056] Incidentally, if the diodes D1 to D6 are directly connected to the three-phase power factor correction converter 1, current may flow through the diodes D1 to D6 even when the output voltage of the three-phase power factor correction converter 1 is higher than the peak value of the input line voltage. As a result, losses may occur in the diodes D1 to D6, and the conversion efficiency and power factor of the three-phase power factor correction converter 1 may decrease. To address this issue, as previously mentioned, in the embodiments starting from the first embodiment, the control unit 24 performs envelope shift control.

[0057] The diode D1 corresponds to an example of the "first diode" of the present disclosure. The diode D2 corresponds to an example of the "second diode" of the present disclosure. The diode D3 corresponds to an example of the "third diode" of the present disclosure. The diode D4 corresponds to an example of the "fourth diode" of the present disclosure. The diode D5 corresponds to an example of the "fifth diode" of the present disclosure. The diode D6 corresponds to an example of the "sixth diode" of the present disclosure.

[0058] The anode of the diode D1 is electrically connected to the terminal 11. The cathode of the diode D1 is electrically connected to the terminal 14.

[0059] The anode of the diode D2 is electrically connected to the terminal 12. The cathode of the diode D2 is electrically connected to the terminal 14.

[0060] The anode of the diode D3 is electrically connected to the terminal 13. The cathode of the diode D3 is electrically connected to the terminal 14.

[0061] The cathode of the diode D4 is electrically connected to the terminal 11. The anode of the diode D4 is electrically connected to the terminal 15.

[0062] The cathode of the diode D5 is electrically connected to the terminal 12. The anode of the diode D5 is electrically connected to the terminal 15.

[0063] The cathode of diode D6 is electrically connected to terminal 13. The anode of diode D6 is electrically connected to terminal 15.

[0064] As described above, in and after the first embodiment, the control unit 24 performs envelope shift control.

[0065] The control unit 24 performs envelope shift on the modulation ratio mu_ref of the U phase, the modulation ratio mv_ref of the V phase, and the modulation ratio mw_ref of the W phase calculated by rotating coordinate transformation (dq transformation) of the alternating current.

[0066] Specifically, the control unit 24 calculates the maximum modulation ratio mx_ref_max by the following formula (1). In formula (1), MAX is an operator that selects the maximum value of the arguments. The control unit 24 calculates the minimum modulation ratio mx_ref_min by the following formula (2). In formula (2), MIN is an operator that selects the minimum value of the arguments. The control unit 24 calculates the envelope shift amount mx_central, which is the average of the maximum modulation ratio mx_ref_max and the minimum modulation ratio mx_ref_min, by the following formula (3).

[0067]

Number

[0068] The control unit 24 subtracts the envelope shift amount mx_central from the modulation ratio mu_ref of the U phase before correction by the following formula (4) to calculate the modulation ratio m_u of the U phase after correction. The control unit 24 subtracts the envelope shift amount mx_central from the modulation ratio mv_ref of the V phase before correction by the following formula (5) to calculate the modulation ratio m_v of the V phase after correction. The control unit 24 subtracts the envelope shift amount mx_central from the modulation ratio mw_ref of the W phase before correction by the following formula (6) to calculate the modulation ratio m_w of the W phase after correction.

[0069]

Number

[0070] Figure 3 is an explanatory diagram of the envelope shift control of the three-phase power factor improvement converter according to the first embodiment. In Figure 3, line 401 indicates the modulation rate mu_ref of phase U before correction. Line 402 indicates the modulation rate mv_ref of phase V before correction. Line 403 indicates the modulation rate mw_ref of phase W before correction. Line 411 indicates the modulation rate m_u of phase U after correction. Line 412 indicates the modulation rate m_v of phase V after correction. Line 413 indicates the modulation rate m_w of phase W after correction.

[0071] As shown by line 411, line 412, and line 413, the modulation rate of each phase after correction has its peak suppressed compared to the modulation rate of each phase before correction. Thereby, the three-phase power factor improvement converter 1 can shorten the time during which current flows from diode D1 to diode D6. Therefore, the three-phase power factor improvement converter 1 can suppress the heat generation from diode D1 to diode D6, can suppress the losses generated in diode D1 to diode D6, can suppress a decrease in conversion efficiency, and can also suppress a decrease in power factor.

[0072] (Effect) For example, when a positive surge voltage is input between terminals 11 and 12, it passes through diodes D1 and D5 and is clamped to the output voltage Vdc of the three-phase power factor improvement converter 1, and an excessive voltage is not applied to the main semiconductors (from diode D7 to diode D12 and from switching element Q1 to switching element Q6). When a negative surge voltage is input between terminals 11 and 12, it passes through diodes D2 and D4 and is clamped to the output voltage Vdc of the three-phase power factor improvement converter 1, and an excessive voltage is not applied to the main semiconductors (from diode D7 to diode D12 and from switching element Q1 to switching element Q6).

[0073] Therefore, since an excessive voltage is not applied to the components (main semiconductors (from diode D7 to diode D12 and from switching element Q1 to switching element Q6)), the three-phase power factor improvement converter 1 can suppress the components from being damaged.

[0074] Also, for example, when a positive surge voltage is input between terminal 12 and terminal 13, it passes through diode D2 and diode D6 and is clamped to the output voltage Vdc of the three-phase power factor correction converter 1, so that an excessive voltage is not applied to the main semiconductors (from diode D7 to diode D12 and from switching element Q1 to switching element Q6). When a negative surge voltage is input between terminal 12 and terminal 13, it passes through diode D3 and diode D5 and is clamped to the output voltage Vdc of the three-phase power factor correction converter 1, so that an excessive voltage is not applied to the main semiconductors (from diode D7 to diode D12 and from switching element Q1 to switching element Q6).

[0075] Therefore, since an excessive voltage is not applied to the components (main semiconductors (from diode D7 to diode D12 and from switching element Q1 to switching element Q6)) of the three-phase power factor correction converter 1, damage to the components can be suppressed.

[0076] Also, for example, when a positive surge voltage is input between terminal 13 and terminal 11, it passes through diode D3 and diode D4 and is clamped to the output voltage Vdc of the three-phase power factor correction converter 1, so that an excessive voltage is not applied to the main semiconductors (from diode D7 to diode D12 and from switching element Q1 to switching element Q6). When a negative surge voltage is input between terminal 13 and terminal 11, it passes through diode D1 and diode D6 and is clamped to the output voltage Vdc of the three-phase power factor correction converter 1, so that an excessive voltage is not applied to the main semiconductors (from diode D7 to diode D12 and from switching element Q1 to switching element Q6).

[0077] Therefore, since an excessive voltage is not applied to the components (main semiconductors (from diode D7 to diode D12 and from switching element Q1 to switching element Q6)) of the three-phase power factor correction converter 1, damage to the components can be suppressed.

[0078] In this way, when a surge voltage is input, the three-phase power factor improvement converter 1 can suppress damage to the constituent components, namely the main semiconductors (from diode D7 to diode D12 and from switching element Q1 to switching element Q6).

[0079] <Second Embodiment> (Problems of the First Embodiment) As mentioned above, when diodes D1 to D6 are connected to the three-phase power factor improvement converter 1, even if the output voltage of the three-phase power factor improvement converter 1 is higher than the peak value of the input line voltage, current may flow through diodes D1 to D6. As a result, losses occur in diodes D1 to D6, and the conversion efficiency and power factor of the three-phase power factor improvement converter 1 may decrease. This will be explained in detail.

[0080] (Circuit Simulation Results of the First Embodiment) Figures 4 and 5 are diagrams showing the circuit simulation results of the three-phase power factor improvement converter of the first embodiment.

[0081] This circuit simulation is a steady-state circuit simulation with no surge voltage input. The three-phase input voltage (input maximum line voltage effective value) is set to AC484V, the DC output voltage (output voltage Vdc) is set to 750V, the voltage Vdc / 2 is set to 375V, and the output current is set to 12.8A.

[0082] Referring to Figure 4, line 201 shows the voltage V_C1 of capacitor C1 (see Figure 2, the phase voltage of the first phase (R phase)). Line 202 shows the voltage V_C2 of capacitor C2 (see Figure 2, the phase voltage of the second phase (S phase)). Line 203 shows the voltage V_C3 of capacitor C3 (see Figure 2, the phase voltage of the third phase (T phase)). Line 204 shows the voltage Vdc / 2 (= 375V).

[0083] Lines 211a, 211b, and 211c indicate the envelope of the current I_D1 (see Figure 2) of diode D1. Lines 212a, 212b, and 212c indicate the envelope of the current I_D2 (see Figure 2) of diode D2. Lines 213a, 213b, and 213c indicate the envelope of the current I_D3 (see Figure 2) of diode D3.

[0084] Lines 214a, 214b, and 214c indicate the envelope of the current I_D4 (see Figure 2) of diode D4. Lines 215a, 215b, and 215c indicate the envelope of the current I_D5 (see Figure 2) of diode D5. Lines 216a, 216b, and 216c indicate the envelope of the current I_D6 (see Figure 2) of diode D6.

[0085] At the timing when the voltage V_C1 (line 201) is at its positive peak, current I_D1 (line 211c) flows through diode D1. At the timing before the positive peak of voltage V_C1 (line 201), current I_D1 (line 211a) flows through diode D1. At the timing after the positive peak of voltage V_C1 (line 201), current I_D1 (line 211b) flows through diode D1.

[0086] At the timing when the voltage V_C2 (line 202) is at its positive peak, current I_D2 (line 212c) flows through diode D2. At the timing before the positive peak of voltage V_C2 (line 202), current I_D2 (line 212a) flows through diode D2. At the timing after the positive peak of voltage V_C2 (line 202), current I_D2 (line 212b) flows through diode D2.

[0087] At the timing when the voltage V_C3 (line 203) is at its positive peak, current I_D3 (line 213c) flows through diode D3. At the timing before the positive peak of voltage V_C3 (line 203), current I_D3 (line 213a) flows through diode D3. At the timing after the positive peak of voltage V_C3 (line 203), current I_D3 (line 213b) flows through diode D3.

[0088] At the timing when the voltage V_C1 (line 201) reaches its negative peak, a current I_D4 (line 214c) flows through the diode D4. At the timing before the voltage V_C1 (line 201) reaches its negative peak, a current I_D4 (line 214a) flows through the diode D4. At the timing after the voltage V_C1 (line 201) reaches its negative peak, a current I_D4 (line 214b) flows through the diode D4.

[0089] At the timing when the voltage V_C2 (line 202) reaches its negative peak, a current I_D5 (line 215c) flows through the diode D5. At the timing before the voltage V_C2 (line 202) reaches its negative peak, a current I_D5 (line 215a) flows through the diode D5. At the timing after the voltage V_C2 (line 202) reaches its negative peak, a current I_D5 (line 215b) flows through the diode D5.

[0090] At the timing when the voltage V_C3 (line 203) reaches its negative peak, a current I_D6 (line 216c) flows through the diode D6. At the timing before the voltage V_C3 (line 203) reaches its negative peak, a current I_D6 (line 216a) flows through the diode D6. At the timing after the voltage V_C3 (line 203) reaches its negative peak, a current I_D6 (line 216b) flows through the diode D6.

[0091] FIG. 5 is a view focusing on the first phase (R phase). Line 221 indicates the high - potential - side envelope of V_C1 + V_center - Vdc / 2. Here, V_center is the voltage between node N1 and node N2. Line 222 indicates the low - potential - side envelope of V_C1 + V_center - Vdc / 2.

[0092] (Analysis of a partial operation mode of the first embodiment) The analysis of a partial operation mode of the three - phase power - factor - improvement converter 1 of the first embodiment will be described. Specifically, the analysis of the operation mode when a current I_D1 flows through the diode D1 in the three - phase power - factor - improvement converter 1 (see lines 211a, 211b, and 211c in FIG. 4) will be described.

[0093] [1]When V_C1 > 0, V_C2 > 0, V_C3 < 0, and the switching elements Q1 to Q6 are all off

[0094] In order to obtain the voltage V_center between node N1 and node N2, it is considered that the three-phase power factor correction converter 1 has no diodes D1 to D6.

[0095] FIG. 6 is a diagram for explaining the operation mode analysis of the three-phase power factor correction converter according to the first embodiment.

[0096] Since it is the timing when the switching elements Q1 to Q6 are all off, as shown in FIG. 6, the current I_R of the first phase (R phase) flows through the diode D7, the current I_S of the second phase (S phase) flows through the diode D8, and the current I_T of the third phase (T phase) flows through the diode D12.

[0097] Then, the following equations (7) to (9) hold. In equations (7) to (9), L_L1 is the inductance value of the inductor L1, L_L2 is the inductance value of the inductor L2, and L_L3 is the inductance value of the inductor L3.

Equation

[0098] Add the left sides and the right sides of equations (7) to (9) to each other. The equation after addition becomes 0V. Therefore, the voltage V_center is expressed by the following equation (10).

Equation

[0099] As described above, in this circuit simulation, the output voltage (Vdc) was set to 750V. That is, V_center = Vdc / 6 = 750 / 6 = 125 (V).

[0100] Therefore, when (the instantaneous value of the first-phase (R-phase) voltage) + V_center > Vdc / 2, that is, when (the instantaneous value of the first-phase (R-phase) voltage) > 250V, a forward voltage is applied to diode D1, and a current I_D1 flows through diode D1.

[0101] Line 211a in Fig. 4 indicates the current I_D1 in this case of [1].

[0102] [2] When V_C1 > 0, V_C2 < 0, V_C3 > 0, and at the timing when switching elements Q1 to Q6 are all off

[0103] To obtain the voltage V_center, it is considered that the three-phase power factor correction converter 1 has no diodes D1 to D6.

[0104] Fig. 7 is a diagram for explaining the operation mode analysis of the three-phase power factor correction converter according to the first embodiment.

[0105] Since it is the timing when switching elements Q1 to Q6 are all off, as shown in Fig. 7, the current I_R of the first phase (R phase) flows through diode D7, the current I_S of the second phase (S phase) flows through diode D11, and the current I_T of the third phase (T phase) flows through diode D9.

[0106] Then, the following equations (11) to (13) hold.

Equation

[0107] Add the left sides and the right sides of equations (11) to (13) to each other. The resulting equation becomes 0V. Therefore, the voltage V_center is expressed by the following equation (14).

Equation

[0108] That is, V_center = Vdc / 6 = 750 / 6 = 125 (V).

[0109] Therefore, when (the instantaneous value of the first-phase (R-phase) voltage) + V_center > Vdc / 2, that is, (the instantaneous value of the first-phase (R-phase) voltage) > 250 V, a forward voltage is applied to the diode D1, and a current I_D1 flows through the diode D1.

[0110] Line 211b in FIG. 3 shows the current I_D1 in this case [2].

[0111] [3] When V_C1 is near the positive peak, V_C2 < 0, V_C3 < 0, and the timing when the switching elements Q1 to Q6 are all on

[0112] To obtain the voltage V_center, consider the three-phase power factor correction converter 1 without the diodes D1 to D6.

[0113] FIG. 8 is a diagram for explaining the operation mode analysis of the three-phase power factor correction converter according to the first embodiment.

[0114] Since it is the timing when the switching elements Q1 to Q6 are all on, as shown in FIG. 8, the current of the first phase (R phase) flows through the bidirectional switch 21, the current of the second phase (S phase) flows through the bidirectional switch 22, and the current of the third phase (T phase) flows through the bidirectional switch 23.

[0115] Then, the following equations (15) to (17) hold.

Equation

[0116] Add the left sides and the right sides of equations (15) to (17) respectively. The equation after addition becomes 0 V. Therefore, the voltage V_center is expressed by the following equation (18).

Equation

[0117] That is, V_center = 0 (V).

[0118] Therefore, when (instantaneous value of the first-phase (R-phase) voltage) + V_center > Vdc / 2, that is, when (instantaneous value of the first-phase (R-phase) voltage) > 375 V, a forward voltage is applied to diode D1, and current I_D1 flows through diode D1.

[0119] As described above, since the three-phase input voltage (effective value of the line voltage) is AC484V, the maximum voltage near the peak of the first-phase (R-phase) voltage is 484 / sqrt(3)×sqrt(2) = 395 (V). Therefore, current I_D1 flows through diode D1 during the period when the first-phase (R-phase) voltage ranges from 375V to 395V.

[0120] Line 211c in Fig. 4 indicates current I_D1 in this case of [3].[[]END]]

[0121] In the above [1] to [3], the case where a forward voltage is applied to diode D1 has been considered. However, the case where a forward voltage is applied to diodes D2 to D6 is the same, so the description is omitted.

[0122] (Summary of the problems of the first embodiment) As described above, in the three-phase power factor improvement converter 1 of the first embodiment, there is a timing when current flows through diodes D1 to D6 in a steady state where no surge voltage is input.

[0123] As a result, in the three-phase power factor improvement converter 1, diodes D1 to D6 generate heat, and heat dissipation measures are required. Also, in the three-phase power factor improvement converter 1, unnecessary currents I_D1 to I_D6 flow, so the conversion efficiency also decreases, and the power factor also decreases.

[0124] (Configuration of the second embodiment) FIG. 9 is a diagram showing the configuration of the three-phase power factor improvement converter according to the second embodiment.

[0125] The three-phase power factor improvement converter 1A further includes a wiring 31 as compared with the three-phase power factor improvement converter 1 (see FIG. 2).

[0126] One end of the wiring 31 is electrically connected to the node N1. The other end of the wiring 31 is electrically connected to the node N2.

[0127] As a result, the voltage V_center between the node N1 and the node N2 becomes 0V.

[0128] (Circuit simulation results of the second embodiment) FIGS. 10 and 11 are diagrams showing the circuit simulation results of the three-phase power factor improvement converter according to the second embodiment.

[0129] Referring to FIG. 10, the line 231 indicates the voltage V_C1 of the capacitor C1. The line 232 indicates the voltage V_C2 of the capacitor C2. The line 233 indicates the voltage V_C3 of the capacitor C3. The line 234 indicates the voltage Vdc / 2 (= 375V).

[0130] The line 241 indicates the current I_D1 of the diode D1, the current I_D2 of the diode D2, and the current I_D3 of the diode D3. The line 242 indicates the current I_D4 of the diode D4, the current I_D5 of the diode D5, and the current I_D6 of the diode D6.

[0131] FIG. 11 is a view focusing on the first phase (R phase). The line 251 indicates the current I_D1. The line 252 indicates V_C1 + V_center - Vdc / 2.

[0132] (Effect) Comparing FIG. 10 with FIG. 4, the three-phase power factor improvement converter 1A can suppress each of the currents from the current I_D1 to the current I_D6 to approximately 0A.

[0133] Therefore, the three-phase power factor improvement converter 1A can suppress the heat generation from diode D1 to diode D6, eliminating the need for heat dissipation measures for diodes D1 to D6. Further, the three-phase power factor improvement converter 1A can suppress the losses generated from diode D1 to diode D6, suppressing the decrease in conversion efficiency and also suppressing the decrease in power factor.

[0134] <Third Embodiment> (Configuration) FIG. 12 is a diagram showing the configuration of the three-phase power factor improvement converter according to the third embodiment.

[0135] The three-phase power factor improvement converter 1B further includes a capacitor C8 as compared with the three-phase power factor improvement converter 1 (see FIG. 2).

[0136] The capacitor C8 corresponds to an example of the "eighth capacitor" of the present disclosure.

[0137] One end of the capacitor C8 is electrically connected to the node N1. The other end of the capacitor C8 is electrically connected to the node N2.

[0138] (Circuit Simulation Results) FIG. 13 is a diagram showing the circuit simulation results of the three-phase power factor improvement converter according to the third embodiment.

[0139] Line 261 indicates the voltage V_C1 of capacitor C1 + the voltage V_C8 of capacitor C8. Line 262 indicates the voltage V_C2 of capacitor C2 + the voltage V_C8 of capacitor C8. Line 263 indicates the voltage V_C3 of capacitor C3 + the voltage V_C8 of capacitor C8. Line 264 indicates the voltage Vdc / 2 (= 375V).

[0140] Line 271 indicates the current I_D1 of diode D1, the current I_D2 of diode D2, and the current I_D3 of diode D3. Line 272 indicates the current I_D4 of diode D4, the current I_D5 of diode D5, and the current I_D6 of diode D6.

[0141] (Effect) Comparing FIG. 13 with FIG. 4, the three-phase power factor improvement converter 1B can suppress each of the currents from current I_D1 to current I_D6 to approximately 0 A.

[0142] As a result, the three-phase power factor improvement converter 1B can suppress the heat generation of the diodes from diode D1 to diode D6, eliminating the need for heat dissipation measures for the diodes from diode D1 to diode D6. Further, the three-phase power factor improvement converter 1B can suppress the losses generated by the diodes from diode D1 to diode D6, suppress the decrease in conversion efficiency, and also suppress the decrease in power factor.

[0143] <The Fourth Embodiment> (Configuration of an Example) FIG. 14 is a diagram showing the configuration of a three-phase power factor improvement converter of an example of the fourth embodiment.

[0144] The three-phase power factor improvement converter 1C does not include the capacitor C3 as compared with the three-phase power factor improvement converter 1A (see FIG. 9).

[0145] (Circuit Simulation Results of an Example) FIG. 15 is a diagram showing the circuit simulation results of a three-phase power factor improvement converter of an example of the fourth embodiment.

[0146] Line 281 indicates the voltage V_R. Line 282 indicates the voltage V_S. Line 283 indicates the voltage V_T. Line 284 indicates the voltage V_C1. Line 285 indicates the voltage V_C2. Line 286 indicates the voltage V_C3.

[0147] Comparing lines 284 to 286 in FIG. 15 with lines 231 to 233 in FIG. 10, the three-phase power factor improvement converter 1C can obtain a voltage V_C3 equivalent to the voltage V_C3 of the three-phase power factor improvement converter 1A.

[0148] (Effect of an Example) The three-phase power factor improvement converter 1C can reduce the number of capacitors compared to the three-phase power factor improvement converter 1A. As a result, the three-phase power factor improvement converter 1C can be miniaturized and cost-reduced.

[0149] (Supplementary Note) In the above description, the case where the three-phase power factor improvement converter 1C does not include the capacitor C3 has been described, but the present disclosure is not limited thereto. The three-phase power factor improvement converter 1C may not include the capacitor C1 or the capacitor C2 instead of the capacitor C3.

[0150] That is, the three-phase power factor improvement converter 1C may delete one capacitor from the capacitors C1 to C3 connected in Y (star) on the input side. In other words, the three-phase power factor improvement converter 1C only needs to include at least two of the three Y-connected capacitors on the input side.

[0151] <Fifth Embodiment> FIG. 16 is a diagram showing the configuration of a three-phase power factor improvement converter according to an example of the fifth embodiment.

[0152] The three-phase power factor improvement converter 1D does not include the capacitor C3 compared to the three-phase power factor improvement converter 1B (see FIG. 12).

[0153] (Circuit Simulation Results of an Example) FIG. 17 is a diagram showing the circuit simulation results of a three-phase power factor improvement converter according to an example of the fifth embodiment.

[0154] Line 291 indicates the voltage V_R. Line 292 indicates the voltage V_S. Line 293 indicates the voltage V_T. Line 294 indicates the voltage V_C1 + the voltage V_C8 of the capacitor C8. Line 295 indicates the voltage V_C2 + the voltage V_C8 of the capacitor C8. Line 296 indicates the voltage V_C3 + the voltage V_C8 of the capacitor C8.

[0155] When comparing the section from line 294 to line 296 in FIG. 17 with the section from line 261 to line 263 in FIG. 13, the three-phase power factor improvement converter 1D can obtain a voltage V_C3 equivalent to the voltage V_C3 of the three-phase power factor improvement converter 1A.

[0156] (Effect of an example) Compared with the three-phase power factor improvement converter 1B, the three-phase power factor improvement converter 1D can reduce the number of capacitors. As a result, the three-phase power factor improvement converter 1D can be miniaturized and cost-reduced.

[0157] (Supplementary note) In the above description, the case where the three-phase power factor improvement converter 1D does not include the capacitor C3 has been explained, but the present disclosure is not limited to this. The three-phase power factor improvement converter 1D may not include the capacitor C1 or the capacitor C2 instead of the capacitor C3.

[0158] That is, the three-phase power factor improvement converter 1D may delete one capacitor from among the capacitors C1 to C3 connected in Y (star) on the input side. In other words, the three-phase power factor improvement converter 1D only needs to include at least two of the three Y-connected capacitors on the input side.

[0159] (First example of the condition where no current flows from current I_D1 to current I_D6) Examine the first example of the condition where no current flows from current I_D1 to current I_D6 in the three-phase power factor improvement converter 1A of the second embodiment.

[0160] FIG. 18 is a diagram showing the circuit simulation result of the three-phase power factor improvement converter of the second embodiment.

[0161] Line 301 indicates the voltage V_R. Line 302 indicates the voltage V_S. Line 303 indicates the voltage V_T. Line 304 indicates the voltage V_C1. Line 305 indicates the voltage V_C2. Line 306 indicates the voltage V_C3.

[0162] Examine the first phase (R phase).

[0163] Referring to timing t1, the peak of voltage V_C1 (line 304) overlaps (crosses) with voltage V_R (line 301) at point P1. Referring to timing t0, voltage V_R (line 301) is 0V at point P0. The phase difference between timing t0 and timing t1 is 60°.

[0164] Therefore, the voltage of voltage V_R at timing t1, that is, the voltage at point P1, is represented by the following equation (19). (Voltage at point P1) =(Input maximum line-to-line voltage rms value) / sqrt(3)×sqrt(2)×sin60° =(Input maximum line-to-line voltage rms value)×sqrt(2) / 2 ···(19)

[0165] That is, the peak value of voltage V_C1 is (input maximum line-to-line voltage rms value)×sqrt(2) / 2.

[0166] If (input maximum line-to-line voltage rms value)×sqrt(2) / 2 < Vdc / 2, no forward voltage is applied to diode D1, so current I_D1 does not flow. That is, if (input maximum line-to-line voltage rms value)×sqrt(2) < Vdc, no forward voltage is applied to diode D1, so current I_D1 does not flow.

[0167] For example, when the input maximum line-to-line voltage rms value ranges from AC373.5V to 484V, the boost of the minimum PFC is 484V*sqrt(2)=684.4794V. If 684.4794V / 2 = 342.2397V < Vdc / 2, current I_D1 does not flow. That is, if 684.4794V < Vdc, current I_D1 does not flow.

[0168] The same applies to the second phase (S phase) and the third phase (T phase).

[0169] (Circuit simulation results of the first example of the condition that currents I_D1 to I_D6 do not flow) FIG. 19 is a diagram showing the circuit simulation results of the three-phase power factor improvement converter according to the second embodiment.

[0170] In this circuit simulation, the three-phase input voltage (input maximum line-to-line voltage effective value) was set to AC484V, the DC output voltage (output voltage Vdc) was set to 689V, and the output current was set to 11.77A.

[0171] Line 311 indicates voltage V_R. Line 312 indicates voltage V_S. Line 313 indicates voltage V_T. Line 314 indicates voltage V_C1. Line 315 indicates voltage V_C2. Line 316 indicates voltage V_C3.

[0172] Line 321 indicates currents I_D1 to I_D6. Each of the currents from I_D1 to I_D6 is approximately 0A.

[0173] (Summary of the first example of the condition where no current flows from current I_D1 to current I_D6) Under the condition that (input maximum line-to-line voltage effective value) × sqrt(2) / 2 < Vdc / 2, that is, (input maximum line-to-line voltage effective value) × sqrt(2) < Vdc, no current flows from current I_D1 to current I_D6 during normal operation (when no surge voltage is input).

[0174] Note that if wiring 31 is not present, even under the above conditions, current will flow from current I_D1 to current I_D6 during normal operation (when no surge voltage is input).

[0175] (Second example of the condition where no current flows from current I_D1 to current I_D6) A second example of the condition where no current flows from current I_D1 to current I_D6 in the three-phase power factor improvement converter 1B according to the third embodiment will be considered.

[0176] FIG. 20 is a diagram showing the circuit simulation results of the three-phase power factor improvement converter according to the third embodiment.

[0177] Line 331 indicates voltage \(V_R\). Line 332 indicates voltage \(V_S\). Line 333 indicates voltage \(V_T\). Line 334 indicates voltage \(V_{C1}+V_{center}\). Line 335 indicates voltage \(V_{C2}+V_{center}\). Line 336 indicates voltage \(V_{C3}+V_{center}\).

[0178] Consider the first phase (R phase).

[0179] Timing \(t\) 11 Referring to it, the peak of voltage \(V_{C1}+V_{center}\) (line 304) overlaps (crosses) voltage \(V_R\) (line 331) at point \(P11\). Timing \(t\) 10 Referring to it, voltage \(V_R\) (line 331) is 0 V at point \(P10\). Timing \(t\) 10 and timing \(t\) 11 The phase difference between them is \(60^{\circ}\).

[0180] Therefore, the voltage of voltage \(V_R\) at timing \(t\) 11 , that is, the voltage at point \(P11\), is represented by the above formula (19).

[0181] That is, the peak value of voltage \(V_{C1}+V_{center}\) is \((\text{input maximum line - to - line voltage rms value})\times\sqrt{2} / 2\).

[0182] If \((\text{input maximum line - to - line voltage rms value})\times\sqrt{2} / 2 < V_{dc} / 2\), no forward voltage is applied to diode \(D1\), so current \(I_{D1}\) does not flow. That is, if \((\text{input maximum line - to - line voltage rms value})\times\sqrt{2}<V_{dc}\), no forward voltage is applied to diode \(D1\), so current \(I_{D1}\) does not flow.

[0183] The same applies to the second phase (S phase) and the third phase (T phase).

[0184] (Circuit simulation result of the second example of the condition that currents \(I_{D1}\) to \(I_{D6}\) do not flow) Figure 21 is a diagram showing the circuit simulation result of the three - phase power factor improvement converter of the third embodiment.

[0185] In this circuit simulation, the three-phase input voltage (the effective value of the maximum line-to-line input voltage) was set to AC484V, the DC output voltage (output voltage Vdc) was set to 689V, and the output current was set to 11.77A.

[0186] Line 341 indicates voltage VR. Line 342 indicates voltage VS. Line 343 indicates voltage VT. Line 344 indicates voltage VC1 + voltage V_center. Line 345 indicates voltage VC2 + voltage V_center. Line 346 indicates voltage VC3 + voltage V_center.

[0187] Line 351 indicates currents ID1 to ID6. Each of the currents from ID1 to ID6 is approximately 0A.

[0188] (Summary of the second example of the condition where no current flows from current ID1 to current ID6) When (the effective value of the maximum line-to-line input voltage) × sqrt(2) / 2 < Vdc / 2, that is, when (the effective value of the maximum line-to-line input voltage) × sqrt(2) < Vdc, no current flows from current ID1 to current ID6 during normal operation (when no surge voltage is input).

[0189] Note that if capacitor C8 is not present, even under the above conditions, current will flow from current ID1 to current ID6 during normal operation (when no surge voltage is input).

[0190] (Supplementary note on the first and second examples of the condition where no current flows from current ID1 to current ID6) It is common for there to be a high-frequency ripple voltage of several volts to several tens of volts from voltage VC1 to voltage VC3. That is, the absolute value α of the high-frequency ripple voltage is several volts to several tens of volts.

[0191] Considering the absolute value α of the high-frequency ripple voltage, it is preferable that (input maximum line-to-line voltage effective value) × sqrt(2) + (absolute value α of the high-frequency ripple voltage) < Vdc. As a result, no forward voltage is applied to diodes D1 to D6, so that currents I_D1 to I_D6 do not flow during normal operation (when no surge voltage is input).

[0192] Note that if wiring 31 or capacitor C8 is missing, currents I_D1 to I_D6 will flow during normal operation (when no surge voltage is input), even under the above conditions.

[0193] <Sixth Embodiment> (Configuration) FIG. 22 is a diagram showing the configuration of the three-phase power factor correction converter according to the sixth embodiment.

[0194] The three-phase power factor correction converter 1E further includes capacitors C6 and C7 as compared with the three-phase power factor correction converter 1A (see FIG. 9). Capacitors C6 and C7 are exemplified by film capacitors, but the present disclosure is not limited thereto.

[0195] One end of capacitor C6 is electrically connected to terminal 14. The other end of capacitor C6 is electrically connected to one end of capacitor C7. The other end of capacitor C7 is electrically connected to terminal 15. The other end of wiring 31 is electrically connected to node N3, which is the connection point between capacitor C6 and capacitor C7.

[0196] (Circuit Simulation Results) FIG. 23 is a diagram showing the circuit simulation results of the three-phase power factor correction converter according to the sixth embodiment.

[0197] Line 501 indicates voltage V_C1. Line 502 indicates voltage V_C2. Line 503 indicates voltage V_C3. Line 504 indicates voltage Vdc / 2 (= 375V).

[0198] Line 511 indicates current I_D1, current I_D2, and current I_D3. Line 512 indicates current I_D4, current I_D5, and current I_D6.

[0199] (Effect) Comparing FIG. 23 with FIG. 4, the three-phase power factor improvement converter 1E can suppress each of the currents from I_D1 to I_D6 to approximately 0 A.

[0200] Thereby, the three-phase power factor improvement converter 1E can suppress the heat generation of the diodes from D1 to D6, and heat dissipation measures for the diodes from D1 to D6 are not required. Further, the three-phase power factor improvement converter 1E can suppress the losses generated in the diodes from D1 to D6, suppress a decrease in conversion efficiency, and suppress a decrease in power factor.

[0201] <Seventh Embodiment> (Configuration) FIG. 24 is a diagram showing the configuration of the three-phase power factor improvement converter according to the seventh embodiment.

[0202] The three-phase power factor improvement converter 1F further includes a capacitor C8 as compared with the three-phase power factor improvement converter 1E (see FIG. 22).

[0203] (Circuit Simulation Results) FIG. 25 is a diagram showing the circuit simulation results of the three-phase power factor improvement converter according to the seventh embodiment.

[0204] Line 521 indicates the voltage V_C8 of the voltage V_C1+C8. Line 522 indicates the voltage V_C8 of the voltage V_C2+C8. Line 523 indicates the voltage V_C8 of the voltage V_C3+C8. Line 524 indicates the voltage Vdc / 2 (=375 V).

[0205] Line 531 indicates the current I_D1 of the diode D1, the current I_D2 of the diode D2, and the current I_D3 of the diode D3. Line 532 indicates the current I_D4 of the diode D4, the current I_D5 of the diode D5, and the current I_D6 of the diode D6.

[0206] (Effect) When comparing Fig. 25 with Fig. 4, the three-phase power factor improvement converter 1F can suppress each of the currents from I_D1 to I_D6 to approximately 0 A.

[0207] As a result, the three-phase power factor improvement converter 1F can suppress the heat generation of the diodes from D1 to D6, eliminating the need for heat dissipation measures for the diodes from D1 to D6. Also, the three-phase power factor improvement converter 1F can suppress the losses generated in the diodes from D1 to D6, suppressing a decrease in conversion efficiency and also suppressing a decrease in power factor.

[0208] <Eighth Embodiment> (Example Configuration) Fig. 26 is a diagram showing the configuration of a three-phase power factor improvement converter according to an example of the eighth embodiment.

[0209] The three-phase power factor improvement converter 1G does not include the capacitor C3 as compared with the three-phase power factor improvement converter 1E (see Fig. 22).

[0210] (Circuit Simulation Results) Fig. 27 is a diagram showing the circuit simulation results of a three-phase power factor improvement converter according to an example of the eighth embodiment.

[0211] Line 541 indicates the voltage V_C1. Line 542 indicates the voltage V_C2. Line 543 indicates the voltage V_C3. Line 544 indicates the voltage Vdc / 2 (= 375 V).

[0212] Line 551 indicates the current I_D1 of the diode D1, the current I_D2 of the diode D2, and the current I_D3 of the diode D3. Line 561 indicates the current I_D4 of the diode D4, the current I_D5 of the diode D5, and the current I_D6 of the diode D6.

[0213] (Effect) Comparing FIG. 27 with FIG. 4, the three-phase power factor improvement converter 1G can suppress each of the currents from I_D1 to I_D3 to approximately 0 A. Also, the three-phase power factor improvement converter 1G can suppress each of the currents from I_D4 to I_D6 to approximately 0 A.

[0214] Thereby, the three-phase power factor improvement converter 1G can suppress the heat generation of the diodes from D1 to D6, and heat dissipation measures for the diodes from D1 to D6 become unnecessary. Also, the three-phase power factor improvement converter 1G can suppress the losses generated in the diodes from D1 to D6, can suppress a decrease in conversion efficiency, and can also suppress a decrease in power factor.

[0215] (Supplementary Note) In the above, the case where the three-phase power factor improvement converter 1G does not include the capacitor C3 has been described, but the present disclosure is not limited thereto. The three-phase power factor improvement converter 1G may not include the capacitor C1 or the capacitor C2 instead of the capacitor C3.

[0216] That is, the three-phase power factor improvement converter 1G may delete one capacitor from the capacitors C1 to C3 connected in Y (star) on the input side. In other words, the three-phase power factor improvement converter 1G only needs to include at least two of the three capacitors connected in Y on the input side.

[0217] (Ninth Embodiment) (Example Configuration) FIG. 28 is a diagram showing the configuration of an example of the three-phase power factor improvement converter according to the ninth embodiment.

[0218] The three-phase power factor improvement converter 1H does not include the capacitor C3 as compared with the three-phase power factor improvement converter 1F (see FIG. 24).

[0219] (Circuit Simulation Results) FIG. 29 is a diagram showing the circuit simulation results of an example of the three-phase power factor improvement converter according to the ninth embodiment.

[0220] Line 571 indicates the voltage V_C8 of the voltage V_C1+C8. Line 572 indicates the voltage V_C8 of the voltage V_C2+C8. Line 573 indicates the voltage V_C8 of the voltage V_C3+C8. Line 574 indicates the voltage Vdc / 2 (=375V).

[0221] Line 581 indicates the current I_D1 of diode D1, the current I_D2 of diode D2, and the current I_D3 of diode D3. Line 591 indicates the current I_D4 of diode D4, the current I_D5 of diode D5, and the current I_D6 of diode D6.

[0222] (Effect) Comparing FIG. 29 with FIG. 4, the three-phase power factor improvement converter 1H can suppress each of the currents from I_D1 to I_D3 to approximately 0A. Also, the three-phase power factor improvement converter 1H can suppress each of the currents from I_D4 to I_D6 to approximately 0A.

[0223] Thereby, the three-phase power factor improvement converter 1H can suppress the heat generation of the diodes from D1 to D6, and heat dissipation measures for the diodes from D1 to D6 are not required. Also, the three-phase power factor improvement converter 1H can suppress the losses generated in the diodes from D1 to D6, suppress the decrease in conversion efficiency, and suppress the decrease in power factor.

[0224] (Supplementary Note) In the above, the case where the three-phase power factor improvement converter 1H does not include the capacitor C3 has been described, but the present disclosure is not limited thereto. The three-phase power factor improvement converter 1H may not include the capacitor C1 or the capacitor C2 instead of the capacitor C3.

[0225] That is, the three-phase power factor improvement converter 1H may delete one of the capacitors from the input-side Y (star)-connected capacitors C1 to C3. In other words, the three-phase power factor improvement converter 1H may include at least two of the three input-side Y-connected capacitors.

[0226] <Embodiment 10> (Configuration) FIG. 30 is a diagram showing the configuration of a three-phase power factor improvement converter according to the tenth embodiment.

[0227] The three-phase power factor improvement converter 1I includes arms 41 to 43 instead of diodes D7 to D12 and bidirectional switches 21 to 23 as compared with the three-phase power factor improvement converter 1A (see FIG. 9).

[0228] Arm 41 includes a high-side switching element Q11 and a low-side switching element Q12. Arm 42 includes a high-side switching element Q13 and a low-side switching element Q14. Arm 43 includes a high-side switching element Q15 and a low-side switching element Q16. Although FETs are exemplified for the switching elements Q11 to Q16, the present disclosure is not limited thereto.

[0229] The switching element Q11 corresponds to an example of the "first switching element" of the present disclosure. The switching element Q12 corresponds to an example of the "second switching element" of the present disclosure. The switching element Q13 corresponds to an example of the "third switching element" of the present disclosure. The switching element Q14 corresponds to an example of the "fourth switching element" of the present disclosure. The switching element Q15 corresponds to an example of the "fifth switching element" of the present disclosure. The switching element Q16 corresponds to an example of the "sixth switching element" of the present disclosure.

[0230] The drain of the switching element Q11 is electrically connected to the terminal 14. The source of the switching element Q11 is electrically connected to the other end of the inductor L1. The drain of the switching element Q12 is electrically connected to the other end of the inductor L1. The source of the switching element Q12 is electrically connected to the terminal 15.

[0231] The drain of the switching element Q13 is electrically connected to terminal 14. The source of the switching element Q13 is electrically connected to the other end of the inductor L2. The drain of the switching element Q14 is electrically connected to the other end of the inductor L2. The source of the switching element Q14 is electrically connected to terminal 15.

[0232] The drain of the switching element Q15 is electrically connected to terminal 14. The source of the switching element Q15 is electrically connected to the other end of the inductor L3. The drain of the switching element Q16 is electrically connected to the other end of the inductor L3. The source of the switching element Q16 is electrically connected to terminal 15.

[0233] (Circuit simulation results) FIG. 31 is a diagram showing the circuit simulation results of the three-phase power factor improvement converter of the tenth embodiment.

[0234] Line 601 indicates the voltage V_C1. Line 602 indicates the voltage V_C2. Line 603 indicates the voltage V_C3. Line 604 indicates the voltage Vdc / 2 (= 375V).

[0235] Line 611 indicates the currents I_D1, I_D2, and I_D3. Line 612 indicates the currents I_D4, I_D5, and I_D6.

[0236] (Effect) Comparing FIG. 31 with FIG. 4, the three-phase power factor improvement converter 1I can suppress each of the currents from I_D1 to I_D6 to approximately 0A.

[0237] Thereby, the three-phase power factor improvement converter 1I can suppress the heat generation of the diodes from D1 to D6, eliminating the need for heat dissipation measures for the diodes from D1 to D6. Also, the three-phase power factor improvement converter 1I can suppress the losses generated in the diodes from D1 to D6, suppressing a decrease in conversion efficiency and also suppressing a decrease in power factor.

[0238] (Supplementary Note) The condition that no current flows from current I_D1 to current I_D6 in the three - phase power factor improvement converter 1I is the same as that in the above - described embodiment. That is, if (input maximum line - to - line voltage effective value)×sqrt(2) / 2 < Vdc / 2, no forward voltage is applied to diodes D1 to D6, so no current flows from current I_D1 to current I_D6. That is, if (input maximum line - to - line voltage effective value)×sqrt(2) < Vdc, no forward voltage is applied to diodes D1 to D6, so no current flows from current I_D1 to current I_D6.

[0239] Also, considering the absolute value α of the high - frequency ripple voltage from voltage V_C1 to voltage V_C3, it is preferable that (input maximum line - to - line voltage effective value)×sqrt(2)+(absolute value α of the high - frequency ripple voltage) < Vdc. Thereby, no forward voltage is applied to diodes D1 to D6, so no current flows from current I_D1 to current I_D6.

[0240] Note that if there is no wiring 31, even under the above conditions, current flows from current I_D1 to current I_D6.

[0241] <The 11th Embodiment> (Configuration) FIG. 32 is a diagram showing the configuration of the three - phase power factor improvement converter of the 11th embodiment.

[0242] The three - phase power factor improvement converter 1J further includes a capacitor C8 as compared with the three - phase power factor improvement converter 1I (see FIG. 30).

[0243] (Circuit Simulation Results) FIG. 33 is a diagram showing the circuit simulation results of the three - phase power factor improvement converter of the 11th embodiment.

[0244] Line 621 indicates the voltage V_C8 of the voltage V_C1+C8. Line 622 indicates the voltage V_C8 of the voltage V_C2+C8. Line 623 indicates the voltage V_C8 of the voltage V_C3+C8. Line 624 indicates the voltage Vdc / 2 (=375V).

[0245] Line 631 indicates the current I_D1, the current I_D2, and the current I_D3. Line 632 indicates the current I_D4, the current I_D5, and the current I_D6.

[0246] (Effect) When comparing FIG. 33 with FIG. 4, the three-phase power factor improvement converter 1J can suppress each of the currents from I_D1 to I_D6 to approximately 0A.

[0247] As a result, the three-phase power factor improvement converter 1J can suppress the heat generation of the diodes from D1 to D6, eliminating the need for heat dissipation measures for the diodes from D1 to D6. In addition, the three-phase power factor improvement converter 1J can suppress the losses generated in the diodes from D1 to D6, suppress the decrease in conversion efficiency, and suppress the decrease in power factor.

[0248] (Supplementary Note) The condition that no current flows from I_D1 to I_D6 in the three-phase power factor improvement converter 1J is the same as that in the above-described embodiment. That is, if (input maximum line-to-line voltage effective value)×sqrt(2) / 2 < Vdc / 2, no forward voltage is applied to the diodes from D1 to D6, so no current flows from I_D1 to I_D6. That is, if (input maximum line-to-line voltage effective value)×sqrt(2) < Vdc, no forward voltage is applied to the diodes from D1 to D6, so no current flows from I_D1 to I_D6.

[0249] Also, considering the absolute value α of the high-frequency ripple voltage from voltage V_C1 to voltage V_C3, it is preferable that (input maximum line-to-line voltage effective value) × sqrt(2) + (absolute value α of the high-frequency ripple voltage) < Vdc. As a result, no forward voltage is applied to diodes D1 to D6, so currents I_D1 to I_D6 do not flow.

[0250] Note that if capacitor C8 is not present, currents I_D1 to I_D6 will flow even under the above conditions.

[0251] <The 12th Embodiment> (Example Configuration) FIG. 34 is a diagram showing the configuration of an example of a three-phase power factor correction converter according to the 12th embodiment.

[0252] The three-phase power factor correction converter 1K does not include capacitor C3 as compared with the three-phase power factor correction converter 1I (see FIG. 30).

[0253] (Circuit Simulation Results) FIG. 35 is a diagram showing the circuit simulation results of an example of a three-phase power factor correction converter according to the 12th embodiment.

[0254] Line 641 indicates voltage V_C1. Line 642 indicates voltage V_C2. Line 643 indicates voltage V_C3. Line 644 indicates voltage Vdc / 2 (= 375V).

[0255] Line 651 indicates currents I_D1, I_D2, and I_D3. Line 652 indicates currents I_D4, I_D5, and I_D6.

[0256] (Effect) Comparing FIG. 35 with FIG. 4, the three-phase power factor correction converter 1K can suppress each of currents I_D1 to I_D6 to approximately 0A.

[0257] As a result, the three-phase power factor improvement converter 1K can suppress heat generation from diode D1 to diode D6, eliminating the need for heat dissipation measures for diodes D1 to D6. Further, the three-phase power factor improvement converter 1K can suppress losses generated from diode D1 to diode D6, suppress a decrease in conversion efficiency, and also suppress a decrease in power factor.

[0258] (Appendix) Note that, in the above description, the case where the three-phase power factor improvement converter 1K does not include the capacitor C3 has been described, but the present disclosure is not limited thereto. The three-phase power factor improvement converter 1K may not include the capacitor C1 or the capacitor C2 instead of the capacitor C3.

[0259] That is, the three-phase power factor improvement converter 1K may delete one capacitor from among capacitors C1 to C3 connected in Y (star) on the input side. In other words, the three-phase power factor improvement converter 1K only needs to include at least two of the three capacitors connected in Y on the input side.

[0260] <13th Embodiment> (Example Configuration) FIG. 36 is a diagram showing the configuration of an example of a three-phase power factor improvement converter according to the 13th embodiment.

[0261] The three-phase power factor improvement converter 1L does not include the capacitor C3 as compared with the three-phase power factor improvement converter 1J (see FIG. 32).

[0262] (Circuit Simulation Results) FIG. 37 is a diagram showing the circuit simulation results of an example of a three-phase power factor improvement converter according to the 13th embodiment.

[0263] Line 661 indicates the voltage V_C8 of the voltage V_C1 + C8. Line 662 indicates the voltage V_C8 of the voltage V_C2 + C8. Line 663 indicates the voltage V_C8 of the voltage V_C3 + C8. Line 664 indicates the voltage Vdc / 2 (= 375V).

[0264] Line 671 indicates current I_D1, current I_D2, and current I_D3. Line 672 indicates current I_D4, current I_D5, and current I_D6.

[0265] (Effect) Comparing FIG. 37 with FIG. 4, the three-phase power factor improvement converter 1L can suppress each of the currents from I_D1 to I_D6 to approximately 0 A.

[0266] As a result, the three-phase power factor improvement converter 1L can suppress the heat generation of the diodes from D1 to D6, and heat dissipation measures for the diodes from D1 to D6 are not required. Further, the three-phase power factor improvement converter 1L can suppress the losses generated in the diodes from D1 to D6, suppress a decrease in conversion efficiency, and suppress a decrease in power factor.

[0267] (Supplementary Note) In the above description, the case where the three-phase power factor improvement converter 1J does not include the capacitor C3 has been described, but the present disclosure is not limited thereto. The three-phase power factor improvement converter 1J may not include the capacitor C1 or the capacitor C2 instead of the capacitor C3.

[0268] That is, the three-phase power factor improvement converter 1J may delete one of the capacitors from the capacitor C1 to the capacitor C3 connected in Y (star) on the input side. In other words, the three-phase power factor improvement converter 1J only needs to include at least two of the three capacitors connected in Y on the input side.

[0269] <The Fourteenth Embodiment> (Configuration) FIG. 38 is a diagram showing the configuration of the three-phase power factor improvement converter according to the fourteenth embodiment.

[0270] The three-phase power factor improvement converter 1M further includes a capacitor C9 as compared with the three-phase power factor improvement converter 1I (see FIG. 30). The capacitor C9 is exemplified by an electrolytic capacitor, but the present disclosure is not limited thereto.

[0271] Capacitor C9 corresponds to an example of the "ninth capacitor" of the present disclosure.

[0272] One end of capacitor C9 is electrically connected to terminal 14. The other end of capacitor C9 is electrically connected to terminal 15.

[0273] (Circuit simulation result) FIG. 39 is a diagram showing the circuit simulation result of the three-phase power factor improvement converter of the 14th embodiment.

[0274] Line 681 indicates voltage V_C1. Line 682 indicates voltage V_C2. Line 683 indicates voltage V_C3. Line 684 indicates voltage Vdc / 2 (= 375V).

[0275] Line 691 indicates current I_D1, current I_D2, and current I_D3. Line 692 indicates current I_D4, current I_D5, and current I_D6.

[0276] (Effect) Comparing FIG. 39 with FIG. 4, the three-phase power factor improvement converter 1M can suppress each of the currents from current I_D1 to current I_D6 to approximately 0A.

[0277] Thereby, the three-phase power factor improvement converter 1M can suppress the heat generation of the diodes from diode D1 to diode D6, and heat dissipation measures for the diodes from diode D1 to diode D6 become unnecessary. Further, the three-phase power factor improvement converter 1M can suppress the losses generated in the diodes from diode D1 to diode D6, can suppress a decrease in conversion efficiency, and can also suppress a decrease in power factor.

[0278] <15th Embodiment> (Configuration) FIG. 40 is a diagram showing the configuration of the three-phase power factor improvement converter of the 15th embodiment.

[0279] The three-phase power factor improvement converter 1N further includes a capacitor C8 as compared with the three-phase power factor improvement converter 1M (see FIG. 38).

[0280] (Circuit simulation result) FIG. 41 is a diagram showing the circuit simulation result of the three-phase power factor improvement converter according to the 15th embodiment.

[0281] Line 701 indicates the voltage V_C8 of the voltage V_C1+C8. Line 702 indicates the voltage V_C8 of the voltage V_C2+C8. Line 703 indicates the voltage V_C8 of the voltage V_C3+C8. Line 704 indicates the voltage Vdc / 2 (=375 V).

[0282] Line 711 indicates the current I_D1, the current I_D2, and the current I_D3. Line 712 indicates the current I_D4, the current I_D5, and the current I_D6.

[0283] (Effect) Comparing FIG. 41 with FIG. 4, the three-phase power factor improvement converter 1N can suppress each of the currents from I_D1 to I_D6 to approximately 0 A.

[0284] Thereby, the three-phase power factor improvement converter 1N can suppress the heat generation of the diodes from D1 to D6, and heat dissipation measures for the diodes from D1 to D6 become unnecessary. Further, the three-phase power factor improvement converter 1N can suppress the losses generated in the diodes from D1 to D6, suppress a decrease in conversion efficiency, and also suppress a decrease in power factor.

[0285] <16th Embodiment> (Example Configuration) FIG. 42 is a diagram showing the configuration of an example of the three-phase power factor improvement converter according to the 16th embodiment.

[0286] The three-phase power factor improvement converter 1O does not include the capacitor C3 as compared with the three-phase power factor improvement converter 1M (see FIG. 38).

[0287] (Circuit simulation result) FIG. 43 is a diagram showing the circuit simulation result of an example of the three-phase power factor improvement converter according to the 16th embodiment.

[0288] Line 721 indicates voltage V_C1. Line 722 indicates voltage V_C2. Line 723 indicates voltage V_C3. Line 724 indicates voltage Vdc / 2 (= 375V).

[0289] Line 731 indicates current I_D1, current I_D2, and current I_D3. Line 732 indicates current I_D4, current I_D5, and current I_D6.

[0290] (Effect) Comparing FIG. 43 with FIG. 4, the three-phase power factor improvement converter 1O can suppress each of the currents from I_D1 to I_D6 to approximately 0A.

[0291] As a result, the three-phase power factor improvement converter 1O can suppress the heat generation of the diodes from D1 to D6, eliminating the need for heat dissipation measures for the diodes from D1 to D6. Also, the three-phase power factor improvement converter 1O can suppress the losses generated in the diodes from D1 to D6, suppressing a decrease in conversion efficiency and also suppressing a decrease in power factor.

[0292] (Supplementary Note) In the above, the case where the three-phase power factor improvement converter 1O does not include the capacitor C3 has been described, but the present disclosure is not limited to this. The three-phase power factor improvement converter 1O may not include the capacitor C1 or the capacitor C2 instead of the capacitor C3.

[0293] That is, the three-phase power factor improvement converter 1O may delete one of the capacitors from the input-side Y (star)-connected capacitors C1 to C3. In other words, the three-phase power factor improvement converter 1O only needs to include at least two of the three input-side Y-connected capacitors.

[0294] <The 17th Embodiment> (Example Configuration) FIG. 44 is a diagram showing the configuration of an example of a three-phase power factor improvement converter according to the 17th embodiment.

[0295] The three-phase power factor improvement converter 1P does not include the capacitor C3 as compared with the three-phase power factor improvement converter 1N (see Fig. 40).

[0296] (Circuit simulation results) Fig. 45 is a diagram showing the circuit simulation results of a three-phase power factor improvement converter as an example of the 17th embodiment.

[0297] Line 741 indicates the voltage V_C8 of the voltage V_C1+C8. Line 742 indicates the voltage V_C8 of the voltage V_C2+C8. Line 743 indicates the voltage V_C8 of the voltage V_C3+C8. Line 744 indicates the voltage Vdc / 2 (=375V).

[0298] Line 751 indicates the current I_D1, the current I_D2, and the current I_D3. Line 752 indicates the current I_D4, the current I_D5, and the current I_D6.

[0299] (Effect) Comparing Fig. 45 with Fig. 4, the three-phase power factor improvement converter 1P can suppress each of the currents from the current I_D1 to the current I_D6 to approximately 0A.

[0300] Thereby, the three-phase power factor improvement converter 1P can suppress the heat generation of the diodes from diode D1 to diode D6, and heat dissipation measures for the diodes from diode D1 to diode D6 become unnecessary. Also, the three-phase power factor improvement converter 1P can suppress the losses generated in the diodes from diode D1 to diode D6, suppress a decrease in the conversion efficiency, and suppress a decrease in the power factor.

[0301] (Supplementary note) Note that, in the above, the case where the three-phase power factor improvement converter 1P does not include the capacitor C3 has been described, but the present disclosure is not limited thereto. The three-phase power factor improvement converter 1P may not include the capacitor C1 or the capacitor C2 instead of the capacitor C3.

[0302] That is, the three-phase power factor improvement converter 1P may delete one capacitor from the capacitors C1 to C3 connected in Y (star) on the input side. In other words, the three-phase power factor improvement converter 1P only needs to include at least two of the three Y-connected capacitors on the input side.

[0303] <Summary of the conditions under which currents I_D1 to I_D6 do not flow in each embodiment> Due to the measure of providing the wiring 31 or the capacitor C8 in each embodiment, under the condition that (input maximum line-to-line voltage effective value)×sqrt(2) / 2 < Vdc / 2, that is, (input maximum line-to-line voltage effective value)×sqrt(2) < Vdc, during normal operation (when no surge voltage is input), currents I_D1 to I_D6 do not flow.

[0304] Also, considering the absolute value α of the high-frequency ripple voltage from voltage V_C1 to voltage V_C3, it is preferable that (input maximum line-to-line voltage effective value)×sqrt(2)+(absolute value α of the high-frequency ripple voltage) < Vdc. Thus, since no forward voltage is applied to the diodes D1 to D6, during normal operation (when no surge voltage is input), currents I_D1 to I_D6 do not flow.

[0305] Note that if there is no wiring 31 or capacitor C8, even under the above conditions, during normal operation (when no surge voltage is input), currents I_D1 to I_D6 will flow.

[0306] As described above, the embodiments of the present disclosure have been described, but the present disclosure is not limited by the contents of these embodiments. Also, the above-described components include those that can be easily assumed by those skilled in the art, substantially the same ones, and those within the so-called equivalent range. Furthermore, the above-described components can be combined as appropriate. Moreover, various omissions, substitutions, or changes of the components can be made without departing from the gist of the above-described embodiments.

Description of Reference Numerals

[0307] 1, 1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H, 1I, 1J, 1K, 1L, 1M, 1N, 1O, 1P Three-phase power factor improvement converter 21, 22, 23 Bidirectional switch 24 Control unit 41, 42, 43 Arm C1, C2, C3, C4, C5, C6, C7, C8, C9 Capacitor D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12 Diode L1, L2, L3 Inductor Q1, Q2, Q3, Q4, Q5, Q6, Q11, Q12, Q13, Q14, Q15, Q16 Switching element

Claims

1. A three-phase power factor improvement converter that receives a three-phase AC voltage at a first input terminal, a second input terminal, and a third input terminal and outputs a DC voltage from a first output terminal and a second output terminal, a first diode having an anode electrically connected to the first input terminal and a cathode electrically connected to the first output terminal; a second diode having an anode electrically connected to the second input terminal and a cathode electrically connected to the first output terminal; a third diode having an anode electrically connected to the third input terminal and a cathode electrically connected to the first output terminal; a fourth diode having a cathode electrically connected to the first input terminal and an anode electrically connected to the second output terminal; a fifth diode having a cathode electrically connected to the second input terminal and an anode electrically connected to the second output terminal; a sixth diode having a cathode electrically connected to the third input terminal and an anode electrically connected to the second output terminal; comprising: A three-phase power factor improvement converter characterized by the above.

2. At least two of a first capacitor having one end electrically connected to the first input terminal and the other end electrically connected to a first node, a second capacitor having one end electrically connected to the second input terminal and the other end electrically connected to the first node, and a third capacitor having one end electrically connected to the third input terminal and the other end electrically connected to the first node; a fourth capacitor having one end electrically connected to the first output terminal and the other end electrically connected to a second node; a fifth capacitor having one end electrically connected to the second node and the other end electrically connected to the second output terminal; a wiring having one end electrically connected to the first node and the other end electrically connected to the second node; comprising: The three-phase power factor improvement converter according to claim 1, characterized by the above.

3. At least two of a first capacitor having one end electrically connected to the first input terminal and the other end electrically connected to a first node, a second capacitor having one end electrically connected to the second input terminal and the other end electrically connected to the first node, and a third capacitor having one end electrically connected to the third input terminal and the other end electrically connected to the first node; a fourth capacitor having one end electrically connected to the first output terminal and the other end electrically connected to a second node; A fifth capacitor having one end electrically connected to the second node and the other end electrically connected to the second output terminal; An eighth capacitor having one end electrically connected to the first node and the other end electrically connected to the second node; comprising The three-phase power factor improvement converter according to claim 1, characterized in that.

4. The DC voltage is higher than the product of the effective value of the maximum line voltage of the three-phase AC voltage and the square root of 2. The three-phase power factor improvement converter according to claim 2 or 3, characterized in that.

5. The DC voltage is higher than the sum of the product of the effective value of the maximum line voltage of the three-phase AC voltage and the square root of 2 and the absolute value of the ripple voltage of the first capacitor, the second capacitor, and the third capacitor. The three-phase power factor improvement converter according to claim 4, characterized in that.

6. A first inductor having one end electrically connected to the first input terminal; A second inductor having one end electrically connected to the second input terminal; A third inductor having one end electrically connected to the third input terminal; A seventh diode having an anode electrically connected to the other end of the first inductor and a cathode electrically connected to the first output terminal; An eighth diode having an anode electrically connected to the other end of the second inductor and a cathode electrically connected to the first output terminal; A ninth diode having an anode electrically connected to the other end of the third inductor and a cathode electrically connected to the first output terminal; A tenth diode having an anode electrically connected to the second output terminal and a cathode electrically connected to the other end of the first inductor; An eleventh diode having an anode electrically connected to the second output terminal and a cathode electrically connected to the other end of the second inductor; A twelfth diode having an anode electrically connected to the second output terminal and a cathode electrically connected to the other end of the third inductor; A first bidirectional switch having one end electrically connected to the other end of the first inductor; A second bidirectional switch having one end electrically connected to the other end of the second inductor and the other end electrically connected to the other end of the first bidirectional switch; A third bidirectional switch having one end electrically connected to the other end of the third inductor and the other end electrically connected to the other end of the first bidirectional switch; comprising The three-phase power factor improvement converter according to claim 2 or 3, characterized in that.

7. The other ends of the first bidirectional switch, the second bidirectional switch, and the third bidirectional switch are electrically connected to the second node. The three-phase power factor improvement converter according to claim 6, characterized in that.

8. A sixth capacitor having one end electrically connected to the first output terminal and the other end electrically connected to the third node; A seventh capacitor having one end electrically connected to the third node and the other end electrically connected to the second output terminal; further comprising The other ends of the first bidirectional switch, the second bidirectional switch, and the third bidirectional switch are electrically connected to the third node. The three-phase power factor improvement converter according to claim 6, characterized in that.

9. A first inductor having one end electrically connected to the first input terminal; A second inductor having one end electrically connected to the second input terminal; A third inductor having one end electrically connected to the third input terminal; A first switching element having one end electrically connected to the other end of the first inductor and the other end electrically connected to the first output terminal; A second switching element having one end electrically connected to the second output terminal and the other end electrically connected to the other end of the first inductor; A third switching element having one end electrically connected to the other end of the second inductor and the other end electrically connected to the first output terminal; A fourth switching element having one end electrically connected to the second output terminal and the other end electrically connected to the other end of the second inductor; A fifth switching element having one end electrically connected to the other end of the third inductor and the other end electrically connected to the first output terminal; A sixth switching element having one end electrically connected to the second output terminal and the other end electrically connected to the other end of the third inductor; including The three-phase power factor improvement converter according to claim 2 or 3, characterized in that.

10. further comprising a ninth capacitor having one end electrically connected to the first output terminal and the other end electrically connected to the second output terminal. The three-phase power factor improvement converter according to claim 9, characterized in that.

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