Display driver and display device

Abstract

To provide a display driver and a display device, which are capable of suppressing the occurrence of noise and display failure.SOLUTION: First and second delay shift portions, each including first to (k / 2)-th delay elements, are provided. Each of the first and second delay shift portions shifts a start pulse signal toward its own first to (k / 2)-th delay elements in a first mode. In a second channel mode, one delay shift portion of the first and second delay shift portions shifts the start pulse signal from its r-th delay element to (k / 2)-th delay element, and the other delay shift portion shifts an output of a g-th delay element from the (k / 2)-th delay element to a (w+1)-th delay element in a reverse direction while shifting the start pulse signal from its j-th delay element to w-th delay element.SELECTED DRAWING: Figure 6B

Description

Technical Field

[0001] The present invention relates to a display driver and a display device that drive a display panel based on a video signal.

Background Art

[0002] Currently, as a liquid crystal or organic EL display device, a display panel in which display cells are formed at each intersection of a plurality of scanning lines and a plurality of signal lines (hereinafter referred to as data lines), and a data driver that drives the plurality of data lines of this display panel are generally known.

[0003] The data driver includes the following data latch section, level shifter section, DA (Digital to analog) conversion section, and output amplifier section.

[0004] The data latch section receives a series of pixel data pieces representing the luminance level of each pixel based on a video signal, and sequentially takes in each of them. Then, the data latch section outputs the plurality of captured pixel data pieces to the level shifter section every one horizontal scanning period. The level shifter section has a plurality of level shifters that individually receive the plurality of pixel data pieces and supply pixel data pieces with increased voltage levels to the DA conversion section. The DA conversion section converts each of the plurality of pixel data pieces with increased voltage levels into a gradation voltage having an analog voltage value, and supplies each of them to the output amplifier section. The output amplifier section amplifies the plurality of gradation voltages and supplies them to the plurality of data lines of the display panel.

[0005] By the way, in a conventional data driver, since the above-described data latch unit supplies a plurality of pixel data pieces to each of the level shifters simultaneously, each level shifter starts operating all at once according to the pixel data piece it has received. Therefore, since currents corresponding to the pixel data pieces flow simultaneously within each of the plurality of level shifters and the total current increases rapidly, noise generation and IR drop occur. When IR drop occurs, the logic level inversion operation becomes impossible within each level shifter and a through current starts to flow. This may cause further IR drop and lead to malfunction.

[0006] Therefore, as a data latch unit, a display driver has been proposed that reduces the number of simultaneously operating level shifters by forcibly shifting the output timing of each of a plurality of pixel data pieces (see, for example, Patent Document 1). The data latch unit described in Patent Document 1 takes in first to k-th pixel data pieces for k channels respectively corresponding to the first to k-th (k is an integer of 2 or more) source lines of the display panel, and outputs each of them in order with first to k-th output timing signals. For example, the data latch unit receives first to k-th output timing signals with the output timing delayed in the order of (first, k), (second, k - 1), (third, k - 2), ···, (w, w + 1) (w is an integer within the range of 2 to k - 1). Thereby, as shown in FIG. 1A, the data latch unit first outputs the first and k-th pixel data pieces, and subsequently outputs the first to k-th pixel data pieces in the order of the second to w-th pixel data pieces and the (k - 1)-th to (w + 1)-th pixel data pieces at a delayed timing (V shift mode).

[0007] Therefore, in the level shifter unit that receives the first to k-th pixel data pieces output from the data latch unit, the number of pixel data pieces received simultaneously becomes only two, and accordingly, the rapid increase in current is eliminated, so that noise generation and IR drop are suppressed.

Prior Art Documents

Patent Documents

[0008]

Patent Document 1

SUMMARY OF THE INVENTION

PROBLEMS TO BE SOLVED BY THE INVENTION

[0009] By the way, in recent years, display panels with different total numbers of data lines have been commercialized, and as data drivers, those capable of supporting various display panels with different total numbers of data lines are desired.

[0010] Therefore, in realizing such a data driver by the technique described in Patent Document 1, for example, it is considered to be capable of supporting both a display panel with a total of 960 data lines and a display panel with 780 data lines.

[0011] First, when driving a display panel with a total of 960 data lines, the data latch section of the data driver has the maximum output delay time at the w-th output channel in the central part among the first to k-th (k = 960) all output channels, and gradually shortens the output delay time toward the right and left output channels. At this time, the time difference between adjacent output channels is set to a predetermined fixed time.

[0012] On the other hand, when driving a display panel with a total of 780 data lines, the data latch section of the data driver sets 180 channels out of the first to 960 all output channels as unused channels. At this time, if 90 channels on the left end side (the first to 90th output channels) and 90 channels on the right end side (the 871st to 960th output channels) are equally set as unused channels, the delay time of each of the remaining 91st to 870th output channels can be set at the timing as shown in FIG. 1A.

[0013] However, in the specifications of currently commercialized display panels, the number of unused channels on each of the left end side and the right end side does not always match.

[0014] Therefore, when operating the data driver in the 780-channel mode, for example, if the number of unused channels on the left end side is smaller than the number of unused channels on the right end side, as shown in FIG. 1B, a time difference Td corresponding to the difference between the number of unused channels on the left end side and the number of unused channels on the right end side occurs between adjacent output channels in the central portion. At this time, as shown in FIG. 1B, if the time difference Td becomes significantly larger than the time difference between adjacent channels, there is a possibility that a display defect such as a vertical line being visually recognized at the boundary between the data lines of the display panel corresponding to a pair of adjacent output channels in the central portion may occur.

[0015] Therefore, an object of the present invention is to provide a display driver and a display device capable of suppressing the generation of noise and display defects.

Means for Solving the Problems

[0016] The display driver according to the present invention is a display driver having first to k-th (k is an integer of 2 or more) output channels that output a group of drive signals based on a video signal, and a channel mode designation signal for designating a first channel mode or a second channel mode, and in response to a start pulse signal composed of a single pulse, an output delay control circuit that generates first to k-th output timing signals respectively corresponding to the first to k-th output channels, and a data latch unit that takes in a series of pixel data pieces representing the luminance levels of the respective pixels based on the video signal and outputs each of the pixel data pieces at a timing corresponding to the first to k-th output timing signals, wherein the output delay control circuit has a first delay shift unit and a second delay shift unit each including first to (k / 2)-th delay elements, outputs of the first to (k / 2)-th delay elements included in the first delay shift unit become the first to (k / 2)-th output timing signals among the first to k-th output timings, outputs of the first to (k / 2)-th delay elements included in the second delay shift unit become the k-th to [(k / 2)+1]-th output timing signals among the first to k-th output timings, and each of the first and second delay shift units shifts the start pulse signal through each delay element from its first delay element to its (k / 2)-th delay element when the channel mode designation signal indicates the first channel mode, and when the channel mode designation signal indicates the second channel mode, one of the first and second delay shift units shifts the start pulse signal through each delay element from its r-th (r is an integer of 2 or more) delay element to its (k / 2)-th delay element among its first to (k / 2)-th delay elements, and the other of the first and second delay shift units shifts the start pulse signal through each delay element from its j-th (j is an integer of 2 or more) delay element to its w-th (w is an integer greater than j) delay element among its first to (k / 2)-th delay elements, and while shifting the signal output from its g-th (g is an integer greater than j and less than w) delay element in the reverse direction through each delay element from its (k / 2)-th delay element to its (w+1)-th delay element.

[0017] The display device according to the present invention includes a level shift unit that generates a plurality of pixel data pieces of high voltage by performing level shift processing on each of the plurality of pixel data pieces output from the data latch unit, a digital-to-analog conversion unit that obtains a plurality of gradation voltages by converting each of the plurality of pixel data pieces of high voltage into a gradation voltage having a voltage value corresponding to the luminance level indicated by the pixel data piece, and an output amplifier unit that outputs, as a plurality of drive signals, the amplified plurality of gradation voltages individually, and the above display driver, and a display panel including a plurality of data lines that receive the plurality of drive signals.

Effect of the Invention

[0018] According to the present invention, when outputting a series of a plurality of pixel data pieces captured by the data latch unit of the display driver at a timing in which the delay time is increased from the pixel data pieces at both ends toward the pixel data pieces at the central part, it is possible to suppress the time difference between adjacent pixel data pieces at the central part.

[0019] Thereby, by avoiding a sharp increase in the current flowing through the circuit in the subsequent stage of the data latch unit, generation of noise is suppressed, and even when the difference between the number of unused output channels on one end side and the number of unused output channels on the other end side is large, the time difference at the time of output between adjacent pixel data pieces at the central part can be suppressed, so that display defects can be prevented.

Brief Description of the Drawings

[0020]

Figure 1A

Figure 1B

Figure 2

Figure 3

Figure 4A

Figure 4B

Figure 5

Figure 6A

Figure 6B

Figure 6C

Figure 7

Figure 8A

Figure 8B

Embodiments for Carrying Out the Invention

[0021] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[0022] FIG. 2 is a block diagram showing the schematic configuration of a display device 200 including a display driver according to the present invention.

[0023] As shown in FIG. 2, the display device 200 includes a display panel 20, a display controller 11, scanning drivers 12_1 and 12_2, and a data driver 13 as a display driver.

[0024] The display panel 20 is composed of, for example, a liquid crystal or an organic EL panel, etc., and includes horizontal scanning lines S1 to Sm (m is an integer of 2 or more) that extend in the horizontal direction of the two-dimensional screen, and data lines D1 to Dn (n is an integer of 2 or more) that extend in the vertical direction of the two-dimensional screen. Display cells PC responsible for pixels are formed at each intersection of the horizontal scanning lines and the data lines.

[0025] The display controller 11 receives the video signal VS and supplies a scanning timing signal indicating the timing to sequentially select the horizontal scanning lines S1 to Sm according to the video signal VS to the scanning drivers 12_1 and 12_2.

[0026] Furthermore, the display controller 11 generates a video data signal VD including a series of pixel data pieces representing the luminance levels of each of the display cells PC responsible for pixels, together with control signals including a start signal STP, a channel mode designation signal CMA, a clock signal CLK, etc., based on the video signal VS. Note that the start signal STP is a single pulse signal synchronized with the horizontal scanning synchronization signal included in the video signal VS. The channel mode designation signal CMA is a signal that designates "n", which is the total number of the first to nth output channels corresponding to the data lines D1 to Dn of the display panel 20.

[0027] Note that in this embodiment, as the specification of the data driver 13, it is compatible with both a 960ch mode (the first channel mode) for driving the display panel 20 having 960 data lines and a 780ch mode (the second channel mode) for driving the display panel 20 having 780 data lines.

[0028] The display controller 11 supplies the data driver 13 with a channel mode designation signal CMA that designates one of the above-described 960ch mode and 780ch mode.

[0029] Note that the data driver 13 has the first to 960th output channels and uses all the first to 960th output channels in the 960ch mode.

[0030] On the other hand, in the 780ch mode, the data driver 13 sets 120 channels out of the first to 120th output channels and 60 channels out of the 901st to 960th output channels among the first to 960th output channels as unused channels.

[0031] Accordingly, when the display panel 20 has 960 data lines, output terminals respectively corresponding to the first to 960th output channels of the data driver 13 are connected to the data lines D1 to D960 of the display panel 20, and the data driver 13 is operated in the 960ch mode. On the other hand, when the display panel 20 has 780 data lines, 780-channel output terminals respectively corresponding to the 121st to 900th output channels of the data driver 13 are connected to the data lines D1 to D780 of the display panel 20.

[0032] The scanning driver 12_1 is connected to one end of each of the horizontal scanning lines S1 to Sm of the display panel 20, and the scanning driver 12_2 is connected to the other end of each of the horizontal scanning lines S1 to Sm of the display panel 20. The scanning drivers 12_1 and 12_2 sequentially apply horizontal scanning pulses to each of the horizontal scanning lines S1 to Sm of the display panel 20 according to the scanning timing signal supplied from the display controller 11.

[0033] The data driver 13 converts each of n pixel data pieces in a series of pixel data pieces included in the video data signal VD into an analog voltage having a magnitude corresponding to the luminance level indicated by the pixel data piece for every n pixel data pieces in accordance with the control signals (STP, CLK, CMA) supplied from the display controller 11. Then, the data driver 13 outputs the n voltages obtained by converting the n pixel data pieces into analog voltages respectively as drive signals G1 to Gn indicating the voltages, and supplies each of them to the data lines D1 to Dn of the display panel 20. As described above, in this embodiment, the above-mentioned "n" is 960 or 780.

[0034] FIG. 3 is a block diagram showing the internal configuration of the data driver 13.

[0035] The data driver 13 is formed on a single or a plurality of semiconductor IC (Integrated Circuit) chips.

[0036] As shown in FIG. 3, it includes a shift register 131, a first data latch section 132, a delay control circuit 133, a second data latch section 134, a level shift section 135, a DA (digital to analog) conversion section 136, and an output amplifier section 137.

[0037] The shift register 131 receives a start signal ST and a clock signal CLK, and generates latch timing signals t1 to t960 with different timings by shifting the start signal ST composed of a single pulse according to the clock signal CLK. The shift register 131 supplies the latch timing signals t1 to t960 to the first data latch section 132.

[0038] The first data latch section 132 receives a series of pixel data pieces included in the video data signal VD, captures each pixel data piece at the timing of the latch timing signals t1 to t960, and supplies the captured 960 pixel data pieces as pixel data P1 to P960 to the second data latch section 134.

[0039] The delay control circuit 133 receives the start signal ST and the channel mode designation signal CMA.

[0040] When the channel mode designation signal CMA indicates the 960ch mode, the delay control circuit 133 generates output timing signals e1 to e480 in which a single pulse signal appears after a delay that increases step by step by a predetermined time dZ according to the start signal ST, as shown in FIG. 4A. Further, at this time, the delay control circuit 133 generates output timing signals e960 to e481 in which a single pulse signal appears after a delay that increases step by step by a predetermined time dZ according to the start signal ST, as shown in FIG. 4A.

[0041] On the other hand, when the channel mode designation signal CMA indicates the 780ch mode, the delay control circuit 133 generates output timing signals e121 to e510 in which a single pulse signal appears after delays that increase stepwise by a predetermined time dZ in accordance with the start signal ST, as shown in FIG. 4B. Further, at this time, the delay control circuit 133 generates output timing signals e900 to e511 in which a single pulse signal appears after delays that increase stepwise by a predetermined time dZ in accordance with the start signal ST, as shown in FIG. 4B.

[0042] Note that in the 780ch mode, each of the output timing signals e1 to e120 and e901 to e960 becomes a fixed level at which no pulse appears.

[0043] The delay control circuit 133 supplies the output timing signals e1 to e960 generated as described above to the second data latch section 134.

[0044] The second data latch section 134 takes in the pixel data P1 to P960 supplied from the first data latch section 132, and outputs them as pixel data Q1 to Q960 to the level shift section 135 at timing according to the output timing signals e1 to e960.

[0045] That is, for example, the second data latch section 134 outputs the captured pixel data P1 as pixel data Q1 at the rising edge timing of the output timing signal e1 shown in FIG. 4A. Further, the second data latch section 134 outputs the captured pixel data P2 as pixel data Q2 at the rising edge timing of the output timing signal e2 shown in FIG. 4A. In this way, the second data latch section 134 outputs the captured pixel data Pi (i is an integer from 1 to 960) as pixel data Qi at the rising edge timing of the output timing signal ei.

[0046] The level shift unit 135 performs a level shift process that increases the amplitude of the signal representing each bit of the pixel data Q1 to Q960, and supplies the pixel data signals L1 to L960 at a high voltage, which are the results of the level shift process for each pixel data, to the DA conversion unit 136.

[0047] The DA conversion unit 136 converts each of the pixel data signals L1 to L960 into a gradation voltage having an analog voltage value corresponding to the luminance level represented by the pixel data signal, and supplies each of them as gradation voltages V1 to V960 to the output amplifier unit 137.

[0048] The output amplifier unit 137 outputs, as drive signals G1 to Gn, the individually amplified gradation voltages V1 to V960.

[0049] FIG. 5 is a block diagram showing the internal configuration of the delay control circuit 133.

[0050] As shown in FIG. 5, the delay control circuit 133 includes a start pulse output circuit 1331, a channel mode selection circuit 1332, a first delay shift unit 1333, and a second delay shift unit 1334.

[0051] The start pulse output circuit 1331 supplies a start pulse signal LOAD, which is a single pulse of logic level 1, to the first delay shift unit 1333 and the second delay shift unit 1334 in response to the above-described start signal ST.

[0052] The channel mode selection circuit 1332 receives the channel mode designation signal CMA. When the channel mode designation signal CMA indicates the 960ch mode, the channel mode selection circuit 1332 supplies the channel mode signal m960 of logic level 1 indicating the 960ch mode and the channel mode signal m780 of logic level 0 to the first delay shift section 1333 and the second delay shift section 1334. On the other hand, when the channel mode designation signal CMA indicates the 780ch mode, the channel mode selection circuit 1332 supplies the channel mode signal m960 of logic level 0 and the channel mode signal m780 of logic level 1 indicating the 780ch mode to the first delay shift section 1333 and the second delay shift section 1334.

[0053] When the channel mode designation signal CMA indicates the 960ch mode, the first delay shift section 1333 generates output timing signals e1 to e480 shown in FIG. 4A in response to the start pulse signal LOAD. On the other hand, when the channel mode designation signal CMA indicates the 780ch mode, the first delay shift section 1333 generates output timing signals e121 to e480 shown in FIG. 4B.

[0054] When the channel mode designation signal CMA indicates the 960ch mode, the second delay shift section 1334 generates output timing signals e481 to e960 shown in FIG. 4A in response to the start pulse signal LOAD. On the other hand, when the channel mode designation signal CMA indicates the 780ch mode, the second delay shift section 1334 generates output timing signals e481 to e900 shown in FIG. 4B.

[0055] FIG. 6A is a circuit diagram showing the internal configuration of the first delay shift section 1333.

[0056] As shown in FIG. 6A, the first delay shift section 1333 includes delay elements A1 to A480 that, together with the AND gate AN1 and the selector SE1, each delay the signal input to itself by a predetermined time dZ and output it to the next stage.

[0057] The AND gate AN1 inputs the start pulse signal LOAD of a single pulse to the delay element A1 only when receiving the channel mode signal m960 of logic level 1.

[0058] The delay element A1 delays the start pulse signal LOAD by a predetermined time dZ and outputs it to the next-stage delay element B2. The delay element B2 delays the start pulse signal LOAD supplied from the previous-stage delay element A1 by a predetermined time dZ and outputs it to the next-stage delay element A3. Similarly, the delay element Ax (x is an integer from 3 to 119) delays the start pulse signal LOAD supplied from the previous-stage delay element A(x - 1) by a predetermined time dZ and outputs it to the next-stage delay element A(x + 1). That is, the delay elements A1 to A120 shift the start pulse signal LOAD received by the delay element A1 from the delay element A1 to the delay element A120 via each delay element (A2 to A119). At this time, the delay elements A1 to A120 output the signals output from each of the delay elements A1 to A120 as output timing signals e1 to e120. The selector SE1 receives the channel mode signal m780, the start pulse signal LOAD, and the output timing signal e120.

[0059] When the channel mode signal m780 is at the logic level 1 indicating the 780ch mode, the selector SE1 inputs the start pulse signal LOAD to the delay element A121. On the other hand, when the channel mode signal m780 is at the logic level 0, that is, indicating the 960ch mode, the selector SE1 inputs the output timing signal e120 to the delay element A121.

[0060] The delay element A121 delays the start pulse signal LOAD or the output timing signal e120 by a predetermined time dZ and outputs it to the next-stage delay element A121. The delay element A122 delays the signal supplied from the previous-stage delay element A121 by a predetermined time dZ and outputs it to the next-stage delay element A123. Similarly, the delay element Ax (x is an integer from 123 to 479) delays the signal supplied from the previous-stage delay element A(x - 1) by a predetermined time dZ and outputs it to the next-stage delay element A(x + 1). That is, the delay elements A121 to A480 shift the signal received by the delay element A121 from the delay element A121 toward the delay element A480 via each delay element (A122 to A479). At this time, the delay elements A121 to A480 output the signals output from the respective delay elements A121 to A480 as output timing signals e121 to e480.

[0061] FIG. 6B is a circuit diagram showing the internal configuration of the second delay shift unit 1334.

[0062] As shown in FIG. 6B, the second delay shift unit 1334 includes delay elements B1 to B480 that delay the signals input to themselves by a predetermined time dZ and output them to the next stage, together with an AND gate AN2, a selector SE2, and a bidirectional shift circuit RSB.

[0063] The AND gate AN2 inputs the single-pulse start pulse signal LOAD to the delay element B1 only when it receives the channel mode signal m960 of logic level 1.

[0064] The delay element B1 delays the start pulse signal LOAD by a predetermined time dZ and outputs it to the next-stage delay element B2. The delay element B2 delays the start pulse signal LOAD supplied from the previous-stage delay element B1 by a predetermined time dZ and outputs it to the next-stage delay element B3. Similarly, the delay element Bx (x is an integer from 3 to 59) delays the start pulse signal LOAD supplied from the previous-stage delay element B(x - 1) by a predetermined time dZ and outputs it to the next-stage delay element B(x + 1). That is, the delay elements B1 to B60 shift the start pulse signal LOAD received by the delay element B1 from the delay element B1 to the delay element B60 through each delay element (B2 to B59). At this time, the delay elements B1 to B60 output the signals output from each of the delay elements B1 to B60 as output timing signals e960 to e901. The selector SE2 receives the channel mode signal m780, the start pulse signal LOAD, and the output timing signal e901.

[0065] When the channel mode signal m780 is at the logic level 1 indicating the 780ch mode, the selector SE2 inputs the start pulse signal LOAD to the delay element B61. On the other hand, when the channel mode signal m780 is at the logic level 0, that is, indicating the 960ch mode, the selector SE2 inputs the output timing signal e901 to the delay element B61.

[0066] The delay element B61 delays the start pulse signal LOAD or the output timing signal e901 by a predetermined time dZ and outputs it to the next-stage delay element B62. The delay element B62 delays the signal supplied from the previous-stage delay element B61 by a predetermined time dZ and outputs it to the next-stage delay element B63. Similarly, the delay element Bx (x is an integer from 63 to 450) delays the signal supplied from the previous-stage delay element B(x - 1) by a predetermined time dZ and outputs it to the next-stage delay element B(x + 1). That is, the delay elements B61 to B450 shift the signal received by the delay element B61 from the delay element B61 toward the delay element B450 via each delay element (B62 to B449). At this time, the delay elements B61 to B450 output the signals output from each of the delay elements B61 to B450 as output timing signals e900 to e511.

[0067] Here, as shown in FIG. 6B, the output timing signal e541 output from the delay element B420 and the output timing signal e511 output from the delay element B450 are supplied to the bidirectional shift circuit RSB.

[0068] The bidirectional shift circuit RSB receives the channel mode signal m780 together with the output timing signals e511 and e541 described above.

[0069] FIG. 6C is a circuit diagram showing an example of the internal configuration of the bidirectional shift circuit RSB.

[0070] As shown in FIG. 6C, the bidirectional shift circuit RSB includes selectors SL451 to SL480 and delay elements B451 to B480 that each delay the signal input to itself by a predetermined time dZ and output it to the next stage.

[0071] The delay elements B451 to B480 are connected in series via the selectors SL provided in the previous stage of each. The signals output from each of the delay elements B451 to B480 are output as output timing signals e510 to e481.

[0072] Selector SL451 selects one of the output timing signals e511 output from delay element B450 shown in FIG. 6B and the output timing signal e509 output from delay element B452 based on the channel mode signal m780, and supplies this to delay element B451. That is, when the channel mode signal m780 is at the logical level 1 indicating the 780ch mode, selector SL451 selects the output timing signal e509 and supplies this to delay element B451. On the other hand, when the channel mode signal m780 is at the logical level 0, selector SL451 selects the output timing signal e511 and supplies this to delay element B451.

[0073] Delay element B451 outputs, as output timing signal e510, the supplied output timing signal e509 or e511 delayed by the predetermined time dZ described above, and supplies this to selector SL452.

[0074] Selector SL452 selects one of the output timing signal e510 and the output timing signal e508 output from delay element B453 based on the channel mode signal m780, and supplies this to delay element B452. That is, when the channel mode signal m780 is at the logical level 1 indicating the 780ch mode, selector SL452 selects the output timing signal e508 and supplies this to delay element B452. On the other hand, when the channel mode signal m780 is at the logical level 0, selector SL452 selects the output timing signal e510 and supplies this to delay element B452.

[0075] Delay element B452 outputs, as output timing signal e509, the supplied output timing signal e510 or e508 delayed by the predetermined time dZ described above, and supplies this to selectors SL451 and SL453.

[0076] Similarly, selector SLx (x is an integer from 453 to 480) selects one of the signal output from delay element B(x + 1) and the signal output from delay element DF(x - 1) based on channel mode signal m780, and supplies this to delay element Bx. Delay element Bx outputs the supplied signal after delaying it by a predetermined time dZ, and supplies this to selectors SL(x + 1) and SL(x - 1).

[0077] Here, selector SL480 selects one of the output timing signal e482 output from delay element B479 and the output timing signal e541 output from delay element B420 shown in FIG. 6B based on channel mode signal m780, and supplies this to delay element B480. That is, when channel mode signal m780 indicates a logical level 1 of the 780ch mode, selector SL480 selects output timing signal e541 and supplies this to delay element B480. On the other hand, when channel mode signal m780 is at a logical level 0, selector SL30 selects output timing signal e482 and supplies this to delay element B480.

[0078] Delay element B480 outputs the supplied output timing signal e541 or e482 after delaying it by a predetermined time dZ as output timing signal e481, and supplies this to selector SL479.

[0079] With the configuration shown in FIG. 6C, when channel mode signal m780 indicates a logical level 0, that is, in the 960ch mode, bidirectional shift circuit RSB shifts the output timing signal e511 output from delay element B450 shown in FIG. 6B from delay element B451 toward the final stage delay element B480 through each delay element (B452 to B479). On the other hand, when channel mode signal m780 indicates a logical level 1, that is, in the 780ch mode, bidirectional shift circuit RSB shifts the output timing signal e541 output from delay element B420 shown in FIG. 6B in the reverse direction from the final stage delay element B480 toward delay element B451 through each delay element (B479 to B452).

[0080] The bidirectional shift circuit RSB outputs, as output timing signals e510 to e481, the signals output from each of the delay elements B451 to B480 by the above-described shift or reverse shift.

[0081] Each of the delay elements A1 to A480 and B1 to B480 shown in FIGS. 6A to 6C is composed of inverter elements IV connected in series, as shown in FIG. 7, for example.

[0082] The operation of the delay control circuit 133 having the configuration shown in FIG. 5 will be described below separately for the 960ch mode and the 780ch mode. [960ch mode] FIG. 8A is a diagram showing an equivalent circuit of each of the first delay shift section 1333 and the second delay shift section 1334 in the 960ch mode.

[0083] As shown in FIG. 8A, in the 960ch mode, the start pulse signal LOAD is input to the delay element A1 of the first delay shift section 1333 and the delay element B1 of the second delay shift section 1334, respectively.

[0084] The first delay shift section 1333 shifts the start pulse signal LOAD from the delay element A1 toward the delay element A480 via each delay element (A2 to A479), and at this time, outputs the signals output from each of the delay elements A1 to A480 as output timing signals e1 to e480.

[0085] Also, in the 960ch mode, the output of the delay element B450 of the second delay shift unit 1334 is connected to the input of the delay element B451 of the bidirectional shift circuit RSB. At this time, the bidirectional shift circuit RSB shifts the signal input to the delay element B451 from the delay element B451 toward the delay element B480 through each delay element (B452 to B479). Therefore, in the 960ch mode, the second delay shift unit 1334 shifts the start pulse signal LOAD from the delay element B1 toward the delay element B480 through each delay element (B2 to B479), and at this time, outputs the signals output from each of the delay elements B1 to B480 as output timing signals e960 to e481. [780ch mode] FIG. 8B is a diagram showing equivalent circuits of the first delay shift unit 1333 and the second delay shift unit 1334 in the 780ch mode.

[0086] In addition, as described above in this embodiment, in the 780ch mode, among all 960 channels, the first to 120th output channels on one end side are the first unused channels, and the 901st to 960th output channels on the other end side are the second unused channels. Therefore, as shown in FIG. 8B, the output timing signals e1 to e120 output from each of the delay elements A1 to A120 of the first delay shift unit 1333 and the output timing signals e960 to e901 output from each of the delay elements B1 to B60 of the second delay shift unit 1334 become unused.

[0087] As a result, in the 780ch mode, the first delay shift unit 1333 receives the start pulse signal LOAD by the delay element A121, and shifts this from the delay element A121 toward the delay element A480 through each delay element (A122 to A479). At this time, the first delay shift unit 1333 outputs the signals output from each of the delay elements A121 to A480 as output timing signals e121 to e480.

[0088] Also, in the 780ch mode, the connection between the delay element B450 of the second delay shift unit 1334 and the delay element B450 of the bidirectional shift circuit RSB is cut off. The second delay shift unit 1334 receives the start pulse signal LOAD by the delay element B61, and shifts it from the delay element B61 toward the delay element B450 through each delay element (B62 to B449). At this time, the second delay shift unit 1334 outputs the signals output from each of the delay elements B61 to B450 as output timing signals e960 to e511, and inputs the output timing signal e541 output from the delay element B420 to the delay element B480 of the bidirectional shift circuit RSB. The bidirectional shift circuit RSB shifts the signal input to the delay element B480 in the reverse direction from the delay element B480 toward the delay element B451 through each delay element (B479 to B452). At this time, the second delay shift unit 1334 outputs the signals output from each of the delay elements B480 to B451 of the bidirectional shift circuit RSB as output timing signals e481 to e510.

[0089] In this way, by adopting the configuration shown in FIG. 5 as the delay control circuit 133, even if the number of unused output channels (60, 120) on each of one end side and the other end side of the data driver 13 is different, as shown in FIG. 4B, all the time differences between adjacent ones in the output timing signals e121 to e900 can be made a predetermined time dZ.

[0090] Thereby, because the number of unused output channels on one end side and the number of unused output channels on the other end side are different, as shown in FIG. 1B, a state in which the time difference Td between adjacent output channels in the central part becomes larger than the time difference (dZ) between other adjacent output channels is avoided, and it becomes possible to prevent display defects associated with such a state.

[0091] Therefore, according to the data driver 13 including the delay control circuit 133 having the configuration shown in FIG. 5, it is possible to prevent the generation of noise accompanying a steep current increase and suppress display defects caused by a large time difference between adjacent output channels.

[0092] Furthermore, in the above embodiment, in the 780cH mode, the unused channels on one end side of the first to 960th output channels are described as 120 channels from the first to 120th channels, and the unused channels on the other end side are described as 60 channels from the 901st to 960th channels. However, the number of unused channels is not limited to the above numbers.

[0093] Also, in the above embodiment, among the first to 480th output channels (referred to as the first output channel group) and the 481st to 960th output channels (referred to as the second output channel group) obtained by dividing all the output channels into two, the first output channel group has a larger number of unused channels. Therefore, in the above-described embodiment, as the second delay shift unit 1334 responsible for the delay control of the second output channel group, a configuration including the bidirectional shift circuit RSB as shown in FIG. 6B is adopted. However, when the second output channel group has a larger number of unused channels, a configuration including the bidirectional shift circuit RSB as shown in FIG. 6B may be adopted for the first delay shift unit 1333, and the configuration shown in FIG. 6A may be adopted for the second delay shift unit 1334.

[0094] That is, the configuration of FIG. 6A may be adopted as one of the delay shift units of the first delay shift unit 1333 and the second delay shift unit 1334, and the configuration of FIG. 6B may be adopted as the other delay shift unit.

[0095] Further, in the above embodiment, as shown in FIG. 4B, in the 780cH mode, in order to make the time difference between the output timing signal e510 with the maximum delay time and the adjacent output timing signals e509 and e511 the same as the time difference (dZ) between other adjacent output timing signals, the connection form shown in FIG. 6B is adopted as the second delay shift unit 1334. That is, the difference (60) between the unused channels for 120 channels of the first output channel group and the unused channels for 60 channels of the second output channel group is used to supply the output of the delay element B420 before the final-stage delay element B480 to the final-stage delay element B480. Then, the output of this delay element B420 is shifted in the reverse direction from the delay element B480 to the delay element B451 adjacent to the delay element B450 before the delay element B480 by the number of stages that is half of the difference.

[0096] However, regarding the time difference between the output timing signal with the maximum delay time and the adjacent output timing signal, it is not necessarily required to be equal to the time difference (dZ) between other adjacent output timing signals. That is, as long as the time difference is suppressed to a level where display defects do not occur, the delay elements that are the starting points of the operation as described above are not limited to B420, B450, and B451.

[0097] Also, in the above embodiment, the configuration and operation of the data driver 13 are described as being capable of facing the display panel 20 with 960 or 780 data lines, but the number of data lines that can be supported, that is, the number of output channels of the data driver 13, is not limited to 960 or 780.

[0098] In short, as the display driver (13) having the first to kth (k is an integer of 2 or more) output channels (for example, 960 channels) for outputting the drive signal (G) based on the video signal (VD) to the display panel (20), it may include the following output delay control circuit that controls the output timing of the data latch unit (134).

[0099] The output delay control circuit (133) receives a channel mode designation signal (CMA) designating a first channel mode (e.g., 960cH mode) or a second channel mode (e.g., 780cH mode) and a start pulse signal (LOAD) consisting of a single pulse.

[0100] The output delay control circuit (133) has first and second delay shift sections each including delay elements 1 to (k / 2), and generates first to k output timing signals (e.g., e1 to e960) corresponding to the first to k output channels according to the above-described channel mode designation signal and start pulse signal. In the output delay control circuit, the outputs of the delay elements 1 to (k / 2) (e.g., A1 to A480) included in the first delay shift section (1333) become the first to (k / 2) output timing signals (e.g., e1 to e480) among the first to k output timings. Also, the outputs of the delay elements 1 to (k / 2) (e.g., B1 to B480) included in the second delay shift section (1334) become the k to [(k / 2)+1] output timing signals (e.g., e960 to e481) among the first to k output timings.

[0101] Here, when the channel mode designation signal (CMA) indicates the first channel mode, each of the first and second delay shift sections shifts the start pulse signal (LOAD) through the respective delay elements from the first delay element (A1, B1) to the (k / 2) - th delay element (A480, B480).

[0102] On the other hand, when the channel mode designation signal indicates the second channel mode, one of the first and second delay shift units (1333 or 1334) shifts the start pulse signal (LOAD) from the r-th (r is an integer of 2 or more) delay element (for example, A121 or B121) to the (k / 2)-th delay element (for example, A480 or B480) among its own first to (k / 2) delay elements (A1 to A480 or B1 to B480) through each delay element in the direction from the r-th delay element to the (k / 2)-th delay element. The other delay shift unit (1334 or 1333) among the first and second delay shift units shifts the start pulse signal from the j-th (j is an integer of 2 or more) delay element (for example, B61 or A61) to the w-th (w is an integer greater than j) delay element (for example, B450 or A450) among its own first to (k / 2) delay elements through each delay element while shifting the signal output from the g-th (g is an integer greater than j and less than w) delay element (for example, B420 or A420) in the reverse direction from the (k / 2)-th delay element (for example, B480 or A480) to the (w + 1)-th delay element (for example, B451 or A451) through each delay element.

[0103] Here, when the channel mode designation signal (CMA) indicates the second channel mode (for example, 780cH mode), the first to (r - 1)-th output channels (for example, the first to 120-th output channels) among the first to k-th output channels (for example, the first to 960-th output channels) are set as the first unused channels, and the (j + 1)-th to k-th channels (for example, the 901-th to 960-th output channels) are set as the second unused channels. At this time, the above-mentioned g-th delay element is set as a delay element (for example, B420) before the (k / 2) delay elements (for example, B480) by the number of the difference between the number of the first unused channels and the number of the second unused channels. Further, the w-th delay element is set as a delay element (for example, B450) before the (k / 2) delay elements by half the number of the above-mentioned difference.

[0104] As a result, regardless of the difference between the number of the above-described first unused channels and the number of the second unused channels, the difference in delay time between the output timing signal with the maximum delay time (e.g., e510 shown in FIG. 4B) and the output timing signal adjacent thereto can be made the same predetermined time dZ as the difference in delay time between other adjacent output timing signals.

Explanation of Signs

[0105] 13 Data driver 133 Delay control circuit 1333 First delay shift section 1334 Second delay shift section A1~A480, B1~B480 Delay elements SE1, SE2 Selectors RSG Bidirectional shift circuit

Claims

1. A display driver having first to k-th (k is an integer of 2 or more) output channels for outputting a group of drive signals based on a video signal to a display panel, an output delay control circuit that generates first to k-th output timing signals respectively corresponding to the first to k-th output channels in response to a channel mode designation signal for designating a first channel mode or a second channel mode and a start pulse signal composed of a single pulse, a data latch unit that takes in a series of pixel data pieces representing the luminance levels of respective pixels based on the video signal and outputs each of the pixel data pieces at a timing corresponding to the first to k-th output timing signals, and includes, the output delay control circuit has a first delay shift unit and a second delay shift unit each including first to (k / 2)-th delay elements, outputs of the first to (k / 2)-th delay elements included in the first delay shift unit become the first to (k / 2)-th output timing signals among the first to k-th output timings, and outputs of the first to (k / 2)-th delay elements included in the second delay shift unit become the k-th to [(k / 2)+1]-th output timing signals among the first to k-th output timings, each of the first and second delay shift units, when the channel mode designation signal indicates the first channel mode, shifts the start pulse signal from its first delay element to the (k / 2)-th delay element through each delay element, when the channel mode designation signal indicates the second channel mode, one of the first and second delay shift units shifts the start pulse signal from the r-th (r is an integer of 2 or more) delay element among its first to (k / 2)-th delay elements to the (k / 2)-th delay element through each delay element, and the other of the first and second delay shift units shifts the start pulse signal from the j-th (j is an integer of 2 or more) delay element among its first to (k / 2)-th delay elements to the w-th (w is an integer greater than j) delay element through each delay element while shifting the signal output from the g-th (g is an integer greater than j and less than w) delay element in the reverse direction from the (k / 2)-th delay element to the (w + 1)-th delay element through each delay element. A display driver characterized by this.

2. When the channel mode designation signal indicates the second channel mode, the first to (r - 1) output channels among the first to k output channels are the first unused channels, and the (j + 1) to k channels are the second unused channels. The g-th delay element is a delay element before the (k / 2) delay elements by the number of the difference between the number of the first unused channels and the number of the second unused channels. The display driver according to claim 1, wherein the w-th delay element is a delay element before the (k / 2) delay elements by half the number of the difference.

3. When the number of the first unused channels is larger than the number of the second unused channels, the first delay shift section is the one delay shift section, and the second delay shift section is the other delay shift section. The display driver according to claim 2, wherein when the number of the first unused channels is smaller than the number of the second unused channels, the second delay shift section is the one delay shift section, and the first delay shift section is the other delay shift section.

4. The display driver according to any one of claims 1 to 3, wherein each of the first to (k / 2) delay elements included in each of the first delay shift section and the second delay shift section is composed of a plurality of inverter elements connected in series.

5. A level shift section that generates a plurality of high-voltage pixel data pieces by performing a level shift process on each of the plurality of pixel data pieces output from the data latch section; A digital-to-analog conversion section that obtains a plurality of gradation voltages by converting each of the plurality of high-voltage pixel data pieces into a gradation voltage having a voltage value corresponding to the luminance level indicated by the pixel data piece; The display driver according to any one of claims 1 to 3, further comprising an output amplifier section that outputs, as a plurality of drive signals, the amplified plurality of gradation voltages individually.

6. A display driver according to claim 5; A display device, comprising: a display panel including a plurality of data lines that receive the plurality of drive signals.

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