Display control device

Abstract

To provide a display control device that removes noise superimposed on data needed for display.SOLUTION: Provided is a display control device for controlling a drive circuit for display panels. The display control device comprises: a first monitoring unit that monitors occurrence of abnormality of a vertical sync signal by using a data enable signal and an image signal, and outputs a first abnormality detection signal when abnormality of the vertical sync signal is detected; a second monitoring unit that monitors occurrence of abnormality of a horizontal sync signal by using the data enable signal and the image signal, and outputs a second abnormality detection signal when abnormality of the horizontal sync signal is detected; and a third monitoring unit that monitors occurrence of abnormality of the image signal by using the data enable signal and outputs a third abnormality detection signal when abnormality of the image signal is detected, and does not output the data enable signal and the image signal when the first abnormality detection signal or the second abnormality detection signal is outputted.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] The present disclosure relates to a display control device.

Background Art

[0002] When a display device performs display based on data, transmission and reception of data and switching of scanning lines are performed based on a synchronization signal. Since the synchronization signal is an important signal when performing display, when the waveform of the synchronization signal becomes a waveform that does not satisfy the specifications (conditions), abnormal display may be performed. Therefore, for example, as disclosed in Patent Document 1, there is a technique aimed at removing noise superimposed on the synchronization signal so that a correct image is displayed.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in addition to the synchronization signal, there is also data necessary for display in the display device, and noise may be superimposed on such data. Therefore, it is required to remove noise superimposed on the data necessary for display including the synchronization signal.

[0005] The present disclosure has been made in view of the above points, and an object thereof is to provide a display control device that removes noise superimposed on data necessary for display.

Means for Solving the Problems

[0006] According to an aspect of the present disclosure, there is provided a display control device for controlling a driving circuit for a display panel, including: a first monitoring unit that monitors the occurrence of an abnormality in a vertical synchronization signal using a data enable signal and an image signal, and outputs a first abnormality detection signal when an abnormality in the vertical synchronization signal is detected; a second monitoring unit that monitors the occurrence of an abnormality in a horizontal synchronization signal using the data enable signal and the image signal, and outputs a second abnormality detection signal when an abnormality in the horizontal synchronization signal is detected; and a third monitoring unit that monitors the occurrence of an abnormality in the image signal using the data enable signal, outputs a third abnormality detection signal when an abnormality in the image signal is detected, and does not output the data enable signal and the image signal when the first abnormality detection signal or the second abnormality detection signal is being output.

[0007] The first monitoring unit may output a first abnormality detection signal when the data enable signal and the image signal are in a high state during a period from the rise to the fall of the vertical synchronization signal.

[0008] The second monitoring unit may output a second abnormality detection signal when the data enable signal and the image signal are in a high state during a period from the rise to the fall of the horizontal synchronization signal.

[0009] When at least any one of the first abnormality detection signal, the second abnormality detection signal, or the third abnormality detection signal is being output, the display control device may further include an abnormality detection unit that causes the driving circuit to maintain the previous display state on the display panel.

[0010] The display control device may further include a conversion unit that converts a serial video signal into the vertical synchronization signal, the horizontal synchronization signal, the data enable signal, and the image signal.

[0011] The serial video signal may be a low voltage differential signal.

[0012] According to an aspect of the present disclosure, there is provided a display control device for controlling a driving circuit for a display panel, including: a vertical synchronization signal monitoring unit that ignores the rising and falling edges of the vertical synchronization signal until a predetermined number of rising and falling edges of the horizontal synchronization signal are detected after detecting the rising and falling edges of the vertical synchronization signal; and an abnormality detection unit that counts the rising and falling edges of the vertical synchronization signal from the falling edge to the rising edge of the horizontal synchronization signal and outputs an abnormality detection signal when the counted value is different from a set value.

Brief Description of the Drawings

[0013]

Figure 1A

Figure 1B

Figure 2A

Figure 2B

Figure 3A

Figure 3B

Figure 4

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Figure 6

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Figure 8A

Figure 8B

Embodiments for Carrying Out the Invention

[0014] Hereinafter, an example of an embodiment of the present disclosure will be described with reference to the drawings. In each drawing, the same or equivalent components and parts are given the same reference numerals. Also, the dimensional ratios in the drawings are exaggerated for the convenience of explanation and may be different from the actual ratios.

[0015] First, before describing an example of an embodiment of the present disclosure, the background leading to the embodiment of the present disclosure will be described.

[0016] Due to the increasing tolerance requirements such as for EMS (Electro Magnetic Susceptibility), noise countermeasures in display devices have become important. On the other hand, due to factors such as the increase in the size of the display panel used in the display device, the lengthening and complication of wiring by using a plurality of chips, the noise tolerance of the display device is rather deteriorating. Even if the video signal is disturbed by noise, the display device needs to continue normal display by detecting the noise on the driver side and processing the noise.

[0017] When noise is applied to the Lvds signal wiring in an EMS test or the like, the driver side may misdetect the synchronization signal or the RGB signal, and the video displayed on the display panel will be disturbed. FIG. 1A is a diagram showing an example of a correct synchronization signal, and FIG. 1B is a diagram showing an example of the video displayed on the display panel 1 when the correct synchronization signal is correctly received by the source drivers 2A, 2B and the gate driver 3. In FIG. 1, a grayscale display that becomes darker line by line from the top to the bottom of the panel 1 is displayed in 4 lines per frame. The RGB output per line is constant.

[0018] However, when noise is superimposed on the horizontal synchronization signal or the vertical synchronization signal, causing the signal to rise and fall at timings different from the original pattern, the driver side may misdetect the synchronization signal. FIG. 2A is a diagram showing an example of a state where noise due to disturbance is superimposed on the vertical synchronization signal, and FIG. 2B shows an example of an image displayed on the display panel 1 when noise is superimposed on the vertical synchronization signal. As shown in FIG. 2B, when noise is superimposed on the vertical synchronization signal received by the source driver 2A during the display of the second line, the source driver 2A misdetects that the frame ends at that line. On the display panel 1, the data that should originally be displayed on the first line is displayed on the third line.

[0019] FIG. 3A is a diagram showing an example of a state where noise due to disturbance is superimposed on the horizontal synchronization signal, and FIG. 3B shows an example of an image displayed on the display panel 1 when noise is superimposed on the horizontal synchronization signal. As shown in FIG. 3B, when noise is superimposed on the horizontal synchronization signal received by the source driver 2A during the display of the second line, the source driver 2A misdetects that the line ends in the middle of that line. On the display panel 1, a part of the signal of the second line is output to the third line, the signal of the first line is output to the second and third lines after the misdetection, and the signal of the third line is output to the fourth line.

[0020] Thus, when noise is superimposed on the synchronization signal or the video signal, it is required to avoid the image displayed on the display panel 1 from being disturbed. Therefore, in the present embodiment, a display control device for avoiding the image displayed on the display panel 1 from being disturbed when noise is superimposed on the synchronization signal or the video signal will be described.

[0021] FIG. 4 is a diagram showing a schematic configuration of a display device according to the present embodiment. The display device shown in FIG. 4 includes a display panel 1, source drivers 2A and 2B, and a gate driver 3. The display panel 1 is a liquid crystal display panel, and a TFT (Thin Film Transistor) is provided for each pixel. The source drivers 2A and 2B are supplied with 4-channel Lvds signals 1 to 4, an Lvds clock, various signals and power for display. The source drivers 2A and 2B are drivers for driving the sources of the respective pixels of the display panel 1. The source driver 2A is a driver for controlling the display of the left half of the display panel 1, and the source driver 2B is a driver for controlling the display of the right half of the display panel 1. The gate driver 3 is a driver for driving the gates of the respective pixels of the display panel 1. The source drivers 2A and 2B and the gate driver 3 are an example of the drive circuit of the present disclosure.

[0022] FIG. 5 is a diagram showing a configuration example of a display control device provided in the source drivers 2A and 2B. The display control device shown in FIG. 5 includes an interface (IF) 101, a conversion unit 102, a vertical synchronization signal monitoring unit 103, a gradation generation unit 104, a video signal timing setting register 105, counters 106 and 107, an abnormality detection unit 108, and a source / gate control unit 109.

[0023] The interface (IF) 101 receives 4-channel Lvds video signals and an Lvds clock, and outputs 4-channel serial video signals and an Lvds clock to the conversion unit 102. The Lvds video signal is an example of the low voltage differential signal of the present disclosure.

[0024] The conversion unit 102 converts and outputs the 4-channel serial video signals and the Lvds clock output from the interface 101 into a vertical synchronization signal, a horizontal synchronization signal, a data enable (EN) signal, and an RGB data signal. That is, the conversion unit 102 is a serial / parallel conversion unit. The RGB data signal is an example of the image signal of the present disclosure.

[0025] The vertical synchronization signal monitoring unit 103 monitors the occurrence of abnormalities in the vertical synchronization signal output by the conversion unit 102. The vertical synchronization signal monitoring unit 103 uses the horizontal synchronization signal output by the conversion unit 102 to monitor the occurrence of abnormalities in the vertical synchronization signal. Specifically, after detecting the vertical synchronization signal, the vertical synchronization signal monitoring unit 103 ignores the vertical synchronization signal until a certain number of horizontal synchronization signals are detected. Detecting the vertical synchronization signal means detecting that the vertical synchronization signal has fallen after rising. Ignoring the vertical synchronization signal until a certain number of horizontal synchronization signals are detected means canceling the rise and fall of the vertical synchronization signal when there is a rise and fall of the vertical synchronization signal until a certain number of horizontal synchronization signals are detected.

[0026] The gradation generation unit 104 generates the gradation of the image to be displayed on the display panel 1 using the RGB data signal output by the conversion unit 102. The video signal timing setting register 105 is a register in which the reset timing for resetting the values counted by the counters 106 and 107 is set.

[0027] The counter 106 counts the vertical synchronization signal using the vertical synchronization signal and the internal clock (CLK). Counting the vertical synchronization signal means counting the set of rise and fall of the vertical synchronization signal. Then, if the value counted by the counter 106 at the reset timing from the video signal timing setting register 105 is different from the set value, the counter 106 outputs an abnormality detection signal to the abnormality detection unit 108. Also, the counter 106 counts the internal clock and outputs an abnormality detection signal to the abnormality detection unit 108 if there is no input during the reset timing from the video signal timing setting register 105.

[0028] The counter 107 counts the horizontal synchronization signal using the horizontal synchronization signal and the internal clock. Counting the horizontal synchronization signal means counting the set of rise and fall of the horizontal synchronization signal. Then, if the value counted by the counter 107 at the reset timing from the video signal timing setting register 105 is different from the set value, the counter 107 outputs an abnormality detection signal to the abnormality detection unit 108.

[0029] When the abnormality detection unit 108 receives an abnormality detection signal from the counters 106 and 107, it outputs a control instruction to the source / gate control unit 109 to maintain the previous display state on the display panel 1. When the abnormality detection signal continues from the counters 106 and 107 for a predetermined period, the abnormality detection unit 108 may output a control instruction to the source / gate control unit 109 to display the display panel 1 in an arbitrary state, for example, in black.

[0030] The source / gate control unit 109 controls each pixel of the display panel 1 using a vertical synchronization signal, a horizontal synchronization signal, and a data enable signal. When there is a control instruction from the abnormality detection unit 108, the source / gate control unit 109 controls each pixel to maintain the previous state and display on the display panel 1.

[0031] By having the configuration shown in FIG. 5, the display control device can normally perform video display on the display panel 1 even when noise due to disturbance is superimposed on the vertical synchronization signal. This is because after the vertical synchronization signal monitoring unit 103 detects the vertical synchronization signal, it ignores the vertical synchronization signal until a certain number of horizontal synchronization signals are detected.

[0032] The display control device having the configuration shown in FIG. 5 can normally perform video display on the display panel 1 even when noise due to disturbance is superimposed on the vertical synchronization signal. Next, a display control device having a configuration that can normally perform video display on the display panel 1 even when noise due to disturbance is superimposed on any of the vertical synchronization signal, horizontal synchronization signal, data enable (EN) signal, and RGB data signal will be described.

[0033] FIG. 6 is a diagram showing a configuration example of a display control device provided in source drivers 2A and 2B. The display control device shown in FIG. 5 includes an interface (IF) 101, a gradation generation unit 104, a source / gate control unit 109, a signal monitoring unit 110, and an abnormality detection unit 120.

[0034] The interface (IF) 101 receives 4-channel Lvds video signals and Lvds clocks, and outputs 4-channel serial video signals and Lvds clocks to the conversion unit 102.

[0035] The conversion unit 102 converts and outputs the 4-channel serial video signals and Lvds clocks output by the interface 101 into a vertical synchronization signal, a horizontal synchronization signal, a data enable (EN) signal, and an RGB data signal. That is, the conversion unit 102 is a serial-parallel conversion unit. The gradation generation unit 104 generates the gradation of the image to be displayed on the display panel 1 using the RGB data signal output by the conversion unit 102.

[0036] The signal monitoring unit 110 monitors the vertical synchronization signal, the horizontal synchronization signal, and the data enable (EN) signal output by the conversion unit 102. The signal monitoring unit 110 includes a vertical synchronization signal monitoring unit 111, a horizontal synchronization signal monitoring unit 112, and a data enable (EN) RGB data monitoring unit 113. The vertical synchronization signal monitoring unit 111 is an example of the first monitoring unit of the present disclosure. The horizontal synchronization signal monitoring unit 112 is an example of the second monitoring unit of the present disclosure. The data enable (EN) RGB data monitoring unit 113 is an example of the third monitoring unit of the present disclosure.

[0037] The vertical synchronization signal monitoring unit 111 monitors the occurrence of an abnormality in the vertical synchronization signal using the data enable (EN) signal and the RGB data signal. The horizontal synchronization signal monitoring unit 112 monitors the occurrence of an abnormality in the horizontal synchronization signal using the data enable (EN) signal and the RGB data signal. The data enable (EN) RGB data monitoring unit 113 monitors the occurrence of an abnormality in the data enable (EN) signal and the RGB data signal. When the signal monitoring unit 110 detects that an abnormality has occurred in the vertical synchronization signal, the horizontal synchronization signal, and the data enable (EN) signal, it outputs an abnormality detection signal to the abnormality detection unit 120. Specific configuration examples of the vertical synchronization signal monitoring unit 111, the horizontal synchronization signal monitoring unit 112, and the data enable (EN) RGB data monitoring unit 113 will be described later.

[0038] When the abnormality detection unit 120 receives an abnormality detection signal from the signal monitoring unit 110, it outputs a control instruction to the source / gate control unit 109 to cause the display panel 1 to display while maintaining the previous state. When the abnormality detection signal continues from the signal monitoring unit 110 for a predetermined period, the abnormality detection unit 120 may output a control instruction to the source / gate control unit 109 to display the display panel 1 in an arbitrary state, for example, in black.

[0039] The source / gate control unit 109 controls each pixel of the display panel 1 using a vertical synchronization signal, a horizontal synchronization signal, and a data enable signal. When there is a control instruction from the abnormality detection unit 120, the source / gate control unit 109 controls each pixel to maintain and display the previous display state on the display panel 1.

[0040] Subsequently, specific configuration examples of the vertical synchronization signal monitoring unit 111, the horizontal synchronization signal monitoring unit 112, and the data enable (EN) RGB data monitoring unit 113 included in the signal monitoring unit 110 will be described. FIG. 7 is a diagram showing an example of the specific logic circuit configuration of the vertical synchronization signal monitoring unit 111, the horizontal synchronization signal monitoring unit 112, and the data enable (EN) RGB data monitoring unit 113.

[0041] The vertical synchronization signal monitoring unit 111 includes a vertical synchronization signal detection unit 121, AND circuits 122, 123, and flip-flops (FF) 124, 125. The horizontal synchronization signal monitoring unit 112 includes a vertical synchronization signal detection unit 131, AND circuits 132, 133, and flip-flops 134, 135. The data enable (EN) RGB data monitoring unit 113 includes AND circuits 141, 146, 147, NOT circuits 142, 144, 145, 149, and OR circuits 143, 148.

[0042] (Vertical synchronization signal monitoring unit 111) The vertical synchronization signal detection unit 121 detects the rising edge, falling edge of the vertical synchronization signal output from the conversion unit 102, and the period from the rising edge to the next rising edge.

[0043] The AND circuit 122 outputs the logical product of the output of the vertical synchronization signal detection unit 121 and the output of the NOT circuit 149. That is, the AND circuit 122 outputs a high state when both the output of the vertical synchronization signal detection unit 121 and the output of the NOT circuit 149 are in the high state, and outputs a low state when at least one of the output of the vertical synchronization signal detection unit 121 and the output of the NOT circuit 149 is in the low state.

[0044] The AND circuit 123 outputs the logical product of the output of the vertical synchronization signal detection unit 121 and the output of the AND circuit 148. That is, the AND circuit 122 outputs a high state signal when both the output of the vertical synchronization signal detection unit 121 and the output of the AND circuit 148 are in the high state, and outputs a low state signal when at least one of the output of the vertical synchronization signal detection unit 121 and the output of the AND circuit 148 is in the low state.

[0045] The flip - flop 124 receives the output signal from the AND circuit 122 and outputs a signal based on the Lvds clock output from the conversion unit 102. The signal output from the flip - flop 124 becomes the vertical synchronization signal.

[0046] The flip - flop 125 receives the output signal from the AND circuit 123 and outputs a signal based on the Lvds clock output from the conversion unit 102. The signal output from the flip - flop 125 becomes the abnormality detection signal. The abnormality detection signal indicates that an abnormality has been detected when in the high state and indicates that there is no abnormality when in the low state. During the period from the rise to the fall of the vertical synchronization signal, the data enable signal and the RGB data signal are always in the low state. That is, the vertical synchronization signal monitoring unit 111 can ignore the high - state signal if there is even 1 bit in the high state in the data enable signal and the RGB data signal during the period from the rise to the fall of the vertical synchronization signal, and can detect that there is an abnormality in the vertical synchronization signal.

[0047] (Horizontal synchronization signal monitoring unit 112) The horizontal synchronization signal detection unit 131 detects the rising edge and falling edge of the horizontal synchronization signal output from the conversion unit 102, and also detects the period from one rising edge to the next rising edge.

[0048] The AND circuit 132 outputs the logical product of the output of the horizontal synchronization signal detection unit 131 and the output of the NOT circuit 149. That is, the AND circuit 132 outputs a high state when both the output of the horizontal synchronization signal detection unit 131 and the output of the NOT circuit 149 are in the high state, and outputs a low state when at least one of the output of the horizontal synchronization signal detection unit 131 and the output of the NOT circuit 149 is in the low state.

[0049] The AND circuit 133 outputs the logical product of the output of the horizontal synchronization signal detection unit 131 and the output of the AND circuit 148. That is, the AND circuit 132 outputs a high state signal when both the output of the horizontal synchronization signal detection unit 131 and the output of the AND circuit 148 are in the high state, and outputs a low state signal when at least one of the output of the horizontal synchronization signal detection unit 131 and the output of the AND circuit 148 is in the low state.

[0050] The flip-flop 134 receives the output signal from the AND circuit 132 and outputs a signal based on the Lvds clock output from the conversion unit 102. The signal output from the flip-flop 134 becomes the horizontal synchronization signal.

[0051] The flip-flop 135 receives the output signal from the AND circuit 133 and outputs a signal based on the Lvds clock output from the conversion unit 102. The signal output from the flip-flop 135 becomes the abnormality detection signal. During the period from the rising edge to the falling edge of the horizontal synchronization signal, the data enable signal and the RGB data signal are always in the low state. That is, the horizontal synchronization signal monitoring unit 112 can detect an abnormality in the horizontal synchronization signal if there is even one bit in the high state in the data enable signal and the RGB data signal during the period from the rising edge to the next rising edge of the horizontal synchronization signal, and ignores the high state signal.

[0052] (Data Enable (EN) RGB Data Monitoring Unit 113) The AND circuit 141 outputs a signal that is the logical product of the Data Enable (EN) signal and the RGB data signal. The NOT circuit 142 outputs a signal obtained by inverting the RGB data signal. The OR circuit 143 outputs a signal that is the logical sum of the output of the AND circuit 141 and the output of the NOT circuit 142. The NOT circuit 144 outputs a signal obtained by inverting the output of the OR circuit 143. The output of the NOT circuit 144 becomes an abnormality detection signal. That is, when the RGB data signal is in the high state even by 1 bit when the Data Enable (EN) signal is in the low state, the Data Enable (EN) RGB data monitoring unit 113 detects an abnormality.

[0053] The NOT circuit 145 outputs a signal obtained by inverting the outputs of the flip-flops 125 and 135, that is, the abnormality detection signal. That is, the NOT circuit 145 outputs a low-state signal when an abnormality has occurred in at least one of the vertical synchronization signal and the horizontal synchronization signal, and outputs a high-state signal when no abnormality has occurred in the vertical synchronization signal and the horizontal synchronization signal.

[0054] The AND circuit 146 takes the logical product of the Data Enable (EN) signal and the NOT circuit 145 and outputs it as the Data Enable (EN) signal. That is, the AND circuit 146 outputs the Data Enable (EN) signal itself when no abnormality has occurred in the vertical synchronization signal and the horizontal synchronization signal, and outputs a low-state signal when an abnormality has occurred in at least one of the vertical synchronization signal and the horizontal synchronization signal. Therefore, when an abnormality has occurred in at least one of the vertical synchronization signal and the horizontal synchronization signal, the Data Enable (EN) signal becomes a low state. That is, the Data Enable (EN) RGB data monitoring unit 113 ignores the Data Enable (EN) signal when an abnormality has occurred in at least one of the vertical synchronization signal and the horizontal synchronization signal.

[0055] The AND circuit 147 takes the logical product of the RGB data signal and the NOT circuit 145 and outputs it as the RGB data signal. That is, when there is no abnormality in the vertical synchronization signal and the horizontal synchronization signal, the AND circuit 147 outputs the RGB data signal itself, and when there is an abnormality in at least one of the vertical synchronization signal or the horizontal synchronization signal, it outputs a signal in the low state. Therefore, when there is an abnormality in at least one of the vertical synchronization signal or the horizontal synchronization signal, the RGB data signal becomes the low state. That is, when there is an abnormality in at least one of the vertical synchronization signal or the horizontal synchronization signal, the data enable (EN) RGB data monitoring unit 113 ignores the RGB data signal.

[0056] The OR circuit 148 outputs a signal that is the logical sum of the data enable (EN) signal and the RGB data signal. The output signal of the OR circuit 148 is used for detecting abnormalities in the vertical synchronization signal and the horizontal synchronization signal. The NOT circuit 149 outputs a signal obtained by inverting the output signal of the OR circuit 148. The output signal of the NOT circuit 149 is used for outputting the vertical synchronization signal and the horizontal synchronization signal.

[0057] The effect of providing the signal monitoring unit 110 will be described. FIGS. 8A and 8B are timing charts for explaining the effect of the signal monitoring unit 110.

[0058] FIG. 8A is a timing chart showing a state in which noise due to disturbance is superimposed on each of the vertical synchronization signal, the horizontal synchronization signal, the data enable (EN) signal, and the RGB data signal.

[0059] For example, when noise due to disturbance is superimposed on the vertical synchronization signal at the timing of (1) in FIG. 8A, the video displayed on the display panel 1 is disturbed as described above. However, by providing the signal monitoring unit 110, since the data enable (EN) signal and the RGB data signal are in the high state at the timing of (1), the signal monitoring unit 110 can detect that an abnormality has occurred in the vertical synchronization signal. Then, as shown in FIG. 8B, the noise due to disturbance is ignored at the timing of (1), and the vertical synchronization signal is output in a normal state.

[0060] Also, for example, when noise due to disturbance is superimposed on the horizontal synchronization signal at the timing of (2) in FIG. 8A, the video displayed on the display panel 1 is disturbed as described above. However, by providing the signal monitoring unit 110, since the data enable (EN) signal and the RGB data signal are in the high state at the timing of (2), the signal monitoring unit 110 can detect that an abnormality has occurred in the horizontal synchronization signal. Then, as shown in FIG. 8B, the noise due to disturbance is ignored at the timing of (2), and the horizontal synchronization signal is output in a normal state.

[0061] Also, for example, when noise due to disturbance is superimposed on the data enable (EN) signal at the timing of (3) in FIG. 8A, since the data enable (EN) signal is simultaneously in the high state as seen from the horizontal synchronization signal, the video displayed on the display panel 1 is disturbed. However, by providing the signal monitoring unit 110, since the signal monitoring unit 110 can see that the data enable (EN) signal is simultaneously in the high state as seen from the horizontal synchronization signal, the signal monitoring unit 110 can detect that an abnormality has occurred in the data enable (EN) signal. Then, as shown in FIG. 8B, the noise due to disturbance is ignored at the timing of (3), and the data enable (EN) signal is output in a normal state.

[0062] Also, for example, when noise due to disturbance is superimposed on the G (green) data signal of the RGB data signal at the timing of (4) in FIG. 8A, since the G data signal includes a high state as seen from the horizontal synchronization signal, the video displayed on the display panel 1 is disturbed. However, by providing the signal monitoring unit 110, since the signal monitoring unit 110 can see that the G data signal includes a high state as seen from the horizontal synchronization signal, the signal monitoring unit 110 can detect that an abnormality has occurred in the RGB data signal. Then, as shown in FIG. 8B, the noise due to disturbance is ignored at the timing of (4), and the G (green) data signal of the RGB data signal is output in a normal state.

[0063] As described above, according to the embodiment of the present disclosure, there is provided a display control device capable of normally performing video display on the display panel 1 even when superimposed on any of a vertical synchronization signal, a horizontal synchronization signal, a data enable (EN) signal, and an RGB data signal.

[0064] In addition, the following supplementary notes are disclosed regarding the above description.

[0065] Supplementary Note 1: A display control device for controlling a drive circuit for a display panel, a first monitoring unit that monitors the occurrence of an abnormality in a vertical synchronization signal using a data enable signal and an image signal, and outputs a first abnormality detection signal when an abnormality in the vertical synchronization signal is detected; a second monitoring unit that monitors the occurrence of an abnormality in a horizontal synchronization signal using the data enable signal and the image signal, and outputs a second abnormality detection signal when an abnormality in the horizontal synchronization signal is detected; a third monitoring unit that monitors the occurrence of an abnormality in the image signal using the data enable signal, outputs a third abnormality detection signal when an abnormality in the image signal is detected, and does not output the data enable signal and the image signal when the first abnormality detection signal or the second abnormality detection signal is output; A display control device comprising the above. Supplementary Note 2: The display control device according to Supplementary Note 1, wherein the first monitoring unit outputs a first abnormality detection signal when the data enable signal and the image signal are in a high state during a period from the rise to the fall of the vertical synchronization signal. Supplementary Note 3: The display control device according to Supplementary Note 1 or 2, wherein the second monitoring unit outputs a second abnormality detection signal when the data enable signal and the image signal are in a high state during a period from the rise to the fall of the horizontal synchronization signal. Supplementary Note 4: The display control device according to any one of Appendices 1 to 3, further comprising an abnormality detection unit that causes the drive circuit to maintain the immediately previous display state on the display panel when at least any one of the first abnormality detection signal, the second abnormality detection signal, or the third abnormality detection signal is output. Appendix 5: The display control device according to any one of Appendices 1 to 4, further comprising a conversion unit that converts a serial video signal into the vertical synchronization signal, the horizontal synchronization signal, the data enable signal, and the image signal. Appendix 6: The display control device according to Appendix 5, wherein the serial video signal is a low voltage differential signal. Appendix 7: A display control device that controls a drive circuit for a display panel, a vertical synchronization signal monitoring unit that ignores the rise and fall of the vertical synchronization signal until a predetermined number of rises and falls of the horizontal synchronization signal are detected after detecting the rise and fall of the vertical synchronization signal; an abnormality detection unit that counts the rise and fall of the vertical synchronization signal from the fall to the rise of the horizontal synchronization signal and outputs an abnormality detection signal when the counted value is different from a set value; A display control device comprising:

Explanation of Signs

[0066] 1 Display panel 2A, 2B Source driver 3 Gate driver 101 Interface (IF) 102 Conversion unit 103 Vertical synchronization signal monitoring unit 104 Gradation generation unit 105 Video signal timing setting register 106, 107 Counter 108 Abnormality detection unit 109 Source / gate control unit 110 Signal monitoring unit 111 Vertical synchronization signal monitoring unit 112 Horizontal synchronization signal monitoring unit 113 Data Enable (EN) RGB Data Monitoring Unit 120 Abnormality Detection Unit

Claims

1. A display control device for controlling a drive circuit for a display panel, comprising: a first monitoring unit that monitors the occurrence of an abnormality in a vertical synchronization signal using a data enable signal and an image signal, and outputs a first abnormality detection signal when an abnormality in the vertical synchronization signal is detected; a second monitoring unit that monitors the occurrence of an abnormality in a horizontal synchronization signal using the data enable signal and the image signal, and outputs a second abnormality detection signal when an abnormality in the horizontal synchronization signal is detected; a third monitoring unit that monitors the occurrence of an abnormality in the image signal using the data enable signal, outputs a third abnormality detection signal when an abnormality in the image signal is detected, and does not output the data enable signal and the image signal when the first abnormality detection signal or the second abnormality detection signal is being output; A display control device comprising the above.

2. The display control device according to claim 1, wherein the first monitoring unit outputs a first abnormality detection signal when the data enable signal and the image signal are in a high state during a period from the rising edge to the falling edge of the vertical synchronization signal.

3. The display control device according to claim 1 or claim 2, wherein the second monitoring unit outputs a second abnormality detection signal when the data enable signal and the image signal are in a high state during a period from the rising edge to the falling edge of the horizontal synchronization signal.

4. The display control device according to claim 1, further comprising an abnormality detection unit that causes the drive circuit to maintain the previous display state on the display panel when at least any one of the first abnormality detection signal, the second abnormality detection signal, or the third abnormality detection signal is being output.

5. The display control device according to claim 1, further comprising a conversion unit that converts a serial video signal into the vertical synchronization signal, the horizontal synchronization signal, the data enable signal, and the image signal.

6. The display control device according to claim 5, wherein the serial video signal is a low voltage differential signal.

7. A display control device for controlling a drive circuit for a display panel, comprising: a vertical synchronization signal monitoring unit that ignores the rising and falling edges of the vertical synchronization signal until a predetermined number of rising and falling edges of the horizontal synchronization signal are detected after detecting the rising and falling edges of the vertical synchronization signal; An abnormality detection unit that counts the rising and falling edges of the vertical synchronization signal from the falling edge to the rising edge of the horizontal synchronization signal and outputs an abnormality detection signal when the counted value is different from a set value; A display control device comprising the same.

Images